A method for testing a functional unit within an arithmetic logic unit, the functional unit having a predetermined structural implementation defined at RTL, gate-level or lower level, the functional unit configured to generate a result based on at least one data input, the method comprising: analyzing the predetermined structural implementation of the functional unit to identify a first plurality of test vectors that test the functional unit. generating the first plurality of test vectors, each test vector comprising a test value for a data input to the functional unit and an expected result value therefrom; and for each one of the first plurality of test vectors: providing the test value to the functional unit; and verifying that the expected result value is generated by the functional unit responsive to providing the test value wherein: the analyzing the predetermined structural implementation of the functional unit to identify a first plurality of test vectors comprises identifying targeted test vectors that test each of one or more components of the functional unit, the targeted test vectors defining the first plurality of test vectors; the ALU comprises a first register for storing a first operand, a second register for storing a second operand, and a third register for storing a sum of the first operand and the second operand; the functional unit is an adder coupled to the first, second, and third registers, and configured to generate a sum of the first operand and the second operand, the sum being stored in the third register; the first plurality of test vectors comprises a plurality of adder test vectors, each adder test vector comprising a first test value, a second test value, and an expected sum; providing the test value to the functional unit comprises providing the first test value and the second test value to the first register and the second register, respectively; and verifying comprises verifying that the expected sum is stored in the third register responsive to providing the test value. analyzing the predetermined structural implementation of the functional unit to identify a first plurality of test vectors that test the functional unit. generating the first plurality of test vectors, each test vector comprising a test value for a data input to the functional unit and an expected result value therefrom; and for each one of the first plurality of test vectors: providing the test value to the functional unit; and verifying that the expected result value is generated by the functional unit responsive to providing the test value providing the test value to the functional unit; and verifying that the expected result value is generated by the functional unit responsive to providing the test value wherein: the analyzing the predetermined structural implementation of the functional unit to identify a first plurality of test vectors comprises identifying targeted test vectors that test each of one or more components of the functional unit, the targeted test vectors defining the first plurality of test vectors; the ALU comprises a first register for storing a first operand, a second register for storing a second operand, and a third register for storing a sum of the first operand and the second operand; the functional unit is an adder coupled to the first, second, and third registers, and configured to generate a sum of the first operand and the second operand, the sum being stored in the third register; the first plurality of test vectors comprises a plurality of adder test vectors, each adder test vector comprising a first test value, a second test value, and an expected sum; providing the test value to the functional unit comprises providing the first test value and the second test value to the first register and the second register, respectively; and verifying comprises verifying that the expected sum is stored in the third register responsive to providing the test value. the analyzing the predetermined structural implementation of the functional unit to identify a first plurality of test vectors comprises identifying targeted test vectors that test each of one or more components of the functional unit, the targeted test vectors defining the first plurality of test vectors; the ALU comprises a first register for storing a first operand, a second register for storing a second operand, and a third register for storing a sum of the first operand and the second operand; the functional unit is an adder coupled to the first, second, and third registers, and configured to generate a sum of the first operand and the second operand, the sum being stored in the third register; the first plurality of test vectors comprises a plurality of adder test vectors, each adder test vector comprising a first test value, a second test value, and an expected sum; providing the test value to the functional unit comprises providing the first test value and the second test value to the first register and the second register, respectively; and verifying comprises verifying that the expected sum is stored in the third register responsive to providing the test value.