A three-dimensional, 3D, memory device (200, 300), comprising: a substrate (202, 302); a memory stack (204, 304) comprising: a first high-κ dielectric layer (232, 332) above the substrate (202, 302), and a plurality of interleaved conductor layers (206, 306) and dielectric layers (208, 308) above the first high-κ dielectric layer (232, 332); and a semiconductor plug (216, 316) disposed above the substrate (202, 302) and in an opening of the first high-κ dielectric layer (232, 332), further comprising a first channel structure (212, 312) extending vertically above the semiconductor plug (216, 316) and through the memory stack (204, 304), the first channel structure (212, 312) comprising: a first memory film (226, 326) above the first high-x dielectric layer (232, 332) and along a sidewall of the first channel structure (212, 312), said first memory film being in contact with the semiconductor plug (216, 316), further comprising: a second channel structure (214, 314) extending vertically above the first channel structure (212, 312) and through the memory stack (204, 304), a second high-κ dielectric layer (234, 334) disposed between the first channel structure (212, 312) and the second channel structure (214, 314); and an inter-deck plug (210, 310) disposed in an opening of the second high-κ dielectric layer (234, 334), said 3D memory device (200, 300) further comprising a second memory film above the second high-κ dielectric layer (234, 334) and along a sidewall of the second channel structure (214, 314), said second memory film being in contact with the inter-deck plug (210, 310). a substrate (202, 302); a memory stack (204, 304) comprising: a first high-κ dielectric layer (232, 332) above the substrate (202, 302), and a plurality of interleaved conductor layers (206, 306) and dielectric layers (208, 308) above the first high-κ dielectric layer (232, 332); and a first high-κ dielectric layer (232, 332) above the substrate (202, 302), and a plurality of interleaved conductor layers (206, 306) and dielectric layers (208, 308) above the first high-κ dielectric layer (232, 332); and a semiconductor plug (216, 316) disposed above the substrate (202, 302) and in an opening of the first high-κ dielectric layer (232, 332), further comprising a first channel structure (212, 312) extending vertically above the semiconductor plug (216, 316) and through the memory stack (204, 304), the first channel structure (212, 312) comprising: a first memory film (226, 326) above the first high-x dielectric layer (232, 332) and along a sidewall of the first channel structure (212, 312), said first memory film being in contact with the semiconductor plug (216, 316), further comprising: a second channel structure (214, 314) extending vertically above the first channel structure (212, 312) and through the memory stack (204, 304), a second high-κ dielectric layer (234, 334) disposed between the first channel structure (212, 312) and the second channel structure (214, 314); and an inter-deck plug (210, 310) disposed in an opening of the second high-κ dielectric layer (234, 334), said 3D memory device (200, 300) further comprising a second memory film above the second high-κ dielectric layer (234, 334) and along a sidewall of the second channel structure (214, 314), said second memory film being in contact with the inter-deck plug (210, 310). a first memory film (226, 326) above the first high-x dielectric layer (232, 332) and along a sidewall of the first channel structure (212, 312), said first memory film being in contact with the semiconductor plug (216, 316), further comprising: a second channel structure (214, 314) extending vertically above the first channel structure (212, 312) and through the memory stack (204, 304), a second high-κ dielectric layer (234, 334) disposed between the first channel structure (212, 312) and the second channel structure (214, 314); and an inter-deck plug (210, 310) disposed in an opening of the second high-κ dielectric layer (234, 334), said 3D memory device (200, 300) further comprising a second memory film above the second high-κ dielectric layer (234, 334) and along a sidewall of the second channel structure (214, 314), said second memory film being in contact with the inter-deck plug (210, 310). a second channel structure (214, 314) extending vertically above the first channel structure (212, 312) and through the memory stack (204, 304), a second high-κ dielectric layer (234, 334) disposed between the first channel structure (212, 312) and the second channel structure (214, 314); and an inter-deck plug (210, 310) disposed in an opening of the second high-κ dielectric layer (234, 334), said 3D memory device (200, 300) further comprising a second memory film above the second high-κ dielectric layer (234, 334) and along a sidewall of the second channel structure (214, 314), said second memory film being in contact with the inter-deck plug (210, 310).