A semiconductor memory device comprising: a first memory string including a first memory cell and a first selection transistor coupled to the first memory cell; a second memory string including a second memory cell and a second selection transistor coupled to the second memory cell; a third memory string including a third memory cell and a third selection transistor coupled to the third memory cell; a word line coupled to gates of the first memory cell, the second memory cell, and the third memory cell; a first selection gate line (SGDO) coupled to a gate of the first selection transistor and the third selection transistor; a second selection gate line coupled to a gate of the second selection transistor; a first bit line coupled to the first and second selection transistors; a second bit line coupled to the third selection transistor; a row decoder coupled to the word line, the first selection gate line, and the second selection gate line; a sense amplifier coupled to the first bit line and the second bit line, and including a latch circuit capable of holding write data; a data register coupled to the sense amplifier to transmit and receive data to and from the sense amplifier; and a control circuit configured for suspending a write operation of the first memory cell and the third memory cell to perform a read operation of the first memory cell and the third memory cell when receiving a read instruction of the first memory cell and the third memory cell during the write operation of the first memory cell and the third memory cell, wherein in the read operation of the first memory cell and the third memory cell performed while suspending the write operation of the first memory cell and the third memory cell, the row decoder is configured to apply a read voltage to the word line, and the sense amplifier transmits data read from the first memory cell to the data register as read data, and transmits the write data of the third memory cell held by the latch circuit to the data register as the read data when the writing of the write data to the first memory cell is completed and the writing of the write data to the third memory cell is not completed. a first memory string including a first memory cell and a first selection transistor coupled to the first memory cell; a second memory string including a second memory cell and a second selection transistor coupled to the second memory cell; a third memory string including a third memory cell and a third selection transistor coupled to the third memory cell; a word line coupled to gates of the first memory cell, the second memory cell, and the third memory cell; a first selection gate line (SGDO) coupled to a gate of the first selection transistor and the third selection transistor; a second selection gate line coupled to a gate of the second selection transistor; a first bit line coupled to the first and second selection transistors; a second bit line coupled to the third selection transistor; a row decoder coupled to the word line, the first selection gate line, and the second selection gate line; a sense amplifier coupled to the first bit line and the second bit line, and including a latch circuit capable of holding write data; a data register coupled to the sense amplifier to transmit and receive data to and from the sense amplifier; and a control circuit configured for suspending a write operation of the first memory cell and the third memory cell to perform a read operation of the first memory cell and the third memory cell when receiving a read instruction of the first memory cell and the third memory cell during the write operation of the first memory cell and the third memory cell, wherein in the read operation of the first memory cell and the third memory cell performed while suspending the write operation of the first memory cell and the third memory cell, the row decoder is configured to apply a read voltage to the word line, and the sense amplifier transmits data read from the first memory cell to the data register as read data, and transmits the write data of the third memory cell held by the latch circuit to the data register as the read data when the writing of the write data to the first memory cell is completed and the writing of the write data to the third memory cell is not completed.