An apparatus comprising: a user input subsystem configured to receive an input from a user; a security component, the security component having a first security processor device configured to: receive an input signal from the user via the user input subsystem; determine a security condition based on the input signal received from the user input subsystem; and transmit, in response to determining the security condition, a security condition signal; and a System on Chip, SoC, component separate from the security component, the SoC component having: multiple apparatus subsystem core devices configured to: communicate with corresponding apparatus subsystems to operate the corresponding apparatus subsystems; and a second security processor device configured to: receive, from the first security processor device, the security condition signal; and according to a security policy communicate, in response to receiving the security condition signal and autonomously from the first security processor device via a secure control and communication bus that is internal to the SoC component, to at least one of the multiple apparatus subsystem core devices, to signal the at least one subsystem core device to perform a security operation that disables a corresponding subsystem. a user input subsystem configured to receive an input from a user; a security component, the security component having a first security processor device configured to: receive an input signal from the user via the user input subsystem; determine a security condition based on the input signal received from the user input subsystem; and transmit, in response to determining the security condition, a security condition signal; and receive an input signal from the user via the user input subsystem; determine a security condition based on the input signal received from the user input subsystem; and transmit, in response to determining the security condition, a security condition signal; and a System on Chip, SoC, component separate from the security component, the SoC component having: multiple apparatus subsystem core devices configured to: communicate with corresponding apparatus subsystems to operate the corresponding apparatus subsystems; and a second security processor device configured to: receive, from the first security processor device, the security condition signal; and according to a security policy communicate, in response to receiving the security condition signal and autonomously from the first security processor device via a secure control and communication bus that is internal to the SoC component, to at least one of the multiple apparatus subsystem core devices, to signal the at least one subsystem core device to perform a security operation that disables a corresponding subsystem. multiple apparatus subsystem core devices configured to: communicate with corresponding apparatus subsystems to operate the corresponding apparatus subsystems; and a second security processor device configured to: receive, from the first security processor device, the security condition signal; and according to a security policy communicate, in response to receiving the security condition signal and autonomously from the first security processor device via a secure control and communication bus that is internal to the SoC component, to at least one of the multiple apparatus subsystem core devices, to signal the at least one subsystem core device to perform a security operation that disables a corresponding subsystem. receive, from the first security processor device, the security condition signal; and according to a security policy communicate, in response to receiving the security condition signal and autonomously from the first security processor device via a secure control and communication bus that is internal to the SoC component, to at least one of the multiple apparatus subsystem core devices, to signal the at least one subsystem core device to perform a security operation that disables a corresponding subsystem.