A method for operating an active input element of an input arrangement comprising a number (N IE) of active input elements, wherein the active input element comprises a clock counter, a shift register, and a data processing unit, and wherein the method is carried out by the data processing unit and comprises the steps: a) set value C of clock counter to 0; b) increase value C of clock counter by 1 and shift data in the shift register by one Bit, when detecting a clock information; c) compare value C of the clock counter with a cycle length CLL, and return to step b) if comparison result is negative or proceed to step d) if comparison result is positive; wherein the cycle length CLL is stored beforehand in each active input element or wherein the cycle length CLL is calculated in each active input element based on the number (N IE) of active input elements stored beforehand and a word length of the shift register stored beforehand, wherein in the second alternative, the word length is the same for all input elements, d) read data (D FIFO) from the shift register; e) compare said read data (D FIFO) from the shift register with predetermined first data value, and proceed to step f) if comparison result is positive or proceed to step a) if comparison result is negative; f) write data (D IE) derived from analog input device into shift register and return to step a). wherein the active input element comprises a clock counter, a shift register, and a data processing unit, and wherein the method is carried out by the data processing unit and comprises the steps: a) set value C of clock counter to 0; b) increase value C of clock counter by 1 and shift data in the shift register by one Bit, when detecting a clock information; c) compare value C of the clock counter with a cycle length CLL, and return to step b) if comparison result is negative or proceed to step d) if comparison result is positive; wherein the cycle length CLL is stored beforehand in each active input element or wherein the cycle length CLL is calculated in each active input element based on the number (N IE) of active input elements stored beforehand and a word length of the shift register stored beforehand, wherein in the second alternative, the word length is the same for all input elements, d) read data (D FIFO) from the shift register; e) compare said read data (D FIFO) from the shift register with predetermined first data value, and proceed to step f) if comparison result is positive or proceed to step a) if comparison result is negative; f) write data (D IE) derived from analog input device into shift register and return to step a). a) set value C of clock counter to 0; b) increase value C of clock counter by 1 and shift data in the shift register by one Bit, when detecting a clock information; c) compare value C of the clock counter with a cycle length CLL, and return to step b) if comparison result is negative or proceed to step d) if comparison result is positive; wherein the cycle length CLL is stored beforehand in each active input element or wherein the cycle length CLL is calculated in each active input element based on the number (N IE) of active input elements stored beforehand and a word length of the shift register stored beforehand, wherein in the second alternative, the word length is the same for all input elements, return to step b) if comparison result is negative or proceed to step d) if comparison result is positive; wherein the cycle length CLL is stored beforehand in each active input element or wherein the cycle length CLL is calculated in each active input element based on the number (N IE) of active input elements stored beforehand and a word length of the shift register stored beforehand, wherein in the second alternative, the word length is the same for all input elements, d) read data (D FIFO) from the shift register; e) compare said read data (D FIFO) from the shift register with predetermined first data value, and proceed to step f) if comparison result is positive or proceed to step a) if comparison result is negative; proceed to step f) if comparison result is positive or proceed to step a) if comparison result is negative; f) write data (D IE) derived from analog input device into shift register and return to step a).