A display device comprising: a display area that includes a plurality of pixels and a plurality of data lines connected to the pixels; a hole area disposed within the display area; a hole crack detection line disposed adjacent to the hole area, the hole crack detection line surrounding the hole area and having a first end and a second end that are separated from each other; a first detection line that includes a first detection transfer line connected to the first end of the hole crack detection line and a first detection receiving line connected to the second end of the hole crack detection line; a second detection line that includes a second detection transfer line connected to the first end of the hole crack detection line and a second detection receiving line connected to the second end of the hole crack detection line; a test controller configured to electrically connect the first detection receiving line to a first data line (DL(k-1)) of the plurality of data lines and the second detection receiving line to a second data line (DL(k+1)) of the plurality of the data lines; a test voltage line that includes a first end connected to the first detection transfer line and a second end connected to the second detection transfer line; and a first test pad, a second test pad and a third test pad; wherein the test controller includes a plurality of test transistors (T1 to Tm) connected to the data lines; first electrodes of the test transistors (T1 to Tm) are connected to the respective data lines; and the test transistors (T1 to Tm) further include second electrodes; wherein a second electrode of a first bright-line transistor (T(k-1)) of the plurality of test transistors (T1 to Tm) is connected with the first detection receiving line, and a second electrode of a second bright-line transistor (T(k+1)) of the plurality of test transistors (T1 to Tm) is connected with the second detection receiving line; wherein each of the second electrodes of the test transistors (T1 to Tm) are connected with the test voltage line except for the second electrode of the first bright-line transistor (T(k-1)) and the second electrode of the second bright-line transistor (T(K+1)) and wherein the first detection transfer line is connected to the first test pad for receiving a first test voltage (P1); and the second detection transfer line is connected to the second test pad for receiving a second test voltage (P2); where the display device further comprises a detection control line configured to have a first end connected to the third test pad and a second end connected to a gate electrode of each of the plurality of test transistors (T1 to Tm). a display area that includes a plurality of pixels and a plurality of data lines connected to the pixels; a hole area disposed within the display area; a hole crack detection line disposed adjacent to the hole area, the hole crack detection line surrounding the hole area and having a first end and a second end that are separated from each other; a first detection line that includes a first detection transfer line connected to the first end of the hole crack detection line and a first detection receiving line connected to the second end of the hole crack detection line; a second detection line that includes a second detection transfer line connected to the first end of the hole crack detection line and a second detection receiving line connected to the second end of the hole crack detection line; a test controller configured to electrically connect the first detection receiving line to a first data line (DL(k-1)) of the plurality of data lines and the second detection receiving line to a second data line (DL(k+1)) of the plurality of the data lines; a test voltage line that includes a first end connected to the first detection transfer line and a second end connected to the second detection transfer line; and a first test pad, a second test pad and a third test pad; wherein the test controller includes a plurality of test transistors (T1 to Tm) connected to the data lines; first electrodes of the test transistors (T1 to Tm) are connected to the respective data lines; and the test transistors (T1 to Tm) further include second electrodes; wherein a second electrode of a first bright-line transistor (T(k-1)) of the plurality of test transistors (T1 to Tm) is connected with the first detection receiving line, and a second electrode of a second bright-line transistor (T(k+1)) of the plurality of test transistors (T1 to Tm) is connected with the second detection receiving line; wherein each of the second electrodes of the test transistors (T1 to Tm) are connected with the test voltage line except for the second electrode of the first bright-line transistor (T(k-1)) and the second electrode of the second bright-line transistor (T(K+1)) and wherein the first detection transfer line is connected to the first test pad for receiving a first test voltage (P1); and the second detection transfer line is connected to the second test pad for receiving a second test voltage (P2);