An arc fault circuit interrupter comprising: separable contacts; a neutral conductor; an operating mechanism structured to open and close said separable contacts; a current sensor structured to sense current flowing through said separable contacts and output a sensed current value; and a processor cooperating with said current sensor to determine and store a plurality of peak values of the sensed current value for a plurality of half-cycles of said current flowing through said separable contacts, wherein said processor is structured to provide arc fault detection and to determine both of: (a) whether a first predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor, and to responsively inhibit said arc fault detection for a first predetermined time, and (b) whether a second predetermined plurality of said half-cycles of said current occur in succession and each of said second predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity, and to responsively inhibit said arc fault detection for a second predetermined time, and wherein said processor is further structured to determine that said arc fault detection is not inhibited for both of said first predetermined time and said second predetermined time, and to responsively indicate that at least one of said half-cycles of said current having a peak amplitude greater than or equal to a predetermined amount is a parallel arc. separable contacts; a neutral conductor; an operating mechanism structured to open and close said separable contacts; a current sensor structured to sense current flowing through said separable contacts and output a sensed current value; and a processor cooperating with said current sensor to determine and store a plurality of peak values of the sensed current value for a plurality of half-cycles of said current flowing through said separable contacts, wherein said processor is structured to provide arc fault detection and to determine both of: (a) whether a first predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor, and to responsively inhibit said arc fault detection for a first predetermined time, and (b) whether a second predetermined plurality of said half-cycles of said current occur in succession and each of said second predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity, and to responsively inhibit said arc fault detection for a second predetermined time, and wherein said processor is further structured to determine that said arc fault detection is not inhibited for both of said first predetermined time and said second predetermined time, and to responsively indicate that at least one of said half-cycles of said current having a peak amplitude greater than or equal to a predetermined amount is a parallel arc. (a) whether a first predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor, and to responsively inhibit said arc fault detection for a first predetermined time, and (b) whether a second predetermined plurality of said half-cycles of said current occur in succession and each of said second predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity, and to responsively inhibit said arc fault detection for a second predetermined time, and