A transistor device including a memory cell, the memory cell comprising: a gate stack with sidewalls provided over a supporting substrate (181A, 1080A, 1080D), the gate stack including: a metal gate layer (171A, 1070A, 1070D) provided over the supporting substrate (181A, 1080A 1080D); a buffer layer (161A, 1060A, 1060D) provided over the metal gate layer (181A, 1070A, 1070D); a ferroelectric layer (151A, 1050A, 1050D) provided over the buffer layer (161A, 1060A, 1060D); and a dielectric layer (141A, 1040A, 1040D) provided on a top surface of the ferroelectric layer (151A, 1050A, 1050D), wherein a ratio of thickness of the dielectric layer (141A, 1040A, 1040D) to the ferroelectric layer (151A, 1050A, 1050D) does not exceed 2; a two-dimensional, 2D, material layer (121A, 1020A, 1020D) provided over a portion of a top surface of the dielectric layer (141A, 1040A, 1040D); and source and drain regions (111A, 1010A, 1010D, 131A, 1030A, 1030D) provided on separate portions of the top surface of the dielectric layer (1040A, 1040D) so as to create a cavity wherein the 2D material layer (121A, 1020A, 1020D) is positioned in the cavity; wherein the ferroelectric layer (151A, 1050A, 1050D) is a layer of inorganic ferroelectric films of zirconium-doped hafnium oxide HfZrOx; wherein the dielectric layer (141A, 1040A, 1040D) is a layer of dielectric hafnium oxide, HfO 2; wherein the 2D material layer (121A, 1020A, 1020D) includes a MoS 2 flake; wherein the buffer layer (161A, 1060A, 1060D) is a layer of titanium nitride, TiN; wherein a poling voltage of the transistor device is smaller than 3V; wherein a bottom surface of the dielectric layer (141A, 1040A, 1040D) is in direct contact with the top surface of the ferroelectric layer (151A, 1050A, 1050D); and wherein the metal gate layer (171A, 1070A, 1070D) is a titanium, Ti,/gold, Au, layer acting as a gate electrode. a gate stack with sidewalls provided over a supporting substrate (181A, 1080A, 1080D), the gate stack including: a metal gate layer (171A, 1070A, 1070D) provided over the supporting substrate (181A, 1080A 1080D); a buffer layer (161A, 1060A, 1060D) provided over the metal gate layer (181A, 1070A, 1070D); a ferroelectric layer (151A, 1050A, 1050D) provided over the buffer layer (161A, 1060A, 1060D); and a dielectric layer (141A, 1040A, 1040D) provided on a top surface of the ferroelectric layer (151A, 1050A, 1050D), wherein a ratio of thickness of the dielectric layer (141A, 1040A, 1040D) to the ferroelectric layer (151A, 1050A, 1050D) does not exceed 2; a metal gate layer (171A, 1070A, 1070D) provided over the supporting substrate (181A, 1080A 1080D); a buffer layer (161A, 1060A, 1060D) provided over the metal gate layer (181A, 1070A, 1070D); a ferroelectric layer (151A, 1050A, 1050D) provided over the buffer layer (161A, 1060A, 1060D); and a dielectric layer (141A, 1040A, 1040D) provided on a top surface of the ferroelectric layer (151A, 1050A, 1050D), wherein a ratio of thickness of the dielectric layer (141A, 1040A, 1040D) to the ferroelectric layer (151A, 1050A, 1050D) does not exceed 2; a two-dimensional, 2D, material layer (121A, 1020A, 1020D) provided over a portion of a top surface of the dielectric layer (141A, 1040A, 1040D); and source and drain regions (111A, 1010A, 1010D, 131A, 1030A, 1030D) provided on separate portions of the top surface of the dielectric layer (1040A, 1040D) so as to create a cavity wherein the 2D material layer (121A, 1020A, 1020D) is positioned in the cavity; wherein the ferroelectric layer (151A, 1050A, 1050D) is a layer of inorganic ferroelectric films of zirconium-doped hafnium oxide HfZrOx; wherein the dielectric layer (141A, 1040A, 1040D) is a layer of dielectric hafnium oxide, HfO 2; wherein the 2D material layer (121A, 1020A, 1020D) includes a MoS 2 flake; wherein the buffer layer (161A, 1060A, 1060D) is a layer of titanium nitride, TiN; wherein a poling voltage of the transistor device is smaller than 3V; wherein a bottom surface of the dielectric layer (141A, 1040A, 1040D) is in direct contact with the top surface of the ferroelectric layer (151A, 1050A, 1050D); and wherein the metal gate layer (171A, 1070A, 1070D) is a titanium, Ti,/gold, Au, layer acting as a gate electrode.