A 3D stacked non-volatile memory device, comprising: a substrate; a stacked non-volatile memory cell array carried by the substrate, and comprising a plurality of sets of memory strings (NSA0 to NSA5, NSB0 to NSB5), and each memory string comprises a plurality of memory cells (MC0,0 to MC6,11) between a drain end (278, 306) of the memory string and a source end (302, 304) of the memory string; a plurality of bit lines (BLA0 to BLAn, BLB0 to BLBn), where, for each set of memory strings of the plurality of sets of memory strings, a respective bit line of the plurality of bit lines is connected to the drain end of each memory string in the set of memory strings; at least one source line (SLA0 to SLA2, SLB0 to SLBn) connected to the source end of at least one memory string in each of the sets of memory strings; and at least one control circuit (110, 112, 114, 116, 140, 150, 160, 165) in communication with the stacked non-volatile memory cell array, the plurality of bit lines and the at least one source line, the at least one control circuit being configured to: select for erasure one or more memory cells in the plurality of sets of memory strings, and perform one erase-verify iteration (EV0 to EV7) in an erase operation on the sets of memory strings containing at least one of the memory cells selected for erasure, by applying an erase voltage to each bit line of the plurality of bit lines connected to the sets of memory strings containing at least one of the memory cells selected for erasure, and then determining whether at least one of the sets of memory strings reaches a set erase-verify condition; wherein the 3D stacked non-volatile memory device is characterised in that the at least one control circuit is configured to perform a next erase-verify iteration in the erase operation by: (i) if it is determined that at least one of the sets of memory strings reaches the set erase-verify condition, applying an erase-inhibit voltage to the bit lines of the plurality of bit lines that are connected to the sets of memory strings that have reached the set erase-verify condition, and applying an erase voltage to the remaining bit lines of the plurality of bit lines that are connected to the sets of memory strings in the erase operation but (ii) if it is determined that none of the sets of memory strings has reached the set erase-verify condition, applying an erase voltage to each bit line of the plurality of bit lines that are connected to the sets of memory strings in the erase operation. a substrate; a stacked non-volatile memory cell array carried by the substrate, and comprising a plurality of sets of memory strings (NSA0 to NSA5, NSB0 to NSB5), and each memory string comprises a plurality of memory cells (MC0,0 to MC6,11) between a drain end (278, 306) of the memory string and a source end (302, 304) of the memory string; a plurality of bit lines (BLA0 to BLAn, BLB0 to BLBn), where, for each set of memory strings of the plurality of sets of memory strings, a respective bit line of the plurality of bit lines is connected to the drain end of each memory string in the set of memory strings; at least one source line (SLA0 to SLA2, SLB0 to SLBn) connected to the source end of at least one memory string in each of the sets of memory strings; and at least one control circuit (110, 112, 114, 116, 140, 150, 160, 165) in communication with the stacked non-volatile memory cell array, the plurality of bit lines and the at least one source line, the at least one control circuit being configured to: select for erasure one or more memory cells in the plurality of sets of memory strings, and perform one erase-verify iteration (EV0 to EV7) in an erase operation on the sets of memory strings containing at least one of the memory cells selected for erasure, by applying an erase voltage to each bit line of the plurality of bit lines connected to the sets of memory strings containing at least one of the memory cells selected for erasure, and then determining whether at least one of the sets of memory strings reaches a set erase-verify condition; wherein the 3D stacked non-volatile memory device is characterised in that the at least one control circuit is configured to perform a next erase-verify iteration in the erase operation by: (i) if it is determined that at least one of the sets of memory strings reaches the set erase-verify condition, applying an erase-inhibit voltage to the bit lines of the plurality of bit lines that are connected to the sets of memory strings that have reached the set erase-verify condition, and applying an erase voltage to the remaining bit lines of the plurality of bit lines that are connected to the sets of memory strings in the erase operation but (ii) if it is determined that none of the sets of memory strings has reached the set erase-verify condition, applying an erase voltage to each bit line of the plurality of bit lines that are connected to the sets of memory strings in the erase operation.