A device which comprises: a first integrated circuitry configured to form a first trust zone, the first integrated circuitry comprising a secure processor; and a second integrated circuitry separate from the first integrated circuitry configured to form a second trust zone, wherein: the second integrated circuitry comprises a secure non-volatile storage within the second trust zone; the first integrated circuitry and the second integrated circuitry are adapted to securely initialise a unique secure shared key between the first integrated circuitry and the second integrated circuitry; the secure processor is configured to communicate information from the first integrated circuitry to the second integrated circuitry in a secure manner using the unique secure shared key; the secure non-volatile storage is configured to securely store the information communicated from the first integrated circuitry to the second integrated circuitry in the secure manner using the unique secure shared key; the second integrated circuitry is configured to communicate the information stored in its secure non-volatile storage from the second integrated circuitry to the secure processor within the first integrated circuitry in a secure manner using the unique secure shared key; characterised in that, said first integrated circuitry and said second integrated circuitry are internal parts of the device; and the secure processor is adapted to include a random value as a parameter in a READ command so that it verifies that a subsequent result received from the second integrated circuitry is fresh, not replayed. a first integrated circuitry configured to form a first trust zone, the first integrated circuitry comprising a secure processor; and a second integrated circuitry separate from the first integrated circuitry configured to form a second trust zone, wherein: the second integrated circuitry comprises a secure non-volatile storage within the second trust zone; the first integrated circuitry and the second integrated circuitry are adapted to securely initialise a unique secure shared key between the first integrated circuitry and the second integrated circuitry; the secure processor is configured to communicate information from the first integrated circuitry to the second integrated circuitry in a secure manner using the unique secure shared key; the secure non-volatile storage is configured to securely store the information communicated from the first integrated circuitry to the second integrated circuitry in the secure manner using the unique secure shared key; the second integrated circuitry is configured to communicate the information stored in its secure non-volatile storage from the second integrated circuitry to the secure processor within the first integrated circuitry in a secure manner using the unique secure shared key; characterised in that, said first integrated circuitry and said second integrated circuitry are internal parts of the device; and the secure processor is adapted to include a random value as a parameter in a READ command so that it verifies that a subsequent result received from the second integrated circuitry is fresh, not replayed. the second integrated circuitry comprises a secure non-volatile storage within the second trust zone; the first integrated circuitry and the second integrated circuitry are adapted to securely initialise a unique secure shared key between the first integrated circuitry and the second integrated circuitry; the secure processor is configured to communicate information from the first integrated circuitry to the second integrated circuitry in a secure manner using the unique secure shared key; the secure non-volatile storage is configured to securely store the information communicated from the first integrated circuitry to the second integrated circuitry in the secure manner using the unique secure shared key; the second integrated circuitry is configured to communicate the information stored in its secure non-volatile storage from the second integrated circuitry to the secure processor within the first integrated circuitry in a secure manner using the unique secure shared key; characterised in that, said first integrated circuitry and said second integrated circuitry are internal parts of the device; and the secure processor is adapted to include a random value as a parameter in a READ command so that it verifies that a subsequent result received from the second integrated circuitry is fresh, not replayed.