A solid-state imaging device, comprising: a pixel array portion in which a plurality of unit pixels (100A; 100B; 100C; 100D; 100E; 100F; 100G) are arranged; and a drive portion configured to control an operation of the unit pixel (100A; 100B; 100C; 100D; 100E; 100F; 100G); the unit pixel (100A; 100B; 100C; 100D; 100E; 100F; 100G) including a first photoelectric conversion portion, a second photoelectric conversion portion a sensitivity of which is lower than that of the first photoelectric conversion portion, an electric charge accumulating portion configured to accumulate electric charges produced by the second photoelectric conversion portion, a counter electrode of the electric charge accumulating portion being connected to a variable voltage power source (FCVDD), a charge-to-voltage conversion portion, a first transfer gate portion configured to transfer the electric charges from the first photoelectric conversion portion to the charge-to-voltage conversion portion, and a second transfer gate portion configured to couple potentials of the charge-to-voltage conversion portion and the electric charge accumulating portion to each other; for at least a part of a period of time for which the electric charges produced by the second photoelectric conversion portion are accumulated in the electric charge accumulating portion, the drive portion is configured to cause a voltage of the variable voltage power source (FCVDD) to be lower than that when a signal based on the electric charges accumulated in the electric charge accumulating portion is read out, wherein the variable voltage power source (FCVDD) can be set to a first voltage and a second voltage lower than the first voltage, and outputs the first voltage through a low-pass filter. a pixel array portion in which a plurality of unit pixels (100A; 100B; 100C; 100D; 100E; 100F; 100G) are arranged; and a drive portion configured to control an operation of the unit pixel (100A; 100B; 100C; 100D; 100E; 100F; 100G); the unit pixel (100A; 100B; 100C; 100D; 100E; 100F; 100G) including a first photoelectric conversion portion, a second photoelectric conversion portion a sensitivity of which is lower than that of the first photoelectric conversion portion, an electric charge accumulating portion configured to accumulate electric charges produced by the second photoelectric conversion portion, a counter electrode of the electric charge accumulating portion being connected to a variable voltage power source (FCVDD), a charge-to-voltage conversion portion, a first transfer gate portion configured to transfer the electric charges from the first photoelectric conversion portion to the charge-to-voltage conversion portion, and a second transfer gate portion configured to couple potentials of the charge-to-voltage conversion portion and the electric charge accumulating portion to each other; for at least a part of a period of time for which the electric charges produced by the second photoelectric conversion portion are accumulated in the electric charge accumulating portion, the drive portion is configured to cause a voltage of the variable voltage power source (FCVDD) to be lower than that when a signal based on the electric charges accumulated in the electric charge accumulating portion is read out, wherein the variable voltage power source (FCVDD) can be set to a first voltage and a second voltage lower than the first voltage, and outputs the first voltage through a low-pass filter.