A semiconductor device (100, 400), comprising: a first semiconductor structure (102, 300, 402, 906, 1006) comprising a processor (202, 412, 608), an array of static random-access memory, SRAM, cells (204, 414, 610), and a first bonding layer (422, 616) comprising a plurality of first bonding contacts (424, 618); a second semiconductor structure (104, 301, 404, 908, 1008) comprising an array of dynamic random-access memory, DRAM, cells (206, 450) and a second bonding layer (426, 716) comprising a plurality of second bonding contacts (428, 718), wherein the first semiconductor structure (102, 300, 402, 906, 1006) comprises a peripheral circuit (416, 612) of the array of DRAM cells (206, 450), wherein transistors form the peripheral circuit (416, 612) including an input/output buffer, a decoder, and a sense amplifier and an interconnect layer vertically between the first bonding layer (424, 618) and the processor (202, 412, 608) above a device layer to transfer electrical signals to and from the processor (202, 412, 608), the array of SRAM cells (204, 414, 610) and the peripheral circuit (416, 612), wherein the device layer comprises the processor (202, 412, 608), an array of SRAM cells (204, 414, 610) and the peripheral circuit (416, 612); and a bonding interface (106, 406, 909, 1014) between the first bonding layer (422, 616) and the second bonding layer (426, 716), wherein the first bonding contacts (424, 618) are in contact with the second bonding contacts (428, 718) at the bonding interface (106, 406, 909, 1014), wherein the first semiconductor structure (102, 300, 402, 906, 1006) comprises: a substrate (408, 702) the processor (202, 412, 608) on the substrate (408, 602); the array of SRAM cells (204, 414, 610) on the substrate (408, 602, 702) and outside of the processor (202, 412, 608); and the first bonding layer (422, 616) above the processor (202, 412, 608) and the array of SRAM cells (204, 414, 610). a first semiconductor structure (102, 300, 402, 906, 1006) comprising a processor (202, 412, 608), an array of static random-access memory, SRAM, cells (204, 414, 610), and a first bonding layer (422, 616) comprising a plurality of first bonding contacts (424, 618); a second semiconductor structure (104, 301, 404, 908, 1008) comprising an array of dynamic random-access memory, DRAM, cells (206, 450) and a second bonding layer (426, 716) comprising a plurality of second bonding contacts (428, 718), wherein the first semiconductor structure (102, 300, 402, 906, 1006) comprises a peripheral circuit (416, 612) of the array of DRAM cells (206, 450), wherein transistors form the peripheral circuit (416, 612) including an input/output buffer, a decoder, and a sense amplifier and an interconnect layer vertically between the first bonding layer (424, 618) and the processor (202, 412, 608) above a device layer to transfer electrical signals to and from the processor (202, 412, 608), the array of SRAM cells (204, 414, 610) and the peripheral circuit (416, 612), wherein the device layer comprises the processor (202, 412, 608), an array of SRAM cells (204, 414, 610) and the peripheral circuit (416, 612); and a bonding interface (106, 406, 909, 1014) between the first bonding layer (422, 616) and the second bonding layer (426, 716), wherein the first bonding contacts (424, 618) are in contact with the second bonding contacts (428, 718) at the bonding interface (106, 406, 909, 1014), wherein the first semiconductor structure (102, 300, 402, 906, 1006) comprises: a substrate (408, 702) the processor (202, 412, 608) on the substrate (408, 602); the array of SRAM cells (204, 414, 610) on the substrate (408, 602, 702) and outside of the processor (202, 412, 608); and the first bonding layer (422, 616) above the processor (202, 412, 608) and the array of SRAM cells (204, 414, 610). a substrate (408, 702) the processor (202, 412, 608) on the substrate (408, 602); the array of SRAM cells (204, 414, 610) on the substrate (408, 602, 702) and outside of the processor (202, 412, 608); and the first bonding layer (422, 616) above the processor (202, 412, 608) and the array of SRAM cells (204, 414, 610).