An integrated circuit, comprising: a first plurality of flip flops (110, 112); a first bank of non-volatile resistive memory cells (202, 204), wherein each flip flop of the first plurality of flip flops (110, 112) uniquely corresponds to a non-volatile resistive memory cell of the first bank of non-volatile resistive memory cells (202, 204); write circuitry configured to store data from the first plurality of flip flops (110, 112) to the first bank of non-volatile resistive memory cells (202, 204); and read circuitry configured to read data from the first bank of non-volatile resistive memory cells (202, 204) and provide the data from the first bank for storage into the first plurality of flip flops (110, 112); wherein the first bank of non-volatile resistive memory cells (202, 204) includes a plurality of bit lines (BL 1 - BL K) in which a corresponding bit line of the plurality of bit lines (BL 1 - BL K) is coupled to each non-volatile resistive memory cell of the first bank of resistive memory cells (202, 204), characterized in that the read circuitry comprises a plurality of sense amplifiers (124 - 128), wherein each sense amplifier of the plurality of sense amplifiers (124 - 128) is coupled to a corresponding bit line of the plurality of bit lines (BL 1 - BL K), wherein each sense amplifier of the plurality of sense amplifiers (124 - 128) comprises a first capacitor, a first inverting amplifier, a second capacitor, and a second inverting amplifier connected in series between the corresponding bit line and sense amplifier output (SENSE_DATA), the output of the first inverting amplifier is coupled to a first terminal of a first transmission gate and a second terminal of the first transmission gate is coupled to the input of the first inverting amplifier, the output of the second inverting amplifier is coupled to said sense amplifier output and to a first terminal of a second transmission gate and a second terminal of the second transmission gate is coupled to the input of the second inverting amplifier, wherein the first and second capacitors (310, 316) are biased at an individual sense circuit voltage offset captured during a calibration phase before a sense phase, the first inverting amplifier and the second inverting amplifier being connected in unity gain mode by switching on said first and second transmission gates. a first plurality of flip flops (110, 112); a first bank of non-volatile resistive memory cells (202, 204), wherein each flip flop of the first plurality of flip flops (110, 112) uniquely corresponds to a non-volatile resistive memory cell of the first bank of non-volatile resistive memory cells (202, 204); write circuitry configured to store data from the first plurality of flip flops (110, 112) to the first bank of non-volatile resistive memory cells (202, 204); and read circuitry configured to read data from the first bank of non-volatile resistive memory cells (202, 204) and provide the data from the first bank for storage into the first plurality of flip flops (110, 112); wherein the first bank of non-volatile resistive memory cells (202, 204) includes a plurality of bit lines (BL 1 - BL K) in which a corresponding bit line of the plurality of bit lines (BL 1 - BL K) is coupled to each non-volatile resistive memory cell of the first bank of resistive memory cells (202, 204), characterized in that the read circuitry comprises a plurality of sense amplifiers (124 - 128), wherein each sense amplifier of the plurality of sense amplifiers (124 - 128) is coupled to a corresponding bit line of the plurality of bit lines (BL 1 - BL K), wherein each sense amplifier of the plurality of sense amplifiers (124 - 128) comprises a first capacitor, a first inverting amplifier, a second capacitor, and a second inverting amplifier connected in series between the corresponding bit line and sense amplifier output (SENSE_DATA), the output of the first inverting amplifier is coupled to a first terminal of a first transmission gate and a second terminal of the first transmission gate is coupled to the input of the first inverting amplifier, the output of the second inverting amplifier is coupled to said sense amplifier output and to a first terminal of a second transmission gate and a second terminal of the second transmission gate is coupled to the input of the second inverting amplifier, wherein the first and second capacitors (310, 316) are biased at an individual sense circuit voltage offset captured during a calibration phase before a sense phase, the first inverting amplifier and the second inverting amplifier being connected in unity gain mode by switching on said first and second transmission gates.