A signal processing device that outputs an electrical signal having a value according to an amount of charge generated in a photodiode according to an amount of incident light onto the photodiode, comprising: an integration circuit including an integration capacitor element that accumulates a charge output from the photodiode, configured to output a voltage value according to an amount of the charge accumulated in the integration capacitor element; a comparator circuit configured to compare the voltage value output from the integration circuit and input thereto with a first reference value, and when the voltage value has reached the first reference value, output a saturation signal indicating that fact; a charge injection circuit configured to, based on the saturation signal output from the comparator circuit, inject a constant amount of charge having a polarity opposite to that of the charge accumulated in the integration capacitor element of the integration circuit into the integration capacitor element; a counter circuit configured to, based on the saturation signal output from the comparator circuit, count a number of times that the voltage value output from the integration circuit has reached the first reference value and output the number of times as a first digital value; and a holding circuit configured to hold and output the voltage value output from the integration circuit; characterized by further comprising: an amplifier circuit configured to output a voltage value generated by amplifying the voltage value held and output by the holding circuit and input thereto by K times, where K>1; an A/D converter circuit configured to output a second digital value corresponding to the voltage value output from the amplifier circuit and input thereto; and a reference value generating circuit configured to be input with a second reference value that sets a maximum input voltage value in the A/D converter circuit, and supply a voltage value one K-th as large as the second reference value to the comparator circuit as the first reference value, wherein the signal processing device is configured to output a digital value represented as (M1+M2) bits of data, the digital value being configured with the first digital value represented by M1 bits and the second digital value represented by M2 bits which is subordinate to the first digital value. an integration circuit including an integration capacitor element that accumulates a charge output from the photodiode, configured to output a voltage value according to an amount of the charge accumulated in the integration capacitor element; a comparator circuit configured to compare the voltage value output from the integration circuit and input thereto with a first reference value, and when the voltage value has reached the first reference value, output a saturation signal indicating that fact; a charge injection circuit configured to, based on the saturation signal output from the comparator circuit, inject a constant amount of charge having a polarity opposite to that of the charge accumulated in the integration capacitor element of the integration circuit into the integration capacitor element; a counter circuit configured to, based on the saturation signal output from the comparator circuit, count a number of times that the voltage value output from the integration circuit has reached the first reference value and output the number of times as a first digital value; and a holding circuit configured to hold and output the voltage value output from the integration circuit; characterized by further comprising: an amplifier circuit configured to output a voltage value generated by amplifying the voltage value held and output by the holding circuit and input thereto by K times, where K>1; an A/D converter circuit configured to output a second digital value corresponding to the voltage value output from the amplifier circuit and input thereto; and a reference value generating circuit configured to be input with a second reference value that sets a maximum input voltage value in the A/D converter circuit, and supply a voltage value one K-th as large as the second reference value to the comparator circuit as the first reference value, wherein the signal processing device is configured to output a digital value represented as (M1+M2) bits of data, the digital value being configured with the first digital value represented by M1 bits and the second digital value represented by M2 bits which is subordinate to the first digital value. an amplifier circuit configured to output a voltage value generated by amplifying the voltage value held and output by the holding circuit and input thereto by K times, where K>1; an A/D converter circuit configured to output a second digital value corresponding to the voltage value output from the amplifier circuit and input thereto; and a reference value generating circuit configured to be input with a second reference value that sets a maximum input voltage value in the A/D converter circuit, and supply a voltage value one K-th as large as the second reference value to the comparator circuit as the first reference value, wherein the signal processing device is configured to output a digital value represented as (M1+M2) bits of data, the digital value being configured with the first digital value represented by M1 bits and the second digital value represented by M2 bits which is subordinate to the first digital value.