A standard cell integrated circuit, IC, comprising: a plurality of p-type metal oxide semiconductor, MOS, pMOS, transistors, each pMOS transistor of the plurality of pMOS transistors having a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate, each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors being coupled to a first voltage source, each pMOS transistor gate of the plurality of pMOS transistors being formed by a pMOS gate interconnect of a plurality of pMOS gate interconnects, each of the pMOS gate interconnects extending in a first direction and being coupled to the first voltage source, wherein one or more of the pMOS gate interconnects are connected to first metal layer one interconnects that extend along the one or more pMOS gate interconnects coupling the pMOS gate interconnects to the first voltage source; and a plurality of n-type MOS, nMOS, transistors, each nMOS transistor of the plurality of nMOS transistors having an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate, each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors being coupled to a second voltage source lower than the first voltage source, each nMOS transistor gate of the plurality of nMOS transistors being formed by an nMOS gate interconnect of a plurality of nMOS gate interconnects, each of the nMOS gate interconnects extending in the first direction and being coupled to the second voltage source, wherein one or more of the nMOS gate interconnects are connected to second metal layer one interconnects that extend along the one or more nMOS gate interconnects coupling the nMOS gate interconnects to the second voltage source. a plurality of p-type metal oxide semiconductor, MOS, pMOS, transistors, each pMOS transistor of the plurality of pMOS transistors having a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate, each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors being coupled to a first voltage source, each pMOS transistor gate of the plurality of pMOS transistors being formed by a pMOS gate interconnect of a plurality of pMOS gate interconnects, each of the pMOS gate interconnects extending in a first direction and being coupled to the first voltage source, wherein one or more of the pMOS gate interconnects are connected to first metal layer one interconnects that extend along the one or more pMOS gate interconnects coupling the pMOS gate interconnects to the first voltage source; and a plurality of n-type MOS, nMOS, transistors, each nMOS transistor of the plurality of nMOS transistors having an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate, each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors being coupled to a second voltage source lower than the first voltage source, each nMOS transistor gate of the plurality of nMOS transistors being formed by an nMOS gate interconnect of a plurality of nMOS gate interconnects, each of the nMOS gate interconnects extending in the first direction and being coupled to the second voltage source, wherein one or more of the nMOS gate interconnects are connected to second metal layer one interconnects that extend along the one or more nMOS gate interconnects coupling the nMOS gate interconnects to the second voltage source.