A register comprising: a plurality of volatile memory cells each having a first input and an output, the volatile memory cells being coupled in series with each other via their first inputs and outputs; a non-volatile memory comprising a plurality of non-volatile memory cells; and one or more serial connections (110, 112, 114), wherein the non-volatile memory comprises either: a common pair of write circuits (222, 224) for the plurality of non-volatile memory cells, and a read circuit associated with each of the non-volatile memory cells, each read circuit having its output coupled in parallel to a corresponding one of the volatile memory cells, the one or more serial connections being adapted to serially supply data to be written to the non-volatile memory from a last or another of the volatile memory cells to the non-volatile memory during a back-up operation of data stored by the volatile memory cells; or a common read circuit for the plurality of non-volatile memory cells, and a pair of write circuits (222, 224) associated with each of the non-volatile memory cells, each write circuit being controlled based on a corresponding one of the outputs of the volatile memory cells to program a data value (D V0 -D V3) in the corresponding non-volatile memory cell, the one or more serial connections being adapted to serially supply data read from the non-volatile memory to a first of the volatile memory cells during a restoration operation of the data stored by the volatile memory cells. a plurality of volatile memory cells each having a first input and an output, the volatile memory cells being coupled in series with each other via their first inputs and outputs; a non-volatile memory comprising a plurality of non-volatile memory cells; and one or more serial connections (110, 112, 114), wherein the non-volatile memory comprises either: a common pair of write circuits (222, 224) for the plurality of non-volatile memory cells, and a read circuit associated with each of the non-volatile memory cells, each read circuit having its output coupled in parallel to a corresponding one of the volatile memory cells, the one or more serial connections being adapted to serially supply data to be written to the non-volatile memory from a last or another of the volatile memory cells to the non-volatile memory during a back-up operation of data stored by the volatile memory cells; or a common read circuit for the plurality of non-volatile memory cells, and a pair of write circuits (222, 224) associated with each of the non-volatile memory cells, each write circuit being controlled based on a corresponding one of the outputs of the volatile memory cells to program a data value (D V0 -D V3) in the corresponding non-volatile memory cell, the one or more serial connections being adapted to serially supply data read from the non-volatile memory to a first of the volatile memory cells during a restoration operation of the data stored by the volatile memory cells. a common pair of write circuits (222, 224) for the plurality of non-volatile memory cells, and a read circuit associated with each of the non-volatile memory cells, each read circuit having its output coupled in parallel to a corresponding one of the volatile memory cells, the one or more serial connections being adapted to serially supply data to be written to the non-volatile memory from a last or another of the volatile memory cells to the non-volatile memory during a back-up operation of data stored by the volatile memory cells; or a common read circuit for the plurality of non-volatile memory cells, and a pair of write circuits (222, 224) associated with each of the non-volatile memory cells, each write circuit being controlled based on a corresponding one of the outputs of the volatile memory cells to program a data value (D V0 -D V3) in the corresponding non-volatile memory cell, the one or more serial connections being adapted to serially supply data read from the non-volatile memory to a first of the volatile memory cells during a restoration operation of the data stored by the volatile memory cells.