A serializer circuit (100,400,500), comprising: a recovery circuit (110, 200,410,510) configured to: receive a first data signal (102,202,402a,502a) at a first frequency, and retime the first data signal (102,202,402a,502a) based on a first clock signal (114,232,414,514) to generate a retimed first data signal (112,212,412a,512a); an adjusting circuit (120,300,420a,520a) configured to receive a second data signal (104,302,402b,502b) and retime the second data signal (104,302,402b,502b) based on the first clock signal (114,232,414,514) to generate a retimed second data signal (122,312,412b,512b); and characterized by: the recovery circuit (110, 200,410,510) being further configured to generate the first clock signal (114,232,414,514) at the first frequency using the first data signal (102,202,402a,502a) and to generate a second clock signal (116,416,516) at a second frequency using the first data signal (102,202,402a,502a); and a multiplexer circuit (130,450,550) configured to multiplex the retimed first data signal (112,212,412a,512a) and the retimed second data signal (122,312,412b,512b), wherein the multiplexer circuit (130,450,550) is configured to multiplex the retimed first data signal (112,212,412a,512a) and the retimed second data signal (122,312,412b,512b) using the second clock signal (116,416,516). a recovery circuit (110, 200,410,510) configured to: receive a first data signal (102,202,402a,502a) at a first frequency, and retime the first data signal (102,202,402a,502a) based on a first clock signal (114,232,414,514) to generate a retimed first data signal (112,212,412a,512a); receive a first data signal (102,202,402a,502a) at a first frequency, and retime the first data signal (102,202,402a,502a) based on a first clock signal (114,232,414,514) to generate a retimed first data signal (112,212,412a,512a); an adjusting circuit (120,300,420a,520a) configured to receive a second data signal (104,302,402b,502b) and retime the second data signal (104,302,402b,502b) based on the first clock signal (114,232,414,514) to generate a retimed second data signal (122,312,412b,512b); and characterized by: the recovery circuit (110, 200,410,510) being further configured to generate the first clock signal (114,232,414,514) at the first frequency using the first data signal (102,202,402a,502a) and to generate a second clock signal (116,416,516) at a second frequency using the first data signal (102,202,402a,502a); and a multiplexer circuit (130,450,550) configured to multiplex the retimed first data signal (112,212,412a,512a) and the retimed second data signal (122,312,412b,512b), wherein the multiplexer circuit (130,450,550) is configured to multiplex the retimed first data signal (112,212,412a,512a) and the retimed second data signal (122,312,412b,512b) using the second clock signal (116,416,516). the recovery circuit (110, 200,410,510) being further configured to generate the first clock signal (114,232,414,514) at the first frequency using the first data signal (102,202,402a,502a) and to generate a second clock signal (116,416,516) at a second frequency using the first data signal (102,202,402a,502a); and a multiplexer circuit (130,450,550) configured to multiplex the retimed first data signal (112,212,412a,512a) and the retimed second data signal (122,312,412b,512b), wherein the multiplexer circuit (130,450,550) is configured to multiplex the retimed first data signal (112,212,412a,512a) and the retimed second data signal (122,312,412b,512b) using the second clock signal (116,416,516).