A power transmitter for wirelessly providing power to a power receiver via an inductive power transfer signal; the power transmitter comprising: an output circuit (203, 103) comprising a transmitter coil arranged to generate the power transfer signal in response to a drive signal being applied to the output circuit (203, 103); a driver arranged to generate the drive signal; a load detector for detecting load variations for the power transfer signal; characterized by the power transmitter further comprising: a store for storing a first chip sequence and a second chip sequence, the second chip sequence having a length exceeding a length of the first chip sequence; a preamble presence detector arranged to correlate the second chip sequence with load variations of the power transfer signal to generate detection correlation values and to determine a detection of a preamble in response to a detection correlation value exceeding a preamble detection threshold; a load modulation receiver arranged to determine load modulation data symbols following the detection of the preamble in dependence on a correlation of the first chip sequence and load variations of the power transfer signal; a synchronizer arranged to synchronize data symbol time intervals for the load modulation receiver in response to a timing of the detection of the preamble, and wherein the load modulation receiver is arranged to align the correlation of the first chip sequence and load variations of the power transfer signal to the data symbol time intervals. an output circuit (203, 103) comprising a transmitter coil arranged to generate the power transfer signal in response to a drive signal being applied to the output circuit (203, 103); a driver arranged to generate the drive signal; a load detector for detecting load variations for the power transfer signal; characterized by the power transmitter further comprising: a store for storing a first chip sequence and a second chip sequence, the second chip sequence having a length exceeding a length of the first chip sequence; a preamble presence detector arranged to correlate the second chip sequence with load variations of the power transfer signal to generate detection correlation values and to determine a detection of a preamble in response to a detection correlation value exceeding a preamble detection threshold; a load modulation receiver arranged to determine load modulation data symbols following the detection of the preamble in dependence on a correlation of the first chip sequence and load variations of the power transfer signal; a synchronizer arranged to synchronize data symbol time intervals for the load modulation receiver in response to a timing of the detection of the preamble, and wherein the load modulation receiver is arranged to align the correlation of the first chip sequence and load variations of the power transfer signal to the data symbol time intervals. a store for storing a first chip sequence and a second chip sequence, the second chip sequence having a length exceeding a length of the first chip sequence; a preamble presence detector arranged to correlate the second chip sequence with load variations of the power transfer signal to generate detection correlation values and to determine a detection of a preamble in response to a detection correlation value exceeding a preamble detection threshold; a load modulation receiver arranged to determine load modulation data symbols following the detection of the preamble in dependence on a correlation of the first chip sequence and load variations of the power transfer signal; a synchronizer arranged to synchronize data symbol time intervals for the load modulation receiver in response to a timing of the detection of the preamble, and wherein the load modulation receiver is arranged to align the correlation of the first chip sequence and load variations of the power transfer signal to the data symbol time intervals.