A data processing apparatus comprising: processing circuitry for processing data, said processing circuitry being configurable to operate at a plurality of privilege levels wherein at different privilege levels (410, 420, 430, 440) said processing circuitry imposes on program instructions different access permissions to at least one of a memory and a set of registers; said program instructions comprising at least one instruction set used in both a non-debug mode and a debug mode a debug module for supplying given instructions of said program instructions, to serve as debug instructions for execution by said processing circuitry; instruction decoding circuitry responsive to said program instructions to generate control signals for controlling said processing circuitry to perform said data processing; wherein said program instructions comprise a debug privilege-level switching instruction, said instruction decoding circuitry being responsive to said debug privilege-level switching instruction to perform the following: (i) if said processing circuitry is in a debug mode to switch said processing circuitry from a current privilege level to a target privilege level; and (ii) if said processing circuitry is in a non-debug mode, to prevent execution of said debug privilege-level switching instruction regardless of said current privilege level and wherein an instruction encoding of said debug privilege-level switching instruction is an encoding belonging to said at least one instruction set. processing circuitry for processing data, said processing circuitry being configurable to operate at a plurality of privilege levels wherein at different privilege levels (410, 420, 430, 440) said processing circuitry imposes on program instructions different access permissions to at least one of a memory and a set of registers; said program instructions comprising at least one instruction set used in both a non-debug mode and a debug mode a debug module for supplying given instructions of said program instructions, to serve as debug instructions for execution by said processing circuitry; instruction decoding circuitry responsive to said program instructions to generate control signals for controlling said processing circuitry to perform said data processing; wherein said program instructions comprise a debug privilege-level switching instruction, said instruction decoding circuitry being responsive to said debug privilege-level switching instruction to perform the following: (i) if said processing circuitry is in a debug mode to switch said processing circuitry from a current privilege level to a target privilege level; and (ii) if said processing circuitry is in a non-debug mode, to prevent execution of said debug privilege-level switching instruction regardless of said current privilege level and wherein an instruction encoding of said debug privilege-level switching instruction is an encoding belonging to said at least one instruction set. (i) if said processing circuitry is in a debug mode to switch said processing circuitry from a current privilege level to a target privilege level; and (ii) if said processing circuitry is in a non-debug mode, to prevent execution of said debug privilege-level switching instruction regardless of said current privilege level and wherein an instruction encoding of said debug privilege-level switching instruction is an encoding belonging to said at least one instruction set.