A bit storage device comprising: a first register including a first output, the first register configured to store an actual value and the first output configured to provide a first output value; a second register including a second output, the second register configured to store an inverse value, wherein a second output value at the second output of the second register is inverse to a first output value at the first output of the first register; a third register including a third output, the third register configured to store a differential actual value that is the value of the actual value stored in the first register and written at a different time; and a fourth register including a fourth output, the fourth register configured to store a differential inverse value that has the value of the inverse value stored in second register and written at a different time, wherein the differential inverse value at the fourth output is inverted relative to the differential actual value at the third output of the third register; the bit storage device characterized by: a validation circuit configured to provide mutually exclusive outputs to indicate whether a combination of values stored in first register, second register, third register, and fourth register validly represent a stored bit value, the validation circuit including a first validation input coupled to the first output of the first register, a second validation input coupled to the second output of the second register, a third validation input coupled to the third output of the third register, a fourth validation input coupled to the fourth output of the fourth register, and a validity output to provide a validity indication; and a write circuit having a first write circuit input coupled to the first register, a second write circuit input coupled to the second register, a third write circuit input coupled to the third register, and a fourth write circuit input coupled to the fourth register, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and a first other storage operation selected from a first group consisting of the second register being caused to store the inverse value and the fourth register being caused to store the differential inverse value, the write circuit configured to cause, at a second clock edge, the third register to store the differential actual value and a second other storage operation selected from a second group consisting of the second register being caused to store the inverse value and the fourth register being caused to store the differential inverse value, wherein the second other storage operation is performed on a different register than the first other storage operation. a first register including a first output, the first register configured to store an actual value and the first output configured to provide a first output value; a second register including a second output, the second register configured to store an inverse value, wherein a second output value at the second output of the second register is inverse to a first output value at the first output of the first register; a third register including a third output, the third register configured to store a differential actual value that is the value of the actual value stored in the first register and written at a different time; and a fourth register including a fourth output, the fourth register configured to store a differential inverse value that has the value of the inverse value stored in second register and written at a different time, wherein the differential inverse value at the fourth output is inverted relative to the differential actual value at the third output of the third register; a validation circuit configured to provide mutually exclusive outputs to indicate whether a combination of values stored in first register, second register, third register, and fourth register validly represent a stored bit value, the validation circuit including a first validation input coupled to the first output of the first register, a second validation input coupled to the second output of the second register, a third validation input coupled to the third output of the third register, a fourth validation input coupled to the fourth output of the fourth register, and a validity output to provide a validity indication; and a write circuit having a first write circuit input coupled to the first register, a second write circuit input coupled to the second register, a third write circuit input coupled to the third register, and a fourth write circuit input coupled to the fourth register, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and a first other storage operation selected from a first group consisting of the second register being caused to store the inverse value and the fourth register being caused to store the differential inverse value, the write circuit configured to cause, at a second clock edge, the third register to store the differential actual value and a second other storage operation selected from a second group consisting of the second register being caused to store the inverse value and the fourth register being caused to store the differential inverse value, wherein the second other storage operation is performed on a different register than the first other storage operation.