A circuit (100, 300) for generating a pulse comprising: a transistor (101, 301) constructed and arranged to be operable in an avalanche mode; and a pulse generating circuit constructed and arranged to receive at least one trigger input signal, generate a voltage pulse having a duration less than an avalanche time of the transistor (101, 301) in response to at least a portion of the at least one trigger input signal, and transmit the voltage pulse to a terminal of the transistor (101, 301); wherein the transistor (101, 301) is constructed and arranged to output an avalanche pulse from at least one terminal of the transistor (101, 301) in response to the voltage pulse; characterised in that the circuit (100, 300) further comprises: at least one negative bias generator constructed and arranged to generate a negative voltage; wherein the pulse generating circuit comprises: at least one step recovery diode (131, 311) referenced to the negative voltage at a cathode of the at least one SRD (131, 311), wherein the SRD (131, 311) is constructed and arranged to receive the at least one trigger input signal at an anode of the at least one SRD (131, 311), store charge when the at least one trigger input signal has a positive voltage, and stop storing charge when the at least one trigger input signal has a negative voltage; and at least one inductor constructed and arranged to generate the voltage pulse after the at least one SRD (131, 311) stops storing charge. a transistor (101, 301) constructed and arranged to be operable in an avalanche mode; and a pulse generating circuit constructed and arranged to receive at least one trigger input signal, generate a voltage pulse having a duration less than an avalanche time of the transistor (101, 301) in response to at least a portion of the at least one trigger input signal, and transmit the voltage pulse to a terminal of the transistor (101, 301); wherein the transistor (101, 301) is constructed and arranged to output an avalanche pulse from at least one terminal of the transistor (101, 301) in response to the voltage pulse; characterised in that the circuit (100, 300) further comprises: at least one negative bias generator constructed and arranged to generate a negative voltage; wherein the pulse generating circuit comprises: at least one step recovery diode (131, 311) referenced to the negative voltage at a cathode of the at least one SRD (131, 311), wherein the SRD (131, 311) is constructed and arranged to receive the at least one trigger input signal at an anode of the at least one SRD (131, 311), store charge when the at least one trigger input signal has a positive voltage, and stop storing charge when the at least one trigger input signal has a negative voltage; and at least one inductor constructed and arranged to generate the voltage pulse after the at least one SRD (131, 311) stops storing charge. at least one step recovery diode (131, 311) referenced to the negative voltage at a cathode of the at least one SRD (131, 311), wherein the SRD (131, 311) is constructed and arranged to receive the at least one trigger input signal at an anode of the at least one SRD (131, 311), store charge when the at least one trigger input signal has a positive voltage, and stop storing charge when the at least one trigger input signal has a negative voltage; and at least one inductor constructed and arranged to generate the voltage pulse after the at least one SRD (131, 311) stops storing charge.