A frequency synthesizer (100, 200) for correcting the phase error in the feedback loop of a phase locked loop, comprising: means for comparing (102, 202) a phase-corrected output signal with a reference clock (112, 212) to produce an error signal (118, 218" 618); means for filtering (104, 204) the error signal; means for creating (106, 206) an oscillator output with a frequency based on the filtered error signal; means for selecting an integer divide ratio to achieve a time-average fractional divide ratio; means for dividing (108, 208) the frequency of the oscillator output by the selected integer divide ratio; and means for adjusting (110, 210, 610) a phase of the divided oscillator output to produce the phase-corrected oscillator output (118, 218, 618), wherein the means for adjusting uses one or more received control signals, and means for determining the control signals, comprising: means for outputting (122, 222, 622) an instantaneous integer divide ratio based on a received time-average fractional divide ratio (124, 224, 624); means for accumulating a difference between the time-average fractional divide ratio and the instantaneous integer divide ratio to produce an accumulated division ratio error; means for scaling the accumulated division ratio error by a gain normalization factor; means for adding an offset to the gain-normalized ratio error; means for truncating the offset ratio error; and means for producing, based on the truncated ratio error, the control signals to alternate delay elements used in the phase correction circuitry. means for comparing (102, 202) a phase-corrected output signal with a reference clock (112, 212) to produce an error signal (118, 218" 618); means for filtering (104, 204) the error signal; means for creating (106, 206) an oscillator output with a frequency based on the filtered error signal; means for selecting an integer divide ratio to achieve a time-average fractional divide ratio; means for dividing (108, 208) the frequency of the oscillator output by the selected integer divide ratio; and means for adjusting (110, 210, 610) a phase of the divided oscillator output to produce the phase-corrected oscillator output (118, 218, 618), wherein the means for adjusting uses one or more received control signals, and means for determining the control signals, comprising: means for outputting (122, 222, 622) an instantaneous integer divide ratio based on a received time-average fractional divide ratio (124, 224, 624); means for accumulating a difference between the time-average fractional divide ratio and the instantaneous integer divide ratio to produce an accumulated division ratio error; means for scaling the accumulated division ratio error by a gain normalization factor; means for adding an offset to the gain-normalized ratio error; means for truncating the offset ratio error; and means for producing, based on the truncated ratio error, the control signals to alternate delay elements used in the phase correction circuitry. means for outputting (122, 222, 622) an instantaneous integer divide ratio based on a received time-average fractional divide ratio (124, 224, 624); means for accumulating a difference between the time-average fractional divide ratio and the instantaneous integer divide ratio to produce an accumulated division ratio error; means for scaling the accumulated division ratio error by a gain normalization factor; means for adding an offset to the gain-normalized ratio error; means for truncating the offset ratio error; and means for producing, based on the truncated ratio error, the control signals to alternate delay elements used in the phase correction circuitry.