A semiconductor device comprising: a master (20, 30, 40) that issues an access request to a memory; a memory controller that is coupled to the master (20, 30, 40) through a bus (24, 34, 44) and accesses the memory according to the access request; and an access control unit that controls output of the access request issued by the master (20, 30, 40) to the memory controller through granting an access right to the memory to the master (20, 30, 40), wherein the access control unit manages the number of rights which indicates the number of the access rights that can be granted, and performs grant of the access right within a range of the number of rights that can be granted, characterized in that the access control unit comprises: a sub-bus controller (22, 32, 42) having a request issuance control unit (23, 33, 43) that receives the access request issued by the master (20, 30, 40); and a central bus control unit that grants an access right to the master (20, 30, 40) that is an issuance source of the access request received by the request issuance control unit (23, 33, 43) by granting the access right to the request issuance control unit (23, 33, 43), and wherein when the access right is granted to the request issuance control unit (23, 33, 43) from the central bus control unit, the request issuance control unit (23, 33, 43) outputs the access request to the memory controller, and when the access right is not granted to the request issuance control unit (23, 33, 43), the request issuance control unit (23, 33, 43) prevents the access request from being outputted to the memory controller, wherein the central bus control unit calculates, as the number of access rights that can be granted, a difference between a maximum number of rights to be granted, which indicates a maximum number of access rights to be granted, and a number of currently granted access rights, wherein when the request issuance control unit (23, 33, 43) outputs the access request to the memory controller, the request issuance control unit (23, 33, 43) notifies the central bus control unit of an access size of the access request to be outputted to the memory controller, the access size indicating a size of data to be read from the memory or a size of data to be written to the memory, and wherein the central bus control unit corrects the number of currently granted rights based on the access size notified from the request issuance control unit (23, 33, 43). a master (20, 30, 40) that issues an access request to a memory; a memory controller that is coupled to the master (20, 30, 40) through a bus (24, 34, 44) and accesses the memory according to the access request; and an access control unit that controls output of the access request issued by the master (20, 30, 40) to the memory controller through granting an access right to the memory to the master (20, 30, 40), wherein the access control unit manages the number of rights which indicates the number of the access rights that can be granted, and performs grant of the access right within a range of the number of rights that can be granted, characterized in that the access control unit comprises: a sub-bus controller (22, 32, 42) having a request issuance control unit (23, 33, 43) that receives the access request issued by the master (20, 30, 40); and a central bus control unit that grants an access right to the master (20, 30, 40) that is an issuance source of the access request received by the request issuance control unit (23, 33, 43) by granting the access right to the request issuance control unit (23, 33, 43), and a sub-bus controller (22, 32, 42) having a request issuance control unit (23, 33, 43) that receives the access request issued by the master (20, 30, 40); and a central bus control unit that grants an access right to the master (20, 30, 40) that is an issuance source of the access request received by the request issuance control unit (23, 33, 43) by granting the access right to the request issuance control unit (23, 33, 43), and wherein when the access right is granted to the request issuance control unit (23, 33, 43) from the central bus control unit, the request issuance control unit (23, 33, 43) outputs the access request to the memory controller, and when the access right is not granted to the request issuance control unit (23, 33, 43), the request issuance control unit (23, 33, 43) prevents the access request from being outputted to the memory controller, wherein the central bus control unit calculates, as the number of access rights that can be granted, a difference between a maximum number of rights to be granted, which indicates a maximum number of access rights to be granted, and a number of currently granted access rights, wherein when the request issuance control unit (23, 33, 43) outputs the access request to the memory controller, the request issuance control unit (23, 33, 43) notifies the central bus control unit of an access size of the access request to be outputted to the memory controller, the access size indicating a size of data to be read from the memory or a size of data to be written to the memory, and wherein the central bus control unit corrects the number of currently granted rights based on the access size notified from the request issuance control unit (23, 33, 43).