An integrated circuit comprising a translation lookaside buffer, TLB, that comprises: a first fixed set-associative sub-TLB that is adapted to store, during runtime, a first plurality of TLB entries corresponding to a first page size set, wherein the first page size set includes only a first page size, and wherein the fixed sub-TLB is adapted to hold the first page size set fixed after boot; a configurable sub-TLB that is configurable to store, during runtime, a second plurality of TLB entries (340, 342, 346) of a second page size set, characterized in that the second page size set includes at least a first page size of the first page size set and includes at least a second page size not of the first page size set, wherein the configurable sub-TLB is configurable to hold different page size sets at different times after boot; a second fixed set-associative sub-TLB that is configured to store, during runtime, a third plurality of TLB entries corresponding to a third page size set wherein the second fixed set-associative sub-TLB is adapted to hold the third page size set fixed after boot; the third page size set includes only a third page size, wherein the second page size set includes the third page size, and wherein the TLB further comprises: control circuitry that is adapted to monitor a first miss rate of the first fixed set-associative TLB and a second miss rate of the second fixed set-associative TLB, and wherein the control circuitry is configured to select whether to store a new TLB entry corresponding to the first page size in the first fixed set-associative sub-TLB or in the configurable sub-TLB based at least in part on whether the first miss rate is higher than the second miss rate. a first fixed set-associative sub-TLB that is adapted to store, during runtime, a first plurality of TLB entries corresponding to a first page size set, wherein the first page size set includes only a first page size, and wherein the fixed sub-TLB is adapted to hold the first page size set fixed after boot; a configurable sub-TLB that is configurable to store, during runtime, a second plurality of TLB entries (340, 342, 346) of a second page size set, characterized in that the second page size set includes at least a first page size of the first page size set and includes at least a second page size not of the first page size set, wherein the configurable sub-TLB is configurable to hold different page size sets at different times after boot; a second fixed set-associative sub-TLB that is configured to store, during runtime, a third plurality of TLB entries corresponding to a third page size set wherein the second fixed set-associative sub-TLB is adapted to hold the third page size set fixed after boot; the third page size set includes only a third page size, wherein the second page size set includes the third page size, and wherein the TLB further comprises: control circuitry that is adapted to monitor a first miss rate of the first fixed set-associative TLB and a second miss rate of the second fixed set-associative TLB, and wherein the control circuitry is configured to select whether to store a new TLB entry corresponding to the first page size in the first fixed set-associative sub-TLB or in the configurable sub-TLB based at least in part on whether the first miss rate is higher than the second miss rate.