A method of forming a memory array, comprising: forming a planar layer of first dielectric material over a first semiconductor material; patterning the first dielectric material to form openings extending through the first dielectric material to the first semiconductor material; after patterning the first dielectric material, forming second semiconductor material over the patterned first dielectric material and within the openings and in direct contact with the first semiconductor material; patterning the second semiconductor material into a plurality of active regions, the active regions being over and in one-to-one correspondence with the openings; forming second dielectric material over and between the active regions and in direct contact with the first dielectric material; patterning the second dielectric material to form trenches (40, 42, 44, 46) extending through the second dielectric material to the first dielectric material, the trenches (40, 42, 44, 46) extending across the active regions, paired trenches (42, 44) extending across individual ones of the active regions; forming wordlines (60, 62, 64, 66) within the trenches (40, 42, 44, 46) that extend through the second dielectric material, the wordlines (60, 62, 64, 66) being paired across the active regions, and segments of the paired wordlines (60, 62, 64, 66) over the active regions corresponding to paired transistor gates, individual transistor gates having a portion directly over the first dielectric material and having another portion directly over an opening, the planar layer of first dielectric material comprising segments that extend from directly under a portion of one of a set of paired transistor gates associated with an individual active region to directly under a portion of one of another set of paired transistor gates associated with an adjacent active region; implanting conductivity-enhancing dopant into the second semiconductor material of the active regions to form source/drain regions (70, 72, 74, 76, 78, 80, 82) within the active regions, each of the plurality of active regions having three source/drain regions (74, 76, 78), one of the three source/drain regions of an individual active region being a shared source/drain region between the paired transistor gates associated with the individual active region, the remaining two (74, 78) of the three source/drain regions being outer source/drain regions on opposing sides of the paired transistor gates from the shared source/drain region; forming capacitors (105, 114, 116,..), wherein a storage node of one of the capacitors (105, 114, 116,..) is electrically connected with one of the outer source/drain regions; and forming bitlines (120, 122, 124), wherein at least one of the bitlines (120, 122, 124) is electrically coupled with the shared source/drain region. forming a planar layer of first dielectric material over a first semiconductor material; patterning the first dielectric material to form openings extending through the first dielectric material to the first semiconductor material; after patterning the first dielectric material, forming second semiconductor material over the patterned first dielectric material and within the openings and in direct contact with the first semiconductor material; patterning the second semiconductor material into a plurality of active regions, the active regions being over and in one-to-one correspondence with the openings; forming second dielectric material over and between the active regions and in direct contact with the first dielectric material; patterning the second dielectric material to form trenches (40, 42, 44, 46) extending through the second dielectric material to the first dielectric material, the trenches (40, 42, 44, 46) extending across the active regions, paired trenches (42, 44) extending across individual ones of the active regions; forming wordlines (60, 62, 64, 66) within the trenches (40, 42, 44, 46) that extend through the second dielectric material, the wordlines (60, 62, 64, 66) being paired across the active regions, and segments of the paired wordlines (60, 62, 64, 66) over the active regions corresponding to paired transistor gates, individual transistor gates having a portion directly over the first dielectric material and having another portion directly over an opening, the planar layer of first dielectric material comprising segments that extend from directly under a portion of one of a set of paired transistor gates associated with an individual active region to directly under a portion of one of another set of paired transistor gates associated with an adjacent active region; implanting conductivity-enhancing dopant into the second semiconductor material of the active regions to form source/drain regions (70, 72, 74, 76, 78, 80, 82) within the active regions, each of the plurality of active regions having three source/drain regions (74, 76, 78), one of the three source/drain regions of an individual active region being a shared source/drain region between the paired transistor gates associated with the individual active region, the remaining two (74, 78) of the three source/drain regions being outer source/drain regions on opposing sides of the paired transistor gates from the shared source/drain region; forming capacitors (105, 114, 116,..), wherein a storage node of one of the capacitors (105, 114, 116,..) is electrically connected with one of the outer source/drain regions; and forming bitlines (120, 122, 124), wherein at least one of the bitlines (120, 122, 124) is electrically coupled with the shared source/drain region.