A communication circuit, comprising: a first communication node comprising a first control chip and a first communication chip, wherein the first communication chip transmitting a differential signal, wherein the first control chip being connected to the first communication chip, the first communication chip being provided with a first output port, wherein the first output port outputting a level signal obtained from the differential signal to the first control chip; a second communication node comprising a second control chip and a second communication chip, wherein the second communication chip transmitting a differential signal, wherein the second control chip being connected to the second communication chip, and the second communication chip being connected to the first communication chip through a first signal line and a second signal line; and a voltage division assembly connected to the first signal line and the second signal line; wherein the first control chip is provided with a detection port, the detection port is connected to the first output port to acquire the level signal output by the first output port, and the level signal output by the first output port determines a correctness of a connection polarity between the first communication chip and the second communication chip characterized in that: the voltage division assembly is connected to the first and second signal line such that a voltage value of the first signal line is higher than that of the second signal line when the first signal line and the second signal line are in an idle state; and the voltage division assembly comprises a first resistive element, a second resistive element and a third resistive element, the first resistive element is connected between a power end and the first signal line, the second resistive element is connected between the first signal line and the second signal line, and the third resistive element is connected between the second signal line and a reference ground; and wherein an absolute voltage value between two ends of the second resistive element is higher than a differential voltage value corresponding to the level signal of the first communication chip or a level signal of the second communication chip. a first communication node comprising a first control chip and a first communication chip, wherein the first communication chip transmitting a differential signal, wherein the first control chip being connected to the first communication chip, the first communication chip being provided with a first output port, wherein the first output port outputting a level signal obtained from the differential signal to the first control chip; a second communication node comprising a second control chip and a second communication chip, wherein the second communication chip transmitting a differential signal, wherein the second control chip being connected to the second communication chip, and the second communication chip being connected to the first communication chip through a first signal line and a second signal line; and a voltage division assembly connected to the first signal line and the second signal line; wherein the first control chip is provided with a detection port, the detection port is connected to the first output port to acquire the level signal output by the first output port, and the level signal output by the first output port determines a correctness of a connection polarity between the first communication chip and the second communication chip characterized in that: the voltage division assembly is connected to the first and second signal line such that a voltage value of the first signal line is higher than that of the second signal line when the first signal line and the second signal line are in an idle state; and the voltage division assembly comprises a first resistive element, a second resistive element and a third resistive element, the first resistive element is connected between a power end and the first signal line, the second resistive element is connected between the first signal line and the second signal line, and the third resistive element is connected between the second signal line and a reference ground; and wherein an absolute voltage value between two ends of the second resistive element is higher than a differential voltage value corresponding to the level signal of the first communication chip or a level signal of the second communication chip. the voltage division assembly is connected to the first and second signal line such that a voltage value of the first signal line is higher than that of the second signal line when the first signal line and the second signal line are in an idle state; and the voltage division assembly comprises a first resistive element, a second resistive element and a third resistive element, the first resistive element is connected between a power end and the first signal line, the second resistive element is connected between the first signal line and the second signal line, and the third resistive element is connected between the second signal line and a reference ground; and wherein an absolute voltage value between two ends of the second resistive element is higher than a differential voltage value corresponding to the level signal of the first communication chip or a level signal of the second communication chip.