A digital-to analog converter, DAC, of the charge transfer type suitable for use in a sigma delta modulator for generating N output levels, wherein N>5 and wherein an output level is defined by a respective amount of charge transferred by the DAC, comprising: a first capacitor switch unit receiving a reference voltage and a first digital input value and being operable to transfer a first plurality of output charges to generate 5 output levels, at least one second capacitor switch unit receiving said reference voltage and a second digital input value and being operable to transfer output charges to generate 5 output levels, wherein an output of the second capacitor switch unit is coupled in parallel with an output of said first capacitor switch unit to generate a sum of said first plurality of transferred output charges and a second plurality of transferred output charges from said second capacitor switch unit (310; 330); and a sequencer operable to control switches of said first and second capacitor switch units (260, 310) depending on said first and second digital input value, respectively, to generate respective output charges, wherein the first and second digital input values depend on a selected DAC input value, wherein switching sequences for the first and second capacitor switch units (260, 310) are chosen such that at least one of said N output levels generated by respective first and second plurality of transferred output charges is proportional to the sum of respective capacitance values of the first and second capacitor switch units (260, 310) and wherein for each of said N output levels for which switching sequences for the first and second capacitor switch units (260, 310) do not produce an output level proportional to a sum of the capacitors of said first and second capacitor switch unit (260, 310), at least one alternative switching sequence is provided to transfer a respective charge, wherein an average DAC output charge of sequential DAC input values having the same values is proportional to a sum of the capacitors of said first and second capacitor switch unit (260, 310) by changing associated switching sequences for said first and/or second capacitor switch unit(260, 310). a first capacitor switch unit receiving a reference voltage and a first digital input value and being operable to transfer a first plurality of output charges to generate 5 output levels, at least one second capacitor switch unit receiving said reference voltage and a second digital input value and being operable to transfer output charges to generate 5 output levels, wherein an output of the second capacitor switch unit is coupled in parallel with an output of said first capacitor switch unit to generate a sum of said first plurality of transferred output charges and a second plurality of transferred output charges from said second capacitor switch unit (310; 330); and a sequencer operable to control switches of said first and second capacitor switch units (260, 310) depending on said first and second digital input value, respectively, to generate respective output charges, wherein the first and second digital input values depend on a selected DAC input value, wherein switching sequences for the first and second capacitor switch units (260, 310) are chosen such that at least one of said N output levels generated by respective first and second plurality of transferred output charges is proportional to the sum of respective capacitance values of the first and second capacitor switch units (260, 310) and wherein for each of said N output levels for which switching sequences for the first and second capacitor switch units (260, 310) do not produce an output level proportional to a sum of the capacitors of said first and second capacitor switch unit (260, 310), at least one alternative switching sequence is provided to transfer a respective charge, wherein an average DAC output charge of sequential DAC input values having the same values is proportional to a sum of the capacitors of said first and second capacitor switch unit (260, 310) by changing associated switching sequences for said first and/or second capacitor switch unit(260, 310).