An ESD power clamp comprising: ESD suppression circuitry to detect an ESD and to shunt the ESD to ground, wherein the ESD suppression circuitry comprises a first switch and a second switch operable to shunt the ESD to the ground; single event effect protection circuitry coupled to the ESD suppression circuitry to suppress a non-ESD transient event that may be experienced by the ESD suppression circuitry, wherein the single event effect protection circuitry includes a first triggering circuit (206; 302) coupled to the first switch of the ESD suppression circuitry and a second triggering circuit (208; 304) coupled to the second switch of the ESD suppression circuitry in order to operate the first switch and the second switch independently; and a defect detector (214; 314) coupled to the ESD suppression circuitry and the single event effect suppression circuitry to detect manufacturing defects of the ESD power clamp, wherein the defect detector comprises: a first P-type transistor having a gate receiving an output of the first triggering circuit, wherein the first triggering circuit comprises a first RC network, a second P-type transistor having a gate receiving an output of the second triggering circuit, wherein the second triggering circuit comprises a second RC network, and wherein the first and second P-type transistors form two parallel paths through which a current source current flows to thereby create a signal indicating a defect; and wherein the defect detector (214; 314) is configured to supplement a leakage current of a resistor in either of the first RC network or the second RC network if a capacitor of the either of the first or second RC network has a defect, to produce a measurable current so that the defect can be identified; wherein if an output from one of the first or second triggering circuits is below a threshold level, a combination of an output of the first P-type transistor and an output of the second P-type transistor results in a signal indicating the defect. ESD suppression circuitry to detect an ESD and to shunt the ESD to ground, wherein the ESD suppression circuitry comprises a first switch and a second switch operable to shunt the ESD to the ground; single event effect protection circuitry coupled to the ESD suppression circuitry to suppress a non-ESD transient event that may be experienced by the ESD suppression circuitry, wherein the single event effect protection circuitry includes a first triggering circuit (206; 302) coupled to the first switch of the ESD suppression circuitry and a second triggering circuit (208; 304) coupled to the second switch of the ESD suppression circuitry in order to operate the first switch and the second switch independently; and a defect detector (214; 314) coupled to the ESD suppression circuitry and the single event effect suppression circuitry to detect manufacturing defects of the ESD power clamp, wherein the defect detector comprises: a first P-type transistor having a gate receiving an output of the first triggering circuit, wherein the first triggering circuit comprises a first RC network, a second P-type transistor having a gate receiving an output of the second triggering circuit, wherein the second triggering circuit comprises a second RC network, and wherein the first and second P-type transistors form two parallel paths through which a current source current flows to thereby create a signal indicating a defect; and wherein the defect detector (214; 314) is configured to supplement a leakage current of a resistor in either of the first RC network or the second RC network if a capacitor of the either of the first or second RC network has a defect, to produce a measurable current so that the defect can be identified; wherein if an output from one of the first or second triggering circuits is below a threshold level, a combination of an output of the first P-type transistor and an output of the second P-type transistor results in a signal indicating the defect. a first P-type transistor having a gate receiving an output of the first triggering circuit, wherein the first triggering circuit comprises a first RC network, a second P-type transistor having a gate receiving an output of the second triggering circuit, wherein the second triggering circuit comprises a second RC network, and wherein the first and second P-type transistors form two parallel paths through which a current source current flows to thereby create a signal indicating a defect; and wherein the defect detector (214; 314) is configured to supplement a leakage current of a resistor in either of the first RC network or the second RC network if a capacitor of the either of the first or second RC network has a defect, to produce a measurable current so that the defect can be identified; wherein if an output from one of the first or second triggering circuits is below a threshold level, a combination of an output of the first P-type transistor and an output of the second P-type transistor results in a signal indicating the defect.