A shift register, comprising: a pull-up node control circuit, configured to control a potential of a pull-up node inside the shift register to be pulled up according to a first input signal received via a first signal input terminal (INPUT 1) and to control the potential of the pull-up node to be pulled up according to a second input signal received via a second signal input terminal (INPUT2) of the shift register; a first capacitor, coupled between a signal output terminal (OUTPUT) of the shift register and the pull-up node; a pull-down node control circuit, configured to control a potential of a pull-down node according to a second clock signal and a third clock signal received respectively via a second clock signal terminal and a third clock signal terminal of the shift register and a potential of the pull-up node; an output circuit, configured to control an output of a gate electrode driving signal at the signal output terminal (OUTPUT) according to the potential of the pull-up node and a first clock signal received via a first clock signal terminal of the shift register; and a pull-down circuit, configured to allow the potential of the pull-up node and the potential of the signal output terminal (OUTPUT) to be pulled down according to a potential of the pull-down node, wherein, the output circuit comprises: a seventh transistor, a control electrode of the seventh transistor being coupled to the pull-up node via an eighth transistor, a first electrode of the seventh transistor being coupled to the first clock signal terminal, and a second electrode of the seventh transistor being coupled to the signal output terminal (OUTPUT); wherein a control electrode of the eighth transistor is coupled to a second potential terminal of the shift register; characterized in that a first electrode of the eighth transistor being coupled to the pull-up node and one terminal of the first capacitor, and a second electrode of the eighth transistor being coupled to the control electrode of the seventh transistor, the other terminal of the first capacitor being coupled to the second electrode of the seventh transistor. a pull-up node control circuit, configured to control a potential of a pull-up node inside the shift register to be pulled up according to a first input signal received via a first signal input terminal (INPUT 1) and to control the potential of the pull-up node to be pulled up according to a second input signal received via a second signal input terminal (INPUT2) of the shift register; a first capacitor, coupled between a signal output terminal (OUTPUT) of the shift register and the pull-up node; a pull-down node control circuit, configured to control a potential of a pull-down node according to a second clock signal and a third clock signal received respectively via a second clock signal terminal and a third clock signal terminal of the shift register and a potential of the pull-up node; an output circuit, configured to control an output of a gate electrode driving signal at the signal output terminal (OUTPUT) according to the potential of the pull-up node and a first clock signal received via a first clock signal terminal of the shift register; and a pull-down circuit, configured to allow the potential of the pull-up node and the potential of the signal output terminal (OUTPUT) to be pulled down according to a potential of the pull-down node, wherein, the output circuit comprises: a seventh transistor, a control electrode of the seventh transistor being coupled to the pull-up node via an eighth transistor, a first electrode of the seventh transistor being coupled to the first clock signal terminal, and a second electrode of the seventh transistor being coupled to the signal output terminal (OUTPUT); wherein a control electrode of the eighth transistor is coupled to a second potential terminal of the shift register; characterized in that a first electrode of the eighth transistor being coupled to the pull-up node and one terminal of the first capacitor, and a second electrode of the eighth transistor being coupled to the control electrode of the seventh transistor, the other terminal of the first capacitor being coupled to the second electrode of the seventh transistor. a seventh transistor, a control electrode of the seventh transistor being coupled to the pull-up node via an eighth transistor, a first electrode of the seventh transistor being coupled to the first clock signal terminal, and a second electrode of the seventh transistor being coupled to the signal output terminal (OUTPUT); wherein a control electrode of the eighth transistor is coupled to a second potential terminal of the shift register; characterized in that a first electrode of the eighth transistor being coupled to the pull-up node and one terminal of the first capacitor, and a second electrode of the eighth transistor being coupled to the control electrode of the seventh transistor, the other terminal of the first capacitor being coupled to the second electrode of the seventh transistor.