A three-dimensional non-volatile storage device, comprising: a semiconductor substrate having a major surface that extends in a horizontal plane; a plurality of word lines (WL0, WL1,...); a plurality of bit lines (BLA0-BLAn; BLB0-BLBn; BL0, BL1); a plurality of NAND strings (NSA0, NSA1,...; NSB0, NSB1,...; NS00, NS01, NS02, NS03, NS10, NS11, NS12) that extend in a vertical direction with respect to the horizontal plane, each of the NAND strings comprising a drain side select transistor (SGD0, SGD1...) coupled to a bit line of the plurality of bit lines, each of the NAND strings being associated with a group of the plurality of word lines, each of the NAND strings comprising a plurality of memory cells (MCn, MCn-1,..., MC0); and managing circuitry (110, 122, 124, 128, 132) in communication with the plurality of word lines, the plurality of bit lines, and the drain side select transistors of the plurality of NAND strings, wherein the managing circuitry is configured to apply a programming voltage (Vpgm) to a selected word line of the plurality of word lines that is connected to a memory cell on a selected NAND string and to a memory cell on an unselected NAND string (NS01, NS11) of the plurality of NAND strings, wherein the managing circuitry is configured to apply a boosting voltage to unselected word lines connected to memory cells on the unselected NAND string while the managing circuitry applies the programming voltage to the selected word line, wherein the managing circuitry is configured to apply a program enable voltage (V_Program Enable) to a selected bit line that is associated with the selected NAND string, wherein the managing circuitry is configured to apply a voltage (V_Program Enable or Vbl_Inhibit) to a bit line associated with the unselected NAND string, wherein the managing circuitry is configured to generate an unselect voltage (Vsdgu) that has a magnitude that depends on temperature and location of the selected word line relative to the drain side select transistors of the unselected NAND string, wherein the managing circuitry is configured to apply the unselect voltage to a control gate of the drain side select transistor of the unselected NAND string while the managing circuitry applies the programming voltage to the selected word line, the boosting voltage to the unselected word lines, and the voltage to the bit line associated with the unselected NAND string, wherein the unselect voltage cuts off the unselected NAND string from the bit line associated with the unselected NAND string. a semiconductor substrate having a major surface that extends in a horizontal plane; a plurality of word lines (WL0, WL1,...); a plurality of bit lines (BLA0-BLAn; BLB0-BLBn; BL0, BL1); a plurality of NAND strings (NSA0, NSA1,...; NSB0, NSB1,...; NS00, NS01, NS02, NS03, NS10, NS11, NS12) that extend in a vertical direction with respect to the horizontal plane, each of the NAND strings comprising a drain side select transistor (SGD0, SGD1...) coupled to a bit line of the plurality of bit lines, each of the NAND strings being associated with a group of the plurality of word lines, each of the NAND strings comprising a plurality of memory cells (MCn, MCn-1,..., MC0); and managing circuitry (110, 122, 124, 128, 132) in communication with the plurality of word lines, the plurality of bit lines, and the drain side select transistors of the plurality of NAND strings, wherein the managing circuitry is configured to apply a programming voltage (Vpgm) to a selected word line of the plurality of word lines that is connected to a memory cell on a selected NAND string and to a memory cell on an unselected NAND string (NS01, NS11) of the plurality of NAND strings, wherein the managing circuitry is configured to apply a boosting voltage to unselected word lines connected to memory cells on the unselected NAND string while the managing circuitry applies the programming voltage to the selected word line, wherein the managing circuitry is configured to apply a program enable voltage (V_Program Enable) to a selected bit line that is associated with the selected NAND string, wherein the managing circuitry is configured to apply a voltage (V_Program Enable or Vbl_Inhibit) to a bit line associated with the unselected NAND string, wherein the managing circuitry is configured to generate an unselect voltage (Vsdgu) that has a magnitude that depends on temperature and location of the selected word line relative to the drain side select transistors of the unselected NAND string, wherein the managing circuitry is configured to apply the unselect voltage to a control gate of the drain side select transistor of the unselected NAND string while the managing circuitry applies the programming voltage to the selected word line, the boosting voltage to the unselected word lines, and the voltage to the bit line associated with the unselected NAND string, wherein the unselect voltage cuts off the unselected NAND string from the bit line associated with the unselected NAND string.