An apparatus comprising: processing circuitry to perform data processing in response to instructions; at least one cache to store cached versions of data from a memory; and translation circuitry to translate a virtual page address into a physical page address of a physical page; wherein the translation circuitry comprises a plurality of translation entries, each translation entry corresponding to a virtual page address and identifying the corresponding physical page address for that virtual page address; wherein in response to a cache maintenance instruction specifying a given virtual page address identifying a given virtual page of a virtual address space, the processing circuitry triggers the at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines, wherein each of the one or more cache lines stores data having a physical address within a given physical page that corresponds to the given virtual page identified by the given virtual page address; wherein performing the cache maintenance operation includes only a single lookup of the translation circuitry to translate the given virtual page address to a physical page address of the given physical page; wherein the physical address of the data is the physical address in the memory at which the corresponding data is stored for which the data stored in the cache line is a cached version; and wherein the cache maintenance instruction specifies one of a plurality of virtual page sizes, and the processing circuitry is responsive to the cache maintenance instruction to trigger the at least one cache to perform the cache maintenance operation with the virtual page having the virtual page size specified by the cache maintenance instruction. processing circuitry to perform data processing in response to instructions; at least one cache to store cached versions of data from a memory; and translation circuitry to translate a virtual page address into a physical page address of a physical page; wherein the translation circuitry comprises a plurality of translation entries, each translation entry corresponding to a virtual page address and identifying the corresponding physical page address for that virtual page address; wherein in response to a cache maintenance instruction specifying a given virtual page address identifying a given virtual page of a virtual address space, the processing circuitry triggers the at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines, wherein each of the one or more cache lines stores data having a physical address within a given physical page that corresponds to the given virtual page identified by the given virtual page address; wherein performing the cache maintenance operation includes only a single lookup of the translation circuitry to translate the given virtual page address to a physical page address of the given physical page; wherein the physical address of the data is the physical address in the memory at which the corresponding data is stored for which the data stored in the cache line is a cached version; and wherein the cache maintenance instruction specifies one of a plurality of virtual page sizes, and the processing circuitry is responsive to the cache maintenance instruction to trigger the at least one cache to perform the cache maintenance operation with the virtual page having the virtual page size specified by the cache maintenance instruction.