An analog neuro memory system, comprising: a two-dimensional array comprising a plurality of vector-by-matrix multiplication arrays (2301a, 2301b, 2301c, 2301d, 2301e, 2301f) arranged into rows and columns, the plurality of vector-by-matrix multiplication arrays comprising three or more vector-by-matrix multiplication arrays comprising: a first vector-by-matrix multiplication array of memory cells arranged into rows and columns, the first vector-by-matrix multiplication array located in a first row and a first column of the two-dimensional array; a second vector-by-matrix multiplication array of memory cells arranged into rows and columns, the second vector-by-matrix multiplication array located in a second row and a second column of the two-dimensional array, the second row different than the first row and the second column different than the first column; a shared output block coupled to the first vector-by-matrix multiplication array and to the second vector-by-matrix multiplication array for generating a vector of output voltages in response to current received from a plurality of memory cells in the first vector-by-matrix multiplication array or the second vector-by-matrix multiplication array; a first activation block coupled to the first vector-by-matrix multiplication array for generating a vector of input currents in response to receiving a vector of input voltages and providing the vector of input currents to a plurality of memory cells in the first vector-by-matrix multiplication array; a second activation block coupled to the second vector-by-matrix multiplication array for generating a vector of input currents in response to receiving a vector of input voltages and providing the vector of input currents to a plurality of memory cells in the second vector-by-matrix multiplication array; and routing circuitry comprising a first multiplexor, a second multiplexor, and a third multiplexor for routing signals from the first vector-by-matrix multiplication array through the second multiplexor, the shared output block, the third multiplexor, and the first multiplexor to the second activation block coupled to the second vector-by-matrix multiplication array. a two-dimensional array comprising a plurality of vector-by-matrix multiplication arrays (2301a, 2301b, 2301c, 2301d, 2301e, 2301f) arranged into rows and columns, the plurality of vector-by-matrix multiplication arrays comprising three or more vector-by-matrix multiplication arrays comprising: a first vector-by-matrix multiplication array of memory cells arranged into rows and columns, the first vector-by-matrix multiplication array located in a first row and a first column of the two-dimensional array; a second vector-by-matrix multiplication array of memory cells arranged into rows and columns, the second vector-by-matrix multiplication array located in a second row and a second column of the two-dimensional array, the second row different than the first row and the second column different than the first column; a first vector-by-matrix multiplication array of memory cells arranged into rows and columns, the first vector-by-matrix multiplication array located in a first row and a first column of the two-dimensional array; a second vector-by-matrix multiplication array of memory cells arranged into rows and columns, the second vector-by-matrix multiplication array located in a second row and a second column of the two-dimensional array, the second row different than the first row and the second column different than the first column; a shared output block coupled to the first vector-by-matrix multiplication array and to the second vector-by-matrix multiplication array for generating a vector of output voltages in response to current received from a plurality of memory cells in the first vector-by-matrix multiplication array or the second vector-by-matrix multiplication array; a first activation block coupled to the first vector-by-matrix multiplication array for generating a vector of input currents in response to receiving a vector of input voltages and providing the vector of input currents to a plurality of memory cells in the first vector-by-matrix multiplication array; a second activation block coupled to the second vector-by-matrix multiplication array for generating a vector of input currents in response to receiving a vector of input voltages and providing the vector of input currents to a plurality of memory cells in the second vector-by-matrix multiplication array; and routing circuitry comprising a first multiplexor, a second multiplexor, and a third multiplexor for routing signals from the first vector-by-matrix multiplication array through the second multiplexor, the shared output block, the third multiplexor, and the first multiplexor to the second activation block coupled to the second vector-by-matrix multiplication array.