A semiconductor device comprising: a substrate; a channel layer disposed above the substrate, the channel layer being a group III nitride not containing Al; a barrier layer disposed above the channel layer, the barrier layer being a group III nitride containing Al; a gate electrode joined to the barrier layer; a recess obtainable by removing at least a portion of the barrier layer from a surface of a laminated semiconductor including the channel layer and the barrier layer; an ohmic electrode disposed in the recess, the ohmic electrode being in ohmic contact with a two-dimensional electron gas layer generated in the channel layer, and in a first direction perpendicular to a surface of the substrate, a first inclined surface of the barrier layer, the first inclined surface including a first position and being in contact with the ohmic electrode; characterized in that an Al composition ratio distribution of the barrier layer in the first direction has a maximum point at the first position, the semiconductor device comprises, in the first direction: a second inclined surface of the barrier layer, the second inclined surface intersecting the first inclined surface at a first intersection line on a lower side of the first inclined surface and being in contact with the ohmic electrode, an angle of the second inclined surface to the surface of the substrate is smaller than an angle of the first inclined surface to the surface of the substrate, a second position that is a position of the first intersection line in the first direction is lower than the first position and an extending direction of the gate electrode along its longest dimension in a plan view of the substrate is a <11-20> direction of a semiconductor crystal configuring the channel layer. a substrate; a channel layer disposed above the substrate, the channel layer being a group III nitride not containing Al; a barrier layer disposed above the channel layer, the barrier layer being a group III nitride containing Al; a gate electrode joined to the barrier layer; a recess obtainable by removing at least a portion of the barrier layer from a surface of a laminated semiconductor including the channel layer and the barrier layer; an ohmic electrode disposed in the recess, the ohmic electrode being in ohmic contact with a two-dimensional electron gas layer generated in the channel layer, and in a first direction perpendicular to a surface of the substrate, a first inclined surface of the barrier layer, the first inclined surface including a first position and being in contact with the ohmic electrode; characterized in that an Al composition ratio distribution of the barrier layer in the first direction has a maximum point at the first position, the semiconductor device comprises, in the first direction: a second inclined surface of the barrier layer, the second inclined surface intersecting the first inclined surface at a first intersection line on a lower side of the first inclined surface and being in contact with the ohmic electrode, an angle of the second inclined surface to the surface of the substrate is smaller than an angle of the first inclined surface to the surface of the substrate, a second position that is a position of the first intersection line in the first direction is lower than the first position and an extending direction of the gate electrode along its longest dimension in a plan view of the substrate is a <11-20> direction of a semiconductor crystal configuring the channel layer. a second inclined surface of the barrier layer, the second inclined surface intersecting the first inclined surface at a first intersection line on a lower side of the first inclined surface and being in contact with the ohmic electrode, an angle of the second inclined surface to the surface of the substrate is smaller than an angle of the first inclined surface to the surface of the substrate, a second position that is a position of the first intersection line in the first direction is lower than the first position and an extending direction of the gate electrode along its longest dimension in a plan view of the substrate is a <11-20> direction of a semiconductor crystal configuring the channel layer.