A level-shifting multiplexer, comprising: a first pull-down circuit coupled to a first node and having first and second inputs, wherein the first pull-down circuit is configured to select one of the first and second inputs based on one or more select signals, to pull down the first node if the first input is selected and driven to a first state, and to pull down the first node if the second input is selected and driven to a second state; a second pull-down circuit coupled to a second node and having third and fourth inputs, wherein the second pull-down circuit is configured to select one of the third and fourth inputs based on the one or more select signals, to pull down the second node if the third input is selected and driven to a third state, and to pull down the second node if the fourth input is selected and driven to a fourth state; a pull-up circuit configured to pull up the first node if the second node is pulled down by the second pull-down circuit, and to pull up the second node if the first node is pulled down by the first pull-down circuit, wherein the pull-up circuit comprises: a first transistor configured to pull up the first node if the second node is pulled down by the second pull-down circuit, wherein the first transistor has a gate coupled to the second node; and a second transistor configured to pull up the second node if the first node is pulled down by the first pull-down circuit, wherein the second transistor has a gate coupled to the first node; and a choke circuit configured to reduce current from a supply rail to the first transistor if the first input is selected and driven to the first state. a first pull-down circuit coupled to a first node and having first and second inputs, wherein the first pull-down circuit is configured to select one of the first and second inputs based on one or more select signals, to pull down the first node if the first input is selected and driven to a first state, and to pull down the first node if the second input is selected and driven to a second state; a second pull-down circuit coupled to a second node and having third and fourth inputs, wherein the second pull-down circuit is configured to select one of the third and fourth inputs based on the one or more select signals, to pull down the second node if the third input is selected and driven to a third state, and to pull down the second node if the fourth input is selected and driven to a fourth state; a pull-up circuit configured to pull up the first node if the second node is pulled down by the second pull-down circuit, and to pull up the second node if the first node is pulled down by the first pull-down circuit, wherein the pull-up circuit comprises: a first transistor configured to pull up the first node if the second node is pulled down by the second pull-down circuit, wherein the first transistor has a gate coupled to the second node; and a second transistor configured to pull up the second node if the first node is pulled down by the first pull-down circuit, wherein the second transistor has a gate coupled to the first node; and a first transistor configured to pull up the first node if the second node is pulled down by the second pull-down circuit, wherein the first transistor has a gate coupled to the second node; and a second transistor configured to pull up the second node if the first node is pulled down by the first pull-down circuit, wherein the second transistor has a gate coupled to the first node; and a choke circuit configured to reduce current from a supply rail to the first transistor if the first input is selected and driven to the first state.