A pixel array of a liquid crystal display, the pixel array comprising a pair of pixels, the pair of pixels comprising: a first pixel including a first pixel electrode (UPXL1) chargeable to a first data voltage, an upper common electrode (UCOM) which is positioned opposite the first pixel electrode (UPXL1) and arranged to form an electric field, a lower common electrode (DCOM) arranged to apply a common voltage to the upper common electrode (UCOM), and a first storage capacitor for holding the first data voltage during a predetermined period; and a second pixel including a second pixel electrode (UPXL2) chargeable to a second data voltage, the upper common electrode (UCOM) which is positioned opposite the second pixel electrode (UPXL2) and arranged to form the electric field, the lower common electrode (DCOM) arranged to apply the common voltage to the upper common electrode (UCOM), and a second storage capacitor for holding the second data voltage during a predetermined period, wherein the first and second storage capacitors are located in an area between the first and second pixels, which are positioned adjacent to each other in a direction parallel to gate lines, wherein gate lines and data lines for driving the first and second pixels are not located in the area between the first and second pixels, wherein the lower common electrode (DCOM) is formed in parallel with the gate lines, wherein the gate lines and data lines are perpendicular to each other, wherein the first storage capacitor includes a first branch pixel electrode (BRPXL1) branching out from the first pixel electrode (UPXL1) as one electrode, and the second storage capacitor includes a second branch pixel electrode (BRPXL2) branching out from the second pixel electrode (UPXL2) as one electrode, and wherein at least one of the upper common electrode (UCOM) and the lower common electrode (DCOM) is divided into two or more electrode patterns in the area between the first and second pixels and is configured to adjust capacitances of the first and second storage capacitors. a first pixel including a first pixel electrode (UPXL1) chargeable to a first data voltage, an upper common electrode (UCOM) which is positioned opposite the first pixel electrode (UPXL1) and arranged to form an electric field, a lower common electrode (DCOM) arranged to apply a common voltage to the upper common electrode (UCOM), and a first storage capacitor for holding the first data voltage during a predetermined period; and a second pixel including a second pixel electrode (UPXL2) chargeable to a second data voltage, the upper common electrode (UCOM) which is positioned opposite the second pixel electrode (UPXL2) and arranged to form the electric field, the lower common electrode (DCOM) arranged to apply the common voltage to the upper common electrode (UCOM), and a second storage capacitor for holding the second data voltage during a predetermined period, wherein the first and second storage capacitors are located in an area between the first and second pixels, which are positioned adjacent to each other in a direction parallel to gate lines, wherein gate lines and data lines for driving the first and second pixels are not located in the area between the first and second pixels, wherein the lower common electrode (DCOM) is formed in parallel with the gate lines, wherein the gate lines and data lines are perpendicular to each other, wherein the first storage capacitor includes a first branch pixel electrode (BRPXL1) branching out from the first pixel electrode (UPXL1) as one electrode, and the second storage capacitor includes a second branch pixel electrode (BRPXL2) branching out from the second pixel electrode (UPXL2) as one electrode, and wherein at least one of the upper common electrode (UCOM) and the lower common electrode (DCOM) is divided into two or more electrode patterns in the area between the first and second pixels and is configured to adjust capacitances of the first and second storage capacitors.