A phase-change memory device, comprising: - a current generator configured to output a reference current (i ref); - a memory array including a plurality of memory cells of phase-change material programmable in SET and RESET resistance state and configured to output, during a reading operation of a memory cell of said plurality of memory cells, a reading current (i read) which is indicative of a SET or a RESET resistance state of the memory cell being read; and - a reading stage, coupled to the current generator and to the memory array, configured to: receive at input the reference current (i ref) and the reading current (i read), compare the reading current (i read) with the reference current (iref), and output a result of such comparison which is indicative of a logic datum stored in the memory cell being read, wherein the current generator comprises a reference array including a plurality of reference cells of a phase-change material, wherein each reference cell is programmed in SET resistance state, the phase-change memory device further comprising: - a decoder for addressing each reference cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; the phase-changed memory device being characterized in that it further comprises: - a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current (i ref) to be lower than said mean value. - a current generator configured to output a reference current (i ref); - a memory array including a plurality of memory cells of phase-change material programmable in SET and RESET resistance state and configured to output, during a reading operation of a memory cell of said plurality of memory cells, a reading current (i read) which is indicative of a SET or a RESET resistance state of the memory cell being read; and - a reading stage, coupled to the current generator and to the memory array, configured to: receive at input the reference current (i ref) and the reading current (i read), compare the reading current (i read) with the reference current (iref), and output a result of such comparison which is indicative of a logic datum stored in the memory cell being read, wherein the current generator comprises a reference array including a plurality of reference cells of a phase-change material, wherein each reference cell is programmed in SET resistance state, the phase-change memory device further comprising: - a decoder for addressing each reference cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; the phase-changed memory device being characterized in that it further comprises: - a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current (i ref) to be lower than said mean value. wherein the current generator comprises a reference array including a plurality of reference cells of a phase-change material, wherein each reference cell is programmed in SET resistance state, the phase-change memory device further comprising: - a decoder for addressing each reference cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; the phase-changed memory device being characterized in that it further comprises: - a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current (i ref) to be lower than said mean value. - a decoder for addressing each reference cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; the phase-changed memory device being characterized in that it further comprises: - a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current (i ref) to be lower than said mean value. - a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current (i ref) to be lower than said mean value.