A multi-processor unified memory management system, comprising: a first programmable processor system configured to communicate via an inter-chip link with a second programmable processor system, wherein the first programmable processor system comprises: a first inter-chip memory management module configured to: analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and the second programmable processor system configured to communicate via the inter-chip link with the first programmable processor system, wherein the second programmable processor system comprises: a second inter-chip memory management module configured to: analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and characterized in that: the first inter-chip memory management module and the second inter-chip memory management module are configured to use a common flat memory map. a first programmable processor system configured to communicate via an inter-chip link with a second programmable processor system, wherein the first programmable processor system comprises: a first inter-chip memory management module configured to: analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and a first inter-chip memory management module configured to: analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and the second programmable processor system configured to communicate via the inter-chip link with the first programmable processor system, wherein the second programmable processor system comprises: a second inter-chip memory management module configured to: analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and characterized in that: the first inter-chip memory management module and the second inter-chip memory management module are configured to use a common flat memory map. a second inter-chip memory management module configured to: analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and characterized in that: the first inter-chip memory management module and the second inter-chip memory management module are configured to use a common flat memory map. analyze memory access transactions; translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and characterized in that: the first inter-chip memory management module and the second inter-chip memory management module are configured to use a common flat memory map.