A integrated microelectronic device structure, comprising: a substrate; a first fin comprising silicon and including a first region over a second region; a first gate stack adjacent to a sidewall surface of the first region, wherein the first gate stack includes a gate dielectric and a gate electrode; a first source and a drain on opposite sides of the first gate stack; a first dielectric layer adjacent to a sidewall surface of the second region, wherein the first dielectric layer is a phosphorus-doped silicate glass, PSG, which comprises phosphorus as an impurity that is also present within the second region; an impurity source film over the first dielectric layer; an isolation dielectric material adjacent to the impurity source film; a second fin comprising silicon, wherein: the second fin includes an upper region and a lower region; a second gate stack, wherein said second gate stack includes a gate dielectric and a gate electrode and is adjacent to a sidewall surface of the upper region; and a second source and drain are coupled to the upper region; a second dielectric layer adjacent to a sidewall surface of the lower region, wherein the second dielectric layer is a boron-doped silicate glass, BSG, which comprises boron as an impurity that is also present within the lower region; and wherein the isolation dielectric material is separating the first dielectric layer from the second dielectric layer, wherein the isolation dielectric material forms a stack of layers, wherein the stack of layers further comprises a silicon nitride layer between the first and second dielectric layers. a substrate; a first fin comprising silicon and including a first region over a second region; a first gate stack adjacent to a sidewall surface of the first region, wherein the first gate stack includes a gate dielectric and a gate electrode; a first source and a drain on opposite sides of the first gate stack; a first dielectric layer adjacent to a sidewall surface of the second region, wherein the first dielectric layer is a phosphorus-doped silicate glass, PSG, which comprises phosphorus as an impurity that is also present within the second region; an impurity source film over the first dielectric layer; an isolation dielectric material adjacent to the impurity source film; a second fin comprising silicon, wherein: the second fin includes an upper region and a lower region; a second gate stack, wherein said second gate stack includes a gate dielectric and a gate electrode and is adjacent to a sidewall surface of the upper region; and a second source and drain are coupled to the upper region; a second dielectric layer adjacent to a sidewall surface of the lower region, wherein the second dielectric layer is a boron-doped silicate glass, BSG, which comprises boron as an impurity that is also present within the lower region; and wherein the isolation dielectric material is separating the first dielectric layer from the second dielectric layer, wherein the isolation dielectric material forms a stack of layers, wherein the stack of layers further comprises a silicon nitride layer between the first and second dielectric layers. the second fin includes an upper region and a lower region; a second gate stack, wherein said second gate stack includes a gate dielectric and a gate electrode and is adjacent to a sidewall surface of the upper region; and a second source and drain are coupled to the upper region; a second dielectric layer adjacent to a sidewall surface of the lower region, wherein the second dielectric layer is a boron-doped silicate glass, BSG, which comprises boron as an impurity that is also present within the lower region; and wherein the isolation dielectric material is separating the first dielectric layer from the second dielectric layer, wherein the isolation dielectric material forms a stack of layers, wherein the stack of layers further comprises a silicon nitride layer between the first and second dielectric layers.