An integrated circuit comprising: a processor comprising: a first memory that stores a first set of instructions; and a second memory that stores the second set of microinstructions (115A, 115B, 115C, 115D), wherein an instruction in the first set of instructions is used as a pointer to a corresponding microinstruction in the second set of instructions; each of the microinstructions (115A, 115B, 115C, 115D) in said second set comprising a number of sub-instructions; characterized by the processor further comprising: a plurality of delay lines having registers (121A, 121B, 121C, 121D) coupled to the second memory, wherein each register (121A, 121B, 121C, 121D) of a respective one of the delay lines is configured to provide random access for writing sub-instruction or data and to act as a circular buffer when reading sub-instructions or data from the respective register (121A, 121B, 121C, 121D); and a plurality of functional units (124A, 124B, 124C, 124D), each of the functional units (124A, 124B, 124C, 124D) being coupled to one of the delay lines and being configured to read sub-instructions from the register (121A, 121B, 121C, 121D) of said one delay line; wherein the sub-instructions of one or more of the microinstructions in the second memory contain an instruction field (115A1) or data field, and cycle offset field (115A2), wherein the cycle offset field (115A2) indicates the address at which the sub-instruction or data in the instruction field or data field (115A1), respectively, is to be written into one of the registers (121A, 121B, 121C, 121D). a processor comprising: a first memory that stores a first set of instructions; and a second memory that stores the second set of microinstructions (115A, 115B, 115C, 115D), wherein an instruction in the first set of instructions is used as a pointer to a corresponding microinstruction in the second set of instructions; a first memory that stores a first set of instructions; and a second memory that stores the second set of microinstructions (115A, 115B, 115C, 115D), wherein an instruction in the first set of instructions is used as a pointer to a corresponding microinstruction in the second set of instructions; each of the microinstructions (115A, 115B, 115C, 115D) in said second set comprising a number of sub-instructions; characterized by the processor further comprising: a plurality of delay lines having registers (121A, 121B, 121C, 121D) coupled to the second memory, wherein each register (121A, 121B, 121C, 121D) of a respective one of the delay lines is configured to provide random access for writing sub-instruction or data and to act as a circular buffer when reading sub-instructions or data from the respective register (121A, 121B, 121C, 121D); and a plurality of functional units (124A, 124B, 124C, 124D), each of the functional units (124A, 124B, 124C, 124D) being coupled to one of the delay lines and being configured to read sub-instructions from the register (121A, 121B, 121C, 121D) of said one delay line; a plurality of delay lines having registers (121A, 121B, 121C, 121D) coupled to the second memory, wherein each register (121A, 121B, 121C, 121D) of a respective one of the delay lines is configured to provide random access for writing sub-instruction or data and to act as a circular buffer when reading sub-instructions or data from the respective register (121A, 121B, 121C, 121D); and a plurality of functional units (124A, 124B, 124C, 124D), each of the functional units (124A, 124B, 124C, 124D) being coupled to one of the delay lines and being configured to read sub-instructions from the register (121A, 121B, 121C, 121D) of said one delay line; wherein the sub-instructions of one or more of the microinstructions in the second memory contain an instruction field (115A1) or data field, and cycle offset field (115A2), wherein the cycle offset field (115A2) indicates the address at which the sub-instruction or data in the instruction field or data field (115A1), respectively, is to be written into one of the registers (121A, 121B, 121C, 121D).