A non-volatile memory device, comprising: a memory array comprising a plurality of memory groups; a read circuit and a write circuit; wherein the plurality of memory groups each include a plurality of memory cells associated with a word line in which digital data is recorded according to a magnitude of a resistance value, the plurality of memory groups each including at least one data cell and at least one dummy cell which are associated with each other, the plurality of memory cells being variable resistance memory cells; the read circuit performs, in parallel, a read operation on each of the plurality of memory cells included in each of the plurality of memory groups, the plurality of memory groups include an information area and a dummy area; wherein helper data are recorded in the at least one data cell of the information area of the first memory group and parity data for correcting an error of the helper data are recorded in the at least one dummy cell of the dummy area the first memory group; wherein physically unclonable function, PUF, data are recorded in the at least one data cell of the information area of the second memory group, the PUF data being device-specific data in which variations in physical characteristics are used; wherein dummy data are recorded in the at least one dummy cell of the dummy area the second memory group, the dummy data being for reducing a correlation between a side-channel leakage and the PUF data, the side-channel leakage being generated when the read operation is performed by the read circuit, the PUF data are generated from variations in one resistance state out of a high resistance state that is state "0" and a low resistance state that is state "1", and the dummy data are data in a same resistance state as a resistance state of random number data generated by a random number generator or of the one resistance state of the PUF data; wherein the helper data are recorded in any of the high or low resistance states and are used to perform an error correction of the PUF data. a memory array comprising a plurality of memory groups; a read circuit and a write circuit; wherein the plurality of memory groups each include a plurality of memory cells associated with a word line in which digital data is recorded according to a magnitude of a resistance value, the plurality of memory groups each including at least one data cell and at least one dummy cell which are associated with each other, the plurality of memory cells being variable resistance memory cells; the read circuit performs, in parallel, a read operation on each of the plurality of memory cells included in each of the plurality of memory groups, the plurality of memory groups include an information area and a dummy area; wherein helper data are recorded in the at least one data cell of the information area of the first memory group and parity data for correcting an error of the helper data are recorded in the at least one dummy cell of the dummy area the first memory group; wherein physically unclonable function, PUF, data are recorded in the at least one data cell of the information area of the second memory group, the PUF data being device-specific data in which variations in physical characteristics are used; wherein dummy data are recorded in the at least one dummy cell of the dummy area the second memory group, the dummy data being for reducing a correlation between a side-channel leakage and the PUF data, the side-channel leakage being generated when the read operation is performed by the read circuit, the PUF data are generated from variations in one resistance state out of a high resistance state that is state "0" and a low resistance state that is state "1", and the dummy data are data in a same resistance state as a resistance state of random number data generated by a random number generator or of the one resistance state of the PUF data; wherein the helper data are recorded in any of the high or low resistance states and are used to perform an error correction of the PUF data.