A method to maintain cache coherency within a multi-core processor comprising multiple processor cores associated with multiple caches, the method comprising: identifying a first cache entry to be evicted from a first cache, the first cache entry comprising a block of data and a first tag indicating an owned state; in response to identifying the first cache entry to be evicted from the first cache, broadcasting an owner eviction message for the first cache entry from the first cache on an interconnect bus that interconnects the multiple processor cores to an off-chip memory through the multiple caches, the interconnect bus interconnecting the multiple caches, and the owner eviction message indicating a pending eviction of the first cache entry; detecting the broadcasted owner eviction message for the first cache entry from the first cache with a second cache by snooping the broadcasted owner eviction message off the interconnect bus; in response to the second cache detecting the broadcasted owner eviction message for the first cache entry from the first cache and identifying in the second cache a second cache entry comprising the block of data and a second tag indicating a shared state, broadcasting an ownership acceptance message for the second cache entry from the second cache on the interconnect bus; detecting the broadcasted ownership acceptance message for the second cache entry from the second cache with the first cache; and in response to the first cache detecting the broadcasted ownership acceptance message for the second cache entry from the second cache, transforming the second tag in the second cache entry from the shared state to the owned state. identifying a first cache entry to be evicted from a first cache, the first cache entry comprising a block of data and a first tag indicating an owned state; in response to identifying the first cache entry to be evicted from the first cache, broadcasting an owner eviction message for the first cache entry from the first cache on an interconnect bus that interconnects the multiple processor cores to an off-chip memory through the multiple caches, the interconnect bus interconnecting the multiple caches, and the owner eviction message indicating a pending eviction of the first cache entry; detecting the broadcasted owner eviction message for the first cache entry from the first cache with a second cache by snooping the broadcasted owner eviction message off the interconnect bus; in response to the second cache detecting the broadcasted owner eviction message for the first cache entry from the first cache and identifying in the second cache a second cache entry comprising the block of data and a second tag indicating a shared state, broadcasting an ownership acceptance message for the second cache entry from the second cache on the interconnect bus; detecting the broadcasted ownership acceptance message for the second cache entry from the second cache with the first cache; and in response to the first cache detecting the broadcasted ownership acceptance message for the second cache entry from the second cache, transforming the second tag in the second cache entry from the shared state to the owned state.