A microprocessor including an instruction translator to translate instructions of an architectural instruction set into microcode instructions, the microprocessor characterized in that it comprises: a plurality of memories (104,108), configured to hold microcode instructions, wherein at least one memory of the plurality of memories is configured to hold microcode instructions wherein at least a portion of the microcode instructions are compressed; a decompression unit, configured to decompress the compressed microcode instructions after being fetched from the at least one memory of the plurality of memories and before being executed; wherein the at least one memory of the plurality of memories are configured to provide words in response to a microcode fetch address input, wherein the words include the microcode instructions at least a portion of which are compressed; wherein the decompression unit is configured to determine whether the words fetched from the at least one memory of the plurality of memories include a compressed microcode instruction or a first portion of an uncompressed microcode instruction having a second portion included in an adjacent word; wherein the decompression unit is configured to decompress the compressed microcode instructions into uncompressed microcode instructions or to join the first and second portions of the uncompressed microcode instructions into uncompressed microcode instructions; wherein to determine whether the words fetched from the at least one memory of the plurality of memories include a compressed microcode instruction or a first portion of an uncompressed microcode instruction, the decompression unit is configured to determine whether or not a predetermined portion of the microcode words is a predetermined value; wherein each of the compressed microcode words is N bits wide; and wherein to decompress the compressed microcode instructions into uncompressed microcode instructions, the decompression unit is configured to decompress the N-bit wide microcode word to generate an M-bit wide microcode word, wherein M and N are integers greater than zero, and M is greater than N; wherein to decompress the N-bit wide microcode word to generate an M-bit wide microcode word, the decompression unit is configured to: output unique L-bit values in response to unique values included in a predetermined K bits of the N-bit wide microcode word according to a predetermined mapping, wherein K is an integer greater than zero and less than N and L is an integer greater than zero and less than M; and pass through the remaining (N-K) bits of the N-bit wide microcode word as the remaining (M-L) bits of the M-bit wide microcode word; wherein the passed through (N-K) bits comprise an immediate value field of the compressed microcode instruction. a plurality of memories (104,108), configured to hold microcode instructions, wherein at least one memory of the plurality of memories is configured to hold microcode instructions wherein at least a portion of the microcode instructions are compressed; a decompression unit, configured to decompress the compressed microcode instructions after being fetched from the at least one memory of the plurality of memories and before being executed; wherein the at least one memory of the plurality of memories are configured to provide words in response to a microcode fetch address input, wherein the words include the microcode instructions at least a portion of which are compressed; wherein the decompression unit is configured to determine whether the words fetched from the at least one memory of the plurality of memories include a compressed microcode instruction or a first portion of an uncompressed microcode instruction having a second portion included in an adjacent word; wherein the decompression unit is configured to decompress the compressed microcode instructions into uncompressed microcode instructions or to join the first and second portions of the uncompressed microcode instructions into uncompressed microcode instructions; wherein to determine whether the words fetched from the at least one memory of the plurality of memories include a compressed microcode instruction or a first portion of an uncompressed microcode instruction, the decompression unit is configured to determine whether or not a predetermined portion of the microcode words is a predetermined value; wherein each of the compressed microcode words is N bits wide; and wherein to decompress the compressed microcode instructions into uncompressed microcode instructions, the decompression unit is configured to decompress the N-bit wide microcode word to generate an M-bit wide microcode word, wherein M and N are integers greater than zero, and M is greater than N; wherein to decompress the N-bit wide microcode word to generate an M-bit wide microcode word, the decompression unit is configured to: output unique L-bit values in response to unique values included in a predetermined K bits of the N-bit wide microcode word according to a predetermined mapping, wherein K is an integer greater than zero and less than N and L is an integer greater than zero and less than M; and pass through the remaining (N-K) bits of the N-bit wide microcode word as the remaining (M-L) bits of the M-bit wide microcode word; wherein the passed through (N-K) bits comprise an immediate value field of the compressed microcode instruction.