A high integrity logic circuit comprising: a. a plurality of parallel cores (215, 225), wherein said parallel cores are used to implement critical functions of said logic circuit, b. wherein said parallel cores (215, 225) are redundant or diverse, c. a redundancy checker, wherein said redundancy checker is used to: i. verify whether a plurality of values internal to a first parallel core between an input and an output of the first parallel core, match a plurality of values internal to a second parallel core between an input and an output of the second parallel core, and ii. activate said logic circuit into a failsafe state according to a predetermined criterion, d. wherein said logic circuit is interfaced to a plurality of inputs and a plurality of outputs, e. wherein said logic circuit performs a mission related to said inputs and said outputs, wherein said mission is a safety critical function, f. wherein communication between said logic circuit and said inputs and said outputs is protected by at least one item selected from the group consisting of: i. redundancy, ii. cyclic redundancy check, iii. toggle test on said inputs, and iv. read back on said outputs, g. a built in self test (BIST 214, BIST 224), wherein said built in self test is used to expose unannounced failures in any said parallel core, h. wherein said built in self test (BIST 214, BIST 224) is performed periodically or continually while said logic circuit performs said mission, i. wherein said critical functions (212, 222) of said logic circuit are implemented in at least one logic device (215, 225), and j. wherein said at least one logic device (215, 125) is implemented free of the use of executable software. a. a plurality of parallel cores (215, 225), wherein said parallel cores are used to implement critical functions of said logic circuit, b. wherein said parallel cores (215, 225) are redundant or diverse, c. a redundancy checker, wherein said redundancy checker is used to: i. verify whether a plurality of values internal to a first parallel core between an input and an output of the first parallel core, match a plurality of values internal to a second parallel core between an input and an output of the second parallel core, and ii. activate said logic circuit into a failsafe state according to a predetermined criterion, i. verify whether a plurality of values internal to a first parallel core between an input and an output of the first parallel core, match a plurality of values internal to a second parallel core between an input and an output of the second parallel core, and ii. activate said logic circuit into a failsafe state according to a predetermined criterion, d. wherein said logic circuit is interfaced to a plurality of inputs and a plurality of outputs, e. wherein said logic circuit performs a mission related to said inputs and said outputs, wherein said mission is a safety critical function, f. wherein communication between said logic circuit and said inputs and said outputs is protected by at least one item selected from the group consisting of: i. redundancy, ii. cyclic redundancy check, iii. toggle test on said inputs, and iv. read back on said outputs, i. redundancy, ii. cyclic redundancy check, iii. toggle test on said inputs, and iv. read back on said outputs, g. a built in self test (BIST 214, BIST 224), wherein said built in self test is used to expose unannounced failures in any said parallel core, h. wherein said built in self test (BIST 214, BIST 224) is performed periodically or continually while said logic circuit performs said mission, i. wherein said critical functions (212, 222) of said logic circuit are implemented in at least one logic device (215, 225), and j. wherein said at least one logic device (215, 125) is implemented free of the use of executable software.