A computing system, comprising: a translator unit arranged to convert a subject code into a target code, the subject code comprising a reference to at least one subject memory page having associated subject page access permission attributes; a target processor unit arranged to execute the target code; a target memory associated with the target processor unit and including a page descriptor store and plurality of memory locations corresponding to the subject memory pages, wherein the page descriptor store comprises access permission information of each of the memory locations in the plurality of memory locations, and wherein there is a direct mapping between each of the memory locations and the corresponding entries in the page descriptor store; wherein the access permission information in the page descriptor store for each target memory location within plurality of memory locations is provided in the address bits of each target memory location within plurality of memory locations; and wherein the translator unit is arranged to set up, in the target memory, a guard representation of the at least one subject memory page, said guard representation resident in an address space in the target memory that is identifiable by the target processor unit as inaccessible, wherein the offset of each guard representation is determined according to access permission information for each corresponding memory location; wherein the translator unit is arranged to allow an attempt to access a first target memory location within the plurality of memory locations to proceed without an interruption in control flow, if the attempted access is within the scope of the subject page access permission attributes for the associated subject memory page; and wherein the translator unit is arranged to detect an attempt to access a second target memory location outside the scope of the corresponding subject page access permission information by attempting to access a corresponding guard representation to generate a target segmentation fault, wherein the corresponding guard representation is offset from the first target memory location determined according to the access permission information for the second target memory location and to pass on page protection fault information to an exception handling unit. a translator unit arranged to convert a subject code into a target code, the subject code comprising a reference to at least one subject memory page having associated subject page access permission attributes; a target processor unit arranged to execute the target code; a target memory associated with the target processor unit and including a page descriptor store and plurality of memory locations corresponding to the subject memory pages, wherein the page descriptor store comprises access permission information of each of the memory locations in the plurality of memory locations, and wherein there is a direct mapping between each of the memory locations and the corresponding entries in the page descriptor store; wherein the access permission information in the page descriptor store for each target memory location within plurality of memory locations is provided in the address bits of each target memory location within plurality of memory locations; and wherein the translator unit is arranged to set up, in the target memory, a guard representation of the at least one subject memory page, said guard representation resident in an address space in the target memory that is identifiable by the target processor unit as inaccessible, wherein the offset of each guard representation is determined according to access permission information for each corresponding memory location;