A circuit for use in a processor, the circuit comprising: an input arranged to receive a set of N input bit-strings each comprising a respective coordinate of a set of N coordinates defining a point in N dimensions, where N ≥ 2, each input bit-string comprising at least a first portion wherein the first portions are the same fixed number of bits in size as one another, wherein within each input bit-string each bit has a corresponding bit position from least to most significant within the bit-string, CHARACTERIZED IN THAT the circuit is capable of accommodating different size coordinates whereby in one or more of the input bit-strings the respective coordinate occupies only some of the bit positions with actual coordinate data representing the respective coordinate, the coordinate data being located in the least significant bit positions while any non-data bits not representing the respective coordinate are located in the most significant bit positions; interleaving circuitry arranged to produce an interleaved bit-string from the input bit-strings, in which the bits, including non-data bits, are grouped into groups of bits originating from the same bit position per group; and a demultiplexer operable to demultiplex the interleaved bit-string into n=1... N demultiplexed bit-strings (545i, 545ii, 545iii) and send each to a respective n-coordinate channel (551, 552, 553), the nth demultiplexed bit-string comprising: a respective part of the interleaved bit-string in which there are n coordinate data bits and N-n non-data bits per group, and all the other groups filled with null bits, unshifted relative to the respective part; wherein each but the N-coordinate channel comprises bit packing circuitry (510, 508) arranged to pack down the respective demultiplexed bit-string into a respective packed bit-string by removing the non-data bits from said respective part, and removing the same number of bits per group from the null bits; and wherein the circuit further comprises shift-and-combine circuitry, arranged to shift the packed bit-strings to align them relative to one another according to the corresponding bit positions, and to combine the shifted bit-strings, thereby producing a combined output bit-string. an input arranged to receive a set of N input bit-strings each comprising a respective coordinate of a set of N coordinates defining a point in N dimensions, where N ≥ 2, each input bit-string comprising at least a first portion wherein the first portions are the same fixed number of bits in size as one another, wherein within each input bit-string each bit has a corresponding bit position from least to most significant within the bit-string, CHARACTERIZED IN THAT the circuit is capable of accommodating different size coordinates whereby in one or more of the input bit-strings the respective coordinate occupies only some of the bit positions with actual coordinate data representing the respective coordinate, the coordinate data being located in the least significant bit positions while any non-data bits not representing the respective coordinate are located in the most significant bit positions; interleaving circuitry arranged to produce an interleaved bit-string from the input bit-strings, in which the bits, including non-data bits, are grouped into groups of bits originating from the same bit position per group; and a demultiplexer operable to demultiplex the interleaved bit-string into n=1... N demultiplexed bit-strings (545i, 545ii, 545iii) and send each to a respective n-coordinate channel (551, 552, 553), the nth demultiplexed bit-string comprising: a respective part of the interleaved bit-string in which there are n coordinate data bits and N-n non-data bits per group, and all the other groups filled with null bits, unshifted relative to the respective part; wherein each but the N-coordinate channel comprises bit packing circuitry (510, 508) arranged to pack down the respective demultiplexed bit-string into a respective packed bit-string by removing the non-data bits from said respective part, and removing the same number of bits per group from the null bits; and wherein the circuit further comprises shift-and-combine circuitry, arranged to shift the packed bit-strings to align them relative to one another according to the corresponding bit positions, and to combine the shifted bit-strings, thereby producing a combined output bit-string.