A system, comprising: a plurality of processors, each comprising a plurality of processor ports; and a plurality of configurable communication elements coupled to the plurality of processors in an interspersed fashion, wherein each configurable communication element comprises: a plurality of communication ports; a routing engine coupled the plurality of communication ports; a plurality of memorie, wherein each memory is coupled to a subset of processors; a plurality of direct memory access, DMA, engines, wherein each DMA engine of the plurality of DMA engines is coupled to a respective one of the plurality of communication ports, and wherein each DMA engine is configured to: transfer data between a subset of the plurality of memories, and the respective one of the communication ports; and process the transferred data; wherein each subset of one or more subsets of the plurality of DMA engines is configured to operate on a common portion of a memory of the plurality of memories to implement one of a plurality of first in first out FIFO, puffers; a DMA controller configured to: control the operation of one or more of the plurality of DMA engines; and control one of the one or more subsets of the plurality of DMA engines; wherein to control the operation of one or more of the plurality of DMA engines, the DMA controller is further configured to allow multiple DMA engines to read from a given FIFO buffer while another DMA engine is writing to the given FIFO buffer, thereby splitting a single input data stream into multiple output data streams, or the reverse. a plurality of processors, each comprising a plurality of processor ports; and a plurality of configurable communication elements coupled to the plurality of processors in an interspersed fashion, wherein each configurable communication element comprises: a plurality of communication ports; a routing engine coupled the plurality of communication ports; a plurality of memorie, wherein each memory is coupled to a subset of processors; a plurality of direct memory access, DMA, engines, wherein each DMA engine of the plurality of DMA engines is coupled to a respective one of the plurality of communication ports, and wherein each DMA engine is configured to: transfer data between a subset of the plurality of memories, and the respective one of the communication ports; and process the transferred data; wherein each subset of one or more subsets of the plurality of DMA engines is configured to operate on a common portion of a memory of the plurality of memories to implement one of a plurality of first in first out FIFO, puffers; a DMA controller configured to: control the operation of one or more of the plurality of DMA engines; and control one of the one or more subsets of the plurality of DMA engines; a plurality of communication ports; a routing engine coupled the plurality of communication ports; a plurality of memorie, wherein each memory is coupled to a subset of processors; a plurality of direct memory access, DMA, engines, wherein each DMA engine of the plurality of DMA engines is coupled to a respective one of the plurality of communication ports, and wherein each DMA engine is configured to: transfer data between a subset of the plurality of memories, and the respective one of the communication ports; and process the transferred data; transfer data between a subset of the plurality of memories, and the respective one of the communication ports; and process the transferred data; wherein each subset of one or more subsets of the plurality of DMA engines is configured to operate on a common portion of a memory of the plurality of memories to implement one of a plurality of first in first out FIFO, puffers; a DMA controller configured to: control the operation of one or more of the plurality of DMA engines; and control one of the one or more subsets of the plurality of DMA engines; control the operation of one or more of the plurality of DMA engines; and control one of the one or more subsets of the plurality of DMA engines;