A processor (100, 200, 300, 400, 500) configured to operate in multiple operating modes, the processor comprising: a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; a third mode resource storage circuitry configured to store third mode resources when the processor is operating in a third mode; a fourth mode resource storage circuitry configured to store fourth mode resources when the processor is operating in a fourth mode, wherein the resource mapping circuitry is configured to provide the third and fourth mode resources to the processor operating in the first mode; an access control interface communicatively coupled to the resource mapping circuitry, the second mode resource storage circuitry, the third mode resource storage circuitry, and the fourth mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry, the third mode resource storage circuitry, and the fourth mode resource storage circuitry; and an instruction execution circuitry configured to: execute an instruction to access the first mode resources when the processor is operating in the first mode, execute an instruction to access the second mode resources when the processor is operating in the second mode, execute an instruction to access the resource mapping circuitry when the processor is operating in the first mode so that the second mode resources in the second mode resource storage circuitry are accessed via the access control interface, execute an instruction to access the third mode resources when the processor is operating in the third mode, and execute an instruction to access the fourth mode resources when the processor is operating in the fourth mode. a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; a third mode resource storage circuitry configured to store third mode resources when the processor is operating in a third mode; a fourth mode resource storage circuitry configured to store fourth mode resources when the processor is operating in a fourth mode, wherein the resource mapping circuitry is configured to provide the third and fourth mode resources to the processor operating in the first mode; an access control interface communicatively coupled to the resource mapping circuitry, the second mode resource storage circuitry, the third mode resource storage circuitry, and the fourth mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry, the third mode resource storage circuitry, and the fourth mode resource storage circuitry; and an instruction execution circuitry configured to: execute an instruction to access the first mode resources when the processor is operating in the first mode, execute an instruction to access the second mode resources when the processor is operating in the second mode, execute an instruction to access the resource mapping circuitry when the processor is operating in the first mode so that the second mode resources in the second mode resource storage circuitry are accessed via the access control interface, execute an instruction to access the third mode resources when the processor is operating in the third mode, and execute an instruction to access the fourth mode resources when the processor is operating in the fourth mode. execute an instruction to access the first mode resources when the processor is operating in the first mode, execute an instruction to access the second mode resources when the processor is operating in the second mode, execute an instruction to access the resource mapping circuitry when the processor is operating in the first mode so that the second mode resources in the second mode resource storage circuitry are accessed via the access control interface, execute an instruction to access the third mode resources when the processor is operating in the third mode, and execute an instruction to access the fourth mode resources when the processor is operating in the fourth mode. execute an instruction to access the third mode resources when the processor is operating in the third mode, and execute an instruction to access the fourth mode resources when the processor is operating in the fourth mode.