A method for accessing an extended memory of a computer system including a processor system and an extended memory system, the extended memory system comprising an extended memory controller and the extended memory, the method comprising: receiving (510; 710; 810), by the extended memory controller, a first memory access request from the processor system, wherein the first memory access request comprises a first access address; determining, by the extended memory controller, a physical address of the to-be-accessed data according to the first access address; sending (550; 730; 830; 910), by the extended memory controller to the extended memory, a read request for to-be-accessed data in the extended memory, wherein the read request comprises the physical address of the to-be-accessed data; reading, by the extended memory controller, the to-be-accessed data into a data buffer of the extended memory controller; receiving (530; 910), by the extended memory controller from the processor system, a second memory access request comprising a second access address, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data; and sending, by the extended memory controller to the processor system, in response to the second memory access request, the to-be-accessed data in the data buffer; wherein the first memory access request and the second memory access request belong to N+1 memory access requests generated by the processor system, wherein the N+1 memory access requests are configured to access the to-be-accessed data, wherein N ≥ 1, and N is an integer, wherein before receiving the to-be-accessed data, each time another memory access request after the first memory access request of the N+1 memory access requests is received, the extended memory controller returns a specific response message to the processor system within an access delay specified in a memory bus protocol; and wherein the method further comprises: determining a value of the integer N according to a delay parameter of the extended memory for obtaining data from the extended memory by the computer system. receiving (510; 710; 810), by the extended memory controller, a first memory access request from the processor system, wherein the first memory access request comprises a first access address; determining, by the extended memory controller, a physical address of the to-be-accessed data according to the first access address; sending (550; 730; 830; 910), by the extended memory controller to the extended memory, a read request for to-be-accessed data in the extended memory, wherein the read request comprises the physical address of the to-be-accessed data; reading, by the extended memory controller, the to-be-accessed data into a data buffer of the extended memory controller; receiving (530; 910), by the extended memory controller from the processor system, a second memory access request comprising a second access address, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data; and sending, by the extended memory controller to the processor system, in response to the second memory access request, the to-be-accessed data in the data buffer; wherein the first memory access request and the second memory access request belong to N+1 memory access requests generated by the processor system, wherein the N+1 memory access requests are configured to access the to-be-accessed data, wherein N ≥ 1, and N is an integer, wherein before receiving the to-be-accessed data, each time another memory access request after the first memory access request of the N+1 memory access requests is received, the extended memory controller returns a specific response message to the processor system within an access delay specified in a memory bus protocol; and wherein the method further comprises: determining a value of the integer N according to a delay parameter of the extended memory for obtaining data from the extended memory by the computer system.