An apparatus comprising: one or more processors, the one or more processors including a plurality of chiplets; and a memory including a plurality of memory portions accessible to processing resources of each of the plurality of chiplets; wherein the one or more processors are to perform memory address hashing for the plurality of memory portions to generate memory address mapping, wherein performing memory address hashing includes: receiving memory address information including identification of one or more memory portions of the plurality of memory portions to be inactive, wherein the one or more memory portions to be inactive include one or more defective memory portions, generating one or more individual memory address hashes, wherein each individual memory address hash includes a mapping of a number of active memory portions of the plurality of memory portions to a range of memory addresses, and outputting a memory address hash including a final memory address mapping that does not provide a view of inactive memory portions of the plurality of memory portions, the final memory address mapping being based at least in part on the memory address mapping for the one or more individual memory address hashes; wherein generating the one or more individual memory address hashes includes generating multiple individual memory address hashes, and wherein one of the multiple individual memory address hashes is selectable for output. one or more processors, the one or more processors including a plurality of chiplets; and a memory including a plurality of memory portions accessible to processing resources of each of the plurality of chiplets; wherein the one or more processors are to perform memory address hashing for the plurality of memory portions to generate memory address mapping, wherein performing memory address hashing includes: receiving memory address information including identification of one or more memory portions of the plurality of memory portions to be inactive, wherein the one or more memory portions to be inactive include one or more defective memory portions, generating one or more individual memory address hashes, wherein each individual memory address hash includes a mapping of a number of active memory portions of the plurality of memory portions to a range of memory addresses, and outputting a memory address hash including a final memory address mapping that does not provide a view of inactive memory portions of the plurality of memory portions, the final memory address mapping being based at least in part on the memory address mapping for the one or more individual memory address hashes; wherein generating the one or more individual memory address hashes includes generating multiple individual memory address hashes, and wherein one of the multiple individual memory address hashes is selectable for output. receiving memory address information including identification of one or more memory portions of the plurality of memory portions to be inactive, wherein the one or more memory portions to be inactive include one or more defective memory portions, generating one or more individual memory address hashes, wherein each individual memory address hash includes a mapping of a number of active memory portions of the plurality of memory portions to a range of memory addresses, and outputting a memory address hash including a final memory address mapping that does not provide a view of inactive memory portions of the plurality of memory portions, the final memory address mapping being based at least in part on the memory address mapping for the one or more individual memory address hashes; wherein generating the one or more individual memory address hashes includes generating multiple individual memory address hashes, and wherein one of the multiple individual memory address hashes is selectable for output.