A method of providing digital varying output pulse width modulation, PWM, control for an inverter comprising at least a first switch and a second switch, the method comprising: generating a first binary control signal (PWM3A) at a system modulation frequency; generating a second binary control signal (PWM1A) having a carrier frequency which is an integral multiple, M, of the system modulation frequency and a having periodically varying duty cycle; wherein generating the second binary control signal comprises: providing a periodic counter having a reset frequency which is an integral multiple K of the modulation frequency, thereby defining K values (C1, C2...) of a counter sequence of the periodic counter; calculating, in a first module, a plurality M of switch-off moments (542, 544, 546, 548) of the second control signal, where M is different from K; determining, for each of the switch-off moments, a corresponding switch-off counter value and a corresponding counter sequence value; providing, in a second module, K memory locations; storing each switch-off counter value in a respective memory location corresponding to the respective counter sequence value; storing a dummy value in each of the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register; the method further comprising, for one half of a period corresponding to the system modulation frequency: providing the first binary control signal to the first switch; and providing the second binary control signal to the second switch by reading the at least one PWM value register. the method comprising: generating a first binary control signal (PWM3A) at a system modulation frequency; generating a second binary control signal (PWM1A) having a carrier frequency which is an integral multiple, M, of the system modulation frequency and a having periodically varying duty cycle; wherein generating the second binary control signal comprises: providing a periodic counter having a reset frequency which is an integral multiple K of the modulation frequency, thereby defining K values (C1, C2...) of a counter sequence of the periodic counter; calculating, in a first module, a plurality M of switch-off moments (542, 544, 546, 548) of the second control signal, where M is different from K; determining, for each of the switch-off moments, a corresponding switch-off counter value and a corresponding counter sequence value; providing, in a second module, K memory locations; storing each switch-off counter value in a respective memory location corresponding to the respective counter sequence value; storing a dummy value in each of the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register; the method further comprising, for one half of a period corresponding to the system modulation frequency: providing the first binary control signal to the first switch; and providing the second binary control signal to the second switch by reading the at least one PWM value register. providing a periodic counter having a reset frequency which is an integral multiple K of the modulation frequency, thereby defining K values (C1, C2...) of a counter sequence of the periodic counter; calculating, in a first module, a plurality M of switch-off moments (542, 544, 546, 548) of the second control signal, where M is different from K; determining, for each of the switch-off moments, a corresponding switch-off counter value and a corresponding counter sequence value; providing, in a second module, K memory locations; storing each switch-off counter value in a respective memory location corresponding to the respective counter sequence value; storing a dummy value in each of the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register; the method further comprising, for one half of a period corresponding to the system modulation frequency: providing the first binary control signal to the first switch; and providing the second binary control signal to the second switch by reading the at least one PWM value register. providing the first binary control signal to the first switch; and providing the second binary control signal to the second switch by reading the at least one PWM value register.