A computer implemented method for designing integrated circuits, comprising: selecting an initial design of a bipolar transistor; scaling said initial design of said bipolar transistor to generate a scaled design of said bipolar transistor; determining that stress compensation of said scaled design of said bipolar transistor is required based on dimensions of an emitter of said bipolar transistor after said scaling; and in response to said determining, adjusting a layout of a trench isolation layout level of said scaled design relative to a layout of an emitter layout level of said scaled design to generate a stress compensated scaled design of said bipolar transistor; wherein said trench isolation layout level defines a collector of said bipolar transistor and dielectric isolation along a perimeter of said collector after said scaling; said emitter layout level defines said emitter of said bipolar transistor after said scaling; and characterised in that: said adjusting said layout of said trench isolation layout level comprises notching said trench isolation in corners of said collector to form a collector having a dog-bone shape, said dog-bone shape of said collector comprising a substantially rectangular shape with projecting portions extending from the corners on at least two opposite sides (I,I',J,J',K,K',L,L'), said projecting portions reducing stress induced at the collector corners of a bipolar transistor made to the generated scaled design, thereby providing stress compensation in the stress compensated scaled design. selecting an initial design of a bipolar transistor; scaling said initial design of said bipolar transistor to generate a scaled design of said bipolar transistor; determining that stress compensation of said scaled design of said bipolar transistor is required based on dimensions of an emitter of said bipolar transistor after said scaling; and in response to said determining, adjusting a layout of a trench isolation layout level of said scaled design relative to a layout of an emitter layout level of said scaled design to generate a stress compensated scaled design of said bipolar transistor; wherein said trench isolation layout level defines a collector of said bipolar transistor and dielectric isolation along a perimeter of said collector after said scaling; said emitter layout level defines said emitter of said bipolar transistor after said scaling; and characterised in that: said adjusting said layout of said trench isolation layout level comprises notching said trench isolation in corners of said collector to form a collector having a dog-bone shape, said dog-bone shape of said collector comprising a substantially rectangular shape with projecting portions extending from the corners on at least two opposite sides (I,I',J,J',K,K',L,L'), said projecting portions reducing stress induced at the collector corners of a bipolar transistor made to the generated scaled design, thereby providing stress compensation in the stress compensated scaled design. said adjusting said layout of said trench isolation layout level comprises notching said trench isolation in corners of said collector to form a collector having a dog-bone shape, said dog-bone shape of said collector comprising a substantially rectangular shape with projecting portions extending from the corners on at least two opposite sides (I,I',J,J',K,K',L,L'), said projecting portions reducing stress induced at the collector corners of a bipolar transistor made to the generated scaled design, thereby providing stress compensation in the stress compensated scaled design.