A processor comprising: memory blocks located in a memory bank; a plurality of computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, wherein the computing nodes each have their own instruction buffer; and a global program controller unit, GPCU, forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes, wherein the instruction buffer is configured to send a beat to the GPCU each time the computing node finishes executing an instruction in the instruction buffer, wherein the processor further comprises a program control unit which comprises the GPCU (202; 512), the program control unit further comprising: a very long instruction word, VLIW, bundle dispatcher configured to decode program code for the task; a data address generation and organization, DAGO, unit configured to assign data pointers for the program code; and a scheduler configured to be coupled to a plurality of computing nodes, the scheduler configured to allocate the plurality of computing nodes to execute the program code, the scheduler configured to allocate a first thread to a first subset of the plurality of computing nodes, and to allocate a second thread to a second subset of the plurality of computing nodes; wherein the GPCU is further configured to use the beats from each of the instruction buffers to form a barrier amongst a subset of the computing nodes to synchronize the computing nodes with the GPCU, wherein the barrier is formed by not sending further instructions until all the computing nodes have synchronized to a common barrier instruction, wherein the GPCU is further configured to count the beats from the computing node to determine when the computing node has synchronized to the common instruction. memory blocks located in a memory bank; a plurality of computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, wherein the computing nodes each have their own instruction buffer; and a global program controller unit, GPCU, forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes, wherein the instruction buffer is configured to send a beat to the GPCU each time the computing node finishes executing an instruction in the instruction buffer, wherein the processor further comprises a program control unit which comprises the GPCU (202; 512), the program control unit further comprising: a very long instruction word, VLIW, bundle dispatcher configured to decode program code for the task; a data address generation and organization, DAGO, unit configured to assign data pointers for the program code; and a scheduler configured to be coupled to a plurality of computing nodes, the scheduler configured to allocate the plurality of computing nodes to execute the program code, the scheduler configured to allocate a first thread to a first subset of the plurality of computing nodes, and to allocate a second thread to a second subset of the plurality of computing nodes; wherein the GPCU is further configured to use the beats from each of the instruction buffers to form a barrier amongst a subset of the computing nodes to synchronize the computing nodes with the GPCU, wherein the barrier is formed by not sending further instructions until all the computing nodes have synchronized to a common barrier instruction, wherein the GPCU is further configured to count the beats from the computing node to determine when the computing node has synchronized to the common instruction. a very long instruction word, VLIW, bundle dispatcher configured to decode program code for the task; a data address generation and organization, DAGO, unit configured to assign data pointers for the program code; and a scheduler configured to be coupled to a plurality of computing nodes, the scheduler configured to allocate the plurality of computing nodes to execute the program code, the scheduler configured to allocate a first thread to a first subset of the plurality of computing nodes, and to allocate a second thread to a second subset of the plurality of computing nodes; wherein the GPCU is further configured to use the beats from each of the instruction buffers to form a barrier amongst a subset of the computing nodes to synchronize the computing nodes with the GPCU, wherein the barrier is formed by not sending further instructions until all the computing nodes have synchronized to a common barrier instruction, wherein the GPCU is further configured to count the beats from the computing node to determine when the computing node has synchronized to the common instruction.