A dynamic random access memory (DRAM) having first and second digit lines and a sense amplifier coupled to said first and second digit lines, each said digit line coupled to a respective memory cell (116, 150), said DRAM comprising: first and second isolation transistors, wherein said sense amplifier is coupled to said first digit line through said first isolation transistor and to said second digit line through said second isolation transistor, wherein a first connection of the sense amplifier is connected to a terminal of the first isolation transistor via a first node and a second connection of the sense amplifier is connected to a terminal of the second isolation transistor via a second node; a first voltage coupling/decoupling device having an output coupled to said first node, said first voltage coupling/decoupling device including a first variable signal driver coupled to said first node via a first capacitor, and said first variable signal driver configured to capacitively couple a first voltage onto or capacitively decouple a second voltage from said first digit line, a second voltage coupling/decoupling device having an output coupled to said second node, said second voltage coupling/decoupling device including a second variable signal driver coupled to said second node via a second capacitor, and said second variable signal driver configured to capacitively couple a first voltage onto or capacitively decouple a second voltage from said second node; and wherein, while the isolation transistors are turned off to isolate the first and second digit lines from the sense amplifier after said memory cell connected to the first digit line is accessed by the sense amplifier, said first variable signal driver is configured to generate an unchanged first bias voltage on the first node and said second variable signal driver is configured to capacitively decouple said second voltage from said second node before said sense amplifier is fired and the isolation transistors are turned on to restore electrical charge in said memory cell connected to said first digit line. first and second isolation transistors, wherein said sense amplifier is coupled to said first digit line through said first isolation transistor and to said second digit line through said second isolation transistor, wherein a first connection of the sense amplifier is connected to a terminal of the first isolation transistor via a first node and a second connection of the sense amplifier is connected to a terminal of the second isolation transistor via a second node; a first voltage coupling/decoupling device having an output coupled to said first node, said first voltage coupling/decoupling device including a first variable signal driver coupled to said first node via a first capacitor, and said first variable signal driver configured to capacitively couple a first voltage onto or capacitively decouple a second voltage from said first digit line, a second voltage coupling/decoupling device having an output coupled to said second node, said second voltage coupling/decoupling device including a second variable signal driver coupled to said second node via a second capacitor, and said second variable signal driver configured to capacitively couple a first voltage onto or capacitively decouple a second voltage from said second node; and wherein, while the isolation transistors are turned off to isolate the first and second digit lines from the sense amplifier after said memory cell connected to the first digit line is accessed by the sense amplifier, said first variable signal driver is configured to generate an unchanged first bias voltage on the first node and said second variable signal driver is configured to capacitively decouple said second voltage from said second node before said sense amplifier is fired and the isolation transistors are turned on to restore electrical charge in said memory cell connected to said first digit line.