A memory unit (10, 20, 30, 50, 60, 70, 80, 90), comprising: a first memory cell comprising: a first floating gate transistor having a first terminal configured to receive a first bit line signal, a second terminal, and a floating gate; and a first capacitance element having a first terminal, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a body configured to receive a first control signal; characterized in that the memory unit further comprises: a first voltage passing device (130, 730) configured to output voltages according to operations of the memory unit (10, 20, 30, 50, 60, 70, 80, 90), the first voltage passing device (130, 730) comprising a first passing gate transistor (PG1') having a first terminal (131, 731) configured to receive an inhibit signal, a second terminal (132, 732) coupled to the first terminal of the first capacitance element, and a control terminal (133, 733) configured to receive a passing gate control signal; wherein: the first terminal of the first capacitance element is coupled to the first voltage passing device (130, 730); and the first capacitance element and the first voltage passing device (130, 730) are disposed in a first N-well. a first memory cell comprising: a first floating gate transistor having a first terminal configured to receive a first bit line signal, a second terminal, and a floating gate; and a first capacitance element having a first terminal, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a body configured to receive a first control signal; a first floating gate transistor having a first terminal configured to receive a first bit line signal, a second terminal, and a floating gate; and a first capacitance element having a first terminal, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a body configured to receive a first control signal; characterized in that the memory unit further comprises: a first voltage passing device (130, 730) configured to output voltages according to operations of the memory unit (10, 20, 30, 50, 60, 70, 80, 90), the first voltage passing device (130, 730) comprising a first passing gate transistor (PG1') having a first terminal (131, 731) configured to receive an inhibit signal, a second terminal (132, 732) coupled to the first terminal of the first capacitance element, and a control terminal (133, 733) configured to receive a passing gate control signal; wherein: the first terminal of the first capacitance element is coupled to the first voltage passing device (130, 730); and the first capacitance element and the first voltage passing device (130, 730) are disposed in a first N-well. a first voltage passing device (130, 730) configured to output voltages according to operations of the memory unit (10, 20, 30, 50, 60, 70, 80, 90), the first voltage passing device (130, 730) comprising a first passing gate transistor (PG1') having a first terminal (131, 731) configured to receive an inhibit signal, a second terminal (132, 732) coupled to the first terminal of the first capacitance element, and a control terminal (133, 733) configured to receive a passing gate control signal; wherein: the first terminal of the first capacitance element is coupled to the first voltage passing device (130, 730); and the first capacitance element and the first voltage passing device (130, 730) are disposed in a first N-well. the first terminal of the first capacitance element is coupled to the first voltage passing device (130, 730); and the first capacitance element and the first voltage passing device (130, 730) are disposed in a first N-well.