A processor device having implemented thereon an executable white box-masked implementation of the cryptographic algorithm AES that comprises a plurality of rounds, in which round output values are produced employing round input values x, - wherein each round comprises an AddRoundKey transformation in which the round key k is employed, and a SubBytes transformation T, - wherein the implementation is white-box masked, for which purpose, at the round input of at least one or of each round, masked round input values are supplied instead of the round input values x, said masked round input values having been produced in advance by applying an invertible masking mapping A to the round input values x, characterized in that the white-box masked implementation is hardened in that at the round input of the at least one or of each round, white-box round input values x' are supplied instead of the round input values x, said white-box round input values being formed from a concatenation of: (i) the round input values x that are masked by means of the invertible masking mapping A and (ii) obfuscation values y that are likewise masked with the invertible masking mapping A; wherein from the white-box round input values x' only the (i) round input values x are fed to the SubBytes transformation T, and (ii) the masked obfuscation values y are not, wherein the implementation further comprises within a respective round: - an unmasking transformation of the masked input values x in the round input values x' before the SubBytes transformation by means of a masking mapping A -1 that is inverse to the masking mapping A and that is adapted to feed non-masked round input values x to the SubBytes transformation T, - and a remasking transformation of the obfuscation values y in the round input values x' from the masking mapping A to a random invertible mapping σ that is adapted to produce obfuscation values y masked with the random invertible mapping σ from the obfuscation values y masked with the masking mapping A, wherein further the round output of at least one or of each round is hardened in that a random invertible affine mapping B is applied at the round output of at least one or of each round, specifically to: (i) the round input values x processed with at least the SubBytes transformation T and (ii) the obfuscation values y masked with at least the random invertible mapping o. - wherein each round comprises an AddRoundKey transformation in which the round key k is employed, and a SubBytes transformation T, - wherein the implementation is white-box masked, for which purpose, at the round input of at least one or of each round, masked round input values are supplied instead of the round input values x, said masked round input values having been produced in advance by applying an invertible masking mapping A to the round input values x, - an unmasking transformation of the masked input values x in the round input values x' before the SubBytes transformation by means of a masking mapping A -1 that is inverse to the masking mapping A and that is adapted to feed non-masked round input values x to the SubBytes transformation T, - and a remasking transformation of the obfuscation values y in the round input values x' from the masking mapping A to a random invertible mapping σ that is adapted to produce obfuscation values y masked with the random invertible mapping σ from the obfuscation values y masked with the masking mapping A, wherein further the round output of at least one or of each round is hardened in that a random invertible affine mapping B is applied at the round output of at least one or of each round, specifically to: (i) the round input values x processed with at least the SubBytes transformation T and (ii) the obfuscation values y masked with at least the random invertible mapping o. (i) the round input values x processed with at least the SubBytes transformation T and (ii) the obfuscation values y masked with at least the random invertible mapping o.