A memory device comprising: a volatile memory cell that includes: a first pass gate having a first current electrode coupled to a true volatile bit line (BLv), a second current electrode coupled to a first data storage node, and a control electrode coupled to a volatile word line (WLv); a non-volatile memory cell that includes: a first resistive element having a first terminal and a second terminal; a second resistive element having a first terminal and a second terminal, wherein the first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node, the second terminal of the first resistive element is coupled to a first source line voltage (SL1nv), the second terminal of the second resistive element is coupled to a second source line voltage (SL2nv); a first transistor having a first current electrode coupled to the first data storage node of the volatile memory cell, a second current electrode coupled to ground, and a control gate coupled to the first node; and a second transistor including a first current electrode coupled to the first node, a second current electrode coupled to a non-volatile bit line (BLnv), and a control electrode coupled to a non-volatile word line (WLnv), wherein data from the non-volatile memory cell is restored to the volatile memory cell when, after a "1".is written to the volatile memory cell, a read voltage is applied at the first source line while a first bias voltage is applied at the second source line. a volatile memory cell that includes: a first pass gate having a first current electrode coupled to a true volatile bit line (BLv), a second current electrode coupled to a first data storage node, and a control electrode coupled to a volatile word line (WLv); a first pass gate having a first current electrode coupled to a true volatile bit line (BLv), a second current electrode coupled to a first data storage node, and a control electrode coupled to a volatile word line (WLv); a non-volatile memory cell that includes: a first resistive element having a first terminal and a second terminal; a second resistive element having a first terminal and a second terminal, wherein the first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node, the second terminal of the first resistive element is coupled to a first source line voltage (SL1nv), the second terminal of the second resistive element is coupled to a second source line voltage (SL2nv); a first transistor having a first current electrode coupled to the first data storage node of the volatile memory cell, a second current electrode coupled to ground, and a control gate coupled to the first node; and a second transistor including a first current electrode coupled to the first node, a second current electrode coupled to a non-volatile bit line (BLnv), and a control electrode coupled to a non-volatile word line (WLnv), wherein data from the non-volatile memory cell is restored to the volatile memory cell when, after a "1".is written to the volatile memory cell, a read voltage is applied at the first source line while a first bias voltage is applied at the second source line. a first resistive element having a first terminal and a second terminal; a second resistive element having a first terminal and a second terminal, wherein the first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node, the second terminal of the first resistive element is coupled to a first source line voltage (SL1nv), the second terminal of the second resistive element is coupled to a second source line voltage (SL2nv); the first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node, the second terminal of the first resistive element is coupled to a first source line voltage (SL1nv), the second terminal of the second resistive element is coupled to a second source line voltage (SL2nv); a first transistor having a first current electrode coupled to the first data storage node of the volatile memory cell, a second current electrode coupled to ground, and a control gate coupled to the first node; and a second transistor including a first current electrode coupled to the first node, a second current electrode coupled to a non-volatile bit line (BLnv), and a control electrode coupled to a non-volatile word line (WLnv), wherein data from the non-volatile memory cell is restored to the volatile memory cell when, after a "1".is written to the volatile memory cell, a read voltage is applied at the first source line while a first bias voltage is applied at the second source line.