A multilevel converter circuit which generates a plurality of voltage levels from a direct current power source divided into two, including three terminals having three mutually different voltage levels including zero, and selects from and outputs the plurality of voltage levels, comprising: first, second, third, and fourth arm pairs (QA1, QA2, QA3, QA4), each configured by connecting two arms formed of semiconductor switches (Ql, Q2, Q3, Q 4, Q5, Q6, Q7, Q8) in series; and a first alternating current switch configured by combining semiconductor switches (QR1, QR2), wherein the first alternating current switch is formed of an inverse parallel connection circuit of semiconductor switches (QR1, QR2), wherein, between a first direct current terminal and a third direct current terminal, the respective outer side terminals of the first arm pair, second arm pair, and third arm pair are connected in series, in order from the first direct current terminal, wherein the potential of the direct current power source is highest at the first direct current terminal and is lowest at the third direct current terminal, the outer side terminals of the fourth arm pair are connected between the midpoint terminal of the first arm pair and the midpoint terminal of the third arm pair, both ends of the first alternating current switch are connected between the midpoint terminal of the fourth arm pair and a second direct current terminal, wherein the potential of the direct current power source is intermediate at the second direct current terminal, both ends of each of a first capacitor and second capacitor are connected in parallel to both ends of each of the second arm pair and fourth arm pair respectively, and the midpoint terminal of the second arm pair is formed as an alternating current terminal, characterized in that both ends of a second alternating current switch are connected between the midpoint terminal of the fourth arm pair and the midpoint terminal of the second arm pair. first, second, third, and fourth arm pairs (QA1, QA2, QA3, QA4), each configured by connecting two arms formed of semiconductor switches (Ql, Q2, Q3, Q 4, Q5, Q6, Q7, Q8) in series; and a first alternating current switch configured by combining semiconductor switches (QR1, QR2), wherein the first alternating current switch is formed of an inverse parallel connection circuit of semiconductor switches (QR1, QR2), wherein, between a first direct current terminal and a third direct current terminal, the respective outer side terminals of the first arm pair, second arm pair, and third arm pair are connected in series, in order from the first direct current terminal, wherein the potential of the direct current power source is highest at the first direct current terminal and is lowest at the third direct current terminal, the outer side terminals of the fourth arm pair are connected between the midpoint terminal of the first arm pair and the midpoint terminal of the third arm pair, both ends of the first alternating current switch are connected between the midpoint terminal of the fourth arm pair and a second direct current terminal, wherein the potential of the direct current power source is intermediate at the second direct current terminal, both ends of each of a first capacitor and second capacitor are connected in parallel to both ends of each of the second arm pair and fourth arm pair respectively, and the midpoint terminal of the second arm pair is formed as an alternating current terminal, characterized in that both ends of a second alternating current switch are connected between the midpoint terminal of the fourth arm pair and the midpoint terminal of the second arm pair.