A system, comprising: a transmitter, comprising a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals (DAT [n:1]), the first main strobe path is configured to generate a first strobe signal (STB, STBN), the first main data path comprises a first delay circuit, the first main strobe path comprises a second delay circuit, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced so that the first strobe signal (STB, STBN) and the plurality of data signals (DAT[n:1]) are not aligned; and a receiver, comprising a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal (STB, STBN) to generate a plurality of second strobe signals (STB'), and the second main data path is configured to receive the plurality of data signals (DAT [n: 1]), and uses the plurality of second strobe signals (STB') to sample the plurality of data signals (DAT[n:1]) to generate a plurality of sampled signals, respectively; a deskew circuit, configured to generate a first control signal (Vc_DAT) and a second control signal (Vc_STB) to control delay amount of the first delay circuit and the second delay circuit, respectively; characterized in that the first main data path comprises: the first delay circuit, configured to receive a first reference clock signal (CK_DAT) to generate a delayed first reference clock signal; a clock tree synthesizer, configured to receive the delayed first reference clock signal to generate a plurality of first clock signals (CK_DAT'); and a plurality of first serializers, configured to use the plurality of first clock signals (CK_DAT') to sample input signals (Din) to generate the plurality of data signals (DAT [n:1]); and the first main strobe path comprises: the second delay circuit, configured to receive a second reference clock signal (CK_STB) to generate a second clock signal (CK_STB'); a second serializer, configured to receive the second clock signal (CK_STB') to generate the first strobe signal (STB, STBN). a transmitter, comprising a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals (DAT [n:1]), the first main strobe path is configured to generate a first strobe signal (STB, STBN), the first main data path comprises a first delay circuit, the first main strobe path comprises a second delay circuit, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced so that the first strobe signal (STB, STBN) and the plurality of data signals (DAT[n:1]) are not aligned; and a receiver, comprising a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal (STB, STBN) to generate a plurality of second strobe signals (STB'), and the second main data path is configured to receive the plurality of data signals (DAT [n: 1]), and uses the plurality of second strobe signals (STB') to sample the plurality of data signals (DAT[n:1]) to generate a plurality of sampled signals, respectively; a deskew circuit, configured to generate a first control signal (Vc_DAT) and a second control signal (Vc_STB) to control delay amount of the first delay circuit and the second delay circuit, respectively; characterized in that the first main data path comprises: the first delay circuit, configured to receive a first reference clock signal (CK_DAT) to generate a delayed first reference clock signal; a clock tree synthesizer, configured to receive the delayed first reference clock signal to generate a plurality of first clock signals (CK_DAT'); and a plurality of first serializers, configured to use the plurality of first clock signals (CK_DAT') to sample input signals (Din) to generate the plurality of data signals (DAT [n:1]); and the first main strobe path comprises: the second delay circuit, configured to receive a second reference clock signal (CK_STB) to generate a second clock signal (CK_STB'); a second serializer, configured to receive the second clock signal (CK_STB') to generate the first strobe signal (STB, STBN). the first delay circuit, configured to receive a first reference clock signal (CK_DAT) to generate a delayed first reference clock signal; a clock tree synthesizer, configured to receive the delayed first reference clock signal to generate a plurality of first clock signals (CK_DAT'); and a plurality of first serializers, configured to use the plurality of first clock signals (CK_DAT') to sample input signals (Din) to generate the plurality of data signals (DAT [n:1]); and the first main strobe path comprises: the second delay circuit, configured to receive a second reference clock signal (CK_STB) to generate a second clock signal (CK_STB'); a second serializer, configured to receive the second clock signal (CK_STB') to generate the first strobe signal (STB, STBN). the second delay circuit, configured to receive a second reference clock signal (CK_STB) to generate a second clock signal (CK_STB'); a second serializer, configured to receive the second clock signal (CK_STB') to generate the first strobe signal (STB, STBN).