A method for synchronizing operations of a plurality of processors (102, 104) within a system, said system comprising at least two processors (102, 104) and an external circuit, said method comprising the steps of: receiving by the external circuit a first request from a first processor for writing first data to or reading first data from a first address in a first data store; subsequently receiving by the external circuit a second request from a second processor for writing second data to or reading second data from a second address in a second data store; comparing, by the external circuit, values of the first and second addresses to each other and values of the first and second data to each other; and concurrently communicating an asynchronous ready signal from the external circuit to the first and second processors (102, 104) when the values of the first and second addresses match each other and the values of the first and second data match each other asserting said at least one write or read request made by at least one of the first processor and the second processor, thereby causing operations of the first and second processors (102, 104) to be synchronized in time with each other characterized in that the method further comprises the steps of: performing operations by the first processor such that a first task is scheduled each time a write to the first data store is to be performed during a first interrupt service routine, and performing operations within the electronic circuit wherein, first and second processors (102, 104) communicate to the other processor an identifier value of a task intended to be dispatched, thereby causing the first processor to make identical dispatch decisions for the first tasks scheduled during the first interrupt service routine as those of the second processor for second tasks scheduled during a second interrupt service routine. receiving by the external circuit a first request from a first processor for writing first data to or reading first data from a first address in a first data store; subsequently receiving by the external circuit a second request from a second processor for writing second data to or reading second data from a second address in a second data store; comparing, by the external circuit, values of the first and second addresses to each other and values of the first and second data to each other; and concurrently communicating an asynchronous ready signal from the external circuit to the first and second processors (102, 104) when the values of the first and second addresses match each other and the values of the first and second data match each other asserting said at least one write or read request made by at least one of the first processor and the second processor, thereby causing operations of the first and second processors (102, 104) to be synchronized in time with each other characterized in that the method further comprises the steps of: performing operations by the first processor such that a first task is scheduled each time a write to the first data store is to be performed during a first interrupt service routine, and performing operations within the electronic circuit wherein, first and second processors (102, 104) communicate to the other processor an identifier value of a task intended to be dispatched, thereby causing the first processor to make identical dispatch decisions for the first tasks scheduled during the first interrupt service routine as those of the second processor for second tasks scheduled during a second interrupt service routine. performing operations by the first processor such that a first task is scheduled each time a write to the first data store is to be performed during a first interrupt service routine, and performing operations within the electronic circuit wherein, first and second processors (102, 104) communicate to the other processor an identifier value of a task intended to be dispatched, thereby causing the first processor to make identical dispatch decisions for the first tasks scheduled during the first interrupt service routine as those of the second processor for second tasks scheduled during a second interrupt service routine.