A memory device, comprising: a plurality of word line layers (WLD4, WLD3, WLL0-WLL10, WLD1, WLD2) which are vertically spaced apart from one another by dielectric layers (DL0-DL19); and a set of NAND strings (700n-703n, 710n-713n, 720n-723n, 730n-733n; 1010-1013; 1070-1075; 1080-1083) extending through the plurality of word line layers, the set of NAND strings comprises NAND strings (1020, 1023; 1070, 1082; 1073) in an interior sub-block (SB1, SB3; SB2, SB5), NAND strings (1022, 1024; 1080) in a first edge portion (SB0a, SB2a) of a divided sub-block (860, 861; 1050, 1051) and NAND strings (1011, 1013; 1072, 1083; 1075) in a second edge portion (SB0b, SB2b; SB3b) of the divided sub-block, wherein the interior sub-block is between the first and second edge portions; characterised in that: a first set of bit lines (even-numbered bit lines of BL0-BL30) are connected to the NAND strings of the first edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the second edge portion; and a second set of bit lines (odd-numbered bit lines of BL0-BL30) are connected to the NAND strings of the second edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the first edge portion, wherein a thickness of a block oxide layer in the NAND strings of the first and second edge portions is less than a thickness of a block oxide layer in the NAND strings of the interior sub-block. a plurality of word line layers (WLD4, WLD3, WLL0-WLL10, WLD1, WLD2) which are vertically spaced apart from one another by dielectric layers (DL0-DL19); and a set of NAND strings (700n-703n, 710n-713n, 720n-723n, 730n-733n; 1010-1013; 1070-1075; 1080-1083) extending through the plurality of word line layers, the set of NAND strings comprises NAND strings (1020, 1023; 1070, 1082; 1073) in an interior sub-block (SB1, SB3; SB2, SB5), NAND strings (1022, 1024; 1080) in a first edge portion (SB0a, SB2a) of a divided sub-block (860, 861; 1050, 1051) and NAND strings (1011, 1013; 1072, 1083; 1075) in a second edge portion (SB0b, SB2b; SB3b) of the divided sub-block, wherein the interior sub-block is between the first and second edge portions; characterised in that: a first set of bit lines (even-numbered bit lines of BL0-BL30) are connected to the NAND strings of the first edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the second edge portion; and a second set of bit lines (odd-numbered bit lines of BL0-BL30) are connected to the NAND strings of the second edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the first edge portion, wherein a thickness of a block oxide layer in the NAND strings of the first and second edge portions is less than a thickness of a block oxide layer in the NAND strings of the interior sub-block. a first set of bit lines (even-numbered bit lines of BL0-BL30) are connected to the NAND strings of the first edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the second edge portion; and a second set of bit lines (odd-numbered bit lines of BL0-BL30) are connected to the NAND strings of the second edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the first edge portion, wherein a thickness of a block oxide layer in the NAND strings of the first and second edge portions is less than a thickness of a block oxide layer in the NAND strings of the interior sub-block.