A semiconductor device comprising a semiconductor substrate having an upper main surface and a lower main surface, said semiconductor substrate including: a drain layer of a first conductivity type formed on said upper main surface; a main base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, said main base region being divided into a plurality of parallel band-shaped regions; an underpad base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer, exposed to said upper main surface and isolated from said main base region; a source region of a first conductivity type selectively formed in said main base region to be shallower than said main base region and exposed to said upper main surface, said source region being divided into a plurality of regions, said plurality of regions of said source region being corresponding to said plurality of regions of said main base region, respectively; and a peripheral base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, said peripheral base region having a portion positioned between said main base region and said underpad base region and a portion contacting one end of each of said parallel band-shaped regions of said main base region, not having a semiconductor region of a first conductivity type provided therein, and isolated from said underpad base region, said semiconductor device further comprising: a first main electrode connected to said main base region, said source region and said peripheral base region and not connected to said underpad base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an exposed surface of said underpad base region in said upper main surface with an insulating layer interposed therebetween and connected to said gate electrode; and a second main electrode connected to said lower main surface. a drain layer of a first conductivity type formed on said upper main surface; a main base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, said main base region being divided into a plurality of parallel band-shaped regions; an underpad base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer, exposed to said upper main surface and isolated from said main base region; a source region of a first conductivity type selectively formed in said main base region to be shallower than said main base region and exposed to said upper main surface, said source region being divided into a plurality of regions, said plurality of regions of said source region being corresponding to said plurality of regions of said main base region, respectively; and a peripheral base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, said peripheral base region having a portion positioned between said main base region and said underpad base region and a portion contacting one end of each of said parallel band-shaped regions of said main base region, not having a semiconductor region of a first conductivity type provided therein, and isolated from said underpad base region, said semiconductor device further comprising: a first main electrode connected to said main base region, said source region and said peripheral base region and not connected to said underpad base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an exposed surface of said underpad base region in said upper main surface with an insulating layer interposed therebetween and connected to said gate electrode; and a second main electrode connected to said lower main surface. a first main electrode connected to said main base region, said source region and said peripheral base region and not connected to said underpad base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an exposed surface of said underpad base region in said upper main surface with an insulating layer interposed therebetween and connected to said gate electrode; and a second main electrode connected to said lower main surface.