A power switch circuit comprising: a first transistor (ma), wherein a first source/drain terminal of the first transistor (ma) is configured to receive a first supply voltage, a second source/drain terminal of the first transistor (ma) is connected with a node (z), a gate terminal of the first transistor (ma) is configured to receive a second supply voltage, a body terminal of the first transistor (ma) is connected with the node (z), and the node (z) is configured to output an output signal (Vs); and a second transistor (mb), wherein a first source/drain terminal of the second transistor (mb) is configured to receive the second supply voltage, a second source/drain terminal of the second transistor (mb) is connected with the node (z), a gate terminal of the second transistor (mb) is configured to receive the first supply voltage, and a body terminal of the second transistor (mb) is connected with the node (z), a current source connected between a bias voltage (Vbias) and the node (z), the power switch circuit being configured such that, if the first supply voltage is lower than the second supply voltage, the first supply voltage is selected as the output signal (Vs) and the first supply voltage is transmitted from the first source/drain terminal of the first transistor (ma) to the node (z), and wherein if the first supply voltage is higher than the second supply voltage, the second supply voltage is selected as the output signal (Vs) and the second supply voltage is transmitted from the first source/drain terminal of the second transistor (mb) to the node (z), and wherein if the first supply voltage is equal to the second supply voltage, the bias voltage (Vbias) is selected as the output signal (Vs); characterised in that the bias voltage (Vbias) is supplied by the current source; and in that the bias voltage (Vbias) is equal to the first supply voltage, or the bias voltage (Vbias) is equal to the second supply voltage. a first transistor (ma), wherein a first source/drain terminal of the first transistor (ma) is configured to receive a first supply voltage, a second source/drain terminal of the first transistor (ma) is connected with a node (z), a gate terminal of the first transistor (ma) is configured to receive a second supply voltage, a body terminal of the first transistor (ma) is connected with the node (z), and the node (z) is configured to output an output signal (Vs); and a second transistor (mb), wherein a first source/drain terminal of the second transistor (mb) is configured to receive the second supply voltage, a second source/drain terminal of the second transistor (mb) is connected with the node (z), a gate terminal of the second transistor (mb) is configured to receive the first supply voltage, and a body terminal of the second transistor (mb) is connected with the node (z), a current source connected between a bias voltage (Vbias) and the node (z), the power switch circuit being configured such that, if the first supply voltage is lower than the second supply voltage, the first supply voltage is selected as the output signal (Vs) and the first supply voltage is transmitted from the first source/drain terminal of the first transistor (ma) to the node (z), and wherein if the first supply voltage is higher than the second supply voltage, the second supply voltage is selected as the output signal (Vs) and the second supply voltage is transmitted from the first source/drain terminal of the second transistor (mb) to the node (z), and wherein if the first supply voltage is equal to the second supply voltage, the bias voltage (Vbias) is selected as the output signal (Vs); characterised in that the bias voltage (Vbias) is supplied by the current source; and in that the bias voltage (Vbias) is equal to the first supply voltage, or the bias voltage (Vbias) is equal to the second supply voltage.