A processor (110; 400; 500; 670, 680; 800; 1100) comprising: a core (120a-120n; 200; 410a-41On; 510o-510 n; 1101, 1102; 674a, 674b; 810 0 -810 n) to execute instructions, the core (120a-120n; 200; 410a-410n; 510 0 -510 n; 1101, 1102; 674a, 674b; 810 0 -810 n) including a clock generation logic (220; 412a-412n) to receive and distribute a first clock signal to a plurality of units of the core (120a-120n; 200; 410a-410n; 510o-510 n; 1101, 1102; 674a, 674b; 810 0 -810 n), a restriction means for receiving a restriction command from a power control unit (138; 455; 555; 840; 1160) of the processor (110; 400; 500; 670, 680; 800; 1100), for determining a restriction level based on the restriction command, and for causing the clock generation logic (220; 412a-412n) to reduce delivery of the first clock signal based on the restriction level to at least one of the plurality of units, wherein the reduced delivery of the first clock signal is at a lower frequency than a frequency of the first clock signal; a clock crossing logic to couple the core (120a-120n; 200; 410a-410n; 510o-510 n; 1101, 1102; 674a, 674b; 810 0 -810 n) to a system agent means of the processor (110; 400; 500; 670, 680; 800; 1100), wherein the clock crossing logic is to operate at the first clock signal without restriction, wherein at least one of the plurality of units is to operate at the first clock signal with the reduced delivery; a buffer coupled to the clock crossing logic, the buffer to be written according to the first clock signal with the reduced delivery and to be read according to the first clock signal without restriction; a bypass path coupled between a first unit of the plurality of units and the clock crossing logic; and a second path coupled between the first unit and the buffer, wherein the bypass path is to be blocked responsive to the restriction command. a core (120a-120n; 200; 410a-41On; 510o-510 n; 1101, 1102; 674a, 674b; 810 0 -810 n) to execute instructions, the core (120a-120n; 200; 410a-410n; 510 0 -510 n; 1101, 1102; 674a, 674b; 810 0 -810 n) including a clock generation logic (220; 412a-412n) to receive and distribute a first clock signal to a plurality of units of the core (120a-120n; 200; 410a-410n; 510o-510 n; 1101, 1102; 674a, 674b; 810 0 -810 n), a restriction means for receiving a restriction command from a power control unit (138; 455; 555; 840; 1160) of the processor (110; 400; 500; 670, 680; 800; 1100), for determining a restriction level based on the restriction command, and for causing the clock generation logic (220; 412a-412n) to reduce delivery of the first clock signal based on the restriction level to at least one of the plurality of units, wherein the reduced delivery of the first clock signal is at a lower frequency than a frequency of the first clock signal; a clock crossing logic to couple the core (120a-120n; 200; 410a-410n; 510o-510 n; 1101, 1102; 674a, 674b; 810 0 -810 n) to a system agent means of the processor (110; 400; 500; 670, 680; 800; 1100), wherein the clock crossing logic is to operate at the first clock signal without restriction, wherein at least one of the plurality of units is to operate at the first clock signal with the reduced delivery; a buffer coupled to the clock crossing logic, the buffer to be written according to the first clock signal with the reduced delivery and to be read according to the first clock signal without restriction; a bypass path coupled between a first unit of the plurality of units and the clock crossing logic; and a second path coupled between the first unit and the buffer, wherein the bypass path is to be blocked responsive to the restriction command.