A time limiter circuit for integration with a phase detector of a phase-locked loop, PLL, the time limiter circuit comprising an absolute phase detection sub-circuit configured to detect whether a phase tracking signal is asserted by the phase detector, the phase tracking signal indicating a detected phase difference between an output signal of the PLL and an input reference signal of the PLL; a delay timer sub-circuit, coupled with the absolute phase detection sub-circuit, and configured to determine, automatically responsive to the absolute phase detection sub-circuit detecting that the phase tracking signal is asserted, whether a signal duration of the phase tracking signal exceeds a threshold duration; and a pulse gating sub-circuit, coupled with the delay timer sub-circuit, and configured to force de-assertion of the phase tracking signal for at least a remainder of a present operating cycle of the PLL automatically responsive to the delay timer sub-circuit determining that the signal duration exceeds the threshold duration; wherein: the absolute phase detection sub-circuit is configured to generate an absolute phase signal responsive to detecting that the phase tracking signal is asserted by the phase detector; the delay timer sub-circuit is configured to generate a gate trigger signal automatically responsive to determining that the signal duration exceeds the threshold duration based on the absolute phase signal; and the pulse gating sub-circuit is configured to generate a time-limited tracking signal, such that a duration of the time-limited tracking signal is limited by the pulse gating sub-circuit forcing the de-assertion responsive to the gate trigger when the signal duration exceeds the threshold duration, and is limited by the duration of the phase tracking signal otherwise; wherein the phase tracking signal is one of an up signal or a down signal, such that assertion of the up signal increases current injection into a loop filter of the PLL, and assertion of the down signal decreases current injection into the loop filter; and the absolute phase detection sub-circuit is configured to generate the absolute phase signal such that the absolute phase signal is asserted responsive to the up signal being asserted and/or the down signal being asserted. a delay timer sub-circuit, coupled with the absolute phase detection sub-circuit, and configured to determine, automatically responsive to the absolute phase detection sub-circuit detecting that the phase tracking signal is asserted, whether a signal duration of the phase tracking signal exceeds a threshold duration; and a pulse gating sub-circuit, coupled with the delay timer sub-circuit, and configured to force de-assertion of the phase tracking signal for at least a remainder of a present operating cycle of the PLL automatically responsive to the delay timer sub-circuit determining that the signal duration exceeds the threshold duration; wherein: the absolute phase detection sub-circuit is configured to generate an absolute phase signal responsive to detecting that the phase tracking signal is asserted by the phase detector; the delay timer sub-circuit is configured to generate a gate trigger signal automatically responsive to determining that the signal duration exceeds the threshold duration based on the absolute phase signal; and the pulse gating sub-circuit is configured to generate a time-limited tracking signal, such that a duration of the time-limited tracking signal is limited by the pulse gating sub-circuit forcing the de-assertion responsive to the gate trigger when the signal duration exceeds the threshold duration, and is limited by the duration of the phase tracking signal otherwise; wherein the phase tracking signal is one of an up signal or a down signal, such that assertion of the up signal increases current injection into a loop filter of the PLL, and assertion of the down signal decreases current injection into the loop filter; and the absolute phase detection sub-circuit is configured to generate the absolute phase signal such that the absolute phase signal is asserted responsive to the up signal being asserted and/or the down signal being asserted. the absolute phase detection sub-circuit is configured to generate an absolute phase signal responsive to detecting that the phase tracking signal is asserted by the phase detector; the delay timer sub-circuit is configured to generate a gate trigger signal automatically responsive to determining that the signal duration exceeds the threshold duration based on the absolute phase signal; and the pulse gating sub-circuit is configured to generate a time-limited tracking signal, such that a duration of the time-limited tracking signal is limited by the pulse gating sub-circuit forcing the de-assertion responsive to the gate trigger when the signal duration exceeds the threshold duration, and is limited by the duration of the phase tracking signal otherwise; wherein the phase tracking signal is one of an up signal or a down signal, such that assertion of the up signal increases current injection into a loop filter of the PLL, and assertion of the down signal decreases current injection into the loop filter; and the absolute phase detection sub-circuit is configured to generate the absolute phase signal such that the absolute phase signal is asserted responsive to the up signal being asserted and/or the down signal being asserted.