An integrated circuit, comprising: a column of memory cells (300, 700, 702), wherein a first portion of the column of memory cells (300, 700, 702) is operable in a first mode and in a second mode that is different than the first mode, and wherein a second portion of the column of memory cells (300, 700, 702) is operable only in the first mode, wherein each memory cell (300, 700, 702) in the first portion of the column of memory cells (300, 700, 702) has a corresponding configuration write port and a corresponding user write port different from the corresponding configuration write port, and each memory cell (300, 700, 702) in the second portion of the column of memory cells (300, 700, 702) has a corresponding configuration write port, wherein each user write port is configured to write corresponding user data and each configuration write port is configured to write a corresponding configuration data bit for a lookup table, LUT, such that the corresponding memory cell (300, 700, 702) of the portion in the first mode stores, via its configuration write port, and supplies the corresponding configuration bit for said LUT, and such that the corresponding memory cell (300, 700, 702) of the portion in the second mode stores, via its user write port, and supplies the corresponding user data, and wherein each memory cell (300, 700, 702) in the column has a corresponding read port, the integrated circuit being characterized by further comprising: a data line connected to the read ports; a read masking circuit connected to the data line and configured to, in response to being activated, set the voltage on the data line to a predetermined level; the integrated circuit comprising further an address decoding logic configured to activate the read masking circuit when one of the memory cells of the first portion is accessed for read and the memory cells of the first portion are in the second mode, such that the read will not be affected by the user content that is stored in said accessed memory cell, and to disable the read masking circuit otherwise. a column of memory cells (300, 700, 702), wherein a first portion of the column of memory cells (300, 700, 702) is operable in a first mode and in a second mode that is different than the first mode, and wherein a second portion of the column of memory cells (300, 700, 702) is operable only in the first mode, wherein each memory cell (300, 700, 702) in the first portion of the column of memory cells (300, 700, 702) has a corresponding configuration write port and a corresponding user write port different from the corresponding configuration write port, and each memory cell (300, 700, 702) in the second portion of the column of memory cells (300, 700, 702) has a corresponding configuration write port, wherein each user write port is configured to write corresponding user data and each configuration write port is configured to write a corresponding configuration data bit for a lookup table, LUT, such that the corresponding memory cell (300, 700, 702) of the portion in the first mode stores, via its configuration write port, and supplies the corresponding configuration bit for said LUT, and such that the corresponding memory cell (300, 700, 702) of the portion in the second mode stores, via its user write port, and supplies the corresponding user data, and wherein each memory cell (300, 700, 702) in the column has a corresponding read port, the integrated circuit being characterized by further comprising: a data line connected to the read ports; a read masking circuit connected to the data line and configured to, in response to being activated, set the voltage on the data line to a predetermined level; the integrated circuit comprising further an address decoding logic configured to activate the read masking circuit when one of the memory cells of the first portion is accessed for read and the memory cells of the first portion are in the second mode, such that the read will not be affected by the user content that is stored in said accessed memory cell, and to disable the read masking circuit otherwise. a data line connected to the read ports; a read masking circuit connected to the data line and configured to, in response to being activated, set the voltage on the data line to a predetermined level; the integrated circuit comprising further an address decoding logic configured to activate the read masking circuit when one of the memory cells of the first portion is accessed for read and the memory cells of the first portion are in the second mode, such that the read will not be affected by the user content that is stored in said accessed memory cell, and to disable the read masking circuit otherwise.