Apparatus for controlling memory access in a data processing system, wherein the data processing system when operating comprises multiple subsystems, each subsystem comprising at least one processing element and at least one peripheral device, the apparatus comprising: memory transaction control circuitry to receive memory transaction information of a memory transaction issued by a peripheral device of the data processing system, wherein the memory transaction information comprises a stream identifier indicative of the peripheral device; a main control register to store a value indicative of an address of a stream table, wherein the stream table comprises multiple entries, and wherein the multiple entries each comprise an owning subsystem identifier; and at least one subsystem control register corresponding to each subsystem of the multiple subsystems, the at least one subsystem control register to store memory access checking configuration information, wherein the memory transaction control circuitry is responsive to reception of the memory transaction information: to select an entry of the multiple entries of the stream table identified by the value indicative of the address of the stream table in dependence on the stream identifier; to select at least one subsystem control register corresponding to the subsystem identified by the owning subsystem identifier of the entry; and to cause enforcement of memory access rules in dependence on the memory transaction information and the memory access checking configuration information stored in the selected at least one subsystem control register, wherein the at least one peripheral device of the data processing system is a multi-stream-identifier peripheral associated with more than one stream identifier, wherein the more than one stream identifiers for the multi-stream-identifier peripheral are associated with mutually independent operations of the multi-stream-identifier peripheral. memory transaction control circuitry to receive memory transaction information of a memory transaction issued by a peripheral device of the data processing system, wherein the memory transaction information comprises a stream identifier indicative of the peripheral device; a main control register to store a value indicative of an address of a stream table, wherein the stream table comprises multiple entries, and wherein the multiple entries each comprise an owning subsystem identifier; and at least one subsystem control register corresponding to each subsystem of the multiple subsystems, the at least one subsystem control register to store memory access checking configuration information, wherein the memory transaction control circuitry is responsive to reception of the memory transaction information: to select an entry of the multiple entries of the stream table identified by the value indicative of the address of the stream table in dependence on the stream identifier; to select at least one subsystem control register corresponding to the subsystem identified by the owning subsystem identifier of the entry; and to cause enforcement of memory access rules in dependence on the memory transaction information and the memory access checking configuration information stored in the selected at least one subsystem control register, to select an entry of the multiple entries of the stream table identified by the value indicative of the address of the stream table in dependence on the stream identifier; to select at least one subsystem control register corresponding to the subsystem identified by the owning subsystem identifier of the entry; and to cause enforcement of memory access rules in dependence on the memory transaction information and the memory access checking configuration information stored in the selected at least one subsystem control register, wherein the at least one peripheral device of the data processing system is a multi-stream-identifier peripheral associated with more than one stream identifier, wherein the more than one stream identifiers for the multi-stream-identifier peripheral are associated with mutually independent operations of the multi-stream-identifier peripheral.