An electronic device with a duty cycle correction loop comprising: a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector (304, 308) coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector (304, 308) being configured to: assign and store a first duty cycle correction code corresponding to a set amount of duty cycle correction for the first clock signal; assign and store a second duty cycle correction code corresponding to a set amount of duty cycle correction for the second clock signal; calculate an offset code configured to represent a duty cycle offset based on the first and second duty cycle correction codes obtained through subsequent duty cycle correction operations; and negate the calculated offset code from results of the subsequent duty cycle correction operations of the duty cycle correction loop the electronic device further comprising a finite state machine configured to control a multiplexer to sequentially output the first clock signal and the second clock signal to the duty cycle corrector (304, 308), wherein the calculated offset code is subtracted or added, depending on whether the calculated offset code is positive or negative, from or to subsequent duty cycle correction calculations, and wherein the duty cycle corrector (304, 308) is further configured to calculate the offset code by averaging the first and second duty cycle correction codes. a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector (304, 308) coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector (304, 308) being configured to: assign and store a first duty cycle correction code corresponding to a set amount of duty cycle correction for the first clock signal; assign and store a second duty cycle correction code corresponding to a set amount of duty cycle correction for the second clock signal; calculate an offset code configured to represent a duty cycle offset based on the first and second duty cycle correction codes obtained through subsequent duty cycle correction operations; and negate the calculated offset code from results of the subsequent duty cycle correction operations of the duty cycle correction loop the electronic device further comprising a finite state machine configured to control a multiplexer to sequentially output the first clock signal and the second clock signal to the duty cycle corrector (304, 308), wherein the calculated offset code is subtracted or added, depending on whether the calculated offset code is positive or negative, from or to subsequent duty cycle correction calculations, and assign and store a first duty cycle correction code corresponding to a set amount of duty cycle correction for the first clock signal; assign and store a second duty cycle correction code corresponding to a set amount of duty cycle correction for the second clock signal; calculate an offset code configured to represent a duty cycle offset based on the first and second duty cycle correction codes obtained through subsequent duty cycle correction operations; and negate the calculated offset code from results of the subsequent duty cycle correction operations of the duty cycle correction loop the electronic device further comprising a finite state machine configured to control a multiplexer to sequentially output the first clock signal and the second clock signal to the duty cycle corrector (304, 308), wherein the calculated offset code is subtracted or added, depending on whether the calculated offset code is positive or negative, from or to subsequent duty cycle correction calculations, and wherein the duty cycle corrector (304, 308) is further configured to calculate the offset code by averaging the first and second duty cycle correction codes.