A time-to-digital converter, TDC, circuitry for converting a phase difference between an input reference signal (109, 309) and an input clock signal (110, 310) to a digitally represented output signal (139, 339), the TDC circuitry comprising: a plurality of constituent TDC:s (101, 102, 103, 200, 301,..., 308), wherein each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183, 282, 381,..., 388) and a constituent clock signal (110, 210, 371,..., 378) to a digitally represented constituent output signal (131, 132, 133, 232, 331,..., 338); a reference signal provider (120, 320) configured to provide the respective constituent reference signals (181, 182, 183, 282, 381,..., 388) to each of the constituent TDC:s (101, 102, 103, 200, 301,..., 308), wherein - in at least a parallel operation mode of the TDC circuitry - each respective constituent reference signal comprises a respectively delayed version of the input reference signal (109, 309) with different respective delays for at least two of the respective constituent reference signals; and a digital signal combiner (130, 330) configured to provide the digitally represented output signal (139, 339) based on the digitally represented constituent output signals (131, 132, 133, 232, 331,..., 338) of the constituent TDC:s; wherein the reference signal provider (120, 320) is configured to provide - in at least the parallel operation mode of the TDC circuitry - the respective constituent reference signals (181, 182, 183, 282, 282, 381,..., 388) as respectively delayed versions of the input reference signal (109, 309) with the respective delays (121, 122, 123, 321,..., 328) being stochastically generated. a plurality of constituent TDC:s (101, 102, 103, 200, 301,..., 308), wherein each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183, 282, 381,..., 388) and a constituent clock signal (110, 210, 371,..., 378) to a digitally represented constituent output signal (131, 132, 133, 232, 331,..., 338); a reference signal provider (120, 320) configured to provide the respective constituent reference signals (181, 182, 183, 282, 381,..., 388) to each of the constituent TDC:s (101, 102, 103, 200, 301,..., 308), wherein - in at least a parallel operation mode of the TDC circuitry - each respective constituent reference signal comprises a respectively delayed version of the input reference signal (109, 309) with different respective delays for at least two of the respective constituent reference signals; and a digital signal combiner (130, 330) configured to provide the digitally represented output signal (139, 339) based on the digitally represented constituent output signals (131, 132, 133, 232, 331,..., 338) of the constituent TDC:s; wherein the reference signal provider (120, 320) is configured to provide - in at least the parallel operation mode of the TDC circuitry - the respective constituent reference signals (181, 182, 183, 282, 282, 381,..., 388) as respectively delayed versions of the input reference signal (109, 309) with the respective delays (121, 122, 123, 321,..., 328) being stochastically generated.