A method of partitioning a via in a multilayer printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via, the method comprising the steps of: - placing at least one island of a first plating resist layer on a first layered structure comprising a first conductive layer and a first dielectric layer and placing at least one island of a second plating resist layer on a second layered structure comprising a second conductive layer and a second dielectric layer; - laminating the first and second layered structures with a third intermediate layered structure comprising at least one third dielectric layer adapted so that the islands of the first and second plating resist layers (233,234) become embedded in the at least one third dielectric layer; - drilling a first hole in the printed circuit board so that the first hole passes through the islands of the first and the second plating resist layer (233,234); - placing said printed circuit board in a copper seed catalyzing bath so that copper is placed on the interior of the first hole except for the portions (252,253) with the plating resist layer (233,234); - placing the printed circuit board in a electrolytic copper plating bath where the copper placed on the at least one third dielectric layer portion of the first hole is electrically isolated from the first and second conductive layers (205,206) so that additional copper is placed on the interior of the first hole except for the portions (252,253) of the first and second plating resist layers (233,234) and except for the portion of the at least one third dielectric layer; - removing the copper placed on the at least one third dielectric layer portion of the first hole. - placing at least one island of a first plating resist layer on a first layered structure comprising a first conductive layer and a first dielectric layer and placing at least one island of a second plating resist layer on a second layered structure comprising a second conductive layer and a second dielectric layer; - laminating the first and second layered structures with a third intermediate layered structure comprising at least one third dielectric layer adapted so that the islands of the first and second plating resist layers (233,234) become embedded in the at least one third dielectric layer; - drilling a first hole in the printed circuit board so that the first hole passes through the islands of the first and the second plating resist layer (233,234); - placing said printed circuit board in a copper seed catalyzing bath so that copper is placed on the interior of the first hole except for the portions (252,253) with the plating resist layer (233,234); - placing the printed circuit board in a electrolytic copper plating bath where the copper placed on the at least one third dielectric layer portion of the first hole is electrically isolated from the first and second conductive layers (205,206) so that additional copper is placed on the interior of the first hole except for the portions (252,253) of the first and second plating resist layers (233,234) and except for the portion of the at least one third dielectric layer; - removing the copper placed on the at least one third dielectric layer portion of the first hole.