A liquid crystal display device that comprises a display panel with a pixel array and a display panel drive circuit for writing an input image to the display panel; wherein the display panel drive circuit comprises a data driver, a gate driver, and a timing controller wherein the display panel comprises a plurality data lines in a first direction and a plurality of gate lines in a second direction, wherein the first direction is orthogonal to the second direction; wherein the pixel array has a plurality of subpixels, and wherein each sub-pixel is arranged at a corresponding intersection of a data line (S1 to Sm) and a gate line (G1 to Gn); wherein the plurality of pixels comprise a plurality of first-color subpixels, a plurality of second-color subpixels, a plurality of third-color subpixels, and a plurality of fourth-color subpixels, being four mutually different colors, wherein each of the subpixels comprises a thin-film transistor, hereinafter referred to as TFT, that is connected to a pixel electrode of this respective subpixel; wherein the pixel array comprises a repeating subpixel matrix consisting of 8 subpixels arranged in a first to fourth directly adjacent rows of subpixels and first to second directly adjacent columns of subpixels, wherein the first row of the repeating subpixel matrix consists of a first-color subpixel (B11, B12) in the first column and a second-color subpixel (R11, R12) in the second column, wherein the second row of the repeating subpixel matrix consists of a third-color subpixel (W21, W22) in the first column and a fourth-color subpixel (G21, G22) in the second column, wherein the third row of the repeating subpixel matrix consists of a second-color subpixel (R31, R32) in the first column and a first-color subpixel (B31, B32) in the second column, wherein the fourth row of the repeating subpixel matrix consists of a fourth-color subpixel (G41, G42) in the first column and a third-color subpixel (W41, W42) in the second column, wherein the TFT of each of the subpixels of the first and third rows of the repeating subpixel matrix is connected to a respective directly adjacent data line on the right side of the subpixel, and wherein the TFT of each of the subpixels of the second and fourth rows of the repeating subpixel matrix is connected to a respective directly adjacent data line on the left side of the subpixel; wherein a gate electrode of the TFT of each of the subpixels of each row is connected to a gate line uniquely corresponding to each row; wherein the data driver has source ICs, wherein data output channels of the source ICs are connected to the plurality of data lines (S1 to Sm), wherein the source ICs are configured to receive the data voltages and a polarity control signal from the timing controller and are configured to reverse the polarity of data voltages supplied through one data line in response to the polarity control signal for charging subpixels on a preset cycle and are configured to supply the data voltages to the data lines (S1 to Sm), wherein the timing controller and the source ICs are configured such that, in response to the polarity control signal, the polarity of the data voltages supplied to each of the data lines is reversed every 4 horizontal periods, wherein the timing controller is configured to generate a polarity control signal for each of the source ICs so that there is a difference of 2 horizontal periods between the polarity reversal timing of data voltages supplied to odd-numbered data lines and the polarity reversal timing of data voltages supplied to even-numbered data lines so that neighbouring subpixels of the same color in the same row have opposite polarity and that neighbouring subpixels of the same color in the same column have opposite polarity.