A current compensation sensing circuit comprising an input terminal, an output terminal, a fully differential operational amplifier, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, and an outputting circuit for amplifying an induced current; wherein one end of the first switch is connected to the input terminal of the external compensation sensing circuit, and the input terminal of the external compensation sensing circuit is connected to receive an input current from a display panel; a negative input terminal of the fully differential operational amplifier is connected to the other end of the first switch, a positive input terminal of the fully differential operational amplifier is connected to a reference voltage, a negative output terminal of the fully differential operational amplifier is connected to a first control terminal of the outputting circuit, and a positive output terminal of the fully differential operational amplifier is connected to a second control terminal of the outputting circuit; the first capacitor and the second switch are connected in parallel, both one terminal of the first capacitor and one end of the second switch are connected to the negative input terminal of the fully differential operational amplifier, and both the other terminal of the first capacitor and the other end of the second switch are connected to an input terminal of the outputting circuit; an output terminal of the outputting circuit is connected to one end of the third switch, and the other end of the third switch is connected to both one terminal of the second capacitor and the output terminal of the current compensating sensing circuit, wherein the other terminal of the second capacitor is grounded; wherein the outputting circuit includes a first outputting circuit and a second outputting circuit, the first outputting circuit includes a first N-type MOS transistor and a first P-type MOS transistor, the gate of the first N-type MOS transistor is the first control terminal of the outputting circuit, the gate of the first P-type MOS transistor is the second control terminal of the outputting circuit, the source of the first N-type MOS transistor and the drain of the first P-type MOS transistor are connected to form the input terminal of the outputting circuit, the drain of the first N-type MOS transistor is grounded, and a source of the first P-type MOS transistor is connected to a power supply; the second outputting circuit includes a second N-type MOS transistor and a second P-type MOS transistor, the source of the second N-type MOS transistor and the drain of the second P-type MOS transistor are connected to form the output terminal of the outputting circuit, the drain of the second N-type MOS transistor is grounded, and the source of the second P-type MOS transistor is connected to the power supply, wherein a width to length ratio of the second N-type MOS transistor in the second outputting circuit is M times of a width to length ratio of the first N-type MOS transistor in the first outputting circuit, and a width to length ratio of the second P-type MOS transistor in the second outputting circuit is M times of a width to length ratio of the first P-type MOS transistor in the first outputting circuit, wherein M is greater than 1 and less than 100.