A method for manufacturing an OLED display having a plurality of current driven pixels (20a, 20b, 20c, 20d) arranged in rows and columns disposed over a display substrate, such that when current is provided to a pixel it produces light, the OLED display comprising: (a) each pixel having first and second electrodes (161a, 169) and a current responsive electroluminescent media disposed between the first and second electrodes; (b) at least one chiplet (120, 300) having a thickness less than 20 micrometers; including transistor drive circuitry (340a, 340b, 340c, 340d) configured for controlling the operation of exactly four pixels, the chiplet being mounted on the display substrate and having connection pads (353a, 353b, 353c, 353d); wherein the chiplet has a width and a length that is greater than the width, and the connection pads of the chiplet are arranged in a first and second row along the direction of the length; (c) a planarization layer disposed over at least a portion of the chiplet; (d) a first conductive layer disposed over the planarization layer and connected to at least one of the connection pads of the chiplet; and (e) means for providing electrical signals through the first conductive layer and at least one of the connection pads of the chiplet so that the transistor drive circuitry of the chiplet controls current to the four pixels; (f) a power line arranged parallel to the width of the chiplet; the method comprising the following steps: - using a silicon-on-insulator SOI technique, forming the chiplets as integrated circuits from an integrated circuit substrate; - performing undercut release etch to partially separate the chiplets from the integrated circuit substrate; - providing the display substrate with an adhesion layer; - picking up the chiplets with a stamp; - stamping the chiplets into the adhesion layer; and, for each chiplet: - forming the planarization layer; - patterning the planarization layer to open first vias; - forming the first conductive layer in the first vias; - forming the first electrode and connecting the first electrode to the first conductive layer though second vias; - forming the current responsive electroluminescent media; and - forming the second electrode. (a) each pixel having first and second electrodes (161a, 169) and a current responsive electroluminescent media disposed between the first and second electrodes; (b) at least one chiplet (120, 300) having a thickness less than 20 micrometers; including transistor drive circuitry (340a, 340b, 340c, 340d) configured for controlling the operation of exactly four pixels, the chiplet being mounted on the display substrate and having connection pads (353a, 353b, 353c, 353d); wherein the chiplet has a width and a length that is greater than the width, and the connection pads of the chiplet are arranged in a first and second row along the direction of the length; (c) a planarization layer disposed over at least a portion of the chiplet; (d) a first conductive layer disposed over the planarization layer and connected to at least one of the connection pads of the chiplet; and (e) means for providing electrical signals through the first conductive layer and at least one of the connection pads of the chiplet so that the transistor drive circuitry of the chiplet controls current to the four pixels; (f) a power line arranged parallel to the width of the chiplet; the method comprising the following steps: - using a silicon-on-insulator SOI technique, forming the chiplets as integrated circuits from an integrated circuit substrate; - performing undercut release etch to partially separate the chiplets from the integrated circuit substrate; - providing the display substrate with an adhesion layer; - picking up the chiplets with a stamp; - stamping the chiplets into the adhesion layer; and, for each chiplet: - forming the planarization layer; - patterning the planarization layer to open first vias; - forming the first conductive layer in the first vias; - forming the first electrode and connecting the first electrode to the first conductive layer though second vias; - forming the current responsive electroluminescent media; and - forming the second electrode. - using a silicon-on-insulator SOI technique, forming the chiplets as integrated circuits from an integrated circuit substrate; - performing undercut release etch to partially separate the chiplets from the integrated circuit substrate; - providing the display substrate with an adhesion layer; - picking up the chiplets with a stamp; - stamping the chiplets into the adhesion layer; - forming the planarization layer; - patterning the planarization layer to open first vias; - forming the first conductive layer in the first vias; - forming the first electrode and connecting the first electrode to the first conductive layer though second vias; - forming the current responsive electroluminescent media; and - forming the second electrode.