A semiconductor device configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising: a first semiconductor die and a second semiconductor die; a first isolating block positioned on the first semiconductor die; a second isolating block positioned on the second semiconductor die; a first interconnect coil having a plurality of wires (150, 152, 154, 156, 158, 159) connecting the first semiconductor die to the second isolating block, wherein the plurality of wires (150, 152, 154, 156, 158, 159) of the first interconnect coil includes a first wire and a second wire, at one end connected to each other via a first conductive trace positioned on the top surface of the second isolating block and, at another end respectively connected to first and second conductive traces (170; 172) positioned on the top surface of the first semiconductor die, each of the first wire and second wire connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires (180, 182, 184, 186, 188, 189) connecting the second semiconductor die to the first isolating block, wherein the plurality of wires (180, 182, 184, 186, 188, 189) of the second interconnect coil includes a first wire and a second wire, at one end connected to each other via a first conductive trace positioned on the top surface of the first isolating block and, at another end respectively connected to first and second conductive traces (196; 197) positioned on the top surface of the second semiconductor die, each of the first wire and second wire connecting the second semiconductor die to the first isolating block. a first semiconductor die and a second semiconductor die; a first isolating block positioned on the first semiconductor die; a second isolating block positioned on the second semiconductor die; a first interconnect coil having a plurality of wires (150, 152, 154, 156, 158, 159) connecting the first semiconductor die to the second isolating block, wherein the plurality of wires (150, 152, 154, 156, 158, 159) of the first interconnect coil includes a first wire and a second wire, at one end connected to each other via a first conductive trace positioned on the top surface of the second isolating block and, at another end respectively connected to first and second conductive traces (170; 172) positioned on the top surface of the first semiconductor die, each of the first wire and second wire connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires (180, 182, 184, 186, 188, 189) connecting the second semiconductor die to the first isolating block, wherein the plurality of wires (180, 182, 184, 186, 188, 189) of the second interconnect coil includes a first wire and a second wire, at one end connected to each other via a first conductive trace positioned on the top surface of the first isolating block and, at another end respectively connected to first and second conductive traces (196; 197) positioned on the top surface of the second semiconductor die, each of the first wire and second wire connecting the second semiconductor die to the first isolating block.