A high electron mobility transistor (HEMT) comprising: a first semiconductor layer (C10, C20); a second semiconductor layer (CS10,CS20) configured to induce a 2-dimensional electron gas in the first semiconductor layer; a source and a drain (S10,S20,D10,D20) on at least one of the first semiconductor layer and the second semiconductor layer, the source and drain being spaced apart from a gate, wherein: an upper surface of the second semiconductor layer defines a recess region (R10,R20); and an insulating mask layer (M1,M2,M10,M11,M20,M21,M22) on the second semiconductor layer, the insulating mask layer defining an opening that exposes one of a portion of the first semiconductor layer and a portion of the second semiconductor layer; a p-doped depletion forming layer (DP10,DP11,DP1,DP12,DP20,DP21,DP22) on the one of the portion of the first semiconductor layer and the portion of the second semiconductor layer that is exposed by the opening in the insulating mask layer, the depletion forming layer being configured to form a depletion region in the 2DEG; the gate (G10,G20) on the depletion forming layer; and the opening in the insulating mask layer exposes one of an upper surface of the first semiconductor layer and at least a portion of the recess region, and the depletion forming layer is in the recess region (R10,R20) of the second semiconductor layer, wherein the insulating mask layer (M1,M2,M10,M11,M20,M21,M22) is on the upper surface of the second semiconductor layer and an inner side surface of the recess region of the second semiconductor layer, and the opening in the insulating mask layer exposes one of a bottom surface of the recess region of the second semiconductor layer and the upper surface of the first semiconductor layer. a first semiconductor layer (C10, C20); a second semiconductor layer (CS10,CS20) configured to induce a 2-dimensional electron gas in the first semiconductor layer; a source and a drain (S10,S20,D10,D20) on at least one of the first semiconductor layer and the second semiconductor layer, the source and drain being spaced apart from a gate, wherein: an upper surface of the second semiconductor layer defines a recess region (R10,R20); and an insulating mask layer (M1,M2,M10,M11,M20,M21,M22) on the second semiconductor layer, the insulating mask layer defining an opening that exposes one of a portion of the first semiconductor layer and a portion of the second semiconductor layer; a p-doped depletion forming layer (DP10,DP11,DP1,DP12,DP20,DP21,DP22) on the one of the portion of the first semiconductor layer and the portion of the second semiconductor layer that is exposed by the opening in the insulating mask layer, the depletion forming layer being configured to form a depletion region in the 2DEG; the gate (G10,G20) on the depletion forming layer; and the opening in the insulating mask layer exposes one of an upper surface of the first semiconductor layer and at least a portion of the recess region, and the depletion forming layer is in the recess region (R10,R20) of the second semiconductor layer, wherein the insulating mask layer (M1,M2,M10,M11,M20,M21,M22) is on the upper surface of the second semiconductor layer and an inner side surface of the recess region of the second semiconductor layer, and the opening in the insulating mask layer exposes one of a bottom surface of the recess region of the second semiconductor layer and the upper surface of the first semiconductor layer. an upper surface of the second semiconductor layer defines a recess region (R10,R20); and an insulating mask layer (M1,M2,M10,M11,M20,M21,M22) on the second semiconductor layer, the insulating mask layer defining an opening that exposes one of a portion of the first semiconductor layer and a portion of the second semiconductor layer; a p-doped depletion forming layer (DP10,DP11,DP1,DP12,DP20,DP21,DP22) on the one of the portion of the first semiconductor layer and the portion of the second semiconductor layer that is exposed by the opening in the insulating mask layer, the depletion forming layer being configured to form a depletion region in the 2DEG; the gate (G10,G20) on the depletion forming layer; and the opening in the insulating mask layer exposes one of an upper surface of the first semiconductor layer and at least a portion of the recess region, and the depletion forming layer is in the recess region (R10,R20) of the second semiconductor layer, wherein the insulating mask layer (M1,M2,M10,M11,M20,M21,M22) is on the upper surface of the second semiconductor layer and an inner side surface of the recess region of the second semiconductor layer, and the opening in the insulating mask layer exposes one of a bottom surface of the recess region of the second semiconductor layer and the upper surface of the first semiconductor layer.