A vertical field effect transistor, FET, structure comprising: a silicon carbide substrate (12, 36) having a top surface and a bottom surface opposite the top surface; a drain/collector contact (28, 52) on the bottom surface of the silicon carbide substrate (12, 36); an epitaxial structure (14, 38) of a first doping type on the top surface of the silicon carbide substrate (12, 36) and having formed therein a first source/emitter region (16, 40) that comprises a first source/emitter implant (20, 44) of the first doping type that is arranged within a first source/emitter well (18, 42) of a second, opposite doping type, a second source/emitter region (16, 40) that comprises a second source/emitter implant (20, 44) of the first doping type that is arranged within a second source/emitter well (18, 42) of the second doping type), and a JFET region formed between the first and second source/emitter regions (16, 40); a gate dielectric (22, 46) on a portion of the epitaxial structure (14, 38); a first plurality of discontinuous source/emitter contact segments (26, 50) spaced apart from each other and directly on a continuous portion of the first source/emitter implant (20, 44) such that the gate dielectric (22, 46) is not below the first plurality of discontinuous source/emitter contact segments (26, 50); a first elongated gate contact (24, 48) and a second elongated gate contact (24, 48) on the gate dielectric (22, 46) and positioned such that the first source/emitter implant (20, 44) is below and between the first elongated gate contact (24, 48) and the second elongated gate contact (24, 48); and a first plurality of inter-gate plates that extend from at least one of the first elongated gate contact (24, 48) and the second elongated gate contact (24, 48) into spaces formed between the first plurality of discontinuous source/emitter contact segments (26, 50), wherein the first plurality of inter-gate plates are separated from the first source/emitter implant (20, 44) by the gate dielectric (22, 46), characterised in that the inter-gate plates do not extend completely between the first elongated gate contact (24, 48) and the second elongated gate contact (24, 48). a silicon carbide substrate (12, 36) having a top surface and a bottom surface opposite the top surface; a drain/collector contact (28, 52) on the bottom surface of the silicon carbide substrate (12, 36); an epitaxial structure (14, 38) of a first doping type on the top surface of the silicon carbide substrate (12, 36) and having formed therein a first source/emitter region (16, 40) that comprises a first source/emitter implant (20, 44) of the first doping type that is arranged within a first source/emitter well (18, 42) of a second, opposite doping type, a second source/emitter region (16, 40) that comprises a second source/emitter implant (20, 44) of the first doping type that is arranged within a second source/emitter well (18, 42) of the second doping type), and a JFET region formed between the first and second source/emitter regions (16, 40); a gate dielectric (22, 46) on a portion of the epitaxial structure (14, 38); a first plurality of discontinuous source/emitter contact segments (26, 50) spaced apart from each other and directly on a continuous portion of the first source/emitter implant (20, 44) such that the gate dielectric (22, 46) is not below the first plurality of discontinuous source/emitter contact segments (26, 50); a first elongated gate contact (24, 48) and a second elongated gate contact (24, 48) on the gate dielectric (22, 46) and positioned such that the first source/emitter implant (20, 44) is below and between the first elongated gate contact (24, 48) and the second elongated gate contact (24, 48); and a first plurality of inter-gate plates that extend from at least one of the first elongated gate contact (24, 48) and the second elongated gate contact (24, 48) into spaces formed between the first plurality of discontinuous source/emitter contact segments (26, 50), wherein the first plurality of inter-gate plates are separated from the first source/emitter implant (20, 44) by the gate dielectric (22, 46), characterised in that the inter-gate plates do not extend completely between the first elongated gate contact (24, 48) and the second elongated gate contact (24, 48).