A semiconductor device comprising: a timer unit having: a binary counter, and a first converter configured to convert a first count value output from the binary counter to a gray code to output as first gray code data (CNTVALUEG), characterized by a processing unit having: a first synchronizer configured to capture the first gray code data (CNTVALUEG) transferred from the timer unit in synchronization with a system clock signal to output as second gray code data (CNTVALUEGS_m), and a fault detection unit configured to generate data for fault detection (CNTVALUEGS_c) based on the first gray code data (CNTVALUEG) transferred from the timer unit, compare a second count value indicated by the second gray code data (CNTVALUEGS_m) with a third count value indicated by the data for fault detection (CNTVALUEGS_c) to detect a difference between the second count value and the third count value, and output a fault detection signal indicating whether a fault is detected based on a comparison result, wherein the first synchronizer receives the first gray code data (CNTVALUEG) through a first path from the first converter, and wherein the fault detection unit further includes a second synchronizer for capturing the first gray code data (CNTVALUEG) transferred through a second path, which is different from the first path, from the first converter in synchronization with the system clock signal to output as the data for fault detection (CNTVALUEGS_c). a timer unit having: a binary counter, and a first converter configured to convert a first count value output from the binary counter to a gray code to output as first gray code data (CNTVALUEG), characterized by a binary counter, and a first converter configured to convert a first count value output from the binary counter to a gray code to output as first gray code data (CNTVALUEG), characterized by a processing unit having: a first synchronizer configured to capture the first gray code data (CNTVALUEG) transferred from the timer unit in synchronization with a system clock signal to output as second gray code data (CNTVALUEGS_m), and a fault detection unit configured to generate data for fault detection (CNTVALUEGS_c) based on the first gray code data (CNTVALUEG) transferred from the timer unit, compare a second count value indicated by the second gray code data (CNTVALUEGS_m) with a third count value indicated by the data for fault detection (CNTVALUEGS_c) to detect a difference between the second count value and the third count value, and output a fault detection signal indicating whether a fault is detected based on a comparison result, a first synchronizer configured to capture the first gray code data (CNTVALUEG) transferred from the timer unit in synchronization with a system clock signal to output as second gray code data (CNTVALUEGS_m), and a fault detection unit configured to generate data for fault detection (CNTVALUEGS_c) based on the first gray code data (CNTVALUEG) transferred from the timer unit, compare a second count value indicated by the second gray code data (CNTVALUEGS_m) with a third count value indicated by the data for fault detection (CNTVALUEGS_c) to detect a difference between the second count value and the third count value, and output a fault detection signal indicating whether a fault is detected based on a comparison result, wherein the first synchronizer receives the first gray code data (CNTVALUEG) through a first path from the first converter, and wherein the fault detection unit further includes a second synchronizer for capturing the first gray code data (CNTVALUEG) transferred through a second path, which is different from the first path, from the first converter in synchronization with the system clock signal to output as the data for fault detection (CNTVALUEGS_c).