A smart IC module comprising: a smart IC substrate; and a chip disposed on the smart IC substrate, wherein the smart IC substrate comprising: a substrate including one surface and the other surface on which a chip mounting region is formed; a circuit pattern on the one surface of the substrate; a connection circuit pattern disposed on the one surface of the substrate and spaced apart from the circuit pattern; and a coil pattern disposed on the other surface of the substrate and including a first terminal provided at one end and a second terminal provided at the other end, the substrate includes a first region disposed inside the coil pattern and a second region disposed outside the coil pattern, the first terminal is disposed in the first region, the second terminal is disposed in the second region, characterized in that: the substrate includes a first via formed in the first region corresponding to the circuit pattern, a second via formed in the second region corresponding to one end of the connection circuit pattern, and a third via formed in the first region corresponding to the other end of the connection circuit pattern, a connection member is disposed in the second via and electrically connects between the one end of the connection circuit pattern and the second terminal, and the chip is bonded to the other end of the connection circuit pattern exposed through the third via by a wire.- a smart IC substrate; and a chip disposed on the smart IC substrate, wherein the smart IC substrate comprising: a substrate including one surface and the other surface on which a chip mounting region is formed; a circuit pattern on the one surface of the substrate; a connection circuit pattern disposed on the one surface of the substrate and spaced apart from the circuit pattern; and a coil pattern disposed on the other surface of the substrate and including a first terminal provided at one end and a second terminal provided at the other end, the substrate includes a first region disposed inside the coil pattern and a second region disposed outside the coil pattern, the first terminal is disposed in the first region, the second terminal is disposed in the second region, characterized in that: the substrate includes a first via formed in the first region corresponding to the circuit pattern, a second via formed in the second region corresponding to one end of the connection circuit pattern, and a third via formed in the first region corresponding to the other end of the connection circuit pattern, a connection member is disposed in the second via and electrically connects between the one end of the connection circuit pattern and the second terminal, and the chip is bonded to the other end of the connection circuit pattern exposed through the third via by a wire.- a substrate including one surface and the other surface on which a chip mounting region is formed; a circuit pattern on the one surface of the substrate; a connection circuit pattern disposed on the one surface of the substrate and spaced apart from the circuit pattern; and a coil pattern disposed on the other surface of the substrate and including a first terminal provided at one end and a second terminal provided at the other end, the substrate includes a first region disposed inside the coil pattern and a second region disposed outside the coil pattern, the first terminal is disposed in the first region, the second terminal is disposed in the second region, characterized in that: the substrate includes a first via formed in the first region corresponding to the circuit pattern, a second via formed in the second region corresponding to one end of the connection circuit pattern, and a third via formed in the first region corresponding to the other end of the connection circuit pattern, a connection member is disposed in the second via and electrically connects between the one end of the connection circuit pattern and the second terminal, and the chip is bonded to the other end of the connection circuit pattern exposed through the third via by a wire.- the substrate includes a first via formed in the first region corresponding to the circuit pattern, a second via formed in the second region corresponding to one end of the connection circuit pattern, and a third via formed in the first region corresponding to the other end of the connection circuit pattern, a connection member is disposed in the second via and electrically connects between the one end of the connection circuit pattern and the second terminal, and the chip is bonded to the other end of the connection circuit pattern exposed through the third via by a wire.-