A graphics processing unit comprising: a single instruction, multiple thread, SIMT, multiprocessor comprising: an instruction cache; a shared memory coupled with the instruction cache; circuitry coupled with the shared memory and the instruction cache, the circuitry including: multiple texture units to perform texture mapping operations; a first core including hardware to accelerate matrix operations; a second core configured to: receive an instruction having multiple operands in a bfloat16, BF16, number format, wherein the multiple operands include a first source operand in the BF16 number format, a second source operand in the BF16 number format, and a third source operand in the BF16 number format, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent; and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply, the result being in the BF16 number format, wherein the instruction cache is shared by the first core and the second core, wherein the SIMT multiprocessor is to execute a warp of threads in response to the instruction, and wherein the second core is further configured to flush subnormal numbers to zero. a single instruction, multiple thread, SIMT, multiprocessor comprising: an instruction cache; a shared memory coupled with the instruction cache; circuitry coupled with the shared memory and the instruction cache, the circuitry including: multiple texture units to perform texture mapping operations; a first core including hardware to accelerate matrix operations; a second core configured to: receive an instruction having multiple operands in a bfloat16, BF16, number format, wherein the multiple operands include a first source operand in the BF16 number format, a second source operand in the BF16 number format, and a third source operand in the BF16 number format, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent; and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply, the result being in the BF16 number format, an instruction cache; a shared memory coupled with the instruction cache; circuitry coupled with the shared memory and the instruction cache, the circuitry including: multiple texture units to perform texture mapping operations; a first core including hardware to accelerate matrix operations; a second core configured to: receive an instruction having multiple operands in a bfloat16, BF16, number format, wherein the multiple operands include a first source operand in the BF16 number format, a second source operand in the BF16 number format, and a third source operand in the BF16 number format, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent; and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply, the result being in the BF16 number format, multiple texture units to perform texture mapping operations; a first core including hardware to accelerate matrix operations; a second core configured to: receive an instruction having multiple operands in a bfloat16, BF16, number format, wherein the multiple operands include a first source operand in the BF16 number format, a second source operand in the BF16 number format, and a third source operand in the BF16 number format, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent; and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply, the result being in the BF16 number format, receive an instruction having multiple operands in a bfloat16, BF16, number format, wherein the multiple operands include a first source operand in the BF16 number format, a second source operand in the BF16 number format, and a third source operand in the BF16 number format, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent; and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply, the result being in the BF16 number format, wherein the instruction cache is shared by the first core and the second core, wherein the SIMT multiprocessor is to execute a warp of threads in response to the instruction, and wherein the second core is further configured to flush subnormal numbers to zero.