A computing system comprising: a host to transfer data, coupled with a memory device (130; 500) wherein said memory device is configurable in an error check mode and in a non-error check mode, respectively, said memory comprising: a split bank pair (502, 504) of memory banks (502, 504) including a first memory bank and a second memory bank wherein when the memory device is configured in the error check mode, data is arranged to be stored in the first memory bank and corresponding host generated error check bits are arranged to be stored in the second memory bank, and vice-versa, and wherein, when the memory device is configured in the non-error check mode, data is arranged to be stored in both the first memory bank and in the second memory bank without corresponding error check bits; ECC computation logic to receive the data from the first memory bank and to generate locally generated error check bits based on the data, when the memory device is configured in the error check mode and is operating in self-refresh mode; a comparator to compare the host generated error check bits stored in the second memory bank with the locally generated error check bits; and error correction logic to correct an error in the data if the host generated error check bits stored in the second memory bank do not match the locally generated error check bits; an oscillator to control a self-refresh frequency, wherein the self-refresh frequency is selected, at least in part, to allow single bit errors in the data and wherein the oscillator dynamically controls the self-refresh frequency based, at least in part, on error information or based, at least in part, on input from the host; and error tracking logic to track errors in the data that are detected during self-refresh and to provide the error information to the host, enabling the host to adjust the self-refresh frequency by adjusting the oscillator. a host to transfer data, coupled with a memory device (130; 500) wherein said memory device is configurable in an error check mode and in a non-error check mode, respectively, said memory comprising: a split bank pair (502, 504) of memory banks (502, 504) including a first memory bank and a second memory bank wherein when the memory device is configured in the error check mode, data is arranged to be stored in the first memory bank and corresponding host generated error check bits are arranged to be stored in the second memory bank, and vice-versa, and wherein, when the memory device is configured in the non-error check mode, data is arranged to be stored in both the first memory bank and in the second memory bank without corresponding error check bits; ECC computation logic to receive the data from the first memory bank and to generate locally generated error check bits based on the data, when the memory device is configured in the error check mode and is operating in self-refresh mode; a comparator to compare the host generated error check bits stored in the second memory bank with the locally generated error check bits; and error correction logic to correct an error in the data if the host generated error check bits stored in the second memory bank do not match the locally generated error check bits; an oscillator to control a self-refresh frequency, wherein the self-refresh frequency is selected, at least in part, to allow single bit errors in the data and wherein the oscillator dynamically controls the self-refresh frequency based, at least in part, on error information or based, at least in part, on input from the host; and error tracking logic to track errors in the data that are detected during self-refresh and to provide the error information to the host, enabling the host to adjust the self-refresh frequency by adjusting the oscillator. a split bank pair (502, 504) of memory banks (502, 504) including a first memory bank and a second memory bank wherein when the memory device is configured in the error check mode, data is arranged to be stored in the first memory bank and corresponding host generated error check bits are arranged to be stored in the second memory bank, and vice-versa, and wherein, when the memory device is configured in the non-error check mode, data is arranged to be stored in both the first memory bank and in the second memory bank without corresponding error check bits; ECC computation logic to receive the data from the first memory bank and to generate locally generated error check bits based on the data, when the memory device is configured in the error check mode and is operating in self-refresh mode; a comparator to compare the host generated error check bits stored in the second memory bank with the locally generated error check bits; and error correction logic to correct an error in the data if the host generated error check bits stored in the second memory bank do not match the locally generated error check bits; an oscillator to control a self-refresh frequency, wherein the self-refresh frequency is selected, at least in part, to allow single bit errors in the data and wherein the oscillator dynamically controls the self-refresh frequency based, at least in part, on error information or based, at least in part, on input from the host; and error tracking logic to track errors in the data that are detected during self-refresh and to provide the error information to the host, enabling the host to adjust the self-refresh frequency by adjusting the oscillator.