A hardware acceleration component, comprising: a plurality of hardware processing clusters, each hardware processing cluster comprising a plurality of soft processor cores and a functional circuit, wherein the plurality of soft processor cores share the functional circuit; wherein: the hardware acceleration component is a free form expression executing hardware acceleration component; the functional circuit comprising one or more of a floating point divide circuit, a natural logarithm circuit, an exponent circuit, and a floating point-to-integer circuit; each of the plurality of soft processor cores comprising a plurality of hardware threads (T0-T3); and a software thread assignor configured to assign software threads to the hardware threads (T0-T3) based on a length of each software thread and a priority assigned to each of the hardware threads, such that where there are hardware threads T0, T1, T2, T3 with priorities that range from highest T0 to lowest T3, software threads with a length L greater than or equal to L1 are assigned to hardware thread T0, software threads that have a length L greater than or equal to L2 and less than L1 are assigned to hardware thread T1, software threads that have a length L greater than or equal to L3 and less than L2 are assigned to hardware thread T2, and software threads that have a length L less than length L3 are assigned to hardware thread T3, where L3 is less than L2 and where L2 is less than L1; wherein the software threads are free form expression software threads. a plurality of hardware processing clusters, each hardware processing cluster comprising a plurality of soft processor cores and a functional circuit, wherein the plurality of soft processor cores share the functional circuit; wherein: the hardware acceleration component is a free form expression executing hardware acceleration component; the functional circuit comprising one or more of a floating point divide circuit, a natural logarithm circuit, an exponent circuit, and a floating point-to-integer circuit; each of the plurality of soft processor cores comprising a plurality of hardware threads (T0-T3); and a software thread assignor configured to assign software threads to the hardware threads (T0-T3) based on a length of each software thread and a priority assigned to each of the hardware threads, such that where there are hardware threads T0, T1, T2, T3 with priorities that range from highest T0 to lowest T3, software threads with a length L greater than or equal to L1 are assigned to hardware thread T0, software threads that have a length L greater than or equal to L2 and less than L1 are assigned to hardware thread T1, software threads that have a length L greater than or equal to L3 and less than L2 are assigned to hardware thread T2, and software threads that have a length L less than length L3 are assigned to hardware thread T3, where L3 is less than L2 and where L2 is less than L1; wherein the software threads are free form expression software threads. the hardware acceleration component is a free form expression executing hardware acceleration component; the functional circuit comprising one or more of a floating point divide circuit, a natural logarithm circuit, an exponent circuit, and a floating point-to-integer circuit; each of the plurality of soft processor cores comprising a plurality of hardware threads (T0-T3); and a software thread assignor configured to assign software threads to the hardware threads (T0-T3) based on a length of each software thread and a priority assigned to each of the hardware threads, such that where there are hardware threads T0, T1, T2, T3 with priorities that range from highest T0 to lowest T3, software threads with a length L greater than or equal to L1 are assigned to hardware thread T0, software threads that have a length L greater than or equal to L2 and less than L1 are assigned to hardware thread T1, software threads that have a length L greater than or equal to L3 and less than L2 are assigned to hardware thread T2, and software threads that have a length L less than length L3 are assigned to hardware thread T3, where L3 is less than L2 and where L2 is less than L1; wherein the software threads are free form expression software threads.