A method for controlling a magnetoresistive random access memory, MRAM, bit-cell comprising: a first transistor, a second transistor, and a resistive memory element, comprising a magnetic tunnel junction, MTJ, pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal; wherein the gates of the first and second transistors are connected to a common word line, the first terminal of the bottom electrode is connected to a first source/drain terminal of first transistor, a second source/drain terminal of the first transistor is connected to a write bit line, the second terminal of the bottom electrode is connected to a first read bit line, the top electrode is connected to a first source/drain terminal of the second transistor, and a second source/drain terminal of the second transistor is connected to a second read bit line, characterized in that the method comprises the steps of: applying a first supply voltage to the common word line, applying a second supply voltage to the second read bit line, the first supply voltage and the second supply voltage representing different voltage levels, and changing a state of the resistive memory element from a first state to a second state by: applying the first supply voltage to the write bit line and applying the second supply voltage to the first read bit line, thereby generating a first spin orbit torque, SOT, generating current through the bottom electrode and a spin transfer torque, STT, generating current through the MTJ pillar; and changing the state of the resistive memory element from the second state to the first state by: applying the first supply voltage to the first read bit line and applying the second supply voltage to the write bit line, thereby generating a second SOT generating current through the bottom electrode and an STT generating current through the MTJ pillar. a first transistor, a second transistor, and a resistive memory element, comprising a magnetic tunnel junction, MTJ, pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal; wherein the gates of the first and second transistors are connected to a common word line, the first terminal of the bottom electrode is connected to a first source/drain terminal of first transistor, a second source/drain terminal of the first transistor is connected to a write bit line, the second terminal of the bottom electrode is connected to a first read bit line, the top electrode is connected to a first source/drain terminal of the second transistor, and a second source/drain terminal of the second transistor is connected to a second read bit line, characterized in that the method comprises the steps of: applying a first supply voltage to the common word line, applying a second supply voltage to the second read bit line, the first supply voltage and the second supply voltage representing different voltage levels, and changing a state of the resistive memory element from a first state to a second state by: applying a first supply voltage to the common word line, applying a second supply voltage to the second read bit line, the first supply voltage and the second supply voltage representing different voltage levels, and changing a state of the resistive memory element from a first state to a second state by: applying the first supply voltage to the write bit line and applying the second supply voltage to the first read bit line, thereby generating a first spin orbit torque, SOT, generating current through the bottom electrode and a spin transfer torque, STT, generating current through the MTJ pillar; and changing the state of the resistive memory element from the second state to the first state by: applying the first supply voltage to the first read bit line and applying the second supply voltage to the write bit line, thereby generating a second SOT generating current through the bottom electrode and an STT generating current through the MTJ pillar. applying the first supply voltage to the first read bit line and applying the second supply voltage to the write bit line, thereby generating a second SOT generating current through the bottom electrode and an STT generating current through the MTJ pillar.