A method of fabricating and programming an apparatus comprising a plurality of fin-type field effect transistors, FinFETs, wherein each FinFET is used as a bit cell configured to store a single data bit and to operate in a hold phase and in a write phase, wherein fabricating each FinFET comprises: forming a bottom gate (108, 208) of a FinFET (100, 200) within a substrate (112, 212) having a top surface; forming a buried oxide, BOX, layer (110, 210) within the substrate, the BOX layer above and adjacent to the bottom gate (108, 208) at a first BOX layer face; forming a fin, which is a raised elongate source-to-drain channel (102, 202), wherein at least a portion of the fin extends and protrudes away from the top surface of the substrate, wherein the fin has a first fin face (116, 214) adjacent a second BOX layer face of the BOX layer, and wherein the bottom gate is electrically coupled to the fin through the BOX layer; forming a second gate (104, 204) adjacent to the fin at a second fin face (118, 216) and above the top surface of the substrate, the second gate separated from the second fin face by a first oxide layer; forming a third gate (106, 206) adjacent to the fin at a third fin face (120, 218) and above the top surface of the substrate, the third gate separated from the third fin face by a second oxide layer; and forming a top gate, wherein the top gate is electrically coupled to the fin at a fourth fin face and separated from the fourth fin face by a third oxide layer; forming a first, second, third and fourth gate write and hold logic control circuit of the apparatus to control, respectively, the bottom gate, the second gate, the third gate and the top gate of each FinFET; wherein the bottom gate, the second gate, the third gate and the top gate are each independently electrically biasable; wherein programming the apparatus comprises controlling the FinFET to be in the hold phase, comprising independently biasing: the bottom gate of each FinFET at a first hold bias voltage by the first gate write and hold logic control circuit of the apparatus, the second gate of each FinFET at a second hold bias voltage by the second gate write and hold logic control circuit of the apparatus, the third gate of each FinFET at a third hold bias voltage by the third gate write and hold logic control circuit of the apparatus, and the top gate of each FinFET at a fourth hold bias voltage by the fourth gate write and hold logic control circuit of the apparatus. forming a bottom gate (108, 208) of a FinFET (100, 200) within a substrate (112, 212) having a top surface; forming a buried oxide, BOX, layer (110, 210) within the substrate, the BOX layer above and adjacent to the bottom gate (108, 208) at a first BOX layer face; forming a fin, which is a raised elongate source-to-drain channel (102, 202), wherein at least a portion of the fin extends and protrudes away from the top surface of the substrate, wherein the fin has a first fin face (116, 214) adjacent a second BOX layer face of the BOX layer, and wherein the bottom gate is electrically coupled to the fin through the BOX layer; forming a second gate (104, 204) adjacent to the fin at a second fin face (118, 216) and above the top surface of the substrate, the second gate separated from the second fin face by a first oxide layer; forming a third gate (106, 206) adjacent to the fin at a third fin face (120, 218) and above the top surface of the substrate, the third gate separated from the third fin face by a second oxide layer; and forming a top gate, wherein the top gate is electrically coupled to the fin at a fourth fin face and separated from the fourth fin face by a third oxide layer; forming a first, second, third and fourth gate write and hold logic control circuit of the apparatus to control, respectively, the bottom gate, the second gate, the third gate and the top gate of each FinFET; wherein the bottom gate, the second gate, the third gate and the top gate are each independently electrically biasable; the bottom gate of each FinFET at a first hold bias voltage by the first gate write and hold logic control circuit of the apparatus, the second gate of each FinFET at a second hold bias voltage by the second gate write and hold logic control circuit of the apparatus, the third gate of each FinFET at a third hold bias voltage by the third gate write and hold logic control circuit of the apparatus, and the top gate of each FinFET at a fourth hold bias voltage by the fourth gate write and hold logic control circuit of the apparatus.