An accumulator-type fractional N-PLL synthesizer comprising: a VCO; a fractional frequency divider, disposed in a feedback path of an output signal of the VCO, for generating a frequency divider output signal of a fractional frequency division number; an accumulator for supplying an overflow signal for periodically switching a frequency division number of the fractional frequency division number, to the fractional frequency divider; and a phase detector for detecting a phase difference between the frequency divider output signal and a predetermined reference signal to generate a control input signal to the VCO based on the detected phase difference, wherein the accumulator is configured to generate an error signal having fractional phase error information, and wherein the phase detector is configured to correct the phase difference between the frequency divider output signal and the reference signal, using the error signal, characterized in that the phase detector includes: a fractional phase error pulse generation circuit for generating a phase error pulse signal having a pulse width proportional to a fractional phase error and generating a feedback signal, based on the frequency divider output signal and the error signal; a frequency and phase detector for generating a frequency and phase detection output signal having a pulse width proportional to a difference in frequency and phase between the reference signal and the feedback signal; and a fractional phase error removal circuit for generating the UP signal and the DN signal with the fractional phase error included in the frequency and phase detection output signal being reduced, based on the phase error pulse signal. a VCO; a fractional frequency divider, disposed in a feedback path of an output signal of the VCO, for generating a frequency divider output signal of a fractional frequency division number; an accumulator for supplying an overflow signal for periodically switching a frequency division number of the fractional frequency division number, to the fractional frequency divider; and a phase detector for detecting a phase difference between the frequency divider output signal and a predetermined reference signal to generate a control input signal to the VCO based on the detected phase difference, wherein the accumulator is configured to generate an error signal having fractional phase error information, and wherein the phase detector is configured to correct the phase difference between the frequency divider output signal and the reference signal, using the error signal, characterized in that the phase detector includes: a fractional phase error pulse generation circuit for generating a phase error pulse signal having a pulse width proportional to a fractional phase error and generating a feedback signal, based on the frequency divider output signal and the error signal; a frequency and phase detector for generating a frequency and phase detection output signal having a pulse width proportional to a difference in frequency and phase between the reference signal and the feedback signal; and a fractional phase error removal circuit for generating the UP signal and the DN signal with the fractional phase error included in the frequency and phase detection output signal being reduced, based on the phase error pulse signal. a fractional phase error pulse generation circuit for generating a phase error pulse signal having a pulse width proportional to a fractional phase error and generating a feedback signal, based on the frequency divider output signal and the error signal; a frequency and phase detector for generating a frequency and phase detection output signal having a pulse width proportional to a difference in frequency and phase between the reference signal and the feedback signal; and a fractional phase error removal circuit for generating the UP signal and the DN signal with the fractional phase error included in the frequency and phase detection output signal being reduced, based on the phase error pulse signal.