A semiconductor structure comprising: a memory-level assembly located over a substrate and including at least one alternating stack ((132, 146), (233, 246)) and memory stack structures vertically extending through the at least one alternating stack, wherein each of the at least one an alternating stack includes alternating layers (132, 232) of respective insulating layers (146, 246) and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion (142', 242') located in the opening contacts a sidewall of the respective electrically conductive layers; at least one through-memory-level via structure that vertically extends through each of the spacer dielectric portions and the insulating layers; and a plurality of laterally-elongated contact via structures that vertically extend through the memory-level assembly, laterally extend along a first horizontal direction, and laterally divide the at least one alternating stack into a plurality of laterally spaced-apart blocks, wherein the spacer dielectric portions (142', 242') are located between a pair of laterally-elongated contact via structures; wherein two or more topmost layers among the electrically conductive layers comprise drain select gate electrodes; each of the drain select gate electrodes is physically divided into multiple portions by a dielectric material portion around the at least one through-memory-level via structure; and a stepped region in which a first drain select electrode extends closer to the at least one through-memory-level via structure than a second drain select electrode located above the first drain select electrode; the semiconductor structure further comprises a pair of drain-select-level shallow trench isolation structures that extend along the first horizontal direction, and the semiconductor structure characterized in that the pair of drain-select-level shallow trench isolation structures along with at least one alternating stack ((132, 142'), (232, 242')) of the respective insulating layers and the spacer dielectric portions divide the two or more electrically conductive layers that comprise the drain select electrodes into three physically disjoined portions, wherein a spacer dielectric portion located at a same level as the pair of drain-select-level shallow trench isolation structures contacts sidewalls of the pair of drain-select-level shallow trench isolation structures. a memory-level assembly located over a substrate and including at least one alternating stack ((132, 146), (233, 246)) and memory stack structures vertically extending through the at least one alternating stack, wherein each of the at least one an alternating stack includes alternating layers (132, 232) of respective insulating layers (146, 246) and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion (142', 242') located in the opening contacts a sidewall of the respective electrically conductive layers; at least one through-memory-level via structure that vertically extends through each of the spacer dielectric portions and the insulating layers; and a plurality of laterally-elongated contact via structures that vertically extend through the memory-level assembly, laterally extend along a first horizontal direction, and laterally divide the at least one alternating stack into a plurality of laterally spaced-apart blocks, wherein the spacer dielectric portions (142', 242') are located between a pair of laterally-elongated contact via structures; wherein two or more topmost layers among the electrically conductive layers comprise drain select gate electrodes; each of the drain select gate electrodes is physically divided into multiple portions by a dielectric material portion around the at least one through-memory-level via structure; and a stepped region in which a first drain select electrode extends closer to the at least one through-memory-level via structure than a second drain select electrode located above the first drain select electrode; the semiconductor structure further comprises a pair of drain-select-level shallow trench isolation structures that extend along the first horizontal direction, and the semiconductor structure characterized in that the pair of drain-select-level shallow trench isolation structures along with at least one alternating stack ((132, 142'), (232, 242')) of the respective insulating layers and the spacer dielectric portions divide the two or more electrically conductive layers that comprise the drain select electrodes into three physically disjoined portions, wherein a spacer dielectric portion located at a same level as the pair of drain-select-level shallow trench isolation structures contacts sidewalls of the pair of drain-select-level shallow trench isolation structures.