A method for forming a semiconductor structure, comprising: providing a substrate, wherein a sacrificial layer and an active layer located on a surface of the sacrificial layer are formed on the substrate; etching the active layer and the sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along a first direction (y); filling an opening located between two adjacent ones of the active lines to form a first isolating layer; etching an end of the active lines to form an opening hole exposing the surface of the substrate, a side wall of the opening holes exposing the sacrificial layer; removing the sacrificial layer along the opening hole, to form a gap between a bottom of the active lines and the substrate; filling a conductive material in the gap to form a bit line extending along the first direction (y); patterning the active lines to form a plurality of separate active pillars that are arrayed along the first direction (y) and a second direction (x); and forming semiconductor pillars on top surfaces of respective ones of the active pillars, characterized in that the method further comprises: filling a conductive material in the opening hole to form a bit-line-connection line in the opening hole, a bottom of the bit-line-connection line being connected to the bit line, wherein the bit-line-connection line and the bit line are formed in a same process; forming a first doped region in the active pillars; forming a channel region above the first doped region and a second doped region above the channel region in the semiconductor pillars; and forming a gate structure surrounding the channel region; forming a second isolating layer covering the gate structure and the second doped region; and forming an interconnect structure connected to the bit-line-connection line through the second isolating layer. providing a substrate, wherein a sacrificial layer and an active layer located on a surface of the sacrificial layer are formed on the substrate; etching the active layer and the sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along a first direction (y); filling an opening located between two adjacent ones of the active lines to form a first isolating layer; etching an end of the active lines to form an opening hole exposing the surface of the substrate, a side wall of the opening holes exposing the sacrificial layer; removing the sacrificial layer along the opening hole, to form a gap between a bottom of the active lines and the substrate; filling a conductive material in the gap to form a bit line extending along the first direction (y); patterning the active lines to form a plurality of separate active pillars that are arrayed along the first direction (y) and a second direction (x); and forming semiconductor pillars on top surfaces of respective ones of the active pillars, characterized in that the method further comprises: filling a conductive material in the opening hole to form a bit-line-connection line in the opening hole, a bottom of the bit-line-connection line being connected to the bit line, wherein the bit-line-connection line and the bit line are formed in a same process; forming a first doped region in the active pillars; forming a channel region above the first doped region and a second doped region above the channel region in the semiconductor pillars; and forming a gate structure surrounding the channel region; forming a second isolating layer covering the gate structure and the second doped region; and forming an interconnect structure connected to the bit-line-connection line through the second isolating layer. filling a conductive material in the opening hole to form a bit-line-connection line in the opening hole, a bottom of the bit-line-connection line being connected to the bit line, wherein the bit-line-connection line and the bit line are formed in a same process; forming a first doped region in the active pillars; forming a channel region above the first doped region and a second doped region above the channel region in the semiconductor pillars; and forming a gate structure surrounding the channel region; forming a second isolating layer covering the gate structure and the second doped region; and forming an interconnect structure connected to the bit-line-connection line through the second isolating layer.