An electronic device (51, 94) having input/output (I/O) and common terminals, comprising: a circuit core coupled between the I/O and common terminals; and characterized by: a plurality of serially arranged resistor triggered bi-directional electrostatic discharge clamp stages (71, 71') coupled between the I/O and common terminals, wherein a first electrostatic discharge clamp stage (41, 71) of the plurality of electrostatic discharge clamp stages comprises serially coupled first and second bipolar transistors located in a substrate, a first external resistor coupled between an emitter and a base of the first bipolar transistor, and a second external resistor coupled between an emitter and a base of the second bipolar transistor, wherein the emitter of the first bipolar transistor is coupled to the common terminal, and collectors (27, 37) of the first and second bipolar transistors are coupled together, wherein a second electrostatic discharge clamp stage (41', 71') of the plurality of electrostatic discharge clamp stages comprises serially coupled third and fourth bipolar transistors located in said substrate, a third external resistor coupled between an emitter and a base of the third bipolar transistor, and a fourth external resistor coupled between an emitter and a base of the fourth bipolar transistor, wherein the emitter of the third bipolar transistor is coupled to the emitter of the second bipolar transistor, and collectors (27', 37') of the third and fourth bipolar transistors are coupled together, wherein each of said external resistors is a thin film resistor and comprises at least two resistors (291, 292, 391, 392, 291', 292', 391', 392') formed on an upper surface of a dielectric passivation layer located on a surface of said substrate, and wherein the resistors of each said external thin film resistor are connected in parallel, in series, or in a series-parallel combination to provide an emitter-base coupling resistance value for providing a desired trigger voltage of the ESD clamp stage. a circuit core coupled between the I/O and common terminals; and characterized by: a plurality of serially arranged resistor triggered bi-directional electrostatic discharge clamp stages (71, 71') coupled between the I/O and common terminals, wherein a first electrostatic discharge clamp stage (41, 71) of the plurality of electrostatic discharge clamp stages comprises serially coupled first and second bipolar transistors located in a substrate, a first external resistor coupled between an emitter and a base of the first bipolar transistor, and a second external resistor coupled between an emitter and a base of the second bipolar transistor, wherein the emitter of the first bipolar transistor is coupled to the common terminal, and collectors (27, 37) of the first and second bipolar transistors are coupled together, wherein a second electrostatic discharge clamp stage (41', 71') of the plurality of electrostatic discharge clamp stages comprises serially coupled third and fourth bipolar transistors located in said substrate, a third external resistor coupled between an emitter and a base of the third bipolar transistor, and a fourth external resistor coupled between an emitter and a base of the fourth bipolar transistor, wherein the emitter of the third bipolar transistor is coupled to the emitter of the second bipolar transistor, and collectors (27', 37') of the third and fourth bipolar transistors are coupled together, wherein each of said external resistors is a thin film resistor and comprises at least two resistors (291, 292, 391, 392, 291', 292', 391', 392') formed on an upper surface of a dielectric passivation layer located on a surface of said substrate, and wherein the resistors of each said external thin film resistor are connected a plurality of serially arranged resistor triggered bi-directional electrostatic discharge clamp stages (71, 71') coupled between the I/O and common terminals, wherein a first electrostatic discharge clamp stage (41, 71) of the plurality of electrostatic discharge clamp stages comprises serially coupled first and second bipolar transistors located in a substrate, a first external resistor coupled between an emitter and a base of the first bipolar transistor, and a second external resistor coupled between an emitter and a base of the second bipolar transistor, wherein the emitter of the first bipolar transistor is coupled to the common terminal, and collectors (27, 37) of the first and second bipolar transistors are coupled together, wherein a second electrostatic discharge clamp stage (41', 71') of the plurality of electrostatic discharge clamp stages comprises serially coupled third and fourth bipolar transistors located in said substrate, a third external resistor coupled between an emitter and a base of the third bipolar transistor, and a fourth external resistor coupled between an emitter and a base of the fourth bipolar transistor, wherein the emitter of the third bipolar transistor is coupled to the emitter of the second bipolar transistor, and collectors (27', 37') of the third and fourth bipolar transistors are coupled together, wherein each of said external resistors is a thin film resistor and comprises at least two resistors (291, 292, 391, 392, 291', 292', 391', 392') formed on an upper surface of a dielectric passivation layer located on a surface of said substrate, and wherein the resistors of each said external thin film resistor are connected in parallel, in series, or in a series-parallel combination to provide an emitter-base coupling resistance value for providing a desired trigger voltage of the ESD clamp stage.