A digital clock circuit for generating high-ratio frequency multiplication clock signal, wherein the digital clock circuit comprises: a first sub-circuit comprising a first digitally-controlled oscillator configured to be driven by a frequency control word F to control a first output frequency of a first periodic signal synthesized from multiple first pulses, and a first frequency divider configured to generate a trigger signal having a frequency equal to 1/M of the first output frequency; a second sub-circuit comprising a feedback loop including a frequency detector configured to compare an input frequency with a feedback frequency, a controller configured to adjust the frequency control word F based on an output of the frequency detector, a second digitally-controlled oscillator configured to be driven by the frequency control word F plus a constant C to control a second output frequency of a second periodic signal synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider configured to set the feedback frequency equal to 1/N of the second output frequency in the feedback loop; wherein the first output frequency is substantially higher than the input frequency by a few orders of magnitudes; wherein said first and second digitally-controlled oscillators are of the type time-average frequency direct period synthesizer, TAF-DPS; and wherein the first sub-circuit further comprises a free-running ring oscillator configured to generate oscillations based on noise and output the multiple first pulses having a first frequency with equally spaced phase shift Δ h, Δ h being the base time unit for the first digitally-controlled oscillator; and wherein the trigger oscillator driven by the trigger signal, comprises a Ki/2-stage Johnson counter configured to output Ki number of second pulses with equally spaced phase shift of 1/Ki of a second period given by inverse of 1/M of the first output frequency, said second pulses with equally spaced phase shift Δ l, Δ l being the base time unit for the second digitally-controlled oscillator; and wherein the first output frequency is substantially equal to the input frequency multiplied by M.N.(F+C). a first sub-circuit comprising a first digitally-controlled oscillator configured to be driven by a frequency control word F to control a first output frequency of a first periodic signal synthesized from multiple first pulses, and a first frequency divider configured to generate a trigger signal having a frequency equal to 1/M of the first output frequency; a second sub-circuit comprising a feedback loop including a frequency detector configured to compare an input frequency with a feedback frequency, a controller configured to adjust the frequency control word F based on an output of the frequency detector, a second digitally-controlled oscillator configured to be driven by the frequency control word F plus a constant C to control a second output frequency of a second periodic signal synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider configured to set the feedback frequency equal to 1/N of the second output frequency in the feedback loop; wherein the first output frequency is substantially higher than the input frequency by a few orders of magnitudes; wherein said first and second digitally-controlled oscillators are of the type time-average frequency direct period synthesizer, TAF-DPS; and wherein the first sub-circuit further comprises a free-running ring oscillator configured to generate oscillations based on noise and output the multiple first pulses having a first frequency with equally spaced phase shift Δ h, Δ h being the base time unit for the first digitally-controlled oscillator; and wherein the trigger oscillator driven by the trigger signal, comprises a Ki/2-stage Johnson counter configured to output Ki number of second pulses with equally spaced phase shift of 1/Ki of a second period given by inverse of 1/M of the first output frequency, said second pulses with equally spaced phase shift Δ l, Δ l being the base time unit for the second digitally-controlled oscillator; and wherein the first output frequency is substantially equal to the input frequency multiplied by M.N.(F+C).