A circuit for reducing jitter in a digital signal, comprising: a clock and data recovery stage comprising: a data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal; a component operative to receive the input data signal and generate in response thereto an unfiltered interpolator code, the unfiltered interpolator code encoding the change in phase of the input data signal over time from one clock cycle of the input data signal to the next clock cycle; and a first phase interpolator stage operative to receive the unfiltered interpolator code and generate in response thereto a recovered clock signal; a filter comprising: a filter operative to receive the unfiltered interpolator code and generate in response thereto a filtered interpolator code encoding low-frequency changes in the phase of the input data signal; and a second phase interpolator stage operative to receive the filtered interpolator code and generate in response thereto a filtered clock signal encoding the clock signal of the input data signal filtered of high-frequency phase jitter; a first-in-first-out (FIFO) memory component having a queue of memory registers, wherein the FIFO memory component is coupled to the clock and data recovery stage and the filter, the FIFO memory component operative to: alternatively store even data and odd data of the recovered data signal using the recovered clock signal, wherein the even data and odd data is stored at a data rate that is half of the data rate of the input data signal; and generate an output data signal by selecting stored data from the memory registers using the filtered clock signal, wherein the selected data is serialized to generate the output data signal at the data rate of the input data signal. a clock and data recovery stage comprising: a data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal; a component operative to receive the input data signal and generate in response thereto an unfiltered interpolator code, the unfiltered interpolator code encoding the change in phase of the input data signal over time from one clock cycle of the input data signal to the next clock cycle; and a first phase interpolator stage operative to receive the unfiltered interpolator code and generate in response thereto a recovered clock signal; a data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal; a component operative to receive the input data signal and generate in response thereto an unfiltered interpolator code, the unfiltered interpolator code encoding the change in phase of the input data signal over time from one clock cycle of the input data signal to the next clock cycle; and a first phase interpolator stage operative to receive the unfiltered interpolator code and generate in response thereto a recovered clock signal; a filter comprising: a filter operative to receive the unfiltered interpolator code and generate in response thereto a filtered interpolator code encoding low-frequency changes in the phase of the input data signal; and a second phase interpolator stage operative to receive the filtered interpolator code and generate in response thereto a filtered clock signal encoding the clock signal of the input data signal filtered of high-frequency phase jitter; a filter operative to receive the unfiltered interpolator code and generate in response thereto a filtered interpolator code encoding low-frequency changes in the phase of the input data signal; and a second phase interpolator stage operative to receive the filtered interpolator code and generate in response thereto a filtered clock signal encoding the clock signal of the input data signal filtered of high-frequency phase jitter; a first-in-first-out (FIFO) memory component having a queue of memory registers, wherein the FIFO memory component is coupled to the clock and data recovery stage and the filter, the FIFO memory component operative to: alternatively store even data and odd data of the recovered data signal using the recovered clock signal, wherein the even data and odd data is stored at a data rate that is half of the data rate of the input data signal; and generate an output data signal by selecting stored data from the memory registers using the filtered clock signal, wherein the selected data is serialized to generate the output data signal at the data rate of the input data signal. alternatively store even data and odd data of the recovered data signal using the recovered clock signal, wherein the even data and odd data is stored at a data rate that is half of the data rate of the input data signal; and generate an output data signal by selecting stored data from the memory registers using the filtered clock signal, wherein the selected data is serialized to generate the output data signal at the data rate of the input data signal.