An apparatus comprising: address translation circuitry for converting a virtual address specified by processing circuitry into a corresponding physical address of a memory system, with reference to address translation data obtained from a hierarchical arrangement of page tables, the hierarchical arrangement of page tables comprising both intermediate level page tables (115, 130, 145) and final level page tables; each final level page table comprising a number of final level descriptors, and each final level descriptor identifying the address translation data for an associated region of memory; each intermediate level page table comprising a number of intermediate level descriptors (117, 132, 147), and each intermediate level descriptor identifying intermediate address translation data used to identify an associated page table at a next level in the hierarchical arrangement; page table update circuitry to maintain state information within each final level descriptor, the page table update circuitry being arranged to update the state information of a given final level descriptor from a clean state to a dirty state to indicate that a modification of content of the associated region of memory is permitted; characterised in that: the page table update circuitry is further arranged to maintain the state information within the intermediate level descriptors provided within at least a subset of the intermediate level page tables, such that for a given intermediate level descriptor in which the state information is maintained, the page table update circuitry is arranged to update the state information of that given intermediate level descriptor from the clean state to the dirty state to indicate occurrence of an update from the clean state to the dirty state within the state information of any final level descriptors that are accessed via that intermediate level descriptor. address translation circuitry for converting a virtual address specified by processing circuitry into a corresponding physical address of a memory system, with reference to address translation data obtained from a hierarchical arrangement of page tables, the hierarchical arrangement of page tables comprising both intermediate level page tables (115, 130, 145) and final level page tables; each final level page table comprising a number of final level descriptors, and each final level descriptor identifying the address translation data for an associated region of memory; each intermediate level page table comprising a number of intermediate level descriptors (117, 132, 147), and each intermediate level descriptor identifying intermediate address translation data used to identify an associated page table at a next level in the hierarchical arrangement; page table update circuitry to maintain state information within each final level descriptor, the page table update circuitry being arranged to update the state information of a given final level descriptor from a clean state to a dirty state to indicate that a modification of content of the associated region of memory is permitted; characterised in that: the page table update circuitry is further arranged to maintain the state information within the intermediate level descriptors provided within at least a subset of the intermediate level page tables, such that for a given intermediate level descriptor in which the state information is maintained, the page table update circuitry is arranged to update the state information of that given intermediate level descriptor from the clean state to the dirty state to indicate occurrence of an update from the clean state to the dirty state within the state information of any final level descriptors that are accessed via that intermediate level descriptor.