A semiconductor device comprising: a substrate comprising a first side and a second side that are opposite to each other; a plurality of logic cells (LC1; LC1, LC2; LC3; LC) on the first side of the substrate and arranged along a first row, a second row adjacent to the first row, and a third row adjacent to the second row, the rows extending in a first direction and each of the rows having a cell height in a second direction, wherein each logic cell extends across one or more of the first, second and third rows in the second direction; a power tap cell extending across all of the first row, the second row and the third row, on the first side of the substrate; a first power rail and a second power rail that are on the power tap cell, extend in the first direction, and are spaced apart from each other in the second direction, wherein the first power rail extends along a boundary between the first row and the second row, and the second power rail extends along a boundary between the second row and the third row; and a power delivery network on the second side of the substrate, wherein the power tap cell comprises: a first power through via (PTSV1) that penetrates the substrate and extends from the power delivery network to the first power rail; and a second power through via (PTSV2) that penetrates the substrate and extends from the power delivery network to the second power rail, wherein the first power rail comprises a first extension part that extends in the first direction, and a first expansion part that has a width greater than a width of the first extension part in the second direction and protrudes from both side walls of the first extension part in the second direction, wherein the second power rail comprises a second extension part that extends in the first direction, and a second expansion part that has a width greater than a width of the second extension part in the second direction and protrudes from both side walls of the second extension part in the second direction, wherein the first power through via (PTSV1) is connected to the first expansion part, and wherein the second power through via (PTSV2) is connected to the second expansion part. a substrate comprising a first side and a second side that are opposite to each other; a plurality of logic cells (LC1; LC1, LC2; LC3; LC) on the first side of the substrate and arranged along a first row, a second row adjacent to the first row, and a third row adjacent to the second row, the rows extending in a first direction and each of the rows having a cell height in a second direction, wherein each logic cell extends across one or more of the first, second and third rows in the second direction; a power tap cell extending across all of the first row, the second row and the third row, on the first side of the substrate; a first power rail and a second power rail that are on the power tap cell, extend in the first direction, and are spaced apart from each other in the second direction, wherein the first power rail extends along a boundary between the first row and the second row, and the second power rail extends along a boundary between the second row and the third row; and a power delivery network on the second side of the substrate, wherein the power tap cell comprises: a first power through via (PTSV1) that penetrates the substrate and extends from the power delivery network to the first power rail; and a second power through via (PTSV2) that penetrates the substrate and extends from the power delivery network to the second power rail, wherein the first power rail comprises a first extension part that extends in the first direction, and a first expansion part that has a width greater than a width of the first extension part in the second direction and protrudes from both side walls of the first extension part in the second direction, wherein the second power rail comprises a second extension part that extends in the first direction, and a second expansion part that has a width greater than a width of the second extension part in the second direction and protrudes from both side walls of the second extension part in the second direction, wherein the first power through via (PTSV1) is connected to the first expansion part, and wherein the second power through via (PTSV2) is connected to the second expansion part. a first power through via (PTSV1) that penetrates the substrate and extends from the power delivery network to the first power rail; and a second power through via (PTSV2) that penetrates the substrate and extends from the power delivery network to the second power rail, wherein the first power rail comprises a first extension part that extends in the first direction, and a first expansion part that has a width greater than a width of the first extension part in the second direction and protrudes from both side walls of the first extension part in the second direction, wherein the second power rail comprises a second extension part that extends in the first direction, and a second expansion part that has a width greater than a width of the second extension part in the second direction and protrudes from both side walls of the second extension part in the second direction, wherein the first power through via (PTSV1) is connected to the first expansion part, and wherein the second power through via (PTSV2) is connected to the second expansion part.