A method of operating a display apparatus according to claim 5, the method comprising: the control circuit performing the following steps: providing a first clock signal and a second clock signal to the data driver, wherein one of the first clock signal and the second clock signal precedes the other of the first clock signal and the second clock signal by a predetermined time period (Δt); providing a polarity inversion signal to the data driver; providing a gate control signal to the gate driver; the gate driver performing the following steps: providing, in response to the gate control signal, gate signals to a plurality of gate lines; the data driver performing the following steps: providing a first data signal to a first data line during an odd-numbered frame, the first data signal having a first polarity, wherein a frame period is a period during which data signals are output for an entire group of pixel rows, wherein a group of pixel rows comprises one of: the odd numbered pixel rows and the even numbered pixel rows; and providing a second data signal to the first data line during an even-numbered frame, the second data signal having a second polarity, the second polarity being opposite to the first polarity; providing, to a second data line among the data lines, a third polarity data signal having the second polarity during the odd-numbered frame, a fourth data signal having the first polarity is provided to the second data line during the even-numbered frame, and the first and second data lines are adjacent one another, characterized in that the method further comprises the data driver using the predetermined time between the first clock signal and the second clock signal to control the timing of the data signals such that data signals of the first polarity precede those of the second polarity by the predetermined time. the control circuit performing the following steps: providing a first clock signal and a second clock signal to the data driver, wherein one of the first clock signal and the second clock signal precedes the other of the first clock signal and the second clock signal by a predetermined time period (Δt); providing a polarity inversion signal to the data driver; providing a gate control signal to the gate driver; providing a first clock signal and a second clock signal to the data driver, wherein one of the first clock signal and the second clock signal precedes the other of the first clock signal and the second clock signal by a predetermined time period (Δt); providing a polarity inversion signal to the data driver; providing a gate control signal to the gate driver; the gate driver performing the following steps: providing, in response to the gate control signal, gate signals to a plurality of gate lines; the data driver performing the following steps: providing a first data signal to a first data line during an odd-numbered frame, the first data signal having a first polarity, wherein a frame period is a period during which data signals are output for an entire group of pixel rows, wherein a group of pixel rows comprises one of: the odd numbered pixel rows and the even numbered pixel rows; and providing a second data signal to the first data line during an even-numbered frame, the second data signal having a second polarity, the second polarity being opposite to the first polarity; providing, to a second data line among the data lines, a third polarity data signal having the second polarity during the odd-numbered frame, a fourth data signal having the first polarity is provided to the second data line during the even-numbered frame, and the first and second data lines are adjacent one another, providing a first data signal to a first data line during an odd-numbered frame, the first data signal having a first polarity, wherein a frame period is a period during which data signals are output for an entire group of pixel rows, wherein a group of pixel rows comprises one of: the odd numbered pixel rows and the even numbered pixel rows; and providing a second data signal to the first data line during an even-numbered frame, the second data signal having a second polarity, the second polarity being opposite to the first polarity; providing, to a second data line among the data lines, a third polarity data signal having the second polarity during the odd-numbered frame, a fourth data signal having the first polarity is provided to the second data line during the even-numbered frame, and the first and second data lines are adjacent one another, characterized in that the method further comprises the data driver using the predetermined time between the first clock signal and the second clock signal to control the timing of the data signals such that data signals of the first polarity precede those of the second polarity by the predetermined time.