A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein: the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a main-output-impedance-inverter connected between the main-power-output-terminal and a combining node; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal; an integrated circuit; a laminate; wherein the splitter, the main-power-amplifier Z and the peaking-power-amplifier are provided by means of the integrated circuit and wherein the main-output-impedance-inverter comprises a CLC-inductor, a first-CLC-capacitor and a second-CLC-capacitor, wherein: the CLC-inductor is connected between the main-power-output-terminal and the combining node; the first-CLC-capacitor is connected between the main-power-output-terminal and a reference terminal; the second-CLC-capacitor is connected between the combining node and the reference terminal; and the first-CLC-capacitor is provided on the integrated circuit, and wherein the CLC-inductor and the second-CLC-capacitor are provided on the laminate, wherein: the splitter-input-terminal is directly connected to the main-splitter-output-terminal, and the splitter comprises a splitter-attenuator and a splitter-phase-shifter connected in cascade between the splitter-input-terminal and the peaking-splitter-output-terminal. a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein: the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a main-output-impedance-inverter connected between the main-power-output-terminal and a combining node; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal; the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal; an integrated circuit; a laminate; wherein the splitter, the main-power-amplifier Z and the peaking-power-amplifier are provided by means of the integrated circuit and wherein the main-output-impedance-inverter comprises a CLC-inductor, a first-CLC-capacitor and a second-CLC-capacitor, wherein: the CLC-inductor is connected between the main-power-output-terminal and the combining node; the first-CLC-capacitor is connected between the main-power-output-terminal and a reference terminal; the second-CLC-capacitor is connected between the combining node and the reference terminal; and the first-CLC-capacitor is provided on the integrated circuit, and wherein the CLC-inductor and the second-CLC-capacitor are provided on the laminate, the CLC-inductor is connected between the main-power-output-terminal and the combining node; the first-CLC-capacitor is connected between the main-power-output-terminal and a reference terminal; the second-CLC-capacitor is connected between the combining node and the reference terminal; and the first-CLC-capacitor is provided on the integrated circuit, and wherein the CLC-inductor and the second-CLC-capacitor are provided on the laminate, wherein: the splitter-input-terminal is directly connected to the main-splitter-output-terminal, and the splitter comprises a splitter-attenuator and a splitter-phase-shifter connected in cascade between the splitter-input-terminal and the peaking-splitter-output-terminal. the splitter-input-terminal is directly connected to the main-splitter-output-terminal, and the splitter comprises a splitter-attenuator and a splitter-phase-shifter connected in cascade between the splitter-input-terminal and the peaking-splitter-output-terminal.