A method for forming nanoscale semiconductor junctions comprising: creating an epitaxial semiconducting layer including a dopant of a first polarity formed on a semiconductor substrate having a dopant of a second polarity, wherein the second polarity is opposite to the first polarity; creating an imprint layer on said epitaxial semiconducting layer; urging a nanoimprinter toward said imprint layer; removing selective portions of said epitaxial semiconducting layer; forming an epitaxial semiconducting structure having an area having at least one lateral dimension less than 75 nanometers; and forming a first semiconducting junction having an area having at least one lateral dimension less than 75 nanometers, and further comprising: creating a first planarizing dielectric layer over said epitaxial semiconducting structure; co-planarizing said first planarizing dielectric layer to substantially the same thickness as said epitaxial semiconductor structure; creating a second semiconducting layer including a dopant of a second polarity over said epitaxial semiconducting layer and said first planarizing dielectric layer; creating a second imprint layer on said second semiconducting layer; urging a nanoimprinter toward said second imprint layer; removing selective portions of said second semiconducting layer; and forming a second semiconducting structure having an area having at least one lateral dimension less than 75 nanometers. creating an epitaxial semiconducting layer including a dopant of a first polarity formed on a semiconductor substrate having a dopant of a second polarity, wherein the second polarity is opposite to the first polarity; creating an imprint layer on said epitaxial semiconducting layer; urging a nanoimprinter toward said imprint layer; removing selective portions of said epitaxial semiconducting layer; forming an epitaxial semiconducting structure having an area having at least one lateral dimension less than 75 nanometers; and forming a first semiconducting junction having an area having at least one lateral dimension less than 75 nanometers, and further comprising: creating a first planarizing dielectric layer over said epitaxial semiconducting structure; co-planarizing said first planarizing dielectric layer to substantially the same thickness as said epitaxial semiconductor structure; creating a second semiconducting layer including a dopant of a second polarity over said epitaxial semiconducting layer and said first planarizing dielectric layer; creating a second imprint layer on said second semiconducting layer; urging a nanoimprinter toward said second imprint layer; removing selective portions of said second semiconducting layer; and forming a second semiconducting structure having an area having at least one lateral dimension less than 75 nanometers. creating a first planarizing dielectric layer over said epitaxial semiconducting structure; co-planarizing said first planarizing dielectric layer to substantially the same thickness as said epitaxial semiconductor structure; creating a second semiconducting layer including a dopant of a second polarity over said epitaxial semiconducting layer and said first planarizing dielectric layer; creating a second imprint layer on said second semiconducting layer; urging a nanoimprinter toward said second imprint layer; removing selective portions of said second semiconducting layer; and forming a second semiconducting structure having an area having at least one lateral dimension less than 75 nanometers.