A memory device for a dynamic random access memory, DRAM, comprising: a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed, an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices, a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells, each bit cell including: a charge storage element, a write transistor and a read transistor,, wherein the write transistor includes a gate electrode connected to a write select line and a first electrode connected to a write bit line, wherein the charge storage element includes a first portion connected to a read select line and a second portion connected to a second electrode of the write transistor and to a gate electrode of the read transistor, and wherein the read transistor includes an electrode connected to a sense line, a driver circuitry adapted to during a read mode apply a voltage to the read select line connected to a bit cell such that a gate voltage of the read transistor of said bit cell, on a condition that a first charge is stored by the charge storage element of said bit cell, is shifted to a first voltage which is smaller than a threshold voltage of the read transistor and, on a condition that a second charge is stored by the charge storage element of said bit cell, is shifted to a second voltage which is equal to or greater than the threshold voltage of the read transistor, and a plurality of gain transistors formed in said semiconductor device layer, each gain transistor being connected to a respective one of said bit cell stacks via the sense lines connected to the read transistor of each bit cell of said respective bit cell stack and being adapted to output an amplified read out signal. a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed, an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices, a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells, each bit cell including: a charge storage element, a write transistor and a read transistor,, wherein the write transistor includes a gate electrode connected to a write select line and a first electrode connected to a write bit line, wherein the charge storage element includes a first portion connected to a read select line and a second portion connected to a second electrode of the write transistor and to a gate electrode of the read transistor, and wherein the read transistor includes an electrode connected to a sense line, a driver circuitry adapted to during a read mode apply a voltage to the read select line connected to a bit cell such that a gate voltage of the read transistor of said bit cell, on a condition that a first charge is stored by the charge storage element of said bit cell, is shifted to a first voltage which is smaller than a threshold voltage of the read transistor and, on a condition that a second charge is stored by the charge storage element of said bit cell, is shifted to a second voltage which is equal to or greater than the threshold voltage of the read transistor, and a charge storage element, a write transistor and a read transistor,, wherein the write transistor includes a gate electrode connected to a write select line and a first electrode connected to a write bit line, wherein the charge storage element includes a first portion connected to a read select line and a second portion connected to a second electrode of the write transistor and to a gate electrode of the read transistor, and wherein the read transistor includes an electrode connected to a sense line, a driver circuitry adapted to during a read mode apply a voltage to the read select line connected to a bit cell such that a gate voltage of the read transistor of said bit cell, on a condition that a first charge is stored by the charge storage element of said bit cell, is shifted to a first voltage which is smaller than a threshold voltage of the read transistor and, on a condition that a second charge is stored by the charge storage element of said bit cell, is shifted to a second voltage which is equal to or greater than the threshold voltage of the read transistor, and a plurality of gain transistors formed in said semiconductor device layer, each gain transistor being connected to a respective one of said bit cell stacks via the sense lines connected to the read transistor of each bit cell of said respective bit cell stack and being adapted to output an amplified read out signal.