A data processing device comprising: a dynamic random access memory, DRAM; a memory controller for controlling the writing/reading of data to/from the DRAM; a processor for requesting the writing/reading of data to the DRAM; and an error detection module for requesting the memory controller to write/read data in accordance with a request from the processor, wherein the error detection module has: a first error detection code computing unit (CRCF410) for calculating a first error detection code of first data for which the processor issues a write request to the DRAM, a memory, a second error detection code computing unit (CRCF411) for reading second data for which the processor issues a read request from the DRAM and calculating a second error detection code from the read data, an error detection code comparing unit (CRCC41) for comparing the first error detection code and the second error detection code, and the data processing device being characterised by: a flag indicating: first mode in which the processor uses the memory as a cache memory for the DRAM when the processor accesses the DRAM, or second mode in which the memory operates as a scratchpad memory not as a cache memory, and the processor accesses the memory without accessing the DRAM, and wherein when the flag indicates the first mode, a part of the memory is used as an error detection code storage unit (CRCB41) to store the first error detection code. a dynamic random access memory, DRAM; a memory controller for controlling the writing/reading of data to/from the DRAM; a processor for requesting the writing/reading of data to the DRAM; and an error detection module for requesting the memory controller to write/read data in accordance with a request from the processor, wherein the error detection module has: a first error detection code computing unit (CRCF410) for calculating a first error detection code of first data for which the processor issues a write request to the DRAM, a memory, a second error detection code computing unit (CRCF411) for reading second data for which the processor issues a read request from the DRAM and calculating a second error detection code from the read data, an error detection code comparing unit (CRCC41) for comparing the first error detection code and the second error detection code, and the data processing device being characterised by: a flag indicating: first mode in which the processor uses the memory as a cache memory for the DRAM when the processor accesses the DRAM, or second mode in which the memory operates as a scratchpad memory not as a cache memory, and the processor accesses the memory without accessing the DRAM, and wherein when the flag indicates the first mode, a part of the memory is used as an error detection code storage unit (CRCB41) to store the first error detection code. a first error detection code computing unit (CRCF410) for calculating a first error detection code of first data for which the processor issues a write request to the DRAM, a memory, a second error detection code computing unit (CRCF411) for reading second data for which the processor issues a read request from the DRAM and calculating a second error detection code from the read data, an error detection code comparing unit (CRCC41) for comparing the first error detection code and the second error detection code, and the data processing device being characterised by: a flag indicating: first mode in which the processor uses the memory as a cache memory for the DRAM when the processor accesses the DRAM, or second mode in which the memory operates as a scratchpad memory not as a cache memory, and the processor accesses the memory without accessing the DRAM, and wherein when the flag indicates the first mode, a part of the memory is used as an error detection code storage unit (CRCB41) to store the first error detection code. a flag indicating: first mode in which the processor uses the memory as a cache memory for the DRAM when the processor accesses the DRAM, or second mode in which the memory operates as a scratchpad memory not as a cache memory, and the processor accesses the memory without accessing the DRAM, and first mode in which the processor uses the memory as a cache memory for the DRAM when the processor accesses the DRAM, or second mode in which the memory operates as a scratchpad memory not as a cache memory, and the processor accesses the memory without accessing the DRAM, and wherein when the flag indicates the first mode, a part of the memory is used as an error detection code storage unit (CRCB41) to store the first error detection code.