A display panel comprising: a substrate comprising a first area and a display area surrounding the first area; and a plurality of pixels arranged in the display area, wherein the display area comprises a first display area (DA1, DA2) around the first area and a second display area (DA3, DA4) other than the first display area (DA1, DA2), wherein a size of a first driving transistor of a first pixel (P1, P2) arranged in the first display area (DA1, DA2) is different from a size of a second driving transistor of a second pixel (P3, P4) arranged in the second display area (DA3, DA4), wherein the first display area (DA1, DA2) comprises a first sub-display area and a second sub-display area arranged apart from each other in a first direction, with the first area therebetween, wherein a first row in which semiconductor layers of first pixels of the first sub-display area are directly connected in the first direction and a second row in which semiconductor layers of the first pixels of the second sub-display area are directly connected in the first direction are apart from each other with the first area therebetween wherein the semiconductor layers form channel areas, source areas and drain areas of transistors of the first pixels, and a length of a third row in which semiconductor layers of second pixels (P3, P4) of the second display area (DA3, DA4) are directly connected in the first direction is longer than a length of the first row or a length of the second row, the semiconductor layers of second pixels forming channel areas, source areas and drain areas of transistors of the second pixels, and wherein for driving transistors in each of the first sub-display area and the second sub-display area, a first channel ratio of a channel width of the first driving transistor to a channel length of the first driving transistor gradually increases or decreases away from the first area, and wherein the first channel ratio of the channel width of the first driving transistor to the channel length of the first driving transistor is greater or less than a second channel ratio of a channel width of the second driving transistor to a channel length of the second driving transistor. a substrate comprising a first area and a display area surrounding the first area; and a plurality of pixels arranged in the display area, wherein the display area comprises a first display area (DA1, DA2) around the first area and a second display area (DA3, DA4) other than the first display area (DA1, DA2), wherein a size of a first driving transistor of a first pixel (P1, P2) arranged in the first display area (DA1, DA2) is different from a size of a second driving transistor of a second pixel (P3, P4) arranged in the second display area (DA3, DA4), wherein the first display area (DA1, DA2) comprises a first sub-display area and a second sub-display area arranged apart from each other in a first direction, with the first area therebetween, wherein a first row in which semiconductor layers of first pixels of the first sub-display area are directly connected in the first direction and a second row in which semiconductor layers of the first pixels of the second sub-display area are directly connected in the first direction are apart from each other with the first area therebetween wherein the semiconductor layers form channel areas, source areas and drain areas of transistors of the first pixels, and a length of a third row in which semiconductor layers of second pixels (P3, P4) of the second display area (DA3, DA4) are directly connected in the first direction is longer than a length of the first row or a length of the second row, the semiconductor layers of second pixels forming channel areas, source areas and drain areas of transistors of the second pixels, and wherein for driving transistors in each of the first sub-display area and the second sub-display area, a first channel ratio of a channel width of the first driving transistor to a channel length of the first driving transistor gradually increases or decreases away from the first area, and wherein the first channel ratio of the channel width of the first driving transistor to the channel length of the first driving transistor is greater or less than a second channel ratio of a channel width of the second driving transistor to a channel length of the second driving transistor.