An apparatus comprising: an integrated circuit die comprising: an array of memory cells; an interface configured to permit data transfer to and from the integrated circuit die; a circuit configured to enter a soft post-package trim mode or a post-package trim mode in response to instructions received over the interface, wherein the circuit is configured to: receive a first set of one or more values from the interface; store the first set of one or more values at a first latch; adjust, via a decoder configured to receive the first set of one or more values from the first latch, a characteristic of the integrated circuit relating to a memory characteristic based at least partly on the first set of one or more values from the first latch; store the first set of one or more values in a first set of fuses in communication with the first latch; receive a second set of one or more values from the interface; store the second set of one or more values at a second latch; cause, in the soft post-package trim mode, a multiplexer to select the second set of one or more values from the second latch received at a first input for provision to an output of the multiplexer; adjust, via the decoder further configured to receive the output of the multiplexer, the characteristic of the integrated circuit relating to the memory characteristic based at least partly on the second set of one or more values from the second latch; and store the second set of one or more values in a second set of fuses, wherein the second set of fuses is electrically isolated from the first latch, wherein the circuit is further configured to cause, in the post-package trim mode, the multiplexer to select the second set of one or more values from the second set of fuses received at a second input for provision to the output of the multiplexer alternatively to causing the multiplexer to select the second set of one or more values from the second latch received at the first input. an array of memory cells; an interface configured to permit data transfer to and from the integrated circuit die; a circuit configured to enter a soft post-package trim mode or a post-package trim mode in response to instructions received over the interface, wherein the circuit is configured to: receive a first set of one or more values from the interface; store the first set of one or more values at a first latch; adjust, via a decoder configured to receive the first set of one or more values from the first latch, a characteristic of the integrated circuit relating to a memory characteristic based at least partly on the first set of one or more values from the first latch; store the first set of one or more values in a first set of fuses in communication with the first latch; receive a second set of one or more values from the interface; store the second set of one or more values at a second latch; cause, in the soft post-package trim mode, a multiplexer to select the second set of one or more values from the second latch received at a first input for provision to an output of the multiplexer; adjust, via the decoder further configured to receive the output of the multiplexer, the characteristic of the integrated circuit relating to the memory characteristic based at least partly on the second set of one or more values from the second latch; and store the second set of one or more values in a second set of fuses, wherein the second set of fuses is electrically isolated from the first latch, wherein the circuit is further configured to cause, in the post-package trim mode, the multiplexer to select the second set of one or more values from the second set of fuses received at a second input for provision to the output of the multiplexer alternatively to causing the multiplexer to select the second set of one or more values from the second latch received at the first input. receive a first set of one or more values from the interface; store the first set of one or more values at a first latch; adjust, via a decoder configured to receive the first set of one or more values from the first latch, a characteristic of the integrated circuit relating to a memory characteristic based at least partly on the first set of one or more values from the first latch; store the first set of one or more values in a first set of fuses in communication with the first latch; receive a second set of one or more values from the interface; store the second set of one or more values at a second latch; cause, in the soft post-package trim mode, a multiplexer to select the second set of one or more values from the second latch received at a first input for provision to an output of the multiplexer; adjust, via the decoder further configured to receive the output of the multiplexer, the characteristic of the integrated circuit relating to the memory characteristic based at least partly on the second set of one or more values from the second latch; and store the second set of one or more values in a second set of fuses, wherein the second set of fuses is electrically isolated from the first latch, wherein the circuit is further configured to cause, in the post-package trim mode, the multiplexer to select the second set of one or more values from the second set of fuses received at a second input for provision to the output of the multiplexer alternatively to causing the multiplexer to select the second set of one or more values from the second latch received at the first input.