A vector reduction circuit configured to reduce an input vector of elements, wherein the input vector is identified as including a plurality of segments of elements, the vector reduction circuit comprising: a control register configured to receive a control vector of elements, wherein the control vector of elements specifies the plurality of segments of elements of the input vector; a plurality of cells, wherein each of the plurality of cells comprises: an input vector element register configured to receive a particular element of the input vector, a temporary reduction element register configured to receive, from another of the plurality of cells, a temporary reduction element being an intermediate result of the vector reduction, computation circuitry (512, 514, 516) configured to perform a reduction operation using the particular element and the temporary reduction element; and wherein each of the plurality of cells is configured to: receive, in a result register, a result of performing the reduction operation using the particular element and the temporary reduction element; receive a control vector element that corresponds to a respective one of the cells; determine, based at least on the control vector element, that the particular element is designated as a last element of a particular segment of the input vector; provide, when the control vector element indicates that the respective one of the plurality of cells is not a last cell for a segment of the input vector, the result of the reduction to a temporary reduction element register of a next cell; and provide, when the control vector element indicates the respective one of the plurality of cells is a last cell for a segment of the input vector, the result of the reduction operation to an output circuit; the output circuit configured to provide, for output as a reduction of a segment of the input vector, the result of performing the reduction operation from said last cell for a segment. a control register configured to receive a control vector of elements, wherein the control vector of elements specifies the plurality of segments of elements of the input vector; a plurality of cells, wherein each of the plurality of cells comprises: an input vector element register configured to receive a particular element of the input vector, a temporary reduction element register configured to receive, from another of the plurality of cells, a temporary reduction element being an intermediate result of the vector reduction, computation circuitry (512, 514, 516) configured to perform a reduction operation using the particular element and the temporary reduction element; and an input vector element register configured to receive a particular element of the input vector, a temporary reduction element register configured to receive, from another of the plurality of cells, a temporary reduction element being an intermediate result of the vector reduction, computation circuitry (512, 514, 516) configured to perform a reduction operation using the particular element and the temporary reduction element; and wherein each of the plurality of cells is configured to: receive, in a result register, a result of performing the reduction operation using the particular element and the temporary reduction element; receive a control vector element that corresponds to a respective one of the cells; determine, based at least on the control vector element, that the particular element is designated as a last element of a particular segment of the input vector; provide, when the control vector element indicates that the respective one of the plurality of cells is not a last cell for a segment of the input vector, the result of the reduction to a temporary reduction element register of a next cell; and provide, when the control vector element indicates the respective one of the plurality of cells is a last cell for a segment of the input vector, the result of the reduction operation to an output circuit; receive, in a result register, a result of performing the reduction operation using the particular element and the temporary reduction element; receive a control vector element that corresponds to a respective one of the cells; determine, based at least on the control vector element, that the particular element is designated as a last element of a particular segment of the input vector; provide, when the control vector element indicates that the respective one of the plurality of cells is not a last cell for a segment of the input vector, the result of the reduction to a temporary reduction element register of a next cell; and provide, when the control vector element indicates the respective one of the plurality of cells is a last cell for a segment of the input vector, the result of the reduction operation to an output circuit; the output circuit configured to provide, for output as a reduction of a segment of the input vector, the result of performing the reduction operation from said last cell for a segment.