A memory device system, comprising: a plurality of stacked memory device dice connected to each other through a plurality of conductors, each of the plurality of stacked memory device dice containing a plurality of memory cells; a logic die coupled to the plurality of stacked memory device dice through a plurality of conductors, the logic die being operable to write data to and read data from the plurality of stacked memory device dice responsive to a received memory command at a location corresponding to a received address, the logic die comprising: a command processing circuit (70a to 70p) comprising a command register including a sequencer, wherein the command register is configured to receive the commands and, the command processing circuit operating according to either a first operating mode or a second operating mode, the command register operable in the first operating mode to convert the received commands to memory command signals having a first format corresponding to an indirect mode, and to apply the memory command signals having the first format to the plurality of stacked memory device dice, wherein in the indirect mode the sequencer transmits the memory command signals to the plurality of stacked memory device dice in a preset order and at preset times; and the command register operable in the second operating mode to convert the received commands to memory command signals having a second format that is different from the first format, the second format corresponding to a direct mode, and to apply the memory command signals having the second format to the plurality of stacked memory device dice, wherein in the direct mode the memory command signals are applied to the plurality of stacked memory device dice as they are received, wherein the command register is operable in the second operating mode to transmit command signals to the plurality of stacked memory device dice in the order and at the times the commands, respectively, are received by the command register. a plurality of stacked memory device dice connected to each other through a plurality of conductors, each of the plurality of stacked memory device dice containing a plurality of memory cells; a logic die coupled to the plurality of stacked memory device dice through a plurality of conductors, the logic die being operable to write data to and read data from the plurality of stacked memory device dice responsive to a received memory command at a location corresponding to a received address, the logic die comprising: a command processing circuit (70a to 70p) comprising a command register including a sequencer, wherein the command register is configured to receive the commands and, the command processing circuit operating according to either a first operating mode or a second operating mode, the command register operable in the first operating mode to convert the received commands to memory command signals having a first format corresponding to an indirect mode, and to apply the memory command signals having the first format to the plurality of stacked memory device dice, wherein in the indirect mode the sequencer transmits the memory command signals to the plurality of stacked memory device dice in a preset order and at preset times; and the command register operable in the second operating mode to convert the received commands to memory command signals having a second format that is different from the first format, the second format corresponding to a direct mode, and to apply the memory command signals having the second format to the plurality of stacked memory device dice, wherein in the direct mode the memory command signals are applied to the plurality of stacked memory device dice as they are received, wherein the command register is operable in the second operating mode to transmit command signals to the plurality of stacked memory device dice in the order and at the times the commands, respectively, are received by the command register. a command processing circuit (70a to 70p) comprising a command register including a sequencer, wherein the command register is configured to receive the commands and, the command processing circuit operating according to either a first operating mode or a second operating mode, the command register operable in the first operating mode to convert the received commands to memory command signals having a first format corresponding to an indirect mode, and to apply the memory command signals having the first format to the plurality of stacked memory device dice, wherein in the indirect mode the sequencer transmits the memory command signals to the plurality of stacked memory device dice in a preset order and at preset times; and the command register operable in the second operating mode to convert the received commands to memory command signals having a second format that is different from the first format, the second format corresponding to a direct mode, and to apply the memory command signals having the second format to the plurality of stacked memory device dice, wherein in the direct mode the memory command signals are applied to the plurality of stacked memory device dice as they are received, wherein the command register is operable in the second operating mode to transmit command signals to the plurality of stacked memory device dice in the order and at the times the commands, respectively, are received by the command register.