An integrated circuit, comprising: a circuit system having a plurality of circuit stages configured to receive respective differential pairs of input data signals (SIG IN1, SIG IN2) on respective differential pairs of input signal lines (237.1, 238.1) and to generate respective differential pairs of circuit stage output data signals (I OUTP, I OUTN); a plurality of load circuits, one provided for each circuit stage, each load circuit having: a first transistor (243.1) having a gate terminal coupled to a first input signal line of the respective differential pair of input signal lines (237.1) to receive a first input data signal of the respective differential pair of input data signals (SIG IN1), and a second transistor (244.1) having a gate terminal coupled to a second input signal line of the respective differential pair of input signal lines (238.1) to receive a second input data signal of the respective differential pair of input data signals (SIG IN2), and a current source (241.1) programmable independently of the current sources of the other load circuits, arranged to propagate a bias current through the first transistor when the first transistor is switched on, to at least in part define a first capacitive load (235.1) on the first input signal line, and to propagate the bias current through the second transistor when the second transistor is switched on, to at least in part define a second capacitive load (236.1) on the second input signal line; and a controller (242.1) configured to adjust the bias currents provided by each current source to alter the capacitive loads to account for timing mismatch between the differential pairs of output data signals of the circuit stages. a circuit system having a plurality of circuit stages configured to receive respective differential pairs of input data signals (SIG IN1, SIG IN2) on respective differential pairs of input signal lines (237.1, 238.1) and to generate respective differential pairs of circuit stage output data signals (I OUTP, I OUTN); a plurality of load circuits, one provided for each circuit stage, each load circuit having: a first transistor (243.1) having a gate terminal coupled to a first input signal line of the respective differential pair of input signal lines (237.1) to receive a first input data signal of the respective differential pair of input data signals (SIG IN1), and a second transistor (244.1) having a gate terminal coupled to a second input signal line of the respective differential pair of input signal lines (238.1) to receive a second input data signal of the respective differential pair of input data signals (SIG IN2), and a current source (241.1) programmable independently of the current sources of the other load circuits, arranged to propagate a bias current through the first transistor when the first transistor is switched on, to at least in part define a first capacitive load (235.1) on the first input signal line, and to propagate the bias current through the second transistor when the second transistor is switched on, to at least in part define a second capacitive load (236.1) on the second input signal line; and a first transistor (243.1) having a gate terminal coupled to a first input signal line of the respective differential pair of input signal lines (237.1) to receive a first input data signal of the respective differential pair of input data signals (SIG IN1), and a second transistor (244.1) having a gate terminal coupled to a second input signal line of the respective differential pair of input signal lines (238.1) to receive a second input data signal of the respective differential pair of input data signals (SIG IN2), and a current source (241.1) programmable independently of the current sources of the other load circuits, arranged to propagate a bias current through the first transistor when the first transistor is switched on, to at least in part define a first capacitive load (235.1) on the first input signal line, and to propagate the bias current through the second transistor when the second transistor is switched on, to at least in part define a second capacitive load (236.1) on the second input signal line; and a controller (242.1) configured to adjust the bias currents provided by each current source to alter the capacitive loads to account for timing mismatch between the differential pairs of output data signals of the circuit stages.