A memory control system comprising: a memory interface circuit configured to receive a memory operation command and generate a plurality of operation instructions (INS 1, INS X) according to the memory operation command; a microcontroller coupled to the memory interface circuit, and configured to receive the plurality of operation instructions (INS 1, INS X) and generate a plurality of task instructions (TSK 1, TSK 2 TSK 3, TSK 4, TSK Y) according a scheduling algorithm through a predetermined protocol; and a sequence processing unit coupled to the microcontroller, comprising at least one finite state machine (FSM1, FSM2), and configured to receive the plurality of task instructions (TSK 1, TSK 2, TSK 3, TSK 4, TSK Y) through the predetermined protocol, and control a plurality of circuits of a memory device according to the plurality of task instructions (TSK 1, TSK 2, TSK 3, TSK 4, TSK Y) with the at least one finite state machine (FSM1, FSM2), wherein the sequence processing unit is further coupled to the memory interface circuit; and in a test mode of the memory control system, the memory interface circuit controls the sequence processing unit to access the memory device directly, wherein the microcontroller is further configured to update the scheduling algorithm to change a transmission order of the plurality of task instructions (TSK 1, TSK 2, TSK 3, TSK 4, TSK Y), wherein the microcontroller comprises a storage unit, the storage unit stores the plurality of task instructions in locations within the storage unit corresponding to the transmission order assigned according to the scheduling algorithm, and wherein receiving the plurality of task instructions through the predetermined protocol includes receiving the plurality of task instructions stored in the storage unit, characterized in that the memory interface circuit and the microcontroller communicate through a standard bus protocol, and the plurality of circuits of the memory device comprises a charge pump and a power regulator. a memory interface circuit configured to receive a memory operation command and generate a plurality of operation instructions (INS 1, INS X) according to the memory operation command; a microcontroller coupled to the memory interface circuit, and configured to receive the plurality of operation instructions (INS 1, INS X) and generate a plurality of task instructions (TSK 1, TSK 2 TSK 3, TSK 4, TSK Y) according a scheduling algorithm through a predetermined protocol; and a sequence processing unit coupled to the microcontroller, comprising at least one finite state machine (FSM1, FSM2), and configured to receive the plurality of task instructions (TSK 1, TSK 2, TSK 3, TSK 4, TSK Y) through the predetermined protocol, and control a plurality of circuits of a memory device according to the plurality of task instructions (TSK 1, TSK 2, TSK 3, TSK 4, TSK Y) with the at least one finite state machine (FSM1, FSM2), wherein the sequence processing unit is further coupled to the memory interface circuit; and in a test mode of the memory control system, the memory interface circuit controls the sequence processing unit to access the memory device directly, wherein the microcontroller is further configured to update the scheduling algorithm to change a transmission order of the plurality of task instructions (TSK 1, TSK 2, TSK 3, TSK 4, TSK Y), wherein the microcontroller comprises a storage unit, the storage unit stores the plurality of task instructions in locations within the storage unit corresponding to the transmission order assigned according to the scheduling algorithm, and wherein receiving the plurality of task instructions through the predetermined protocol includes receiving the plurality of task instructions stored in the storage unit, characterized in that the memory interface circuit and the microcontroller communicate through a standard bus protocol, and the plurality of circuits of the memory device comprises a charge pump and a power regulator.