Non-volatile memory, characterized in that it comprises: - a first selection transistor having: - a first layer of semiconductor material in which a first channel zone and first and second conduction electrodes (32, 31) are arranged; - a first gate stack formed on said first channel zone and including a first gate electrode and a first gate insulator positioned between the first gate electrode and the first channel zone; - a second selection transistor having: - a second layer of semiconductor material in which a second channel zone and third and fourth conduction electrodes (22, 21) are arranged; - a second gate stack formed on said second channel zone and including a second gate electrode and a second gate insulator positioned between the second gate electrode and the second channel zone; - an isolation trench positioned between the first and second selection transistors (3, 2); - an RRAM memory structure (4, 5) having: - a control electrode; - a dielectric layer formed underneath the control electrode, having a median part vertical to the isolation trench and first and second ends (403, 402) extending vertically respectively to the first and third conduction electrodes (32, 22), the dielectric layer being configured so as to selectively form a first conductive filament between the control electrode and the first conduction electrode, and so as to selectively form a second conductive filament between the control electrode and the third conduction electrode, the dielectric layer, the first gate insulator and the second gate insulator being formed of the same material, said memory structure and said first and second selection transistors are formed in one and the same layer prior to metallization. - a first selection transistor having: - a first layer of semiconductor material in which a first channel zone and first and second conduction electrodes (32, 31) are arranged; - a first gate stack formed on said first channel zone and including a first gate electrode and a first gate insulator positioned between the first gate electrode and the first channel zone; - a first layer of semiconductor material in which a first channel zone and first and second conduction electrodes (32, 31) are arranged; - a first gate stack formed on said first channel zone and including a first gate electrode and a first gate insulator positioned between the first gate electrode and the first channel zone; - a second selection transistor having: - a second layer of semiconductor material in which a second channel zone and third and fourth conduction electrodes (22, 21) are arranged; - a second gate stack formed on said second channel zone and including a second gate electrode and a second gate insulator positioned between the second gate electrode and the second channel zone; - a second layer of semiconductor material in which a second channel zone and third and fourth conduction electrodes (22, 21) are arranged; - a second gate stack formed on said second channel zone and including a second gate electrode and a second gate insulator positioned between the second gate electrode and the second channel zone; - an isolation trench positioned between the first and second selection transistors (3, 2); - an RRAM memory structure (4, 5) having: - a control electrode; - a dielectric layer formed underneath the control electrode, having a median part vertical to the isolation trench and first and second ends (403, 402) extending vertically respectively to the first and third conduction electrodes (32, 22), the dielectric layer being configured so as to selectively form a first conductive filament between the control electrode and the first conduction electrode, and so as to selectively form a second conductive filament between the control electrode and the third conduction electrode, the dielectric layer, the first gate insulator and the second gate insulator being formed of the same material, said memory structure and said first and second selection transistors are formed in one and the same layer prior to metallization. - a control electrode; - a dielectric layer formed underneath the control electrode, having a median part vertical to the isolation trench and first and second ends (403, 402) extending vertically respectively to the first and third conduction electrodes (32, 22), the dielectric layer being configured so as to selectively form a first conductive filament between the control electrode and the first conduction electrode, and so as to selectively form a second conductive filament between the control electrode and the third conduction electrode, the dielectric layer, the first gate insulator and the second gate insulator being formed of the same material, said memory structure and said first and second selection transistors are formed in one and the same layer prior to metallization.