Detector circuit for the galvanically isolated transmission of digital signals, comprising - two differential signal inputs (RF1, RF2), - an input common-mode voltage connection, - an AC voltage coupling, - a differential stage, - an operating voltage connection (AVDD), - an operating earth connection (AVSS), - a signal output (IRECT), - a bias current connection (IBIAS), wherein the AC voltage coupling comprises two capacitors (C1, C2) and two resistors (R1, R2), and wherein a respective capacitor (C1, C2) is connected on a first side to a respective one of the differential signal inputs (RF1, RF2), and wherein the second sides of the two capacitors (C1, C2) are each connected to the differential stage and, via a respective resistor (R1, R2), to the input common-mode voltage connection, wherein the differential stage comprises a first n-channel transistor and a second n-channel transistor, and the first and the second n-channel transistor (MN1, MN2) are each connected to a respective resistor (R1, R2) and a respective capacitor (C1, C2) of the AC voltage coupling, wherein the operating earth connection (AVSS) is connected to a third n-channel transistor, characterized in that the detector circuit also has a rectifier stage, wherein the bias current connection (IBIAS) is connected to the differential stage via the third n-channel transistor, and wherein the bias current connection (IBIAS) is connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor, wherein the operating earth connection (AVSS) is connected to the fourth and fifth n-channel transistors (MN4, MN5), wherein the rectifier stage comprises five p-channel transistors (MP1, MP2, MP3, MP4, MP5), and wherein the first n-channel transistor is connected to the first p-channel transistor, the fourth p-channel transistor and the fifth p-channel transistor, and wherein the second n-channel transistor is connected to the second p-channel transistor, the fourth p-channel transistor and the fifth p-channel transistor, wherein the operating voltage connection (AVDD) is connected to the first, second and third p-channel transistors (MP1, MP2, MP3), wherein the signal output (IRECT) is connected to the fourth and fifth p-channel transistors (MP4, MP5). - two differential signal inputs (RF1, RF2), - an input common-mode voltage connection, - an AC voltage coupling, - a differential stage, - an operating voltage connection (AVDD), - an operating earth connection (AVSS), - a signal output (IRECT), - a bias current connection (IBIAS), wherein the AC voltage coupling comprises two capacitors (C1, C2) and two resistors (R1, R2), and wherein a respective capacitor (C1, C2) is connected on a first side to a respective one of the differential signal inputs (RF1, RF2), and wherein the second sides of the two capacitors (C1, C2) are each connected to the differential stage and, via a respective resistor (R1, R2), to the input common-mode voltage connection, wherein the differential stage comprises a first n-channel transistor and a second n-channel transistor, and the first and the second n-channel transistor (MN1, MN2) are each connected to a respective resistor (R1, R2) and a respective capacitor (C1, C2) of the AC voltage coupling, wherein the operating earth connection (AVSS) is connected to a third n-channel transistor, characterized in that the detector circuit also has a rectifier stage, wherein the bias current connection (IBIAS) is connected to the differential stage via the third n-channel transistor, and wherein the bias current connection (IBIAS) is connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor, wherein the operating earth connection (AVSS) is connected to the fourth and fifth n-channel transistors (MN4, MN5), wherein the rectifier stage comprises five p-channel transistors (MP1, MP2, MP3, MP4, MP5), and wherein the first n-channel transistor is connected to the first p-channel transistor, the fourth p-channel transistor and the fifth p-channel transistor, and wherein the second n-channel transistor is connected to the second p-channel transistor, the fourth p-channel transistor and the fifth p-channel transistor, wherein the operating voltage connection (AVDD) is connected to the first, second and third p-channel transistors (MP1, MP2, MP3), wherein the signal output (IRECT) is connected to the fourth and fifth p-channel transistors (MP4, MP5).