A system for scheduling and executing best-effort processes, real-time processes and high-performance computing or HPC processes (106, 107), said system comprising: - a multi-core processor comprising plural cores (102, 103) for executing said best-effort processes, real-time processes and HPC processes (106, 107); - a core designated as noise core for handling device generated interrupts; - for each core (102, 103) in said multi-core processor, a per-core scheduler (141, 151) with a per-core run queue and a per-core clock (121, 131) for interrupt-based scheduling execution of processes (106, 107) on a respective core (102, 103) of said multi-core processor, all per-core schedulers (141, 151) being adapted to be able to deactivate their per-core clock (121, 131) temporarily for execution of an HPC process or best-effort process, and each per-core scheduler (141, 151) being able to reactivate its per-core clock (121, 131) when a process executed on said core (141, 151) stops execution to wait for an event; - a ready function (142, 152) adapted to receive from a core (102, 103) notification of an event that causes execution of a process on said core (102, 103) or another core (103, 102), said ready function (142, 152) being adapted to reactivate the scheduler (141, 151) that has previously deactivated the per-core clock (121, 131) of said core (102, 103); and - an inter-core-interrupt handler (122, 132) adapted to receive notification of a core (102, 103) to cause an interrupt on a different core (103, 102), said inter-core interrupt handler (122, 132) being adapted to activate a scheduler (141, 151) with a deactivated per-core clock (121, 131) of said different core (103,102). - a multi-core processor comprising plural cores (102, 103) for executing said best-effort processes, real-time processes and HPC processes (106, 107); - a core designated as noise core for handling device generated interrupts; - for each core (102, 103) in said multi-core processor, a per-core scheduler (141, 151) with a per-core run queue and a per-core clock (121, 131) for interrupt-based scheduling execution of processes (106, 107) on a respective core (102, 103) of said multi-core processor, all per-core schedulers (141, 151) being adapted to be able to deactivate their per-core clock (121, 131) temporarily for execution of an HPC process or best-effort process, and each per-core scheduler (141, 151) being able to reactivate its per-core clock (121, 131) when a process executed on said core (141, 151) stops execution to wait for an event; - a ready function (142, 152) adapted to receive from a core (102, 103) notification of an event that causes execution of a process on said core (102, 103) or another core (103, 102), said ready function (142, 152) being adapted to reactivate the scheduler (141, 151) that has previously deactivated the per-core clock (121, 131) of said core (102, 103); and - an inter-core-interrupt handler (122, 132) adapted to receive notification of a core (102, 103) to cause an interrupt on a different core (103, 102), said inter-core interrupt handler (122, 132) being adapted to activate a scheduler (141, 151) with a deactivated per-core clock (121, 131) of said different core (103,102).