A linear regulator (100, 200) comprising - a differential amplification stage configured to provide a stage output voltage at an output node, based on a first input voltage at a first input node and a second input voltage at a second input node; wherein the differential amplification stage comprises a first input transistor and a second input transistor forming a differential pair; wherein a gate of the first input transistor forms the first input node for receiving the first input voltage; wherein a gate of the second input transistor forms the second input node for receiving the second input voltage; and wherein an output node of the second input transistor forms the output node of the differential amplification stage; - a second amplification stage comprising - an amplifier current source configured to provide an amplifier current; and - an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the output node of the differential amplification stage; and - a detection circuit (300, 310) comprising - a detection current source (301, 311) configured to provide a detection current; - a detection transistor (303, 313) arranged in series with the detection current source (301, 311); wherein a gate of the detection transistor (303, 313) is coupled to the output node of the differential amplification stage; wherein a mid-point between the detection current source (301, 311) and an input node of the detection transistor (303, 313) forms a sensing point (305, 315); and - a clamping transistor (304, 314) arranged in parallel to the first or the second input transistor; wherein a gate of the clamping transistor (304, 314) is coupled to the sensing point (305,315); wherein the detection circuit (300, 310) is configured such that the sensing point (305, 315) changes from a default state to a detection state, subject to the stage output voltage at the output node deviating from a default voltage by at least a pre-determined threshold value. - a differential amplification stage configured to provide a stage output voltage at an output node, based on a first input voltage at a first input node and a second input voltage at a second input node; wherein the differential amplification stage comprises a first input transistor and a second input transistor forming a differential pair; wherein a gate of the first input transistor forms the first input node for receiving the first input voltage; wherein a gate of the second input transistor forms the second input node for receiving the second input voltage; and wherein an output node of the second input transistor forms the output node of the differential amplification stage; - a second amplification stage comprising - an amplifier current source configured to provide an amplifier current; and - an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the output node of the differential amplification stage; and - an amplifier current source configured to provide an amplifier current; and - an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the output node of the differential amplification stage; and - a detection circuit (300, 310) comprising - a detection current source (301, 311) configured to provide a detection current; - a detection transistor (303, 313) arranged in series with the detection current source (301, 311); wherein a gate of the detection transistor (303, 313) is coupled to the output node of the differential amplification stage; wherein a mid-point between the detection current source (301, 311) and an input node of the detection transistor (303, 313) forms a sensing point (305, 315); and - a clamping transistor (304, 314) arranged in parallel to the first or the second input transistor; wherein a gate of the clamping transistor (304, 314) is coupled to the sensing point (305,315); - a detection current source (301, 311) configured to provide a detection current; - a detection transistor (303, 313) arranged in series with the detection current source (301, 311); wherein a gate of the detection transistor (303, 313) is coupled to the output node of the differential amplification stage; wherein a mid-point between the detection current source (301, 311) and an input node of the detection transistor (303, 313) forms a sensing point (305, 315); and - a clamping transistor (304, 314) arranged in parallel to the first or the second input transistor; wherein a gate of the clamping transistor (304, 314) is coupled to the sensing point (305,315);