An insulated gate power semiconductor device on basis of a silicon substrate having - an emitter electrode on an emitter side and a collector electrode on a collector side, which collector side is arranged opposite to the emitter side, - a drift layer of a first conductivity type, which is arranged between the emitter side and the collector side, - a base layer of a second conductivity type, which is different from the first conductivity type, which base layer is arranged between the drift layer and the emitter side, and which base layer contacts the emitter electrode, - a source layer, which is arranged on the emitter side, which is separated from the drift layer by the base layer and which contacts the emitter electrode, - a trench gate electrode (7, 7'), which comprises an electrically conductive gate layer and a first electrically insulating layer, which surrounds and thus separates the gate layer from the drift layer, the base layer and the source layer, which trench gate electrode has a trench bottom, - an enhancement layer of the first conductivity type having higher doping concentration than the drift layer, which separates the base layer from the drift layer, wherein the enhancement layer has a maximum enhancement layer doping concentration in an enhancement layer depth, - a protection pillow of the second conductivity type, which covers the trench bottom, characterized in, that - a plasma enhancement layer (9, 9') of the first conductivity type having higher doping concentration than the drift layer, which covers an edge between the protection pillow and the trench gate electrode (7, 7'), at which the plasma enhancement layer (9, 9') is arranged, and which has a maximum plasma enhancement layer doping concentration, wherein a doping concentration of the first conductivity type rises from a local doping concentration minimum between the enhancement layer and the plasma enhancement layer (9, 9') towards the emitter side to the maximum enhancement layer doping concentration and towards the collector side to the maximum plasma enhancement layer doping concentration and wherein the plasma enhancement layer has the doping concentration maximum at the junction to the protection pillow. - an emitter electrode on an emitter side and a collector electrode on a collector side, which collector side is arranged opposite to the emitter side, - a drift layer of a first conductivity type, which is arranged between the emitter side and the collector side, - a base layer of a second conductivity type, which is different from the first conductivity type, which base layer is arranged between the drift layer and the emitter side, and which base layer contacts the emitter electrode, - a source layer, which is arranged on the emitter side, which is separated from the drift layer by the base layer and which contacts the emitter electrode, - a trench gate electrode (7, 7'), which comprises an electrically conductive gate layer and a first electrically insulating layer, which surrounds and thus separates the gate layer from the drift layer, the base layer and the source layer, which trench gate electrode has a trench bottom, - an enhancement layer of the first conductivity type having higher doping concentration than the drift layer, which separates the base layer from the drift layer, wherein the enhancement layer has a maximum enhancement layer doping concentration in an enhancement layer depth, - a protection pillow of the second conductivity type, which covers the trench bottom, characterized in, that - a plasma enhancement layer (9, 9') of the first conductivity type having higher doping concentration than the drift layer, which covers an edge between the protection pillow and the trench gate electrode (7, 7'), at which the plasma enhancement layer (9, 9') is arranged, and which has a maximum plasma enhancement layer doping concentration,