A bit line driver for a static random access memory (SRAM) cell comprising: a first voltage supply for supplying a first voltage (Vdd); a second voltage supply for supplying a second voltage (Vss) that is less than the first voltage (Vdd); a write circuit configured to selectively pull-up or pull-down a bit line (BLm) and an inverse bit line (BLNm) when writing to the SRAM cell according to a data signal and a write signal, wherein the write circuit comprises: a pair of pull up circuits comprising a first transistor coupled between the first voltage supply and the bit line (BLm), and a second transistor coupled between the first voltage supply and the inverse bit line (BLNm); a pair of pull down circuits comprising a third transistor coupled between the second voltage supply and the bit line (BLm), and a fourth transistor coupled between the second voltage supply and the inverse bit line (BLNm), wherein the pair of pull down circuits each have a gate cross-coupled with a gate of an opposite side pull up circuit of the pair of pull up circuits; and a pair of access circuits comprising a fifth transistor interposed between the first transistor and the bit line (BLm), a sixth transistor interposed between the second transistor and the inverse bit line (BLNm), a seventh transistor interposed between the third transistor and the bit line (BLm), and an eighth transistor interposed between the fourth transistor and the inverse bit line (BLNm), wherein the pair of access circuits each interposed between a corresponding one of the pull-up circuits and a same-side pull-down circuit of the pair of pull-down circuits; and a pre-charge circuit configured to pre-charge the bit line (BLm) and the inverse bit line (BLNm) before reading the content of the SRAM cell, wherein the bit line driver is configured to supply a voltage less than the first voltage (Vdd) by a threshold voltage of one transistor to the bit line (BLm) or the inverse bit line (BLNm) when the bit line driver drives the bit line (BLm) or the inverse bit line (BLNm) to a high state, and wherein the first transistor and the third transistor are a same type of transistor as row access transistors (M5, M6) of the SRAM cell. a first voltage supply for supplying a first voltage (Vdd); a second voltage supply for supplying a second voltage (Vss) that is less than the first voltage (Vdd); a write circuit configured to selectively pull-up or pull-down a bit line (BLm) and an inverse bit line (BLNm) when writing to the SRAM cell according to a data signal and a write signal, wherein the write circuit comprises: a pair of pull up circuits comprising a first transistor coupled between the first voltage supply and the bit line (BLm), and a second transistor coupled between the first voltage supply and the inverse bit line (BLNm); a pair of pull down circuits comprising a third transistor coupled between the second voltage supply and the bit line (BLm), and a fourth transistor coupled between the second voltage supply and the inverse bit line (BLNm), wherein the pair of pull down circuits each have a gate cross-coupled with a gate of an opposite side pull up circuit of the pair of pull up circuits; and a pair of access circuits comprising a fifth transistor interposed between the first transistor and the bit line (BLm), a sixth transistor interposed between the second transistor and the inverse bit line (BLNm), a seventh transistor interposed between the third transistor and the bit line (BLm), and an eighth transistor interposed between the fourth transistor and the inverse bit line (BLNm), wherein the pair of access circuits each interposed between a corresponding one of the pull-up circuits and a same-side pull-down circuit of the pair of pull-down circuits; and a pair of pull up circuits comprising a first transistor coupled between the first voltage supply and the bit line (BLm), and a second transistor coupled between the first voltage supply and the inverse bit line (BLNm); a pair of pull down circuits comprising a third transistor coupled between the second voltage supply and the bit line (BLm), and a fourth transistor coupled between the second voltage supply and the inverse bit line (BLNm), wherein the pair of pull down circuits each have a gate cross-coupled with a gate of an opposite side pull up circuit of the pair of pull up circuits; and a pair of access circuits comprising a fifth transistor interposed between the first transistor and the bit line (BLm), a sixth transistor interposed between the second transistor and the inverse bit line (BLNm), a seventh transistor interposed between the third transistor and the bit line (BLm), and an eighth transistor interposed between the fourth transistor and the inverse bit line (BLNm), wherein the pair of access circuits each interposed between a corresponding one of the pull-up circuits and a same-side pull-down circuit of the pair of pull-down circuits; and a pre-charge circuit configured to pre-charge the bit line (BLm) and the inverse bit line (BLNm) before reading the content of the SRAM cell, wherein the bit line driver is configured to supply a voltage less than the first voltage (Vdd) by a threshold voltage of one transistor to the bit line (BLm) or the inverse bit line (BLNm) when the bit line driver drives the bit line (BLm) or the inverse bit line (BLNm) to a high state, and wherein the first transistor and the third transistor are a same type of transistor as row access transistors (M5, M6) of the SRAM cell.