A method of manufacturing a transistor, comprising: forming a first source/drain metal layer on a substrate; forming an insulating layer (32, 33) above the first source/drain metal layer, the insulating layer comprising a first insulating region and a second insulating region, the first insulating region and the second insulating region being disposed oppositely with respect to a central line of the first source/drain metal layer with a blank area therebetween; forming a gate metal layer (34, 35) on the insulating layer (32, 33), the gate metal layer (34, 35) comprising a first gate electrode region and a second gate electrode region, and the first gate electrode region covering the first insulating region, the second gate electrode region covering the second insulating region; forming a gate insulating layer on the gate metal layer (34, 35); forming a semiconductor layer above the gate insulating layer, an orthographic projection region of the first source/drain metal layer on the substrate is within an orthographic projection region of the semiconductor layer on the substrate; forming an etching blocking layer on the semiconductor layer, an orthographic projection region of the blank area between the first insulating region and the second insulating region on the substrate is within an orthographic projection region of the etching blocking layer on the substrate; forming a second source/drain metal layer (39, 310) above the etching blocking layer, the second source/drain metal layer (39, 310) comprising a source electrode region and a drain electrode region, characterized in that an orthographic projection region of an overlapping portion of the semiconductor layer and the first gate electrode region on the substrate is within an orthographic projection region formed by the source electrode region on the substrate, an orthographic projection region of an overlapping portion of the semiconductor layer and the second gate electrode region on the substrate is within an orthographic projection region formed by the drain electrode region on the substrate; and forming an insulating layer above the second source/drain metal layer (39, 310). forming a first source/drain metal layer on a substrate; forming an insulating layer (32, 33) above the first source/drain metal layer, the insulating layer comprising a first insulating region and a second insulating region, the first insulating region and the second insulating region being disposed oppositely with respect to a central line of the first source/drain metal layer with a blank area therebetween; forming a gate metal layer (34, 35) on the insulating layer (32, 33), the gate metal layer (34, 35) comprising a first gate electrode region and a second gate electrode region, and the first gate electrode region covering the first insulating region, the second gate electrode region covering the second insulating region; forming a gate insulating layer on the gate metal layer (34, 35); forming a semiconductor layer above the gate insulating layer, an orthographic projection region of the first source/drain metal layer on the substrate is within an orthographic projection region of the semiconductor layer on the substrate; forming an etching blocking layer on the semiconductor layer, an orthographic projection region of the blank area between the first insulating region and the second insulating region on the substrate is within an orthographic projection region of the etching blocking layer on the substrate; forming a second source/drain metal layer (39, 310) above the etching blocking layer, the second source/drain metal layer (39, 310) comprising a source electrode region and a drain electrode region, characterized in that an orthographic projection region of an overlapping portion of the semiconductor layer and the first gate electrode region on the substrate is within an orthographic projection region formed by the source electrode region on the substrate, an orthographic projection region of an overlapping portion of the semiconductor layer and the second gate electrode region on the substrate is within an orthographic projection region formed by the drain electrode region on the substrate; and forming an insulating layer above the second source/drain metal layer (39, 310).