An interconnect structure for an integrated circuit, IC, comprising: an underlying metal layer, comprising: a plurality of underlying metal lines (208, 208) disposed in a dielectric layer (218) having a top surface comprising an underlying metal line (208) among the plurality of underlying metal lines and an adjacent underlying metal line (208) among the plurality of underlying metal lines adjacent to the underlying metal line; a recess area (216) of a recess width disposed in the dielectric layer below the top surface of the dielectric layer of a recess distance down to the underlying metal line among the plurality of underlying metal lines; an adjacent recess area (216) disposed in the dielectric layer below the top surface of the dielectric layer of the recess distance down to the adjacent underlying metal line; and an etch stop layer disposed in the adjacent recess area, wherein the etch stop layer is comprised of Aluminum Nitride, AlN, and wherein a thickness of the etch stop layer is less than or equal to two, 2, nanometers, nm; an overlying metal layer disposed above the underlying metal layer, the overlying metal layer comprising a plurality of overlying metal lines (210, 210); a second dielectric layer (218) disposed between the underlying metal layer and the overlying metal layer; and a self-aligned via (212) of a via opening width through the second dielectric layer disposed between the underlying metal layer and the overlying metal layer and electrically interconnecting the underlying metal line to an overlying metal line among the plurality of overlying metal lines, wherein the self-aligned via comprises: a first via portion (230) of the self-aligned via extending into the recess area of the underlying metal line to be self-aligned with the underlying metal line; and a second via portion (230) of the self-aligned via extending outside of the recess area of the via opening width. an underlying metal layer, comprising: a plurality of underlying metal lines (208, 208) disposed in a dielectric layer (218) having a top surface comprising an underlying metal line (208) among the plurality of underlying metal lines and an adjacent underlying metal line (208) among the plurality of underlying metal lines adjacent to the underlying metal line; a recess area (216) of a recess width disposed in the dielectric layer below the top surface of the dielectric layer of a recess distance down to the underlying metal line among the plurality of underlying metal lines; an adjacent recess area (216) disposed in the dielectric layer below the top surface of the dielectric layer of the recess distance down to the adjacent underlying metal line; and an etch stop layer disposed in the adjacent recess area, wherein the etch stop layer is comprised of Aluminum Nitride, AlN, and wherein a thickness of the etch stop layer is less than or equal to two, 2, nanometers, nm; a plurality of underlying metal lines (208, 208) disposed in a dielectric layer (218) having a top surface comprising an underlying metal line (208) among the plurality of underlying metal lines and an adjacent underlying metal line (208) among the plurality of underlying metal lines adjacent to the underlying metal line; a recess area (216) of a recess width disposed in the dielectric layer below the top surface of the dielectric layer of a recess distance down to the underlying metal line among the plurality of underlying metal lines; an adjacent recess area (216) disposed in the dielectric layer below the top surface of the dielectric layer of the recess distance down to the adjacent underlying metal line; and an etch stop layer disposed in the adjacent recess area, wherein the etch stop layer is comprised of Aluminum Nitride, AlN, and wherein a thickness of the etch stop layer is less than or equal to two, 2, nanometers, nm; an overlying metal layer disposed above the underlying metal layer, the overlying metal layer comprising a plurality of overlying metal lines (210, 210); a second dielectric layer (218) disposed between the underlying metal layer and the overlying metal layer; and a self-aligned via (212) of a via opening width through the second dielectric layer disposed between the underlying metal layer and the overlying metal layer and electrically interconnecting the underlying metal line to an overlying metal line among the plurality of overlying metal lines, wherein the self-aligned via comprises: a first via portion (230) of the self-aligned via extending into the recess area of the underlying metal line to be self-aligned with the underlying metal line; and a second via portion (230) of the self-aligned via extending outside of the recess area of the via opening width. a first via portion (230) of the self-aligned via extending into the recess area of the underlying metal line to be self-aligned with the underlying metal line; and a second via portion (230) of the self-aligned via extending outside of the recess area of the via opening width.