A SIMD processing module comprising: two or more vector processing units; and a control unit configured to: receive a set of one or more instructions to be executed by each of a plurality of the vector processing units, wherein the set of one or more instructions are to be executed by each vector processing unit on a respective subvector of one or more vectors, wherein each respective subvector is a section within a vector, and wherein each of the plurality of vector processing units is an n-way vector processing unit configured to execute an instruction on n data items of a subvector in parallel, the instructions being arranged to be executed by each vector processing unit so that the set of one or more instructions are executed on n data items of its respective subvector in a first cycle and on the next n data items of its respective subvector in a second cycle; for each of the plurality of the vector processing units, determine a respective vector position indication (Ind) which indicates a position of the subvector within the one or more vectors on which the vector processing unit is to execute the set of one or more instructions; and cause the plurality of n-way vector processing units to execute the set of one or more instructions on subvectors of the one or more vectors in accordance with the vector position indications (Ind); wherein each of the plurality of vector processing units is configured to, on each cycle, execute the set of one or more instructions on n data items in parallel from the respective subvector. two or more vector processing units; and a control unit configured to: receive a set of one or more instructions to be executed by each of a plurality of the vector processing units, wherein the set of one or more instructions are to be executed by each vector processing unit on a respective subvector of one or more vectors, wherein each respective subvector is a section within a vector, and wherein each of the plurality of vector processing units is an n-way vector processing unit configured to execute an instruction on n data items of a subvector in parallel, the instructions being arranged to be executed by each vector processing unit so that the set of one or more instructions are executed on n data items of its respective subvector in a first cycle and on the next n data items of its respective subvector in a second cycle; for each of the plurality of the vector processing units, determine a respective vector position indication (Ind) which indicates a position of the subvector within the one or more vectors on which the vector processing unit is to execute the set of one or more instructions; and cause the plurality of n-way vector processing units to execute the set of one or more instructions on subvectors of the one or more vectors in accordance with the vector position indications (Ind); receive a set of one or more instructions to be executed by each of a plurality of the vector processing units, wherein the set of one or more instructions are to be executed by each vector processing unit on a respective subvector of one or more vectors, wherein each respective subvector is a section within a vector, and wherein each of the plurality of vector processing units is an n-way vector processing unit configured to execute an instruction on n data items of a subvector in parallel, the instructions being arranged to be executed by each vector processing unit so that the set of one or more instructions are executed on n data items of its respective subvector in a first cycle and on the next n data items of its respective subvector in a second cycle; for each of the plurality of the vector processing units, determine a respective vector position indication (Ind) which indicates a position of the subvector within the one or more vectors on which the vector processing unit is to execute the set of one or more instructions; and cause the plurality of n-way vector processing units to execute the set of one or more instructions on subvectors of the one or more vectors in accordance with the vector position indications (Ind); wherein each of the plurality of vector processing units is configured to, on each cycle, execute the set of one or more instructions on n data items in parallel from the respective subvector.