An integrated circuit, IC, connectable to an external resistor network comprising three resistors (6-1, 6-2, 6-3) in a π-configuration, the integrated circuit comprising: - an integrated reference current generation circuit adapted to generate a reference current (I ref) for said integrated circuit and having a first reference voltage source, a first integrated switch, a first amplifier, a first integrated transistor, a first network connection pin, a second reference voltage source, a second integrated switch, a second amplifier (12,) a second integrated transistor and a second network connection pin, - wherein said first reference voltage source supplying a reference voltage (V ref1) via said first integrated switch to said first amplifier; - said second reference voltage source supplying a reference voltage (V ref2) via said second integrated switch to said second amplifier; - the generated reference current (I ref) is a weighted sum of a first current (I 1) flowing through said integrated first transistor via said first network connection pin and a second current (I 2) flowing through said integrated second transistor via said second network connection pin of said integrated circuit to said external reference resistor network connectable to said integrated circuit, IC; and - said network connection pins (4-1, 4-2) are connectable to each other by means of a third integrated switch and to a reference potential by means of said first and second switch (SW1, SW2); - the said integrated circuit further comprising an integrated control circuit adapted to detect a failure in said external reference resistor network on the basis of the first and the second current (I 1, I 2) and to control said integrated switches (SW1, SW2, SW3) such that the reference current (I ref) generated by said integrated reference current generation circuit is maintained constant if a failure occurs in said external reference resistor network; - a fourth integrated switch adapted to interrupt the first current (I 1) flowing through said first integrated transistor and said first network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fourth switch by said integrated control circuit; and - a fifth integrated switch adapted to interrupt said second current (I 2) flowing through an said second integrated transistor via said second network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fifth switch by said integrated control circuit. - an integrated reference current generation circuit adapted to generate a reference current (I ref) for said integrated circuit and having a first reference voltage source, a first integrated switch, a first amplifier, a first integrated transistor, a first network connection pin, a second reference voltage source, a second integrated switch, a second amplifier (12,) a second integrated transistor and a second network connection pin, - wherein said first reference voltage source supplying a reference voltage (V ref1) via said first integrated switch to said first amplifier; - said second reference voltage source supplying a reference voltage (V ref2) via said second integrated switch to said second amplifier; - the generated reference current (I ref) is a weighted sum of a first current (I 1) flowing through said integrated first transistor via said first network connection pin and a second current (I 2) flowing through said integrated second transistor via said second network connection pin of said integrated circuit to said external reference resistor network connectable to said integrated circuit, IC; and - said network connection pins (4-1, 4-2) are connectable to each other by means of a third integrated switch and to a reference potential by means of said first and second switch (SW1, SW2); - the said integrated circuit further comprising an integrated control circuit adapted to detect a failure in said external reference resistor network on the basis of the first and the second current (I 1, I 2) and to control said integrated switches (SW1, SW2, SW3) such that the reference current (I ref) generated by said integrated reference current generation circuit is maintained constant if a failure occurs in said external reference resistor network; - a fourth integrated switch adapted to interrupt the first current (I 1) flowing through said first integrated transistor and said first network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fourth switch by said integrated control circuit; and - a fifth integrated switch adapted to interrupt said second current (I 2) flowing through an said second integrated transistor via said second network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fifth switch by said integrated control circuit.