A method for forming a transistor structure comprising a fin-shaped channel structure, comprising: - providing a layer stack embedded laterally in shallow trench isolation, STI, structures; - recessing said STI structures adjacent to said layer stack to thereby expose an upper portion of said layer stack, said upper portion comprising at least a channel portion; - providing one or more protection layers on said upper portion of said layer stack; - after providing one or more protection layers, further recessing said STI structures selectively to said protection layers and said layer stack, to thereby expose a central portion of said layer stack; - removing said central portion of said layer stack, resulting in a freestanding upper part and a lower part of said layer stack being physically separated from each other; wherein providing said layer stack comprises providing an etch stop layer at a position directly below said channel portion, such that said freestanding upper part of said layer stack comprises the etch stop layer at its lower surface after selectively removing said central portion, and characterized by further comprising: directly after recessing said STI structures adjacent to said layer stack to thereby expose an upper portion of said layer stack, epitaxially growing a wrap-around etch stop layer around said exposed upper portion of said layer stack, said wrap-around etch stop layer embodying a protection layer for further recessing said STI structures, wherein the wrap-around etch stop layer covers sidewalls and an upper surface of said channel portion and together with the etch stop layer forms a full envelope of said channel portion; and providing a gate dielectric layer and gate layer stack on the freestanding upper part of the stack, whereby the wrap-around etch stop layer is not removed. - providing a layer stack embedded laterally in shallow trench isolation, STI, structures; - recessing said STI structures adjacent to said layer stack to thereby expose an upper portion of said layer stack, said upper portion comprising at least a channel portion; - providing one or more protection layers on said upper portion of said layer stack; - after providing one or more protection layers, further recessing said STI structures selectively to said protection layers and said layer stack, to thereby expose a central portion of said layer stack; - removing said central portion of said layer stack, resulting in a freestanding upper part and a lower part of said layer stack being physically separated from each other; wherein providing said layer stack comprises providing an etch stop layer at a position directly below said channel portion, such that said freestanding upper part of said layer stack comprises the etch stop layer at its lower surface after selectively removing said central portion, and characterized by further comprising: directly after recessing said STI structures adjacent to said layer stack to thereby expose an upper portion of said layer stack, epitaxially growing a wrap-around etch stop layer around said exposed upper portion of said layer stack, said wrap-around etch stop layer embodying a protection layer for further recessing said STI structures, wherein the wrap-around etch stop layer covers sidewalls and an upper surface of said channel portion and together with the etch stop layer forms a full envelope of said channel portion; and providing a gate dielectric layer and gate layer stack on the freestanding upper part of the stack, whereby the wrap-around etch stop layer is not removed. directly after recessing said STI structures adjacent to said layer stack to thereby expose an upper portion of said layer stack, epitaxially growing a wrap-around etch stop layer around said exposed upper portion of said layer stack, said wrap-around etch stop layer embodying a protection layer for further recessing said STI structures, wherein the wrap-around etch stop layer covers sidewalls and an upper surface of said channel portion and together with the etch stop layer forms a full envelope of said channel portion; and providing a gate dielectric layer and gate layer stack on the freestanding upper part of the stack, whereby the wrap-around etch stop layer is not removed.