An electronic latch circuit comprising: an output circuit comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108); and an input circuit comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104); wherein the electronic latch circuit comprises only 5 transistors and wherein the input circuit comprises: a first Metal Oxide Semiconductor, MOS, transistor with a gate connected to the first input (A, 102), a source connected to a first voltage potential (VCC, 108) and a drain connected to a first node of the output circuit; a second MOS transistor with a gate connected to the second input (B, 103), a source connected to the first voltage potential (VCC, 108) and a drain connected to a second node of the output circuit; and a third MOS transistor with a gate connected to the clock signal input (CLK, 104), a source connected to a second voltage potential, and a drain connected to a third node of the output circuit; the output circuit comprises: a fourth MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node; and a fifth MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node; and wherein the first output (X, 106) is connected to the first node, the second output (Y, 107) is connected to the second node and the third output (Z, 108) is connected to the third node; and wherein the electronic latch circuit is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit and a present state of the output circuit. an output circuit comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108); and an input circuit comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104); wherein the electronic latch circuit comprises only 5 transistors and wherein the input circuit comprises: a first Metal Oxide Semiconductor, MOS, transistor with a gate connected to the first input (A, 102), a source connected to a first voltage potential (VCC, 108) and a drain connected to a first node of the output circuit; a second MOS transistor with a gate connected to the second input (B, 103), a source connected to the first voltage potential (VCC, 108) and a drain connected to a second node of the output circuit; and a third MOS transistor with a gate connected to the clock signal input (CLK, 104), a source connected to a second voltage potential, and a drain connected to a third node of the output circuit; a first Metal Oxide Semiconductor, MOS, transistor with a gate connected to the first input (A, 102), a source connected to a first voltage potential (VCC, 108) and a drain connected to a first node of the output circuit; a second MOS transistor with a gate connected to the second input (B, 103), a source connected to the first voltage potential (VCC, 108) and a drain connected to a second node of the output circuit; and a third MOS transistor with a gate connected to the clock signal input (CLK, 104), a source connected to a second voltage potential, and a drain connected to a third node of the output circuit; the output circuit comprises: a fourth MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node; and a fifth MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node; and wherein the first output (X, 106) is connected to the first node, the second output (Y, 107) is connected to the second node and the third output (Z, 108) is connected to the third node; and wherein the electronic latch circuit is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit and a present state of the output circuit. a fourth MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node; and a fifth MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node; and wherein the first output (X, 106) is connected to the first node, the second output (Y, 107) is connected to the second node and the third output (Z, 108) is connected to the third node; and wherein the electronic latch circuit is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit and a present state of the output circuit.