A power amplifier comprising: - a pulse wave modulation controller; - a first power control stage configured to drive a first output between VDD and VSS in response to a control signal from the PWM controller; - a second power control stage configured to drive a second output between VDD and VSS in response to a control signal from the PWM controller; and a mid-voltage control circuit configured to: - hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS; and - hold the voltage of the second output at the mid-voltage during an interval between when the second output is driven between VDD and VSS, wherein the mid-voltage control circuit includes: - a voltage holding circuit having an output, - a first switch connected between the first output and the output of the voltage holding circuit to hold the voltage of the first output at the mid-voltage that is between VDD and VSS during the interval between when the first output is driven between VDD and VSS; and - a second switch connected between the second output and the output of the voltage holding circuit to hold the voltage of the second output at the mid-voltage during the interval between when the second output is driven between VDD and VSS, characterized in that the mid-voltage control circuit further includes a freewheel driver circuit configured to drive the first switch and the second switch in response to a freewheel control signal from the PWM controller in order to turn on and off the first switch and the second switch, wherein the freewheel control signal includes two parallel signals that control the first switch and the second switch in parallel, and wherein the PWM controller is configured to adjust said parallel signals to adjust the interval over which the voltage of the first output and the voltage of the second output are held at the mid-voltage. - a pulse wave modulation controller; - a first power control stage configured to drive a first output between VDD and VSS in response to a control signal from the PWM controller; - a second power control stage configured to drive a second output between VDD and VSS in response to a control signal from the PWM controller; and a mid-voltage control circuit configured to: - hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS; and - hold the voltage of the second output at the mid-voltage during an interval between when the second output is driven between VDD and VSS, - hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS; and - hold the voltage of the second output at the mid-voltage during an interval between when the second output is driven between VDD and VSS, - a first switch connected between the first output and the output of the voltage holding circuit to hold the voltage of the first output at the mid-voltage that is between VDD and VSS during the interval between when the first output is driven between VDD and VSS; and - a second switch connected between the second output and the output of the voltage holding circuit to hold the voltage of the second output at the mid-voltage during the interval between when the second output is driven between VDD and VSS,