An integrated circuit device comprising at least one clock monitor, the at least one clock monitor comprising: a timer arranged to: receive a clock signal; generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal; and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that state transition occurs; a detector arranged to: receive at a first input thereof the first timing signal; receive at a second input thereof the second timing signal; compare states of the first and second timing signals (212, 214); and generate an indication of a timing discrepancy signal based at least partly on the comparison of the first and second timing signals (212, 214); characterised in that the detector further comprises a timing violation detector arranged to: receive an indication of whether the states of the first and second timing signals (212, 214) are counterpart states, detect timing discrepancies within the clock signal based at least partly on the indication of whether the states of the first and second timing signals (212, 214) are counterpart states; and generate the indication of a timing discrepancy signal based at least partly on the detection of timing discrepancies within the clock signal. a timer arranged to: receive a clock signal; generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal; and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that state transition occurs; receive a clock signal; generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal; and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that state transition occurs; a detector arranged to: receive at a first input thereof the first timing signal; receive at a second input thereof the second timing signal; compare states of the first and second timing signals (212, 214); and generate an indication of a timing discrepancy signal based at least partly on the comparison of the first and second timing signals (212, 214); receive at a first input thereof the first timing signal; receive at a second input thereof the second timing signal; compare states of the first and second timing signals (212, 214); and generate an indication of a timing discrepancy signal based at least partly on the comparison of the first and second timing signals (212, 214); receive an indication of whether the states of the first and second timing signals (212, 214) are counterpart states, detect timing discrepancies within the clock signal based at least partly on the indication of whether the states of the first and second timing signals (212, 214) are counterpart states; and generate the indication of a timing discrepancy signal based at least partly on the detection of timing discrepancies within the clock signal.