A multiprocessor system having at least two processing modules (14a to 14h), each having at least one processor, and a predetermined processing module, and a ring type bus for relaying data transmission among the processing modules (14a to 14h) and the predetermined processing module, wherein the bus comprises a plurality of data transmission paths (16a to 16d), and the processing modules (14a to 14h) carry out data transmission with respect to the predetermined processing module using any of the plurality of data transmission paths (16a to 16d), characterized by: damaged processor specifying means for specifying at least one damaged processing module among the processing modules (14a to 14h); communication restricted processor selecting means for selecting a processing module to become a communication restricted processing module from among the processing modules (14a to 14h) according to a position where the damaged processing module is connected to the bus, so that, in order to balance the load on the bus, selected communication restricted processing module is carrying out data transmission with respect to the predetermined processing module, using a data transmission path, among the plurality of data transmission paths (16a to 16d), different from a data transmission path to be used in data transmission from the damaged processing module to the predetermined processing module; and communication restricting means for restricting data transmission via the bus by said selected communication restricted processing module, and the communication restricted processor selecting means selects the communication restricted processing module such that the difference of the numbers of all processing modules (12, 20, 14a to 14h, 24, 28) connected to the bus on each path between the position where the damaged processing module is connected to the bus and a position where the communication restricted processing module is connected to the bus is made smaller. damaged processor specifying means for specifying at least one damaged processing module among the processing modules (14a to 14h); communication restricted processor selecting means for selecting a processing module to become a communication restricted processing module from among the processing modules (14a to 14h) according to a position where the damaged processing module is connected to the bus, so that, in order to balance the load on the bus, selected communication restricted processing module is carrying out data transmission with respect to the predetermined processing module, using a data transmission path, among the plurality of data transmission paths (16a to 16d), different from a data transmission path to be used in data transmission from the damaged processing module to the predetermined processing module; and communication restricting means for restricting data transmission via the bus by said selected communication restricted processing module, and the communication restricted processor selecting means selects the communication restricted processing module such that the difference of the numbers of all processing modules (12, 20, 14a to 14h, 24, 28) connected to the bus on each path between the position where the damaged processing module is connected to the bus and a position where the communication restricted processing module is connected to the bus is made smaller.