A reconfigurable interface device (108, 110), comprising: an arrangement of storage elements (220, 222, 224, 226, 228) arranged sequentially in a chain structure, wherein each storage element (220, 222, 224, 226, 228) is configured for storing a state of a binary signal; a combinatorial logic circuitry connectable to the arrangement of storage elements, wherein the combinatorial logic circuitry is configured to enable the arrangement of storage elements to form a binary synchronous counter; a bypass logic circuitry connectable to the arrangement of storage elements, wherein the bypass logic circuitry is configured to enable the arrangement of storage elements to form a serial shift register; a switching circuitry having a mode signal input terminal for receiving a mode signal indicative of at least one of a counter mode and a shift register mode, wherein the switching circuitry is configured to selectively connect the arrangement of storage elements (220, 222, 224, 226, 228) to the combinatory logic circuitry if the mode signal indicates the counter mode, and to selectively connect the arrangement of storage elements (220, 222, 224, 226, 228) to the bypass logic circuitry if the mode signal indicates the shift register mode; and an input signal switching unit having a first input terminal for receiving a predefined time-invariant signal, a second input terminal for receiving a stream of binary data signals varying in time, and an output terminal to which one of the time-invariant signal and binary data signals is selectively transmitted based on the mode signal, wherein the input signal switching unit is configured to selectively present the time-invariant signal at an output terminal if the mode signal indicates the counter mode, and to selectively present the data signal stream at an output terminal if the mode signal indicates the shift register mode. an arrangement of storage elements (220, 222, 224, 226, 228) arranged sequentially in a chain structure, wherein each storage element (220, 222, 224, 226, 228) is configured for storing a state of a binary signal; a combinatorial logic circuitry connectable to the arrangement of storage elements, wherein the combinatorial logic circuitry is configured to enable the arrangement of storage elements to form a binary synchronous counter; a bypass logic circuitry connectable to the arrangement of storage elements, wherein the bypass logic circuitry is configured to enable the arrangement of storage elements to form a serial shift register; a switching circuitry having a mode signal input terminal for receiving a mode signal indicative of at least one of a counter mode and a shift register mode, wherein the switching circuitry is configured to selectively connect the arrangement of storage elements (220, 222, 224, 226, 228) to the combinatory logic circuitry if the mode signal indicates the counter mode, and to selectively connect the arrangement of storage elements (220, 222, 224, 226, 228) to the bypass logic circuitry if the mode signal indicates the shift register mode; and to selectively connect the arrangement of storage elements (220, 222, 224, 226, 228) to the combinatory logic circuitry if the mode signal indicates the counter mode, and to selectively connect the arrangement of storage elements (220, 222, 224, 226, 228) to the bypass logic circuitry if the mode signal indicates the shift register mode; and an input signal switching unit having a first input terminal for receiving a predefined time-invariant signal, a second input terminal for receiving a stream of binary data signals varying in time, and an output terminal to which one of the time-invariant signal and binary data signals is selectively transmitted based on the mode signal, wherein the input signal switching unit is configured to selectively present the time-invariant signal at an output terminal if the mode signal indicates the counter mode, and to selectively present the data signal stream at an output terminal if the mode signal indicates the shift register mode. to selectively present the time-invariant signal at an output terminal if the mode signal indicates the counter mode, and to selectively present the data signal stream at an output terminal if the mode signal indicates the shift register mode.