A microprocessor, comprising: a first-level cache memory; a second-level cache memory; and a data prefetcher, wherein the data prefetcher is configured to: detect a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetch cache lines into the second-level cache memory based on the predominant direction and pattern; receive from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line; determine one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction; and cause the one or more cache lines to be prefetched into the first-level cache memory; characterised in that in order to detect the predominant direction and pattern, the data prefetcher is configured to: maintain, as the recent memory accesses are received, largest and smallest addresses thereof within a memory block and counts of changes to the largest and smallest addresses; and determine the predominant direction based on the counts. a first-level cache memory; a second-level cache memory; and a data prefetcher, wherein the data prefetcher is configured to: detect a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetch cache lines into the second-level cache memory based on the predominant direction and pattern; receive from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line; determine one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction; and cause the one or more cache lines to be prefetched into the first-level cache memory; characterised in that in order to detect the predominant direction and pattern, the data prefetcher is configured to: maintain, as the recent memory accesses are received, largest and smallest addresses thereof within a memory block and counts of changes to the largest and smallest addresses; and determine the predominant direction based on the counts. detect a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetch cache lines into the second-level cache memory based on the predominant direction and pattern; receive from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line; determine one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction; and cause the one or more cache lines to be prefetched into the first-level cache memory; characterised in that in order to detect the predominant direction and pattern, the data prefetcher is configured to: maintain, as the recent memory accesses are received, largest and smallest addresses thereof within a memory block and counts of changes to the largest and smallest addresses; and determine the predominant direction based on the counts. maintain, as the recent memory accesses are received, largest and smallest addresses thereof within a memory block and counts of changes to the largest and smallest addresses; and determine the predominant direction based on the counts.