A computer implemented method for replacing an atomic sequence (605, 610), wherein the atomic sequence comprises a sequence of instructions executed atomically, the sequence comprising a load reserve instruction (lwarx) and a store conditional instruction (stwcx), the method comprising: receiving, by a processing circuit, the atomic sequence; detecting (805, 1210), by the processing circuit, the atomic sequence; generating (810, 1215), by the processing circuit, an internal atomic operation (615, 620, 625) to replace the atomic sequence, wherein the internal atomic operation is a single instruction, the generating characterised by: based on separate instructions of the atomic sequence not being in a same group and based on the separate instructions being positioned to execute separately, configuring the instruction decoder to initially mark the load reserve instruction based on the load reserve instruction being detected first in the separate instructions or initially mark the store conditional instruction based on the store conditional instruction being detected first in the separate instructions; in response to configuring the instruction decoder to initially mark, configuring an instruction decoder to perform instruction cache marking of the separate instructions that are not in the same group to force the load reserve instruction and the store conditional instruction into the same group, wherein a group comprises a plurality of instructions fetched by the instruction cache; configuring the instruction decoder to complete formation of the same group by marking the load reserve instruction based on the load reserve instruction being detected last in the separate instructions or by marking the store conditional instruction based on the store conditional instruction being detected last in the separate instructions; and configuring the instruction decode to translate the separate instructions having been grouped into the same group for the atomic sequence into the internal atomic operation. receiving, by a processing circuit, the atomic sequence; detecting (805, 1210), by the processing circuit, the atomic sequence; generating (810, 1215), by the processing circuit, an internal atomic operation (615, 620, 625) to replace the atomic sequence, wherein the internal atomic operation is a single instruction, the generating characterised by: based on separate instructions of the atomic sequence not being in a same group and based on the separate instructions being positioned to execute separately, configuring the instruction decoder to initially mark the load reserve instruction based on the load reserve instruction being detected first in the separate instructions or initially mark the store conditional instruction based on the store conditional instruction being detected first in the separate instructions; in response to configuring the instruction decoder to initially mark, configuring an instruction decoder to perform instruction cache marking of the separate instructions that are not in the same group to force the load reserve instruction and the store conditional instruction into the same group, wherein a group comprises a plurality of instructions fetched by the instruction cache; configuring the instruction decoder to complete formation of the same group by marking the load reserve instruction based on the load reserve instruction being detected last in the separate instructions or by marking the store conditional instruction based on the store conditional instruction being detected last in the separate instructions; and configuring the instruction decode to translate the separate instructions having been grouped into the same group for the atomic sequence into the internal atomic operation. based on separate instructions of the atomic sequence not being in a same group and based on the separate instructions being positioned to execute separately, configuring the instruction decoder to initially mark the load reserve instruction based on the load reserve instruction being detected first in the separate instructions or initially mark the store conditional instruction based on the store conditional instruction being detected first in the separate instructions; in response to configuring the instruction decoder to initially mark, configuring an instruction decoder to perform instruction cache marking of the separate instructions that are not in the same group to force the load reserve instruction and the store conditional instruction into the same group, wherein a group comprises a plurality of instructions fetched by the instruction cache; configuring the instruction decoder to complete formation of the same group by marking the load reserve instruction based on the load reserve instruction being detected last in the separate instructions or by marking the store conditional instruction based on the store conditional instruction being detected last in the separate instructions; and configuring the instruction decode to translate the separate instructions having been grouped into the same group for the atomic sequence into the internal atomic operation.