A semiconductor construction comprising a transistor comprising a gate; a source region; a drain region; a channel region between the source and drain regions (26, 28); and a gate dielectric (18e, 20, 22) between the gate and the source, drain and channel regions;the semiconductor construction further comprising: a semiconductor base; wherein the gate extends into the semiconductor base; a first region of the semiconductor base adjacent the gate being conductively-doped and providing the source region, and a second region of the semiconductor base adjacent the gate and spaced from the first region being conductively-doped and providing the drain region; wherein the gate dielectric consists of a first segment between the source region and the gate, a second segment between the drain region and the gate and a third segment between the first and second segments (23, 25); wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein; wherein the first segment of the gate dielectric comprises a first vertical leg of the container, the second segment of the gate dielectric comprises a second vertical leg of the container, and the third segment of the gate dielectric comprises a bottom of the container; wherein the gate dielectric comprises a first material as the entire outer boundary of the container and which is directly positioned against the semiconductor base; wherein the first material is a non-ferroelectric material; wherein the non-ferroelectric material is within the first, second, and third segments (23, 25, 27); wherein the gate dielectric comprises a second material between the first material and the gate within the first, second and third segments (23, 25, 27); wherein the second material is a ferroelectric material; characterised in that the non-ferroelectric material is thicker along the bottom of the container than along the first and second vertical legs (23, 25) of the container. a semiconductor base; wherein the gate extends into the semiconductor base; a first region of the semiconductor base adjacent the gate being conductively-doped and providing the source region, and a second region of the semiconductor base adjacent the gate and spaced from the first region being conductively-doped and providing the drain region; wherein the gate dielectric consists of a first segment between the source region and the gate, a second segment between the drain region and the gate and a third segment between the first and second segments (23, 25); wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein; wherein the first segment of the gate dielectric comprises a first vertical leg of the container, the second segment of the gate dielectric comprises a second vertical leg of the container, and the third segment of the gate dielectric comprises a bottom of the container; wherein the gate dielectric comprises a first material as the entire outer boundary of the container and which is directly positioned against the semiconductor base; wherein the first material is a non-ferroelectric material; wherein the non-ferroelectric material is within the first, second, and third segments (23, 25, 27); wherein the gate dielectric comprises a second material between the first material and the gate within the first, second and third segments (23, 25, 27); wherein the second material is a ferroelectric material; characterised in that the non-ferroelectric material is thicker along the bottom of the container than along the first and second vertical legs (23, 25) of the container.