A CPU unit of a PLC controlling a control target, comprising: a microprocessor; a memory means (104, 106); a communication circuit (120, 140) configured to transmit output data and to receive input data; and a means configured to set a constant period of a control cycle, wherein the CPU unit of the PLC is configured so as to control the control target by repeating transmission of the output data, reception of the input data, and execution of a first control program that generates the output data using the input data, the first control program and a scheduler program controlling execution of the first control program are stored in the memory means (104, 106), the microprocessor is configured to execute the scheduler program and the first control program, which are stored in the memory means (104, 106), characterized in that the communication circuit (120, 140) is configured to transmit the output data and to receive the input data with the constant period of the control cycle, the communication circuit (120, 140) is configured so as to start transmission of the output data and reception of the input data controlled by the microprocessor, the CPU unit is configured such that, if the control program has not ended by the end of a control cyle, execution of the control program is interrupted, and the scheduler program includes: a command causing the microprocessor to start execution of the first control program after the communication circuit (120, 140) transmits the output data and receives the input data, in a control cycle following a control cycle in which the first control program has ended execution; a command causing the microprocessor to execute an unexecuted portion of the first control program in a control cycle following a control cycle in which the first control program has not ended execution a command causing the communication circuit (120, 140) to start the communication with the constant period of the control cycle, and a command causing, in a case where execution of the first control program has not ended within a control cycle, the communication circuit (120, 140) to execute, in the following control cycle, processing to start the communication in preference to the unexecuted portion of the first control program and then causing the microprocessor to execute the unexecuted portion of the first control program. a microprocessor; a memory means (104, 106); a communication circuit (120, 140) configured to transmit output data and to receive input data; and a means configured to set a constant period of a control cycle, wherein a command causing the microprocessor to start execution of the first control program after the communication circuit (120, 140) transmits the output data and receives the input data, in a control cycle following a control cycle in which the first control program has ended execution; a command causing the microprocessor to execute an unexecuted portion of the first control program in a control cycle following a control cycle in which the first control program has not ended execution a command causing the communication circuit (120, 140) to start the communication with the constant period of the control cycle, and a command causing, in a case where execution of the first control program has not ended within a control cycle, the communication circuit (120, 140) to execute, in the following control cycle, processing to start the communication in preference to the unexecuted portion of the first control program and then causing the microprocessor to execute the unexecuted portion of the first control program.