A circuit, comprising: a rectifier stage including a differential input transistor pair (M 1, M 2) coupled between a reference voltage node and an intermediate node, and a load (M 3, R F, C F) coupled between the intermediate node and a supply voltage node (Vcc), the differential input transistor pair (M 1, M 2) being configured to receive a radio-frequency amplitude modulated signal ( S RF+, S RF-), wherein a rectified signal indicative of an envelope of said radio-frequency amplitude modulated signal ( S RF+, S RF-) is produced at said intermediate node; an amplifier stage (82; 83) coupled to said intermediate node to receive said rectified signal and configured to produce at an output node an amplified rectified signal ( ENV OUT) indicative of the envelope of said radio-frequency amplitude modulated signal ( S RF+, S RF-), wherein the rectifier stage further comprises a first resistive element (R L1) coupled between said intermediate node and said supply voltage node ( Vcc) in parallel to said load (M 3, R F, C F), the circuit being characterized in that said amplifier stage (82; 83) comprises: an output transistor (M 6) arranged in a common source or common emitter configuration and an output load (R L3) coupled between a drain or collector terminal of said output transistor (M 6) and said reference voltage node, wherein said output node is intermediate said drain or collector terminal of said output transistor (M 6) and said output load (R L3); a current-matching transistor (M 4) having a current path arranged between said supply voltage node ( Vcc) and a current control node, and a control terminal coupled to said intermediate node; a bias source coupled between said current control node and said reference voltage node to sink a current ( I b) from said current control node; and a current-mirroring transistor (M 5) having a current path arranged between said supply voltage node ( Vcc) and said current control node, and having a drain or collector terminal coupled to its control terminal, and in that the control terminal of said current-mirroring transistor (M 5) is coupled to a control terminal of said output transistor (M 6). a rectifier stage including a differential input transistor pair (M 1, M 2) coupled between a reference voltage node and an intermediate node, and a load (M 3, R F, C F) coupled between the intermediate node and a supply voltage node (Vcc), the differential input transistor pair (M 1, M 2) being configured to receive a radio-frequency amplitude modulated signal ( S RF+, S RF-), wherein a rectified signal indicative of an envelope of said radio-frequency amplitude modulated signal ( S RF+, S RF-) is produced at said intermediate node; an amplifier stage (82; 83) coupled to said intermediate node to receive said rectified signal and configured to produce at an output node an amplified rectified signal ( ENV OUT) indicative of the envelope of said radio-frequency amplitude modulated signal ( S RF+, S RF-), wherein the rectifier stage further comprises a first resistive element (R L1) coupled between said intermediate node and said supply voltage node ( Vcc) in parallel to said load (M 3, R F, C F), the circuit being characterized in that said amplifier stage (82; 83) comprises: an output transistor (M 6) arranged in a common source or common emitter configuration and an output load (R L3) coupled between a drain or collector terminal of said output transistor (M 6) and said reference voltage node, wherein said output node is intermediate said drain or collector terminal of said output transistor (M 6) and said output load (R L3); a current-matching transistor (M 4) having a current path arranged between said supply voltage node ( Vcc) and a current control node, and a control terminal coupled to said intermediate node; a bias source coupled between said current control node and said reference voltage node to sink a current ( I b) from said current control node; and a current-mirroring transistor (M 5) having a current path arranged between said supply voltage node ( Vcc) and said current control node, and having a drain or collector terminal coupled to its control terminal, an output transistor (M 6) arranged in a common source or common emitter configuration and an output load (R L3) coupled between a drain or collector terminal of said output transistor (M 6) and said reference voltage node, wherein said output node is intermediate said drain or collector terminal of said output transistor (M 6) and said output load (R L3); a current-matching transistor (M 4) having a current path arranged between said supply voltage node ( Vcc) and a current control node, and a control terminal coupled to said intermediate node; a bias source coupled between said current control node and said reference voltage node to sink a current ( I b) from said current control node; and a current-mirroring transistor (M 5) having a current path arranged between said supply voltage node ( Vcc) and said current control node, and having a drain or collector terminal coupled to its control terminal, and in that the control terminal of said current-mirroring transistor (M 5) is coupled to a control terminal of said output transistor (M 6).