A resource domain controller comprising: a master domain assignment controller, MDAC, comprising a plurality of MDAC instances, wherein a first MDAC instance comprises: a first plurality of registers corresponding to a processor bus master, the first plurality of registers comprising a first register corresponding to a first set of process identifiers, PIDs, and a second register corresponding to a second set of PIDs; comparison circuitry coupled to receive an input PID (PID_IN) from the processor and configured to determine if the input PID is one of the first set or the second set of PIDs, wherein: when the input PID is one of the first set of PIDs, a first output domain identifier, DID, is generated, and when the input PID is one of the second set of PIDs, a second output DID is generated, wherein the second output DID is different from the first output DID; and wherein a further MDAC instance comprises: one or more registers corresponding to a corresponding further non-processor bus master coupled to the MDAC, and corresponding comparison circuitry configured to generate a corresponding output DID using the one or more registers; and wherein the resource domain controller further comprises: a switch fabric coupled to receive an output DID from the MDAC and coupled to a plurality of slaves (130,132,134), wherein the switch fabric is configured to provide communication between the masters and the slaves. a master domain assignment controller, MDAC, comprising a plurality of MDAC instances, wherein a first MDAC instance comprises: a first plurality of registers corresponding to a processor bus master, the first plurality of registers comprising a first register corresponding to a first set of process identifiers, PIDs, and a second register corresponding to a second set of PIDs; comparison circuitry coupled to receive an input PID (PID_IN) from the processor and configured to determine if the input PID is one of the first set or the second set of PIDs, wherein: when the input PID is one of the first set of PIDs, a first output domain identifier, DID, is generated, and when the input PID is one of the second set of PIDs, a second output DID is generated, wherein the second output DID is different from the first output DID; and a first plurality of registers corresponding to a processor bus master, the first plurality of registers comprising a first register corresponding to a first set of process identifiers, PIDs, and a second register corresponding to a second set of PIDs; comparison circuitry coupled to receive an input PID (PID_IN) from the processor and configured to determine if the input PID is one of the first set or the second set of PIDs, wherein: when the input PID is one of the first set of PIDs, a first output domain identifier, DID, is generated, and when the input PID is one of the second set of PIDs, a second output DID is generated, wherein the second output DID is different when the input PID is one of the first set of PIDs, a first output domain identifier, DID, is generated, and when the input PID is one of the second set of PIDs, a second output DID is generated, wherein the second output DID is different from the first output DID; and wherein a further MDAC instance comprises: one or more registers corresponding to a corresponding further non-processor bus master coupled to the MDAC, and corresponding comparison circuitry configured to generate a corresponding output DID using the one or more registers; and one or more registers corresponding to a corresponding further non-processor bus master coupled to the MDAC, and corresponding comparison circuitry configured to generate a corresponding output DID using the one or more registers; and wherein the resource domain controller further comprises: a switch fabric coupled to receive an output DID from the MDAC and coupled to a plurality of slaves (130,132,134), wherein the switch fabric is configured to provide communication between the masters and the slaves.