A junction field-effect transistor, JFET, comprising: a. a silicon carbide, SiC, drift region atop a SiC drain, the drift region and the drain being of a first doping type; b. above and vertically abutting the drift region, a SiC bottom gate region having outer dimensions in plan view corresponding to a shape, the bottom gate region being of the second doping type; c. above and vertically abutting the bottom gate region, a SiC horizontal channel region having the same outer dimensions in plan view corresponding to the same shape, the horizontal channel region being vertically aligned with the bottom gate region, the horizontal channel region being of the first doping type, where the doping concentration of the horizontal channel region is lower than the doping concentration of the drain (N+) and higher than the doping concentration of the drift region (N-); d. above and vertically abutting the horizontal channel region, a SiC top gate region (105a; 105c) having the same outer dimensions in plan view corresponding to the same shape, the top gate region being vertically aligned with the bottom gate region, the top gate region being of a second doping type the top gate region, the horizontal channel region and the bottom gate region being implanted using a first mask; e. a connection from the top gate region (105a; 105c) to the bottom gate region; f. within the outer dimensions in plan view of the top gate region (105a; 105c), a source region; and g. abutting the top gate region (105a; 105c), horizontal channel region, and bottom gate region to one side, a SiC vertical channel region (102a; 102b), the SiC vertical channel region (102a; 102b) being of the first doping type, the vertical channel region (102a; 102b) extending vertically below the bottom gate region to abut the drift region; h. where doping concentrations of the drain, the vertical channel region (105a; 105c), and the horizontal channel region respectively are selected such that the threshold voltage of the JFET is set by the horizontal channel region, i. such that, when activated by the top gate region and the bottom gate region, current flows from the source region into the horizontal channel region and then into the vertical channel region, the drift region, and the drain. a. a silicon carbide, SiC, drift region atop a SiC drain, the drift region and the drain being of a first doping type; b. above and vertically abutting the drift region, a SiC bottom gate region having outer dimensions in plan view corresponding to a shape, the bottom gate region being of the second doping type; c. above and vertically abutting the bottom gate region, a SiC horizontal channel region having the same outer dimensions in plan view corresponding to the same shape, the horizontal channel region being vertically aligned with the bottom gate region, the horizontal channel region being of the first doping type, where the doping concentration of the horizontal channel region is lower than the doping concentration of the drain (N+) and higher than the doping concentration of the drift region (N-); d. above and vertically abutting the horizontal channel region, a SiC top gate region (105a; 105c) having the same outer dimensions in plan view corresponding to the same shape, the top gate region being vertically aligned with the bottom gate region, the top gate region being of a second doping type the top gate region, the horizontal channel region and the bottom gate region being implanted using a first mask; e. a connection from the top gate region (105a; 105c) to the bottom gate region; f. within the outer dimensions in plan view of the top gate region (105a; 105c), a source region; and g. abutting the top gate region (105a; 105c), horizontal channel region, and bottom gate region to one side, a SiC vertical channel region (102a; 102b), the SiC vertical channel region (102a; 102b) being of the first doping type, the vertical channel region (102a; 102b) extending vertically below the bottom gate region to abut the drift region; h. where doping concentrations of the drain, the vertical channel region (105a; 105c), and the horizontal channel region respectively are selected such that the threshold voltage of the JFET is set by the horizontal channel region, i. such that, when activated by the top gate region and the bottom gate region, current flows from the source region into the horizontal channel region and then into the vertical channel region, the drift region, and the drain.