A reconfigurable instruction cell array, RICA, comprising: an array of switch boxes organized into broadcast sets of switch boxes (210 - 215), each switch box including a programmable instruction cell and switch fabric configurable according to a corresponding configuration word, each switch box (210 - 215) including a latch array configured to store the corresponding configuration word, wherein each configuration word comprises a plurality of configuration bits and each latch array comprises a plurality of latches corresponding to the plurality of configuration bits; a plurality of configuration busses corresponding to the plurality of broadcast sets, each configuration bus comprising a plurality of configuration bit conductors corresponding to the plurality of configuration bits, each configuration bit conductor configured to conduct the corresponding configuration bit, wherein for each broadcast set, the corresponding bit conductor for each configuration bit couples to a data input terminal for the corresponding latch in each latch array for the broadcast set; and an addressing circuit configured to consecutively address the latch arrays such that each latch array latches its corresponding configuration word from the corresponding configuration bus, wherein each latch array is configured to be transparent in a non-address state and to be closed when addressed by the addressing circuit; and wherein the switch boxes (210 - 215) are arranged into rows and columns, and wherein the addressing circuit is configured to consecutively address the latch arrays for each row of switch boxes; and wherein the address circuit comprises a shift register; and wherein the shift register is configured to be reset in a default state and to consecutively shift a latching word comprising all logical ones responsive to cycles of a RICA clock to consecutively close rows of the latch arrays. an array of switch boxes organized into broadcast sets of switch boxes (210 - 215), each switch box including a programmable instruction cell and switch fabric configurable according to a corresponding configuration word, each switch box (210 - 215) including a latch array configured to store the corresponding configuration word, wherein each configuration word comprises a plurality of configuration bits and each latch array comprises a plurality of latches corresponding to the plurality of configuration bits; a plurality of configuration busses corresponding to the plurality of broadcast sets, each configuration bus comprising a plurality of configuration bit conductors corresponding to the plurality of configuration bits, each configuration bit conductor configured to conduct the corresponding configuration bit, wherein for each broadcast set, the corresponding bit conductor for each configuration bit couples to a data input terminal for the corresponding latch in each latch array for the broadcast set; and an addressing circuit configured to consecutively address the latch arrays such that each latch array latches its corresponding configuration word from the corresponding configuration bus, wherein each latch array is configured to be transparent in a non-address state and to be closed when addressed by the addressing circuit; and wherein the switch boxes (210 - 215) are arranged into rows and columns, and wherein the addressing circuit is configured to consecutively address the latch arrays for each row of switch boxes; and wherein the address circuit comprises a shift register; and wherein the shift register is configured to be reset in a default state and to consecutively shift a latching word comprising all logical ones responsive to cycles of a RICA clock to consecutively close rows of the latch arrays.