A SRAM device biasing circuit, comprising: a pair of semiconductor devices (410, 420, 910, 920) configured to: receive a supply voltage from a power supply providing a supply voltage level suitable for operating a SRAM device in an active mode; and provide, using the supply voltage, an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the SRAM device in a data retention mode, the pair of semiconductor devices comprising: a first semiconductor device (410, 910); and, a second semiconductor device (420, 920) comprising a bulk portion, wherein the second semiconductor device is an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices comprises each of an NMOS semiconductor device and a PMOS semiconductor device; and, a bias adjustment circuit coupled to the bulk portion of the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage, wherein the bias adjustment circuit changes a threshold voltage characteristic of the second semiconductor device. a pair of semiconductor devices (410, 420, 910, 920) configured to: receive a supply voltage from a power supply providing a supply voltage level suitable for operating a SRAM device in an active mode; and provide, using the supply voltage, an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the SRAM device in a data retention mode, the pair of semiconductor devices comprising: a first semiconductor device (410, 910); and, a second semiconductor device (420, 920) comprising a bulk portion, wherein the second semiconductor device is an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices comprises each of an NMOS semiconductor device and a PMOS semiconductor device; and, receive a supply voltage from a power supply providing a supply voltage level suitable for operating a SRAM device in an active mode; and provide, using the supply voltage, an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the SRAM device in a data retention mode, the pair of semiconductor devices comprising: a first semiconductor device (410, 910); and, a second semiconductor device (420, 920) comprising a bulk portion, wherein the second semiconductor device is an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices comprises each of an NMOS semiconductor device and a PMOS semiconductor device; and, a first semiconductor device (410, 910); and, a second semiconductor device (420, 920) comprising a bulk portion, wherein the second semiconductor device is an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices comprises each of an NMOS semiconductor device and a PMOS semiconductor device; and, a bias adjustment circuit coupled to the bulk portion of the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage, wherein the bias adjustment circuit changes a threshold voltage characteristic of the second semiconductor device.