A method of operating an electrostatic discharge, "ESD" protection device to provide ESD protection against a system level ESD pulse comprising a first current peak and a subsequent second current peak that is lower than the first current peak, the ESD protection device comprising: a voltage rail and a power supply rail for providing a supply voltage; a resistor connected to the voltage rail; an NMOS transistor connected between the power supply rail and the voltage rail, wherein the NMOS transistor comprises: a drain terminal connected to the power supply rail; a source terminal connected to the voltage rail; a gate terminal; and a body, wherein the gate terminal and the body of the NMOS transistor are connected to the source terminal via the resistor and said voltage rail; and a bigFET connected between the power supply rail and the voltage rail and in parallel with the NMOS transistor; a device to be protected connected in parallel with the ESD protection device; and a decoupling capacitor connected in parallel with the NMOS transistor, wherein the decoupling capacitor has a parasitic inductance, the method comprising: the decoupling capacitor suppressing ripple on the supply voltage during normal operation of the ESD protection device; the NMOS transistor shunting current between the power supply rail and the voltage rail during the first peak of the ESD pulse; the bigFET conducting ESD current between the power supply rail and the voltage rail during the second peak of the ESD pulse; and during the system level ESD pulse, the decoupling capacitor storing a portion of the second current peak of the ESD pulse not shunted by the bigFET of the ESD protection device at a voltage that is lower than a threshold voltage of the NMOS transistor. a voltage rail and a power supply rail for providing a supply voltage; a resistor connected to the voltage rail; an NMOS transistor connected between the power supply rail and the voltage rail, wherein the NMOS transistor comprises: a drain terminal connected to the power supply rail; a source terminal connected to the voltage rail; a gate terminal; and a body, wherein the gate terminal and the body of the NMOS transistor are connected to the source terminal via the resistor and said voltage rail; and a drain terminal connected to the power supply rail; a source terminal connected to the voltage rail; a gate terminal; and a body, wherein the gate terminal and the body of the NMOS transistor are connected to the source terminal via the resistor and said voltage rail; and a bigFET connected between the power supply rail and the voltage rail and in parallel with the NMOS transistor; a device to be protected connected in parallel with the ESD protection device; and a decoupling capacitor connected in parallel with the NMOS transistor, wherein the decoupling capacitor has a parasitic inductance, the method comprising: the decoupling capacitor suppressing ripple on the supply voltage during normal operation of the ESD protection device; the NMOS transistor shunting current between the power supply rail and the voltage rail during the first peak of the ESD pulse; the bigFET conducting ESD current between the power supply rail and the voltage rail during the second peak of the ESD pulse; and during the system level ESD pulse, the decoupling capacitor storing a portion of the second current peak of the ESD pulse not shunted by the bigFET of the ESD protection device at a voltage that is lower than a threshold voltage of the NMOS transistor. the decoupling capacitor suppressing ripple on the supply voltage during normal operation of the ESD protection device; the NMOS transistor shunting current between the power supply rail and the voltage rail during the first peak of the ESD pulse; the bigFET conducting ESD current between the power supply rail and the voltage rail during the second peak of the ESD pulse; and during the system level ESD pulse, the decoupling capacitor storing a portion of the second current peak of the ESD pulse not shunted by the bigFET of the ESD protection device at a voltage that is lower than a threshold voltage of the NMOS transistor.