A clock switching control circuit, comprising: a power control logic configured to switch an electronic circuit from a first reference clock signal associated with a first operation mode to a second reference clock signal associated with a second operation mode; and an oscillation detection logic comprising a ripple divider and coupled to the power control logic wherein the ripple divider is configured to derive a plurality of divided clock signals from the second reference clock signal, wherein each of the plurality of divided clock signals has a slower respective frequency than the second reference clock signal; the oscillation detection logic is configured to: programmably select a sampled clock signal among the plurality of divided clock signals based on the first reference clock signal; provide one or more edge detect indications of the sampled clock signal to a sampling comparison logic configured to: provide a frequency match indication for each of the one or more edge detect indications having a respective frequency differential between the edge detect indication and the first reference clock signal less than a predetermined frequency match threshold; determine that the second reference clock signal is stable if a count of consecutive frequency match indications is greater than or equal to a predetermined clock stability threshold; and provide a clock stability indication to the power control logic if the second reference clock signal is determined stable; wherein the power control logic is configured to control the electronic circuit to switch from the first reference clock signal to the second reference clock signal in response to receiving the clock stability indication. a power control logic configured to switch an electronic circuit from a first reference clock signal associated with a first operation mode to a second reference clock signal associated with a second operation mode; and an oscillation detection logic comprising a ripple divider and coupled to the power control logic wherein the ripple divider is configured to derive a plurality of divided clock signals from the second reference clock signal, wherein each of the plurality of divided clock signals has a slower respective frequency than the second reference clock signal; the oscillation detection logic is configured to: programmably select a sampled clock signal among the plurality of divided clock signals based on the first reference clock signal; provide one or more edge detect indications of the sampled clock signal to a sampling comparison logic configured to: provide a frequency match indication for each of the one or more edge detect indications having a respective frequency differential between the edge detect indication and the first reference clock signal less than a predetermined frequency match threshold; determine that the second reference clock signal is stable if a count of consecutive frequency match indications is greater than or equal to a predetermined clock stability threshold; and provide a clock stability indication to the power control logic if the second reference clock signal is determined stable; programmably select a sampled clock signal among the plurality of divided clock signals based on the first reference clock signal; provide one or more edge detect indications of the sampled clock signal to a sampling comparison logic configured to: provide a frequency match indication for each of the one or more edge detect indications having a respective frequency differential between the edge detect indication and the first reference clock signal less than a predetermined frequency match threshold; determine that the second reference clock signal is stable if a count of consecutive frequency match indications is greater than or equal to a predetermined clock stability threshold; and provide a clock stability indication to the power control logic if the second reference clock signal is determined stable; wherein the power control logic is configured to control the electronic circuit to switch from the first reference clock signal to the second reference clock signal in response to receiving the clock stability indication.