An apparatus, comprising: a register store to store vector operands, each vector operand comprising a plurality of elements; execution circuitry to execute instructions in order to perform operations specified by the instructions, the execution circuitry comprising access circuitry to perform memory access operations in order to move the vector operands between the register store and memory, and processing circuitry to perform data processing operations using said vector operands; the execution circuitry being arranged to iteratively execute a vector loop, during each iteration the execution circuitry being arranged to execute a sequence of instructions to implement the vector loop, said sequence including a check instruction identifying a plurality of memory addresses, and the execution circuitry being responsive to execution of the check instruction to determine whether an address hazard condition exists amongst the plurality of memory addresses; for each iteration of the vector loop, the execution circuitry being responsive to execution of the check instruction determining an absence of said address hazard condition, to employ a default level of vectorisation when executing the sequence of instructions to implement the vector loop, and being responsive to execution of the check instruction determining a presence of said address hazard condition, to employ a reduced level of vectorisation when executing the sequence of instructions to implement the vector loop; wherein at the start of each iteration of the vector loop, the execution circuitry is arranged to revert to employing the default level of vectorisation; wherein the execution circuitry is responsive to execution of the check instruction determining the absence of said address hazard condition, to employ said default level of vectorisation by executing a first plurality of instructions within said sequence of instructions to implement the vector loop; and the execution circuitry is responsive to execution of the check instruction determining the presence of said address hazard condition, to employ said reduced level of vectorisation by iteratively executing a second plurality of instructions within said sequence of instructions to implement the vector loop; and wherein the execution circuitry is responsive to execution of said check instruction to generate result data indicating whether said address hazard condition exists, for reference by a subsequent instruction in said sequence; and wherein said result data comprises one or more flags, and said subsequent instruction is a branch instruction which, when executed by the execution circuitry, references the one or more flags in order to determine whether to execute said first plurality of instructions or whether to iteratively execute said second plurality of instructions. a register store to store vector operands, each vector operand comprising a plurality of elements; execution circuitry to execute instructions in order to perform operations specified by the instructions, the execution circuitry comprising access circuitry to perform memory access operations in order to move the vector operands between the register store and memory, and processing circuitry to perform data processing operations using said vector operands; the execution circuitry being arranged to iteratively execute a vector loop, during each iteration the execution circuitry being arranged to execute a sequence of instructions to implement the vector loop, said sequence including a check instruction identifying a plurality of memory addresses, and the execution circuitry being responsive to execution of the check instruction to determine whether an address hazard condition exists amongst the plurality of memory addresses; for each iteration of the vector loop, the execution circuitry being responsive to execution of the check instruction determining an absence of said address hazard condition, to employ a default level of vectorisation when executing the sequence of instructions to implement the vector loop, and being responsive to execution of the check instruction determining a presence of said address hazard condition, to employ a reduced level of vectorisation when executing the sequence of instructions to implement the vector loop; wherein at the start of each iteration of the vector loop, the execution circuitry is arranged to revert to employing the default level of vectorisation; wherein the execution circuitry is responsive to execution of the check instruction determining the absence of said address hazard condition, to employ said default level of vectorisation by executing a first plurality of instructions within said sequence of instructions to implement the vector loop; and the execution circuitry is responsive to execution of the check instruction determining the presence of said address hazard condition, to employ said reduced level of vectorisation by iteratively executing a second plurality of instructions within said sequence of instructions to implement the vector loop; and wherein the execution circuitry is responsive to execution of said check instruction to generate result data indicating whether said address hazard condition exists, for reference by a subsequent instruction in said sequence; and wherein said result data comprises one or more flags, and said subsequent instruction is a branch instruction which, when executed by the execution circuitry, references the one or more flags in order to determine whether to execute said first plurality of instructions or whether to iteratively execute said second plurality of instructions.