Charge transfer device - having a charge transfer channel in a semiconductor substrate - having a doped conduction layer - for movably accepting the charge carriers, - having a sequence of at least two electrically isolated gates - which adjacently succeed one another - for transferring the charge carriers in the conduction layer - in a flow direction, - wherein the charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer, and - having a clock generator - having a clock frequency of more than 100 MHz, preferably of more than 150 MHz, more than 200 MHz or more than 250 MHz and particularly preferably up to 300 MHz or 400 MHz, - which applies changes in potential at the clock frequency to the gates, - for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer to adjacent regions of the overlap between adjacent gates and the conduction layer, wherein - the charge transfer channel has an influx region - which, in the flow direction, is arranged at a lateral outer boundary of the charge transfer channel and - which at least partly extends over the regions of exactly two adjacent gates of the charge transfer channel - in order to supply charge carriers to the charge transfer channel from a region outside the charge transfer channel that adjoins the influx region, in particular from a second charge transfer channel, and - in order to reduce the spillback or the flow resistance or the loss of the charge carriers in the flow direction of the charge transfer channel or of the region supplying charge carriers to the charge transfer channel, preferably of a second charge transfer channel, wherein - the length of the influx region along the conduction channel - is less than the length of the region of the assigned two adjacent gates along the charge transfer channel and - corresponds to 45-75% or 55-65% or 60% of the length of the region of the assigned two adjacent gates along the charge transfer channel, wherein - the influx region - with its length along the conduction transfer channel - adjoins in an offset manner the region of the assigned gate situated counter to the flow direction over a greater length than the region of the assigned gate situated in the flow direction, wherein the gates are arranged with spacings in an electrically isolated manner, and - preferably adjoins the region of the assigned gate situated counter to the flow direction to an extent of more than 50%, more than 60%, between 60% and 75%, or 2/3. - having a charge transfer channel in a semiconductor substrate - having a doped conduction layer - for movably accepting the charge carriers, - having a sequence of at least two electrically isolated gates - which adjacently succeed one another - for transferring the charge carriers in the conduction layer - in a flow direction, - wherein the charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer, and - having a clock generator - having a clock frequency of more than 100 MHz, preferably of more than 150 MHz, more than 200 MHz or more than 250 MHz and particularly preferably up to 300 MHz or 400 MHz, - which applies changes in potential at the clock frequency to the gates, - for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer to adjacent regions of the overlap between adjacent gates and the conduction layer, - the charge transfer channel has an influx region - which, in the flow direction, is arranged at a lateral outer boundary of the charge transfer channel and - which at least partly extends over the regions of exactly two adjacent gates of the charge transfer channel - in order to supply charge carriers to the charge transfer channel from a region outside the charge transfer channel that adjoins the influx region, in particular from a second charge transfer channel, and - in order to reduce the spillback or the flow resistance or the loss of the charge carriers in the flow direction of the charge transfer channel or of the region supplying charge carriers to the charge transfer channel, preferably of a second charge transfer channel, - the length of the influx region along the conduction channel - is less than the length of the region of the assigned two adjacent gates along the charge transfer channel and - corresponds to 45-75% or 55-65% or 60% of the length of the region of the assigned two adjacent gates along the charge transfer channel, wherein - the influx region - with its length along the conduction transfer channel - adjoins in an offset manner the region of the assigned gate situated counter to the flow direction over a greater length than the region of the assigned gate situated in the flow direction, wherein the gates are arranged with spacings in an electrically isolated manner, and - preferably adjoins the region of the assigned gate situated counter to the flow direction to an extent of more than 50%, more than 60%, between 60% and 75%, or 2/3.