A method, comprising: relaying a first plurality of commands for a particular logical unit from a switch coupled to non-volatile memory control circuitry, wherein the first plurality of commands are relayed with a channel request queue 'CRQ' of the non-volatile memory control circuitry that is coupled to a respective logical unit request queue 'LRQ' of each of a plurality of channel control circuits, and wherein the first plurality of commands are relayed via a particular logical unit request queue 'LRQ' in a particular channel control circuit to one of a plurality of logical unit command queues 'LCQs' in the channel control circuit associated with the particular logical unit in an order of reception of the first plurality of commands; relaying a first one of a second plurality of commands for different logical units from the switch with the CRQ via the particular LRQ to a first LCQ of the plurality of LCQs associated with the different logical units before relaying a second one of the second plurality of commands to a second LCQ of the plurality of LCQs in response to the status of the different logical unit associated with the second LCQ being busy, wherein the first one of the second plurality of commands is received later in time than the second one of the second plurality of commands; relaying the second one of the second plurality of commands to the second LCQ in response to the status of the associated different logical unit being ready; queuing, with the particular LRQ, a first command for a second particular logical unit in response to the LCQ associated with the second particular logical unit being full; receiving, with the CRQ, a second command and relaying the second command to the LRQ; and queuing, with the CRQ, a third command for the particular LRQ in response to the particular LRQ being full. relaying a first plurality of commands for a particular logical unit from a switch coupled to non-volatile memory control circuitry, wherein the first plurality of commands are relayed with a channel request queue 'CRQ' of the non-volatile memory control circuitry that is coupled to a respective logical unit request queue 'LRQ' of each of a plurality of channel control circuits, and wherein the first plurality of commands are relayed via a particular logical unit request queue 'LRQ' in a particular channel control circuit to one of a plurality of logical unit command queues 'LCQs' in the channel control circuit associated with the particular logical unit in an order of reception of the first plurality of commands; relaying a first one of a second plurality of commands for different logical units from the switch with the CRQ via the particular LRQ to a first LCQ of the plurality of LCQs associated with the different logical units before relaying a second one of the second plurality of commands to a second LCQ of the plurality of LCQs in response to the status of the different logical unit associated with the second LCQ being busy, wherein the first one of the second plurality of commands is received later in time than the second one of the second plurality of commands; relaying the second one of the second plurality of commands to the second LCQ in response to the status of the associated different logical unit being ready; queuing, with the particular LRQ, a first command for a second particular logical unit in response to the LCQ associated with the second particular logical unit being full; receiving, with the CRQ, a second command and relaying the second command to the LRQ; and queuing, with the CRQ, a third command for the particular LRQ in response to the particular LRQ being full.