A test method of detecting an error in a memory module to provide early warning of an increasing failure rate, the method comprising the sequential steps of: i) receiving a request from a processor executing an application for a read or write operation at a location of the memory module identified by an address; ii) outputting data from, or writing to, the location of the memory module; iii) generating by an error detection module a further read request for the location of the memory module identified by the address; iv) receiving at the error detection module an error correction code from the memory module for the location identified by the address; and vi) providing by the error detection module an alert output for the address if the error correction code indicates an error, characterised in that: during step i) a first multiplexer receives a first address input for an application to address the memory module and a second address input from the error detection module; during step iii) a second multiplexer receives a first read enable input for the application and a second read enable input from the error detection module; and during step iii) the error detection module provides a control signal to the first and second multiplexers (118, 119) to enable the address and further read request to be provided to the memory module if a new read or write request is not received by the memory module and disables the control signal if a new request for a read or write request is received by the memory module. i) receiving a request from a processor executing an application for a read or write operation at a location of the memory module identified by an address; ii) outputting data from, or writing to, the location of the memory module; iii) generating by an error detection module a further read request for the location of the memory module identified by the address; iv) receiving at the error detection module an error correction code from the memory module for the location identified by the address; and vi) providing by the error detection module an alert output for the address if the error correction code indicates an error, characterised in that: during step i) a first multiplexer receives a first address input for an application to address the memory module and a second address input from the error detection module; during step iii) a second multiplexer receives a first read enable input for the application and a second read enable input from the error detection module; and during step iii) the error detection module provides a control signal to the first and second multiplexers (118, 119) to enable the address and further read request to be provided to the memory module if a new read or write request is not received by the memory module and disables the control signal if a new request for a read or write request is received by the memory module. during step i) a first multiplexer receives a first address input for an application to address the memory module and a second address input from the error detection module; during step iii) a second multiplexer receives a first read enable input for the application and a second read enable input from the error detection module; and during step iii) the error detection module provides a control signal to the first and second multiplexers (118, 119) to enable the address and further read request to be provided to the memory module if a new read or write request is not received by the memory module and disables the control signal if a new request for a read or write request is received by the memory module.