A method for fabricating a Cu-In-Ga-Se film solar cell, comprising: a) fabricating a molybdenum back electrode on a substrate; b) fabricating a Cu-In-Ga-Se absorbing layer on the molybdenum back electrode by a multi-step sputtering, wherein the Cu-In-Ga-Se absorbing layer is fabricated by a sputter equipment, comprising: an input stage, an input chamber, a first to N th sputtering chambers, an unloading chamber and an unloading stage, the N sputtering chambers are connected in series, an internal volume of the input chamber is less than or equal to an internal volume of each sputtering chamber, an internal volume of the unloading chamber is less than or equal to the internal volume of each sputtering chamber, a vacuum of a first sputtering chamber is not destroyed when the substrate is transmitted from the input chamber into the first sputtering chamber, a vacuum of the last sputtering chamber is not destroyed when the substrate is transmitted from the last sputtering chamber to the unloading chamber, a CuIn x Ga 1-x Se 2 alloy target is mounted in each sputtering chamber, a sputtering with any power density ranging from 2W/cm 2 to 3W/cm 2 is performed with each CuIn x Ga 1-x Se 2 alloy target for 1-2 minutes, a working pressure of each sputtering chamber is 1×10 -4 Torr, and a temperature of the substrate in the sputtering chamber is maintained at any temperature between 200 °C and 450°C; c) performing an annealing for the Cu-In-Ga-Se absorbing layer in a rapid heating mode in the unloading chamber under a temperature of 400-600 °C for 55-90 seconds so that a Ga concentration in the Cu-In-Ga-Se absorbing layer has a gradient, the Ga concentration has a maximum on a surface of the Cu-In-Ga-Se absorbing layer contacting with the molybdenum back electrode and has a minimum on the other surface of the Cu-In-Ga-Se absorbing layer; d) fabricating an In 2 Se 3 or ZnS buffer layer with a thickness of 80-120nm on the Cu-In-Ga-Se absorbing layer; e) fabricating an intrinsic zinc oxide high impedance layer with a thickness of 0.1-0.5μm on the In 2 Se 3 or ZnS buffer layer; f) fabricating an indium tin oxide film low impedance layer with a thickness of 0.3-0.8μm on the intrinsic zinc oxide high impedance layer; g) fabricating an aluminum electrode on the indium tin oxide film low impedance layer. a) fabricating a molybdenum back electrode on a substrate; b) fabricating a Cu-In-Ga-Se absorbing layer on the molybdenum back electrode by a multi-step sputtering, wherein the Cu-In-Ga-Se absorbing layer is fabricated by a sputter equipment, comprising: an input stage, an input chamber, a first to N th sputtering chambers, an unloading chamber and an unloading stage, the N sputtering chambers are connected in series, an internal volume of the input chamber is less than or equal to an internal volume of each sputtering chamber, an internal volume of the unloading chamber is less than or equal to the internal volume of each sputtering chamber, a vacuum of a first sputtering chamber is not destroyed when the substrate is transmitted from the input chamber into the first sputtering chamber, a vacuum of the last sputtering chamber is not destroyed when the substrate is transmitted from the last sputtering chamber to the unloading chamber, a CuIn x Ga 1-x Se 2 alloy target is mounted in each sputtering chamber, a sputtering with any power density ranging from 2W/cm 2 to 3W/cm 2 is performed with each CuIn x Ga 1-x Se 2 alloy target for 1-2 minutes, a working pressure of each sputtering chamber is 1×10 -4 Torr, and a temperature of the substrate in the sputtering chamber is maintained at any temperature between 200 °C and 450°C; c) performing an annealing for the Cu-In-Ga-Se absorbing layer in a rapid heating mode in the unloading chamber under a temperature of 400-600 °C for 55-90 seconds so that a Ga concentration in the Cu-In-Ga-Se absorbing layer has a gradient, the Ga concentration has a maximum on a surface of the Cu-In-Ga-Se absorbing layer contacting with the molybdenum back electrode and has a minimum on the other surface of the Cu-In-Ga-Se absorbing layer; d) fabricating an In 2 Se 3 or ZnS buffer layer with a thickness of 80-120nm on the Cu-In-Ga-Se absorbing layer; e) fabricating an intrinsic zinc oxide high impedance layer with a thickness of 0.1-0.5μm on the In 2 Se 3 or ZnS buffer layer; f) fabricating an indium tin oxide film low impedance layer with a thickness of 0.3-0.8μm on the intrinsic zinc oxide high impedance layer; g) fabricating an aluminum electrode on the indium tin oxide film low impedance layer.