An integrated circuit (300, 400) comprising: at least one D flip-flop configured to receive a clock signal, receive an input data signal, and provide an output data signal; a clock line coupled to provide the clock signal to the at least one D flip-flop; and a return clock line, wherein the clock line and the return clock line are connected across a stacked driver to provide current for driving the clock signal, and wherein the at least one D flip-flop further comprises: a clock terminal coupled for receiving the clock signal via the clock line, a data input terminal coupled for receiving the input data signal, a data output terminal coupled to provide the output data signal, a first inductor coupled between the data input terminal and a first terminal, a second inductor coupled between the first terminal and a third terminal, a third inductor coupled between the third terminal and the data output terminal wherein the output data signal is provided through the third inductor via the data output terminal; a first Josephson junction, JJ, coupled between the first terminal and a second terminal wherein the JJ is coupled between the first inductor and the second inductor, and a superconducting quantum interference device (116 and 118), SQUID, coupled between the third terminal and a fourth terminal wherein the SQUID is coupled between the second inductor and the third inductor, wherein an inductive loop, formed between the first JJ and the SQUID (116 and 118), is configured to in response to receiving a first clock pulse via the clock line, store a fluxon when a state of the input data signal is high, and wherein the inductive loop is configured to in response to receiving a second clock pulse via the clock line to annihilate the stored fluxon when a state of the input data signal is low. at least one D flip-flop configured to receive a clock signal, receive an input data signal, and provide an output data signal; a clock line coupled to provide the clock signal to the at least one D flip-flop; and a return clock line, wherein the clock line and the return clock line are connected across a stacked driver to provide current for driving the clock signal, and wherein the at least one D flip-flop further comprises: a clock terminal coupled for receiving the clock signal via the clock line, a data input terminal coupled for receiving the input data signal, a data output terminal coupled to provide the output data signal, a first inductor coupled between the data input terminal and a first terminal, a second inductor coupled between the first terminal and a third terminal, a third inductor coupled between the third terminal and the data output terminal wherein the output data signal is provided through the third inductor via the data output terminal; a first Josephson junction, JJ, coupled between the first terminal and a second terminal wherein the JJ is coupled between the first inductor and the second inductor, and a superconducting quantum interference device (116 and 118), SQUID, coupled between the third terminal and a fourth terminal wherein the SQUID is coupled between the second inductor and the third inductor, wherein an inductive loop, formed between the first JJ and the SQUID (116 and 118), is configured to in response to receiving a first clock pulse via the clock line, store a fluxon when a state of the input data signal is high, and wherein the inductive loop is configured to in response to receiving a second clock pulse via the clock line to annihilate the stored fluxon when a state of the input data signal is low. a clock terminal coupled for receiving the clock signal via the clock line, a data input terminal coupled for receiving the input data signal, a data output terminal coupled to provide the output data signal, a first inductor coupled between the data input terminal and a first terminal, a second inductor coupled between the first terminal and a third terminal, a third inductor coupled between the third terminal and the data output terminal wherein the output data signal is provided through the third inductor via the data output terminal; a first Josephson junction, JJ, coupled between the first terminal and a second terminal wherein the JJ is coupled between the first inductor and the second inductor, and a superconducting quantum interference device (116 and 118), SQUID, coupled between the third terminal and a fourth terminal wherein the SQUID is coupled between the second inductor and the third inductor, wherein an inductive loop, formed between the first JJ and the SQUID (116 and 118), is configured to in response to receiving a first clock pulse via the clock line, store a fluxon when a state of the input data signal is high, and wherein the inductive loop is configured to in response to receiving a second clock pulse via the clock line to annihilate the stored fluxon when a state of the input data signal is low.