An antifuse physically unclonable function unit, comprising: a first sub-antifuse cell comprising a first select transistor, a first switching transistor and a first antifuse transistor, wherein a gate terminal of the first select transistor is connected with a word line, a first source/drain terminal of the first select transistor is connected with a first cell bit line, a second source/drain terminal of the first select transistor is connected with a first node (node a), a gate terminal of the first switching transistor is connected with a switch control line, a first source/drain terminal of the first switching transistor is connected with the first node (node a), a gate terminal of the first antifuse transistor is connected with a first antifuse control line, and a first source/drain terminal of the first antifuse transistor is connected with a second source/drain terminal of the first switching transistor; a second sub-antifuse cell comprising a second select transistor, a second switching transistor and a second antifuse transistor, wherein a gate terminal of the second select transistor is connected with the word line, a first source/drain terminal of the second select transistor is connected with a second cell bit line, a second source/drain terminal of the second select transistor is connected with a second node (node b), a gate terminal of the second switching transistor is connected with the switch control line, a first source/drain terminal of the second switching transistor is connected with the second node (node b), a gate terminal of the second antifuse transistor is connected with a second antifuse control line, and a first source/drain terminal of the second antifuse transistor is connected with a second source/drain terminal of the second switching transistor; a connection circuit connected with a second source/drain terminal of the first antifuse transistor and a second source/drain terminal of the second antifuse transistor, a first copying circuit connected with the first sub-antifuse cell, and comprising a third antifuse transistor; and a first reading circuit connected with the first copying circuit, wherein the first reading circuit generates a random code according to a state of the third antifuse transistor. a first sub-antifuse cell comprising a first select transistor, a first switching transistor and a first antifuse transistor, wherein a gate terminal of the first select transistor is connected with a word line, a first source/drain terminal of the first select transistor is connected with a first cell bit line, a second source/drain terminal of the first select transistor is connected with a first node (node a), a gate terminal of the first switching transistor is connected with a switch control line, a first source/drain terminal of the first switching transistor is connected with the first node (node a), a gate terminal of the first antifuse transistor is connected with a first antifuse control line, and a first source/drain terminal of the first antifuse transistor is connected with a second source/drain terminal of the first switching transistor; a second sub-antifuse cell comprising a second select transistor, a second switching transistor and a second antifuse transistor, wherein a gate terminal of the second select transistor is connected with the word line, a first source/drain terminal of the second select transistor is connected with a second cell bit line, a second source/drain terminal of the second select transistor is connected with a second node (node b), a gate terminal of the second switching transistor is connected with the switch control line, a first source/drain terminal of the second switching transistor is connected with the second node (node b), a gate terminal of the second antifuse transistor is connected with a second antifuse control line, and a first source/drain terminal of the second antifuse transistor is connected with a second source/drain terminal of the second switching transistor; a connection circuit connected with a second source/drain terminal of the first antifuse transistor and a second source/drain terminal of the second antifuse transistor, a first copying circuit connected with the first sub-antifuse cell, and comprising a third antifuse transistor; and a first reading circuit connected with the first copying circuit, wherein the first reading circuit generates a random code according to a state of the third antifuse transistor.