A data processor comprising: a memory storing a program in which a plurality of instructions are written; an instruction cache operating only when a branch instruction included in said program is executed, data of a greater capacity than a width of a bus of said memory being read from said memory and stored in said instruction cache in advance; a processing unit accessing both said memory and said instruction cache and executing, in a pipelined manner, instructions read from said memory or said instruction cache; the data processor being characterized in that it further comprises: a fetch process control unit generating, in response to a branch instruction executed by said processing unit, a stop signal for stopping a fetch process of reading an instruction from said memory, and outputting the stop signal to said memory, wherein said instruction cache includes a comparator comparing, when the branch instruction is executed by said processing unit, an address in said memory to be accessed with an address of an instruction stored in advance in said instruction cache and, when these addresses match each other, said comparator determines that said instruction cache stores an instruction of a branch target for said branch instruction, said fetch process control unit is a stop unit generating, when said comparator determines that said instruction cache stores the instruction of the branch target, a stop signal for stopping said fetch process and outputting the stop signal to said memory, during a period in which the instruction stored in said instruction cache is read, when said addresses match each other, said comparator counts a hit quantity representing the number of times instructions stored in said instruction cache can be read, and said stop unit includes a counter setting said hit quantity to an initial value and counting down said hit quantity to set a period in which access to said memory is stopped. a memory storing a program in which a plurality of instructions are written; an instruction cache operating only when a branch instruction included in said program is executed, data of a greater capacity than a width of a bus of said memory being read from said memory and stored in said instruction cache in advance; a processing unit accessing both said memory and said instruction cache and executing, in a pipelined manner, instructions read from said memory or said instruction cache; the data processor being characterized in that it further comprises: a fetch process control unit generating, in response to a branch instruction executed by said processing unit, a stop signal for stopping a fetch process of reading an instruction from said memory, and outputting the stop signal to said memory, wherein said instruction cache includes a comparator comparing, when the branch instruction is executed by said processing unit, an address in said memory to be accessed with an address of an instruction stored in advance in said instruction cache and, when these addresses match each other, said comparator determines that said instruction cache stores an instruction of a branch target for said branch instruction, said fetch process control unit is a stop unit generating, when said comparator determines that said instruction cache stores the instruction of the branch target, a stop signal for stopping said fetch process and outputting the stop signal to said memory, during a period in which the instruction stored in said instruction cache is read, when said addresses match each other, said comparator counts a hit quantity representing the number of times instructions stored in said instruction cache can be read, and said stop unit includes a counter setting said hit quantity to an initial value and counting down said hit quantity to set a period in which access to said memory is stopped. a fetch process control unit generating, in response to a branch instruction executed by said processing unit, a stop signal for stopping a fetch process of reading an instruction from said memory, and outputting the stop signal to said memory, wherein said instruction cache includes a comparator comparing, when the branch instruction is executed by said processing unit, an address in said memory to be accessed with an address of an instruction stored in advance in said instruction cache and, when these addresses match each other, said comparator determines that said instruction cache stores an instruction of a branch target for said branch instruction, said fetch process control unit is a stop unit generating, when said comparator determines that said instruction cache stores the instruction of the branch target, a stop signal for stopping said fetch process and outputting the stop signal to said memory, during a period in which the instruction stored in said instruction cache is read, when said addresses match each other, said comparator counts a hit quantity representing the number of times instructions stored in said instruction cache can be read, and said stop unit includes a counter setting said hit quantity to an initial value and counting down said hit quantity to set a period in which access to said memory is stopped.