A method, comprising: receiving a reference clock signal by a first integrated circuit chip and a second integrated circuit chip; generating a first clock signal by the first integrated circuit chip using the reference clock signal; generating a second clock signal by the second integrated circuit chip using the reference clock signal; generating a first synchronization signal (SYNC) by the first integrated circuit chip using the reference clock signal; generating a second synchronization signal by the second integrated circuit chip using the reference clock signal, wherein the first and the second synchronization signals are phase-aligned to the reference clock signal; distributing a first primary clock signal to a first plurality of digital circuits included in the first integrated circuit chip, wherein the first primary clock signal is edge-aligned to the first synchronization signal; distributing a second primary clock signal to a second plurality of digital circuits included in the second integrated circuit, wherein the second primary clock signal is edge-aligned to the second synchronization signal; dividing a frequency of the first primary clock signal using the first synchronization signal to generate a first divided-frequency clock signal; dividing a frequency of the second primary clock signal using the second synchronization signal to generate a second divided-frequency clock signal, wherein a frequency of the second divided-frequency clock signal is the same as a frequency of the first divided-frequency clock signal; transmitting data by the first integrated circuit chip using the first divided-frequency clock signal; and receiving the data by the second integrated circuit chip using the second divided-frequency clock signal. receiving a reference clock signal by a first integrated circuit chip and a second integrated circuit chip; generating a first clock signal by the first integrated circuit chip using the reference clock signal; generating a second clock signal by the second integrated circuit chip using the reference clock signal; generating a first synchronization signal (SYNC) by the first integrated circuit chip using the reference clock signal; generating a second synchronization signal by the second integrated circuit chip using the reference clock signal, wherein the first and the second synchronization signals are phase-aligned to the reference clock signal; distributing a first primary clock signal to a first plurality of digital circuits included in the first integrated circuit chip, wherein the first primary clock signal is edge-aligned to the first synchronization signal; distributing a second primary clock signal to a second plurality of digital circuits included in the second integrated circuit, wherein the second primary clock signal is edge-aligned to the second synchronization signal; dividing a frequency of the first primary clock signal using the first synchronization signal to generate a first divided-frequency clock signal; dividing a frequency of the second primary clock signal using the second synchronization signal to generate a second divided-frequency clock signal, wherein a frequency of the second divided-frequency clock signal is the same as a frequency of the first divided-frequency clock signal; transmitting data by the first integrated circuit chip using the first divided-frequency clock signal; and receiving the data by the second integrated circuit chip using the second divided-frequency clock signal.