A display device comprising: a barrier layer disposed on a substrate; a transistor disposed on the barrier layer; a first impact buffer layer configured to prevent damage from an external impact and disposed on the barrier layer; a buffer layer disposed between the first impact buffer layer and the transistor, wherein the buffer layer is patterned to partially cover the first impact buffer layer; wherein the transistor comprises: a semiconductor layer disposed on the buffer layer, wherein the semiconductor layer overlaps a portion of the buffer layer; a gate electrode disposed on the semiconductor layer; a source electrode electrically connected to the semiconductor layer; and a drain electrode electrically connected to the semiconductor layer; wherein the display device further comprises: a first insulation layer disposed between the semiconductor layer and the gate electrode, wherein the first insulation layer covers the semiconductor layer and the buffer layer; a second insulation layer disposed between the gate electrode and the source and drain electrodes, wherein the second insulation layer covers the first insulation layer and the gate electrode; and a third insulation layer disposed between the second insulation layer and the source and drain electrodes, wherein the third insulation layer covers the second insulation layer and the first impact buffer layer, wherein the first impact buffer layer comprises nanostructures and pores, and wherein the third insulation layer directly contacts the first impact buffer layer. a barrier layer disposed on a substrate; a transistor disposed on the barrier layer; a first impact buffer layer configured to prevent damage from an external impact and disposed on the barrier layer; a buffer layer disposed between the first impact buffer layer and the transistor, wherein the buffer layer is patterned to partially cover the first impact buffer layer; wherein the transistor comprises: a semiconductor layer disposed on the buffer layer, wherein the semiconductor layer overlaps a portion of the buffer layer; a gate electrode disposed on the semiconductor layer; a source electrode electrically connected to the semiconductor layer; and a drain electrode electrically connected to the semiconductor layer; a semiconductor layer disposed on the buffer layer, wherein the semiconductor layer overlaps a portion of the buffer layer; a gate electrode disposed on the semiconductor layer; a source electrode electrically connected to the semiconductor layer; and a drain electrode electrically connected to the semiconductor layer; wherein the display device further comprises: a first insulation layer disposed between the semiconductor layer and the gate electrode, wherein the first insulation layer covers the semiconductor layer and the buffer layer; a second insulation layer disposed between the gate electrode and the source and drain electrodes, wherein the second insulation layer covers the first insulation layer and the gate electrode; and a third insulation layer disposed between the second insulation layer and the source and drain electrodes, wherein the third insulation layer covers the second insulation layer and the first impact buffer layer, a first insulation layer disposed between the semiconductor layer and the gate electrode, wherein the first insulation layer covers the semiconductor layer and the buffer layer; a second insulation layer disposed between the gate electrode and the source and drain electrodes, wherein the second insulation layer covers the first insulation layer and the gate electrode; and a third insulation layer disposed between the second insulation layer and the source and drain electrodes, wherein the third insulation layer covers the second insulation layer and the first impact buffer layer, wherein the first impact buffer layer comprises nanostructures and pores, and wherein the third insulation layer directly contacts the first impact buffer layer.