A circuit, comprising: a first amplifier (151_1) configured to operate based on a first power supply voltage (VDDA) and to generate a first output signal (OTA1_OUT) by comparing a ramp signal (RAMP) and a reset signal of a pixel signal output from a pixel array during a first operation period and comparing the ramp signal (RAMP) and an image signal of the pixel signal output from the pixel array during a second operation period; a second amplifier (151_2) configured to operate based on the first power supply voltage (VDDA) and to generate a second output signal (OTA2_OUT) based on the first output signal (OTA1_OUT); and a counter configured to operate based on a second power supply voltage (VDDD), and in response to a counter clock signal (CNT_CLK) and the second output signal (OTA2_OUT), to output a counting result as a digital signal, wherein a first level of the first power supply voltage (VDDA) is greater than a second level of the second power supply voltage (VDDD), wherein the second amplifier (151_2) is further configured to adjust a voltage level of the second output signal (OTA2_OUT) from a low level to a third level, and wherein the third level is less than or equal to the second level of the second power supply voltage (VDDD), wherein the second amplifier (151_2) includes: a first transistor configured to provide a voltage equal to or smaller than the second power supply voltage (VDDD) to a first output node, from which the second output signal (OTA2_OUT) is output, in response to the first output signal (OTA1_OUT); a clipping circuit coupled between a power supply voltage terminal and the first transistor, and configured to adjust the voltage level of the second output signal (OTA2_OUT) by causing a voltage drop between the power supply voltage terminal and the first transistor; and a current source coupled with the first transistor through the first output node, and configured to generate a power current. a first amplifier (151_1) configured to operate based on a first power supply voltage (VDDA) and to generate a first output signal (OTA1_OUT) by comparing a ramp signal (RAMP) and a reset signal of a pixel signal output from a pixel array during a first operation period and comparing the ramp signal (RAMP) and an image signal of the pixel signal output from the pixel array during a second operation period; a second amplifier (151_2) configured to operate based on the first power supply voltage (VDDA) and to generate a second output signal (OTA2_OUT) based on the first output signal (OTA1_OUT); and a counter configured to operate based on a second power supply voltage (VDDD), and in response to a counter clock signal (CNT_CLK) and the second output signal (OTA2_OUT), to output a counting result as a digital signal, wherein a first level of the first power supply voltage (VDDA) is greater than a second level of the second power supply voltage (VDDD), wherein the second amplifier (151_2) is further configured to adjust a voltage level of the second output signal (OTA2_OUT) from a low level to a third level, and wherein the third level is less than or equal to the second level of the second power supply voltage (VDDD), wherein the second amplifier (151_2) includes: a first transistor configured to provide a voltage equal to or smaller than the second power supply voltage (VDDD) to a first output node, from which the second output signal (OTA2_OUT) is output, in response to the first output signal (OTA1_OUT); a clipping circuit coupled between a power supply voltage terminal and the first transistor, and configured to adjust the voltage level of the second output signal (OTA2_OUT) by causing a voltage drop between the power supply voltage terminal and the first transistor; and a current source coupled with the first transistor through the first output node, and configured to generate a power current. a first transistor configured to provide a voltage equal to or smaller than the second power supply voltage (VDDD) to a first output node, from which the second output signal (OTA2_OUT) is output, in response to the first output signal (OTA1_OUT); a clipping circuit coupled between a power supply voltage terminal and the first transistor, and configured to adjust the voltage level of the second output signal (OTA2_OUT) by causing a voltage drop between the power supply voltage terminal and the first transistor; and a current source coupled with the first transistor through the first output node, and configured to generate a power current.