A pixel circuit, disposed within an image sensing system, wherein the pixel circuit is coupled to a first collection node and a second collection node, characterized in that, the pixel circuit comprises: a first capacitor (C_A), comprising a first terminal (N A) and a second terminal (D A); a second capacitor (C_B), comprising a first terminal (N B) and a second terminal (D B); a first shutter switch (MSH_A1), coupled between the second terminal (D A) of the first capacitor (C_A) and the first collection node (FD_A); a second shutter switch (MSH_B1), coupled between the second terminal (D B) of the second capacitor (C_B) and the second collection node (FD_B); a third shutter switch (MSH_A2), coupled between the second terminal (D B) of the second capacitor (C_B) and the first collection node (FD_A); a fourth shutter switch (MSH_B2), coupled between the second terminal (D A) of the first capacitor (C_A) and the second collection node (FD_B); and a common mode reset module, coupled to the first capacitor and the second capacitor; wherein the image sensing system comprises a light emitting module and a clock generating module, the clock generating module generates a modulation signal to the light emitting module to emit an incident light; wherein the pixel circuit is coupled to a pixel light sensing region, a first polysilicon gate (Poly_A) and a second polysilicon gate (Poly_B) are disposed on the pixel light sensing region, the first polysilicon gate (Poly_A) receives a first clock signal (CLK_A) and the second polysilicon gate (Poly_B) receives a second clock signal (CLK_B); wherein the first clock signal (CLK_A) and the modulation signal are in-phase during a first time (T 1); wherein the second clock signal (CLK_B) and the modulation signal are in-phase during a second time (T 2); wherein during the first time (T 1), the first shutter switch (MSH_A1) and the second shutter switch (MSH_B1) are conducted, the third shutter switch (MSH_A2) and the fourth shutter switch (MSH_B2) are cutoff; wherein during the second time (T 2), the first shutter switch (MSH_A1) and the second shutter (MSH_B1) switch are cutoff, the third shutter (MSH_A2) switch and the fourth shutter (MSH_B2) switch are conducted; wherein the first time (T 1) and the second time (T 2) have the same time length. a first capacitor (C_A), comprising a first terminal (N A) and a second terminal (D A); a second capacitor (C_B), comprising a first terminal (N B) and a second terminal (D B); a first shutter switch (MSH_A1), coupled between the second terminal (D A) of the first capacitor (C_A) and the first collection node (FD_A); a second shutter switch (MSH_B1), coupled between the second terminal (D B) of the second capacitor (C_B) and the second collection node (FD_B); a third shutter switch (MSH_A2), coupled between the second terminal (D B) of the second capacitor (C_B) and the first collection node (FD_A); a fourth shutter switch (MSH_B2), coupled between the second terminal (D A) of the first capacitor (C_A) and the second collection node (FD_B); and a common mode reset module, coupled to the first capacitor and the second capacitor; wherein the image sensing system comprises a light emitting module and a clock generating module, the clock generating module generates a modulation signal to the light emitting module to emit an incident light; wherein the pixel circuit is coupled to a pixel light sensing region, a first polysilicon gate (Poly_A) and a second polysilicon gate (Poly_B) are disposed on the pixel light sensing region, the first polysilicon gate (Poly_A) receives a first clock signal (CLK_A) and the second polysilicon gate (Poly_B) receives a second clock signal (CLK_B); wherein the first clock signal (CLK_A) and the modulation signal are in-phase during a first time (T 1); wherein the second clock signal (CLK_B) and the modulation signal are in-phase during a second time (T 2); wherein during the first time (T 1), the first shutter switch (MSH_A1) and the second shutter switch (MSH_B1) are conducted, the third shutter switch (MSH_A2) and the fourth shutter switch (MSH_B2) are cutoff; wherein during the second time (T 2), the first shutter switch (MSH_A1) and the second shutter (MSH_B1) switch are cutoff, the third shutter (MSH_A2) switch and the fourth shutter (MSH_B2) switch are conducted; wherein the first time (T 1) and the second time (T 2) have the same time length.