A method for forming a multi-level interconnect structure for a semiconductor device, the method comprising: forming a first interconnection level including a set of conductive lines (111, 112, 113, 114) arranged in a first common horizontal plane of the first interconnection level and extending parallel to a first direction, forming a second interconnection level, wherein forming the second interconnection level comprises: forming, on the first interconnection level, a first sub-level of the second interconnection level, the first sub-level including a set of conductive lines (211, 212) arranged in a first common horizontal plane of the second interconnection level and extending parallel to a second direction transverse to the first direction, covering the first sub-level with a dielectric layer, forming a via hole extending through said dielectric layer and the first sub-level to a line of said set of lines of the first interconnection level, filling the via hole with a conductive via material to form a via, covering said dielectric layer with an additional dielectric layer, forming, in said additional dielectric layer, a set of trenches for accommodating a set of lines of the second sub-level, wherein said set of trenches are formed such that a top portion of the via protrudes from a bottom of a trench of said set of trenches, and filling said set of trenches with a conductive line material to form said set of lines of the second sub-level, wherein said set of conductive lines (221, 222) of the second sub-level are arranged in a second common horizontal plane of the second interconnection level, extend parallel to the second direction and are horizontally displaced from the set of lines (211, 212) of the first sub-level, and wherein the via extends past said set of lines (211, 212) of the first sub-level in a space between a pair of adjacent lines (211, 212) of said set of lines (211, 212) of the first sub-level. forming a first interconnection level including a set of conductive lines (111, 112, 113, 114) arranged in a first common horizontal plane of the first interconnection level and extending parallel to a first direction, forming a second interconnection level, wherein forming the second interconnection level comprises: forming, on the first interconnection level, a first sub-level of the second interconnection level, the first sub-level including a set of conductive lines (211, 212) arranged in a first common horizontal plane of the second interconnection level and extending parallel to a second direction transverse to the first direction, covering the first sub-level with a dielectric layer, forming a via hole extending through said dielectric layer and the first sub-level to a line of said set of lines of the first interconnection level, filling the via hole with a conductive via material to form a via, covering said dielectric layer with an additional dielectric layer, forming, in said additional dielectric layer, a set of trenches for accommodating a set of lines of the second sub-level, wherein said set of trenches are formed such that a top portion of the via protrudes from a bottom of a trench of said set of trenches, and filling said set of trenches with a conductive line material to form said set of lines of the second sub-level, wherein said set of conductive lines (221, 222) of the second sub-level are arranged in a second common horizontal plane of the second interconnection level, extend parallel to the second direction and are horizontally displaced from the set of lines (211, 212) of the first sub-level, and forming, on the first interconnection level, a first sub-level of the second interconnection level, the first sub-level including a set of conductive lines (211, 212) arranged in a first common horizontal plane of the second interconnection level and extending parallel to a second direction transverse to the first direction, covering the first sub-level with a dielectric layer, forming a via hole extending through said dielectric layer and the first sub-level to a line of said set of lines of the first interconnection level, filling the via hole with a conductive via material to form a via, covering said dielectric layer with an additional dielectric layer, forming, in said additional dielectric layer, a set of trenches for accommodating a set of lines of the second sub-level, wherein said set of trenches are formed such that a top portion of the via protrudes from a bottom of a trench of said set of trenches, and filling said set of trenches with a conductive line material to form said set of lines of the second sub-level, wherein said set of conductive lines (221, 222) of the second sub-level are arranged in a second common horizontal plane of the second interconnection level, extend parallel to the second direction and are horizontally displaced from the set of lines (211, 212) of the first sub-level, and wherein the via extends past said set of lines (211, 212) of the first sub-level in a space between a pair of adjacent lines (211, 212) of said set of lines (211, 212) of the first sub-level.