A processor comprising: a cache to store data; and a plurality of cores coupled to the cache, at least one core of the plurality of cores comprising: execution circuitry adapted to execute one or more instructions to perform a matrix multiplication with a first source matrix and a second source matrix to generate a result matrix, the execution circuitry adapted to: convert a first plurality of data elements of the first source matrix and a second plurality of data elements of the second source matrix from a single-precision floating point data format to a reduced precision floating point format having fewer mantissa bits than the single-precision floating point format and a same number of exponent bits as the single-precision floating point format; and subsequently perform a plurality of parallel fused multiply-add operations to multiply the first plurality of data elements in the reduced precision floating point format by corresponding data elements of the second plurality of data elements in the reduced precision floating point format to generate a plurality of products, and to add the plurality of products to accumulated values to generate single-precision floating point data elements of the result matrix. a cache to store data; and a plurality of cores coupled to the cache, at least one core of the plurality of cores comprising: execution circuitry adapted to execute one or more instructions to perform a matrix multiplication with a first source matrix and a second source matrix to generate a result matrix, the execution circuitry adapted to: convert a first plurality of data elements of the first source matrix and a second plurality of data elements of the second source matrix from a single-precision floating point data format to a reduced precision floating point format having fewer mantissa bits than the single-precision floating point format and a same number of exponent bits as the single-precision floating point format; and subsequently perform a plurality of parallel fused multiply-add operations to multiply the first plurality of data elements in the reduced precision floating point format by corresponding data elements of the second plurality of data elements in the reduced precision floating point format to generate a plurality of products, and to add the plurality of products to accumulated values to generate single-precision floating point data elements of the result matrix. convert a first plurality of data elements of the first source matrix and a second plurality of data elements of the second source matrix from a single-precision floating point data format to a reduced precision floating point format having fewer mantissa bits than the single-precision floating point format and a same number of exponent bits as the single-precision floating point format; and subsequently perform a plurality of parallel fused multiply-add operations to multiply the first plurality of data elements in the reduced precision floating point format by corresponding data elements of the second plurality of data elements in the reduced precision floating point format to generate a plurality of products, and to add the plurality of products to accumulated values to generate single-precision floating point data elements of the result matrix.