A processor, comprising: a plurality of processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture, wherein each of said plurality of processor cores includes a respective local microcode unit configured to store microcode entries; and a remote microcode unit accessible by each of said processor cores and including a remote microcode store configured to store microcode entries; wherein any given one of said processor cores is further configured to: generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by said given processor core; characterized in that said any given one of said processor cores is further configured to determine whether said particular microcode entry is stored within said respective local microcode unit of said given processor core; and in response to determining that said particular microcode entry is not stored within said respective local microcode unit, convey a request for said particular microcode entry to said remote microcode unit, and characterized in that a local set of microcode routines corresponding to microcode entries stored within said local microcode units are selected for storage within said local microcode units dependent upon determining that each of the local set of microcode routines satisfies a performance sensitivity threshold requirement, while at least some microcode routines corresponding to microcode entries stored within said remote microcode unit are selected for storage within said remote microcode unit dependent upon determining that each of said at least some microcode routines does not satisfy said performance sensitivity threshold requirement; wherein determining that a given microcode routine does or does not satisfy said performance sensitivity threshold requirement occurs prior to manufacture of the processor. a plurality of processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture, wherein each of said plurality of processor cores includes a respective local microcode unit configured to store microcode entries; and a remote microcode unit accessible by each of said processor cores and including a remote microcode store configured to store microcode entries; wherein any given one of said processor cores is further configured to: generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by said given processor core; characterized in that said any given one of said processor cores is further configured to determine whether said particular microcode entry is stored within said respective local microcode unit of said given processor core; and in response to determining that said particular microcode entry is not stored within said respective local microcode unit, convey a request for said particular microcode entry to said remote microcode unit, and characterized in that a local set of microcode routines corresponding to microcode entries stored within said local microcode units are selected for storage within said local microcode units dependent upon determining that each of the local set of microcode routines satisfies a performance sensitivity threshold requirement, while at least some microcode routines corresponding to microcode entries stored within said remote microcode unit are selected for storage within said remote microcode unit dependent upon determining that each of said at least some microcode routines does not satisfy said performance sensitivity threshold requirement; wherein determining that a given microcode routine does or does not satisfy said performance sensitivity threshold requirement occurs prior to manufacture of the processor.