A stacked half-bridge package comprising: a control transistor (Q 1) having a control drain (D 1) for connection to a high voltage input (V H), a control source (S 1) coupled to a common conductive clip, and a control gate (G 1) for being driven by a driver IC, wherein said control transistor (Q 1) has top and bottom surfaces, said control drain (D 1) being on said bottom surface and said control source (S 1) and said control gate (G 1) being on said top surface; a sync transistor (Q 2) having a sync drain (D 2) for connection to said common conductive clip, a sync source (S 2) coupled to a low voltage input (V L), and a sync gate (G 2) for being driven by said driver IC, wherein said sync transistor (Q 2) has top and bottom surfaces, said sync drain (D 2) being on said bottom surface and said sync source (S 2) and said sync gate (G 2) being on said top surface.; said control and sync transistors being stacked on opposite sides of said common conductive clip, said common conductive clip electrically and mechanically coupling said control source with said sync drain, wherein said common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe, wherein a conductive web of said common conductive clip provides said electrical and mechanical coupling of said control source (S 1) with said sync drain (D 2), said conductive leg of said common conductive clip is of a thickness greater than that of said control transistor (Q 1), wherein a control drain leadframe provides mechanical and electrical connection for said control drain (D 1), wherein respective bottom surfaces of a sync source leadframe, said control drain leadframe, and said output terminal leadframe are flush with one another and respective top surfaces of said sync source leadframe, said control drain leadframe, and said output terminal leadframe are flush with one another, a conductive source clip coupling said sync source (S 2) to said low voltage input, characterizsed in that said conductive source clip includes a source clip web and a source clip leg perpendicular to said source clip web; said source clip web completely overlies said common conductive clip, and said sync transistor (Q 2) is situated over said conductive leg of said common conductive clip and over said output terminal leadframe. a control transistor (Q 1) having a control drain (D 1) for connection to a high voltage input (V H), a control source (S 1) coupled to a common conductive clip, and a control gate (G 1) for being driven by a driver IC, wherein said control transistor (Q 1) has top and bottom surfaces, said control drain (D 1) being on said bottom surface and said control source (S 1) and said control gate (G 1) being on said top surface; a sync transistor (Q 2) having a sync drain (D 2) for connection to said common conductive clip, a sync source (S 2) coupled to a low voltage input (V L), and a sync gate (G 2) for being driven by said driver IC, wherein said sync transistor (Q 2) has top and bottom surfaces, said sync drain (D 2) being on said bottom surface and said sync source (S 2) and said sync gate (G 2) being on said top surface.; said control and sync transistors being stacked on opposite sides of said common conductive clip, said common conductive clip electrically and mechanically coupling said control source with said sync drain, wherein said common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe, wherein a conductive web of said common conductive clip provides said electrical and mechanical coupling of said control source (S 1) with said sync drain (D 2), said conductive leg of said common conductive clip is of a thickness greater than that of said control transistor (Q 1), wherein a control drain leadframe provides mechanical and electrical connection for said control drain (D 1), wherein respective bottom surfaces of a sync source leadframe, said control drain leadframe, and said output terminal leadframe are flush with one another and respective top surfaces of said sync source leadframe, said control drain leadframe, and said output terminal leadframe are flush with one another, a conductive source clip coupling said sync source (S 2) to said low voltage input, characterizsed in that said conductive source clip includes a source clip web and a source clip leg perpendicular to said source clip web; said source clip web completely overlies said common conductive clip, and said sync transistor (Q 2) is situated over said conductive leg of said common conductive clip and over said output terminal leadframe.