A method of clock synchronous data communication between processor cores of a multi-core processor, the multi-core processor comprising a plurality of processor cores among which a clock synchronous data communication is performed using a frequency conversion device which includes a state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit, the method comprising the following steps: Step A in which a first processor core sends data to a second processor core, the data including a single-bit data valid bit and a multi-bit data content; Step B in which the frequency conversion device of the second processor core receives the data valid bit sent by the first processor core, the output of the multiple selector and the data valid bit signal inputs into the multi-input OR gate and changes the output state of the multi-input OR gate into a valid state, and sends the valid state as a new gating signal to the clock-gating circuit unit thereof, the output clock changing from a frequency conversion clock to a common original clock of the plurality of processor cores; and Step C in which the second processor core uses the common original clock of the plurality of processor cores to sample the data content sent from the first processor core, wherein the following step is further performed before the Step A: rewriting the values of the frequency conversion coefficient registers in the frequency conversion devices of the first and second processor cores so that the first and second processor cores each operate at a set clock frequency, wherein the clock frequency is a common original clock frequency of the processor or a clock frequency after frequency conversion, and wherein the following step is further performed after the Step C: after the second processor core receives the data sent from the first processor core completely, changing the data transmission valid bit of the first processor core into an invalid bit, and controlling the clock-gating circuit in the frequency conversion device of the second processor core by the frequency conversion coefficient register once again. Step A in which a first processor core sends data to a second processor core, the data including a single-bit data valid bit and a multi-bit data content; Step B in which the frequency conversion device of the second processor core receives the data valid bit sent by the first processor core, the output of the multiple selector and the data valid bit signal inputs into the multi-input OR gate and changes the output state of the multi-input OR gate into a valid state, and sends the valid state as a new gating signal to the clock-gating circuit unit thereof, the output clock changing from a frequency conversion clock to a common original clock of the plurality of processor cores; and Step C in which the second processor core uses the common original clock of the plurality of processor cores to sample the data content sent from the first processor core, rewriting the values of the frequency conversion coefficient registers in the frequency conversion devices of the first and second processor cores so that the first and second processor cores each operate at a set clock frequency, after the second processor core receives the data sent from the first processor core completely, changing the data transmission valid bit of the first processor core into an invalid bit, and controlling the clock-gating circuit in the frequency conversion device of the second processor core by the frequency conversion coefficient register once again.