mhurhangee/ep-ind-claims huggingface dataset:
A multiport valve, comprising: a valve body comprising a body inlet coaxial to a first axis and a plurality of body outlets (22a, 22b, 22c) each oriented at an angle transverse to the first axis; a spherical flow control element disposed within a cavity of the valve body comprising a ball inlet having a ball inlet area radially arranged about the first axis, and a ball outlet radially arranged at the transverse angle to the first axis, the flow control element rotatable about the first axis to selectively align the ball outlet with each of the plurality of body outlets separately; a like plurality of outlet seat recesses, each outlet seat recess radially arranged about a respective one of the body outlets, each outlet seat recess receiving a respective outlet valve seat assembly in sealing engagement between the valve body and the flow control element; a like plurality of resilient members, each biasing a respective one of the outlet valve seat assemblies against the valve body; an inlet sleeve assembly radially arranged about the body inlet in sealing, biased engagement between the valve body and the flow control element; wherein the valve body comprises a main body sealingly engaged with an upper bonnet; wherein a lower portion of each outlet seat recess is formed into the main body, whereby a corresponding lower portion of each resilient member is biased against the main body; and wherein an upper portion of each outlet seat recess is formed into the bonnet, whereby a corresponding upper portion of each resilient member is biased against the bonnet. a valve body comprising a body inlet coaxial to a first axis and a plurality of body outlets (22a, 22b, 22c) each oriented at an angle transverse to the first axis; a spherical flow control element disposed within a cavity of the valve body comprising a ball inlet having a ball inlet area radially arranged about the first axis, and a ball outlet radially arranged at the transverse angle to the first axis, the flow control element rotatable about the first axis to selectively align the ball outlet with each of the plurality of body outlets separately; a like plurality of outlet seat recesses, each outlet seat recess radially arranged about a respective one of the body outlets, each outlet seat recess receiving a respective outlet valve seat assembly in sealing engagement between the valve body and the flow control element; a like plurality of resilient members, each biasing a respective one of the outlet valve seat assemblies against the valve body; an inlet sleeve assembly radially arranged about the body inlet in sealing, biased engagement between the valve body and the flow control element; wherein the valve body comprises a main body sealingly engaged with an upper bonnet; wherein a lower portion of each outlet seat recess is formed into the main body, whereby a corresponding lower portion of each resilient member is biased against the main body; and wherein an upper portion of each outlet seat recess is formed into the bonnet, whereby a corresponding upper portion of each resilient member is biased against the bonnet.
Polymer composition comprising a mixture of: a) Phenyl boronic acid modified hyaluronic acid polymer grafted on at least a hydroxyl with a group comprising phenylboronic acid, wherein said group is selected in the group consisting of phenylboronic acid, 3-aminophenylboronic acid, 4-aminophenylboronic acid, 4-(aminoethylcarbamoyl)-3-fluorophenylboronic acid and 4-[(2-aminoethyl) carbamoyl] phenylboronic acid, and b) Cis-diol modified hyaluronic acid polymer grafted on at least a hydroxyl with a group comprising a cis-diol, wherein said cis-diol is selected in the group consisting of: disaccharides, hexoses, uronic acid derivatives of hexoses, hexosamines, N -acetyl derivatives of hexosamines, glycerol, mannitol and sialic acid. a) Phenyl boronic acid modified hyaluronic acid polymer grafted on at least a hydroxyl with a group comprising phenylboronic acid, wherein said group is selected in the group consisting of phenylboronic acid, 3-aminophenylboronic acid, 4-aminophenylboronic acid, 4-(aminoethylcarbamoyl)-3-fluorophenylboronic acid and 4-[(2-aminoethyl) carbamoyl] phenylboronic acid, and b) Cis-diol modified hyaluronic acid polymer grafted on at least a hydroxyl with a group comprising a cis-diol, wherein said cis-diol is selected in the group consisting of: disaccharides, hexoses, uronic acid derivatives of hexoses, hexosamines, N -acetyl derivatives of hexosamines, glycerol, mannitol and sialic acid.
Optical position measuring device having a material measure and a scanning plate, the position of which relative to one another is determinable in three linearly independent spatial directions (X, Y, Z) by means of a plurality of interfering light beams, wherein two spatial directions (X, Y) lie parallel to the plane of the material measure and parallel to the plane of the scanning plate and the third spatial direction is perpendicular thereto with one component, - having a splitter grating (Ga), arranged on the scanning plate, for splitting light into a plurality of partial beams (+1, 0, -1) of different orders of diffraction, - having an optical grating (Gm), arranged on the material measure, for further splitting of the partial beams (+1, 0, -1) and for reunifying these further split partial beams (+1, 0, -1) after their back reflection from the scanning plate, - having a plurality of grating fields (A1-A4, B1-B4, X1-X4) on the side of the scanning plate facing the material measure, said grating fields serving as diffractive optical units for influencing the partial beams (+1, 0, -1) that are split further at the material measure, - having an output coupling grating (Gk), arranged on the scanning plate, for output coupling of light, reflected multiple times between the material measure and the scanning plate, as interfering partial beams, characterized in that - there is a difference in a step height (t1, t2, t3) of the plurality of grating fields (A1-A4, B1-B4, X1-X4) embodied as phase gratings. - having a splitter grating (Ga), arranged on the scanning plate, for splitting light into a plurality of partial beams (+1, 0, -1) of different orders of diffraction, - having an optical grating (Gm), arranged on the material measure, for further splitting of the partial beams (+1, 0, -1) and for reunifying these further split partial beams (+1, 0, -1) after their back reflection from the scanning plate, - having a plurality of grating fields (A1-A4, B1-B4, X1-X4) on the side of the scanning plate facing the material measure, said grating fields serving as diffractive optical units for influencing the partial beams (+1, 0, -1) that are split further at the material measure, - having an output coupling grating (Gk), arranged on the scanning plate, for output coupling of light, reflected multiple times between the material measure and the scanning plate, as interfering partial beams, - there is a difference in a step height (t1, t2, t3) of the plurality of grating fields (A1-A4, B1-B4, X1-X4) embodied as phase gratings.
A method of tuning an electric charge extraction circuit of a vibrational energy harvester having a mechanical resonator, the method comprising: - varying, during a first phase (PHASE 1), first and second parameters (ψ 1,ψ 2) of the electric charge extraction circuit (1402, 1802) based on detected harvested power (P HARVEST), each of the first and second parameters (ψ 1,ψ 2) influencing the amount of damping (ξ e) of the mechanical resonator and at least the first parameter (Ψ 1) influencing the resonance frequency (f res) of the mechanical resonator, wherein the first and second parameters (ψ 1,ψ 2) are varied during the first phase (PHASE 1) such that the amount of damping (ξ e) remains constant or varies by less than a first significant amount and the resonance frequency reaches a final level (f res '). - varying, during a first phase (PHASE 1), first and second parameters (ψ 1,ψ 2) of the electric charge extraction circuit (1402, 1802) based on detected harvested power (P HARVEST), each of the first and second parameters (ψ 1,ψ 2) influencing the amount of damping (ξ e) of the mechanical resonator and at least the first parameter (Ψ 1) influencing the resonance frequency (f res) of the mechanical resonator, wherein the first and second parameters (ψ 1,ψ 2) are varied during the first phase (PHASE 1) such that the amount of damping (ξ e) remains constant or varies by less than a first significant amount and the resonance frequency reaches a final level (f res ').
A compound of formula: where: X is a -(CHR 1) p group, where R 1 is hydrogen, or a C 1 -C 6 alkyl group, or a C 6 -C 10 aryl group, and p is 0 or 1; Y is selected from: a single bond; -(CH 2) n, with n being 1, 2, 3, 4, or 5; arylidene or heteroarylidene, connected with the rest of the molecule by means of (1,3) or (1,4) bonds; -C -N -CH 2 (Ar)-, and -Ar-C -N -CH 2 -(Ar)-; where -Ar- means arylidene; q is 0 or 1; Z is selected from OH, SH, and optionally substituted C 6 -C 10 aryl, or a pharmaceutically acceptable salt, or solvate thereof, for use in the treatment of polycystic diseases. X is a -(CHR 1) p group, where R 1 is hydrogen, or a C 1 -C 6 alkyl group, or a C 6 -C 10 aryl group, and p is 0 or 1; Y is selected from: a single bond; -(CH 2) n, with n being 1, 2, 3, 4, or 5; arylidene or heteroarylidene, connected with the rest of the molecule by means of (1,3) or (1,4) bonds; -C -N -CH 2 (Ar)-, and -Ar-C -N -CH 2 -(Ar)-; where -Ar- means arylidene; a single bond; -(CH 2) n, with n being 1, 2, 3, 4, or 5; arylidene or heteroarylidene, connected with the rest of the molecule by means of (1,3) or (1,4) bonds; -C -N -CH 2 (Ar)-, and -Ar-C -N -CH 2 -(Ar)-; where -Ar- means arylidene; q is 0 or 1; Z is selected from OH, SH, and optionally substituted C 6 -C 10 aryl,
A device joining substrate having a base substrate (2, 11) and a lead free solder layer formed on the base substrate (2, 11), wherein the solder layer consists of two layers of a solder which are different in its phase from one another, and the upper layer on a device joining face side is consisting of Au 5 Sn as a phase which has a relatively low melting temperature, the lower layer thereunder is consisting of AuSn as a phase which has a relatively high melting temperature, and said upper layer and said lower layer have lamellar forms.
A clock synchronization circuit to be used in a 2 n -QAM demodulator, where n is an integer of 4 or more, the clock synchronization circuit comprising: a voltage-controlled oscillator for producing a sampling clock signal in accordance with a control signal; an A/D converter for converting an analog base band signal, which has been converted into a base band by a quadrature demodulator, into a digital signal in synchronization with the sampling clock signal; a phase error detector for extracting, from the digital signal, a phase error corresponding to an optimum sampling phase of the analog base band signal and the sampling clock signal to produce a phase error signal corresponding to a value of the phase error; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing, based on the limited phase error signal, the control signal so that the phase of the sampling clock signal matches with the optimum phase, to thereby determine frequency characteristics of a loop. a voltage-controlled oscillator for producing a sampling clock signal in accordance with a control signal; an A/D converter for converting an analog base band signal, which has been converted into a base band by a quadrature demodulator, into a digital signal in synchronization with the sampling clock signal; a phase error detector for extracting, from the digital signal, a phase error corresponding to an optimum sampling phase of the analog base band signal and the sampling clock signal to produce a phase error signal corresponding to a value of the phase error; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing, based on the limited phase error signal, the control signal so that the phase of the sampling clock signal matches with the optimum phase, to thereby determine frequency characteristics of a loop.
A battery module (100; 200) comprising: a battery pack comprising positive and negative electrodes; a first main relay and a second main relay electrically coupled to the positive and negative electrodes of the battery pack; and a master battery management system (130; 230) electrically coupled to the first main relay and the second main relay and configured to control the first main relay and the second main relay to be driven, wherein the master battery management system (130; 230) is configured to control a turn-off order of the first main relay and the second main relay according to stress variables of the first main relay and the second main relay, characterized in that the master battery management system (130; 230) is configured to selectively and sequentially turn off the first main relay and the second main relay, wherein the main relay having a smaller stress variable is first turned off and the other main relay is then turned off. a battery pack comprising positive and negative electrodes; a first main relay and a second main relay electrically coupled to the positive and negative electrodes of the battery pack; and a master battery management system (130; 230) electrically coupled to the first main relay and the second main relay and configured to control the first main relay and the second main relay to be driven, wherein the master battery management system (130; 230) is configured to control a turn-off order of the first main relay and the second main relay according to stress variables of the first main relay and the second main relay, the master battery management system (130; 230) is configured to selectively and sequentially turn off the first main relay and the second main relay, wherein the main relay having a smaller stress variable is first turned off and the other main relay is then turned off.
A memory arrangement for a fluid ejection die, the fluid ejection die comprising a plurality of nozzles (104, 206, 256) to eject drops of fluid, the memory arrangement comprising: a memory bank (300, 400, 500) having a plurality of memory units (306, 402, 512) arranged in the form of a matrix (304; 502), the matrix having a plurality of rows and a plurality of columns; each memory unit (306, 402, 512) comprising a floating gate transistor (308, 404) capable of being accessed by applying a voltage for being read from and written to; and a single bank select transistor (302, 414, 506) common to the plurality of memory units (306, 402, 512), wherein the single bank select transistor (302, 414, 506) is connected to each of the memory units (306, 402, 512) through a row select transistor (312, 408, 520) and a column select transistor (310, 406, 516) connected to the corresponding memory unit (306, 402, 512), wherein the floating gate transistor (308, 404) of each memory unit (306, 402, 512) is connected to the column select transistor (310, 406, 516) corresponding to the memory unit (306, 406, 516) and the row select transistor (312, 408, 520) corresponding to a row having the memory unit (306, 406, 516)to facilitate accessing a memory unit of the plurality of memory units based on a single bank select signal (324, 510) provided to the single bank select transistor (302, 414, 506). a memory bank (300, 400, 500) having a plurality of memory units (306, 402, 512) arranged in the form of a matrix (304; 502), the matrix having a plurality of rows and a plurality of columns; each memory unit (306, 402, 512) comprising a floating gate transistor (308, 404) capable of being accessed by applying a voltage for being read from and written to; and a single bank select transistor (302, 414, 506) common to the plurality of memory units (306, 402, 512), wherein the single bank select transistor (302, 414, 506) is connected to each of the memory units (306, 402, 512) through a row select transistor (312, 408, 520) and a column select transistor (310, 406, 516) connected to the corresponding memory unit (306, 402, 512), wherein the floating gate transistor (308, 404) of each memory unit (306, 402, 512) is connected to the column select transistor (310, 406, 516) corresponding to the memory unit (306, 406, 516) and the row select transistor (312, 408, 520) corresponding to a row having the memory unit (306, 406, 516)to facilitate accessing a memory unit of the plurality of memory units based on a single bank select signal (324, 510) provided to the single bank select transistor (302, 414, 506).
Polypropylene composition comprising a blend of: (a) 60.0 to 95.0 wt%, preferably 75.0 to 95.0 wt%, of a propylene-ethylene random copolymer having: ethylene content in the range of from 1.5 to 6.0 wt%; MFR 2 (230°C, 2.16 kg, ISO1133) in a range of from 1.5 to 20.0 g/10 min; melting temperature Tm is in the range of from 135°C to 155°C; and (b) 5.0 to 40.0 wt%, preferably 5.0 to 25.0 wt%, of a component selected from a propylene-hexene random copolymer or a propylene-hexene-ethylene terpolymer, or a mixture thereof, having: hexene content in the range of from 3.0 to 5.5 wt%; optionally an ethylene content of from 0.1 to 2.0 wt%; MFR 2 (230°C, 2.16kg, ISO1133) in a range of from 1.5 to 20.0 g/10 min; melting temperature Tm in the range of from 125°C to 145°C, based on the total weight of the sum of the component and component, whereby the MFR 2 (230°C, 2.16kg, ISO1133) of the blend is in a range of from 1.5 to 20.0 g/10 min. (a) 60.0 to 95.0 wt%, preferably 75.0 to 95.0 wt%, of a propylene-ethylene random copolymer having: ethylene content in the range of from 1.5 to 6.0 wt%; MFR 2 (230°C, 2.16 kg, ISO1133) in a range of from 1.5 to 20.0 g/10 min; melting temperature Tm is in the range of from 135°C to 155°C; and ethylene content in the range of from 1.5 to 6.0 wt%; MFR 2 (230°C, 2.16 kg, ISO1133) in a range of from 1.5 to 20.0 g/10 min; melting temperature Tm is in the range of from 135°C to 155°C; and (b) 5.0 to 40.0 wt%, preferably 5.0 to 25.0 wt%, of a component selected from a propylene-hexene random copolymer or a propylene-hexene-ethylene terpolymer, or a mixture thereof, having: hexene content in the range of from 3.0 to 5.5 wt%; optionally an ethylene content of from 0.1 to 2.0 wt%; MFR 2 (230°C, 2.16kg, ISO1133) in a range of from 1.5 to 20.0 g/10 min; melting temperature Tm in the range of from 125°C to 145°C, based on the total weight of the sum of the component and component, whereby the MFR 2 (230°C, 2.16kg, ISO1133) of the blend is in a range of from 1.5 to 20.0 g/10 min. hexene content in the range of from 3.0 to 5.5 wt%; optionally an ethylene content of from 0.1 to 2.0 wt%; MFR 2 (230°C, 2.16kg, ISO1133) in a range of from 1.5 to 20.0 g/10 min; melting temperature Tm in the range of from 125°C to 145°C, based on the total weight of the sum of the component and component, whereby the MFR 2 (230°C, 2.16kg, ISO1133) of the blend is in a range of from 1.5 to 20.0 g/10 min.
A switching apparatus for connecting/disconnecting appliances or devices to a power grid, the apparatus coupled to the power grid via at least one input terminal, said apparatus comprising: a bidirectional semiconductor switch (M1, M2); a bias supply circuit coupled to the at least one input terminal, the bias supply circuit being for generating a floating auxiliary voltage from the power grid by use of at least one capacitor (C1, C2); and a switching control circuit powered by said floating auxiliary voltage characterized in that the switching apparatus comprises an isolation circuit; and in that the switching control circuit is configured to output a gate control voltage to turn on said bidirectional semiconductor switch (M1, M2) in response to an appearance of a supply voltage supplied via the bias supply circuit, said supply voltage being derived from said power grid and to at least one control signal (Ctrl) supplied to the switching control circuit via the isolation circuit; wherein said switching control circuit comprises a latch circuit, providing the gate control signal to the bidirectional semiconductor switch (M1, M2),and wherein said isolation circuit comprises a signal transformer or optical coupler for supplying said at least one control signal to a signal processing circuit, provided by the isolation circuit, for generating control commands to be supplied to said latch circuit. a bidirectional semiconductor switch (M1, M2); a bias supply circuit coupled to the at least one input terminal, the bias supply circuit being for generating a floating auxiliary voltage from the power grid by use of at least one capacitor (C1, C2); and a switching control circuit powered by said floating auxiliary voltage characterized in that the switching apparatus comprises an isolation circuit; and in that the switching control circuit is configured to output a gate control voltage to turn on said bidirectional semiconductor switch (M1, M2) in response to an appearance of a supply voltage supplied via the bias supply circuit, said supply voltage being derived from said power grid and to at least one control signal (Ctrl) supplied to the switching control circuit via the isolation circuit; wherein said switching control circuit comprises a latch circuit, providing the gate control signal to the bidirectional semiconductor switch (M1, M2),and wherein said isolation circuit comprises a signal transformer or optical coupler for supplying said at least one control signal to a signal processing circuit, provided by the isolation circuit, for generating control commands to be supplied to said latch circuit.
An apparatus, comprising: a memory device, wherein the memory device comprises: a bank arbiter; a plurality of banks (121-0,..., 121-7), wherein each bank of the plurality of banks is coupled to the bank arbiter and comprises; an array (130; 230) of memory cells; sensing circuitry (150; 250) coupled to the array via a plurality of sense lines (205-1, 205-2; 305-1, 305-2), the sensing circuitry including sense amplifiers (206; 306) and a compute component (231; 331) configured to implement logical operations; and a memory controller coupled to the array and sensing circuitry, the memory controller configured to: receive a block of resolved instructions from at least one of a host and a channel controller; set a series of registers in the bank arbiter, wherein at least one of the memory controller and the bank arbiter are configured to receive a multicast write command to the memory device; and write the resolved instructions to a plurality of locations in the array in parallel. a bank arbiter; a plurality of banks (121-0,..., 121-7), wherein each bank of the plurality of banks is coupled to the bank arbiter and comprises; an array (130; 230) of memory cells; sensing circuitry (150; 250) coupled to the array via a plurality of sense lines (205-1, 205-2; 305-1, 305-2), the sensing circuitry including sense amplifiers (206; 306) and a compute component (231; 331) configured to implement logical operations; and a memory controller coupled to the array and sensing circuitry, the memory controller configured to: receive a block of resolved instructions from at least one of a host and a channel controller; set a series of registers in the bank arbiter, wherein at least one of the memory controller and the bank arbiter are configured to receive a multicast write command to the memory device; and write the resolved instructions to a plurality of locations in the array in parallel. receive a block of resolved instructions from at least one of a host and a channel controller; set a series of registers in the bank arbiter, wherein at least one of the memory controller and the bank arbiter are configured to receive a multicast write command to the memory device; and write the resolved instructions to a plurality of locations in the array in parallel.