A latch circuit (2; 10; 64) for use as a multiplexer to multiplex information carried by respective pairs of input information signals (RZA, /RZA, RZB, /RZB) onto an output information signal (RZC, /RZC), each pair of input information signals comprising a first input information signal (RZA, /RZA) and a second input information signal (RZB, /RZB), and each pair of input information signals carrying information values based on signal values of those input information signals and interleaved with information values carried by the other pair or pairs of input information signals, the latch circuit comprising: a plurality of pairs of input switches (12, 14, 16, 18), each pair of input switches comprising a first input switch (12, 16) and a second input switch (14, 18), and each pair of input switches configured to be controlled by a corresponding said pair of input information signals; and two cross-coupled inverters (28, 30), the outputs of said inverters providing an output configured to output said output information signal, wherein: of each said pair of input switches, the first input switch (12, 16) is configured to receive the first input information signal of the corresponding pair of input information signals and the second input switch (14, 18) is configured to receive the second input information signal of that pair of input information signals; of said input switches, the first input switches (12, 16) are connected in parallel with one another between a common tail node and a first node to control a first current at said first node of the latch circuit and the second input switches (14, 18) are connected in parallel with one another between the common tail node and a second node to control a second current at said second node of the latch circuit; a first inverter of the cross-coupled inverters is connected between the first node and a first reference voltage source and a second inverter of the cross-coupled inverters is connected between the second node and the first reference voltage source; an activate transistor is connected between the common tail node and a second reference voltage source; and the latch circuit is configured to control the output information signal based on which of said first and second currents is larger than the other so as to latch successive information values carried by the pairs of input information signals onto the output information signal. a plurality of pairs of input switches (12, 14, 16, 18), each pair of input switches comprising a first input switch (12, 16) and a second input switch (14, 18), and each pair of input switches configured to be controlled by a corresponding said pair of input information signals; and two cross-coupled inverters (28, 30), the outputs of said inverters providing an output configured to output said output information signal, wherein: of each said pair of input switches, the first input switch (12, 16) is configured to receive the first input information signal of the corresponding pair of input information signals and the second input switch (14, 18) is configured to receive the second input information signal of that pair of input information signals; of said input switches, the first input switches (12, 16) are connected in parallel with one another between a common tail node and a first node to control a first current at said first node of the latch circuit and the second input switches (14, 18) are connected in parallel with one another between the common tail node and a second node to control a second current at said second node of the latch circuit; a first inverter of the cross-coupled inverters is connected between the first node and a first reference voltage source and a second inverter of the cross-coupled inverters is connected between the second node and the first reference voltage source; an activate transistor is connected between the common tail node and a second reference voltage source; and the latch circuit is configured to control the output information signal based on which of said first and second currents is larger than the other so as to latch successive information values carried by the pairs of input information signals onto the output information signal. of each said pair of input switches, the first input switch (12, 16) is configured to receive the first input information signal of the corresponding pair of input information signals and the second input switch (14, 18) is configured to receive the second input information signal of that pair of input information signals; of said input switches, the first input switches (12, 16) are connected in parallel with one another between a common tail node and a first node to control a first current at said first node of the latch circuit and the second input switches (14, 18) are connected in parallel with one another between the common tail node and a second node to control a second current at said second node of the latch circuit; a first inverter of the cross-coupled inverters is connected between the first node and a first reference voltage source and a second inverter of the cross-coupled inverters is connected between the second node and the first reference voltage source; an activate transistor is connected between the common tail node and a second reference voltage source; and the latch circuit is configured to control the output information signal based on which of said first and second currents is larger than the other so as to latch successive information values carried by the pairs of input information signals onto the output information signal.