A Phase Rotator and Amplitude control Unit, PRAU, for performing phase rotation and amplitude control of an input signal and generating an output signal (Out) with an individual phase shift, the PRAU comprising: a plurality N1 of Phase Rotator and Amplitude control Circuits, PRAC (PRAC<1>,...PRAC<i>,...PRAC<N1>), wherein each PRAC comprises: an input port comprising in-phase and quadrature-phase inputs (Ip, In, Qp, Qn) to receive the input signal; an output port comprising in-phase and quadrature-phase outputs (Olp, Oln, OQp, OQn); control inputs to receive phase and amplitude control parameters, wherein the phase and amplitude control parameters comprise sign control signals (pa11, pa12, pa21, pa22, na11, na12, na21, na22) and positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), each positive amplitude coefficient signal has N1 digital bits; and each PRAC further comprises: a plurality of switched transconductance branches, wherein each switched transconductance branch comprises one transconductance transistor connected in series with two switching transistors, and wherein a gate of one switching transistor is coupled to one of the sign control signals (pa11, pa12, pa21, pa22, na11, na12, na21 na22), a gate of another switching transistor is coupled to one of the positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), a gate of the transconductance transistor is coupled to one of the in-phase and quadrature-phase inputs (Ip, In; Qp, Qn), and a drain of the transconductance transistor is coupled to one of the in-phase and quadrature-phase outputs (Olp, Oln, OQp, OQn); and wherein each PRAC (PRAC1,... PRACn) is configured to receive one bit of the positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), and the output signal (Out) comprises in-phase and quadrature-phase output signals, and wherein the in-phase outputs (Olp, Oln) from each PRAC (PRAC<1>,...PRAC<i>,... PRAC<N1>) are arranged to be combined to generate the in-phase output signal of the output signal (Out), and the quadrature-phase outputs (OQp, OQn) from each PRAC (PRAC<1>,...PRAC<i>,...PRAC<N1>) are arranged to be combined to generate the quadrature-phase output signal of the output signal (Out). an input port comprising in-phase and quadrature-phase inputs (Ip, In, Qp, Qn) to receive the input signal; an output port comprising in-phase and quadrature-phase outputs (Olp, Oln, OQp, OQn); control inputs to receive phase and amplitude control parameters, wherein the phase and amplitude control parameters comprise sign control signals (pa11, pa12, pa21, pa22, na11, na12, na21, na22) and positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), each positive amplitude coefficient signal has N1 digital bits; and each PRAC further comprises: a plurality of switched transconductance branches, wherein each switched transconductance branch comprises one transconductance transistor connected in series with two switching transistors, and wherein a gate of one switching transistor is coupled to one of the sign control signals (pa11, pa12, pa21, pa22, na11, na12, na21 na22), a gate of another switching transistor is coupled to one of the positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), a gate of the transconductance transistor is coupled to one of the in-phase and quadrature-phase inputs (Ip, In; Qp, Qn), and a drain of the transconductance transistor is coupled to one of the in-phase and quadrature-phase outputs (Olp, Oln, OQp, OQn); and wherein each PRAC (PRAC1,... PRACn) is configured to receive one bit of the positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), and the output signal (Out) comprises in-phase and quadrature-phase output signals, and wherein the in-phase outputs (Olp, Oln) from each PRAC (PRAC<1>,...PRAC<i>,... PRAC<N1>) are arranged to be combined to generate the in-phase output signal of the output signal (Out), and the quadrature-phase outputs (OQp, OQn) from each PRAC (PRAC<1>,...PRAC<i>,...PRAC<N1>) are arranged to be combined to generate the quadrature-phase output signal of the output signal (Out). a gate of one switching transistor is coupled to one of the sign control signals (pa11, pa12, pa21, pa22, na11, na12, na21 na22), a gate of another switching transistor is coupled to one of the positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), a gate of the transconductance transistor is coupled to one of the in-phase and quadrature-phase inputs (Ip, In; Qp, Qn), and a drain of the transconductance transistor is coupled to one of the in-phase and quadrature-phase outputs (Olp, Oln, OQp, OQn); and wherein each PRAC (PRAC1,... PRACn) is configured to receive one bit of the positive amplitude coefficient signals (a11<i>, a12<i>, a21<i>, a22<i>), and the output signal (Out) comprises in-phase and quadrature-phase output signals, and wherein the in-phase outputs (Olp, Oln) from each PRAC (PRAC<1>,...PRAC<i>,... PRAC<N1>) are arranged to be combined to generate the in-phase output signal of the output signal (Out), and the quadrature-phase outputs (OQp, OQn) from each PRAC (PRAC<1>,...PRAC<i>,...PRAC<N1>) are arranged to be combined to generate the quadrature-phase output signal of the output signal (Out).