A system for converting a Boolean masked value to an arithmetically masked value for a cryptographic operation comprising: a first set of registers to store the Boolean masked value as a first share ( x ⊕ r 1 ⊕ r 2 ⊕ α), a second input share value r 1, and a third input share value r 2, the first share ( x ⊕ r 1 ⊕ r 2 ⊕ α) being a ⊕ Boolean combination between an input value x, the second input share value ( r 1), the third input share value ( r 2), and a first random number α; a second set of registers to store the arithmetically masked value as a first output share value, a second output share value s 1, and a third output share value s 2, the first output share value representing an arithmetic combination between the input value (x), the second output share value, and the third output share value; a cryptographic component to perform the cryptographic operation based on a Boolean operation and an arithmetic operation; and a processing device, operatively coupled with the first set of registers and the second set of registers, to receive an indication that the cryptographic operation being performed by the cryptographic component has switched from using the Boolean operation to using the arithmetic operation; in response to the indication, receive the first, second, and third input share values from the first set of registers; and configured to perform a series of operations according to an algorithm, wherein the input x' to the algorithm is the first share ( x ⊕ r 1 ⊕ r 2 ⊕ α), the second input share value ( r 1), and the third input share value ( r 2) and random numbers γ 1,γ 2, α, s 1,s 2 and the output x" the first output share value, wherein the algorithm consists in the following series of operations: 1: z ← γ 1 ⊕r 1; 2: z ← z⊕ γ 2; 3: z ← z⊕r 2; 4: u ← x' ⊕ z; 5: z ← z⊕ α; 6: u ← u+z; 7: v ← x'⊕ γ 1; 8: v ← v⊕ α; 9: v ← v + γ 1; 10: w ← x'⊕ γ 2; 11: w ← w⊕ α; 12: w ← w+ γ 2; 13: z ← r 2 ⊕ s 1; 14: u ← u+ r 2; 15: u ← u⊕ v; 16: u ← u⊕ w; 17: v ← u⊕ s 1; 18: v ← v+ r 2; 19: w ← u⊕ z; 20: v ← v⊕ w; 21: w ← u+ z; 22: z ← v⊕ w; 23: w ← α⊕ r 2; 24: u ← s 2 ⊕ r 1; 25: u ←u - w; 26: w ← w ⊕ s 2; 27: v ← w ⊕ r 1; 28: w ←w - r 1; 29: u ← u ⊕ v; 30: u ← u ⊕ w; 31 z ←z + u; return z; a first set of registers to store the Boolean masked value as a first share ( x ⊕ r 1 ⊕ r 2 ⊕ α), a second input share value r 1, and a third input share value r 2, the first share ( x ⊕ r 1 ⊕ r 2 ⊕ α) being a ⊕ Boolean combination between an input value x, the second input share value ( r 1), the third input share value ( r 2), and a first random number α; a second set of registers to store the arithmetically masked value as a first output share value, a second output share value s 1, and a third output share value s 2, the first output share value representing an arithmetic combination between the input value (x), the second output share value, and the third output share value; a cryptographic component to perform the cryptographic operation based on a Boolean operation and an arithmetic operation; and a processing device, operatively coupled with the first set of registers and the second set of registers, to receive an indication that the cryptographic operation being performed by the cryptographic component has switched from using the Boolean operation to using the arithmetic operation; in response to the indication, receive the first, second, and third input share values from the first set of registers; and configured to perform a series of operations according to an algorithm, wherein the input x' to the algorithm is the first share ( x ⊕ r 1 ⊕ r 2 ⊕ α), the second input share value ( r 1), and the third input share value ( r 2) and random numbers γ 1,γ 2, α, s 1,s 2 and the output x" the first output share value, wherein the algorithm consists in the following series of operations: 1: z ← γ 1 ⊕r 1; 2: z ← z⊕ γ 2; 3: z ← z⊕r 2; 4: u ← x' ⊕ z; 5: z ← z⊕ α; 6: u ← u+z; 7: v ← x'⊕ γ 1; 8: v ← v⊕ α; 9: v ← v + γ 1; 10: w ← x'⊕ γ 2; 11: w ← w⊕ α; 12: w ← w+ γ 2; 13: z ← r 2 ⊕ s 1; 14: u ← u+ r 2; 15: u ← u⊕ v; 16: u ← u⊕ w; 17: v ← u⊕ s 1; 18: v ← v+ r 2; 19: w ← u⊕ z; 20: v ← v⊕ w; 21: w ← u+ z; 22: z ← v⊕ w; 23: w ← α⊕ r 2; 24: u ← s 2 ⊕ r 1; 25: u ←u - w; 26: w ← w ⊕ s 2; 27: v ← w ⊕ r 1; 28: w ←w - r 1; 29: u ← u ⊕ v; 30: u ← u ⊕ w; 31 z ←z + u; return z; 1: z ← γ 1 ⊕r 1; 2: z ← z⊕ γ 2; 3: z ← z⊕r 2; 4: u ← x' ⊕ z; 5: z ← z⊕ α; 6: u ← u+z; 7: v ← x'⊕ γ 1; 8: v ← v⊕ α; 9: v ← v + γ 1; 10: w ← x'⊕ γ 2; 11: w ← w⊕ α; 12: w ← w+ γ 2; 13: z ← r 2 ⊕ s 1; 14: u ← u+ r 2; 15: u ← u⊕ v; 16: u ← u⊕ w; 17: v ← u⊕ s 1; 18: v ← v+ r 2; 19: w ← u⊕ z; 20: v ← v⊕ w; 21: w ← u+ z; 22: z ← v⊕ w; 23: w ← α⊕ r 2; 24: u ← s 2 ⊕ r 1; 25: u ←u - w; 26: w ← w ⊕ s 2; 27: v ← w ⊕ r 1; 28: w ←w - r 1; 29: u ← u ⊕ v; 30: u ← u ⊕ w; 31 z ←z + u;