A sense amplifier circuit, comprising: a first current path and a second current path; a first transistor and a second transistor, wherein: the first transistor is configured as a current source for the first current path during at least a latter portion of a first phase of a memory read operation and during at least an initial portion of a second phase of the memory read operation, the second transistor is configured as a current source for the second current path during at least the latter portion of the first phase of the memory read operation and during at least the initial portion of the second phase of the memory read operation; a third transistor located in the first current path; a fourth transistor located in the second current path; a capacitor having a first electrode connected to a control terminal of the third transistor, and a second electrode coupled to a control terminal of the fourth transistor; a control circuit; a first switch and a second switch configured to respectively couple the first current path and the second current path to respectively a first cell and a second cell in a closed position; wherein the control circuit is configured to close during the first phase of the memory read operation and to open during the second phase of the memory read operation the first switch and the second switch; a third switch and a fourth switch configured to respectively couple the first current path and the second current path to respectively the second cell and first cell in a closed position; wherein the control circuit is configured to close during the second phase of the memory read operation and to open during the first phase of the memory read operation the third switch and the fourth switch; a fifth switch connected between a first node of the first current path and the first electrode of the capacitor, and wherein the control circuit is configured to close during the first phase of the memory read operation and to open during the second phase of the memory read operation said fifth switch characterized by: a sixth switch connected between a second node of the second current path and the second electrode of the capacitor, wherein said control circuit is configured to close said sixth switch during the during both the first phase and second phase of the memory read operation and wherein the second electrode of the capacitor is connected to the control terminal of the fourth transistor. a first current path and a second current path; a first transistor and a second transistor, wherein: the first transistor is configured as a current source for the first current path during at least a latter portion of a first phase of a memory read operation and during at least an initial portion of a second phase of the memory read operation, the second transistor is configured as a current source for the second current path during at least the latter portion of the first phase of the memory read operation and during at least the initial portion of the second phase of the memory read operation; the first transistor is configured as a current source for the first current path during at least a latter portion of a first phase of a memory read operation and during at least an initial portion of a second phase of the memory read operation, the second transistor is configured as a current source for the second current path during at least the latter portion of the first phase of the memory read operation and during at least the initial portion of the second phase of the memory read operation; a third transistor located in the first current path; a fourth transistor located in the second current path; a capacitor having a first electrode connected to a control terminal of the third transistor, and a second electrode coupled to a control terminal of the fourth transistor; a control circuit; a first switch and a second switch configured to respectively couple the first current path and the second current path to respectively a first cell and a second cell in a closed position; wherein the control circuit is configured to close during the first phase of the memory read operation and to open during the second phase of the memory read operation the first switch and the second switch; a third switch and a fourth switch configured to respectively couple the first current path and the second current path to respectively the second cell and first cell in a closed position; wherein the control circuit is configured to close during the second phase of the memory read operation and to open during the first phase of the memory read operation the third switch and the fourth switch; a fifth switch connected between a first node of the first current path and the first electrode of the capacitor, and wherein the control circuit is configured to close during the first phase of the memory read operation and to open during the second phase of the memory read operation said fifth switch characterized by: a sixth switch connected between a second node of the second current path and the second electrode of the capacitor, wherein said control circuit is configured to close said sixth switch during the during both the first phase and second phase of the memory read operation and wherein the second electrode of the capacitor is connected to the control terminal of the fourth transistor.