A level shifter comprising: high breakdown voltage first and second PMOS transistors (P1, P2) placed in parallel between a first power supply voltage terminal (VDDQ) and a reference voltage terminal, each transistor having a gate connected to a drain of the other transistor; high breakdown voltage first and second depletion NMOS transistors (NA1, NA2) placed between the first and second PMOS transistors (P1, P2) and the reference voltage terminal and having gates respectively supplied with first and second control signals (IN1, IN2); low breakdown voltage first and second NMOS transistors (N1, N2) placed between the first and second depletion NMOS transistors (NA1, NA2) and the reference voltage terminal and having gates respectively supplied with third and fourth control signals (IN3, IN4); and a timing control unit (12, 13, INV1) placed between a second power supply voltage terminal supplied with a second power supply voltage lower than a first power supply voltage supplied to the first power supply voltage terminal (VDDQ) and the reference voltage terminal, the timing control unit (12, 13, INV1) generating the first control signal and the third control signal, each corresponding to an inverted signal of an input signal, and generating the second control signal and the fourth control signal, each corresponding to a non-inverted signal of the input signal, characterized in that: the first control signal and the second control signal have a lower slew rate at a rising edge than the third control signal and the fourth control signal respectively, and the third control signal and the fourth control signal have a lower slew rate at a falling edge than the first control signal and the second control signal respectively. high breakdown voltage first and second PMOS transistors (P1, P2) placed in parallel between a first power supply voltage terminal (VDDQ) and a reference voltage terminal, each transistor having a gate connected to a drain of the other transistor; high breakdown voltage first and second depletion NMOS transistors (NA1, NA2) placed between the first and second PMOS transistors (P1, P2) and the reference voltage terminal and having gates respectively supplied with first and second control signals (IN1, IN2); low breakdown voltage first and second NMOS transistors (N1, N2) placed between the first and second depletion NMOS transistors (NA1, NA2) and the reference voltage terminal and having gates respectively supplied with third and fourth control signals (IN3, IN4); and a timing control unit (12, 13, INV1) placed between a second power supply voltage terminal supplied with a second power supply voltage lower than a first power supply voltage supplied to the first power supply voltage terminal (VDDQ) and the reference voltage terminal, the timing control unit (12, 13, INV1) generating the first control signal and the third control signal, each corresponding to an inverted signal of an input signal, and generating the second control signal and the fourth control signal, each corresponding to a non-inverted signal of the input signal, characterized in that: the first control signal and the second control signal have a lower slew rate at a rising edge than the third control signal and the fourth control signal respectively, and the third control signal and the fourth control signal have a lower slew rate at a falling edge than the first control signal and the second control signal respectively. the first control signal and the second control signal have a lower slew rate at a rising edge than the third control signal and the fourth control signal respectively, and the third control signal and the fourth control signal have a lower slew rate at a falling edge than the first control signal and the second control signal respectively.