An automated test equipment apparatus for use in connection with a memory repair circuit for repairing one or more failures in an embedded memory, the apparatus comprising: at least one processor operative: (i) to generate a first control signal, the first control signal being supplied to the memory repair circuit for initiating an automated memory repair procedure in the memory repair circuit; (ii) to receive, from the memory repair circuit, status information relating to a memory built-in self-test (MBIST) procedure performed on the embedded memory; (iii) to determine, based at least in part on the status information, whether the embedded memory is repairable; characterized in that the automated test equipment apparatus further comprises a programmable voltage source, and in that the at least one processor is coupled to the programmable voltage source and is operative to (iv) when the embedded memory is determined to be repairable, to set the programmable voltage source to a first voltage level at least equal to a minimum voltage potential suitable for burning at least one fuse register in the memory repair circuit and to generate a second control signal, the second control signal being supplied to the memory repair circuit for initiating an automated fuse burn procedure for programming the at least one fuse register; (v) to receive a first acknowledgment indicating whether the fuse burn procedure has been completed; (vi) in response to the first acknowledgment that the fuse burn procedure has been completed, to set the programmable voltage source to a second voltage level which is less than the minimum voltage potential suitable for burning the at least one fuse register; (vii) to generate a third control signal, the third control signal being supplied to the memory repair circuit for initiating an automated verification procedure in the memory repair circuit for verifying data burned into the at least one fuse register; and (viii) to receive a second acknowledgment indicating a result of the verification procedure. at least one processor operative: (i) to generate a first control signal, the first control signal being supplied to the memory repair circuit for initiating an automated memory repair procedure in the memory repair circuit; (ii) to receive, from the memory repair circuit, status information relating to a memory built-in self-test (MBIST) procedure performed on the embedded memory; (iii) to determine, based at least in part on the status information, whether the embedded memory is repairable; (iv) when the embedded memory is determined to be repairable, to set the programmable voltage source to a first voltage level at least equal to a minimum voltage potential suitable for burning at least one fuse register in the memory repair circuit and to generate a second control signal, the second control signal being supplied to the memory repair circuit for initiating an automated fuse burn procedure for programming the at least one fuse register; (v) to receive a first acknowledgment indicating whether the fuse burn procedure has been completed; (vi) in response to the first acknowledgment that the fuse burn procedure has been completed, to set the programmable voltage source to a second voltage level which is less than the minimum voltage potential suitable for burning the at least one fuse register; (vii) to generate a third control signal, the third control signal being supplied to the memory repair circuit for initiating an automated verification procedure in the memory repair circuit for verifying data burned into the at least one fuse register; and (viii) to receive a second acknowledgment indicating a result of the verification procedure.