A semiconductor device (100; 200), comprising: an insulating substrate with conductive patterns (1; 1a), which has, at least, a first conductive pattern (4; 4a), a second conductive pattern (5; 5a), and a third conductive pattern (6; 6a; 6b; 6c) on a first insulating substrate (2; 2a); a positive-electrode external lead terminal (21; 21a) that is fixed to the first conductive pattern (4; 4a); a negative-electrode external lead terminal (22; 22a) that is fixed to the second conductive pattern (5; 5a); an external lead terminal of intermediate potential (23; 23a) that is fixed to the third conductive pattern (6; 6a; 6b; 6c); a first semiconductor element (9, 10; 9a, 10a, 9b, 10b, 9c, 10c) having one surface fixed to the first conductive pattern (4; 4a); a second semiconductor element (11, 12; 11a, 12a, 11b, 12b, 11c, 12c) having one surface fixed to the third conductive pattern (6; 6a, 6b, 6c); and an insulating substrate with conductive pins (13; 13a), which has conductive layers (15, 16; 15a, 16a) on front and rear surfaces of a second insulating substrate (14; 14a) respectively, a plurality of first conductive pins (18, 19) fixed to the conductive layer on the rear surface (16; 16a) of the second insulating substrate (14; 14a), and a plurality of second conductive pins (17, 20) fixed to the conductive layer on the front surface (15; 15a) of the second insulating substrate (14; 14a), wherein the positive-electrode external lead terminal (21; 21a) and the negative-electrode external lead terminal (22; 22a) are disposed adjacent to each other in parallel, some of the first conductive pins (18, 19) are fixed to the other surface of the first semiconductor element (9, 10; 9a, 10a, 9b, 10b, 9c, 10c), while the other first conductive pins are fixed to the third conductive pattern (6; 6a, 6b, 6c), some of the second conductive pins (17, 20) are fixed to the other surface of the second semiconductor element (11, 12; 11a, 12a, 11b, 12b, 11c, 12c), while the other second conductive pins are fixed to the second conductive pattern (5; 5a), the insulating substrate with conductive pins (13; 13a) is disposed on the other surface of the first semiconductor element (9, 10; 9a, 10a, 9b, 10b, 9c, 10c) and the other surface of the second semiconductor element (11, 12; 11a, 12a, 11b, 12b, 11c, 12c), characterized in that the size of the insulating substrate with conductive pins (13; 13a) is such that it includes sections of the second and third conductive patterns (5, 6) to which the pins (13, 13a) are fixed and includes an area in which the first semiconductor element (9, 10; 9a, 10a, 9b, 10b, 9c, 10c) and the second semiconductor element (11, 12; 11a, 12a, 11b, 12b, 11c, 12c) is disposed. an insulating substrate with conductive patterns (1; 1a), which has, at least, a first conductive pattern (4; 4a), a second conductive pattern (5; 5a), and a third conductive pattern (6; 6a; 6b; 6c) on a first insulating substrate (2; 2a); a positive-electrode external lead terminal (21; 21a) that is fixed to the first conductive pattern (4; 4a); a negative-electrode external lead terminal (22; 22a) that is fixed to the second conductive pattern (5; 5a); an external lead terminal of intermediate potential (23; 23a) that is fixed to the third conductive pattern (6; 6a; 6b; 6c); a first semiconductor element (9, 10; 9a, 10a, 9b, 10b, 9c, 10c) having one surface fixed to the first conductive pattern (4; 4a); a second semiconductor element (11, 12; 11a, 12a, 11b, 12b, 11c, 12c) having one surface fixed to the third conductive pattern (6; 6a, 6b, 6c); and an insulating substrate with conductive pins (13; 13a), which has conductive layers (15, 16; 15a, 16a) on front and rear surfaces of a second insulating substrate (14; 14a) respectively, a plurality of first conductive pins (18, 19) fixed to the conductive layer on the rear surface (16; 16a) of the second insulating substrate (14; 14a), and a plurality of second conductive pins (17, 20) fixed to the conductive layer on the front surface (15; 15a) of the second insulating substrate (14; 14a), wherein the positive-electrode external lead terminal (21; 21a) and the negative-electrode external lead terminal (22; 22a) are disposed adjacent to each other in parallel, some of the first conductive pins (18, 19) are fixed to the other surface of the first semiconductor element (9, 10; 9a, 10a, 9b, 10b, 9c, 10c), while the other first conductive pins are fixed to the third conductive pattern (6; 6a, 6b, 6c), some of the second conductive pins (17, 20) are fixed to the other surface of the second semiconductor element (11, 12; 11a, 12a, 11b, 12b, 11c, 12c), while the other second conductive pins are fixed to the second conductive pattern (5; 5a), the insulating substrate with conductive pins (13; 13a) is disposed on the other surface of the first semiconductor element (9, 10; 9a, 10a, 9b, 10b, 9c, 10c) and the other surface of the second semiconductor element (11, 12; 11a, 12a, 11b, 12b, 11c, 12c),