Memory device comprising - a non-volatile memory block to store data to be written, read or erased, - a protection unit arranged for connecting to a communication bus to detect an unlock, write or erase command and comprising a unit for locking and unlocking said memory block, said unit arranged to receive and process said unlock, write or erase command, and characterized by - a sequencer arranged to receive from said protection unit, in accordance with said unlock, write or erase command, an enabling signal to enable access to said memory block, whereby said unit for locking and unlocking comprises, for processing said unlock, write or erase command, a logic circuit arranged to output said enabling signal, said logic circuit comprising a first logic subcircuit arranged for comparing a first part of said command with a first part of a hard coded key, whereby a first subcircuit output signal corresponding to a first active logic signal is output if there is a match between said first part of said command and said first part of said hard coded key a second logic subcircuit arranged for comparing a second part of said command with a second part of said hard coded key, whereby a second subcircuit output signal corresponding to a second active logic signal inverse to said first active logic signal is output if there is a match between said second part of said command and said second part of said hard coded key, whereby one of said first and second logic subcircuit is operable on a logic 1 active signal and the other one is operable on a logic 0 active signal, and a combiner logic circuit arranged for combining said first and said second subcircuit output signal and for outputting said enabling signal corresponding to an active logic signal only if said first and said second subcircuit output signals correspond to said first and second active logic signal, respectively. - a non-volatile memory block to store data to be written, read or erased, - a protection unit arranged for connecting to a communication bus to detect an unlock, write or erase command and comprising a unit for locking and unlocking said memory block, said unit arranged to receive and process said unlock, write or erase command, - a sequencer arranged to receive from said protection unit, in accordance with said unlock, write or erase command, an enabling signal to enable access to said memory block, a first logic subcircuit arranged for comparing a first part of said command with a first part of a hard coded key, whereby a first subcircuit output signal corresponding to a first active logic signal is output if there is a match between said first part of said command and said first part of said hard coded key a second logic subcircuit arranged for comparing a second part of said command with a second part of said hard coded key, whereby a second subcircuit output signal corresponding to a second active logic signal inverse to said first active logic signal is output if there is a match between said second part of said command and said second part of said hard coded key, whereby one of said first and second logic subcircuit is operable on a logic 1 active signal and the other one is operable on a logic 0 active signal, and a combiner logic circuit arranged for combining said first and said second subcircuit output signal and for outputting said enabling signal corresponding to an active logic signal only if said first and said second subcircuit output signals correspond to said first and second active logic signal, respectively.