A demultiplexer, comprising a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor, a first control gate line, a second control gate line, and a third control gate line, wherein, sources (13, 13, 33) of the first thin film transistor, the second thin film transistor and the third thin film transistor are coupled together to form a first input terminal of the demultiplexer; sources (43, 43, 63) of the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are coupled together to form a second input terminal of the demultiplexer; drains (12, 22, 32, 42, 52, 62) of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are respectively used as a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal and a sixth output terminal of the demultiplexer; gates (11, 51) of the first thin film transistor and the fifth thin film transistor are coupled to a first control terminal, gates (31, 41) of the third thin film transistor and the fourth thin film transistor are coupled to a second control terminal, and gates (21, 61) of the second thin film transistor and the sixth thin film transistor are coupled to a third control terminal, the first control terminal, the second control terminal and the third control terminal are configured to be a first control gate line to a third control gate line which are arranged in parallel; and the first thin film transistor, the second thin film transistor and the third thin film transistor are located on a side of the first control gate line, the second control gate line and the third control gate line which are parallel to each other, and the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are located on another side of the first control gate line, the second control gate line and the third control gate line away from the first thin film transistor, the second thin film transistor and the third thin film transistor, and the source (13, 13) of the first thin film transistor and the source of the second thin film transistor are a first common source shared by the first thin film transistor and the second thin film transistor; the source (43, 43) of the fourth thin film transistor and the source of the fifth thin film transistor are a second common source shared by the fourth thin film transistor and the fifth thin film transistor. sources (13, 13, 33) of the first thin film transistor, the second thin film transistor and the third thin film transistor are coupled together to form a first input terminal of the demultiplexer; sources (43, 43, 63) of the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are coupled together to form a second input terminal of the demultiplexer; drains (12, 22, 32, 42, 52, 62) of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are respectively used as a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal and a sixth output terminal of the demultiplexer; gates (11, 51) of the first thin film transistor and the fifth thin film transistor are coupled to a first control terminal, gates (31, 41) of the third thin film transistor and the fourth thin film transistor are coupled to a second control terminal, and gates (21, 61) of the second thin film transistor and the sixth thin film transistor are coupled to a third control terminal, the first control terminal, the second control terminal and the third control terminal are configured to be a first control gate line to a third control gate line which are arranged in parallel; and the first thin film transistor, the second thin film transistor and the third thin film transistor are located on a side of the first control gate line, the second control gate line and the third control gate line which are parallel to each other, and the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are located on another side of the first control gate line, the second control gate line and the third control gate line away from the first thin film transistor, the second thin film transistor and the third thin film transistor, and the source (13, 13) of the first thin film transistor and the source of the second thin film transistor are a first common source shared by the first thin film transistor and the second thin film transistor; the source (43, 43) of the fourth thin film transistor and the source of the fifth thin film transistor are a second common source shared by the fourth thin film transistor and the fifth thin film transistor.