A clock recovery apparatus (100, 200, 2000, 2200) comprising: three pulse generating circuits (1608, 1610, 1612, 1808, 1810, 1812), each pulse generating circuit (1608, 1610, 1612, 1808, 1810, 1812) being configured to generate a transition pulse (1408, 1704, 1706, 1708, 1904, 1906, 1908) in response to a transition in one of three difference signals (810a, 1202, 1602, 1802, 2222) representative of a difference in signaling state of a pair of wires in a three-wire bus (2010, 2220), wherein transitions in one or more difference signals (810a, 1202, 1602, 1802, 2222) occur at boundaries between symbols that are sequentially transmitted over the three-wire bus (2010, 2220); a first logic circuit (1614, 1814) configured to provide a single pulse (1714, 1914) in a combination signal (1630, 1830) at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses (1408, 1704, 1706, 1708, 1904, 1906, 1908) received from the three pulse generating circuits (1608, 1610, 1612, 1808, 1810, 1812); and a delay flipflop (1642, 1842) configured to respond to each single pulse (1714, 1914) in the combination signal by changing signaling state of a clock signal (1650, 1850) that is output by the clock recovery apparatus (100, 200, 2000, 2200), wherein to respond to a first single pulse (1714, 1914), the delay flipflop (1642, 1842) is configured to change the signaling state from a logic 0 state to a logic 1 state, and in response to a second single pulse (1714, 1914) consecutive to the first single pulse (1714, 1914), the delay flipflop (1642, 1842) is configured to change the signaling state from a logic 1 state to a logic 0 state. three pulse generating circuits (1608, 1610, 1612, 1808, 1810, 1812), each pulse generating circuit (1608, 1610, 1612, 1808, 1810, 1812) being configured to generate a transition pulse (1408, 1704, 1706, 1708, 1904, 1906, 1908) in response to a transition in one of three difference signals (810a, 1202, 1602, 1802, 2222) representative of a difference in signaling state of a pair of wires in a three-wire bus (2010, 2220), wherein transitions in one or more difference signals (810a, 1202, 1602, 1802, 2222) occur at boundaries between symbols that are sequentially transmitted over the three-wire bus (2010, 2220); a first logic circuit (1614, 1814) configured to provide a single pulse (1714, 1914) in a combination signal (1630, 1830) at each boundary between pairs of sequentially-transmitted symbols by combining one or more transition pulses (1408, 1704, 1706, 1708, 1904, 1906, 1908) received from the three pulse generating circuits (1608, 1610, 1612, 1808, 1810, 1812); and a delay flipflop (1642, 1842) configured to respond to each single pulse (1714, 1914) in the combination signal by changing signaling state of a clock signal (1650, 1850) that is output by the clock recovery apparatus (100, 200, 2000, 2200), wherein to respond to a first single pulse (1714, 1914), the delay flipflop (1642, 1842) is configured to change the signaling state from a logic 0 state to a logic 1 state, and in response to a second single pulse (1714, 1914) consecutive to the first single pulse (1714, 1914), the delay flipflop (1642, 1842) is configured to change the signaling state from a logic 1 state to a logic 0 state.