An integrated circuit comprising: first driver circuitry (224, 265, 300) including first current mirror circuitry and a first output stage, the first current mirror circuitry including a second current source and a first transistor, the first output stage comprising a first leg and a second leg in parallel with the first leg between a first node and a second node, the first leg and the second leg each to receive a respective signal of a first differential signal pair (S1, S2), and a first current source to draw current from the second node, wherein the first output stage to provide at least one output signal based on the first differential signal pair (S1, S2); characterized in that the first driver circuitry further comprises: configuration logic to select from among: a first operational mode of the first driver circuitry wherein a first circuit is closed, the first circuit coupled between the first node and a supply voltage (Vdd), wherein the first current mirror circuitry is disabled from providing a first current signal to the first node and wherein the first operational mode includes the second current source being switchedly decoupled from the first transistor; and a second operational mode of the first driver circuitry wherein the first circuit is open, the first current mirror circuitry is configured to provide the first current signal to the first node. first driver circuitry (224, 265, 300) including first current mirror circuitry and a first output stage, the first current mirror circuitry including a second current source and a first transistor, the first output stage comprising a first leg and a second leg in parallel with the first leg between a first node and a second node, the first leg and the second leg each to receive a respective signal of a first differential signal pair (S1, S2), and a first current source to draw current from the second node, wherein the first output stage to provide at least one output signal based on the first differential signal pair (S1, S2); characterized in that the first driver circuitry further comprises: the first current mirror circuitry including a second current source and a first transistor, the first output stage comprising a first leg and a second leg in parallel with the first leg between a first node and a second node, the first leg and the second leg each to receive a respective signal of a first differential signal pair (S1, S2), and a first current source to draw current from the second node, wherein the first output stage to provide at least one output signal based on the first differential signal pair (S1, S2); characterized in that the first driver circuitry further comprises: a first leg and a second leg in parallel with the first leg between a first node and a second node, the first leg and the second leg each to receive a respective signal of a first differential signal pair (S1, S2), and a first current source to draw current from the second node, wherein the first output stage to provide at least one output signal based on the first differential signal pair (S1, S2); characterized in that the first driver circuitry further comprises: configuration logic to select from among: a first operational mode of the first driver circuitry wherein a first circuit is closed, the first circuit coupled between the first node and a supply voltage (Vdd), wherein the first current mirror circuitry is disabled from providing a first current signal to the first node and wherein the first operational mode includes the second current source being switchedly decoupled from the first transistor; and a second operational mode of the first driver circuitry wherein the first circuit is open, the first current mirror circuitry is configured to provide the first current signal to the first node. a first operational mode of the first driver circuitry wherein a first circuit is closed, the first circuit coupled between the first node and a supply voltage (Vdd), wherein the first current mirror circuitry is disabled from providing a first current signal to the first node and wherein the first operational mode includes the second current source being switchedly decoupled from the first transistor; and a second operational mode of the first driver circuitry wherein the first circuit is open, the first current mirror circuitry is configured to provide the first current signal to the first node.