An on-chip cache apparatus, comprising: a read-write processing module, a cache module and a memory module, wherein the read-write processing module is connected with the cache module and the memory module respectively, and is configured to store packets into the cache module and the memory module, read packets stored in the cache module and the memory module, and transfer packets cached in the cache module to the memory module for storing; the cache module is connected with the memory module through the read-write processing module, and comprises at least one cache register configured to temporarily cache the packets; and the memory module is connected with the read-write processing module, and is configured to store the packets cached in the cache module; characterized by: the on-chip cache apparatus further comprises: an idle address management module configured to manage idle row addresses in the memory module, and wherein the read-write processing module comprises a write processing component connected to the cache module, the memory module and the idle address management module respectively, and configured to receive the packet, acquire the idle row address from the idle address management module, store the packet into the cache module according to the idle row address, and in response to that all cache registers corresponding to the idle row address in the cache module are occupied, transfer packets stored in the cache registers corresponding to the idle row address to the memory module for storing. a read-write processing module, a cache module and a memory module, wherein the read-write processing module is connected with the cache module and the memory module respectively, and is configured to store packets into the cache module and the memory module, read packets stored in the cache module and the memory module, and transfer packets cached in the cache module to the memory module for storing; the cache module is connected with the memory module through the read-write processing module, and comprises at least one cache register configured to temporarily cache the packets; and the memory module is connected with the read-write processing module, and is configured to store the packets cached in the cache module; characterized by: the on-chip cache apparatus further comprises: an idle address management module configured to manage idle row addresses in the memory module, and wherein the read-write processing module comprises a write processing component connected to the cache module, the memory module and the idle address management module respectively, and configured to receive the packet, acquire the idle row address from the idle address management module, store the packet into the cache module according to the idle row address, and in response to that all cache registers corresponding to the idle row address in the cache module are occupied, transfer packets stored in the cache registers corresponding to the idle row address to the memory module for storing. the on-chip cache apparatus further comprises: an idle address management module configured to manage idle row addresses in the memory module, and wherein the read-write processing module comprises a write processing component connected to the cache module, the memory module and the idle address management module respectively, and configured to receive the packet, acquire the idle row address from the idle address management module, store the packet into the cache module according to the idle row address, and in response to that all cache registers corresponding to the idle row address in the cache module are occupied, transfer packets stored in the cache registers corresponding to the idle row address to the memory module for storing.