A method of encoding for multiple different codes, wherein a parity check matrix of each of the multiple different codes (A, B, C, D) can be partitioned into a first sub-matrix (H 1) and a second sub-matrix (H 2) and the multiple different codes are binary QC-LDPC codes, comprising steps of: computing an intermediate parity bits vector (P 1) from a message bits vector (s) using the first sub-matrix (H 1) of the parity check matrix of a particular code of the multiple different codes; and computing a parity bits vector for the particular code of the multiple different codes from the intermediate parity bits vector (P 1) using fixed hardware resources comprising XOR gate trees that are configured to compute parity bits vectors for each of the multiple different codes and wherein an arrangement for the hardware resources is determined from a common sub-expression solution such that portions of a XOR gate tree that is configured to compute a parity bit of the parity bits vector for the particular code of the multiple different codes are commonly shared with portions of a XOR gate tree that is configured to compute a parity bit of a parity bits vector for another particular one of the multiple different codes, the method being characterized in that the transpose of the second sub-matrix (H 2 T) of each of the multiple different codes has a dual-diagonal structure and the inverse matrices ((H 2 T) A -1, (H 2 T) B -1, (H 2 T) C -1, (H 2 T) D -1) of said transposed second sub-matrices of the multiple different codes have common parts among their columns; the XOR gate trees are configured in accordance with said inverse matrices of said transposed second sub-matrices of the multiple different codes and common parts among said inverse matrices of said transposed second sub-matrices of the multiple different codes correspond to common parts among the XOR gate trees. computing an intermediate parity bits vector (P 1) from a message bits vector (s) using the first sub-matrix (H 1) of the parity check matrix of a particular code of the multiple different codes; and computing a parity bits vector for the particular code of the multiple different codes from the intermediate parity bits vector (P 1) using fixed hardware resources comprising XOR gate trees that are configured to compute parity bits vectors for each of the multiple different codes and wherein an arrangement for the hardware resources is determined from a common sub-expression solution such that portions of a XOR gate tree that is configured to compute a parity bit of the parity bits vector for the particular code of the multiple different codes are commonly shared with portions of a XOR gate tree that is configured to compute a parity bit of a parity bits vector for another particular one of the multiple different codes, the method being characterized in that the transpose of the second sub-matrix (H 2 T) of each of the multiple different codes has a dual-diagonal structure and the inverse matrices ((H 2 T) A -1, (H 2 T) B -1, (H 2 T) C -1, (H 2 T) D -1) of said transposed second sub-matrices of the multiple different codes have common parts among their columns; the XOR gate trees are configured in accordance with said inverse matrices of said transposed second sub-matrices of the multiple different codes and common parts among said inverse matrices of said transposed second sub-matrices of the multiple different codes correspond to common parts among the XOR gate trees.