An apparatus having improved pulse width modulation frequency resolution, said apparatus comprising: a period register for storing a pulse width modulation period value; control logic coupled to a least significant bit of the period register; a plus one effective period adder coupled to the period register and having a carry-in input coupled to the control logic, wherein when the carry-in input is at a first logic level, one is added to the PWM period value; a period comparator coupled to the plus one effective period adder and receiving the PWM period value when the carry-in input is at a second logic level and the PWM period value plus one when the carry-in input is at the first logic level; a clock counter for counting clock pulses from a clock source, the clock counter being coupled to the period comparator, wherein the period comparator compares a clock count from the clock counter with the PWM period value or the PWM period value plus one from the plus one effective period adder, whereby the period comparator resets the clock counter when the clock count is greater than or equal to the PWM period value or the PWM period value plus one; a duty cycle register for storing a PWM duty cycle; a duty cycle comparator coupled to the clock counter and the duty cycle register, wherein the duty cycle comparator compares the PWM duty cycle to the clock count and whenever the clock count is less than or equal to the PWM duty cycle a first logic level is generated from an output of the duty cycle comparator, otherwise a second logic level is generated therefrom, thereby generating a first PWM signal; a delay element coupled to the output of the duty cycle comparator, wherein the delay element delays the first PWM signal from the duty cycle comparator; a multiplexer coupled to the delay element and the output of the duty cycle comparator, wherein either a delayed first PWM signal or non-delayed first PWM signal is selected to produce a second PWM signal from an output of the multiplexer; and a delay flip-flop coupled to the control logic and the multiplexer, wherein the delay flip-flop states are controlled by the control logic depending on whether the delayed first PWM signal or the non-delayed first PWM signal was last selected, and the delay flip-flop generates a multiplexer control signal for selection of either the delayed first PWM signal or the non-delayed first PWM signal, whereby the second PWM signal has a PWM period resolution substantially equal to a time delay of the delay element. a period register for storing a pulse width modulation period value; control logic coupled to a least significant bit of the period register; a plus one effective period adder coupled to the period register and having a carry-in input coupled to the control logic, wherein when the carry-in input is at a first logic level, one is added to the PWM period value; a period comparator coupled to the plus one effective period adder and receiving the PWM period value when the carry-in input is at a second logic level and the PWM period value plus one when the carry-in input is at the first logic level; a clock counter for counting clock pulses from a clock source, the clock counter being coupled to the period comparator, wherein the period comparator compares a clock count from the clock counter with the PWM period value or the PWM period value plus one from the plus one effective period adder, whereby the period comparator resets the clock counter when the clock count is greater than or equal to the PWM period value or the PWM period value plus one; a duty cycle register for storing a PWM duty cycle; a duty cycle comparator coupled to the clock counter and the duty cycle register, wherein the duty cycle comparator compares the PWM duty cycle to the clock count and whenever the clock count is less than or equal to the PWM duty cycle a first logic level is generated from an output of the duty cycle comparator, otherwise a second logic level is generated therefrom, thereby generating a first PWM signal; a delay element coupled to the output of the duty cycle comparator, wherein the delay element delays the first PWM signal from the duty cycle comparator; a multiplexer coupled to the delay element and the output of the duty cycle comparator, wherein either a delayed first PWM signal or non-delayed first PWM signal is selected to produce a second PWM signal from an output of the multiplexer; and a delay flip-flop coupled to the control logic and the multiplexer, wherein the delay flip-flop states are controlled by the control logic depending on whether the delayed first PWM signal or the non-delayed first PWM signal was last selected, and the delay flip-flop generates a multiplexer control signal for selection of either the delayed first PWM signal or the non-delayed first PWM signal, whereby the second PWM signal has a PWM period resolution substantially equal to a time delay of the delay element.