A circuit, comprising: a pull-down signal generator including a plurality of logic gates corresponding to a plurality of pull-down signals, each logic gate being configured to process a pair of bits from received digital words to assert the corresponding pull-down signal; a plurality of pull-down circuits (206, 207, 405, 406) corresponding to the plurality of pull-down signals, wherein each pull-down circuit includes: a first NMOS transistor having a gate driven by the corresponding pull-down signal and a drain coupled to a common node; an inverter configured to invert the corresponding pull-down signal into a delayed pull-down signal; and a second NMOS transistor coupled between ground and a drain of the first NMOS transistor and having a gate driven by the delayed pull-down signal, wherein the inverter is configured to delay the delayed pull-down signal such that the pull-down circuit is configured to discharge the common node for a first delay period after the assertion of the corresponding pull-down signal; wherein the circuit further comprises a pull-up circuit including a PMOS transistor (205, 410, 415) coupled between the common node and a power supply node providing a power supply voltage, the pull-up circuit also including at least one buffer coupled between the common node and a gate of the PMOS transistor, wherein the at least one buffer is configured to switch on the PMOS transistor to bias the common node to the power supply voltage after a second delay period from the discharge of the common node, and wherein the second delay period is greater than or equal to a sum of the first delay period and an expected skew time for the received digital words; and wherein the circuit is located in a receiver configured to use a clock signal derived from the discharge and bias of the common node responsive to each digital word. a pull-down signal generator including a plurality of logic gates corresponding to a plurality of pull-down signals, each logic gate being configured to process a pair of bits from received digital words to assert the corresponding pull-down signal; a plurality of pull-down circuits (206, 207, 405, 406) corresponding to the plurality of pull-down signals, wherein each pull-down circuit includes: a first NMOS transistor having a gate driven by the corresponding pull-down signal and a drain coupled to a common node; an inverter configured to invert the corresponding pull-down signal into a delayed pull-down signal; and a second NMOS transistor coupled between ground and a drain of the first NMOS transistor and having a gate driven by the delayed pull-down signal, wherein the inverter is configured to delay the delayed pull-down signal such that the pull-down circuit is configured to discharge the common node for a first delay period after the assertion of the corresponding pull-down signal; a first NMOS transistor having a gate driven by the corresponding pull-down signal and a drain coupled to a common node; an inverter configured to invert the corresponding pull-down signal into a delayed pull-down signal; and a second NMOS transistor coupled between ground and a drain of the first NMOS transistor and having a gate driven by the delayed pull-down signal, wherein the inverter is configured to delay the delayed pull-down signal such that the pull-down circuit is configured to discharge the common node for a first delay period after the assertion of the corresponding pull-down signal; wherein the circuit further comprises a pull-up circuit including a PMOS transistor (205, 410, 415) coupled between the common node and a power supply node providing a power supply voltage, the pull-up circuit also including at least one buffer coupled between the common node and a gate of the PMOS transistor, wherein the at least one buffer is configured to switch on the PMOS transistor to bias the common node to the power supply voltage after a second delay period from the discharge of the common node, and wherein the second delay period is greater than or equal to a sum of the first delay period and an expected skew time for the received digital words; and wherein the circuit is located in a receiver configured to use a clock signal derived from the discharge and bias of the common node responsive to each digital word.