A chirp linearity detector for a frequency modulated continuous wave radar comprising: a PLL linearity monitor, the PLL linearity monitor comprising: a programmable-divisor frequency divider circuit for receiving a frequency source output signal from a phase-locked loop, PLL, as a frequency source, for performing frequency division according to a programmable divisor value, and for providing a frequency divided output signal; a first low pass filter circuit coupled to the programmable-divisor frequency divider circuit, the first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal; a mixer circuit coupled to the first low pass filter circuit, the mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal; a second low pass filter circuit coupled to the mixer circuit, the second low pass filter circuit for receiving the mixer output signal, for performing anti-aliasing filtering, and for providing an analog-to-digital converter, ADC, input signal; an ADC circuit coupled to the second low pass filter circuit, the ADC circuit for receiving the ADC input signal, for digitizing the ADC input signal, and for providing a digital output signal; a digital filter circuit coupled to the ADC circuit, the digital filter circuit for receiving the digital output signal and for detecting frequencies of a swept frequency chirp; wherein the PLL linearity monitor is configured to compare relationships of the frequencies of the swept frequency chirp to measure a linearity of the swept frequency chirp. a programmable-divisor frequency divider circuit for receiving a frequency source output signal from a phase-locked loop, PLL, as a frequency source, for performing frequency division according to a programmable divisor value, and for providing a frequency divided output signal; a first low pass filter circuit coupled to the programmable-divisor frequency divider circuit, the first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal; a mixer circuit coupled to the first low pass filter circuit, the mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal; a second low pass filter circuit coupled to the mixer circuit, the second low pass filter circuit for receiving the mixer output signal, for performing anti-aliasing filtering, and for providing an analog-to-digital converter, ADC, input signal; an ADC circuit coupled to the second low pass filter circuit, the ADC circuit for receiving the ADC input signal, for digitizing the ADC input signal, and for providing a digital output signal; a digital filter circuit coupled to the ADC circuit, the digital filter circuit for receiving the digital output signal and for detecting frequencies of a swept frequency chirp; wherein the PLL linearity monitor is configured to compare relationships of the frequencies of the swept frequency chirp to measure a linearity of the swept frequency chirp.