A sending apparatus, comprising: a conversion module, configured to: receive N channels of bit signals, and perform serial-to-parallel conversion on one of the N channels of bit signals, to generate two channels of first bit signals, wherein N is a natural number greater than 1, wherein the rate of each of the received bit signals corresponding to the N received channels is 1/T, and the rate of each of the generated channels of first bit signals is 1/2T; wherein the apparatus further comprises: a delay module, configured to: perform delay control on the two channels of first bit signals generated by the conversion module, to generate two channels of code bit signals, wherein one channel of the code bit signals is delayed with respect to the other channel of code bit signals by one clock cycle T; a mapping module, configured to: perform QAM quadrature amplitude modulation mapping on the two channels of code bit signals generated by the delay module and other N-1 channels of bit signals, to generate a channel of quadrature electrical signal and a channel of in-phase electrical signal, wherein four quadrants of the in-phase electrical signal and the quadrature electrical signal are determined by bit values that correspond to the two channels of code bit signals at a same moment; and a modulation module, configured to: modulate the quadrature electrical signal and the in-phase electrical signal that are generated by the mapping module, to obtain a transmit signal. a conversion module, configured to: receive N channels of bit signals, and perform serial-to-parallel conversion on one of the N channels of bit signals, to generate two channels of first bit signals, wherein N is a natural number greater than 1, wherein the rate of each of the received bit signals corresponding to the N received channels is 1/T, and the rate of each of the generated channels of first bit signals is 1/2T; wherein the apparatus further comprises: a delay module, configured to: perform delay control on the two channels of first bit signals generated by the conversion module, to generate two channels of code bit signals, wherein one channel of the code bit signals is delayed with respect to the other channel of code bit signals by one clock cycle T; a mapping module, configured to: perform QAM quadrature amplitude modulation mapping on the two channels of code bit signals generated by the delay module and other N-1 channels of bit signals, to generate a channel of quadrature electrical signal and a channel of in-phase electrical signal, wherein four quadrants of the in-phase electrical signal and the quadrature electrical signal are determined by bit values that correspond to the two channels of code bit signals at a same moment; and a modulation module, configured to: modulate the quadrature electrical signal and the in-phase electrical signal that are generated by the mapping module, to obtain a transmit signal. a delay module, configured to: perform delay control on the two channels of first bit signals generated by the conversion module, to generate two channels of code bit signals, wherein one channel of the code bit signals is delayed with respect to the other channel of code bit signals by one clock cycle T; a mapping module, configured to: perform QAM quadrature amplitude modulation mapping on the two channels of code bit signals generated by the delay module and other N-1 channels of bit signals, to generate a channel of quadrature electrical signal and a channel of in-phase electrical signal, wherein four quadrants of the in-phase electrical signal and the quadrature electrical signal are determined by bit values that correspond to the two channels of code bit signals at a same moment; and a modulation module, configured to: modulate the quadrature electrical signal and the in-phase electrical signal that are generated by the mapping module, to obtain a transmit signal.