A power backup processor unit comprising: a) a first AC input line comprising a first inductance and provided to be connected to an AC power supply with a cyclical voltage V L,in; b) a first AC output line comprising a second inductance and provided to be connected to a critical load; c) a second AC output line provided to be connected to the critical load; d) a neutral line provided to be connected to a neutral port; e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply; f) a single capacitor directly interposed between the first and second DC voltage busses (311,312); g) a first half-bridge circuit comprising a first switch and a second switch, wherein the first switch is connected between the first AC input line and the first DC voltage bus and the second switch is connected between the first AC input line and the second DC voltage bus; h) a second half-bridge circuit comprising a third switch and a fourth switch, wherein the third switch is connected between the first AC output line and the first DC voltage bus and the fourth switch is connected between the first AC output line and the second DC voltage bus; i) a third half-bridge circuit comprising a fifth switch and a sixth switch, wherein the fifth switch is connected between the neutral line and the first DC voltage bus and the sixth switch is connected between the neutral line and the second DC voltage bus; j) a series of controllers provided to command the switches (301a...303b), wherein said series of controllers is provided to command at least the first to fourth switches (301a...302b) using pulse width modulation to convert V L,in into two different, substantially continuous voltages +V b, -V b at the first and the second DC voltage busses (311,312) and said two different, substantially continuous voltages +V b, -V b into a cyclical voltage V L, out at the first AC output line; k) a third inductance connected between said neutral line and said fifth and sixth switches (303a, 303b); said second AC output line being directly connected to said neutral line; said series of controllers being provided to synchronize said first and second half-bridge circuits (301, 302) so that V L,in and V L,out have substantially the same phase and frequency, and said series of controllers being also provided to open the fifth switch and close the sixth switch for a period t 1 of at least 50%, and preferably at least 95%, of a first half of a cycle of V L,in and close the fifth switch and open the sixth switch for a period t 2 of at least 50%, and preferably at least 95%, of a second half of the cycle of V L,in. a) a first AC input line comprising a first inductance and provided to be connected to an AC power supply with a cyclical voltage V L,in; b) a first AC output line comprising a second inductance and provided to be connected to a critical load; c) a second AC output line provided to be connected to the critical load; d) a neutral line provided to be connected to a neutral port; e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply; f) a single capacitor directly interposed between the first and second DC voltage busses (311,312); g) a first half-bridge circuit comprising a first switch and a second switch, wherein the first switch is connected between the first AC input line and the first DC voltage bus and the second switch is connected between the first AC input line and the second DC voltage bus; h) a second half-bridge circuit comprising a third switch and a fourth switch, wherein the third switch is connected between the first AC output line and the first DC voltage bus and the fourth switch is connected between the first AC output line and the second DC voltage bus; i) a third half-bridge circuit comprising a fifth switch and a sixth switch, wherein the fifth switch is connected between the neutral line and the first DC voltage bus and the sixth switch is connected between the neutral line and the second DC voltage bus; j) a series of controllers provided to command the switches (301a...303b), wherein said series of controllers is provided to command at least the first to fourth switches (301a...302b) using pulse width modulation to convert V L,in into two different, substantially continuous voltages +V b, -V b at the first and the second DC voltage busses (311,312) and said two different, substantially continuous voltages +V b, -V b into a cyclical voltage V L, out at the first AC output line; k) a third inductance connected between said neutral line and said fifth and sixth switches (303a, 303b);