A metrology system comprising: a processor; a wafer scanning device connected to the processor; memory connected to the processor; and computer executable program code configured to execute on the processor, wherein the computer executable program code configures the processor to: scan one or more training wafers to determine one or more error correlated parameters of the training wafers, the one or more error correlated parameters comprising at least one of a wafer shape, a wafer flatness, a chip layout, a film stack thickness and a lithography scanner settings; produce one or more training wafer profiles corresponding to the one or more error correlated parameters of one or more training wafers; determine that the training wafer profiles represent heterogeneous error correlated parameters; organize the training wafer profiles into homogeneous error correlated parameters; apply a plurality of overlay error predictive models to the training wafer profiles to produce corresponding predicted overlay error profiles, wherein applying the plurality of overlay error predictive models comprises executing a neural network based on the one or more error correlated parameters; scan the one or more training wafer to determine one or more training wafer error profiles error profiles; compare the training wafer error profiles to the plurality of predicted overlay error profiles to determine a best fit overlay error predictive model from the plurality of overlay error predictive models; and determine a correction to a lithographic overlay process based on the best fit overlay error predictive model. a processor; a wafer scanning device connected to the processor; memory connected to the processor; and computer executable program code configured to execute on the processor, wherein the computer executable program code configures the processor to: scan one or more training wafers to determine one or more error correlated parameters of the training wafers, the one or more error correlated parameters comprising at least one of a wafer shape, a wafer flatness, a chip layout, a film stack thickness and a lithography scanner settings; produce one or more training wafer profiles corresponding to the one or more error correlated parameters of one or more training wafers; determine that the training wafer profiles represent heterogeneous error correlated parameters; organize the training wafer profiles into homogeneous error correlated parameters; apply a plurality of overlay error predictive models to the training wafer profiles to produce corresponding predicted overlay error profiles, wherein applying the plurality of overlay error predictive models comprises executing a neural network based on the one or more error correlated parameters; scan the one or more training wafer to determine one or more training wafer error profiles error profiles; compare the training wafer error profiles to the plurality of predicted overlay error profiles to determine a best fit overlay error predictive model from the plurality of overlay error predictive models; and determine a correction to a lithographic overlay process based on the best fit overlay error predictive model. scan one or more training wafers to determine one or more error correlated parameters of the training wafers, the one or more error correlated parameters comprising at least one of a wafer shape, a wafer flatness, a chip layout, a film stack thickness and a lithography scanner settings; produce one or more training wafer profiles corresponding to the one or more error correlated parameters of one or more training wafers; determine that the training wafer profiles represent heterogeneous error correlated parameters; organize the training wafer profiles into homogeneous error correlated parameters; apply a plurality of overlay error predictive models to the training wafer profiles to produce corresponding predicted overlay error profiles, wherein applying the plurality of overlay error predictive models comprises executing a neural network based on the one or more error correlated parameters; scan the one or more training wafer to determine one or more training wafer error profiles error profiles; compare the training wafer error profiles to the plurality of predicted overlay error profiles to determine a best fit overlay error predictive model from the plurality of overlay error predictive models; and determine a correction to a lithographic overlay process based on the best fit overlay error predictive model.