An amplifying circuit for amplifying an input signal input from an input terminal and outputting the signal from an output terminal, the circuit comprising: a first PNP transistor, a second NPN transistor, a third NPN transistor and a fourth PNP transistor provided in an input stage; and a first bias circuit, wherein the input signal is input into a base terminal of the first PNP transistor and a base terminal of the second NPN transistor, an emitter terminal of the first PNP transistor is connected to an emitter terminal of the third NPN transistor, an emitter terminal of the second NPN transistor is connected to an emitter terminal of the fourth PNP transistor, a collector terminal of the first PNP transistor and a collector terminal of the second NPN transistor are connected and grounded to ground potential, a collector terminal of the third NPN transistor is connected to a potential of a first constant power source, a collector terminal of the fourth PNP transistor is connected to a potential of a second constant power source, the first bias circuit is connected between a base terminal of the third NPN transistor and a base terminal of the fourth PNP transistor, the first bias circuit includes an NPN biasing transistor, a PNP biasing transistor, characterised in that the first bias circuit further includes a first biasing resistor, a second biasing resistor, a third biasing resistor and a fourth biasing resistor, wherein an emitter of the NPN biasing transistor is connected to a reference terminal (Vre) corresponding to the ground potential, wherein the first resistor is provided between the collector and a base of the NPN biasing transistor, wherein an emitter of the PNP biasing transistor is connected to the reference terminal (Vre), wherein the second resistor is provided between the collector and a base of the PNP biasing transistor, wherein the third and fourth resistors (R26, R27) are connected in series between the bases of the NPN biasing transistor and the PNP biasing transistor, and wherein the NPN biasing transistor and the PNP biasing transistor are thermally bonded to the first PNP transistor, the second NPN transistor, the third NPN transistor and the fourth PNP transistor for compensating temperature changes of the first PNP transistor, the second NPN transistor, the third NPN transistor and the fourth PNP transistor. a first PNP transistor, a second NPN transistor, a third NPN transistor and a fourth PNP transistor provided in an input stage; and a first bias circuit, wherein the input signal is input into a base terminal of the first PNP transistor and a base terminal of the second NPN transistor, an emitter terminal of the first PNP transistor is connected to an emitter terminal of the third NPN transistor, an emitter terminal of the second NPN transistor is connected to an emitter terminal of the fourth PNP transistor, a collector terminal of the first PNP transistor and a collector terminal of the second NPN transistor are connected and grounded to ground potential, a collector terminal of the third NPN transistor is connected to a potential of a first constant power source, a collector terminal of the fourth PNP transistor is connected to a potential of a second constant power source, the first bias circuit is connected between a base terminal of the third NPN transistor and a base terminal of the fourth PNP transistor, the first bias circuit includes an NPN biasing transistor, a PNP biasing transistor, characterised in that the first bias circuit further includes a first biasing resistor, a second biasing resistor, a third biasing resistor and a fourth biasing resistor, wherein an emitter of the NPN biasing transistor is connected to a reference terminal (Vre) corresponding to the ground potential, wherein the first resistor is provided between the collector and a base of the NPN biasing transistor, wherein an emitter of the PNP biasing transistor is connected to the reference terminal (Vre), wherein the second resistor is provided between the collector and a base of the PNP biasing transistor, wherein the third and fourth resistors (R26, R27) are connected in series between the bases of the NPN biasing transistor and the PNP biasing transistor, and wherein the NPN biasing transistor and the PNP biasing transistor are thermally bonded to the first PNP transistor, the second NPN transistor, the third NPN transistor and the fourth PNP transistor for compensating temperature changes of the first PNP transistor, the second NPN transistor, the third NPN transistor and the fourth PNP transistor.