A digital CMOS circuit (20, 30, 40, 50, 60, 70, 80, 90, 110) comprising: at least one pull-up circuit (21, 31, 41, 51, 61, 71, 81, 91, 111) comprising at least one transistor of a first type, which is operable between an on-state and an off-state based on a predetermined voltage level supplied to a gate terminal of the at least one first type transistor, wherein the at least one pull-up circuit (21, 31, 41, 51, 61, 71, 81, 91, 111) is arranged when the at least one first type transistor is in the on-state to switch an output node of the digital CMOS circuit (20, 30, 40, 50, 60, 70, 80, 90, 110) from a first voltage level to a second voltage level within a rising transition delay; at least one pull-down circuit (22, 32, 42, 52, 62, 72, 82, 92, 112) comprising at least one transistor of a second type different from the first type, which is operable between an on-state and an off-state based on a predetermined voltage level supplied to a gate terminal of the at least one second type transistor, wherein the at least one pull-down circuit (22, 32, 42, 52, 62, 72, 82, 92, 112) is arranged when the at least one second type transistor is in the on-state to switch the voltage level of the output node of the digital CMOS circuit (20, 30, 40, 50, 60, 70, 80, 90, 110) from the second voltage level to the first voltage level within a falling transition delay; and wherein the first and second types are either P-type or N-type; and wherein the first and second type transistors have drain-source paths which are serially connected to each other, with an output node of the digital circuit being provided between the at least one pull-up circuit and the at least one pull-down circuit; characterised in that the digital CMOS circuit (20, 30, 40, 50, 60, 70, 80, 90, 110) comprises: at least one performance matching transistor (23, 33, 43, 53, 63, 73, 83, 93, 113) being either at least one transistor of the first type provided in the at least one pull-down circuit and having a drain-source path serially connected between that of the second type transistors and the output node, or at least one transistor of the second type provided in the at least one pull-up circuit and having a drain-source path serially connected between that of the first type transistors and the output node; and a biasing means connected to a gate terminal of each of the at least one performance matching transistor and arranged for supplying a predetermined voltage to the gate terminal for biasing the at least one performance matching transistor (23, 33, 43, 53, 63, 73, 83, 93, 113) such that the at least one performance matching transistor compensates effects of process variation and causes the at least one pull-up circuit and the at least one pull-down circuit to experience a same process skew. at least one pull-up circuit (21, 31, 41, 51, 61, 71, 81, 91, 111) comprising at least one transistor of a first type, which is operable between an on-state and an off-state based on a predetermined voltage level supplied to a gate terminal of the at least one first type transistor, wherein the at least one pull-up circuit (21, 31, 41, 51, 61, 71, 81, 91, 111) is arranged when the at least one first type transistor is in the on-state to switch an output node of the digital CMOS circuit (20, 30, 40, 50, 60, 70, 80, 90, 110) from a first voltage level to a second voltage level within a rising transition delay; at least one pull-down circuit (22, 32, 42, 52, 62, 72, 82, 92, 112) comprising at least one transistor of a second type different from the first type, which is operable between an on-state and an off-state based on a predetermined voltage level supplied to a gate terminal of the at least one second type transistor, wherein the at least one pull-down circuit (22, 32, 42, 52, 62, 72, 82, 92, 112) is arranged when the at least one second type transistor is in the on-state to switch the voltage level of the output node of the digital CMOS circuit (20, 30, 40, 50, 60, 70, 80, 90, 110) from the second voltage level to the first voltage level within a falling transition delay; and wherein the first and second types are either P-type or N-type; and wherein the first and second type transistors have drain-source paths which are serially connected to each other, with an output node of the digital circuit being provided between the at least one pull-up circuit and the at least one pull-down circuit; at least one performance matching transistor (23, 33, 43, 53, 63, 73, 83, 93, 113) being either at least one transistor of the first type provided in the at least one pull-down circuit and having a drain-source path serially connected between that of the second type transistors and the output node, or at least one transistor of the second type provided in the at least one pull-up circuit and having a drain-source path serially connected between that of the first type transistors and the output node; and a biasing means connected to a gate terminal of each of the at least one performance matching transistor and arranged for supplying a predetermined voltage to the gate terminal for biasing the at least one performance matching transistor (23, 33, 43, 53, 63, 73, 83, 93, 113) such that the at least one performance matching transistor compensates effects of process variation and causes the at least one pull-up circuit and the at least one pull-down circuit to experience a same process skew.