A level shift regulator circuit, comprising: - a first terminal to apply a supply potential (Vdd) and a second terminal to apply a ground potential, - a current source to provide a constant current, connected between the first terminal and an input node, - a level shift transistor (Mls) having its drain connected to the input node and having its gate connected to a reference voltage (Vref), - an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) having its source connected to the second terminal, - a current splitter to split the current of the current source at the input node, wherein the current splitter is connected to the gate connection of the output transistor (Mreg), - a current mirror, wherein the current mirror is coupled to the gate connection of the output transistor (Mreg), - another current source being arranged between the gate connection of the output transistor (Mreg) and the second terminal, - wherein the current splitter comprises a first transistor (Mfold) and a second transistor (Mfold_2), - wherein the drain connection of the first transistor (Mfold) of the current splitter is connected to the gate connection of the output transistor (Mreg), - wherein the current mirror comprises a first transistor and a second transistor, - wherein the drain connection of the second transistor (Mfold_2) of the current splitter is connected to the gate terminal of the first and second transistor (MT1, MT2) of the current mirror, - wherein the drain connection of the first transistor of the current mirror is connected to the gate connection of the output transistor (Mreg). - a first terminal to apply a supply potential (Vdd) and a second terminal to apply a ground potential, - a current source to provide a constant current, connected between the first terminal and an input node, - a level shift transistor (Mls) having its drain connected to the input node and having its gate connected to a reference voltage (Vref), - an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) having its source connected to the second terminal, - a current splitter to split the current of the current source at the input node, wherein the current splitter is connected to the gate connection of the output transistor (Mreg), - a current mirror, wherein the current mirror is coupled to the gate connection of the output transistor (Mreg), - another current source being arranged between the gate connection of the output transistor (Mreg) and the second terminal, - wherein the current splitter comprises a first transistor (Mfold) and a second transistor (Mfold_2), - wherein the drain connection of the first transistor (Mfold) of the current splitter is connected to the gate connection of the output transistor (Mreg), - wherein the current mirror comprises a first transistor and a second transistor, - wherein the drain connection of the second transistor (Mfold_2) of the current splitter is connected to the gate terminal of the first and second transistor (MT1, MT2) of the current mirror, - wherein the drain connection of the first transistor of the current mirror is connected to the gate connection of the output transistor (Mreg).