A manufacturing method for a capacitor, comprising: etching a semiconductor substrate to form at least one trench in the semiconductor substrate, wherein the trench is formed downward from an upper surface of the semiconductor substrate, and a depth of the trench is less than or equal to a thickness of the semiconductor substrate; depositing a first insulating layer on the upper surface of the semiconductor substrate and an inner surface of the at least one trench; depositing a first conductive layer on an upper surface and an inner surface of the first insulating layer; performing photolithography processing on the first insulating layer and the first conductive layer to expose the upper surface of the semiconductor substrate; depositing a second insulating layer on an upper surface and an inner surface of the first conductive layer and the upper surface of the semiconductor substrate; depositing a third conductive layer on an upper surface and an inner surface of the second insulating layer; performing photolithography processing on the second insulating layer and the third conductive layer to expose the upper surfaces of the semiconductor substrate and the first conductive layer; depositing a third insulating layer on an upper surface and an inner surface of the third conductive layer and the upper surface of the semiconductor substrate; performing photolithography processing on the third insulating layer to expose the upper surfaces of the semiconductor substrate and the third conductive layer, and forming at least one window on the third insulating layer to expose the upper surface of the first conductive layer; depositing a second conductive layer on an upper surface and an inner surface of the third insulating layer, the upper surface of the third conductive layer and the upper surface of the semiconductor substrate, and in the at least one window; and performing photolithography processing on the second conductive layer to form a first conductive region and a second conductive region that are independent from each other, wherein the first conductive region is electrically connected to the semiconductor substrate, the first conductive region is further electrically connected to the third conductive layer, and the second conductive region is electrically connected to the first conductive layer; wherein the first conductive region is configured as a first electrode of the capacitor, and the second conductive region is configured as a second electrode of the capacitor; and wherein projected areas of the first insulating layer and the first conductive layer on the semiconductor substrate are the same, and a projected area of the second insulating layer on the semiconductor substrate is larger than the projected area of the first conductive layer on the semiconductor substrate. etching a semiconductor substrate to form at least one trench in the semiconductor substrate, wherein the trench is formed downward from an upper surface of the semiconductor substrate, and a depth of the trench is less than or equal to a thickness of the semiconductor substrate; depositing a first insulating layer on the upper surface of the semiconductor substrate and an inner surface of the at least one trench; depositing a first conductive layer on an upper surface and an inner surface of the first insulating layer; performing photolithography processing on the first insulating layer and the first conductive layer to expose the upper surface of the semiconductor substrate; depositing a second insulating layer on an upper surface and an inner surface of the first conductive layer and the upper surface of the semiconductor substrate; depositing a third conductive layer on an upper surface and an inner surface of the second insulating layer; performing photolithography processing on the second insulating layer and the third conductive layer to expose the upper surfaces of the semiconductor substrate and the first conductive layer; depositing a third insulating layer on an upper surface and an inner surface of the third conductive layer and the upper surface of the semiconductor substrate; performing photolithography processing on the third insulating layer to expose the upper surfaces of the semiconductor substrate and the third conductive layer, and forming at least one window on the third insulating layer to expose the upper surface of the first conductive layer; depositing a second conductive layer on an upper surface and an inner surface of the third insulating layer, the upper surface of the third conductive layer and the upper surface of the semiconductor substrate, and in the at least one window; and performing photolithography processing on the second conductive layer to form a first conductive region and a second conductive region that are independent from each other, wherein the first conductive region is electrically connected to the semiconductor substrate, the first conductive region is further electrically connected to the third conductive layer, and the second conductive region is electrically connected to the first conductive layer; wherein the first conductive region is configured as a first electrode of the capacitor, and the second conductive region is configured as a second electrode of the capacitor; and wherein projected areas of the first insulating layer and the first conductive layer on the semiconductor substrate are the same, and a projected area of the second insulating layer on the semiconductor substrate is larger than the projected area of the first conductive layer on the semiconductor substrate.