A method for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the guest operating system, the computer system further comprising one or more bus connected modules being operationally connected with the plurality of processors via a bus and a bus attachment device the computer system further comprising a memory operationally connected with the bus attachment device, each processor of the plurality of processors being assigned with a logical processor ID used by the bus attachment device to identify and address the respective processor, each processor of the plurality of processors assigned for usage by the guest operating system further being assigned with an interrupt target ID used by the guest operating system and the one or more bus connected modules to address the respective processor, the method comprising: receiving by the bus attachment device an interrupt signal from one of the bus connected modules, the interrupt signal including an interrupt target ID, the interrupt target ID identifying one of the processors assigned for usage by the guest operating system as a target processor for handling the interrupt signal, retrieving by the bus attachment device a first copy of an interrupt table entry assigned to the received interrupt target ID from an interrupt table stored in the memory, the first copy of the interrupt table entry comprising a first mapping of the received interrupt target ID assigned to the target processor to a logical processor ID of the target processor, translating by the bus attachment device the received interrupt target ID assigned to the target processor to the logical processor ID of the target processor using the first copy of the interrupt table entry, forwarding by the bus attachment device the interrupt signal to the target processor for handling using the logical processor ID resulting from the translation to address the target processor directly. each processor of the plurality of processors being assigned with a logical processor ID used by the bus attachment device to identify and address the respective processor, each processor of the plurality of processors assigned for usage by the guest operating system further being assigned with an interrupt target ID used by the guest operating system and the one or more bus connected modules to address the respective processor, the method comprising: receiving by the bus attachment device an interrupt signal from one of the bus connected modules, the interrupt signal including an interrupt target ID, the interrupt target ID identifying one of the processors assigned for usage by the guest operating system as a target processor for handling the interrupt signal, retrieving by the bus attachment device a first copy of an interrupt table entry assigned to the received interrupt target ID from an interrupt table stored in the memory, the first copy of the interrupt table entry comprising a first mapping of the received interrupt target ID assigned to the target processor to a logical processor ID of the target processor, translating by the bus attachment device the received interrupt target ID assigned to the target processor to the logical processor ID of the target processor using the first copy of the interrupt table entry, forwarding by the bus attachment device the interrupt signal to the target processor for handling using the logical processor ID resulting from the translation to address the target processor directly. receiving by the bus attachment device an interrupt signal from one of the bus connected modules, the interrupt signal including an interrupt target ID, the interrupt target ID identifying one of the processors assigned for usage by the guest operating system as a target processor for handling the interrupt signal, retrieving by the bus attachment device a first copy of an interrupt table entry assigned to the received interrupt target ID from an interrupt table stored in the memory, the first copy of the interrupt table entry comprising a first mapping of the received interrupt target ID assigned to the target processor to a logical processor ID of the target processor, translating by the bus attachment device the received interrupt target ID assigned to the target processor to the logical processor ID of the target processor using the first copy of the interrupt table entry, forwarding by the bus attachment device the interrupt signal to the target processor for handling using the logical processor ID resulting from the translation to address the target processor directly.