A method of testing linearity of an analog-to-digital converter ADC, comprising: receiving a trigger signal indicating an ADC input voltage step increment adjustment; reading an ADC output sample upon receiving the trigger signal, wherein the ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes; computing and storing a histogram of code occurrences for M consecutive ADC output codes, wherein the histogram includes M number of bins corresponding to the M consecutive ADC output codes, and wherein M is less than N; updating a maximum code occurrences, a minimum code occurrences, a differential non-linearity DNL value and an integral non-linearity INL value according to the histogram at an interval of K number of ADC output sample readings, wherein the interval of K number of ADC output sample readings corresponds to an average number of occurrences for each of the N ADC output codes; and shifting the histogram by one ADC output code after updating the maximum code occurrences, the minimum code occurrences, the DNL and the INL values; wherein updating the DNL value includes: comparing a bin value of a lowest histogram bin to the minimum code occurrences and the maximum code occurrences, wherein the bin value is a number of code occurrences for a current ADC output code that corresponds to the lowest histogram bin; setting the minimum code occurrences to the bin value when the bin value is less than the minimum code occurrences; setting a minimum DNL ADC code to the current ADC output code when the bin value is less than the minimum code occurrences; setting the maximum code occurrences to the bin value when the bin value is greater than the maximum code occurrences; and setting a maximum DNL ADC code to the current ADC output code when the bin value is greater than the maximum code occurrences. receiving a trigger signal indicating an ADC input voltage step increment adjustment; reading an ADC output sample upon receiving the trigger signal, wherein the ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes; computing and storing a histogram of code occurrences for M consecutive ADC output codes, wherein the histogram includes M number of bins corresponding to the M consecutive ADC output codes, and wherein M is less than N; updating a maximum code occurrences, a minimum code occurrences, a differential non-linearity DNL value and an integral non-linearity INL value according to the histogram at an interval of K number of ADC output sample readings, wherein the interval of K number of ADC output sample readings corresponds to an average number of occurrences for each of the N ADC output codes; and shifting the histogram by one ADC output code after updating the maximum code occurrences, the minimum code occurrences, the DNL and the INL values; wherein updating the DNL value includes: comparing a bin value of a lowest histogram bin to the minimum code occurrences and the maximum code occurrences, wherein the bin value is a number of code occurrences for a current ADC output code that corresponds to the lowest histogram bin; setting the minimum code occurrences to the bin value when the bin value is less than the minimum code occurrences; setting a minimum DNL ADC code to the current ADC output code when the bin value is less than the minimum code occurrences; setting the maximum code occurrences to the bin value when the bin value is greater than the maximum code occurrences; and setting a maximum DNL ADC code to the current ADC output code when the bin value is greater than the maximum code occurrences. comparing a bin value of a lowest histogram bin to the minimum code occurrences and the maximum code occurrences, wherein the bin value is a number of code occurrences for a current ADC output code that corresponds to the lowest histogram bin; setting the minimum code occurrences to the bin value when the bin value is less than the minimum code occurrences; setting a minimum DNL ADC code to the current ADC output code when the bin value is less than the minimum code occurrences; setting the maximum code occurrences to the bin value when the bin value is greater than the maximum code occurrences; and setting a maximum DNL ADC code to the current ADC output code when the bin value is greater than the maximum code occurrences.