A semiconductor device (1A-1I, 9) comprising: a First In First Out (FIFO) (91, 101); a test data write circuit (92, 100, 102) that sequentially writes a plurality of test data to the FIFO (91, 101) in synchronization with a first clock signal (110, 910); and a test control circuit (93, 200, 300) that, in parallel with writing of the plurality of test data to the FIFO (91, 101) by the test data write circuit (92, 100, 102), sequentially reads a plurality of test data stored in the FIFO (91, 101) in synchronization with a second clock signal (210, 920), which is not synchronous with the first clock signal (110, 910), and performs a scan test of a circuit to be tested (94, 201, 301), characterized in that: the circuit to be tested (94, 201, 301) has a scan chain for performing the scan test, and performs a scan shift operation in synchronization with the second clock signal (210, 920) and thereby reads test data from the FIFO (91, 101) and scans the test data into the scan chain, and scans out test result data stored in the scan chain, the test data write circuit (92, 100, 102) sequentially writes the plurality of test data and a plurality of mask data respectively corresponding to the plurality of test data to the FIFO (91, 101) in synchronization with the first clock signal (110, 910), the semiconductor device (1A-1I, 9) further includes a test result processing circuit to which the test result data scanned out of the scan chain is input, and the test result processing circuit includes a mask circuit (2021, 2022) that, when the test data is scanned into the scan chain, reads mask data corresponding to the test data from the FIFO (91, 101), and masks, by the read mask data, the test result data to be scanned out when the test data is scanned into the scan chain, and thereby fixes a value of the test result data to a Low value or a High value. a First In First Out (FIFO) (91, 101); a test data write circuit (92, 100, 102) that sequentially writes a plurality of test data to the FIFO (91, 101) in synchronization with a first clock signal (110, 910); and a test control circuit (93, 200, 300) that, in parallel with writing of the plurality of test data to the FIFO (91, 101) by the test data write circuit (92, 100, 102), sequentially reads a plurality of test data stored in the FIFO (91, 101) in synchronization with a second clock signal (210, 920), which is not synchronous with the first clock signal (110, 910), and performs a scan test of a circuit to be tested (94, 201, 301), characterized in that: the circuit to be tested (94, 201, 301) has a scan chain for performing the scan test, and performs a scan shift operation in synchronization with the second clock signal (210, 920) and thereby reads test data from the FIFO (91, 101) and scans the test data into the scan chain, and scans out test result data stored in the scan chain, the test data write circuit (92, 100, 102) sequentially writes the plurality of test data and a plurality of mask data respectively corresponding to the plurality of test data to the FIFO (91, 101) in synchronization with the first clock signal (110, 910), the semiconductor device (1A-1I, 9) further includes a test result processing circuit to which the test result data scanned out of the scan chain is input, and the test result processing circuit includes a mask circuit (2021, 2022) that, when the test data is scanned into the scan chain, reads mask data corresponding to the test data from the FIFO (91, 101), and masks, by the read mask data, the test result data to be scanned out when the test data is scanned into the scan chain, and thereby fixes a value of the test result data to a Low value or a High value. the circuit to be tested (94, 201, 301) has a scan chain for performing the scan test, and performs a scan shift operation in synchronization with the second clock signal (210, 920) and thereby reads test data from the FIFO (91, 101) and scans the test data into the scan chain, and scans out test result data stored in the scan chain, the test data write circuit (92, 100, 102) sequentially writes the plurality of test data and a plurality of mask data respectively corresponding to the plurality of test data to the FIFO (91, 101) in synchronization with the first clock signal (110, 910), the semiconductor device (1A-1I, 9) further includes a test result processing circuit to which the test result data scanned out of the scan chain is input, and the test result processing circuit includes a mask circuit (2021, 2022) that, when the test data is scanned into the scan chain, reads mask data corresponding to the test data from the FIFO (91, 101), and masks, by the read mask data, the test result data to be scanned out when the test data is scanned into the scan chain, and thereby fixes a value of the test result data to a Low value or a High value.