A memory device, comprising: a semiconductor substrate having a memory area and a logic device area, wherein an upper surface of the substrate in the memory area is recessed lower than an upper surface of the substrate in the logic device area; a plurality of memory cells formed in the memory area of the substrate, wherein each of the memory cells includes: a first source region formed in the substrate, a first drain region formed in the substrate, wherein a first channel region is defined in the substrate between the first source region and the first drain region, a floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the first source region, a control gate disposed over and insulated from the floating gate, a select gate disposed over and insulated from a second portion of the first channel region that is adjacent to the drain region, and an erase gate disposed over and insulated from the first source region; a plurality of logic devices formed in the logic device area of the substrate, wherein each of the logic devices includes: a second source region formed in the substrate, a second drain region formed in the substrate, wherein a second channel region is defined in the substrate between the second source region and the second drain region, and a logic gate disposed over and insulated from the second channel region; a layer of silicide on an upper surface of each of the erase gates; a layer of silicide on portions of the substrate surface over the first drain regions; and a layer of silicide on portions of the substrate surface over the second source regions and the second drain regions; wherein: the floating gates, the erase gates and the control gates are formed of polysilicon, the select gates and the logic gates are formed entirely of a metal material, the select gates are insulated from the substrate by at least a layer of silicon dioxide and a layer of high K material having a dielectric constant greater than that of silicon dioxide. a semiconductor substrate having a memory area and a logic device area, wherein an upper surface of the substrate in the memory area is recessed lower than an upper surface of the substrate in the logic device area; a plurality of memory cells formed in the memory area of the substrate, wherein each of the memory cells includes: a first source region formed in the substrate, a first drain region formed in the substrate, wherein a first channel region is defined in the substrate between the first source region and the first drain region, a floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the first source region, a control gate disposed over and insulated from the floating gate, a select gate disposed over and insulated from a second portion of the first channel region that is adjacent to the drain region, and an erase gate disposed over and insulated from the first source region; a first source region formed in the substrate, a first drain region formed in the substrate, wherein a first channel region is defined in the substrate between the first source region and the first drain region, a floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the first source region, a control gate disposed over and insulated from the floating gate, a select gate disposed over and insulated from a second portion of the first channel region that is adjacent to the drain region, and an erase gate disposed over and insulated from the first source region; a plurality of logic devices formed in the logic device area of the substrate, wherein each of the logic devices includes: a second source region formed in the substrate, a second drain region formed in the substrate, wherein a second channel region is defined in the substrate between the second source region and the second drain region, and a logic gate disposed over and insulated from the second channel region; a second source region formed in the substrate, a second drain region formed in the substrate, wherein a second channel region is defined in the substrate between the second source region and the second drain region, and a layer of silicide on an upper surface of each of the erase gates; a layer of silicide on portions of the substrate surface over the first drain regions; and a layer of silicide on portions of the substrate surface over the second source regions and the second drain regions; wherein: the floating gates, the erase gates and the control gates are formed of polysilicon, the select gates and the logic gates are formed entirely of a metal material, the select gates are insulated from the substrate by at least a layer of silicon dioxide and a layer of high K material having a dielectric constant greater than that of silicon dioxide. the floating gates, the erase gates and the control gates are formed of polysilicon, the select gates and the logic gates are formed entirely of a metal material, the select gates are insulated from the substrate by at least a layer of silicon dioxide and a layer of high K material having a dielectric constant greater than that of silicon dioxide.