A memory control device comprising: a CPU; an electrically-rewritable non-volatile memory that records therein first information having undergone an error-correction coding process and second information not having undergone an error-correction coding process; a first switch that detects an address output from the CPU, and switches between a first path that connects an address bus to the memory so that the CPU can read first information recorded in the memory and a second path that connects the address bus to the memory so that the second information recorded in the memory can be erased, written, and read; a decoder that performs error correction on the first information recorded in the memory, removes a redundant bit from corrected information, and decodes information before undergoing an error-correction coding process; and a second switch that detects an address output from the CPU, and switches between a third path that connects the decoder to a data bus so that information decoded by the decoder is transmitted to the data bus of the CPU and a fourth path that connects the memory to the data bus so that the second information recorded in the memory can be erased, written, and read, wherein when an address output from the CPU is a first address indicating that the first information is to be read, the first switch detects the first address and connects the address bus to the memory by the first path and the second switch detects the first address and connects the decoder to the data bus by the third path, and when an address output from the CPU is a second address indicating that the second information is to be erased, written, and read, the first switch detects the second address and connects the address bus to the memory by the second path and the second switch detects the second address and connects the decoder to the data bus by the fourth path. a CPU; an electrically-rewritable non-volatile memory that records therein first information having undergone an error-correction coding process and second information not having undergone an error-correction coding process; a first switch that detects an address output from the CPU, and switches between a first path that connects an address bus to the memory so that the CPU can read first information recorded in the memory and a second path that connects the address bus to the memory so that the second information recorded in the memory can be erased, written, and read; a decoder that performs error correction on the first information recorded in the memory, removes a redundant bit from corrected information, and decodes information before undergoing an error-correction coding process; and a second switch that detects an address output from the CPU, and switches between a third path that connects the decoder to a data bus so that information decoded by the decoder is transmitted to the data bus of the CPU and a fourth path that connects the memory to the data bus so that the second information recorded in the memory can be erased, written, and read, wherein when an address output from the CPU is a first address indicating that the first information is to be read, the first switch detects the first address and connects the address bus to the memory by the first path and the second switch detects the first address and connects the decoder to the data bus by the third path, and when an address output from the CPU is a second address indicating that the second information is to be erased, written, and read, the first switch detects the second address and connects the address bus to the memory by the second path and the second switch detects the second address and connects the decoder to the data bus by the fourth path.