Apparatus for processing data comprising: processing circuitry (108, 112, 114, 116, 119) to perform processing operations specified by program instructions including at least one vector processing program instruction supporting processing of up to N max vector elements associated with respective vector processing lanes; an instruction decoder to decode said program instructions to generate control signals to control said processing circuitry to perform said processing operations; floating point registers to store floating point data values; and a floating point control register to store floating point control data and a value indicative of a vector element width VE width; when floating point data values are accessible to said program instructions, said floating point control register is also accessible; when said floating point data values are inaccessible to said program instructions, said floating point control register is also inaccessible; wherein said instruction decoder comprises predicated-loop instruction decoder circuitry to decode a predicated-loop instruction having associated therewith a number of vector elements N ve to be processed during a number of iterations of a program loop body to be performed, wherein in response to decoding of the predicated-loop instruction, the processing circuitry is configured to store a loop count value indicating the number of vector elements N ve, and at a finish of the program loop body for an iteration other than a final iteration of the loop, the processing circuitry is configured to decrement the loop count value by a number of vector elements determined based on a read value of VE width; said processing circuitry comprises predication loop control circuitry to operate, when N ve /N max does not equal a whole number, at least partially to suppress processing in one or more of said vector processing lanes during one of more of said iterations such that a total number of vector elements processed during said iterations is N ve; and when the floating point data values are inaccessible, an attempt to read VE width from the floating point control register returns VR width as the read value of VE width, where VR width is a number of bits in one vector register. processing circuitry (108, 112, 114, 116, 119) to perform processing operations specified by program instructions including at least one vector processing program instruction supporting processing of up to N max vector elements associated with respective vector processing lanes; an instruction decoder to decode said program instructions to generate control signals to control said processing circuitry to perform said processing operations; floating point registers to store floating point data values; and a floating point control register to store floating point control data and a value indicative of a vector element width VE width; when floating point data values are accessible to said program instructions, said floating point control register is also accessible; when said floating point data values are inaccessible to said program instructions, said floating point control register is also inaccessible; wherein when floating point data values are accessible to said program instructions, said floating point control register is also accessible; when said floating point data values are inaccessible to said program instructions, said floating point control register is also inaccessible; said instruction decoder comprises predicated-loop instruction decoder circuitry to decode a predicated-loop instruction having associated therewith a number of vector elements N ve to be processed during a number of iterations of a program loop body to be performed, wherein in response to decoding of the predicated-loop instruction, the processing circuitry is configured to store a loop count value indicating the number of vector elements N ve, and at a finish of the program loop body for an iteration other than a final iteration of the loop, the processing circuitry is configured to decrement the loop count value by a number of vector elements determined based on a read value of VE width; said processing circuitry comprises predication loop control circuitry to operate, when N ve /N max does not equal a whole number, at least partially to suppress processing in one or more of said vector processing lanes during one of more of said iterations such that a total number of vector elements processed during said iterations is N ve; and when the floating point data values are inaccessible, an attempt to read VE width from the floating point control register returns VR width as the read value of VE width, where VR width is a number of bits in one vector register.