Electrical converter for converting between an AC signal comprising three phase voltages and a galvanically isolated DC voltage, comprising: three phase terminals (A, B, C) and two DC terminals (P, N), a first converter stage comprising a conversion circuitry configured for converting between the three phase voltages at the three phase terminals and first voltages ( v T, v B) at a first intermediate node and a second intermediate node, and a phase selector comprising first active switches ( S S, a, S S,b, S S, c) configured to selectively connect the three phase terminals (A, B, C) to a third intermediate node, a second converter stage configured for converting between second signals at a fourth intermediate node (r) and a fifth intermediate node (s) and third signals at a sixth intermediate node (P') and a seventh intermediate node (N'), wherein the second converter stage comprises a boost circuit (19, 20) operably coupled to the sixth and seventh intermediate nodes (P', N'), a link connecting the first intermediate node to the fourth intermediate node, and the second intermediate node to the fifth intermediate node, and a third converter stage, comprising a galvanically isolated DC/DC converter stage (141, 142, 140) comprising a first side connected to the sixth intermediate node (P'), a first common node (t) and the seventh intermediate node (N'), wherein the DC terminals (P, N) are connected to a second side of the DC/DC converter stage galvanically isolated from the first side, wherein the first common node (t) is operably connected to the third intermediate node and wherein the DC/DC converter stage is configured to be operated such that a difference of a first current ( i P ') applied to the DC/DC converter stage at the sixth intermediate node (P') and a second current ( i N ') applied to the DC/DC converter stage at the seventh intermediate node (N') is provided at the third intermediate node, wherein the boost circuit comprises a first boost circuit and a second boost circuit stacked between the sixth and seventh intermediate nodes, wherein the first and second boost circuits have a second common node (m) being free from a direct link to the first common node (t) and the third intermediate node. three phase terminals (A, B, C) and two DC terminals (P, N), a first converter stage comprising a conversion circuitry configured for converting between the three phase voltages at the three phase terminals and first voltages ( v T, v B) at a first intermediate node and a second intermediate node, and a phase selector comprising first active switches ( S S, a, S S,b, S S, c) configured to selectively connect the three phase terminals (A, B, C) to a third intermediate node, a second converter stage configured for converting between second signals at a fourth intermediate node (r) and a fifth intermediate node (s) and third signals at a sixth intermediate node (P') and a seventh intermediate node (N'), wherein the second converter stage comprises a boost circuit (19, 20) operably coupled to the sixth and seventh intermediate nodes (P', N'), a link connecting the first intermediate node to the fourth intermediate node, and the second intermediate node to the fifth intermediate node, and a third converter stage, comprising a galvanically isolated DC/DC converter stage (141, 142, 140) comprising a first side connected to the sixth intermediate node (P'), a first common node (t) and the seventh intermediate node (N'), wherein the DC terminals (P, N) are connected to a second side of the DC/DC converter stage galvanically isolated from the first side, wherein the first common node (t) is operably connected to the third intermediate node and wherein the DC/DC converter stage is configured to be operated such that a difference of a first current ( i P ') applied to the DC/DC converter stage at the sixth intermediate node (P') and a second current ( i N ') applied to the DC/DC converter stage at the seventh intermediate node (N') is provided at the third intermediate node, wherein the boost circuit comprises a first boost circuit and a second boost circuit stacked between the sixth and seventh intermediate nodes, wherein the first and second boost circuits have a second common node (m) being free from a direct link to the first common node (t) and the third intermediate node.