An inter-CPU data transfer device for an electronic control apparatus, the electronic apparatus including a first CPU having a first memory for storing computation results and a second CPU having a second memory for storing computation results, said first CPU periodically performing a data-updating process to update a plurality data items stored in said first memory, said second CPU performing a data-referring process in which said plurality of said data items updated by said first CPU are referred to for computation purpose, said inter-CPU data transfer device comprising: a data transfer memory; and a controller, the controller being external to the first CPU and to the second CPU; wherein said controller includes: a first data transfer section activated in order to write said plurality of said data items written in said first memory to said data transfer memory when said first CPU starts said data updating process; a second data transfer section writing said plurality of said data items written in said data transfer memory to said second memory when said second data transfer section detects that said second CPU is not performing said data-referring process; said second CPU inhibiting interruption when said data-referring process is started and permitting interruption when said data-referring process is completed, and said second data transfer section monitoring whether or not said second CPU is in an interruption permitting state and judging that said second CPU is not performing said data-referring function when said second CPU is in said interruption permitting state. a data transfer memory; and a controller, the controller being external to the first CPU and to the second CPU; wherein said controller includes: a first data transfer section activated in order to write said plurality of said data items written in said first memory to said data transfer memory when said first CPU starts said data updating process; a second data transfer section writing said plurality of said data items written in said data transfer memory to said second memory when said second data transfer section detects that said second CPU is not performing said data-referring process; said second CPU inhibiting interruption when said data-referring process is started and permitting interruption when said data-referring process is completed, and said second data transfer section monitoring whether or not said second CPU is in an interruption permitting state and judging that said second CPU is not performing said data-referring function when said second CPU is in said interruption permitting state. a first data transfer section activated in order to write said plurality of said data items written in said first memory to said data transfer memory when said first CPU starts said data updating process; a second data transfer section writing said plurality of said data items written in said data transfer memory to said second memory when said second data transfer section detects that said second CPU is not performing said data-referring process; said second CPU inhibiting interruption when said data-referring process is started and permitting interruption when said data-referring process is completed, and said second data transfer section monitoring whether or not said second CPU is in an interruption permitting state and judging that said second CPU is not performing said data-referring function when said second CPU is in said interruption permitting state.