An inverter system, comprising a plurality of inverter modules connected in parallel, wherein: input terminals of all of the plurality of inverter modules are connected to a same direct current input bus, and output terminals of all of the plurality of inverter modules are connected to a same alternating current output bus; and an input contact S1 of the direct current input bus and an output contact S2 of the alternating current output bus are located in a manner that a difference between impedances of all branches between S1 and S2 is less than or equal to a preset value, each inverter module being included in a corresponding branch, and impedance values (R1, R2, R3, R4) of the direct current input bus and the alternating current output bus being defined between input terminals of the inverter modules and further between output terminals of the inverter modules, characterized in that each inverter module has an I-type three-level circuit topology comprising a first sub-module, a second sub-module and a third sub-module, wherein the first sub-module has a positive input terminal connected to a positive terminal of the direct current input bus, a negative input terminal connected to a neutral point of the direct current input bus, and an output terminal connected to a positive input terminal of the third sub-module, and the second sub-module has a positive input terminal connected to the neutral point of the direct current input bus, a negative input terminal connected to a negative terminal of the direct current input bus, and an output terminal connected to a negative input terminal of the third sub-module, wherein the inverter system further comprises a first circulation bus L1 and a second circulation bus L2, wherein the first circulation bus L1 is connected to the output terminal of each first sub-module, and the second circulation bus L2 is connected to the output terminal of each second sub-module, the first circulation bus L1 being configured to equalize the output potentials of all the first sub-modules and the second circulation bus L2 being configured to equalize the output potentials of all the second sub-modules, so that currents flowing through each third module are balanced. input terminals of all of the plurality of inverter modules are connected to a same direct current input bus, and output terminals of all of the plurality of inverter modules are connected to a same alternating current output bus; and an input contact S1 of the direct current input bus and an output contact S2 of the alternating current output bus are located in a manner that a difference between impedances of all branches between S1 and S2 is less than or equal to a preset value, each inverter module being included in a corresponding branch, and impedance values (R1, R2, R3, R4) of the direct current input bus and the alternating current output bus being defined between input terminals of the inverter modules and further between output terminals of the inverter modules, characterized in that each inverter module has an I-type three-level circuit topology comprising a first sub-module, a second sub-module and a third sub-module, wherein the first sub-module has a positive input terminal connected to a positive terminal of the direct current input bus, a negative input terminal connected to a neutral point of the direct current input bus, and an output terminal connected to a positive input terminal of the third sub-module, and the second sub-module has a positive input terminal connected to the neutral point of the direct current input bus, a negative input terminal connected to a negative terminal of the direct current input bus, and an output terminal connected to a negative input terminal of the third sub-module, wherein the inverter system further comprises a first circulation bus L1 and a second circulation bus L2, wherein the first circulation bus L1 is connected to the output terminal of each first sub-module, and the second circulation bus L2 is connected to the output terminal of each second sub-module, the first circulation bus L1 being configured to equalize the output potentials of all the first sub-modules and the second circulation bus L2 being configured to equalize the output potentials of all the second sub-modules, so that currents flowing through each third module are balanced.