A current-controlled CMOS, C3MOS, wideband variable delay cell circuit, the circuit comprising: a first differential transistor comprising a first source, a first gate, and a first drain; a second differential transistor comprising a second source, a second gate, and a second drain; a first current source ( I b) that is coupled to the first source of the first differential transistor and to the second source of the second differential transistor; a first input impedance that is coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor; a second input impedance that is coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor; a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, that is coupled between the first drain of the first differential transistor and a supply voltage (V cc); a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, that is coupled between the second drain of the second differential transistor and the supply voltage (V cc); a third differential transistor comprising a third source, a third gate, and a third drain; a fourth differential transistor comprising a fourth source, a fourth gate, and a fourth drain; a second current source ( I r) that is coupled to the third source of the third differential transistor and to the fourth source of the fourth differential transistor; wherein the second drain of the second differential transistor, the fourth drain of the fourth differential transistor, and the third gate of the third differential transistor are directly coupled to form a first differential output node OUTP of the C3MOS wideband variable delay cell circuit, wherein the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are directly coupled to form a second differential output node OUTN of the C3MOS wideband variable delay cell circuit, wherein the C3MOS wideband variable delay cell circuit is configured to reduce the current of the first current source while the current of the second current source is increased by the same amount to increase a variable delay of the C3MOS wideband variable delay cell circuit, wherein: the first input impedance comprises a first series inductor; and the second input impedance comprises a second series inductor. a first differential transistor comprising a first source, a first gate, and a first drain; a second differential transistor comprising a second source, a second gate, and a second drain; a first current source ( I b) that is coupled to the first source of the first differential transistor and to the second source of the second differential transistor; a first input impedance that is coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor; a second input impedance that is coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor; a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, that is coupled between the first drain of the first differential transistor and a supply voltage (V cc); a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, that is coupled between the second drain of the second differential transistor and the supply voltage (V cc); a third differential transistor comprising a third source, a third gate, and a third drain; a fourth differential transistor comprising a fourth source, a fourth gate, and a fourth drain; a second current source ( I r) that is coupled to the third source of the third differential transistor and to the fourth source of the fourth differential transistor; wherein the second drain of the second differential transistor, the fourth drain of the fourth differential transistor, and the third gate of the third differential transistor are directly coupled to form a first differential output node OUTP of the C3MOS wideband variable delay cell circuit, wherein the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are directly coupled to form a second differential output node OUTN of the C3MOS wideband variable delay cell circuit, wherein the C3MOS wideband variable delay cell circuit is configured to reduce the current of the first current source while the current of the second current source is increased by the same amount to increase a variable delay of the C3MOS wideband variable delay cell circuit, wherein: the first input impedance comprises a first series inductor; and the second input impedance comprises a second series inductor. the first input impedance comprises a first series inductor; and the second input impedance comprises a second series inductor.