A bus relaying device to relay interrupt information communicated between a CPU (Central Processing Unit) and an I/O (input/Output) device, an upper-order side of the bus relaying device being connected to either the CPU or another relaying device, a lower-order side of the bus relaying device being connected to, from among the I/O device and still another relaying device which is different from said another relaying device on the upper-order side, at least the I/O device, wherein the bus relaying device comprises: an interrupt notification receiving part to receive an interrupt notification from a lower-order-side port, and output a port number of the port, the interrupt notification having been sent by the I/O device; a first address memory part to store interrupt factor address information including a plurality of sets each having a port number and an interrupt factor address being an address to be used for reading an interrupt factor; an address selecting part to receive the port number outputted by the interrupt notification receiving part; acquire the interrupt factor address from the interrupt factor address information of the first address memory part based on the port number received; determine whether or not a device connected to a port of the port number received is the I/O device based on connection information held in advance; and when having determined that the device connected to the port is the I/O device, output the interrupt factor address acquired from the first address memory part; a lower-order-side transmitting part to transmit a factor read request for reading the interrupt factor, the factor read request including the interrupt factor address outputted by the address selecting part, to the I/O device connected to the port; a lower-order-side receiving part to receive the interrupt factor from the I/O device connected to the port, and output the interrupt factor received, the interrupt factor responding to the factor read request for the interrupt factor, the factor read request being transmitted by the lower-order-side transmitting part; and a second address memory part to store a plurality of sets each having an interrupt factor address, an interrupt factor, and a data read address being an address used for reading internal data of the I/O device; receive the interrupt factor address outputted by the address selecting part and the interrupt factor outputted by the lower-order-side receiving part; determine whether or not a set including the interrupt factor address received and the interrupt factor received exists among the plurality of sets stored; and when having determined that the set including the interrupt factor address received and the interrupt factor received exists, output the data read address included in the set, wherein the lower-order-side transmitting part creates a data read request requesting read of the internal data of the I/O device based on the data read address outputted by the second address memory part, and transmits the data read request created, to the I/O device connected to the port. an interrupt notification receiving part to receive an interrupt notification from a lower-order-side port, and output a port number of the port, the interrupt notification having been sent by the I/O device; a first address memory part to store interrupt factor address information including a plurality of sets each having a port number and an interrupt factor address being an address to be used for reading an interrupt factor; an address selecting part to receive the port number outputted by the interrupt notification receiving part; acquire the interrupt factor address from the interrupt factor address information of the first address memory part based on the port number received; determine whether or not a device connected to a port of the port number received is the I/O device based on connection information held in advance; and when having determined that the device connected to the port is the I/O device, output the interrupt factor address acquired from the first address memory part; a lower-order-side transmitting part to transmit a factor read request for reading the interrupt factor, the factor read request including the interrupt factor address outputted by the address selecting part, to the I/O device connected to the port; a lower-order-side receiving part to receive the interrupt factor from the I/O device connected to the port, and output the interrupt factor received, the interrupt factor responding to the factor read request for the interrupt factor, the factor read request being transmitted by the lower-order-side transmitting part; and a second address memory part to store a plurality of sets each having an interrupt factor address, an interrupt factor, and a data read address being an address used for reading internal data of the I/O device; receive the interrupt factor address outputted by the address selecting part and the interrupt factor outputted by the lower-order-side receiving part; determine whether or not a set including the interrupt factor address received and the interrupt factor received exists among the plurality of sets stored; and when having determined that the set including the interrupt factor address received and the interrupt factor received exists, output the data read address included in the set, wherein the lower-order-side transmitting part creates a data read request requesting read of the internal data of the I/O device based on the data read address outputted by the second address memory part, and transmits the data read request created, to the I/O device connected to the port.