An interconnect apparatus comprising: a clock generator configured to generate a clock signal; a phase shifter configured to phase shift the clock signal by a test phase; an error rate detector configured to measure an error rate of the test phase; and an operational phase selector configured to select an operational phase of the clock signal based at least in part on the error rate of the test phase, the interconnect apparatus further comprising an error comparator, wherein the test phase is a first test phase, and wherein: the phase shifter is further configured to shift the clock signal by a second test phase; the error rate detector is further configured to measure an error of the second test phase; and the error comparator is configured to compare the error rate of the first test phase to the error rate of the second test phase and to select an optimal test phase; and the operational phase selector is configured to select the operational phase of the clock signal based at least in part on the error rate of the first test phase by selecting the operational phase of the clock signal based at least in part on the optimal test phase, the interconnect apparatus further comprising: a reference voltage shifter, and an operational voltage selector, wherein: the reference voltage shifter is configured to shift a reference voltage by a test voltage; wherein the error rate detector is further configured to measure an error rate of the test voltage; and wherein the operational voltage selector is configured to select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage. a clock generator configured to generate a clock signal; a phase shifter configured to phase shift the clock signal by a test phase; an error rate detector configured to measure an error rate of the test phase; and an operational phase selector configured to select an operational phase of the clock signal based at least in part on the error rate of the test phase, the interconnect apparatus further comprising an error comparator, wherein the test phase is a first test phase, and wherein: the phase shifter is further configured to shift the clock signal by a second test phase; the error rate detector is further configured to measure an error of the second test phase; and the error comparator is configured to compare the error rate of the first test phase to the error rate of the second test phase and to select an optimal test phase; and the phase shifter is further configured to shift the clock signal by a second test phase; the error rate detector is further configured to measure an error of the second test phase; and the error comparator is configured to compare the error rate of the first test phase to the error rate of the second test phase and to select an optimal test phase; and the operational phase selector is configured to select the operational phase of the clock signal based at least in part on the error rate of the first test phase by selecting the operational phase of the clock signal based at least in part on the optimal test phase, the interconnect apparatus further comprising: a reference voltage shifter, and an operational voltage selector, wherein: the reference voltage shifter is configured to shift a reference voltage by a test voltage; wherein the error rate detector is further configured to measure an error rate of the test voltage; and wherein the operational voltage selector is configured to select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage. a reference voltage shifter, and an operational voltage selector, wherein: the reference voltage shifter is configured to shift a reference voltage by a test voltage; wherein the error rate detector is further configured to measure an error rate of the test voltage; and wherein the operational voltage selector is configured to select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage.