A liquid crystal display panel comprising: an insulating substrate; a plurality of gate lines (22; G1, G2,..., Gn) extending in a first direction on the insulating substrate; a plurality of data lines (62; D1, D2,..., Dm) extending in a second direction that crosses with the first direction at a cross point to define a pixel; a thin film transistor formed near the cross point of the gate line (22; G1, G2,..., Gn) and the data line (62; D1, D2,..., Dm) and connected to the gate line (22; G1, G2,..., Gn) and the data line (62; D1, D2,..., Dm); a pixel electrode connected to the thin film transistor and disposed within said pixel, wherein the pixel electrode comprising a lower boundary adjacent to the gate line; a plurality of first light blocking electrodes (21; 221; FP) comprising a first portion extending in the second direction and substantially parallel to the data line (62; D1, D2,..., Dm), a second portion extending in the first direction and across the data line (62; D1, D2,..., Dm), and a third portion extending from an area where the first portion and the second portion meet each other and extending along at least a first part of the lower boundary of the pixel electrode, wherein the third portion comprises a bent portion, and wherein the first, second and third portions contact one another near a second part of the lower boundary of the pixel electrode; characterized by a bridge electrode connecting the first light blocking electrode (21; 221; FP) and a second light blocking electrode, wherein the second light blocking electrode is disposed next to the first light blocking electrode in the second direction. an insulating substrate; a plurality of gate lines (22; G1, G2,..., Gn) extending in a first direction on the insulating substrate; a plurality of data lines (62; D1, D2,..., Dm) extending in a second direction that crosses with the first direction at a cross point to define a pixel; a thin film transistor formed near the cross point of the gate line (22; G1, G2,..., Gn) and the data line (62; D1, D2,..., Dm) and connected to the gate line (22; G1, G2,..., Gn) and the data line (62; D1, D2,..., Dm); a pixel electrode connected to the thin film transistor and disposed within said pixel, wherein the pixel electrode comprising a lower boundary adjacent to the gate line; a plurality of first light blocking electrodes (21; 221; FP) comprising a first portion extending in the second direction and substantially parallel to the data line (62; D1, D2,..., Dm), a second portion extending in the first direction and across the data line (62; D1, D2,..., Dm), and a third portion extending from an area where the first portion and the second portion meet each other and extending along at least a first part of the lower boundary of the pixel electrode, wherein the third portion comprises a bent portion, and wherein the first, second and third portions contact one another near a second part of the lower boundary of the pixel electrode; characterized by a bridge electrode connecting the first light blocking electrode (21; 221; FP) and a second light blocking electrode, wherein the second light blocking electrode is disposed next to the first light blocking electrode in the second direction.