A method of operating an SRAM memory (101, 301) selectably in either a normal voltage operation mode or a low voltage operation mode, the memory (101, 301) comprising memory cells (113, 117, 115, 119), each of the memory cells (113, 117, 115, 119) including a first voltage supply node and a second voltage supply node, wherein a voltage across a memory cell is a voltage differential between a voltage of the first voltage supply node and a voltage of the second voltage supply node, the method comprising: during performing a first access in the normal voltage operation mode and a second access in the low voltage operation mode on a subset of the memory cells, the memory receiving a first supply voltage at a first voltage supply terminal and a second supply voltage at a second voltage supply terminal (VDD; HSU312), in the normal voltage operation mode, performing the first access on the subset of the memory cells while maintaining a first voltage across the memory cells (113, 117, 115, 119); following a decision to operate in the low voltage operation mode, performing the second access (515, 517) on the subset of the memory cells (113, 117, 115, 119) while maintaining a second voltage across the memory cells; and wherein the first voltage maintained across the memory cells (113, 117, 115, 119) is a difference between the first supply voltage and the second supply voltage, and the second voltage maintained across the memory cells (113, 117, 115, 119) is regulated (131, 400) to be less than the first voltage; wherein each memory cell of the subset of memory cells is coupled to a bit line of a plurality of bit lines (WBLO, WBL1, RBLO, RBL1); wherein a voltage swing of a bit line of a memory cell of the subset of memory cells is a voltage difference between a high voltage state of the bit line and a low voltage state of the bit line, where the voltage state is dependent on a value being written or being read, and: (i) for the first access, a voltage swing of a bit line associated with the first access is the first voltage; (ii) for the second access (15, 517), a voltage swing of a bit line associated with the second access is the second voltage; wherein: the first access and the second access are writes; and for the write of the first access, a voltage swing on the plurality of bit lines (WBLO, WBL1, RBLO, RBL1) is the first voltage; for the write of the second access, the voltage swing on the plurality of bit lines is the second voltage. during performing a first access in the normal voltage operation mode and a second access in the low voltage operation mode on a subset of the memory cells, the memory receiving a first supply voltage at a first voltage supply terminal and a second supply voltage at a second voltage supply terminal (VDD; HSU312), in the normal voltage operation mode, performing the first access on the subset of the memory cells while maintaining a first voltage across the memory cells (113, 117, 115, 119); following a decision to operate in the low voltage operation mode, performing the second access (515, 517) on the subset of the memory cells (113, 117, 115, 119) while maintaining a second voltage across the memory cells; and wherein the first voltage maintained across the memory cells (113, 117, 115, 119) is a difference between the first supply voltage and the second supply voltage, and the second voltage maintained across the memory cells (113, 117, 115, 119) is regulated (131, 400) to be less than the first voltage; wherein each memory cell of the subset of memory cells is coupled to a bit line of a plurality of bit lines (WBLO, WBL1, RBLO, RBL1); wherein a voltage swing of a bit line of a memory cell of the subset of memory cells is a voltage difference between a high voltage state of the bit line and a low voltage state of the bit line, where the voltage state is dependent on a value being written or being read, and: (i) for the first access, a voltage swing of a bit line associated with the first access is the first voltage; (ii) for the second access (15, 517), a voltage swing of a bit line associated with the second access is the second voltage; (i) for the first access, a voltage swing of a bit line associated with the first access is the first voltage; (ii) for the second access (15, 517), a voltage swing of a bit line associated with the second access is the second voltage; wherein: the first access and the second access are writes; and for the write of the first access, a voltage swing on the plurality of bit lines (WBLO, WBL1, RBLO, RBL1) is the first voltage; for the write of the second access, the voltage swing on the plurality of bit lines is the second voltage. the first access and the second access are writes; and for the write of the first access, a voltage swing on the plurality of bit lines (WBLO, WBL1, RBLO, RBL1) is the first voltage; for the write of the second access, the voltage swing on the plurality of bit lines is the second voltage.