A switched capacitor notch filter, comprising: a first sampling capacitor having a first terminal selectively coupled to an input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch; a second sampling capacitor having a first terminal selectively coupled to the input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch; a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node; a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node; a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node; a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node; an operational amplifier having a first input node coupled to the common node, a second input node, and an output node at which an output signal of the filter is provided; a first feedback capacitor coupled between the output node and the first input node of the operational amplifier; and a clock signal generator for providing a first clock signal to close the first switch and the first reference switch during a first portion of each clock cycle, a second clock signal to close the third switch and the third reference switch during a second portion of each clock cycle and an averaging clock signal to close the second switch, fourth switch, second reference switch, and fourth reference switch during a third portion of each clock cycle, wherein the first, second and third clock signals of each clock cycle do not overlap with each other in each clock cycle, and wherein the first clock signal is devoted to sampling the first sampling capacitor during the first portion of each clock cycle, the second clock signal is devoted to sampling the second sampling capacitor during the second portion of each clock cycle, and the third clock signal is devoted to averaging the output signal from the first and the second sampling capacitors during the third portion of each clock cycle, and wherein the input signal is not sampled by the switched capacitor notch filter during the third portion of each clock cycle. a first sampling capacitor having a first terminal selectively coupled to an input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch; a second sampling capacitor having a first terminal selectively coupled to the input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch; a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node; a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node; a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node; a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node; an operational amplifier having a first input node coupled to the common node, a second input node, and an output node at which an output signal of the filter is provided; a first feedback capacitor coupled between the output node and the first input node of the operational amplifier; and a clock signal generator for providing a first clock signal to close the first switch and the first reference switch during a first portion of each clock cycle, a second clock signal to close the third switch and the third reference switch during a second portion of each clock cycle and an averaging clock signal to close the second switch, fourth switch, second reference switch, and fourth reference switch during a third portion of each clock cycle, wherein the first, second and third clock signals of each clock cycle do not overlap with each other in each clock cycle, and wherein the first clock signal is devoted to sampling the first sampling capacitor during the first portion of each clock cycle, the second clock signal is devoted to sampling the second sampling capacitor during the second portion of each clock cycle, and the third clock signal is devoted to averaging the output signal from the first and the second sampling capacitors during the third portion of each clock cycle, and wherein the input signal is not sampled by the switched capacitor notch filter during the third portion of each clock cycle.