A digitally-controlled power amplifier (called DPA hereinafter) (100, 200, 300) with bandpass filtering, comprising: - a radio-frequency (called RF hereinafter) clock input (102, 202), arranged for receiving an RF clock; - an amplitude control word (called ACW hereinafter) input (104, 204), arranged for receiving a digital ACW signal; and - a plurality of DPA cells (107_1, 107_M, 109_1, 109_N, 211, 213, 215, 217, 311, 1400), coupled to said RF clock and said digital ACW signal, wherein at least one of said DPA cells is gradually turned on and off in response to at least one bit of said digital ACW signal, characterized in that: gradual turning on and off is performed through resistive charging of a capacitor, said at least one of said DPA cells comprises: - a controller, arranged for receiving at least a bit of said digital ACW signal, and generating a plurality of intermediate control signals; and - an output driver, arranged for generating an RF output according to said intermediate control signals, said output driver comprises: - a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and - an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals, and said controller comprises: - a coupling block, comprising said capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and - a control block, arranged for controlling said intermediate control signals according to at least said bit of said digital ACW signal. - a radio-frequency (called RF hereinafter) clock input (102, 202), arranged for receiving an RF clock; - an amplitude control word (called ACW hereinafter) input (104, 204), arranged for receiving a digital ACW signal; and - a plurality of DPA cells (107_1, 107_M, 109_1, 109_N, 211, 213, 215, 217, 311, 1400), coupled to said RF clock and said digital ACW signal, wherein at least one of said DPA cells is gradually turned on and off in response to at least one bit of said digital ACW signal, characterized in that: gradual turning on and off is performed through resistive charging of a capacitor, said at least one of said DPA cells comprises: - a controller, arranged for receiving at least a bit of said digital ACW signal, and generating a plurality of intermediate control signals; and - an output driver, arranged for generating an RF output according to said intermediate control signals, said output driver comprises: - a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and - an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals, and said controller comprises: - a coupling block, comprising said capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and - a control block, arranged for controlling said intermediate control signals according to at least said bit of said digital ACW signal. gradual turning on and off is performed through resistive charging of a capacitor, said at least one of said DPA cells comprises: - a controller, arranged for receiving at least a bit of said digital ACW signal, and generating a plurality of intermediate control signals; and - an output driver, arranged for generating an RF output according to said intermediate control signals, - a controller, arranged for receiving at least a bit of said digital ACW signal, and generating a plurality of intermediate control signals; and - an output driver, arranged for generating an RF output according to said intermediate control signals, said output driver comprises: - a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and - an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals, and - a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and - an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals, and said controller comprises: - a coupling block, comprising said capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and - a control block, arranged for controlling said intermediate control signals according to at least said bit of said digital ACW signal. - a coupling block, comprising said capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and - a control block, arranged for controlling said intermediate control signals according to at least said bit of said digital ACW signal.