A computing apparatus, comprising: an internal interface circuit, an external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103), a cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104), a protocol conversion circuit, and at least one general computing core circuit (11, 21, 31, 41, 91), wherein the internal interface circuit is configured to couple to an internal apparatus by using a first communication protocol, wherein the first communication protocol is a communication protocol used by a system bus, and the internal apparatus is an apparatus sharing a resource with the computing apparatus by using the system bus; the external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103) is configured to couple to an external apparatus by using a second communication protocol, wherein the second communication protocol is a network communication protocol; and the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is separately coupled to the internal interface circuit and each general computing core circuit (11, 21, 31, 41, 91); wherein the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is configured to run a cache coherence protocol to implement data consistency between a cache and a memory; the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) selectively works in at least a first mode or a second mode, wherein when the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) works in the first mode, the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) implements cache coherence between the internal apparatus, the external apparatus, and the computing apparatus, and the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is further coupled to the protocol conversion circuit and the external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103) in sequence, and the protocol conversion circuit is configured to perform protocol conversion between a protocol used by the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) and the second communication protocol; and when the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) works in the second mode, the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) implements cache coherence between the computing apparatus and the internal apparatus, and the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is directly coupled to the external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103). an internal interface circuit, an external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103), a cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104), a protocol conversion circuit, and at least one general computing core circuit (11, 21, 31, 41, 91), wherein the internal interface circuit is configured to couple to an internal apparatus by using a first communication protocol, wherein the first communication protocol is a communication protocol used by a system bus, and the internal apparatus is an apparatus sharing a resource with the computing apparatus by using the system bus; the external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103) is configured to couple to an external apparatus by using a second communication protocol, wherein the second communication protocol is a network communication protocol; and the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is separately coupled to the internal interface circuit and each general computing core circuit (11, 21, 31, 41, 91); wherein the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is configured to run a cache coherence protocol to implement data consistency between a cache and a memory; the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) selectively works in at least a first mode or a second mode, wherein when the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) works in the first mode, the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) implements cache coherence between the internal apparatus, the external apparatus, and the computing apparatus, and the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is further coupled to the protocol conversion circuit and the external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103) in sequence, and the protocol conversion circuit is configured to perform protocol conversion between a protocol used by the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) and the second communication protocol; and when the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) works in the second mode, the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) implements cache coherence between the computing apparatus and the internal apparatus, and the cache coherence engine circuit (14, 24, 34, 44, 64, 84, 94, 104) is directly coupled to the external interface circuit (13, 23, 33, 43, 53, 63, 73, 83, 93, 103).