A semiconductor radiation detector device comprising at least one pixel, wherein the at least one pixel comprises a semiconductor substrate and in one surface of the substrate the at least one pixel comprises: - a first conductivity type well doping, - a second conductivity type source doping (911, 913, 1111, 1113) and a second conductivity type drain doping (912, 914, 1112, 1114) inside said first conductivity type well doping, - an opening in the first conductivity type well doping located in between said source doping and drain doping, - a first layer of semiconductor of second conductivity type, hereinafter the MIG layer, said MIG layer located in said opening of the first conductivity type well doping, - a barrier layer of semiconductor of first conductivity type arranged directly on the MIG layer in between the MIG layer and said one surface of the substrate and located in said opening of the first conductivity type well doping, said barrier layer configured to form a potential energy barrier for signal charges accumulated in said MIG layer during operation of the device, - a channel layer of a semiconductor of second conductivity type arranged directly on the barrier layer and at the one surface of the substrate, the channel layer located in between said barrier layer and said one surface, wherein the semiconductor radiation detector device is configured such that a channel that is located in between said source doping and drain doping as well as extends through said opening in the first conductivity type well doping in between said one surface and said barrier layer, goes through said channel layer, wherein the at least one pixel further comprises on the one surface of the substrate - a main gate (983, 1085) external to the semiconductor substrate and located in between said source doping and drain doping as well as on said opening in the first conductivity type well doping above said channel, and - at least one extra gate (981, 982, 1083, 1084) external to the semiconductor substrate and located in between the main gate and the second conductivity type source doping or drain doping wherein the at least one extra gate is located above a corresponding MIG border region at which a part of said channel is vertically aligned with an edge of said MIG layer, and wherein the at least one extra gate is adapted to be coupled to a potential such that the channel resistance is lower beneath the at least one extra gate than beneath the main gate such as to create inside the semiconductor substrate underneath the extra gate: - an artificial source if the extra gate (981, 1083) is located in between the second conductivity type source doping and the main gate (983, 1085), or - an artificial drain if the extra gate (982, 1084) is located in between the second conductivity type drain doping and the main gate (983, 1085). - a first conductivity type well doping, - a second conductivity type source doping (911, 913, 1111, 1113) and a second conductivity type drain doping (912, 914, 1112, 1114) inside said first conductivity type well doping, - an opening in the first conductivity type well doping located in between said source doping and drain doping, - a first layer of semiconductor of second conductivity type, hereinafter the MIG layer, said MIG layer located in said opening of the first conductivity type well doping, - a barrier layer of semiconductor of first conductivity type arranged directly on the MIG layer in between the MIG layer and said one surface of the substrate and located in said opening of the first conductivity type well doping, said barrier layer configured to form a potential energy barrier for signal charges accumulated in said MIG layer during operation of the device, - a channel layer of a semiconductor of second conductivity type arranged directly on the barrier layer and at the one surface of the substrate, - a main gate (983, 1085) external to the semiconductor substrate and located in between said source doping and drain doping as well as on said opening in the first conductivity type well doping above said channel, and - at least one extra gate (981, 982, 1083, 1084) external to the semiconductor substrate and located in between the main gate and the second conductivity type source doping or drain doping wherein the at least one extra gate is located above a corresponding MIG border region at which a part of said channel is vertically aligned with an edge of said MIG layer, and wherein the at least one extra gate is adapted to be coupled to a potential such that the channel resistance is lower beneath the at least one extra gate than beneath the main gate such as to create inside the semiconductor substrate underneath the extra gate: - an artificial source if the extra gate (981, 1083) is located in between the second conductivity type source doping and the main gate (983, 1085), or - an artificial drain if the extra gate (982, 1084) is located in between the second conductivity type drain doping and the main gate (983, 1085). - an artificial source if the extra gate (981, 1083) is located in between the second conductivity type source doping and the main gate (983, 1085), or - an artificial drain if the extra gate (982, 1084) is located in between the second conductivity type drain doping and the main gate (983, 1085).