A silicon-based quantum device for confining charge carriers, the device comprising: a substrate having a first planar region; a silicon layer (32, 132, 232, 332) which forms part of the substrate and includes a step (33, 133, 233) with an edge (34, 134, 234, 334) and a second planar region (35, 135), wherein the second planar region (35, 135) is substantially parallel to and offset from the first planar region; a first electrically insulating layer (42, 142, 242, 342) provided on the silicon layer (32, 132, 232, 332), overlying the step (33, 133, 233); a first metallic layer (51, 151, 251, 353), provided on the first electrically insulating layer (42, 142, 242, 342), overlying the step (33, 133, 233), arranged to be electrically connected such that when a first bias potential is applied to the first metallic layer (51, 151, 251, 353), a first confinement region (10, 110, 210, 310) is induced in which a charge carrier or charge carriers are confined at the edge (34, 134, 234, 334); and a second metallic layer (52, 152, 252, 352), provided overlying the second planar region of the silicon layer (32, 132, 232, 332), wherein the second metallic layer (52, 152, 252, 352) is: electrically separated from the first metallic layer (51, 151, 251, 353); the second metallic layer (52, 152, 252, 352) is arranged to be electrically connected such that when a second bias potential is applied to the second metallic layer (52, 152, 252, 352), a second confinement region (11, 111, 211) is induced, and the first confinement region (10, 110, 210, 310) is couplable to the second confinement region (11, 111, 211); wherein the first confinement region (10, 110, 210, 310) is displaced from the second confinement region (11, 111, 211) in a direction that is perpendicular to the edge; characterized in that $ a charge carrier or charge carriers are confined in the second confinement region (11, 111, 211) only in the second planar region (35, 135) of the silicon layer (32, 132, 232, 332) under the second metallic layer (52, 152, 252, 352). a substrate having a first planar region; a silicon layer (32, 132, 232, 332) which forms part of the substrate and includes a step (33, 133, 233) with an edge (34, 134, 234, 334) and a second planar region (35, 135), wherein the second planar region (35, 135) is substantially parallel to and offset from the first planar region; a first electrically insulating layer (42, 142, 242, 342) provided on the silicon layer (32, 132, 232, 332), overlying the step (33, 133, 233); a first metallic layer (51, 151, 251, 353), provided on the first electrically insulating layer (42, 142, 242, 342), overlying the step (33, 133, 233), arranged to be electrically connected such that when a first bias potential is applied to the first metallic layer (51, 151, 251, 353), a first confinement region (10, 110, 210, 310) is induced in which a charge carrier or charge carriers are confined at the edge (34, 134, 234, 334); and a second metallic layer (52, 152, 252, 352), provided overlying the second planar region of the silicon layer (32, 132, 232, 332), wherein the second metallic layer (52, 152, 252, 352) is: electrically separated from the first metallic layer (51, 151, 251, 353); the second metallic layer (52, 152, 252, 352) is arranged to be electrically connected such that when a second bias potential is applied to the second metallic layer (52, 152, 252, 352), a second confinement region (11, 111, 211) is induced, and the first confinement region (10, 110, 210, 310) is couplable to the second confinement region (11, 111, 211); wherein the first confinement region (10, 110, 210, 310) is displaced from the second confinement region (11, 111, 211) in a direction that is perpendicular to the edge; electrically separated from the first metallic layer (51, 151, 251, 353); the second metallic layer (52, 152, 252, 352) is arranged to be electrically connected such that when a second bias potential is applied to the second metallic layer (52, 152, 252, 352), a second confinement region (11, 111, 211) is induced, and the first confinement region (10, 110, 210, 310) is couplable to the second confinement region (11, 111, 211); wherein the first confinement region (10, 110, 210, 310) is displaced from the second confinement region (11, 111, 211) in a direction that is perpendicular to the edge; characterized in that $ a charge carrier or charge carriers are confined in the second confinement region (11, 111, 211) only in the second planar region (35, 135) of the silicon layer (32, 132, 232, 332) under the second metallic layer (52, 152, 252, 352).