A data acquisition system comprising: a plurality of processors (215, 412, 413, 414) comprising at least one first processor and a plurality of second digital signal processors, wherein said at least one first processor is configured to receive at least one configuration file and generate at least one measurement data application (506, 507) from the at least one configuration file; and a field-programmable gate array (FPGA) coupled to said plurality of processors (215, 412 413 414), wherein said FPGA is configured to receive said at least one measurement data application and comprises an embedded soft core processor configured to allocate at least a portion of the FPGA and at least one second digital signal processor of said plurality of second digital signal processors to calculate measurement data (556, 558, 562) at least partially based on said at least one measurement data application (506 507) and an availability of at least a portion of said FPGA, wherein said FPGA comprises at least one FPGA core configured to calculate a first portion of the measurement data, wherein the embedded soft core processor is configured to manage signal transmission such that the FPGA does not receive untested measurement data algorithms and at least one of said plurality of second digital signal processors is configured to receive and test at least one untested measurement data algorithm with real-time measurement data, such that testing is performed without interruption of standard execution of measurement data algorithms by the FPGA and the digital signal processors; and the embedded soft core processor is arranged to configure an FPGA database manager configured to receive and store, at least temporarily, the calculated measurement data (556, 558, 562) and to maintain a list of direct memory access segment descriptors. a plurality of processors (215, 412, 413, 414) comprising at least one first processor and a plurality of second digital signal processors, wherein said at least one first processor is configured to receive at least one configuration file and generate at least one measurement data application (506, 507) from the at least one configuration file; and a field-programmable gate array (FPGA) coupled to said plurality of processors (215, 412 413 414), wherein said FPGA is configured to receive said at least one measurement data application and comprises an embedded soft core processor configured to allocate at least a portion of the FPGA and at least one second digital signal processor of said plurality of second digital signal processors to calculate measurement data (556, 558, 562) at least partially based on said at least one measurement data application (506 507) and an availability of at least a portion of said FPGA, wherein said FPGA comprises at least one FPGA core configured to calculate a first portion of the measurement data, wherein the embedded soft core processor is configured to manage signal transmission such that the FPGA does not receive untested measurement data algorithms and at least one of said plurality of second digital signal processors is configured to receive and test at least one untested measurement data algorithm with real-time measurement data, such that testing is performed without interruption of standard execution of measurement data algorithms by the FPGA and the digital signal processors; and the embedded soft core processor is arranged to configure an FPGA database manager configured to receive and store, at least temporarily, the calculated measurement data (556, 558, 562) and to maintain a list of direct memory access segment descriptors. an embedded soft core processor configured to allocate at least a portion of the FPGA and at least one second digital signal processor of said plurality of second digital signal processors to calculate measurement data (556, 558, 562) at least partially based on said at least one measurement data application (506 507) and an availability of at least a portion of said FPGA, wherein said FPGA comprises at least one FPGA core configured to calculate a first portion of the measurement data, wherein the embedded soft core processor is configured to manage signal transmission such that the FPGA does not receive untested measurement data algorithms and at least one of said plurality of second digital signal processors is configured to receive and test at least one untested measurement data algorithm with real-time measurement data, such that testing is performed without interruption of standard execution of measurement data algorithms by the FPGA and the digital signal processors; and the embedded soft core processor is arranged to configure an FPGA database manager configured to receive and store, at least temporarily, the calculated measurement data (556, 558, 562) and to maintain a list of direct memory access segment descriptors.