An apparatus for compensating for a timing offset in a spread spectrum system, the apparatus comprising: an oversampling unit configured to oversample, by a multiple P, data whose each of N symbols is spread over and received by C chips; an oversampled chip collection unit configured to collect C, which is a number of chips, samples at positions apart from each of all the oversampled samples by the multiple P, which is the oversampling multiple; a despreading unit configured to despread each of collected oversampled chips using a unique code of a corresponding symbol; a peak value detection/storage unit configured to detect an oversampled chip having a largest correlation value among despread oversampled chips in every predetermined section, and then store sample indices of the detected oversampled chips as peak value sample indices; a timing offset calculation unit configured to calculate a chip clock timing offset O ct and a system clock timing offset O st using the respective peak value sample indices; and a downsampling unit configured to downsample the oversampled samples while compensating for the chip clock timing offset and the system clock timing offset, wherein the chip clock timing offset O ct is calculated using an equation below: O ct n = C cto ∗ n n being a symbol index, where the chip clock timing offset coefficient C cto is calculated using an equation below: C cto = N * δ − β * α N * γ − β * β, and the system clock timing offset coefficient O st is calculated using an equation below: O st = α * δ − β * δ N * γ − β * β, where d[n] = q[n] - q, n = 0, 1,..., N-1, e n = d n − n ∗ P ∗ C, n = 0, 1,..., N − 1, α = ∑ n = 0 N − 1 e n, β = ∑ n = 0 N − 1 n = N * N − 1 2, γ = ∑ n = 0 N − 1 n 2 = N * N − 1 * 2 N − 1 6, δ = ∑ n = 0 N − 1 e n * n, q denotes the peak value sample index of the first symbol, and q[n] denotes a peak value sample index of an n th symbol. an oversampling unit configured to oversample, by a multiple P, data whose each of N symbols is spread over and received by C chips; an oversampled chip collection unit configured to collect C, which is a number of chips, samples at positions apart from each of all the oversampled samples by the multiple P, which is the oversampling multiple; a despreading unit configured to despread each of collected oversampled chips using a unique code of a corresponding symbol; a peak value detection/storage unit configured to detect an oversampled chip having a largest correlation value among despread oversampled chips in every predetermined section, and then store sample indices of the detected oversampled chips as peak value sample indices; a timing offset calculation unit configured to calculate a chip clock timing offset O ct and a system clock timing offset O st using the respective peak value sample indices; and a downsampling unit configured to downsample the oversampled samples while compensating for the chip clock timing offset and the system clock timing offset, wherein the chip clock timing offset O ct is calculated using an equation below: O ct n = C cto ∗ n n being a symbol index, where the chip clock timing offset coefficient C cto is calculated using an equation below: C cto = N * δ − β * α N * γ − β * β, and the system clock timing offset coefficient O st is calculated using an equation below: O st = α * δ − β * δ N * γ − β * β, where d[n] = q[n] - q, n = 0, 1,..., N-1, e n = d n − n ∗ P ∗ C, n = 0, 1,..., N − 1, α = ∑ n = 0 N − 1 e n, β = ∑ n = 0 N − 1 n = N * N − 1 2, γ = ∑ n = 0 N − 1 n 2 = N * N − 1 * 2 N − 1 6, δ = ∑ n = 0 N − 1 e n * n, q denotes the peak value sample index of the first symbol, and q[n] denotes a peak value sample index of an n th symbol. q denotes the peak value sample index of the first symbol, and q[n] denotes a peak value sample index of an n th symbol.