A pixel arrangement, comprising: a differential pixel structure, each pixel comprising: a polysilicon finger(311, 411, 511); a charge storage element 315); and a diffusion node (312, 318, 412, 512, 518, 618); and output circuitry (333, 533, 640) comprising: measurement capacitance elements configured to store measurement voltages of each of the pixels presented by the diffusion nodes that are representative of integrated charges established by the polysilicon fingers during a measurement phase and are dumped from the charge storage element; and reset capacitance elements configured to store reset voltages of each of the pixels presented by the diffusion nodes during a reset phase performed prior to the measurement phase; wherein, for each of the pixels, the output circuitry is configured to subtract the reset voltage stored in the reset capacitance element from the measurement voltage stored in the measurement capacitance element to establish a compensated result that at least partially reduces readout voltage uncertainty and provide the compensated results for both of the pixels for processing into a differentially derived pixel output voltage; characterized by bias gate elements (314, 414, 514, 614) for each of the pixels configured to establish a bias potential between the polysilicon finger and the charge storage element to provide a pathway for transfer of at least a portion of the charges established at the polysilicon finger to the charge storage element and reduce a quantity of the charges transferred to the charge storage element from returning to the polysilicon finger; and transfer gate elements (317, 417, 517, 617) for each of the pixels, based on activation, configured to establish a transfer potential between at least the charge storage element and the diffusion node to dump ones of the integrated charges stored at the charge storage element to the diffusion node. a polysilicon finger(311, 411, 511); a charge storage element 315); and a diffusion node (312, 318, 412, 512, 518, 618); and output circuitry (333, 533, 640) comprising: measurement capacitance elements configured to store measurement voltages of each of the pixels presented by the diffusion nodes that are representative of integrated charges established by the polysilicon fingers during a measurement phase and are dumped from the charge storage element; and reset capacitance elements configured to store reset voltages of each of the pixels presented by the diffusion nodes during a reset phase performed prior to the measurement phase; wherein, for each of the pixels, the output circuitry is configured to subtract the reset voltage stored in the reset capacitance element from the measurement voltage stored in the measurement capacitance element to establish a compensated result that at least partially reduces readout voltage uncertainty and provide the compensated results for both of the pixels for processing into a differentially derived pixel output voltage; characterized by bias gate elements (314, 414, 514, 614) for each of the pixels configured to establish a bias potential between the polysilicon finger and the charge storage element to provide a pathway for transfer of at least a portion of the charges established at the polysilicon finger to the charge storage element and reduce a quantity of the charges transferred to the charge storage element from returning to the polysilicon finger; and transfer gate elements (317, 417, 517, 617) for each of the pixels, based on activation, configured to establish a transfer potential between at least the charge storage element and the diffusion node to dump ones of the integrated charges stored at the charge storage element to the diffusion node. measurement capacitance elements configured to store measurement voltages of each of the pixels presented by the diffusion nodes that are representative of integrated charges established by the polysilicon fingers during a measurement phase and are dumped from the charge storage element; and reset capacitance elements configured to store reset voltages of each of the pixels presented by the diffusion nodes during a reset phase performed prior to the measurement phase; wherein, for each of the pixels, the output circuitry is configured to subtract the reset voltage stored in the reset capacitance element from the measurement voltage stored in the measurement capacitance element to establish a compensated result that at least partially reduces readout voltage uncertainty and provide the compensated results for both of the pixels for processing into a differentially derived pixel output voltage; characterized by bias gate elements (314, 414, 514, 614) for each of the pixels configured to establish a bias potential between the polysilicon finger and the charge storage element to provide a pathway for transfer of at least a portion of the charges established at the polysilicon finger to the charge storage element and reduce a quantity of the charges transferred to the charge storage element from returning to the polysilicon finger; and transfer gate elements (317, 417, 517, 617) for each of the pixels, based on activation, configured to establish a transfer potential between at least the charge storage element and the diffusion node to dump ones of the integrated charges stored at the charge storage element to the diffusion node.