A charge pump CMOS circuit for use in an oscillator, comprising: a first diode-connected MOS transistor having a source connected to a first common node and a drain and gate connected together (Vb); a first input MOS transistor having a drain connected to the common drain and gate of said first diode-connected MOS transistor (Vb), a source connected to a second common node and a gate receiving a first differential input signal; a second diode-connected MOS transistor having a source connected to said first common node and a drain and gate connected together (Va); a second input MOS transistor having a drain connected to the common drain and gate of said second diode-connected MOS transistor (Va), a source connected to said second common node and a gate receiving a second differential input signal; a first current source (Ib) connected between said second common node and a third common node; a second current source connected between said common drain and gate of said first diode-connected MOS transistor and said third common node; a third current source connected between said common drain and gate of said second diode-connected MOS transistor and said third common node; a first current mirror circuit including a first current mirror MOS transistor having a source connected to said first common node, a gate connected to the common drain and gate (Vb) of said first diode-connected MOS transistor and a drain, and a second current mirror MOS transistor having a drain connected to said drain of said first current mirror transistor, a gate connected to said drain and a source connected to said third common node; and a second current mirror circuit including a third current mirror MOS transistor having a source connected to said first common node, a gate connected to the common drain and gate (Va) of said second diode-connected MOS transistor and a drain, a fourth current mirror MOS transistor having a drain connected to said drain of said third current mirror transistor, a gate connected to the common drain and gate of said second current mirror MOS transistor and a source connected to said third common node, and an output terminal connected to said drain of said third current mirror MOS transistor and said drain of said fourth current mirror MOS transistor. a first diode-connected MOS transistor having a source connected to a first common node and a drain and gate connected together (Vb); a first input MOS transistor having a drain connected to the common drain and gate of said first diode-connected MOS transistor (Vb), a source connected to a second common node and a gate receiving a first differential input signal; a second diode-connected MOS transistor having a source connected to said first common node and a drain and gate connected together (Va); a second input MOS transistor having a drain connected to the common drain and gate of said second diode-connected MOS transistor (Va), a source connected to said second common node and a gate receiving a second differential input signal; a first current source (Ib) connected between said second common node and a third common node; a second current source connected between said common drain and gate of said first diode-connected MOS transistor and said third common node; a third current source connected between said common drain and gate of said second diode-connected MOS transistor and said third common node; a first current mirror circuit including a first current mirror MOS transistor having a source connected to said first common node, a gate connected to the common drain and gate (Vb) of said first diode-connected MOS transistor and a drain, and a second current mirror MOS transistor having a drain connected to said drain of said first current mirror transistor, a gate connected to said drain and a source connected to said third common node; and a first current mirror MOS transistor having a source connected to said first common node, a gate connected to the common drain and gate (Vb) of said first diode-connected MOS transistor and a drain, and a second current mirror MOS transistor having a drain connected to said drain of said first current mirror transistor, a gate connected to said drain and a source connected to said third common node; and a second current mirror circuit including a third current mirror MOS transistor having a source connected to said first common node, a gate connected to the common drain and gate (Va) of said second diode-connected MOS transistor and a drain, a fourth current mirror MOS transistor having a drain connected to said drain of said third current mirror transistor, a gate connected to the common drain and gate of said second current mirror MOS transistor and a source connected to said third common node, and an output terminal connected to said drain of said third current mirror MOS transistor and said drain of said fourth current mirror MOS transistor. a third current mirror MOS transistor having a source connected to said first common node, a gate connected to the common drain and gate (Va) of said second diode-connected MOS transistor and a drain, a fourth current mirror MOS transistor having a drain connected to said drain of said third current mirror transistor, a gate connected to the common drain and gate of said second current mirror MOS transistor and a source connected to said third common node, and an output terminal connected to said drain of said third current mirror MOS transistor and said drain of said fourth current mirror MOS transistor.