An active matrix type display apparatus, comprising: a display area section wherein pixels each having an electro-optical device are disposed in a matrix manner; a vertical driving circuit for selecting the pixels of said display area section in a unit of a row; a horizontal driving circuit (13U, 13D) for receiving digital image data as an input thereto, said horizontal driving circuit (13U, 13D) including a sampling latch circuit for successively sampling and latching the digital image data, a line sequence latch circuit for line sequence the latch data of said sampling latch circuit, and said horizontal driving circuit is characterized in that it further comprises: a D/A conversion circuit for converting the digital image data line sequenced by said line sequence latch circuit into an analog image signal in order to supply the digital image data as an analog image signal to the pixels of a row selected by said vertical driving circuit; and a control circuit for selectively assuming a low gradation mode which uses a smaller number of gradations than a normal mode, said control circuit being configured to place only a number of circuit portions of said horizontal driving circuit (13U, 13D) equal to the number of gradations into an active state when the low gradation mode is being set, wherein said control circuits is configured to use only a number of input control lines equal to the number of gradations from among input control lines of said D/A conversion circuit and to fix the potentials at the remaining input control lines to the logic "0" or the logic "1". a display area section wherein pixels each having an electro-optical device are disposed in a matrix manner; a vertical driving circuit for selecting the pixels of said display area section in a unit of a row; a horizontal driving circuit (13U, 13D) for receiving digital image data as an input thereto, said horizontal driving circuit (13U, 13D) including a sampling latch circuit for successively sampling and latching the digital image data, a line sequence latch circuit for line sequence the latch data of said sampling latch circuit, and said horizontal driving circuit is characterized in that it further comprises: a D/A conversion circuit for converting the digital image data line sequenced by said line sequence latch circuit into an analog image signal in order to supply the digital image data as an analog image signal to the pixels of a row selected by said vertical driving circuit; and a control circuit for selectively assuming a low gradation mode which uses a smaller number of gradations than a normal mode, said control circuit being configured to place only a number of circuit portions of said horizontal driving circuit (13U, 13D) equal to the number of gradations into an active state when the low gradation mode is being set, wherein said control circuits is configured to use only a number of input control lines equal to the number of gradations from among input control lines of said D/A conversion circuit and to fix the potentials at the remaining input control lines to the logic "0" or the logic "1". a D/A conversion circuit for converting the digital image data line sequenced by said line sequence latch circuit into an analog image signal in order to supply the digital image data as an analog image signal to the pixels of a row selected by said vertical driving circuit; and a control circuit for selectively assuming a low gradation mode which uses a smaller number of gradations than a normal mode, said control circuit being configured to place only a number of circuit portions of said horizontal driving circuit (13U, 13D) equal to the number of gradations into an active state when the low gradation mode is being set, wherein said control circuits is configured to use only a number of input control lines equal to the number of gradations from among input control lines of said D/A conversion circuit and to fix the potentials at the remaining input control lines to the logic "0" or the logic "1".