A non-volatile memory circuit, the non-volatile memory circuit comprising: memory rows (220, 260), wherein at least one of the memory rows (220; 260) comprises at least one Electrically Erasable Programmable Read-Only Memory, EEPROM, memory element (222, 224; 262, 264) and at least one Flash memory element (226; 266), and wherein the at least one EEPROM element (222, 224; 262, 264) and the at least one Flash element (226, 266) are configured to be accessed in parallel; and supporting circuits coupled to the memory rows (220, 260), wherein some of the supporting circuits are shared by the at least one EEPROM element (222, 224; 262, 264) and the at least one Flash element (226; 266) of the at least one of the memory rows; wherein each of the EEPROM memory elements (222, 224; 262, 264) of a memory row (220, 260) comprises one or more EEPROM memory cells, each of which comprises an EEPROM cell transistor and an EEPROM access transistor, wherein each of the Flash elements (226; 266) of said memory row (220, 260) comprises one or more Flash memory cells, each of which comprises a Flash cell transistor and an access transistor, and wherein the length of each EEPROM memory element (222, 224; 262, 264) of said memory row (220, 260) and the length of each Flash element (226; 266) of said memory row (220, 260) for storing the same amount of data differ; and wherein for said memory row (220; 260), the access transistors of the one or more EEPROM memory cells and of the one or more Flash memory cells are coupled to a common access voltage supply line (240, 280) associated with said memory row(220; 240) and are configured to select each EEPROM cell transistor and each Flash cell transistor of said memory row (220, 240) when the common access voltage supply line (240, 280) is activated. memory rows (220, 260), wherein at least one of the memory rows (220; 260) comprises at least one Electrically Erasable Programmable Read-Only Memory, EEPROM, memory element (222, 224; 262, 264) and at least one Flash memory element (226; 266), and wherein the at least one EEPROM element (222, 224; 262, 264) and the at least one Flash element (226, 266) are configured to be accessed in parallel; and supporting circuits coupled to the memory rows (220, 260), wherein some of the supporting circuits are shared by the at least one EEPROM element (222, 224; 262, 264) and the at least one Flash element (226; 266) of the at least one of the memory rows; wherein each of the EEPROM memory elements (222, 224; 262, 264) of a memory row (220, 260) comprises one or more EEPROM memory cells, each of which comprises an EEPROM cell transistor and an EEPROM access transistor, wherein each of the Flash elements (226; 266) of said memory row (220, 260) comprises one or more Flash memory cells, each of which comprises a Flash cell transistor and an access transistor, and wherein the length of each EEPROM memory element (222, 224; 262, 264) of said memory row (220, 260) and the length of each Flash element (226; 266) of said memory row (220, 260) for storing the same amount of data differ; and wherein for said memory row (220; 260), the access transistors of the one or more EEPROM memory cells and of the one or more Flash memory cells are coupled to a common access voltage supply line (240, 280) associated with said memory row(220; 240) and are configured to select each EEPROM cell transistor and each Flash cell transistor of said memory row (220, 240) when the common access voltage supply line (240, 280) is activated.