A phase locked loop comprising: a phase detector, operable in a bang-bang mode to provide a binary phase error signal (Δ φ) either indicating there is a positive or a negative phase difference between a reference signal ( φ ref) and a feedback signal ( φ fb); a loop filter configured to provide a control signal derived from the binary phase error signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; and a lock/unlock detector configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from spectral characteristics of the binary phase error signal and/or a duty cycle of the binary phase error signal; characterized in that the lock detector comprises: a high pass filter configured to receive the phase error signal, and to pass high frequency content at the expected frequencies with which the bang-bang phase error will switch between its normalised limit values of +0.5 and -0.5 with a duty cycle of approximately 50% in phase lock and to attenuate lower frequencies associated with a settling phase of the phase locked loop; a rectifier for rectifying the output from the high pass filter to produce a rectified signal; a low pass filter arranged to receive a signal derived from the rectified signal; a comparator configured to compare an output signal from the low pass filter with at least one threshold value, and to output a signal, derived from the comparison, that indicates at least one criterion for phase lock is met; and an input enable device, configured not to pass the binary phase error signal when a signal indicating an unlock condition is present. a phase detector, operable in a bang-bang mode to provide a binary phase error signal (Δ φ) either indicating there is a positive or a negative phase difference between a reference signal ( φ ref) and a feedback signal ( φ fb); a loop filter configured to provide a control signal derived from the binary phase error signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; and a lock/unlock detector configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from spectral characteristics of the binary phase error signal and/or a duty cycle of the binary phase error signal; characterized in that the lock detector comprises: a high pass filter configured to receive the phase error signal, and to pass high frequency content at the expected frequencies with which the bang-bang phase error will switch between its normalised limit values of +0.5 and -0.5 with a duty cycle of approximately 50% in phase lock and to attenuate lower frequencies associated with a settling phase of the phase locked loop; a rectifier for rectifying the output from the high pass filter to produce a rectified signal; a low pass filter arranged to receive a signal derived from the rectified signal; a comparator configured to compare an output signal from the low pass filter with at least one threshold value, and to output a signal, derived from the comparison, that indicates at least one criterion for phase lock is met; and an input enable device, configured not to pass the binary phase error signal when a signal indicating an unlock condition is present. a high pass filter configured to receive the phase error signal, and to pass high frequency content at the expected frequencies with which the bang-bang phase error will switch between its normalised limit values of +0.5 and -0.5 with a duty cycle of approximately 50% in phase lock and to attenuate lower frequencies associated with a settling phase of the phase locked loop; a rectifier for rectifying the output from the high pass filter to produce a rectified signal; a low pass filter arranged to receive a signal derived from the rectified signal; a comparator configured to compare an output signal from the low pass filter with at least one threshold value, and to output a signal, derived from the comparison, that indicates at least one criterion for phase lock is met; and an input enable device, configured not to pass the binary phase error signal when a signal indicating an unlock condition is present.