A circuit for selecting a supply voltage (VS j), comprising: - a first node designed to receive a first input supply voltage (VDD H); - a second node designed to receive a second input supply voltage (VDD L) less than the first input supply voltage (VDD H); - a third node designed to supply an output supply voltage (VCORE); - a first power transistor (PS H) connecting the first node to the third node; - a second power transistor (PS L) connecting the second node to the third node; - and a configuration circuit (CONF) designed, in a first configuration, to keep the first (PS H) and second (PS L) transistors respectively in the on state and in the off state so as to apply the first input supply voltage (VDD H) to the third node and, in a second configuration, to keep the first (PS H) and second (PS L) transistors respectively in the off state and in the on state so as to apply the second input supply voltage (VDD L) to the third node; a transition phase from the first configuration to the second configuration being called downward transition; a transition phase from the second configuration to the first configuration being called upward transition; the configuration circuit (CONF) comprising: - a first transition management circuit (CGT H) configured to control the gate of the first transistor (PS H) upon the upward or downward transition so as to apply, to the third node: ∘ at least one first voltage ramp having a first slope for a first duration defining a slow phase (φ1, φ'2, φ"1, φ′′′2); ∘ and a second voltage ramp having a second slope, greater than the first slope, for a second duration defining a fast phase (φ3, φ'1, φ"3, φ′′′1), - a second transition management circuit (CGT L) configured to control the gate of the second transistor (PS L) upon the upward or downward transition so as to apply a control signal (VGATE_PS L) having a gradual variation; upon an upward transition, the first voltage ramp being applied before the second voltage ramp; upon a downward transition, the second voltage ramp being applied before the first voltage ramp. - a first node designed to receive a first input supply voltage (VDD H); - a second node designed to receive a second input supply voltage (VDD L) less than the first input supply voltage (VDD H); - a third node designed to supply an output supply voltage (VCORE); - a first power transistor (PS H) connecting the first node to the third node; - a second power transistor (PS L) connecting the second node to the third node; - and a configuration circuit (CONF) designed, in a first configuration, to keep the first (PS H) and second (PS L) transistors respectively in the on state and in the off state so as to apply the first input supply voltage (VDD H) to the third node and, in a second configuration, to keep the first (PS H) and second (PS L) transistors respectively in the off state and in the on state so as to apply the second input supply voltage (VDD L) to the third node; a transition phase from the first configuration to the second configuration being called downward transition; a transition phase from the second configuration to the first configuration being called upward transition; the configuration circuit (CONF) comprising: a transition phase from the first configuration to the second configuration being called downward transition; a transition phase from the second configuration to the first configuration being called upward transition; the configuration circuit (CONF) comprising: - a first transition management circuit (CGT H) configured to control the gate of the first transistor (PS H) upon the upward or downward transition so as to apply, to the third node: ∘ at least one first voltage ramp having a first slope for a first duration defining a slow phase (φ1, φ'2, φ"1, φ′′′2); ∘ and a second voltage ramp having a second slope, greater than the first slope, for a second duration defining a fast phase (φ3, φ'1, φ"3, φ′′′1), ∘ at least one first voltage ramp having a first slope for a first duration defining a slow phase (φ1, φ'2, φ"1, φ′′′2); ∘ and a second voltage ramp having a second slope, greater than the first slope, for a second duration defining a fast phase (φ3, φ'1, φ"3, φ′′′1), - a second transition management circuit (CGT L) configured to control the gate of the second transistor (PS L) upon the upward or downward transition so as to apply a control signal (VGATE_PS L) having a gradual variation;