A method performed in a receive node of a communication network to perform a first stage processing a symbol of interest contained in a first composite signal, and to perform a second stage processing the same symbol of interest contained in a second composite signal, wherein the first and second composite signals are both signals in a chip domain, wherein the first stage processing comprises: first stage despreading and combining the first composite signal in the chip domain to obtain first stage equalized symbols in a symbol domain; first stage generating first stage symbol estimates in the symbol domain based on the first stage equalized symbols; first stage regenerating a first stage signal estimate in the chip domain based on the first stage symbol estimates; and first stage interference canceling the first stage signal estimate from the first composite signal in the chip domain to generate an interference reduced version, the second composite signal, of the first composite signal, and wherein the second stage processing comprises: second stage despreading and combining the second composite signal in the chip domain to obtain second stage symbol values in the symbol domain; second stage symbol adding-back a scaled version of a previous stage symbol estimates to the second stage symbol values to obtain second stage equalized symbols in the symbol domain, wherein from the perspective of a particular symbol of interest, that symbol is equalized by adding back a soft symbol s to form a fully equalized symbol ŝ, wherein the soft symbol s is scaled by a scaling factor g; and second stage generating second stage symbol estimates in the symbol domain based on the second stage equalized symbols, wherein the second composite signal is based on the interference-reduced version of the first composite signal, and wherein in the step of second stage generating the second stage symbol estimates, the previous stage symbol estimates are the first stage symbol estimates or the second stage symbol estimates generated in a previous run of the second stage processing, wherein the step of second stage generating the second stage symbol estimates comprises: demodulating the second stage equalized symbols to obtain second stage demodulated bit soft values; soft decoding the second stage demodulated bit soft values to obtain second stage likelihood indicators; and soft modulating the second stage likelihood indicators to generate the second stage symbol estimates, or wherein the step of second stage generating the second stage symbol estimates comprises: demodulating the second stage equalized symbols to obtain second stage demodulated bits or second stage likelihood indicators; and decoding the second stage demodulated bits or the second stage likelihood indicators obtain second stage decoded information bit values; reencoding the second stage decoded information bit values to obtain second stage reencoded bit values; and modulating the second stage reencoded bit values to generate the second stage symbol estimates. first stage despreading and combining the first composite signal in the chip domain to obtain first stage equalized symbols in a symbol domain; first stage generating first stage symbol estimates in the symbol domain based on the first stage equalized symbols; first stage regenerating a first stage signal estimate in the chip domain based on the first stage symbol estimates; and first stage interference canceling the first stage signal estimate from the first composite signal in the chip domain to generate an interference reduced version, the second composite signal, of the first composite signal, and second stage despreading and combining the second composite signal in the chip domain to obtain second stage symbol values in the symbol domain; second stage symbol adding-back a scaled version of a previous stage symbol estimates to the second stage symbol values to obtain second stage equalized symbols in the symbol domain, wherein from the perspective of a particular symbol of interest, that symbol is equalized by adding back a soft symbol s to form a fully equalized symbol ŝ, wherein the soft symbol s is scaled by a scaling factor g; and second stage generating second stage symbol estimates in the symbol domain based on the second stage equalized symbols, demodulating the second stage equalized symbols to obtain second stage demodulated bit soft values; soft decoding the second stage demodulated bit soft values to obtain second stage likelihood indicators; and soft modulating the second stage likelihood indicators to generate the second stage symbol estimates, demodulating the second stage equalized symbols to obtain second stage demodulated bits or second stage likelihood indicators; and decoding the second stage demodulated bits or the second stage likelihood indicators obtain second stage decoded information bit values; reencoding the second stage decoded information bit values to obtain second stage reencoded bit values; and modulating the second stage reencoded bit values to generate the second stage symbol estimates.