An apparatus, comprising: a padding circuitry that is operative to pad at least one bit to a plurality of header information bits thereby generating a padded bit block; an LDPC (Low Density Parity Check) encoder circuitry, coupled to the padding circuitry, that is operative to encode the padded bit block thereby generating a plurality of LDPC coded bits; a shorten/puncture circuitry, coupled to the encoder circuitry, that is operative to: shorten at least one bit within the plurality of LDPC coded bits that corresponds to the at least one bit padded to the plurality of header information bits thereby generating a plurality of shortened coded bits; perform repetition coding on the plurality of shortened coded bits thereby generating at least one duplicate of the plurality of shortened coded bits; puncture at least one of the plurality of shortened coded bits thereby generating a first plurality of remaining bits; and puncture at least one of the at least one duplicate of the plurality of shortened coded bits thereby generating a second plurality of remaining bits using a different puncturing pattern than for the at least one of the plurality of shortened coded bits; and a spreader circuitry, coupled to the shorten/puncture circuitry, that is operative to process the first plurality of remaining bits and the second plurality of remaining bits thereby generating a header. a padding circuitry that is operative to pad at least one bit to a plurality of header information bits thereby generating a padded bit block; an LDPC (Low Density Parity Check) encoder circuitry, coupled to the padding circuitry, that is operative to encode the padded bit block thereby generating a plurality of LDPC coded bits; a shorten/puncture circuitry, coupled to the encoder circuitry, that is operative to: shorten at least one bit within the plurality of LDPC coded bits that corresponds to the at least one bit padded to the plurality of header information bits thereby generating a plurality of shortened coded bits; perform repetition coding on the plurality of shortened coded bits thereby generating at least one duplicate of the plurality of shortened coded bits; puncture at least one of the plurality of shortened coded bits thereby generating a first plurality of remaining bits; and puncture at least one of the at least one duplicate of the plurality of shortened coded bits thereby generating a second plurality of remaining bits using a different puncturing pattern than for the at least one of the plurality of shortened coded bits; and shorten at least one bit within the plurality of LDPC coded bits that corresponds to the at least one bit padded to the plurality of header information bits thereby generating a plurality of shortened coded bits; perform repetition coding on the plurality of shortened coded bits thereby generating at least one duplicate of the plurality of shortened coded bits; puncture at least one of the plurality of shortened coded bits thereby generating a first plurality of remaining bits; and puncture at least one of the at least one duplicate of the plurality of shortened coded bits thereby generating a second plurality of remaining bits using a different puncturing pattern than for the at least one of the plurality of shortened coded bits; and a spreader circuitry, coupled to the shorten/puncture circuitry, that is operative to process the first plurality of remaining bits and the second plurality of remaining bits thereby generating a header.