A driver system (100, 110) for digitally driving pixels of a display, each pixel of the display comprising a pixel driving circuit (300, 400) connected between a first and a second power supply line of a power supply line pair (311, 312) and further connected to a data line, each pixel driving circuit being adapted for selecting data signals from the data line and for opening and closing a current path between the first and second power supply line according to selected data signals, each opening and closing of the current path corresponding to the generation of a current pulse for illuminating the pixel associated with that pixel driving circuit, the driver system comprising: - at least one power supply unit (10, 11), operably connectable to power supply line pairs (311, 312) of the display, for providing a predetermined voltage to each power supply line of the display, - a voltage drop calculation unit for calculating voltage drops over the power supply lines at the level of each connected pixel driving circuit, wherein a voltage drop to be calculated for a pixel driving circuit in a row of display pixels accounts for current paths between the first and the second power supply line being open or closed in respect of one or more pixel driving circuits in said same row of display pixels, - at least one voltage drop compensation unit (109, 119) configured to receive voltage drops calculated by the voltage drop calculation unit as inputs and, based thereon, to generate data compensation signals in order to compensate for the calculated voltage drops at each connected pixel driving circuit, - at least one data line driver for generating and supplying pulse width modulation encoded data signals to data lines of the display, the at least one data line driver being configured to receive data compensation signals generated by the voltage drop compensation unit and to apply received data compensation signals to said PWM encoded data signals, characterized in that the at least one data line driver is configured to PWM encode an n-bit data signal according to two different colour scales of n-m bit colour depth each, a first colour scale using only the n-m least significant bits and discarding the m most significant bits and a second colour scale using only the n-m most significant bits and discarding the m least significant bits, depending on whether the m MSB are all equalling logic zero or at least one of the m MSB is not equalling logic zero, respectively, wherein the at least one data line driver is configured so that supplied data signals encoded according to said first colour scale induce current pulses of a low reference current level (LL ∗ I ref) in respective pixel driving circuits and data signals encoded according to said second colour scale induce current pulses of a high reference current level (HL ∗ I ref). - at least one power supply unit (10, 11), operably connectable to power supply line pairs (311, 312) of the display, for providing a predetermined voltage to each power supply line of the display, - a voltage drop calculation unit for calculating voltage drops over the power supply lines at the level of each connected pixel driving circuit, wherein a voltage drop to be calculated for a pixel driving circuit in a row of display pixels accounts for current paths between the first and the second power supply line being open or closed in respect of one or more pixel driving circuits in said same row of display pixels, - at least one voltage drop compensation unit (109, 119) configured to receive voltage drops calculated by the voltage drop calculation unit as inputs and, based thereon, to generate data compensation signals in order to compensate for the calculated voltage drops at each connected pixel driving circuit, - at least one data line driver for generating and supplying pulse width modulation encoded data signals to data lines of the display, the at least one data line driver being configured to receive data compensation signals generated by the voltage drop compensation unit and to apply received data compensation signals to said PWM encoded data signals, characterized in that the at least one data line driver is configured to PWM encode an n-bit data signal according to two different colour scales of n-m bit colour depth each, a first colour scale using only the n-m least significant bits and discarding the m most significant bits and a second colour scale using only the n-m most significant bits and discarding the m least significant bits, depending on whether the m MSB are all equalling logic zero or at least one of the m MSB is not equalling logic zero, respectively, wherein the at least one data line driver is configured so that supplied data signals encoded according to said first colour scale induce current pulses of a low reference current level (LL ∗ I ref) in respective pixel driving circuits and data signals encoded according to said second colour scale induce current pulses of a high reference current level (HL ∗ I ref).