A device for performing Long Short Term Memory, LSTM, neural network operations, comprising: a plurality of data buffer units arranged in parallel for buffering data, states and results required for the LSTM neural network operations; and a plurality of data processing modules arranged in parallel configured to obtain input data, weights and biases required for operations, from the corresponding data buffer units, to perform the LSTM neural network operations, wherein the plurality of data processing modules correspond one-to-one to the data buffer units; the device being characterized in that each data processing module comprises a data processing control sub-module, a data dependency determination sub-module and a data operation sub-module; wherein the data operation sub-module is configured to perform data operations; wherein the data processing control sub-module is configured to control the data operations performed by the data operation sub-module and control the data dependency determination sub-module to determine whether or not a current operation has a data dependency; wherein the data operation sub-module comprises registers R1, R2, R3, R4 and R5, respectively indicating whether an operation of an input gate, of an forget gate, of an output gate, of a candidate state cell and of a tanh function transformation on an updated state cell, is completed; wherein a non-zero value of any of the registers R1, R2, R3, R4 and R5 indicates that the corresponding operation is completed and a zero value of the register indicates that the corresponding operation is not completed; wherein the data dependency determination sub-module is configured to determine whether there is data dependency in the data operation sub-module twice, comprising: 1) to determine whether there is data dependency among the input gate, the output gate, and the candidate state cell when calculating a new state cell, based on whether the values of the registers R1, R3, and R4 are all non-zero, and 2) to determine whether there is data dependency between the output gate and the tanh function transformation on the updated state cell when calculating an output value, based on whether the values of the registers R2 and R5 are both non-zero. a plurality of data buffer units arranged in parallel for buffering data, states and results required for the LSTM neural network operations; and a plurality of data processing modules arranged in parallel configured to obtain input data, weights and biases required for operations, from the corresponding data buffer units, to perform the LSTM neural network operations, wherein the plurality of data processing modules correspond one-to-one to the data buffer units; the device being characterized in that each data processing module comprises a data processing control sub-module, a data dependency determination sub-module and a data operation sub-module; wherein the data operation sub-module is configured to perform data operations; wherein the data processing control sub-module is configured to control the data operations performed by the data operation sub-module and control the data dependency determination sub-module to determine whether or not a current operation has a data dependency; wherein the data operation sub-module comprises registers R1, R2, R3, R4 and R5, respectively indicating whether an operation of an input gate, of an forget gate, of an output gate, of a candidate state cell and of a tanh function transformation on an updated state cell, is completed; wherein a non-zero value of any of the registers R1, R2, R3, R4 and R5 indicates that the corresponding operation is completed and a zero value of the register indicates that the corresponding operation is not completed; wherein the data dependency determination sub-module is configured to determine whether there is data dependency in the data operation sub-module twice, comprising: 1) to determine whether there is data dependency among the input gate, the output gate, and the candidate state cell when calculating a new state cell, based on whether the values of the registers R1, R3, and R4 are all non-zero, and 2) to determine whether there is data dependency between the output gate and the tanh function transformation on the updated state cell when calculating an output value, based on whether the values of the registers R2 and R5 are both non-zero. 1) to determine whether there is data dependency among the input gate, the output gate, and the candidate state cell when calculating a new state cell, based on whether the values of the registers R1, R3, and R4 are all non-zero, and 2) to determine whether there is data dependency between the output gate and the tanh function transformation on the updated state cell when calculating an output value, based on whether the values of the registers R2 and R5 are both non-zero.