An integrated RF Power Amplifier circuit, comprising: i) a drive circuit comprising: a) an input node to accept an input signal with respect to a reference voltage Vref, connected to a first gate G1 of a first MOSFET M1, wherein a source of MOSFET M1 is connected to Vref; and b)a plurality of additional MOSFETs M2 to Mn having associated and corresponding gates G2 to Gn, connected in series with the MOSFET M1 to form a transistor stack, wherein the MOSFET M1 is the bottom transistor of the transistor stack, and the MOSFET Mn is the top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to the drain of the top transistor Mn of the transistor stack; ii) a matching, coupling and filtering circuit connected to the output drive node (106; 224), wherein the matching, coupling and filtering circuit is disposed between the output drive node (106; 224) and an external antenna; iii) a corresponding predominantly capacitive element (214, 222)_connected between each gate, G2 to G n, and the reference voltage Vref; and iv) a shunt circuit connected between the output drive node and the reference voltage (202; 104) and configured to have a minimum non-zero impedance value matching the impedance of said drive circuit at a frequency that is a harmonic of a center operation frequency F 0 of the PA. i) a drive circuit comprising: a) an input node to accept an input signal with respect to a reference voltage Vref, connected to a first gate G1 of a first MOSFET M1, wherein a source of MOSFET M1 is connected to Vref; and b)a plurality of additional MOSFETs M2 to Mn having associated and corresponding gates G2 to Gn, connected in series with the MOSFET M1 to form a transistor stack, wherein the MOSFET M1 is the bottom transistor of the transistor stack, and the MOSFET Mn is the top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to the drain of the top transistor Mn of the transistor stack; a) an input node to accept an input signal with respect to a reference voltage Vref, connected to a first gate G1 of a first MOSFET M1, wherein a source of MOSFET M1 is connected to Vref; and b)a plurality of additional MOSFETs M2 to Mn having associated and corresponding gates G2 to Gn, connected in series with the MOSFET M1 to form a transistor stack, wherein the MOSFET M1 is the bottom transistor of the transistor stack, and the MOSFET Mn is the top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to the drain of the top transistor Mn of the transistor stack; ii) a matching, coupling and filtering circuit connected to the output drive node (106; 224), wherein the matching, coupling and filtering circuit is disposed between the output drive node (106; 224) and an external antenna; iii) a corresponding predominantly capacitive element (214, 222)_connected between each gate, G2 to G n, and the reference voltage Vref; and iv) a shunt circuit connected between the output drive node and the reference voltage (202; 104) and configured to have a minimum non-zero impedance value matching the impedance of said drive circuit at a frequency that is a harmonic of a center operation frequency F 0 of the PA.