A method for manufacturing a semiconductor device, the semiconductor device being a vertical type MOSFET, the method comprising the steps of: preparing a substrate (1, 31) having a main surface on which a silicon carbide layer (2, 3, 4) is formed; said silicon carbide layer including an n-type epitaxial layer serving as a breakdown voltage holding layer, a p-type semiconductor layer formed by ion implantation on said n-type epitaxial layer, and an n-type source contact layer formed by ion implantation on said p-type semiconductor layer, performing a first trench forming step by forming a trench having side walls substantially perpendicular to the main surface of substrate, performing a second trench forming step by thermal etching to exhibit a predetermined crystal plane in each of the n-type epitaxial layer, the p-type semiconductor layer, and the n-type source contact layer, by thermally etching the side walls of said trench having a bottom portion in said n-type epitaxial layer such that an end surface is spontaneously formed as a side surface of said trench, said end surface being inclined relative to a main surface of said silicon carbide layer (2, 3, 4) by removing a portion of said main surface of said silicon carbide layer (2, 3, 4) by etching by heating said silicon carbide layer (2, 3, 4) while exposing said silicon carbide layer (2, 3, 4) to a reaction gas containing oxygen and chlorine; forming a gate insulating film by thermal oxidation of said end surface, and a crystal plane constituting said end surface being one of a plane and a plane, or a plane having an off-angle of not less than -3° and not more than 3° relative to one of the plane and the plane in any crystal orientation in a case where said silicon carbide layer (2, 3, 4) is of hexagonal crystal type, and being a plane, or a plane having an off-angle of not less than -3° and not more than 3° relative to the plane in any crystal orientation in a case where said silicon carbide layer (2, 3, 4) is of cubic crystal type, forming a field relaxing region at the bottom of the trench by implanting ions of p-type impurity, forming a gate electrode on the gate insulating film, forming a source electrode in ohmic contact with the p type contact region and the source contact layer, and forming a drain electrode on the backside of the substrate. preparing a substrate (1, 31) having a main surface on which a silicon carbide layer (2, 3, 4) is formed; said silicon carbide layer including an n-type epitaxial layer serving as a breakdown voltage holding layer, a p-type semiconductor layer formed by ion implantation on said n-type epitaxial layer, and an n-type source contact layer formed by ion implantation on said p-type semiconductor layer, performing a first trench forming step by forming a trench having side walls substantially perpendicular to the main surface of substrate, performing a second trench forming step by thermal etching to exhibit a predetermined crystal plane in each of the n-type epitaxial layer, the p-type semiconductor layer, and the n-type source contact layer, by thermally etching the side walls of said trench having a bottom portion in said n-type epitaxial layer such that an end surface is spontaneously formed as a side surface of said trench, said end surface being inclined relative to a main surface of said silicon carbide layer (2, 3, 4) by removing a portion of said main surface of said silicon carbide layer (2, 3, 4) by etching by heating said silicon carbide layer (2, 3, 4) while exposing said silicon carbide layer (2, 3, 4) to a reaction gas containing oxygen and chlorine; forming a gate insulating film by thermal oxidation of said end surface, and a crystal plane constituting said end surface being one of a plane and a plane, or a plane having an off-angle of not less than -3° and not more than 3° relative to one of the plane and the plane in any crystal orientation in a case where said silicon carbide layer (2, 3, 4) is of hexagonal crystal type, and being a plane, or a plane having an off-angle of not less than -3° and not more than 3° relative to the plane in any crystal orientation in a case where said silicon carbide layer (2, 3, 4) is of cubic crystal type, forming a field relaxing region at the bottom of the trench by implanting ions of p-type impurity, forming a gate electrode on the gate insulating film, forming a source electrode in ohmic contact with the p type contact region and the source contact layer, and forming a drain electrode on the backside of the substrate.