An apparatus comprising: a microcode store having a number of microcoded instruction implementations; a central processing unit in communication with the microcode store, the central processing unit utilizing transport triggered architecture and configured to execute microcoded instructions that allow a single instruction to be implemented as multiple instructions; wherein the central processing unit further comprises a control unit configured to load a microcoded instruction from a program and a microcoded instruction implementation from the microcode store; a first functional unit and a second functional unit; a useful entry point into the microcode store of a microcoded instruction implementation, wherein the control unit is configured to transfer the useful entry point to a program counter of the central processing unit; and wherein the useful entry point is used by the central processing unit to load a microcoded instruction implementation from the microcode store; the central processing unit being arranged to: determine whether the instruction type of the microcoded instruction implementation loaded from the microcode store is at least one of a return, non-microcoded, and microcoded type instruction; responsive to a determination that the instruction is a microcoded type instruction, using a branch and link operation to save a state of a current execution point in the microcoded instruction implementation; and repeating the loading, transferring, and determining steps; and responsive to a determination that the instruction is a non-microcoded type instruction, transferring data between the first functional unit and the second functional unit; and repeating the loading, transferring, and determining steps wherein a next instruction in the microcoded instruction implementation is loaded. a microcode store having a number of microcoded instruction implementations; a central processing unit in communication with the microcode store, the central processing unit utilizing transport triggered architecture and configured to execute microcoded instructions that allow a single instruction to be implemented as multiple instructions; wherein the central processing unit further comprises a control unit configured to load a microcoded instruction from a program and a microcoded instruction implementation from the microcode store; a first functional unit and a second functional unit; a useful entry point into the microcode store of a microcoded instruction implementation, wherein the control unit is configured to transfer the useful entry point to a program counter of the central processing unit; and wherein the useful entry point is used by the central processing unit to load a microcoded instruction implementation from the microcode store; the central processing unit being arranged to: determine whether the instruction type of the microcoded instruction implementation loaded from the microcode store is at least one of a return, non-microcoded, and microcoded type instruction; responsive to a determination that the instruction is a microcoded type instruction, using a branch and link operation to save a state of a current execution point in the microcoded instruction implementation; and repeating the loading, transferring, and determining steps; and determine whether the instruction type of the microcoded instruction implementation loaded from the microcode store is at least one of a return, non-microcoded, and microcoded type instruction; responsive to a determination that the instruction is a microcoded type instruction, using a branch and link operation to save a state of a current execution point in the microcoded instruction implementation; and repeating the loading, transferring, and determining steps; and responsive to a determination that the instruction is a non-microcoded type instruction, transferring data between the first functional unit and the second functional unit; and repeating the loading, transferring, and determining steps wherein a next instruction in the microcoded instruction implementation is loaded.