A control circuit for a neural network system, the control circuit comprising: a first multiply accumulate circuit comprising n memristive cells (c11~cn1), wherein first terminals of the n memristive cells (c11~cn1) receive a supply voltage (Vs), second terminals of the n memristive cells (c11~cn1) are connected with a first bit line, and control terminals of the n memristive cells (c11~cn1) are respectively connected with n word lines (WL1~WLn); a first neuron value storage circuit connected with the n word lines (WL1~WLn), and comprising n registers (411~41n), wherein n neuron values (Din_1~Din_n) of a first layer are stored in the corresponding registers (411~41n); and a first processor connected with the first bit line; wherein in an application phase of the neural network system, the first neuron value storage circuit controls the n word lines (WL1~WLn) according to binary codes of the n neuron values (Din_1~Din_n), so that the first multiply accumulate circuit generates plural first bitline currents (I BL1) to the first processor through the first bit line, wherein after the first processor performs an analog computation on the plural first bitline currents (I BL1) to covert the plural first bitline currents (I BL1) into an output current (I out), the output current (I out) is converted into a first neuron value (Do_1) of a second layer; wherein the n word lines (WL1~WLn) are activated or inactivated in response to the binary codes of the neuron values (Din_1~Din_n), a first portion of the n memristive cells (c11~cn1) corresponding to the activated word lines generates cell currents, and a second portion of the n memristive cells (c11~cn1) corresponding to the inactivated word lines does not generate the cell current, wherein the binary codes of the n neuron values (Din_1~Din_n) of the first layer are L-bit values, and the first neuron value storage circuit sequentially provides one bit of the n neuron values (Din_1~Din_n) for L times to control the n word lines (WL1~WLn) of the first multiply accumulate circuit, so that the first multiply accumulate circuit generates the first bitline currents (I BL1) for L times. a first multiply accumulate circuit comprising n memristive cells (c11~cn1), wherein first terminals of the n memristive cells (c11~cn1) receive a supply voltage (Vs), second terminals of the n memristive cells (c11~cn1) are connected with a first bit line, and control terminals of the n memristive cells (c11~cn1) are respectively connected with n word lines (WL1~WLn); a first neuron value storage circuit connected with the n word lines (WL1~WLn), and comprising n registers (411~41n), wherein n neuron values (Din_1~Din_n) of a first layer are stored in the corresponding registers (411~41n); and a first processor connected with the first bit line; wherein in an application phase of the neural network system, the first neuron value storage circuit controls the n word lines (WL1~WLn) according to binary codes of the n neuron values (Din_1~Din_n), so that the first multiply accumulate circuit generates plural first bitline currents (I BL1) to the first processor through the first bit line, wherein after the first processor performs an analog computation on the plural first bitline currents (I BL1) to covert the plural first bitline currents (I BL1) into an output current (I out), the output current (I out) is converted into a first neuron value (Do_1) of a second layer; wherein the n word lines (WL1~WLn) are activated or inactivated in response to the binary codes of the neuron values (Din_1~Din_n), a first portion of the n memristive cells (c11~cn1) corresponding to the activated word lines generates cell currents, and a second portion of the n memristive cells (c11~cn1) corresponding to the inactivated word lines does not generate the cell current, wherein the binary codes of the n neuron values (Din_1~Din_n) of the first layer are L-bit values, and the first neuron value storage circuit sequentially provides one bit of the n neuron values (Din_1~Din_n) for L times to control the n word lines (WL1~WLn) of the first multiply accumulate circuit, so that the first multiply accumulate circuit generates the first bitline currents (I BL1) for L times.