A differential amplifier, comprising: a first amplifier stage, configured to generate first stage differential output signals (N1, N2) based on input differential signals (INP, INM); a bias circuit, coupled to the first amplifier stage and a ground, comprising a bias current source and first and second control transistors coupled to the ground through the bias current source, configured to provide a bias current with a desired quiescent current level by the bias current source, and bias the first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair configured to receive the first stage differential output signals; a second amplifier stage (12a, 12b), coupled to the bias circuit, comprising first and second output amplifier stages configured to output second stage differential output signals (OUTP, OUTM), wherein each of the first and second output amplifier stages comprises complementary push (MP9, MP10) and pull (MN5, MN6) transistors coupled in series to each other, and respective mirror transistors (MP7, MP8) coupled to the push transistors, each mirror transistor being configured to mirror one of the first and second currents to the respective push device, and the mirrored current being configured to bias the respective pull transistor; and a voltage common mode feedback circuit, coupled to the second amplifier stage and the first amplifier stage, configured to adjust the second stage differential output signals to match with a reference voltage (V 0) by feeding back a voltage difference of an averaged voltage of the second stage differential output signals and the reference voltage to the first amplifier stage, and comprising: a reference voltage generation circuit, coupled to the voltage common mode feedback circuit, comprising a replica circuit of the first and second amplifier stages, configured to generate a fixed voltage replica as the reference voltage to the voltage common mode feedback circuit. a first amplifier stage, configured to generate first stage differential output signals (N1, N2) based on input differential signals (INP, INM); a bias circuit, coupled to the first amplifier stage and a ground, comprising a bias current source and first and second control transistors coupled to the ground through the bias current source, configured to provide a bias current with a desired quiescent current level by the bias current source, and bias the first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair configured to receive the first stage differential output signals; a second amplifier stage (12a, 12b), coupled to the bias circuit, comprising first and second output amplifier stages configured to output second stage differential output signals (OUTP, OUTM), wherein each of the first and second output amplifier stages comprises complementary push (MP9, MP10) and pull (MN5, MN6) transistors coupled in series to each other, and respective mirror transistors (MP7, MP8) coupled to the push transistors, each mirror transistor being configured to mirror one of the first and second currents to the respective push device, and the mirrored current being configured to bias the respective pull transistor; and a voltage common mode feedback circuit, coupled to the second amplifier stage and the first amplifier stage, configured to adjust the second stage differential output signals to match with a reference voltage (V 0) by feeding back a voltage difference of an averaged voltage of the second stage differential output signals and the reference voltage to the first amplifier stage, and comprising: a reference voltage generation circuit, coupled to the voltage common mode feedback circuit, comprising a replica circuit of the first and second amplifier stages, configured to generate a fixed voltage replica as the reference voltage to the voltage common mode feedback circuit.