A method of manufacturing a semiconductor device, the method comprising: first, providing a substrate structure including a PMOS region having a first trench and an NMOS region having a second trench, a high-k dielectric layer at a bottom and on sidewalls of the first and second trenches (201, 202), and a first P-type work function adjustment layer on the high-k dielectric layer; thereafter, forming a first protective layer on the substrate structure and a second protective layer on the first protective layer; thereafter, forming a mask layer on the second protective layer; thereafter, removing the portion of the mask layer which is on the NMOS region using a first dry etching process to expose the portion of the second protective layer which is on the NMOS region; thereafter, removing the exposed portion of the second protective layer on the NMOS region to expose the portion of the first protective layer which is on the NMOS region; thereafter, removing the mask layer on the PMOS region using a second dry etching process to expose the second protective layer on the PMOS region; thereafter, removing the portion of the first protective layer and the portion of the first P-type work function adjustment layer which are on the NMOS region, the portion of the first protective layer being removed by a wet etching process; and thereafter, removing the second protective layer and the first protective layer on the PMOS region by a wet etching process, thereafter, forming a second P-type work function adjustment layer on the portion of the first P-type work function adjustment layer which is on the PMOS region and on the portion of the high-k dielectric layer which is on the NMOS region: forming an N-type work function adjustment layer on the second P-type work function adjustment layer; and forming a metal layer on the N-type work function adjustment layer. first, providing a substrate structure including a PMOS region having a first trench and an NMOS region having a second trench, a high-k dielectric layer at a bottom and on sidewalls of the first and second trenches (201, 202), and a first P-type work function adjustment layer on the high-k dielectric layer; thereafter, forming a first protective layer on the substrate structure and a second protective layer on the first protective layer; thereafter, forming a mask layer on the second protective layer; thereafter, removing the portion of the mask layer which is on the NMOS region using a first dry etching process to expose the portion of the second protective layer which is on the NMOS region; thereafter, removing the exposed portion of the second protective layer on the NMOS region to expose the portion of the first protective layer which is on the NMOS region; thereafter, removing the mask layer on the PMOS region using a second dry etching process to expose the second protective layer on the PMOS region; thereafter, removing the portion of the first protective layer and the portion of the first P-type work function adjustment layer which are on the NMOS region, the portion of the first protective layer being removed by a wet etching process; and thereafter, removing the second protective layer and the first protective layer on the PMOS region by a wet etching process, forming a second P-type work function adjustment layer on the portion of the first P-type work function adjustment layer which is on the PMOS region and on the portion of the high-k dielectric layer which is on the NMOS region: forming an N-type work function adjustment layer on the second P-type work function adjustment layer; and forming a metal layer on the N-type work function adjustment layer.