A current repeater (200, 205), comprising: a plurality of first cascode transistors, each first cascode transistor having a first terminal coupled to an internal reference current node carrying an internal reference current (IREF) and supplying a reference voltage and having a gate coupled to a bias voltage source; a plurality of first transistors corresponding on a one-to-one basis with the plurality of first cascode transistors, each first transistor having a terminal coupled to a second terminal of the corresponding first cascode transistor and having a gate coupled to the internal reference current node (VREF); a plurality of second cascode transistors, each second transistor having a first terminal coupled to a feedback reference current node carrying a feedback reference current (IFEEDBK) from a successive current repeater and having a gate coupled to the bias voltage source; a plurality of second transistors corresponding on a one-to-one basis with the plurality of second cascode transistors, each second transistor having a terminal coupled to a second terminal of the corresponding second cascode transistor, the plurality of second transistors being divided into a majority set of the second transistors and a remaining set of the second transistors, wherein the majority set is larger than the remaining set, and wherein the reference current node is coupled to a gate of each second transistor in the majority set, and wherein a gate for each second transistor in the remaining set is configured to generate a feedback voltage (VFBK); a bias circuit configured to generate a first and second bias voltage responsive to a received reference current (IFOR) from a previous current repeater, wherein the gates of the first cascode transistors and the gates of the second cascode transistors are all coupled to the second bias voltage; a third current source configured to generate the internal reference current responsive to the first bias voltage; a fourth current source configured to drive a local feedback reference current to the previous current repeater responsive to the first bias voltage; an error amplifier configured to compare the reference voltage to the feedback voltage to generate an error signal; and a first current source configured to drive a forwarded reference current to the successive current repeater responsive to the error signal and the first bias voltage. a plurality of first cascode transistors, each first cascode transistor having a first terminal coupled to an internal reference current node carrying an internal reference current (IREF) and supplying a reference voltage and having a gate coupled to a bias voltage source; a plurality of first transistors corresponding on a one-to-one basis with the plurality of first cascode transistors, each first transistor having a terminal coupled to a second terminal of the corresponding first cascode transistor and having a gate coupled to the internal reference current node (VREF); a plurality of second cascode transistors, each second transistor having a first terminal coupled to a feedback reference current node carrying a feedback reference current (IFEEDBK) from a successive current repeater and having a gate coupled to the bias voltage source; a plurality of second transistors corresponding on a one-to-one basis with the plurality of second cascode transistors, each second transistor having a terminal coupled to a second terminal of the corresponding second cascode transistor, the plurality of second transistors being divided into a majority set of the second transistors and a remaining set of the second transistors, wherein the majority set is larger than the remaining set, and wherein the reference current node is coupled to a gate of each second transistor in the majority set, and wherein a gate for each second transistor in the remaining set is configured to generate a feedback voltage (VFBK); a bias circuit configured to generate a first and second bias voltage responsive to a received reference current (IFOR) from a previous current repeater, wherein the gates of the first cascode transistors and the gates of the second cascode transistors are all coupled to the second bias voltage; a third current source configured to generate the internal reference current responsive to the first bias voltage; a fourth current source configured to drive a local feedback reference current to the previous current repeater responsive to the first bias voltage; an error amplifier configured to compare the reference voltage to the feedback voltage to generate an error signal; and a first current source configured to drive a forwarded reference current to the successive current repeater responsive to the error signal and the first bias voltage.