A method for preparing a semiconductor structure, comprising: forming an initial semiconductor structure on a substrate; etching the initial semiconductor structure to form an array area structure and a peripheral area structure, heights of the array area structure and the peripheral area structure on the substrate being different, the peripheral area structure comprising a peripheral area gate structure, and the array area structure and the peripheral area structure respectively comprising a first dielectric layer (213, 224, 236, 244, 255), wherein a material of the first dielectric layer (213, 224, 236, 244, 255) comprises silicon nitride; forming an isolation wall surrounding the peripheral area gate structure on the substrate where the peripheral area structure locates, wherein the isolation wall comprises a silicon nitride-silicon oxide-silicon nitride structure; depositing a second dielectric layer (611, 621, 631, 641, 651) on the peripheral area gate structure comprising the isolation wall and on the array area structure, wherein a material of the second dielectric layer (611, 621, 631, 641, 651) comprises silicon oxide; characterized in that, performing thinning processing to the second dielectric layer (611, 621, 631, 641, 651) to reduce a thickness of the second dielectric layer (611, 621, 631, 641, 651) by using a chemical mechanical polishing process; subsequently etching the second dielectric layer (611, 621, 631, 641, 651), the first dielectric layer (213, 224, 236, 244, 255) and the isolation wall with an etching rate ratio of silicon oxide to silicon nitride, wherein the etching rate ratio is 1: 1, to form the semiconductor structure with a flat surface. forming an initial semiconductor structure on a substrate; etching the initial semiconductor structure to form an array area structure and a peripheral area structure, heights of the array area structure and the peripheral area structure on the substrate being different, the peripheral area structure comprising a peripheral area gate structure, and the array area structure and the peripheral area structure respectively comprising a first dielectric layer (213, 224, 236, 244, 255), wherein a material of the first dielectric layer (213, 224, 236, 244, 255) comprises silicon nitride; forming an isolation wall surrounding the peripheral area gate structure on the substrate where the peripheral area structure locates, wherein the isolation wall comprises a silicon nitride-silicon oxide-silicon nitride structure; depositing a second dielectric layer (611, 621, 631, 641, 651) on the peripheral area gate structure comprising the isolation wall and on the array area structure, wherein a material of the second dielectric layer (611, 621, 631, 641, 651) comprises silicon oxide; characterized in that, performing thinning processing to the second dielectric layer (611, 621, 631, 641, 651) to reduce a thickness of the second dielectric layer (611, 621, 631, 641, 651) by using a chemical mechanical polishing process; subsequently etching the second dielectric layer (611, 621, 631, 641, 651), the first dielectric layer (213, 224, 236, 244, 255) and the isolation wall with an etching rate ratio of silicon oxide to silicon nitride, wherein the etching rate ratio is 1: 1, to form the semiconductor structure with a flat surface.