A method of operating a display apparatus comprising a data driver, the method comprising: combining a clock signal and an output image data to form a clock embedded data signal (CEDS); during a first period in which image data is provided to the data driver as part of the clock embedded data signal (CEDS), setting an output differential voltage of a clock embedded data signal (CEDS) to a first voltage value and applying the clock embedded data signal (CEDS) to the data driver, wherein the output differential voltage of the clock embedded data signal (CEDS) relates to a voltage difference between a high level and a low level of the clock embedded data signal (CEDS); and during a second period in which the image data is not provided to the data driver as part of the clock embedded data signal (CEDS) and the clock embedded data signal (CEDS) comprises second data that does not correspond to image data, changing the output differential voltage of the clock embedded data signal (CEDS) to a second voltage value smaller than the first voltage value and applying the clock embedded data signal (CEDS) to the data driver; the method being characterized in that: during the whole first period, each of the high level and the low level of the clock embedded data signal (CEDS) is a fixed level, and the output differential voltage of the clock embedded data signal (CEDS) is maintained to the first voltage value, and during the whole second period, each of the high level (HL2') and the low level of the clock embedded data signal (CEDS) is a fixed level, and the output differential voltage of the clock embedded data signal (CEDS) is maintained to the second voltage value, wherein the method further comprises: during (S100a) the first period, setting a slew rate of the clock embedded data signal (CEDS) to a first time value (TV1'), wherein the slew rate of the clock embedded data signal (CEDS) relates to a time required to transition from one of the high level and the low level of the clock embedded data signal (CEDS) to the other of the high level and the low level of the clock embedded data signal (CEDS); and during the second period, changing the slew rate of the clock embedded data signal (CEDS) applied to the data driver to a second time value (TV2') greater than the first time value (TV1'). combining a clock signal and an output image data to form a clock embedded data signal (CEDS); during a first period in which image data is provided to the data driver as part of the clock embedded data signal (CEDS), setting an output differential voltage of a clock embedded data signal (CEDS) to a first voltage value and applying the clock embedded data signal (CEDS) to the data driver, wherein the output differential voltage of the clock embedded data signal (CEDS) relates to a voltage difference between a high level and a low level of the clock embedded data signal (CEDS); and during a second period in which the image data is not provided to the data driver as part of the clock embedded data signal (CEDS) and the clock embedded data signal (CEDS) comprises second data that does not correspond to image data, changing the output differential voltage of the clock embedded data signal (CEDS) to a second voltage value smaller than the first voltage value and applying the clock embedded data signal (CEDS) to the data driver; the method being characterized in that: during the whole first period, each of the high level and the low level of the clock embedded data signal (CEDS) is a fixed level, and the output differential voltage of the clock embedded data signal (CEDS) is maintained to the first voltage value, and during the whole second period, each of the high level (HL2') and the low level of the clock embedded data signal (CEDS) is a fixed level, and the output differential voltage of the clock embedded data signal (CEDS) is maintained to the second voltage value, during the whole first period, each of the high level and the low level of the clock embedded data signal (CEDS) is a fixed level, and the output differential voltage of the clock embedded data signal (CEDS) is maintained to the first voltage value, and during the whole second period, each of the high level (HL2') and the low level of the clock embedded data signal (CEDS) is a fixed level, and the output differential voltage of the clock embedded data signal (CEDS) is maintained to the second voltage value, wherein the method further comprises: during (S100a) the first period, setting a slew rate of the clock embedded data signal (CEDS) to a first time value (TV1'), wherein the slew rate of the clock embedded data signal (CEDS) relates to a time required to transition from one of the high level and the low level of the clock embedded data signal (CEDS) to the other of the high level and the low level of the clock embedded data signal (CEDS); and during the second period, changing the slew rate of the clock embedded data signal (CEDS) applied to the data driver to a second time value (TV2') greater than the first time value (TV1'). during (S100a) the first period, setting a slew rate of the clock embedded data signal (CEDS) to a first time value (TV1'), wherein the slew rate of the clock embedded data signal (CEDS) relates to a time required to transition from one of the high level and the low level of the clock embedded data signal (CEDS) to the other of the high level and the low level of the clock embedded data signal (CEDS); and during the second period, changing the slew rate of the clock embedded data signal (CEDS) applied to the data driver to a second time value (TV2') greater than the first time value (TV1').