A simulation apparatus that executes a simulation of instruction execution of a program for a target processor that controls a pipeline process, the simulation apparatus comprising: a code converter configured to perform a process to divide a code of the program into prescribed blocks, and to set an execution result of an externally dependent instruction that is an instruction among instructions included in the blocks whose execution process depends on an external environment outside the target processor as a prediction result; a process to perform a function simulation of the instruction execution of the program assuming the prediction result, to obtain timing information representing an execution timing of an instruction included in the block, and to calculate an execution time of the externally dependent instruction in the prediction result, based on a result of the function simulation and the timing information; and a process to generate, based on the result of the function simulation, a host code to make a host processor perform a performance simulation of the instruction execution of the program for the target processor assuming the prediction result; and a simulation executor configured to, when, in an execution result of execution of the generated host code by the host processor, an execution result of the externally dependent instruction included in the host code is different from the prediction result, correct the execution time of the externally dependent instruction in the prediction result by a process to obtain an available delay time of the externally dependent instruction by adding a prescribed delay time of the externally dependent instruction to a remaining execution time of the externally dependent instruction and to subtract an execution time of a next instruction executed next to the externally dependent instruction from the available delay time of the externally dependent instruction, and set the corrected execution time of the externally dependent instruction as the execution time of the externally dependent instruction in the function simulation. a code converter configured to perform a process to divide a code of the program into prescribed blocks, and to set an execution result of an externally dependent instruction that is an instruction among instructions included in the blocks whose execution process depends on an external environment outside the target processor as a prediction result; a process to perform a function simulation of the instruction execution of the program assuming the prediction result, to obtain timing information representing an execution timing of an instruction included in the block, and to calculate an execution time of the externally dependent instruction in the prediction result, based on a result of the function simulation and the timing information; and a process to generate, based on the result of the function simulation, a host code to make a host processor perform a performance simulation of the instruction execution of the program for the target processor assuming the prediction result; and a simulation executor configured to, when, in an execution result of execution of the generated host code by the host processor, an execution result of the externally dependent instruction included in the host code is different from the prediction result, correct the execution time of the externally dependent instruction in the prediction result by a process to obtain an available delay time of the externally dependent instruction by adding a prescribed delay time of the externally dependent instruction to a remaining execution time of the externally dependent instruction and to subtract an execution time of a next instruction executed next to the externally dependent instruction from the available delay time of the externally dependent instruction, and set the corrected execution time of the externally dependent instruction as the execution time of the externally dependent instruction in the function simulation.