A register mapping circuit in a processor device, the register mapping circuit comprising: a rename map table, RMT, comprising a plurality of RMT entries (128 -128) each representing a mapping of a logical register number, LRN, among a plurality of LRNs (LRN 0 -LRN L) to a physical register number, PRN, among a plurality of PRNs (PRN 0 -PRN P); and a sliced reorder buffer, SROB, subdivided into a plurality of SROB slices (150 -150) each corresponding to a respective LRN among the plurality of LRNs, and each comprising a plurality of SROB slice entries (152 -152, 154 -154); the register mapping circuit configured to: detect, within an execution pipeline of the processor device, an uncommitted instruction (I 0) comprising a write instruction to a destination LRN (LRN 0) among the plurality of LRNs; allocate, to the uncommitted instruction, an SROB slice entry (152) among the plurality of SROB slice entries of an SROB slice (150) corresponding to the destination LRN among the plurality of SROB slices of the SROB; receive an indication of a pipeline flush from a target instruction (I 3) within the execution pipeline; and responsive to receiving the indication of the pipeline flush, restore the plurality of RMT entries (128 -128) to a corresponding plurality of prior mapping states, based on parallel walks of the plurality of SROB slices corresponding to LRNs of the plurality of RMT entries (128 -128). a rename map table, RMT, comprising a plurality of RMT entries (128 -128) each representing a mapping of a logical register number, LRN, among a plurality of LRNs (LRN 0 -LRN L) to a physical register number, PRN, among a plurality of PRNs (PRN 0 -PRN P); and a sliced reorder buffer, SROB, subdivided into a plurality of SROB slices (150 -150) each corresponding to a respective LRN among the plurality of LRNs, and each comprising a plurality of SROB slice entries (152 -152, 154 -154); the register mapping circuit configured to: detect, within an execution pipeline of the processor device, an uncommitted instruction (I 0) comprising a write instruction to a destination LRN (LRN 0) among the plurality of LRNs; allocate, to the uncommitted instruction, an SROB slice entry (152) among the plurality of SROB slice entries of an SROB slice (150) corresponding to the destination LRN among the plurality of SROB slices of the SROB; receive an indication of a pipeline flush from a target instruction (I 3) within the execution pipeline; and responsive to receiving the indication of the pipeline flush, restore the plurality of RMT entries (128 -128) to a corresponding plurality of prior mapping states, based on parallel walks of the plurality of SROB slices corresponding to LRNs of the plurality of RMT entries (128 -128). detect, within an execution pipeline of the processor device, an uncommitted instruction (I 0) comprising a write instruction to a destination LRN (LRN 0) among the plurality of LRNs; allocate, to the uncommitted instruction, an SROB slice entry (152) among the plurality of SROB slice entries of an SROB slice (150) corresponding to the destination LRN among the plurality of SROB slices of the SROB; receive an indication of a pipeline flush from a target instruction (I 3) within the execution pipeline; and responsive to receiving the indication of the pipeline flush, restore the plurality of RMT entries (128 -128) to a corresponding plurality of prior mapping states, based on parallel walks of the plurality of SROB slices corresponding to LRNs of the plurality of RMT entries (128 -128).