A processing system comprising: - a plurality of circuits (102, 104, 106) configured to generate a plurality of error signals ( ERR, EB, ERR'); - a plurality of error pads; - a fault collection circuit configured to receive at input said error signals ( ERR, EB, ERR') and generate a respective combined error signal for each of said error pads, wherein said fault collection circuit comprises: - a first combinational logic circuit configured to generate said combined error signal by selectively routing said error signals ( ERR, EB, ERR') to said error pads as a function of a first set of configuring bits characterized in that said processing system comprises at least one safety-critical pad, wherein each safety-critical pad has associated a respective interface circuit configured to set the electric output level of the safety-critical pad to a given safety state as a function of a safety control signal, wherein said fault collection circuit is configured to receive at input said error signals ( ERR, EB, ERR') and generate a respective safety control signal for each of said at least one safety-critical pads, and wherein said fault collection circuit comprises a second combinational logic circuit configured to generate said safety control signal by selectively routing said combined error signals to said safety-critical pads as a function of a second set of configuring bits. - a plurality of circuits (102, 104, 106) configured to generate a plurality of error signals ( ERR, EB, ERR'); - a plurality of error pads; - a fault collection circuit configured to receive at input said error signals ( ERR, EB, ERR') and generate a respective combined error signal for each of said error pads, wherein said fault collection circuit comprises: - a first combinational logic circuit configured to generate said combined error signal by selectively routing said error signals ( ERR, EB, ERR') to said error pads as a function of a first set of configuring bits characterized in that said processing system comprises at least one safety-critical pad, wherein each safety-critical pad has associated a respective interface circuit configured to set the electric output level of the safety-critical pad to a given safety state as a function of a safety control signal, wherein said fault collection circuit is configured to receive at input said error signals ( ERR, EB, ERR') and generate a respective safety control signal for each of said at least one safety-critical pads, and wherein said fault collection circuit comprises a second combinational logic circuit configured to generate said safety control signal by selectively routing said combined error signals to said safety-critical pads as a function of a second set of configuring bits. - a first combinational logic circuit configured to generate said combined error signal by selectively routing said error signals ( ERR, EB, ERR') to said error pads as a function of a first set of configuring bits characterized in that said processing system comprises at least one safety-critical pad, wherein each safety-critical pad has associated a respective interface circuit configured to set the electric output level of the safety-critical pad to a given safety state as a function of a safety control signal, wherein said fault collection circuit is configured to receive at input said error signals ( ERR, EB, ERR') and generate a respective safety control signal for each of said at least one safety-critical pads, and wherein said fault collection circuit comprises a second combinational logic circuit configured to generate said safety control signal by selectively routing said combined error signals to said safety-critical pads as a function of a second set of configuring bits.