An integrated circuit comprising an embedded memory, the integrated circuit comprising: a memory interface circuit, comprising: a plurality of interface pins, arranged to receive at least a clock signal, a non-clock signal, and a setup-hold time control setting; and a programmable path delay circuit, arranged to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting, wherein the clock path is arranged to deliver the clock signal, and the non-clock path is arranged to deliver the non-clock signal; wherein the programmable path delay circuit is arranged to control the path delay of the clock path according to the setup-hold time control setting; wherein the programmable path delay circuit comprises: a base delay circuit, arranged in between a first node and a second node to receive the clock signal, and apply a programmable delay amount to the clock signal; a first delay control circuit, comprising a plurality of first transistors connected in parallel between the first node of the base delay circuit and a supply voltage, wherein a number of turned-on first transistors in the first delay control circuit is controlled by the setup-hold time control setting; and a second delay control circuit, comprising a plurality of second transistors connected in parallel between the second node of the base delay circuit and a ground voltage, wherein a number of turned-on second transistors in the second delay control circuit is controlled by the setup-hold time control setting; wherein the programmable delay amount is set by the number of turned-on first transistors in the first delay control circuit and the number of turned-on second transistors in the second delay control circuit; a cell array, comprising a plurality of memory cells; and a peripheral circuit, arranged to access the cell array according to at least the clock signal provided from the clock path circuit and the non-clock signal provided from the non-clock path. a memory interface circuit, comprising: a plurality of interface pins, arranged to receive at least a clock signal, a non-clock signal, and a setup-hold time control setting; and a programmable path delay circuit, arranged to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting, wherein the clock path is arranged to deliver the clock signal, and the non-clock path is arranged to deliver the non-clock signal; a plurality of interface pins, arranged to receive at least a clock signal, a non-clock signal, and a setup-hold time control setting; and a programmable path delay circuit, arranged to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting, wherein the clock path is arranged to deliver the clock signal, and the non-clock path is arranged to deliver the non-clock signal; wherein the programmable path delay circuit is arranged to control the path delay of the clock path according to the setup-hold time control setting; wherein the programmable path delay circuit comprises: a base delay circuit, arranged in between a first node and a second node to receive the clock signal, and apply a programmable delay amount to the clock signal; a first delay control circuit, comprising a plurality of first transistors connected in parallel between the first node of the base delay circuit and a supply voltage, wherein a number of turned-on first transistors in the first delay control circuit is controlled by the setup-hold time control setting; and a second delay control circuit, comprising a plurality of second transistors connected in parallel between the second node of the base delay circuit and a ground voltage, wherein a number of turned-on second transistors in the second delay control circuit is controlled by the setup-hold time control setting; a base delay circuit, arranged in between a first node and a second node to receive the clock signal, and apply a programmable delay amount to the clock signal; a first delay control circuit, comprising a plurality of first transistors connected in parallel between the first node of the base delay circuit and a supply voltage, wherein a number of turned-on first transistors in the first delay control circuit is controlled by the setup-hold time control setting; and a second delay control circuit, comprising a plurality of second transistors connected in parallel between the second node of the base delay circuit and a ground voltage, wherein a number of turned-on second transistors in the second delay control circuit is controlled by the setup-hold time control setting; wherein the programmable delay amount is set by the number of turned-on first transistors in the first delay control circuit and the number of turned-on second transistors in the second delay control circuit; a cell array, comprising a plurality of memory cells; and a peripheral circuit, arranged to access the cell array according to at least the clock signal provided from the clock path circuit and the non-clock signal provided from the non-clock path.