A semiconductor device comprising: a semiconductor substrate including a memory cell area and a logic circuit area; an isolation trench formed in the semiconductor substrate, the isolation trench defining a first active region in the memory cell area and a second active region in the logic circuit area; a shallow trench isolation film formed in the isolation trench and including a step formed at a position between the first active region and the second active region; a floating gate (FG, 7) and a control gate (CG, 9) formed above the first active region and extending onto an upper surface of the shallow trench isolation film in an area nearby the first active region; an inter-gate insulating film formed on the floating gate (FG, 7), the control gate (CG, 9) being formed on the inter-gate insulating film; a gate electrode (G, 9) of a MOS transistor traverses the second active region and extends on the shallow trench isolation film; wherein a height of a first flat surface of the shallow trench isolation film in the memory cell area between a surface of the first active region and the step is lower than a height of a second flat surface of the shallow trench isolation film in the logic circuit area between a surface of the second active region and the step the height of the second flat surface of the shallow trench isolation film in the logic circuit area is higher than a height of a surface of the second active region; an edge of the floating gate is located on the upper surface of the shallow trench isolation film and between the step and the first active region; and the step is formed by a difference between the height of the first flat surface and the height of the second flat surface, characterised in comprising: a first concave portion formed in the shallow trench isolation film around the first active region; and a second concave portion formed in the shallow trench isolation film around the second active region. a semiconductor substrate including a memory cell area and a logic circuit area; an isolation trench formed in the semiconductor substrate, the isolation trench defining a first active region in the memory cell area and a second active region in the logic circuit area; a shallow trench isolation film formed in the isolation trench and including a step formed at a position between the first active region and the second active region; a floating gate (FG, 7) and a control gate (CG, 9) formed above the first active region and extending onto an upper surface of the shallow trench isolation film in an area nearby the first active region; an inter-gate insulating film formed on the floating gate (FG, 7), the control gate (CG, 9) being formed on the inter-gate insulating film; a gate electrode (G, 9) of a MOS transistor traverses the second active region and extends on the shallow trench isolation film; wherein a height of a first flat surface of the shallow trench isolation film in the memory cell area between a surface of the first active region and the step is lower than a height of a second flat surface of the shallow trench isolation film in the logic circuit area between a surface of the second active region and the step the height of the second flat surface of the shallow trench isolation film in the logic circuit area is higher than a height of a surface of the second active region; an edge of the floating gate is located on the upper surface of the shallow trench isolation film and between the step and the first active region; and the step is formed by a difference between the height of the first flat surface and the height of the second flat surface, characterised in comprising: a first concave portion formed in the shallow trench isolation film around the first active region; and a second concave portion formed in the shallow trench isolation film around the second active region. a first concave portion formed in the shallow trench isolation film around the first active region; and a second concave portion formed in the shallow trench isolation film around the second active region.