A method of forming a semiconductor structure comprising: forming a high dielectric constant, high-k, gate dielectric layer comprising a dielectric material having a dielectric constant greater than 4.0 directly on a doped semiconductor well located in a semiconductor substrate; forming a metal gate layer directly on a first portion of said high-k gate dielectric layer; depositing a metal layer directly on said metal gate layer and a second portion of said high-k gate dielectric layer, the metal layer comprising a group IIA element or a group IIIB element, forming a dielectric metal oxide layer directly on said second portion of said high-k dielectric layer through oxidation of a portion of said metal layer that is in direct contact with said second portion of said high-k dielectric layer, while not oxidizing another portion of said metal layer overlying said metal gate layer; and forming a conductive gate material layer directly on said metal layer and said dielectric metal oxide layer to thereby form: a first field effect transistor including a first gate stack, wherein said first gate stack includes, from bottom to top, a first high dielectric constant, high-k, gate dielectric comprising said dielectric material, a metal gate portion comprising a same material as said metal gate layer, at least one metal portion comprising a same material as said metal layer, and a first conductive gate material portion; and a second field effect transistor including a second gate stack, wherein said second gate stack includes, from bottom to top, a second high-k gate dielectric comprising said dielectric material, a dielectric metal oxide portion comprising a same material as said dielectric metal oxide layer, and a second conductive gate material portion, wherein said first field effect transistor and said second field effect transistor have different threshold voltages, wherein a first portion of said doped semiconductor well abutting said first high-k gate dielectric and a second portion of said doped semiconductor well abutting said second high-k gate dielectric have a same dopant concentration and doping type. forming a high dielectric constant, high-k, gate dielectric layer comprising a dielectric material having a dielectric constant greater than 4.0 directly on a doped semiconductor well located in a semiconductor substrate; forming a metal gate layer directly on a first portion of said high-k gate dielectric layer; depositing a metal layer directly on said metal gate layer and a second portion of said high-k gate dielectric layer, the metal layer comprising a group IIA element or a group IIIB element, forming a dielectric metal oxide layer directly on said second portion of said high-k dielectric layer through oxidation of a portion of said metal layer that is in direct contact with said second portion of said high-k dielectric layer, while not oxidizing another portion of said metal layer overlying said metal gate layer; and forming a conductive gate material layer directly on said metal layer and said dielectric metal oxide layer to thereby form: a first field effect transistor including a first gate stack, wherein said first gate stack includes, from bottom to top, a first high dielectric constant, high-k, gate dielectric comprising said dielectric material, a metal gate portion comprising a same material as said metal gate layer, at least one metal portion comprising a same material as said metal layer, and a first conductive gate material portion; and a second field effect transistor including a second gate stack, wherein said second gate stack includes, from bottom to top, a second high-k gate dielectric comprising said dielectric material, a dielectric metal oxide portion comprising a same material as said dielectric metal oxide layer, and a second conductive gate material portion, wherein said first field effect transistor and said second field effect transistor have different threshold voltages, wherein a first portion of said doped semiconductor well abutting said first high-k gate dielectric and a second portion of said doped semiconductor well abutting said second high-k gate dielectric have a same dopant concentration and doping type. a first field effect transistor including a first gate stack, wherein said first gate stack includes, from bottom to top, a first high dielectric constant, high-k, gate dielectric comprising said dielectric material, a metal gate portion comprising a same material as said metal gate layer, at least one metal portion comprising a same material as said metal layer, and a first conductive gate material portion; and a second field effect transistor including a second gate stack, wherein said second gate stack includes, from bottom to top, a second high-k gate dielectric comprising said dielectric material, a dielectric metal oxide portion comprising a same material as said dielectric metal oxide layer, and a second conductive gate material portion, wherein said first field effect transistor and said second field effect transistor have different threshold voltages, wherein a first portion of said doped semiconductor well abutting said first high-k gate dielectric and a second portion of said doped semiconductor well abutting said second high-k gate dielectric have a same dopant concentration and doping type.