A memory system comprising: a plurality of first memory cells coupled to a first bit line; a voltage bias transistor having a first terminal configured to receive a first system voltage, a second terminal, and a control terminal; a first page buffer coupled to the first bit line and the second terminal of the voltage bias transistor; a common source transistor having a first terminal coupled to the first bit line, a second terminal configured to receive a second system voltage, and a control terminal; and a bias circuit comprising: a charging current reproduce unit coupled to the voltage bias transistor, and configured to generate a charging reference voltage (Vref1) according to a charging current (Ichg) flowing through the voltage bias transistor; a cell current reproduce unit coupled to the common source transistor, and configured to generate a cell reference voltage (Vref2) according to a cell current (Icell) flowing through the common source transistor; a current comparator coupled to the charging current reproduce unit and the cell current reproduce unit, and comprising: a first current generator configured to generate a first replica charging current (I rchg1) according to the charging reference voltage (Vrefl); and a second current generator configured to generate a first replica cell current (I rcell1) according to the cell reference voltage (Vref2); and a bit line bias generator coupled to the current comparator and the first page buffer, and configured to generate a bit line bias voltage (VBLB) according to a difference between the first replica charging current (I rchg1) and the first replica cell current (I rcell1); and wherein: the bit line bias generator raises the bit line bias voltage (VBLB) when the first replica charging current (I rchg1) is greater than the first replica cell current (I rcell1); and the bit line bias generator keeps the bit line bias voltage (VBLB) when the first replica charging current (I rchg1) is substantially equal to the first replica cell current (I rcell1). a plurality of first memory cells coupled to a first bit line; a voltage bias transistor having a first terminal configured to receive a first system voltage, a second terminal, and a control terminal; a first page buffer coupled to the first bit line and the second terminal of the voltage bias transistor; a common source transistor having a first terminal coupled to the first bit line, a second terminal configured to receive a second system voltage, and a control terminal; and a bias circuit comprising: a charging current reproduce unit coupled to the voltage bias transistor, and configured to generate a charging reference voltage (Vref1) according to a charging current (Ichg) flowing through the voltage bias transistor; a cell current reproduce unit coupled to the common source transistor, and configured to generate a cell reference voltage (Vref2) according to a cell current (Icell) flowing through the common source transistor; a current comparator coupled to the charging current reproduce unit and the cell current reproduce unit, and comprising: a first current generator configured to generate a first replica charging current (I rchg1) according to the charging reference voltage (Vrefl); and a second current generator configured to generate a first replica cell current (I rcell1) according to the cell reference voltage (Vref2); and a bit line bias generator coupled to the current comparator and the first page buffer, and configured to generate a bit line bias voltage (VBLB) according to a difference between the first replica charging current (I rchg1) and the first replica cell current (I rcell1); and wherein: a charging current reproduce unit coupled to the voltage bias transistor, and configured to generate a charging reference voltage (Vref1) according to a charging current (Ichg) flowing through the voltage bias transistor; a cell current reproduce unit coupled to the common source transistor, and configured to generate a cell reference voltage (Vref2) according to a cell current (Icell) flowing through the common source transistor; a current comparator coupled to the charging current reproduce unit and the cell current reproduce unit, and comprising: a first current generator configured to generate a first replica charging current (I rchg1) according to the charging reference voltage (Vrefl); and a second current generator configured to generate a first replica cell current (I rcell1) according to the cell reference voltage (Vref2); and a first current generator configured to generate a first replica charging current (I rchg1) according to the charging reference voltage (Vrefl); and a second current generator configured to generate a first replica cell current (I rcell1) according to the cell reference voltage (Vref2); and a bit line bias generator coupled to the current comparator and the first page buffer, and configured to generate a bit line bias voltage (VBLB) according to a difference between the first replica charging current (I rchg1) and the first replica cell current (I rcell1); and wherein: the bit line bias generator raises the bit line bias voltage (VBLB) when the first replica charging current (I rchg1) is greater than the first replica cell current (I rcell1); and the bit line bias generator keeps the bit line bias voltage (VBLB) when the first replica charging current (I rchg1) is substantially equal to the first replica cell current (I rcell1).