A capacitor, comprising: a semiconductor substrate; a first insulating layer disposed under the semiconductor substrate; a first trench group disposed in the semiconductor substrate and the first insulating layer, wherein the first trench group comprises at least two first trenches which penetrate through the semiconductor substrate downward from an upper surface of the semiconductor substrate and enter the first insulating layer, and bottoms of the at least two first trenches are communicated to form a first cavity structure located in the first insulating layer; a laminated structure disposed above the semiconductor substrate, in the first trench group, and in the first cavity structure, wherein the laminated structure comprises m insulating layer(s) and n conductive layers, and the m insulating layer(s) and the n conductive layers form a structure that a conductive layer and an insulating layer are adjacent to each other so that corresponding insulating layer(s) in the m insulating layer(s) electrically isolates the n conductive layers from each other, and m and n are positive integers; a first electrode layer electrically connected to all odd-numbered conductive layer(s) in the n conductive layers disposed in the first trench group; and a second electrode layer electrically connected to all even-numbered conductive layer(s) in the n conductive layers disposed in the first trench group; wherein the capacitor further comprises an etching stop layer and a fifth insulating layer, the etching stop layer is disposed above the semiconductor substrate and the laminated structure, the fifth insulating layer is disposed on an upper surface of the etching stop layer, and the etching stop layer is more resistant to etching than the fifth insulating layer; wherein an insulating layer is not provided under the conductive layer located at a bottom of the first trench group and a bottom of the first cavity structure, and the first electrode layer is directly electrically connected to the conductive layer located at a bottom of the first trench group and a bottom of the first cavity structure, so that the first electrode layer is electrically connected to all the odd-numbered conductive layer(s) in the n conductive layers disposed in the first trench group; and the second electrode layer is electrically connected to all the even-numbered conductive layer(s) in the n conductive layers disposed in the first trench group through at least one second via structure. a semiconductor substrate; a first insulating layer disposed under the semiconductor substrate; a first trench group disposed in the semiconductor substrate and the first insulating layer, wherein the first trench group comprises at least two first trenches which penetrate through the semiconductor substrate downward from an upper surface of the semiconductor substrate and enter the first insulating layer, and bottoms of the at least two first trenches are communicated to form a first cavity structure located in the first insulating layer; a laminated structure disposed above the semiconductor substrate, in the first trench group, and in the first cavity structure, wherein the laminated structure comprises m insulating layer(s) and n conductive layers, and the m insulating layer(s) and the n conductive layers form a structure that a conductive layer and an insulating layer are adjacent to each other so that corresponding insulating layer(s) in the m insulating layer(s) electrically isolates the n conductive layers from each other, and m and n are positive integers; a first electrode layer electrically connected to all odd-numbered conductive layer(s) in the n conductive layers disposed in the first trench group; and a second electrode layer electrically connected to all even-numbered conductive layer(s) in the n conductive layers disposed in the first trench group; wherein the capacitor further comprises an etching stop layer and a fifth insulating layer, the etching stop layer is disposed above the semiconductor substrate and the laminated structure, the fifth insulating layer is disposed on an upper surface of the etching stop layer, and the etching stop layer is more resistant to etching than the fifth insulating layer; wherein an insulating layer is not provided under the conductive layer located at a bottom of the first trench group and a bottom of the first cavity structure, and the first electrode layer is directly electrically connected to the conductive layer located at a bottom of the first trench group and a bottom of the first cavity structure, so that the first electrode layer is electrically connected to all the odd-numbered conductive layer(s) in the n conductive layers disposed in the first trench group; and the second electrode layer is electrically connected to all the even-numbered conductive layer(s) in the n conductive layers disposed in the first trench group through at least one second via structure.