An adaptive logic module (10; 10') comprising: a plurality of look-up tables; circuitry for supplying configuration data (CONFIG DATA, NCONFIG DATA) to the plurality of look-up tables; and circuitry (70, 110, 130) for selectively supplying a set of inputs (E0, E1, F0, F1) to the plurality of look-up tables, wherein the circuitry (70, 110, 130) for selectively supplying the set of inputs (E0, E1, F0, F1) is controllable to select a number of the set of inputs (E0, E1, F0, F1) that are applied in parallel to the plurality of look-up tables so that depth of memory implemented by the plurality of look-up tables can be varied, wherein the circuitry (70, 110, 130) for selectively supplying the set of inputs (E0, E1, F0, F1) comprises: a first multiplexer that receives a first subset of the inputs (E0, F1) and a first output signal (READ-DATA) from one of the look-up tables; a first register that registers an output of the first multiplexer; a second multiplexer that receives a second subset of the inputs (E1, F0) and a second output signal from one of the look-up tables [, the inputs of said first subset being different from the inputs of the second subset]; a second register that registers an output of the second multiplexer; and a third multiplexer that receives the registered output of the first multiplexer and the registered output of the second multiplexer over register feedback paths (110a, 110b), wherein an output of the third multiplexer is provided to a subset (20-5, 20-6, 20-7, 20-8) of the plurality of look-up tables as an input in the set of inputs (E0, E1, F0, F1). a plurality of look-up tables; circuitry for supplying configuration data (CONFIG DATA, NCONFIG DATA) to the plurality of look-up tables; and circuitry (70, 110, 130) for selectively supplying a set of inputs (E0, E1, F0, F1) to the plurality of look-up tables, wherein the circuitry (70, 110, 130) for selectively supplying the set of inputs (E0, E1, F0, F1) is controllable to select a number of the set of inputs (E0, E1, F0, F1) that are applied in parallel to the plurality of look-up tables so that depth of memory implemented by the plurality of look-up tables can be varied, wherein the circuitry (70, 110, 130) for selectively supplying the set of inputs (E0, E1, F0, F1) comprises: a first multiplexer that receives a first subset of the inputs (E0, F1) and a first output signal (READ-DATA) from one of the look-up tables; a first register that registers an output of the first multiplexer; a second multiplexer that receives a second subset of the inputs (E1, F0) and a second output signal from one of the look-up tables [, the inputs of said first subset being different from the inputs of the second subset]; a second register that registers an output of the second multiplexer; and a third multiplexer that receives the registered output of the first multiplexer and the registered output of the second multiplexer over register feedback paths (110a, 110b), wherein an output of the third multiplexer is provided to a subset (20-5, 20-6, 20-7, 20-8) of the plurality of look-up tables as an input in the set of inputs (E0, E1, F0, F1). a first multiplexer that receives a first subset of the inputs (E0, F1) and a first output signal (READ-DATA) from one of the look-up tables; a first register that registers an output of the first multiplexer; a second multiplexer that receives a second subset of the inputs (E1, F0) and a second output signal from one of the look-up tables [, the inputs of said first subset being different from the inputs of the second subset]; a second register that registers an output of the second multiplexer; and a third multiplexer that receives the registered output of the first multiplexer and the registered output of the second multiplexer over register feedback paths (110a, 110b), wherein an output of the third multiplexer is provided to a subset (20-5, 20-6, 20-7, 20-8) of the plurality of look-up tables as an input in the set of inputs (E0, E1, F0, F1).