An apparatus comprising: a first current mirror circuit including a first leg and a second leg, wherein a first current flowing through the first leg from a charge pump output node to a ground node is mirrored to a second current flowing through the second leg to the ground node, wherein the first current is controlled by a charge pump input signal, wherein a gate of a mirror transistor of the second leg is coupled to a bias node and to a gate of a mirror transistor of the first leg; and a first replica circuit that is substantially structurally identical to the first leg, wherein the replica circuit receives an inverted version of the charge pump input signal, wherein a gate of a transistor of the replica circuit is coupled to the bias node; a second current mirror circuit including a third leg and a fourth leg, wherein a third current flowing through the third leg from the supply node to the charge pump output node is mirrored to a fourth current flowing from the supply node and through the fourth leg, wherein the third current is controlled by a second charge pump input signal, and wherein a gate of a mirror transistor of the fourth leg is coupled to a second bias node and to a gate of a mirror transistor of the third leg; and a second replica circuit that is substantially structurally identical to the third leg of the second current mirror circuit but that conducts a second replica current from the supply node to the ground node, wherein the second replica current is controlled by an inverted version of the second charge pump input signal, and wherein a gate of a transistor of the second replica circuit is coupled to the second bias node. a first current mirror circuit including a first leg and a second leg, wherein a first current flowing through the first leg from a charge pump output node to a ground node is mirrored to a second current flowing through the second leg to the ground node, wherein the first current is controlled by a charge pump input signal, wherein a gate of a mirror transistor of the second leg is coupled to a bias node and to a gate of a mirror transistor of the first leg; and a first replica circuit that is substantially structurally identical to the first leg, wherein the replica circuit receives an inverted version of the charge pump input signal, wherein a gate of a transistor of the replica circuit is coupled to the bias node; a second current mirror circuit including a third leg and a fourth leg, wherein a third current flowing through the third leg from the supply node to the charge pump output node is mirrored to a fourth current flowing from the supply node and through the fourth leg, wherein the third current is controlled by a second charge pump input signal, and wherein a gate of a mirror transistor of the fourth leg is coupled to a second bias node and to a gate of a mirror transistor of the third leg; and a second replica circuit that is substantially structurally identical to the third leg of the second current mirror circuit but that conducts a second replica current from the supply node to the ground node, wherein the second replica current is controlled by an inverted version of the second charge pump input signal, and wherein a gate of a transistor of the second replica circuit is coupled to the second bias node.