A method for heterogeneous computing on a graphics processing unit, GPU, the GPU comprising compute units and comprising or executing a meta scheduler, the method comprising: receiving, with a processor, a pipeline topology of an execution model that defines a data processing algorithm in a platform-independent manner, wherein the pipeline topology identifies producer kernels and consumer kernels, wherein the producer kernels produce data that is to be consumed by the consumer kernels, and wherein the pipeline topology identifies the maximum amount of data that a producer kernel will produce for a given amount of data that the kernel will receive of the pipeline topology; generating, with the processor, object code of the producer and consumer kernels to be executed on the compute units of the GPU; generating, using the identification of producer kernels and consumer kernels and the identified maximum amount of data that a producer kernel will produce for a given amount of data that the kernel will receive of the pipeline topology, with the processor, instructions which define a static scheduling scheme of the kernels for indicating a platform-dependent manner in which the pipeline topology of the execution model is to be implemented on a GPU, wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on a platform of the GPU, wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on the configuration of the GPU, wherein the configuration of the GPU defines at least one of a number of compute units of the GPU and a number of lanes within the GPU for implementing a SIMD programming model; transmitting, with the processor, the instructions for the meta scheduler and the object code of the kernels to the GPU; and executing the object code of the kernels on the compute units of the GPU as directed by the meta scheduler in accordance with the instructions that define the static scheduling schemes. receiving, with a processor, a pipeline topology of an execution model that defines a data processing algorithm in a platform-independent manner, wherein the pipeline topology identifies producer kernels and consumer kernels, wherein the producer kernels produce data that is to be consumed by the consumer kernels, and wherein the pipeline topology identifies the maximum amount of data that a producer kernel will produce for a given amount of data that the kernel will receive of the pipeline topology; generating, with the processor, object code of the producer and consumer kernels to be executed on the compute units of the GPU; generating, using the identification of producer kernels and consumer kernels and the identified maximum amount of data that a producer kernel will produce for a given amount of data that the kernel will receive of the pipeline topology, with the processor, instructions which define a static scheduling scheme of the kernels for indicating a platform-dependent manner in which the pipeline topology of the execution model is to be implemented on a GPU, wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on a platform of the GPU, wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on the configuration of the GPU, wherein the configuration of the GPU defines at least one of a number of compute units of the GPU and a number of lanes within the GPU for implementing a SIMD programming model; transmitting, with the processor, the instructions for the meta scheduler and the object code of the kernels to the GPU; and executing the object code of the kernels on the compute units of the GPU as directed by the meta scheduler in accordance with the instructions that define the static scheduling schemes.