A loop filter for a phase-locked loop comprising: a first switched-capacitor network, coupled to an input node (N IN) of the loop filter; and a second switched-capacitor network, coupled to the input node (N IN) of the loop filter; wherein the input node (N IN) of the loop filter is arranged to receive an input from a charge pump and is selectively coupleable to a current source of the charge pump through a switch of the charge pump; wherein the first switched-capacitor network is coupled between the input node (N IN) of the loop filter and a reference voltage; the second switched-capacitor network is coupled between the input node (N IN) of the loop filter and the reference voltage, and is further arranged to generate an output to an output node (N OUT) of the loop filter; wherein the loop filter further comprises a first switch, coupled between the input node (N IN) of the loop filter and the reference voltage; characterized in that the first switched-capacitor network comprises: a capacitor digital-to-analog converter, CDAC, comprising: a plurality of second switches; and a plurality of unit capacitors (C UNIT), coupled to the second switches, respectively; wherein the second switched-capacitor network comprises: a third switch connected to the reference voltage; a first capacitor (C DN), having a first end connected to the input node and a second end coupled to the third switch; and a fourth switch, between the second end of the first capacitor (C DN) and an output node (N OUT) of the loop filter; wherein the loop filter further comprises: a second capacitor (C H), coupled between the output node (N OUT) of the loop filter and the reference voltage. a first switched-capacitor network, coupled to an input node (N IN) of the loop filter; and a second switched-capacitor network, coupled to the input node (N IN) of the loop filter; wherein the input node (N IN) of the loop filter is arranged to receive an input from a charge pump and is selectively coupleable to a current source of the charge pump through a switch of the charge pump; wherein the first switched-capacitor network is coupled between the input node (N IN) of the loop filter and a reference voltage; the second switched-capacitor network is coupled between the input node (N IN) of the loop filter and the reference voltage, and is further arranged to generate an output to an output node (N OUT) of the loop filter; wherein the loop filter further comprises a first switch, coupled between the input node (N IN) of the loop filter and the reference voltage; characterized in that the first switched-capacitor network comprises: a capacitor digital-to-analog converter, CDAC, comprising: a plurality of second switches; and a plurality of unit capacitors (C UNIT), coupled to the second switches, respectively; wherein the second switched-capacitor network comprises: a third switch connected to the reference voltage; a first capacitor (C DN), having a first end connected to the input node and a second end coupled to the third switch; and a fourth switch, between the second end of the first capacitor (C DN) and an output node (N OUT) of the loop filter; wherein the loop filter further comprises: a second capacitor (C H), coupled between the output node (N OUT) of the loop filter and the reference voltage. a capacitor digital-to-analog converter, CDAC, comprising: a plurality of second switches; and a plurality of unit capacitors (C UNIT), coupled to the second switches, respectively; a plurality of second switches; and a plurality of unit capacitors (C UNIT), coupled to the second switches, respectively; wherein the second switched-capacitor network comprises: a third switch connected to the reference voltage; a first capacitor (C DN), having a first end connected to the input node and a second end coupled to the third switch; and a fourth switch, between the second end of the first capacitor (C DN) and an output node (N OUT) of the loop filter; a third switch connected to the reference voltage; a first capacitor (C DN), having a first end connected to the input node and a second end coupled to the third switch; and a fourth switch, between the second end of the first capacitor (C DN) and an output node (N OUT) of the loop filter; wherein the loop filter further comprises: a second capacitor (C H), coupled between the output node (N OUT) of the loop filter and the reference voltage.