A memory system (100, 400, 500) comprising: a volatile memory (114, 414, 514) that includes a volatile memory array, wherein during an activate operation to the volatile memory (114, 414, 514), the volatile memory (114, 414, 514) is configured to read a page of volatile data from the volatile memory array and store the page of volatile data in data-store latches of the volatile memory (114, 414, 514); a non-volatile memory (118, 418, 518) that includes a non-volatile memory array, wherein during an activate operation to the non-volatile memory (118, 418, 518), the non-volatile memory (118, 418, 518) is configured to read a page of non-volatile data from the non-volatile memory array and store the page of non-volatile data in data-store latches of the non-volatile memory (118, 418, 518), wherein an activate latency of the non-volatile memory (118, 418, 518) is longer than an activate latency of the volatile memory (118, 418, 518); a shared data bus (439, 440, 539, 540) coupled to the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518); and a shared address bus (437, 537) coupled to volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518); the memory system (100, 400, 500) further comprising a memory controller (102, 402, 502) coupled to the shared data bus (439, 440, 539, 540) and the shared address bus (437, 537), wherein the memory controller (102, 402, 502) is configured to: simultaneously initiate activation operations in the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518), including sending an address for the activation operations from the memory controller (102, 402, 502) over the shared address bus (437, 537) to both the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518); and initiate read operations for the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518), wherein the memory controller (102, 402, 502) is configured to receive data for the read operations for the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518) over the shared data bus (439, 440, 539, 540); wherein the memory controller (102, 402, 502) is further configured to, after the activate operation in the volatile memory (114, 414, 514) is complete and while the activate operation in the non-volatile memory (118, 418, 518) is ongoing, initiate a read operation in only the volatile memory (114, 414, 514). a volatile memory (114, 414, 514) that includes a volatile memory array, wherein during an activate operation to the volatile memory (114, 414, 514), the volatile memory (114, 414, 514) is configured to read a page of volatile data from the volatile memory array and store the page of volatile data in data-store latches of the volatile memory (114, 414, 514); a non-volatile memory (118, 418, 518) that includes a non-volatile memory array, wherein during an activate operation to the non-volatile memory (118, 418, 518), the non-volatile memory (118, 418, 518) is configured to read a page of non-volatile data from the non-volatile memory array and store the page of non-volatile data in data-store latches of the non-volatile memory (118, 418, 518), wherein an activate latency of the non-volatile memory (118, 418, 518) is longer than an activate latency of the volatile memory (118, 418, 518); a shared data bus (439, 440, 539, 540) coupled to the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518); and a shared address bus (437, 537) coupled to volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518); the memory system (100, 400, 500) further comprising a memory controller (102, 402, 502) coupled to the shared data bus (439, 440, 539, 540) and the shared address bus (437, 537), wherein the memory controller (102, 402, 502) is configured to: simultaneously initiate activation operations in the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518), including sending an address for the activation operations from the memory controller (102, 402, 502) over the shared address bus (437, 537) to both the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518); and initiate read operations for the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518), wherein the memory controller (102, 402, 502) is configured to receive data for the read operations for the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518) over the shared data bus (439, 440, 539, 540); simultaneously initiate activation operations in the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518), including sending an address for the activation operations from the memory controller (102, 402, 502) over the shared address bus (437, 537) to both the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518); and initiate read operations for the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518), wherein the memory controller (102, 402, 502) is configured to receive data for the read operations for the volatile memory (114, 414, 514) and the non-volatile memory (118, 418, 518) over the shared data bus (439, 440, 539, 540); wherein the memory controller (102, 402, 502) is further configured to, after the activate operation in the volatile memory (114, 414, 514) is complete and while the activate operation in the non-volatile memory (118, 418, 518) is ongoing, initiate a read operation in only the volatile memory (114, 414, 514).