A data receiving circuit for receiving data which are encoded in a Manchester code, comprising: an analog-to-digital converter circuit configured to convert an analog signal received through a communication transmission path to a digital signal based on the Manchester code; an edge detecting module configured to synchronize the digital signal to a clock signal, to produce a synchronized reception signal, to detect rising and falling edges from the synchronized reception signal, and to output an edge detection signal; and a characteristic compensating unit configured to compensate one of rise delay characteristics in which a rising time of the digital signal is longer than a falling time, and fall delay characteristics in which the falling time of the digital signal is longer than the rising time, the characteristic compensating unit comprising: a clock extraction counter configured to execute a predetermined counting operation; and a clock extraction controlling module configured to compare a count value of the clock extraction counter at the timing when the edge detection signal becomes active with a count value of an ideal edge position where there is no jitter and to produce a count value control signal for adjusting the count value of the clock extraction controlling module based on the comparison such that a follow-up width which follows an edge position of the synchronized reception signal is changed according to a deviation width of the edge position, wherein the characteristic compensating unit includes a characteristic-based control element storing module configured to store a characteristic-based control element, and is configured to execute a clock extracting operation based on the characteristic-based control element which is read out from the characteristic-based control element storing module, characterised in that the characteristic compensating unit is configured to perform control for suppressing an output of a reception clock signal and for skipping sampling in case sampling is the third one at 1 bit time of communication data and in case sampling is the second one at 1/2 bit time of communication data. an analog-to-digital converter circuit configured to convert an analog signal received through a communication transmission path to a digital signal based on the Manchester code; an edge detecting module configured to synchronize the digital signal to a clock signal, to produce a synchronized reception signal, to detect rising and falling edges from the synchronized reception signal, and to output an edge detection signal; and a characteristic compensating unit configured to compensate one of rise delay characteristics in which a rising time of the digital signal is longer than a falling time, and fall delay characteristics in which the falling time of the digital signal is longer than the rising time, the characteristic compensating unit comprising: a clock extraction counter configured to execute a predetermined counting operation; and a clock extraction controlling module configured to compare a count value of the clock extraction counter at the timing when the edge detection signal becomes active with a count value of an ideal edge position where there is no jitter and to produce a count value control signal for adjusting the count value of the clock extraction controlling module based on the comparison such that a follow-up width which follows an edge position of the synchronized reception signal is changed according to a deviation width of the edge position, a clock extraction counter configured to execute a predetermined counting operation; and a clock extraction controlling module configured to compare a count value of the clock extraction counter at the timing when the edge detection signal becomes active with a count value of an ideal edge position where there is no jitter and to produce a count value control signal for adjusting the count value of the clock extraction controlling module based on the comparison such that a follow-up width which follows an edge position of the synchronized reception signal is changed according to a deviation width of the edge position, wherein the characteristic compensating unit includes a characteristic-based control element storing module configured to store a characteristic-based control element, and is configured to execute a clock extracting operation based on the characteristic-based control element which is read out from the characteristic-based control element storing module, characterised in that the characteristic compensating unit is configured to perform control for suppressing an output of a reception clock signal and for skipping sampling in case sampling is the third one at 1 bit time of communication data and in case sampling is the second one at 1/2 bit time of communication data.