A cascode switching circuit comprising a normally-on semiconductor device, a normally-off semiconductor device, and a gate driver, wherein: said normally-on semiconductor device and said normally-off semiconductor device each have a gate terminal, a drain terminal, and a source terminal; said gate driver has a first output and a second output; said first output of said gate driver is coupled to said gate terminal of said normally-on semiconductor device; said second output of said gate driver is coupled to said gate terminal of said normally-off semiconductor device; said drain terminal of said normally-off semiconductor device is coupled to said source terminal of said normally-on semiconductor device so that a current path is formed through said normally-on semiconductor device and said normally-off semiconductor device; said gate driver is configured such that a turn-on process of said cascode switching circuit is controlled by controlling said normally-off semiconductor device; a turn-off process of said cascode switching circuit is configured to be controlled by controlling said normally-on semiconductor device; and during said turn-off process of said cascode switching circuit, said gate driver is configured to cause a transition of said cascode switching circuit from ON-state to OFF-state by changing said first output of said gate driver from a first voltage level to a second voltage level to turn off said normally-on semiconductor device, then, after a first predetermined delay time, changing said second output of said gate driver from a third voltage level to a fourth voltage level to turn off said normally-off semiconductor device, and after a second predetermined delay time, changing said first output of said gate driver from said second voltage level to said first voltage level. said normally-on semiconductor device and said normally-off semiconductor device each have a gate terminal, a drain terminal, and a source terminal; said gate driver has a first output and a second output; said first output of said gate driver is coupled to said gate terminal of said normally-on semiconductor device; said second output of said gate driver is coupled to said gate terminal of said normally-off semiconductor device; said drain terminal of said normally-off semiconductor device is coupled to said source terminal of said normally-on semiconductor device so that a current path is formed through said normally-on semiconductor device and said normally-off semiconductor device; said gate driver is configured such that a turn-on process of said cascode switching circuit is controlled by controlling said normally-off semiconductor device; a turn-off process of said cascode switching circuit is configured to be controlled by controlling said normally-on semiconductor device; and during said turn-off process of said cascode switching circuit, said gate driver is configured to cause a transition of said cascode switching circuit from ON-state to OFF-state by changing said first output of said gate driver from a first voltage level to a second voltage level to turn off said normally-on semiconductor device, then, after a first predetermined delay time, changing said second output of said gate driver from a third voltage level to a fourth voltage level to turn off said normally-off semiconductor device, and after a second predetermined delay time, changing said first output of said gate driver from said second voltage level to said first voltage level.