An imaging device comprising: a test signal generator (120, 130) comprising: a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to a test voltage generation circuit; a first reset transistor, wherein a first terminal of the first reset transistor is coupled to the test voltage generation circuit and coupled to the first terminal of the first transfer transistor; a first amplifier transistor, wherein a gate of the first amplifier transistor is coupled to a second terminal of the first reset transistor and a second terminal of the first transfer transistor; a first select transistor coupled to the first amplifier transistor; and a pixel comprising: a first photoelectric conversion element; a second transfer transistor coupled to the first photoelectric conversion element; a second reset transistor configured to discharge electric charges by applying a first predetermined voltage as a voltage supplied from a power line; a second amplifier transistor coupled to the second transfer transistor and the second reset transistor; and a second select transistor coupled to the second amplifier transistor; and a vertical scanning unit (210, 220) configured to generate control signals for the pixel and the test signal generator (120, 130) and output the control signals through a signal line; wherein the vertical scanning unit (210, 220) is disposed on a first chip; wherein the test signal generator (120, 130) and the pixel are disposed on a second chip; and wherein the vertical scanning unit (210, 220) is coupled through the signal line to a gate of the first select transistor and to a gate of the second select transistor via an inter-chip connection terminal. a test signal generator (120, 130) comprising: a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to a test voltage generation circuit; a first reset transistor, wherein a first terminal of the first reset transistor is coupled to the test voltage generation circuit and coupled to the first terminal of the first transfer transistor; a first amplifier transistor, wherein a gate of the first amplifier transistor is coupled to a second terminal of the first reset transistor and a second terminal of the first transfer transistor; a first select transistor coupled to the first amplifier transistor; and a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to a test voltage generation circuit; a first reset transistor, wherein a first terminal of the first reset transistor is coupled to the test voltage generation circuit and coupled to the first terminal of the first transfer transistor; a first amplifier transistor, wherein a gate of the first amplifier transistor is coupled to a second terminal of the first reset transistor and a second terminal of the first transfer transistor; a first select transistor coupled to the first amplifier transistor; and a pixel comprising: a first photoelectric conversion element; a second transfer transistor coupled to the first photoelectric conversion element; a second reset transistor configured to discharge electric charges by applying a first predetermined voltage as a voltage supplied from a power line; a second amplifier transistor coupled to the second transfer transistor and the second reset transistor; and a second select transistor coupled to the second amplifier transistor; and a first photoelectric conversion element; a second transfer transistor coupled to the first photoelectric conversion element; a second reset transistor configured to discharge electric charges by applying a first predetermined voltage as a voltage supplied from a power line; a second amplifier transistor coupled to the second transfer transistor and the second reset transistor; and a second select transistor coupled to the second amplifier transistor; and a vertical scanning unit (210, 220) configured to generate control signals for the pixel and the test signal generator (120, 130) and output the control signals through a signal line; wherein the vertical scanning unit (210, 220) is disposed on a first chip; wherein the test signal generator (120, 130) and the pixel are disposed on a second chip; and wherein the vertical scanning unit (210, 220) is coupled through the signal line to a gate of the first select transistor and to a gate of the second select transistor via an inter-chip connection terminal.