A data synchronization arrangement for exchanging clocked data between different clock domains running in a digital processing equipment at substantially the same clock frequency but at an arbitrary relative phase shift, comprising: a buffer memory with a predetermined limited number of memory locations each af which has a data write port and a data read port, a write select multiplexer having a data input receiving an input data stream (WR-DATA) synchronized with the clock (WR-CLOCK) from a first clock domain, one data output for each of said memory locations and connected to a respective data write port, and one write select input for each data output, a read select multiplexer having one data input for each of said memory locations and connected to a respective data read port, one read select input for each data input, and a data output supplying an output data stream (RD-DATA) synchronized with the clock (RD-CLOCK) from second clock domain, a write select shift register with a number of stages corresponding to the predetermined number of memory locations and an output of the most significant bit stage being looped back to an input of the least significant bit stage, each stage having an output connected to a respective one of the write select inputs of the write select multiplexer, the write select shift register being clocked with the clock (WR-CLOCK) from the first clock domain, a read select shift register with a number of stages corresponding to the predetermined number of memory locations, each stage having an output connected to a respective one of the read select inputs of the read select multiplexer, the read select shift register being clocked with the clock (RD-CLOCK) from the second clock domain, and a bit synchronization circuit, coupled between the output of the most significant bit stage of the write select shift register and an input of the least significant bit stage of the read select shift register, for loading each shift register (16, 18) with a bit pattern that contains only one high logic value; the bit synchronization circuit being effective to introduce a fixed offset between the bit patterns loaded into the shift registers (16, 18) and keep the offset constant during operation. a buffer memory with a predetermined limited number of memory locations each af which has a data write port and a data read port, a write select multiplexer having a data input receiving an input data stream (WR-DATA) synchronized with the clock (WR-CLOCK) from a first clock domain, one data output for each of said memory locations and connected to a respective data write port, and one write select input for each data output, a read select multiplexer having one data input for each of said memory locations and connected to a respective data read port, one read select input for each data input, and a data output supplying an output data stream (RD-DATA) synchronized with the clock (RD-CLOCK) from second clock domain, a write select shift register with a number of stages corresponding to the predetermined number of memory locations and an output of the most significant bit stage being looped back to an input of the least significant bit stage, each stage having an output connected to a respective one of the write select inputs of the write select multiplexer, the write select shift register being clocked with the clock (WR-CLOCK) from the first clock domain, a read select shift register with a number of stages corresponding to the predetermined number of memory locations, each stage having an output connected to a respective one of the read select inputs of the read select multiplexer, the read select shift register being clocked with the clock (RD-CLOCK) from the second clock domain, and a bit synchronization circuit, coupled between the output of the most significant bit stage of the write select shift register and an input of the least significant bit stage of the read select shift register, for loading each shift register (16, 18) with a bit pattern that contains only one high logic value; the bit synchronization circuit being effective to introduce a fixed offset between the bit patterns loaded into the shift registers (16, 18) and keep the offset constant during operation.