A transition minimized differential signaling, TMDS, coding scheme based digital transmitter capable of sending side channel data, the transmitter comprising: a channel zero encoder means for producing channel zero encoded data, said channel zero encoder means having first and second inputs and an output, the first input receiving channel zero primary data (D[7:0], DI (7:0]), the second input receiving a channel zero Data Enable out signal (DE out 0), and the output producing channel zero encoded data based on the channel zero primary data (D[7:0], DI[7:0]) and the channel zero Data Enable out signal (DE out 0); a channel one multiplexing means for multiplexing channel one primary data (D[8:15], DI[8:15]) and channel one side channel data (S[0:7]), said channel one multiplexing means having first and second data inputs, a control input, and an output, the first data input receiving channel one primary data (D[8:15], DI[8:15]), the second data input receiving channel one side channel data (S[0:7]), the control input receiving a Data Enable in signal, and the output providing channel one side channel data (S[0:7]) or channel one primary data (D[8:15], DI[8:15]) depending on the value of the Data Enable in signal; a channel one Data Enable out control logic means for producing a channel one Data Enable out signal (DE out 1) for facilitating the transfer of channel one side channel data (S[0:7]), said channel one Data Enable out control logic means having a first input and an output, the first input receiving a Data Enable in signal, and the output producing a channel one Data Enable out signal (DE out 1); and a channel one encoding means for producing channel one encoded data, said channel one encoding means having first and second inputs and an output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one Data Enable out control logic, the output producing channel one encoded data based on the two inputs. a channel zero encoder means for producing channel zero encoded data, said channel zero encoder means having first and second inputs and an output, the first input receiving channel zero primary data (D[7:0], DI (7:0]), the second input receiving a channel zero Data Enable out signal (DE out 0), and the output producing channel zero encoded data based on the channel zero primary data (D[7:0], DI[7:0]) and the channel zero Data Enable out signal (DE out 0); a channel one multiplexing means for multiplexing channel one primary data (D[8:15], DI[8:15]) and channel one side channel data (S[0:7]), said channel one multiplexing means having first and second data inputs, a control input, and an output, the first data input receiving channel one primary data (D[8:15], DI[8:15]), the second data input receiving channel one side channel data (S[0:7]), the control input receiving a Data Enable in signal, and the output providing channel one side channel data (S[0:7]) or channel one primary data (D[8:15], DI[8:15]) depending on the value of the Data Enable in signal; a channel one Data Enable out control logic means for producing a channel one Data Enable out signal (DE out 1) for facilitating the transfer of channel one side channel data (S[0:7]), said channel one Data Enable out control logic means having a first input and an output, the first input receiving a Data Enable in signal, and the output producing a channel one Data Enable out signal (DE out 1); and a channel one encoding means for producing channel one encoded data, said channel one encoding means having first and second inputs and an output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one Data Enable out control logic, the output producing channel one encoded data based on the two inputs.