An operational amplifier used for a class AB amplifier, the operational amplifier being configured to operate in an offset calibration phase and in a turn-on phase and comprising: a first amplifier stage, configured to generate a pair of first output voltages (V ON1, V OP1) at a pair of first output nodes according to a pair of first input voltages (V IP, V IN); a logic loop circuit, wherein in the offset calibration phase, the logic loop circuit is connected to the pair of first output nodes, and is configured to adjust a difference between the pair of first output voltages (V ON1, V OP1) to be close to zero; wherein in the turn-on phase, the logic loop circuit is turned off and disconnected from the pair of first output nodes; a second amplifier stage, configured to generate a plurality of second output voltages (V ogp1, V ogn1, V ogp2, V ogn2) at a plurality of second output nodes according to a pair of second input voltages at a pair of first input nodes of the second amplifier stage, wherein the pair of the first input nodes is disconnected from the pair of the first output nodes in the offset calibration phase; in the turn-on phase, the pair of the first input nodes is connected to the pair of the first output nodes, and the pair of first output voltages (V ON1, V OP1) serves as the pair of second input voltages; a first output stage circuit and a second output stage circuit, wherein in the offset calibration phase, the first output stage circuit is disconnected from the plurality of second output nodes, and the second output stage circuit is connected to the plurality of second output nodes, and configured to generate a pair of third output voltages at a third pair of output nodes according to the plurality of second output voltages (V ogp1, V ogn1, V ogp2, V ogn2); in the turn-on phase, the first output stage circuit is turned on, configured to receive the plurality of second output voltages (V ogp1, V ogn1, V ogp2, V ogn2) at the plurality of second output nodes to generate a plurality of output voltages (V OP and V ON) at a pair of output nodes of the operational amplifier, the third pair of output nodes is coupled to the pair of output nodes, and the second output stage circuit is turned off; each of the pair of third output voltages produced in the offset calibration phase is close to a corresponding one of the pair of output voltages (V OP and V ON) produced in the turn-on phase; and a first common-mode feedback circuit, coupled to the second amplifier stage and the second output stage circuit, the first common-mode feedback circuit configured to keep an output common-mode voltage (V CPY) of the pair of third output voltages at a predetermined value in the offset calibration phase, and keep an output common-mode voltage of the pair of output voltages (V OP and V ON) at the predetermined value. a first amplifier stage, configured to generate a pair of first output voltages (V ON1, V OP1) at a pair of first output nodes according to a pair of first input voltages (V IP, V IN); a logic loop circuit, wherein in the offset calibration phase, the logic loop circuit is connected to the pair of first output nodes, and is configured to adjust a difference between the pair of first output voltages (V ON1, V OP1) to be close to zero; wherein in the turn-on phase, the logic loop circuit is turned off and disconnected from the pair of first output nodes; a second amplifier stage, configured to generate a plurality of second output voltages (V ogp1, V ogn1, V ogp2, V ogn2) at a plurality of second output nodes according to a pair of second input voltages at a pair of first input nodes of the second amplifier stage, wherein the pair of the first input nodes is disconnected from the pair of the first output nodes in the offset calibration phase; in the turn-on phase, the pair of the first input nodes is connected to the pair of the first output nodes, and the pair of first output voltages (V ON1, V OP1) serves as the pair of second input voltages; a first output stage circuit and a second output stage circuit, wherein in the offset calibration phase, the first output stage circuit is disconnected from the plurality of second output nodes, and the second output stage circuit is connected to the plurality of second output nodes, and configured to generate a pair of third output voltages at a third pair of output nodes according to the plurality of second output voltages (V ogp1, V ogn1, V ogp2, V ogn2); in the turn-on phase, the first output stage circuit is turned on, configured to receive the plurality of second output voltages (V ogp1, V ogn1, V ogp2, V ogn2) at the plurality of second output nodes to generate a plurality of output voltages (V OP and V ON) at a pair of output nodes of the operational amplifier, the third pair of output nodes is coupled to the pair of output nodes, and the second output stage circuit is turned off; each of the pair of third output voltages produced in the offset calibration phase is close to a corresponding one of the pair of output voltages (V OP and V ON) produced in the turn-on phase; and a first common-mode feedback circuit, coupled to the second amplifier stage and the second output stage circuit, the first common-mode feedback circuit configured to keep an output common-mode voltage (V CPY) of the pair of third output voltages at a predetermined value in the offset calibration phase, and keep an output common-mode voltage of the pair of output voltages (V OP and V ON) at the predetermined value.