A delay locked loop unit comprising: a delay line configured to receive a reference clock (Ref Clk) at an input of the delay line and to provide a delayed version of the reference clock (Ref Clk) as a feedback clock; a phase detector coupled to the delay line and configured to provide an output signal (Up/Dn) that is dependent upon a phase difference between the reference clock (Ref Clk) and the feedback clock and that is indicative of a change in a delay associated with the delay line that is needed to reduce the phase difference; and a phase lock determining unit configured to determine a phase lock; characterized by a step size controller coupled to the phase detector and configured to selectably provide one or more step size indications to control a delay step size of the delay line; and in that the delay line comprises one or more delay units (16a, 16b, 16c, 16n), and by a control unit coupled to the delay line and to the step size controller and configured to generate control signals (Delay Ctl 0, Delay Ctl 1, Delay Ctl 2, Delay Ctl x) to program each of the one or more delay units (16a, 16b, 16c, 16n), wherein the control signals (Delay Ctl 0, Delay Ctl 1, Delay Ctl 2) are based upon the one or more step size indications provided by the step size controller and the output signal (Up/Dn) of the phase detector, and in that the step size controller is configured to use larger step sizes during a phase lock acquisition and smaller step sizes upon achieving phase lock, wherein during the phase lock acquisition, in response to detecting that the output signal (Up/Dn) indicates a first change in delay that is needed to reduce the phase difference, the step size controller is configured to provide one or more step size indications corresponding to a first step size to change the delay step size of the delay line to the first step size, and in response to detecting that the output signal (Up/Dn) indicates a second change in delay that is needed to reduce the phase difference, the step size controller is configured to provide one or more second step size indications corresponding to a second step size to change the delay step size of the delay line to the second step size, wherein the first step size is larger than the second step size. a delay line configured to receive a reference clock (Ref Clk) at an input of the delay line and to provide a delayed version of the reference clock (Ref Clk) as a feedback clock; a phase detector coupled to the delay line and configured to provide an output signal (Up/Dn) that is dependent upon a phase difference between the reference clock (Ref Clk) and the feedback clock and that is indicative of a change in a delay associated with the delay line that is needed to reduce the phase difference; and a phase lock determining unit configured to determine a phase lock; characterized by a step size controller coupled to the phase detector and configured to selectably provide one or more step size indications to control a delay step size of the delay line; and in that the delay line comprises one or more delay units (16a, 16b, 16c, 16n), and by a control unit coupled to the delay line and to the step size controller and configured to generate control signals (Delay Ctl 0, Delay Ctl 1, Delay Ctl 2, Delay Ctl x) to program each of the one or more delay units (16a, 16b, 16c, 16n), wherein the control signals (Delay Ctl 0, Delay Ctl 1, Delay Ctl 2) are based upon the one or more step size indications provided by the step size controller and the output signal (Up/Dn) of the phase detector, and in that the step size controller is configured to use larger step sizes during a phase lock acquisition and smaller step sizes upon achieving phase lock, wherein during the phase lock acquisition, in response to detecting that the output signal (Up/Dn) indicates a first change in delay that is needed to reduce the phase difference, the step size controller is configured to provide one or more step size indications corresponding to a first step size to change the delay step size of the delay line to the first step size, and in response to detecting that the output signal (Up/Dn) indicates a second change in delay that is needed to reduce the phase difference, the step size controller is configured to provide one or more second step size indications corresponding to a second step size to change the delay step size of the delay line to the second step size, wherein the first step size is larger than the second step size.