An arithmetic processing apparatus coupled to a main storage apparatus, comprising: a plurality of arithmetic processors each coupled to the main storage apparatus through a bus (34, 35) and including: a plurality of arithmetic circuits configured to individually execute an arithmetic operation instruction for fixed point number data, the arithmetic processing apparatus further including a statistical information acquisition circuit configured to acquire at least one of first statistical information or second statistical information, with regard to a plurality of fixed point number data that are results of arithmetic operations executed by the plurality of arithmetic circuits, wherein the first statistical information is obtained by cumulative addition of bit patterns, each of the bit patterns is obtained by setting a flag bit to each of bit positions corresponding to a range from a least significant bit position of the fixed point number data to a highest-order bit position from among bit positions having a bit value different from a sign bit, for each digit corresponding to the bit positions, and wherein the second statistical information is obtained by cumulative addition of bit patterns, each of the bit pat terns is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order bit position from among bit positions having a bit value different from the sign bit, for each digit corresponding to the bit positions, wherein the statistical information acquisition circuit includes a holding circuit (AR0-AR39) configured to hold information accumulated at respective digits of the acquired at least one of first statistical information or second statistical information and a first selector configured to select information of a specific digit of the information held by the holding circuit (AR0-AR39) in accordance with a control signal that designates the specific digit, and to output the specific digit of the information held by the holding circuit (AR0-AR39) to the main storage apparatus through the bus (34, 35). a plurality of arithmetic circuits configured to individually execute an arithmetic operation instruction for fixed point number data, the arithmetic processing apparatus further including a statistical information acquisition circuit configured to acquire at least one of first statistical information or second statistical information, with regard to a plurality of fixed point number data that are results of arithmetic operations executed by the plurality of arithmetic circuits, wherein the first statistical information is obtained by cumulative addition of bit patterns, each of the bit patterns is obtained by setting a flag bit to each of bit positions corresponding to a range from a least significant bit position of the fixed point number data to a highest-order bit position from among bit positions having a bit value different from a sign bit, for each digit corresponding to the bit positions, and wherein the second statistical information is obtained by cumulative addition of bit patterns, each of the bit pat terns is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order bit position from among bit positions having a bit value different from the sign bit, for each digit corresponding to the bit positions, wherein the statistical information acquisition circuit includes a holding circuit (AR0-AR39) configured to hold information accumulated at respective digits of the acquired at least one of first statistical information or second statistical information and a first selector configured to select information of a specific digit of the information held by the holding circuit (AR0-AR39) in accordance with a control signal that designates the specific digit, and to output the specific digit of the information held by the holding circuit (AR0-AR39) to the main storage apparatus through the bus (34, 35).