A control system for a multi-level inverter with n levels, comprising: a processor; and a memory having stored thereon instructions, which, when executed by the processor, cause the processor to: sample a reference voltage vector (V*) and an angle (Θ e *); identify a sector (A;... F) among a plurality of sectors (A;... F) of the multi-level inverter and a region (1;... 16) among a plurality of regions (1;... 16) of the multi-level inverter based on the sampled reference voltage vector (V*) and the sampled angle (Θ e *); and select a switching sequence and a plurality of turn-on time values (T 1, T 2, T 3, T 4) from a look-up table stored in the memory based on the identified sector (A;... F) and region (1;... 16); and a circuit configured to generate pulse width modulation switching signals for the plurality of regions (1;... 16) of the multi-level inverter and the plurality of sectors (A;... F) of the multi-level inverter based on the turn on time values (T 1, T 2, T 3, T 4) and the selected switching sequence, characterized in that the circuit includes (n-1) comparators each having a first input and a second input, (n-1) inverters coupled to respective outputs of respective comparators, and (n-2) AND gates each having a first input and a second input, wherein the first input of the x th AND gate is coupled to the output of the x th inverter and the second input of the x th AND gate is coupled to the output of the (x+1) th comparator, where n and x are integers with 1≤x≤(n-2), wherein the circuit further includes a counter coupled to first inputs of the (n-1) comparators, and wherein the processor transmits turn-on time values to second inputs of the (n-1) comparators to generate switching signals, the switching signals corresponding to the output of the first comparator, the outputs of the (n-2) AND gates and the output of the (n-1) th inverter. a processor; and a memory having stored thereon instructions, which, when executed by the processor, cause the processor to: sample a reference voltage vector (V*) and an angle (Θ e *); identify a sector (A;... F) among a plurality of sectors (A;... F) of the multi-level inverter and a region (1;... 16) among a plurality of regions (1;... 16) of the multi-level inverter based on the sampled reference voltage vector (V*) and sample a reference voltage vector (V*) and an angle (Θ e *); identify a sector (A;... F) among a plurality of sectors (A;... F) of the multi-level inverter and a region (1;... 16) among a plurality of regions (1;... 16) of the multi-level inverter based on the sampled reference voltage vector (V*) and the sampled angle (Θ e *); and select a switching sequence and a plurality of turn-on time values (T 1, T 2, T 3, T 4) from a look-up table stored in the memory based on the identified sector (A;... F) and region (1;... 16); and a circuit configured to generate pulse width modulation switching signals for the plurality of regions (1;... 16) of the multi-level inverter and the plurality of sectors (A;... F) of the multi-level inverter based on the turn on time values (T 1, T 2, T 3, T 4) and the selected switching sequence, characterized in that the circuit includes (n-1) comparators each having a first input and a second input, (n-1) inverters coupled to respective outputs of respective comparators, and (n-2) AND gates each having a first input and a second input, wherein the first input of the x th AND gate is coupled to the output of the x th inverter and the second input of the x th AND gate is coupled to the output of the (x+1) th comparator, where n and x are integers with 1≤x≤(n-2), wherein the circuit further includes a counter coupled to first inputs of the (n-1) comparators, and wherein the processor transmits turn-on time values to second inputs of the (n-1) comparators to generate switching signals, the switching signals corresponding to the output of the first comparator, the outputs of the (n-2) AND gates and the output of the (n-1) th inverter.