A direct-transfer marching memory, wherein the direct-transfer marching memory includes an array of memory units (U k1, U k2, U k3,..., U k(n-1), U kn), each of the memory units (U k1, U k2, U k3,..., U k(n-1), U kn) comprising bit-level cells aligned along a column direction so as to store information of byte size or word size, each of the bit-level cells comprising an electron-storage region being configured to accumulate cell-electrons, wherein the memory units (U k1, U k2, U k3,..., U k(n-1), U kn) are arranged in rows extending in a row direction and columns extending in the column direction so as to form a matrix, the row direction being orthogonal to the column direction, wherein the direct-transfer marching memory comprises: - a substrate wherein each of the bit-level cell includes a corresponding stack comprising; - a corresponding substrate insulator (18 2j-2, 18 2j-1, 18 2j, 18 k(2j+1)) stacked on the substrate; - a corresponding floating-gate electrode (19 2j-2, 19 2j-1, 19 2j, 19 k(2j+1)) serving as the corresponding electron-storage region, being stacked on the corresponding substrate insulator; - a corresponding inter-electrode dielectric (20 2j-2, 20 2j-1, 20 2j, 20 k(2j+1)) stacked on the corresponding floating-gate electrode; and - a corresponding control-gate electrode (22 2j-2, 22 2j-1, 22 2j, 22 k(2j+1)) stacked on the corresponding inter-electrode dielectric; the direct transfer marching memory comprising further a plurality of insulators, each insulator disposed between corresponding two stacks adjacent along the row direction so as to serve as a corresponding inter-unit dielectric; wherein the direct-transfer marching memory comprises a circuit configured to provide a plurality of clock signals to the array of memory units, applying to each of the control gate electrodes a corresponding one of the clock signals; and wherein the circuit and the inter-unit dielectrics are such that in response to the clock signals the cell-electrons accumulated in one of the floating-gate electrode in a subject memory unit (U k1, U k2, U k3,..., U k(n-1), U kn) are directly transferred by quantum tunneling to an adjacent floating-gate electrode through the corresponding inter-unit dielectric, and the information of byte size or word size is transferred synchronously, step by step, along the row direction. wherein the memory units (U k1, U k2, U k3,..., U k(n-1), U kn) are arranged in rows extending in a row direction and columns extending in the column direction so as to form a matrix, the row direction being orthogonal to the column direction, wherein the direct-transfer marching memory comprises: - a substrate - a substrate wherein each of the bit-level cell includes a corresponding stack comprising; - a corresponding substrate insulator (18 2j-2, 18 2j-1, 18 2j, 18 k(2j+1)) stacked on the substrate; - a corresponding floating-gate electrode (19 2j-2, 19 2j-1, 19 2j, 19 k(2j+1)) serving as the corresponding electron-storage region, being stacked on the corresponding substrate insulator; - a corresponding inter-electrode dielectric (20 2j-2, 20 2j-1, 20 2j, 20 k(2j+1)) stacked on the corresponding floating-gate electrode; and - a corresponding control-gate electrode (22 2j-2, 22 2j-1, 22 2j, 22 k(2j+1)) stacked on the corresponding inter-electrode dielectric; - a corresponding substrate insulator (18 2j-2, 18 2j-1, 18 2j, 18 k(2j+1)) stacked on the substrate; - a corresponding floating-gate electrode (19 2j-2, 19 2j-1, 19 2j, 19 k(2j+1)) serving as the corresponding electron-storage region, being stacked on the corresponding substrate insulator; - a corresponding inter-electrode dielectric (20 2j-2, 20 2j-1, 20 2j, 20 k(2j+1)) stacked on the corresponding floating-gate electrode; and - a corresponding control-gate electrode (22 2j-2, 22 2j-1, 22 2j, 22 k(2j+1)) stacked on the corresponding inter-electrode dielectric; the direct transfer marching memory comprising further a plurality of insulators, each insulator disposed between corresponding two stacks adjacent along the row direction so as to serve as a corresponding inter-unit dielectric; wherein the direct-transfer marching memory comprises a circuit configured to provide a plurality of clock signals to the array of memory units, applying to each of the control gate electrodes a corresponding one of the clock signals; and wherein the circuit and the inter-unit dielectrics are such that in response to the clock signals the cell-electrons accumulated in one of the floating-gate electrode in a subject memory unit (U k1, U k2, U k3,..., U k(n-1), U kn) are directly transferred by quantum tunneling to an adjacent floating-gate electrode through the corresponding inter-unit dielectric, and the information of byte size or word size is transferred synchronously, step by step, along the row direction.