A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising: performing each erase-verify iteration (1201-1205, 1301-1308, 1401-1408) of a plurality of erase-verify iterations of the erase operation for a set of memory cells in at least one NAND string (NSO-NS8), the at least one NAND string comprises a drain-side end (DSEO-DSE7) in communication with a bit line (BLO, BL1), and a drain-side select gate transistor (SGDO-SGD7), the drain-side select gate transistor comprises a drain in communication with the drain-side end, and the drain-side select gate transistor comprises a control gate, characterised in that the performing each erase-verify iteration comprises applying an erase pulse comprising an intermediate voltage level and a peak voltage level to the bit line followed by performing a verify test for the set of memory cells, the applying the erase pulse in each erase-verify iteration comprising: raising a voltage of the bit line from a starting level (Vss) to the intermediate voltage level (Vgidl); raising the voltage of the bit line from the intermediate voltage level (Vgidl) to the peak voltage level (Verase); and when the voltage of the bit line is at the starting level and at the intermediate voltage level, controlling the control gate of the drain-side select gate transistor to provide a gate-to-drain voltage of the drain-side select gate transistor which is sufficiently high to generate gate-induced drain leakage (GIDL) current in the at least one NAND string; and stepping up the intermediate voltage level in at least one erase-verify iteration of the plurality of erase-verify iterations. performing each erase-verify iteration (1201-1205, 1301-1308, 1401-1408) of a plurality of erase-verify iterations of the erase operation for a set of memory cells in at least one NAND string (NSO-NS8), the at least one NAND string comprises a drain-side end (DSEO-DSE7) in communication with a bit line (BLO, BL1), and a drain-side select gate transistor (SGDO-SGD7), the drain-side select gate transistor comprises a drain in communication with the drain-side end, and the drain-side select gate transistor comprises a control gate, characterised in that the performing each erase-verify iteration comprises applying an erase pulse comprising an intermediate voltage level and a peak voltage level to the bit line followed by performing a verify test for the set of memory cells, the applying the erase pulse in each erase-verify iteration comprising: raising a voltage of the bit line from a starting level (Vss) to the intermediate voltage level (Vgidl); raising the voltage of the bit line from the intermediate voltage level (Vgidl) to the peak voltage level (Verase); and when the voltage of the bit line is at the starting level and at the intermediate voltage level, controlling the control gate of the drain-side select gate transistor to provide a gate-to-drain voltage of the drain-side select gate transistor which is sufficiently high to generate gate-induced drain leakage (GIDL) current in the at least one NAND string; and raising a voltage of the bit line from a starting level (Vss) to the intermediate voltage level (Vgidl); raising the voltage of the bit line from the intermediate voltage level (Vgidl) to the peak voltage level (Verase); and when the voltage of the bit line is at the starting level and at the intermediate voltage level, controlling the control gate of the drain-side select gate transistor to provide a gate-to-drain voltage of the drain-side select gate transistor which is sufficiently high to generate gate-induced drain leakage (GIDL) current in the at least one NAND string; and stepping up the intermediate voltage level in at least one erase-verify iteration of the plurality of erase-verify iterations.