A power conversion apparatus for power conversion between a DC circuit and an AC circuit, the power conversion apparatus comprising: ― m cell blocks (m is an integer of 2 or more) connected in cascade, the m cell blocks including a first cell block at a high-potential end to an mth cell block (CLBm) at a low-potential end; and ― m bypass circuits, the m bypass circuits including a first bypass circuit at a high-potential end to an mth bypass circuit (BCm) at a low-potential end, each of the m bypass circuits being electrically connected in parallel with a corresponding one of the m cell blocks, each of the cell blocks including: - a first connection node on a high-potential side and a second connection node on a low-potential side for connection to another cell block; and - a plurality of cell converters connected in cascade between the first connection node and the second connection node, each of the plurality of cell converters including an energy storage device, wherein when a DC current flows in a direction from the low-potential side to the high-potential side at a time of short-circuit fault at the DC circuit, a current path via the plurality of cell blocks is larger in impedance than a current path via the plurality of bypass circuits, the plurality of cell converters include 3 or more cell converters, an ith bypass circuit (i is any integer satisfying 1 ≤ i ≤ m) (BCi) is connected to the first connection node (TPi) and the second connection node (TNi) of a corresponding ith cell block (CLBi), and in the ith cell block (CLBi), a cell converter at a highest-potential end connected to the first connection node (TPi) and a cell converter (CLn) at a lowest-potential end connected to the second connection node (TNi) are arranged closer in distance to the corresponding ith bypass circuit (BCi) than remaining cell converters (CL2:CLn-1) are. ― m cell blocks (m is an integer of 2 or more) connected in cascade, the m cell blocks including a first cell block at a high-potential end to an mth cell block (CLBm) at a low-potential end; and ― m bypass circuits, the m bypass circuits including a first bypass circuit at a high-potential end to an mth bypass circuit (BCm) at a low-potential end, each of the m bypass circuits being electrically connected in parallel with a corresponding one of the m cell blocks, each of the cell blocks including: - a first connection node on a high-potential side and a second connection node on a low-potential side for connection to another cell block; and - a plurality of cell converters connected in cascade between the first connection node and the second connection node, each of the plurality of cell converters including an energy storage device, wherein when a DC current flows in a direction from the low-potential side to the high-potential side at a time of short-circuit fault at the DC circuit, a current path via the plurality of cell blocks is larger in impedance than a current path via the plurality of bypass circuits, the plurality of cell converters include 3 or more cell converters, an ith bypass circuit (i is any integer satisfying 1 ≤ i ≤ m) (BCi) is connected to the first connection node (TPi) and the second connection node (TNi) of a corresponding ith cell block (CLBi), and in the ith cell block (CLBi), a cell converter at a highest-potential end connected to the first connection node (TPi) and a cell converter (CLn) at a lowest-potential end connected to the second connection node (TNi) are arranged closer in distance to the corresponding ith bypass circuit (BCi) than remaining cell converters (CL2:CLn-1) are. - a first connection node on a high-potential side and a second connection node on a low-potential side for connection to another cell block; and - a plurality of cell converters connected in cascade between the first connection node and the second connection node, each of the plurality of cell converters including an energy storage device, wherein when a DC current flows in a direction from the low-potential side to the high-potential side at a time of short-circuit fault at the DC circuit, a current path via the plurality of cell blocks is larger in impedance than a current path via the plurality of bypass circuits, the plurality of cell converters include 3 or more cell converters, an ith bypass circuit (i is any integer satisfying 1 ≤ i ≤ m) (BCi) is connected to the first connection node (TPi) and the second connection node (TNi) of a corresponding ith cell block (CLBi), and in the ith cell block (CLBi), a cell converter at a highest-potential end connected to the first connection node (TPi) and a cell converter (CLn) at a lowest-potential end connected to the second connection node (TNi) are arranged closer in distance to the corresponding ith bypass circuit (BCi) than remaining cell converters (CL2:CLn-1) are.