A method for programming in a 3D stacked memory device, comprising: performing a programming operation for a set of memory cells (410a, 534a, 561a), the set of memory cells is connected to a selected word line layer among a plurality of word line layers (WLL0-WLL10) which are vertically spaced apart from one another by dielectric layers (DLL5-DLL14) in a stack, wherein each memory cell in the set of memory cells is in a respective NAND string and is associated with a respective bit line BL0-BL23) among a plurality of bit lines, the selected word line layer comprises a first edge (500, 501, 532, 533, 552, 553), characterised in that the set of memory cells comprises a first row (502, 505, 520, 523, 540, 545) of memory cells at a first distance (d1a, d2a, d3a, d4a, d5a, d6a) from the first edge, and a second row (503, 504, 521, 522, 542, 544) of memory cells at a second distance (d1b, d2b, d3b, d4b, d5b, d6b) from the first edge, wherein the second distance is greater than the first distance, and the performing the programming operation comprises: performing a plurality of program-verify iterations for the selected word line layer, each program-verify iteration of the plurality of program-verify iterations comprises a program portion followed by a verify portion, wherein at least one program-verify iteration of the plurality of program-verify iterations provides compensation for different programming speeds of the first row of memory cells and the second row of memory cells, wherein: the compensation is provided during the program portion by providing a bit line voltage (Vb1_slow) for the second row of memory cells which is higher than a bit line voltage of the first row of memory cells. performing a programming operation for a set of memory cells (410a, 534a, 561a), the set of memory cells is connected to a selected word line layer among a plurality of word line layers (WLL0-WLL10) which are vertically spaced apart from one another by dielectric layers (DLL5-DLL14) in a stack, wherein each memory cell in the set of memory cells is in a respective NAND string and is associated with a respective bit line BL0-BL23) among a plurality of bit lines, the selected word line layer comprises a first edge (500, 501, 532, 533, 552, 553), characterised in that the set of memory cells comprises a first row (502, 505, 520, 523, 540, 545) of memory cells at a first distance (d1a, d2a, d3a, d4a, d5a, d6a) from the first edge, and a second row (503, 504, 521, 522, 542, 544) of memory cells at a second distance (d1b, d2b, d3b, d4b, d5b, d6b) from the first edge, wherein the second distance is greater than the first distance, and the performing the programming operation comprises: performing a plurality of program-verify iterations for the selected word line layer, each program-verify iteration of the plurality of program-verify iterations comprises a program portion followed by a verify portion, wherein at least one program-verify iteration of the plurality of program-verify iterations provides compensation for different programming speeds of the first row of memory cells and the second row of memory cells, wherein: the compensation is provided during the program portion by providing a bit line voltage (Vb1_slow) for the second row of memory cells which is higher than a bit line voltage of the first row of memory cells.