A write operation circuit applied to a semiconductor memory comprising a Data Queue, DQ, port, a Data Bus Inversion, DBI, port, and a memory bank, the write operation circuit comprising a serial-to-parallel conversion circuit, a data buffer, a DBI decoder and a precharge module, wherein the serial-to-parallel conversion circuit is coupled to the DBI port and the DQ port, and the serial-to-parallel conversion circuit is configured to: perform serial-to-parallel conversion on a first DBI data of the DBI port to generate a second DBI data for transfer by a DBI signal line, and generate an input data of the data buffer based on the second DBI data and an input data of the DQ port, wherein when a number of low data bits in an external data is greater than a preset value, the first DBI data is set to high, and the input data of the DQ port is an flipped data of the external data, and when the number of low data bits in the external data is less than or equal to the pre-set value, the first DBI data is set to low, and the input data of the DQ port is the external data, and wherein the input data of the data buffer comprises flipped data of the input data of the DQ port; the data buffer comprises a plurality of Negative channel Metal Oxide Semiconductor, NMOS, transistors, each of the plurality of NMOS transistors comprising a gate coupled to the serial-to-parallel conversion circuit for receiving the input data of the data buffer, and a drain coupled to a respective global bus, wherein the data buffer is configured to determine whether to flip the global bus based on the input data of the data buffer; the DBI decoder is coupled to the memory bank and configured to receive a global bus data on the global bus and receive the second DBI data through the DBI signal line, and configured to decode the global bus data according to the second DBI data, and write the decoded global bus data into the memory bank, the decoding comprising determining whether to flip the global bus data; and the precharge module is coupled to a precharge signal line and configured to set an initial state of the global bus to high. the serial-to-parallel conversion circuit is coupled to the DBI port and the DQ port, and the serial-to-parallel conversion circuit is configured to: perform serial-to-parallel conversion on a first DBI data of the DBI port to generate a second DBI data for transfer by a DBI signal line, and generate an input data of the data buffer based on the second DBI data and an input data of the DQ port, wherein when a number of low data bits in an external data is greater than a preset value, the first DBI data is set to high, and the input data of the DQ port is an flipped data of the external data, and when the number of low data bits in the external data is less than or equal to the pre-set value, the first DBI data is set to low, and the input data of the DQ port is the external data, and wherein the input data of the data buffer comprises flipped data of the input data of the DQ port; the data buffer comprises a plurality of Negative channel Metal Oxide Semiconductor, NMOS, transistors, each of the plurality of NMOS transistors comprising a gate coupled to the serial-to-parallel conversion circuit for receiving the input data of the data buffer, and a drain coupled to a respective global bus, wherein the data buffer is configured to determine whether to flip the global bus based on the input data of the data buffer; the DBI decoder is coupled to the memory bank and configured to receive a global bus data on the global bus and receive the second DBI data through the DBI signal line, and configured to decode the global bus data according to the second DBI data, and write the decoded global bus data into the memory bank, the decoding comprising determining whether to flip the global bus data; and the precharge module is coupled to a precharge signal line and configured to set an initial state of the global bus to high.