A method for producing a semiconductor integrated circuit device comprising a memory circuit region and a peripheral circuit region, the memory circuit region including a memory cell in which a memory gate structure (4a, 4b) is disposed between a first select gate structure (5a, 5b) and a second select gate structure (6a, 6b) such that the first and second select gate structures (5a, 5b, 6a, 6b) are separated from the memory gate structure (4a, 4b) by a sidewall spacer, the first select gate structure (5a, 5b) including a first select gate electrode (G2a, G2b), the second select gate structure (6a, 6b) including a second select gate electrode (G3a, G3b), the peripheral circuit region including a logic gate structure (7a, 7b) of a peripheral circuit, the method comprising: a sidewall spacer formation step of forming the memory gate structure (4a, 4b) in the memory circuit region and then forming the sidewall spacer covering the memory gate structure (4a, 4b), the memory gate structure (4a, 4b) including a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode (G1a, G1b) stacked in this order; a conductive layer formation step of stacking a gate insulating film (25a,25b, 29a,29b) and a conductive layer in this order in the memory circuit region formed with the memory gate structure (4a, 4b) and in the peripheral circuit region; a logic gate structure formation step of patterning the conductive layer in the peripheral circuit region by using a first resist (Rr1a, Rr1b) patterned by using a photomask, so as to form a logic gate electrode (G5, G6) of the logic gate structure (7a, 7b) on the gate insulating film (29a, 29b), and removing at least a part of the conductive layer in a plurality of select gate electrode cutout planned regions (13a,14a,15a,16a) around the sidewall spacer in the memory circuit region by using the first resist (Rr1a, Rr1b), thereby forming a remaining conductive layer remaining in the plurality of select gate electrode cutout planned regions (13a,14a,15a,16a); and a conductive layer patterning step of etching back the conductive layer in the memory circuit region while covering the peripheral circuit region by using a second resist (Rm4a, Rm4b) patterned by using a photomask to remove the remaining conductive layer remaining in the plurality of select gate electrode cutout planned regions (13a,14a,15a,16a) while leaving the conductive layer intact along the sidewall spacer, so as to form the first select gate electrode (G2a, G2b) having sidewall-shape and the second select gate electrode (G3a, G3b) having sidewall-shape electrically separated from the first select gate electrode (G2a, G2b) at the plurality of select gate electrode cutout planned regions (13a,14a,15a,16a). a sidewall spacer formation step of forming the memory gate structure (4a, 4b) in the memory circuit region and then forming the sidewall spacer covering the memory gate structure (4a, 4b), the memory gate structure (4a, 4b) including a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode (G1a, G1b) stacked in this order; a conductive layer formation step of stacking a gate insulating film (25a,25b, 29a,29b) and a conductive layer in this order in the memory circuit region formed with the memory gate structure (4a, 4b) and in the peripheral circuit region; a logic gate structure formation step of patterning the conductive layer in the peripheral circuit region by using a first resist (Rr1a, Rr1b) patterned by using a photomask, so as to form a logic gate electrode (G5, G6) of the logic gate structure (7a, 7b) on the gate insulating film (29a, 29b), and removing at least a part of the conductive layer in a plurality of select gate electrode cutout planned regions (13a,14a,15a,16a) around the sidewall spacer in the memory circuit region by using the first resist (Rr1a, Rr1b), thereby forming a remaining conductive layer remaining in the plurality of select gate electrode cutout planned regions (13a,14a,15a,16a); and a conductive layer patterning step of etching back the conductive layer in the memory circuit region while covering the peripheral circuit region by using a second resist (Rm4a, Rm4b) patterned by using a photomask to remove the remaining conductive layer remaining in the plurality of select gate electrode cutout planned regions (13a,14a,15a,16a) while leaving the conductive layer intact along the sidewall spacer, so as to form the first select gate electrode (G2a, G2b) having sidewall-shape and the second select gate electrode (G3a, G3b) having sidewall-shape electrically separated from the first select gate electrode (G2a, G2b) at the plurality of select gate electrode cutout planned regions (13a,14a,15a,16a).