A shift register comprising an input module, an output module and an output control module, wherein the input module is configured to control a signal transmission between a start signal input terminal and a first node; the output module is configured to control a signal output at a signal output terminal (OUT-PUT), wherein the output module comprises a first output unit and a second output unit; the first output unit is connected to the first node, and the first node is configured to control the first output unit; the first output unit is configured to control a signal transmission between a second clock signal input terminal and the signal output terminal (OUT-PUT); the second output unit is connected to a second node, and the second node is configured to control the second output unit; the second output unit is configured to control a signal transmission between a first level signal input terminal (VGH;VGL) and the signal output terminal (OUT-PUT); and the output control module comprises a first control unit and a second control unit; the first control unit is configured to control a level at the first node, and the second control unit is configured to control a level at the second node; the input module comprises a first Thin Film Transistor TFT having a gate connected to a first clock signal input terminal, a first electrode connected to the start signal input terminal and a second electrode connected to the first node. the first output unit comprises a second TFT having a gate connected to the first node, a first electrode connected to the signal output terminal (OUT-PUT) and a second electrode connected to the second clock signal input terminal. the second output unit comprises a third TFT having a gate connected to the second node, a first electrode connected to the first level signal input terminal (VGH;VGL) and a second electrode connected to the signal output terminal (OUT-PUT). the second control unit comprises a ninth TFT, a tenth TFT and a third capacitor; a gate of the ninth TFT is connected to the first node, a first electrode of the ninth TFT is connected to the start signal input terminal, a second electrode of the ninth TFT is connected to the second node; a gate of the tenth TFT is connected to a third clock signal input terminal, a first electrode of the tenth TFT is connected to the second node, a second electrode of the tenth TFT is connected to a second level signal input terminal (VGL;VGH); and one terminal of the third capacitor is connected to the second node, and the other terminal of the third capacitor is connected to the first level signal input terminal (VGH;VGL) characterised in that: the first control unit comprises a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a first capacitor and a second capacitor; a gate of the fourth TFT is connected to the first node, a first electrode of the fourth TFT is connected to a third node, and a second electrode of the fourth TFT is connected to the first level signal input terminal (VGH;VGL); a gate of the fifth TFT is connected to the third clock signal input terminal, a first electrode of the fifth TFT is connected to the third node, and a second electrode of the fifth TFT is connected to the second level signal input terminal (VGL;VGH); a gate of the sixth TFT is connected to the third node, a first electrode of the sixth TFT is connected to a second electrode of the seventh TFT, and a second electrode of the sixth TFT is connected to the first level signal input terminal (VGH;VGL); a gate of the seventh TFT is connected to the second clock signal input terminal, a first electrode of the seventh TFT is connected to the first node, and the second electrode of the seventh TFT is connected to the first electrode of the sixth TFT; a gate of the eighth TFT is connected to the third clock signal input terminal, a first electrode of the eighth TFT is connected to the first level signal input terminal (VGH;VGL), and a second electrode of the eighth TFT is connected to the first node; one terminal of the first capacitor is connected to the signal output terminal (OUT-PUT), and the other terminal of the first capacitor is connected to the first node; and one terminal of the second capacitor is connected to the third node, and the other terminal of the second capacitor is connected to the first level signal input terminal (VGH;VGL).