A receiver apparatus comprising at least one antenna and at least one switch coupled to the antenna, said switch comprising: a first circuit portion corresponding to a first input port, a second circuit portion corresponding to a second input port, and an output port, wherein the first circuit portion includes an isolation channel including at least one first differential amplifier pair of two transistors (256, 250), said isolation channel providing isolation between the first input port and the output port, a transmit channel including at least one second differential amplifier pair of two transistors (245, 247), said transmit channel providing coupling between the first input port and the output port, and at least one third transistor (241', 240) for providing a control bias for selecting either the isolation channel or the transmit channel of the first circuit portion, wherein the isolation and transmit channels of the first circuit portion provide a constant return loss at the first input port irrespective of which channel of the first circuit portion is selected, wherein the second circuit portion includes an isolation channel including at least one first differential amplifier pair of two transistors (251, 257), said isolation channel providing isolation between the second input port and the output port, a transmit channel including at least one second differential amplifier pair of two transistors (248, 246), said transmit channel providing coupling between the second input port and the output port, and at least one third transistor (240', 241) for providing a control bias for selecting either the isolation channel or the transmit channel of the second circuit portion, wherein the isolation and transmit channels of the second circuit portion provide a constant return loss at the second input port irrespective of which channel of the second circuit portion is selected, wherein the at least one third transistor (240, 240', 241, 241') of each of the first and second circuit portions provides the control bias for selecting which of the first and second input ports (201, 202) are coupled to the output port. a first circuit portion corresponding to a first input port, a second circuit portion corresponding to a second input port, and an output port, wherein the first circuit portion includes an isolation channel including at least one first differential amplifier pair of two transistors (256, 250), said isolation channel providing isolation between the first input port and the output port, a transmit channel including at least one second differential amplifier pair of two transistors (245, 247), said transmit channel providing coupling between the first input port and the output port, and at least one third transistor (241', 240) for providing a control bias for selecting either the isolation channel or the transmit channel of the first circuit portion, wherein the isolation and transmit channels of the first circuit portion provide a constant return loss at the first input port irrespective of which channel of the first circuit portion is selected, wherein the second circuit portion includes an isolation channel including at least one first differential amplifier pair of two transistors (251, 257), said isolation channel providing isolation between the second input port and the output port, a transmit channel including at least one second differential amplifier pair of two transistors (248, 246), said transmit channel providing coupling between the second input port and the output port, and at least one third transistor (240', 241) for providing a control bias for selecting either the isolation channel or the transmit channel of the second circuit portion, wherein the isolation and transmit channels of the second circuit portion provide a constant return loss at the second input port irrespective of which channel of the second circuit portion is selected, wherein the at least one third transistor (240, 240', 241, 241') of each of the first and second circuit portions provides the control bias for selecting which of the first and second input ports (201, 202) are coupled to the output port.