Apparatus for processing data comprising: processing circuitry responsive to program instructions to perform data processing operations and configured to operate in a plurality of modes; and memory management circuitry coupled to said processing circuitry and to a memory and configured to control access permissions to data values stored within said memory in dependence upon page table data; wherein said memory has a memory address space divided in to a plurality of memory pages (34, 36, 38) and said page table data comprises a plurality of access control bits for each of said plurality of memory pages defining access permissions for a respective memory page, characterized in that: when said processing circuitry is in a first of said plurality of modes using a predetermined number of access control bits (40, 42) to encode access permissions, said memory management circuitry is responsive to at least one instance of a redundant encoding in which a plurality of different combinations of said access control bits provides a same set of access permissions; and when said processing circuitry is in a second of said plurality of modes using said predetermined number of access control bits to encode access permissions, said memory management unit is responsive said plurality of different combinations of access control bits to provide a plurality of different sets of access permissions in a non-redundant encoding. processing circuitry responsive to program instructions to perform data processing operations and configured to operate in a plurality of modes; and memory management circuitry coupled to said processing circuitry and to a memory and configured to control access permissions to data values stored within said memory in dependence upon page table data; wherein said memory has a memory address space divided in to a plurality of memory pages (34, 36, 38) and said page table data comprises a plurality of access control bits for each of said plurality of memory pages defining access permissions for a respective memory page, characterized in that: when said processing circuitry is in a first of said plurality of modes using a predetermined number of access control bits (40, 42) to encode access permissions, said memory management circuitry is responsive to at least one instance of a redundant encoding in which a plurality of different combinations of said access control bits provides a same set of access permissions; and when said processing circuitry is in a second of said plurality of modes using said predetermined number of access control bits to encode access permissions, said memory management unit is responsive said plurality of different combinations of access control bits to provide a plurality of different sets of access permissions in a non-redundant encoding. when said processing circuitry is in a first of said plurality of modes using a predetermined number of access control bits (40, 42) to encode access permissions, said memory management circuitry is responsive to at least one instance of a redundant encoding in which a plurality of different combinations of said access control bits provides a same set of access permissions; and when said processing circuitry is in a second of said plurality of modes using said predetermined number of access control bits to encode access permissions, said memory management unit is responsive said plurality of different combinations of access control bits to provide a plurality of different sets of access permissions in a non-redundant encoding.