A semiconductor device comprising: a plurality of processing circuits (B1 to Bn); an arbitration circuit that arbitrates a plurality of data transfer requests (RQ1 to RQn) issued by the plurality of processing circuits; a mask control circuit that loads the plurality of data transfer requests (RQ1 to RQn) arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period; and a memory controller that accesses a memory based on the plurality of data transfer requests (RQ1 to RQn) sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period characterised in that the mask control circuit comprises: a first monitor that monitors a total amount of data on data transfer requests (RQ1 to RQn) issued by the plurality of processing circuits (B1 to Bn) during a monitoring period; a second monitor that monitors a total amount of data that can be accepted by the memory; a mask signal generation unit that generates a mask signal, the mask signal being periodically switched between an active state and an inactive state and sets a length of an active period of the mask signal as the mask period, based on monitoring results of the first and second monitors; and a transfer request output unit that sequentially outputs the plurality of loaded data transfer requests (RQ1 to RQn) when the mask signal is in the inactive state. a plurality of processing circuits (B1 to Bn); an arbitration circuit that arbitrates a plurality of data transfer requests (RQ1 to RQn) issued by the plurality of processing circuits; a mask control circuit that loads the plurality of data transfer requests (RQ1 to RQn) arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period; and a memory controller that accesses a memory based on the plurality of data transfer requests (RQ1 to RQn) sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period characterised in that the mask control circuit comprises: a first monitor that monitors a total amount of data on data transfer requests (RQ1 to RQn) issued by the plurality of processing circuits (B1 to Bn) during a monitoring period; a second monitor that monitors a total amount of data that can be accepted by the memory; a mask signal generation unit that generates a mask signal, the mask signal being periodically switched between an active state and an inactive state and sets a length of an active period of the mask signal as the mask period, based on monitoring results of the first and second monitors; and a transfer request output unit that sequentially outputs the plurality of loaded data transfer requests (RQ1 to RQn) when the mask signal is in the inactive state. a first monitor that monitors a total amount of data on data transfer requests (RQ1 to RQn) issued by the plurality of processing circuits (B1 to Bn) during a monitoring period; a second monitor that monitors a total amount of data that can be accepted by the memory; a mask signal generation unit that generates a mask signal, the mask signal being periodically switched between an active state and an inactive state and sets a length of an active period of the mask signal as the mask period, based on monitoring results of the first and second monitors; and a transfer request output unit that sequentially outputs the plurality of loaded data transfer requests (RQ1 to RQn) when the mask signal is in the inactive state.