A microprocessor configured to perform out of order execution wherein the microprocessor comprises a load queue comprising multiple entries each corresponding to a load instruction, wherein each entry includes a corresponding load address and age information; a store queue comprising multiple entries each corresponding to a store instruction, wherein each entry includes a corresponding store address and age information; a comparison circuit comprising: a first comparison unit configured to compare a first subset of bits of a load address with a corresponding first subset of bits of a store address to produce a first comparison result indicating whether the first subset of bits of the load address is equal to the first subset of bits of the store address; and; an age comparison circuit, wherein the microprocessor is characterized in that the age comparison circuit is configured to compare age information corresponding to the load address to age information corresponding to the store address, wherein when age information corresponding to the load address is greater than age information corresponding to the store address, the age comparison circuit produces a disable signal, and when age information corresponding to the load address is less than age information corresponding to the store address, the age comparison circuit produces an enable signal; and in that a second comparison unit is coupled to the first comparison unit for receiving the first comparison result, wherein the second comparison unit is configured to be one of enabled and disabled based on the enable or disable signal produced by the age comparison unit and based on the first comparison result, wherein, when the second comparison unit is enabled, the second comparison unit is configured to compare a second subset of bits of the load address with a corresponding second subset of bits of the store address to produce a second comparison result indicating whether the second subset of bits of the load address is equal to the second subset of bits of the store address; wherein the second comparison result is combined with the first comparison result to produce a final result for searching the load queue for mis-speculative load instructions. a first comparison unit configured to compare a first subset of bits of a load address with a corresponding first subset of bits of a store address to produce a first comparison result indicating whether the first subset of bits of the load address is equal to the first subset of bits of the store address; and; an age comparison circuit, wherein the microprocessor is characterized in that the age comparison circuit is configured to compare age information corresponding to the load address to age information corresponding to the store address, wherein when age information corresponding to the load address is greater than age information corresponding to the store address, the age comparison circuit produces a disable signal, and when age information corresponding to the load address is less than age information corresponding to the store address, the age comparison circuit produces an enable signal; and in that a second comparison unit is coupled to the first comparison unit for receiving the first comparison result, wherein the second comparison unit is configured to be one of enabled and disabled based on the enable or disable signal produced by the age comparison unit and based on the first comparison result, wherein, when the second comparison unit is enabled, the second comparison unit is configured to compare a second subset of bits of the load address with a corresponding second subset of bits of the store address to produce a second comparison result indicating whether the second subset of bits of the load address is equal to the second subset of bits of the store address; wherein the second comparison result is combined with the first comparison result to produce a final result for searching the load queue for mis-speculative load instructions.