An analog to digital converter comprising at least one sampling capacitor connectable to an input node, and a pre-charge circuit, the analog to digital converter having a sample and convert cycle, the sample and convert cycle having a pre-charge phase (T5, T6), an acquire mode (T7, T9) and a conversion phase (T9, EOC), the pre-charge phase temporally preceding and ending prior to the start of the acquire mode, the acquire mode temporally preceding and ending prior to the start of the conversion phase, wherein the pre-charge circuit comprises a pre-charge buffer amplifier, the pre-charge buffer amplifier being arranged, in the pre-charge phase, to cause a voltage across the at least one sampling capacitor to substantially match an input voltage of the input node prior to the analog to digital converter entering the acquire mode, wherein during the acquire mode, the at least one sampling capacitor is connected to the input node by a first sample switch, and in the conversion phase, the analog to digital converter is arranged to convert the voltage across the at least one sampling capacitor, wherein an input of the pre-charge buffer amplifier is configured to be connected by capacitor level shifting (172, 174) to the input node (17,100) and an output of the pre-charge buffer amplifier is configured to be connected to a voltage translation circuit (160, 305, 400), wherein the voltage translation circuit (160, 305, 400) is operable to level-shift an output voltage of the pre-charge buffer amplifier, whereby the pre-charge buffer amplifier operates from a reduced voltage power supply when compared to an input voltage range of the analog to digital converter, as a result of capacitor level shifting (172, 174) and the voltage translation circuit (160, 305, 400), wherein the output of the pre-charge buffer amplifier is further configured to be connected to the at least one sampling capacitor via a pre-charge output switch and wherein during the pre-charge phase the pre-charge output switch is configured to be placed in a low impedance state and the first sample switch is configured to be placed in a high impedance state, and during the acquire mode the pre-charge output switch is configured to be placed in a high impedance state and the first sample switch is configured to be placed in a low impedance state so as to store charge on the at least one sampling capacitor. wherein the pre-charge circuit comprises a pre-charge buffer amplifier, the pre-charge buffer amplifier being arranged, in the pre-charge phase, to cause a voltage across the at least one sampling capacitor to substantially match an input voltage of the input node prior to the analog to digital converter entering the acquire mode, wherein during the acquire mode, the at least one sampling capacitor is connected to the input node by a first sample switch, and in the conversion phase, the analog to digital converter is arranged to convert the voltage across the at least one sampling capacitor, wherein an input of the pre-charge buffer amplifier is configured to be connected by capacitor level shifting (172, 174) to the input node (17,100) and an output of the pre-charge buffer amplifier is configured to be connected to a voltage translation circuit (160, 305, 400), wherein the voltage translation circuit (160, 305, 400) is operable to level-shift an output voltage of the pre-charge buffer amplifier, whereby the pre-charge buffer amplifier operates from a reduced voltage power supply when compared to an input voltage range of the analog to digital converter, as a result of capacitor level shifting (172, 174) and the voltage translation circuit (160, 305, 400), wherein the output of the pre-charge buffer amplifier is further configured to be connected to the at least one sampling capacitor via a pre-charge output switch and wherein during the pre-charge phase the pre-charge output switch is configured to be placed in a low impedance state and the first sample switch is configured to be placed in a high impedance state, and during the acquire mode the pre-charge output switch is configured to be placed in a high impedance state and the first sample switch is configured to be placed in a low impedance state so as to store charge on the at least one sampling capacitor.