A pixel circuit comprising: a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node; a light emitting element including an anode electrode connected to the fourth node and a cathode electrode connected to a fourth power line for receiving a low-potential power supply voltage, the light emitting element being driven according to a current from the driving element; a first switch element including a first electrode connected to the first node, a second electrode connected to the second node and a gate electrode connected to a second gate line for receiving a second scan pulse; a second switch element including a first electrode connected to the third node, a second electrode connected to the fourth node and a gate electrode connected to a fifth gate line for receiving a second EM pulse; a third switch element including a first electrode connected to a second power line for receiving an initialization voltage (Vinit), a second electrode connected to a fifth node, and a gate electrode connected to the second gate line; a fourth switch element including a first electrode connected to a data line for receiving a data voltage (Vdata), a second electrode connected to the fifth node, and a gate electrode connected to a first gate line for receiving a first scan pulse; a fifth switch element including a first electrode connected to a first power line (VDDL) for receiving a pixel driving voltage, a second electrode connected to the first node, and a gate electrode connected to a fourth gate line for receiving a first EM pulse; a sixth switch element including a first electrode connected to a third power line (REFL) for receiving a reference voltage (Vref), a second electrode connected to the third node, and a gate electrode connected to a third gate line for receiving a third scan pulse; and a seventh switch element including a first electrode connected to the second power line, a second electrode connected to the fourth node, and a gate electrode connected to the third gate line; a first capacitor including a first electrode connected to the fifth node, and a second electrode connected to the second node; and a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node. a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node; a light emitting element including an anode electrode connected to the fourth node and a cathode electrode connected to a fourth power line for receiving a low-potential power supply voltage, the light emitting element being driven according to a current from the driving element; a first switch element including a first electrode connected to the first node, a second electrode connected to the second node and a gate electrode connected to a second gate line for receiving a second scan pulse; a second switch element including a first electrode connected to the third node, a second electrode connected to the fourth node and a gate electrode connected to a fifth gate line for receiving a second EM pulse; a third switch element including a first electrode connected to a second power line for receiving an initialization voltage (Vinit), a second electrode connected to a fifth node, and a gate electrode connected to the second gate line; a fourth switch element including a first electrode connected to a data line for receiving a data voltage (Vdata), a second electrode connected to the fifth node, and a gate electrode connected to a first gate line for receiving a first scan pulse; a fifth switch element including a first electrode connected to a first power line (VDDL) for receiving a pixel driving voltage, a second electrode connected to the first node, and a gate electrode connected to a fourth gate line for receiving a first EM pulse; a sixth switch element including a first electrode connected to a third power line (REFL) for receiving a reference voltage (Vref), a second electrode connected to the third node, and a gate electrode connected to a third gate line for receiving a third scan pulse; and a seventh switch element including a first electrode connected to the second power line, a second electrode connected to the fourth node, and a gate electrode connected to the third gate line; a first capacitor including a first electrode connected to the fifth node, and a second electrode connected to the second node; and a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node.