A memory device comprising: a memory cell array including a plurality of cell strings (NS11-NS33), each of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor arranged vertically, the string selection transistor being connected to a string selection line, the plurality of memory cells being respectively connected to a plurality of word lines (WL1 - WL8), and the ground selection transistor being connected to a ground selection line (GSL1, GSL2); and a voltage generating circuit configured to generate a plurality of word line voltages provided to the plurality of word lines (WL1 - WL8), wherein the plurality of word lines (WL1 - WL8) are classified into a plurality of groups on the basis of how close a corresponding word line (WL1 - WL8) is to the string selection line or the ground selection line, wherein the voltage generating circuit is configured to provide word line voltages (WL1 - WL8) having slopes having different values with respect to the plurality of groups, in a first period of a read operation of the memory device, wherein the plurality of groups comprise a first edge group including one or more word lines (WL1-WL8) of the plurality of word lines, the first edge group adjacent to the string selection line, a second edge group including one or more word lines of the plurality of word lines, the second edge group adjacent to the ground selection line, and a center group including one or more word lines of the plurality of word lines between the first edge group and the second edge group, wherein: the first period corresponds to a prepulse period in the read operation, and the voltage generating circuit is configured to, during the prepulse period, provide a first word line voltage having a first slope to the one or more word lines (WL1 - WL8) of the first edge group, and provide a second word line voltage having a second slope, which is less than the first slope, to the one or more word lines of the center group. a memory cell array including a plurality of cell strings (NS11-NS33), each of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor arranged vertically, the string selection transistor being connected to a string selection line, the plurality of memory cells being respectively connected to a plurality of word lines (WL1 - WL8), and the ground selection transistor being connected to a ground selection line (GSL1, GSL2); and a voltage generating circuit configured to generate a plurality of word line voltages provided to the plurality of word lines (WL1 - WL8), wherein the plurality of word lines (WL1 - WL8) are classified into a plurality of groups on the basis of how close a corresponding word line (WL1 - WL8) is to the string selection line or the ground selection line, wherein the voltage generating circuit is configured to provide word line voltages (WL1 - WL8) having slopes having different values with respect to the plurality of groups, in a first period of a read operation of the memory device, wherein the plurality of groups comprise a first edge group including one or more word lines (WL1-WL8) of the plurality of word lines, the first edge group adjacent to the string selection line, a second edge group including one or more word lines of the plurality of word lines, the second edge group adjacent to the ground selection line, and a center group including one or more word lines of the plurality of word lines between the first edge group and the second edge group, wherein: the first period corresponds to a prepulse period in the read operation, and the voltage generating circuit is configured to, during the prepulse period, provide a first word line voltage having a first slope to the one or more word lines (WL1 - WL8) of the first edge group, and provide a second word line voltage having a second slope, which is less than the first slope, to the one or more word lines of the center group. the first period corresponds to a prepulse period in the read operation, and the voltage generating circuit is configured to, during the prepulse period, provide a first word line voltage having a first slope to the one or more word lines (WL1 - WL8) of the first edge group, and provide a second word line voltage having a second slope, which is less than the first slope, to the one or more word lines of the center group.