A solid-state imaging device comprising: a pixel unit in which plural pixels each having a photoelectric conversion element which converts light signals into electric signals and accumulates the electric signals according to exposure time are arranged in a matrix state; plural control lines (SEL, RST, TRG) for controlling the pixels; and a pixel drive unit (120, 130, 140, 150) controlling operation of the pixels to perform electronic shutter operation and reading of the pixel unit through the control lines, wherein the pixel drive unit includes a row selection circuit for outputting read row selection signals (RLSEL) and shutter row selection signals (SLSEL) of row addresses of read rows from which signals are read and shutter rows from which charges accumulated in the photoelectric conversion elements are swept out and reset in accordance with address signals, selecting means for selecting plural successive rows by designating only the lowest address signal (R_ADDR_L, S_ADDR1_L, S_ADDR2_L) and the highest address signal (R_ADDR_H, S_ADDR1_1, SADDR2_H) of the plural successive rows, and an address decoder for decoding only the lowest address signal and the highest address signal to output a lowest address decoded signal (R_ADDR_L_DEC, S_ADDR1_L_DEC, S_ADDR2_L_DEC) and a highest address decoded signal (R_ADDR_H_DEC, S_ADDR1_H_DEC, S_ADDR2_H_DEC); wherein the row selection circuit outputs, in response to the lowest address decoded signal and the highest address decoded signal, the read row selection signals or the shutter row selection signals for each of the selected plural successive rows at the same time. a pixel unit in which plural pixels each having a photoelectric conversion element which converts light signals into electric signals and accumulates the electric signals according to exposure time are arranged in a matrix state; plural control lines (SEL, RST, TRG) for controlling the pixels; and a pixel drive unit (120, 130, 140, 150) controlling operation of the pixels to perform electronic shutter operation and reading of the pixel unit through the control lines, wherein the pixel drive unit includes a row selection circuit for outputting read row selection signals (RLSEL) and shutter row selection signals (SLSEL) of row addresses of read rows from which signals are read and shutter rows from which charges accumulated in the photoelectric conversion elements are swept out and reset in accordance with address signals, selecting means for selecting plural successive rows by designating only the lowest address signal (R_ADDR_L, S_ADDR1_L, S_ADDR2_L) and the highest address signal (R_ADDR_H, S_ADDR1_1, SADDR2_H) of the plural successive rows, and an address decoder for decoding only the lowest address signal and the highest address signal to output a lowest address decoded signal (R_ADDR_L_DEC, S_ADDR1_L_DEC, S_ADDR2_L_DEC) and a highest address decoded signal (R_ADDR_H_DEC, S_ADDR1_H_DEC, S_ADDR2_H_DEC); wherein the row selection circuit outputs, in response to the lowest address decoded signal and the highest address decoded signal, the read row selection signals or the shutter row selection signals for each of the selected plural successive rows at the same time.