A computer-implemented neural network tiling method, the method comprising the steps of: • obtaining (step 501) a neural network graph, wherein the neural network graph is used to represent a neural network, the neural network graph comprises a plurality of vertices, and each vertex represents a calculation unit in the neural network; and • tiling (steps 502 - 508) the neural network graph to obtain a depth subgraph, wherein the depth subgraph is used to represent a depth subnetwork, a plurality of vertices comprised in the depth subnetwork exchange data with each other by reading and writing an on-chip buffer, the depth subnetwork is configured to successively process at least two groups of data obtained by tiling first input data, to obtain first output data, the first input data is input data of the depth subnetwork, and the first input data comprises one or more signals that can be processed by a computer, wherein the depth subnetwork is a subnetwork obtained by tiling the neural network, wherein the depth subnetwork includes a part of the plurality of vertices of the neural network, wherein after the tiling the neural network graph to obtain the depth subgraph, the method further comprises: • when a quantity of vertices comprised in the depth subgraph is not less than a first threshold, tiling the depth subgraph to obtain a first second-order subgraph and a second second-order subgraph, wherein the first second-order subgraph is used to represent a first second-order subnetwork, the second second-order subgraph is used to represent a second second-order subnetwork, both the first second-order subnetwork and the second second-order subnetwork are comprised in the depth subnetwork, and vertices comprised in the first second-order subnetwork are all different from vertices comprised in the second second-order subnetwork, wherein output data of the first second-order subnetwork is stored into a middle buffer, and the second second-order subnetwork reads the data from the middle buffer, wherein the middle buffer is an off-chip buffer whose reading and writing speed is lower than that of the on-chip buffer, and the reading and writing speed of the middle buffer is faster than that of an external memory. • obtaining (step 501) a neural network graph, wherein the neural network graph is used to represent a neural network, the neural network graph comprises a plurality of vertices, and each vertex represents a calculation unit in the neural network; and • tiling (steps 502 - 508) the neural network graph to obtain a depth subgraph, wherein the depth subgraph is used to represent a depth subnetwork, a plurality of vertices comprised in the depth subnetwork exchange data with each other by reading and writing an on-chip buffer, the depth subnetwork is configured to successively process at least two groups of data obtained by tiling first input data, to obtain first output data, the first input data is input data of the depth subnetwork, and the first input data comprises one or more signals that can be processed by a computer, wherein the depth subnetwork is a subnetwork obtained by tiling the neural network, wherein the depth subnetwork includes a part of the plurality of vertices of the neural network, • when a quantity of vertices comprised in the depth subgraph is not less than a first threshold, tiling the depth subgraph to obtain a first second-order subgraph and a second second-order subgraph, wherein the first second-order subgraph is used to represent a first second-order subnetwork, the second second-order subgraph is used to represent a second second-order subnetwork, both the first second-order subnetwork and the second second-order subnetwork are comprised in the depth subnetwork, and vertices comprised in the first second-order subnetwork are all different from vertices comprised in the second second-order subnetwork, wherein output data of the first second-order subnetwork is stored into a middle buffer, and the second second-order subnetwork reads the data from the middle buffer, wherein the middle buffer is an off-chip buffer whose reading and writing speed is lower than that of the on-chip buffer, and the reading and writing speed of the middle buffer is faster than that of an external memory.