A circuit (36,80), comprising: a clock input for at least one clock signal; only one clock buffer connected to the clock input configured to generate, based on the at least one clock signal at least a first modified clock signal and a second modified clock signal; a plurality of flip-flops (38,40,82) connected to the only one clock buffer, each of which are configured to receive the first modified clock signal and the second modified clock signal; a plurality of data inputs (D4,D8,D12), each being connected to at least one of the plurality of flip-flops, and configured to provide input data to the plurality of flip-flops; and a plurality of data outputs (Q1,Q2,Q3), each being connected to at least one of the plurality of flip-flops, and configured to provide output data from the plurality of flip-flops; wherein each of the plurality of flip-flops is configured to transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal; wherein each of the flip-flops comprises: a first switch (48,56,84), connected to at least one of the plurality of data inputs, configured to receive the input data and the first modified clock signal, wherein the first switch operates based on the first modified clock signal; a second switch (50,58,86) configured to receive the second modified clock signal, wherein the second switch operates based on the second modified clock signal to provide output data (D6,D10,D14); a third switch (52,60,88) configured to receive the second modified clock signal, wherein the third switch operates based on the second modified clock signal; and a fourth switch (54,62,90) configured to receive the first modified clock signal, wherein the fourth switch operates based on the first modified clock signal to provide output data. a clock input for at least one clock signal; only one clock buffer connected to the clock input configured to generate, based on the at least one clock signal at least a first modified clock signal and a second modified clock signal; a plurality of flip-flops (38,40,82) connected to the only one clock buffer, each of which are configured to receive the first modified clock signal and the second modified clock signal; a plurality of data inputs (D4,D8,D12), each being connected to at least one of the plurality of flip-flops, and configured to provide input data to the plurality of flip-flops; and a plurality of data outputs (Q1,Q2,Q3), each being connected to at least one of the plurality of flip-flops, and configured to provide output data from the plurality of flip-flops; wherein each of the plurality of flip-flops is configured to transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal; wherein each of the flip-flops comprises: a first switch (48,56,84), connected to at least one of the plurality of data inputs, configured to receive the input data and the first modified clock signal, wherein the first switch operates based on the first modified clock signal; a second switch (50,58,86) configured to receive the second modified clock signal, wherein the second switch operates based on the second modified clock signal to provide output data (D6,D10,D14); a third switch (52,60,88) configured to receive the second modified clock signal, wherein the third switch operates based on the second modified clock signal; and a fourth switch (54,62,90) configured to receive the first modified clock signal, wherein the fourth switch operates based on the first modified clock signal to provide output data. a first switch (48,56,84), connected to at least one of the plurality of data inputs, configured to receive the input data and the first modified clock signal, wherein the first switch operates based on the first modified clock signal; a second switch (50,58,86) configured to receive the second modified clock signal, wherein the second switch operates based on the second modified clock signal to provide output data (D6,D10,D14); a third switch (52,60,88) configured to receive the second modified clock signal, wherein the third switch operates based on the second modified clock signal; and a fourth switch (54,62,90) configured to receive the first modified clock signal, wherein the fourth switch operates based on the first modified clock signal to provide output data.