A scan driving circuit, comprising: a first scan driver including a plurality of first units (SCU1, SCU2, SCU3, SCU4), the first units (SCU1, SCU2, SCU3, SCU4) being adapted to receive an input signal (INPUT) or an output voltage (SOUT1, SOUT2, SOUT3, SOUT4) of its previous first unit (SCU1, SCU2, SCU3) and first and second clock signals (CLKa, CLKb) and to output a scan signal; and a emission control driver having a plurality of second units (CCU1, CCU2, CCU3), the second units (CCU1, CCU2, CCU3) being adapted to receive a plurality of scan signals (S1, S2, S3) output from respective ones of the first units (SCU1, SCU2, SCU3) and of the previous first unit (SCU1, SCU2, SCU3) of the respective first unit (SCU1, SCU2, SCU3), to receive the first and second clock signals (CLKa, CLKb), and to output an emission control signal (E1, E2, E3), characterised in that each of the first units comprises: a first transistor including a first terminal connected to an input terminal, a gate terminal connected to a first clock terminal, and a second terminal; a second transistor including a gate terminal connected to the second terminal of the first transistor, a first terminal connected to a second clock terminal, and a second terminal connected to an output terminal (SOUT); a third transistor including a gate terminal connected to the first clock terminal, a first terminal connected to a first node, and a second terminal connected to a first power supply; a fourth transistor including a gate terminal connected to the second terminal of the first transistor, a first terminal connected to the first clock terminal, and a second terminal connected to the first node; and a fifth transistor including a gate terminal connected to the first node, a first terminal connected to a second power supply, and a second terminal connected to the output terminal (SOUT). a first scan driver including a plurality of first units (SCU1, SCU2, SCU3, SCU4), the first units (SCU1, SCU2, SCU3, SCU4) being adapted to receive an input signal (INPUT) or an output voltage (SOUT1, SOUT2, SOUT3, SOUT4) of its previous first unit (SCU1, SCU2, SCU3) and first and second clock signals (CLKa, CLKb) and to output a scan signal; and a emission control driver having a plurality of second units (CCU1, CCU2, CCU3), the second units (CCU1, CCU2, CCU3) being adapted to receive a plurality of scan signals (S1, S2, S3) output from respective ones of the first units (SCU1, SCU2, SCU3) and of the previous first unit (SCU1, SCU2, SCU3) of the respective first unit (SCU1, SCU2, SCU3), to receive the first and second clock signals (CLKa, CLKb), and to output an emission control signal (E1, E2, E3), characterised in that each of the first units comprises: a first transistor including a first terminal connected to an input terminal, a gate terminal connected to a first clock terminal, and a second terminal; a second transistor including a gate terminal connected to the second terminal of the first transistor, a first terminal connected to a second clock terminal, and a second terminal connected to an output terminal (SOUT); a third transistor including a gate terminal connected to the first clock terminal, a first terminal connected to a first node, and a second terminal connected to a first power supply; a fourth transistor including a gate terminal connected to the second terminal of the first transistor, a first terminal connected to the first clock terminal, and a second terminal connected to the first node; and a fifth transistor including a gate terminal connected to the first node, a first terminal connected to a second power supply, and a second terminal connected to the output terminal (SOUT). a first transistor including a first terminal connected to an input terminal, a gate terminal connected to a first clock terminal, and a second terminal; a second transistor including a gate terminal connected to the second terminal of the first transistor, a first terminal connected to a second clock terminal, and a second terminal connected to an output terminal (SOUT); a third transistor including a gate terminal connected to the first clock terminal, a first terminal connected to a first node, and a second terminal connected to a first power supply; a fourth transistor including a gate terminal connected to the second terminal of the first transistor, a first terminal connected to the first clock terminal, and a second terminal connected to the first node; and a fifth transistor including a gate terminal connected to the first node, a first terminal connected to a second power supply, and a second terminal connected to the output terminal (SOUT).