An integrated circuit for protecting against transient electrical stress events, comprising: a trigger circuit including: a first detection circuit coupled to a first supply voltage; a second detection circuit coupled to a second supply voltage; a rail clamp device, wherein during a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit, and during a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit, wherein the first detection circuit includes a first capacitive element (42, 70) coupled in series with a first resistive element (44, 72) between the first supply voltage and a third supply voltage, and an output terminal (41, 71) between the first capacitive element and the first resistive element provides the first output signal, wherein the second detection circuit includes a second capacitive element (46, 74) coupled in series with a second resistive element (48, 76) between the second supply voltage and the third supply voltage, and an output terminal (47, 75) between the second capacitive element and the second resistive element provides the second output signal, the integrated circuit further comprising a combinatorial logic circuit including: a first inverter including an input coupled to the first output signal of the first detection circuit; a second inverter including an input coupled to the second output signal of the second detection circuit; and a NAND gate that generates a third output signal, wherein the NAND gate includes a first input configured to receive an output signal from the first inverter, and a second input configured to receive an output signal from the second inverter, wherein the first inverter includes a third ballast element coupled in series with a first MOS transistor between the first supply voltage and the third supply voltage, wherein a gate electrode of the first MOS transistor is coupled to the first output signal, and wherein the second inverter includes a fourth ballast element coupled in series with a second MOS transistor between the second supply voltage and the third supply voltage, wherein a gate electrode of the second MOS transistor is coupled to the second output signal. a trigger circuit including: a first detection circuit coupled to a first supply voltage; a second detection circuit coupled to a second supply voltage; a first detection circuit coupled to a first supply voltage; a second detection circuit coupled to a second supply voltage; a rail clamp device, wherein during a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit, and during a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit, wherein the first detection circuit includes a first capacitive element (42, 70) coupled in series with a first resistive element (44, 72) between the first supply voltage and a third supply voltage, and an output terminal (41, 71) between the first capacitive element and the first resistive element provides the first output signal, wherein the second detection circuit includes a second capacitive element (46, 74) coupled in series with a second resistive element (48, 76) between the second supply voltage and the third supply voltage, and an output terminal (47, 75) between the second capacitive element and the second resistive element provides the second output signal, a first inverter including an input coupled to the first output signal of the first detection circuit; a second inverter including an input coupled to the second output signal of the second detection circuit; and a NAND gate that generates a third output signal, wherein the NAND gate includes a first input configured to receive an output signal from the first inverter, and a second input configured to receive an output signal from the second inverter, wherein the first inverter includes a third ballast element coupled in series with a first MOS transistor between the first supply voltage and the third supply voltage, wherein a gate electrode of the first MOS transistor is coupled to the first output signal, and wherein the second inverter includes a fourth ballast element coupled in series with a second MOS transistor between the second supply voltage and the third supply voltage, wherein a gate electrode of the second MOS transistor is coupled to the second output signal.