An image sensor comprising a first layer (1, 12) and second layer (2, 18) arranged vertically with respect to each other, wherein: the first layer is a PMOS photodetection circuit layer comprising: an array of pixel elements, each pixel element comprising: a pinned photodiode; and an amplifier, the amplifier comprising P-FET transistors; Analog to Digital Converter circuit portions (123, 124) comprising P-FETs; and Column Buffer circuit portions (123, 124) comprising P-FETs; wherein the ADC and Column Buffer circuit portions are formed around the periphery of, or in a ring around, the array of pixel elements; and the second layer is a CMOS circuit layer comprising supporting pixel circuitry, the supporting pixel circuitry comprising: pixel circuitry comprising N-FETs connected to corresponding pixel circuitry in the PMOS circuit layer; Analog to Digital Converter circuit portions (183, 184) comprising N-FETs connected to corresponding ADC circuit portions in the PMOS circuit layer; and Column Buffer circuit portions (183, 184) comprising N-FETs connected to corresponding Column Buffer circuit portions in the PMOS circuit layer; wherein the array of pixel elements is triggered using an electronic global shutter, without requiring a mechanical shutter. the first layer is a PMOS photodetection circuit layer comprising: an array of pixel elements, each pixel element comprising: a pinned photodiode; and an amplifier, the amplifier comprising P-FET transistors; Analog to Digital Converter circuit portions (123, 124) comprising P-FETs; and Column Buffer circuit portions (123, 124) comprising P-FETs; wherein the ADC and Column Buffer circuit portions are formed around the periphery of, or in a ring around, the array of pixel elements; and an array of pixel elements, each pixel element comprising: a pinned photodiode; and an amplifier, the amplifier comprising P-FET transistors; a pinned photodiode; and an amplifier, the amplifier comprising P-FET transistors; Analog to Digital Converter circuit portions (123, 124) comprising P-FETs; and Column Buffer circuit portions (123, 124) comprising P-FETs; wherein the ADC and Column Buffer circuit portions are formed around the periphery of, or in a ring around, the array of pixel elements; and the second layer is a CMOS circuit layer comprising supporting pixel circuitry, the supporting pixel circuitry comprising: pixel circuitry comprising N-FETs connected to corresponding pixel circuitry in the PMOS circuit layer; Analog to Digital Converter circuit portions (183, 184) comprising N-FETs connected to corresponding ADC circuit portions in the PMOS circuit layer; and Column Buffer circuit portions (183, 184) comprising N-FETs connected to corresponding Column Buffer circuit portions in the PMOS circuit layer; wherein the array of pixel elements is triggered using an electronic global shutter, without requiring a mechanical shutter. pixel circuitry comprising N-FETs connected to corresponding pixel circuitry in the PMOS circuit layer; Analog to Digital Converter circuit portions (183, 184) comprising N-FETs connected to corresponding ADC circuit portions in the PMOS circuit layer; and Column Buffer circuit portions (183, 184) comprising N-FETs connected to corresponding Column Buffer circuit portions in the PMOS circuit layer; wherein the array of pixel elements is triggered using an electronic global shutter, without requiring a mechanical shutter.