A semiconductor integrated circuit comprising: an AD converter for converting an analog signal received in synchronization with a sampling pulse into a digital signal (DOUT); a frequency detecting circuit for detecting frequency of said sampling pulse, and outputting the detected frequency as a detection value (VOUT); and a current adjusting circuit for adjusting a power supply current to be supplied to said AD converter in accordance with said detection value (VOUT); wherein said AD converter includes a plurality of cascaded AD conversion units for sequentially generating a plurality of bits of said digital signal in units of k bits of digital values, and an operational circuit for synthesizing said k bits of digital values generated sequentially into said plurality of bits of digital signal; each of said AD conversion units including: a holding unit (S/H) for holding an analog value output from said AD conversion unit at the preceding stage or said analog signal in synchronization with said sampling pulse, a sub AD converter for converting said analog value or said analog signal held by said holding unit (S/H) into k bits of digital value, a sub DA converter for converting said digital value converted by said sub AD converter into an analog value, a subtracter for subtracting said analog value converted by said sub DA converter from said analog value or said analog signal held by said holding unit (S/H), and a multiplier for multiplying an analog signal output from said subtracter by 2 k, and supplying the multiplied value to said holding unit S/H at the next stage; characterised in that the said current adjusting circuit is operable to adjust a plurality of types of bias voltages (VB1-VB4) each of which is for adjusting a power supply current to be supplied to each of said multipliers, in accordance with said detection value (VOUT), the current adjusting circuit being further operable to supply the said bias voltages (VB1-VB4) to the said multipliers respectively. an AD converter for converting an analog signal received in synchronization with a sampling pulse into a digital signal (DOUT); a frequency detecting circuit for detecting frequency of said sampling pulse, and outputting the detected frequency as a detection value (VOUT); and a current adjusting circuit for adjusting a power supply current to be supplied to said AD converter in accordance with said detection value (VOUT); wherein said AD converter includes a plurality of cascaded AD conversion units for sequentially generating a plurality of bits of said digital signal in units of k bits of digital values, and an operational circuit for synthesizing said k bits of digital values generated sequentially into said plurality of bits of digital signal; each of said AD conversion units including: a holding unit (S/H) for holding an analog value output from said AD conversion unit at the preceding stage or said analog signal in synchronization with said sampling pulse, a sub AD converter for converting said analog value or said analog signal held by said holding unit (S/H) into k bits of digital value, a sub DA converter for converting said digital value converted by said sub AD converter into an analog value, a holding unit (S/H) for holding an analog value output from said AD conversion unit at the preceding stage or said analog signal in synchronization with said sampling pulse, a sub AD converter for converting said analog value or said analog signal held by said holding unit (S/H) into k bits of digital value, a sub DA converter for converting said digital value converted by said sub AD converter into an analog value, a subtracter for subtracting said analog value converted by said sub DA converter from said analog value or said analog signal held by said holding unit (S/H), and a multiplier for multiplying an analog signal output from said subtracter by 2 k, and supplying the multiplied value to said holding unit S/H at the next stage; characterised in that the said current adjusting circuit is operable to adjust a plurality of types of bias voltages (VB1-VB4) each of which is for adjusting a power supply current to be supplied to each of said multipliers, in accordance with said detection value (VOUT), the current adjusting circuit being further operable to supply the said bias voltages (VB1-VB4) to the said multipliers respectively.