A method for controlling a high-voltage switching circuit with low-voltage control signals, said method comprising: providing non-overlapping clock signals (clk, clkb); providing a low-voltage inverter (102, 104; 202, 204) coupled to a first clock signal (clkb) of the non-overlapping clock signals; providing a first high-voltage transistor (118; 218) having a gate, a drain and a source, the drain being coupled directly to an output of the low-voltage inverter (102, 104; 202, 204) and the source being coupled to a first node (Node 1), wherein a second clock signal (clk) of the non-overlapping clock signals controls a coupling of the gate of the first high-voltage transistor (118; 218) with ground; providing a second high-voltage transistor (114; 214) having a gate coupled directly with the first node (Node 1) and a source coupled with the output of the low voltage inverter (102; 104; 202, 204); and providing a primary input/output signal path receiving a high voltage and comprising back-to-back drain source paths of third and fourth high-voltage transistors (128; 228, 132; 232) whose gates are coupled to a drain of the second high-voltage transistor (114; 214); wherein when the low-voltage inverter (102. 104) drives its output voltage from high to low, a voltage at the first node (Node 1) is pulled down through the first high-voltage transistor (118; 218) thereby turning on the second high-voltage transistor (114; 214), and the second high-voltage transistor (114; 214) enables the primary input/output signal path to conduct by turning on the third and fourth high-voltage transistors (128, 132; 229, 232) and the gates of the third and fourth high-voltage transistors (128, 132; 229, 232) are released from ground through a control circuit (134, 136; 234, 236), wherein a first terminal of a bootstrap capacitor (110; 210) is coupled to the source of the second high-voltage transistor (114; 214) and a second terminal of the bootstrap capacitor receives the high voltage or a similar voltage and is coupled with the gate of the first high-voltage transistor (118; 218) to receive a switching voltage across its first and second terminals. providing non-overlapping clock signals (clk, clkb); providing a low-voltage inverter (102, 104; 202, 204) coupled to a first clock signal (clkb) of the non-overlapping clock signals; providing a first high-voltage transistor (118; 218) having a gate, a drain and a source, the drain being coupled directly to an output of the low-voltage inverter (102, 104; 202, 204) and the source being coupled to a first node (Node 1), wherein a second clock signal (clk) of the non-overlapping clock signals controls a coupling of the gate of the first high-voltage transistor (118; 218) with ground; providing a second high-voltage transistor (114; 214) having a gate coupled directly with the first node (Node 1) and a source coupled with the output of the low voltage inverter (102; 104; 202, 204); and providing a primary input/output signal path receiving a high voltage and comprising back-to-back drain source paths of third and fourth high-voltage transistors (128; 228, 132; 232) whose gates are coupled to a drain of the second high-voltage transistor (114; 214); wherein when the low-voltage inverter (102. 104) drives its output voltage from high to low, a voltage at the first node (Node 1) is pulled down through the first high-voltage transistor (118; 218) thereby turning on the second high-voltage transistor (114; 214), and the second high-voltage transistor (114; 214) enables the primary input/output signal path to conduct by turning on the third and fourth high-voltage transistors (128, 132; 229, 232) and the gates of the third and fourth high-voltage transistors (128, 132; 229, 232) are released from ground through a control circuit (134, 136; 234, 236), wherein a first terminal of a bootstrap capacitor (110; 210) is coupled to the source of the second high-voltage transistor (114; 214) and a second terminal of the bootstrap capacitor receives the high voltage or a similar voltage and is coupled with the gate of the first high-voltage transistor (118; 218) to receive a switching voltage across its first and second terminals. when the low-voltage inverter (102. 104) drives its output voltage from high to low, a voltage at the first node (Node 1) is pulled down through the first high-voltage transistor (118; 218) thereby turning on the second high-voltage transistor (114; 214), and the second high-voltage transistor (114; 214) enables the primary input/output signal path to conduct by turning on the third and fourth high-voltage transistors (128, 132; 229, 232) and the gates of the third and fourth high-voltage transistors (128, 132; 229, 232) are released from ground through a control circuit (134, 136; 234, 236), wherein a first terminal of a bootstrap capacitor (110; 210) is coupled to the source of the second high-voltage transistor (114; 214) and a second terminal of the bootstrap capacitor receives the high voltage or a similar voltage and is coupled with the gate of the first high-voltage transistor (118; 218) to receive a switching voltage across its first and second terminals.