A comparator device for comparing an analog signal with a reference signal (SREF), comprising • a first input terminal connectable with a reference signal generator generating said reference signal (SREF), • a second input terminal connectable with a signal providing device providing said analog signal, • a first comparator circuit for comparing the analog signal with the reference signal (S REF) and for generating a first output signal (S OUT), said first comparator circuit comprising a first input device, a second input device, and an first output for outputting the first output signal (S OUT) generated by the first comparator circuit, and wherein said first input device and said second input device comprise respectively a first and a second CMOS transistor and wherein a gate of the first CMOS transistor is connected with said first input terminal for receiving said reference signal (S REF) and a gate of said second transistor is connected with the second input terminal for receiving the analog signal, wherein said comparator device comprises • a compensating device comprising i) a controlling device configured for sensing an operational parameter of said first input device and wherein a variation (ΔV) of said operational parameter is generating a first variation of an input load to the reference signal, wherein said operational parameter is a drain voltage of said first CMOS transistor, and ii) a third input device operable for generating a second variation of the input load to the reference signal, and wherein said third input device comprises a compensating CMOS transistor having a gate connected to the first input terminal for receiving said reference signal (SREF), wherein the third input device is essentially identical to the first input device and wherein said controlling device is configured for controlling said third input device such that any first variation of the input load through the first input device is cancelled out by a complementary second variation of the input load through the third input device, and wherein the controlling device is operable for increasing a drain current (I COM) flowing through the compensating CMOS transistor if the drain current flowing through the first CMOS transistor of the first input device is decreasing, and vice versa, such that that the sum of the drain current flowing through the first CMOS transistor of the first input device and the drain current flowing through the compensating CMOS transistor of the third input device remains constant. • a first input terminal connectable with a reference signal generator generating said reference signal (SREF), • a second input terminal connectable with a signal providing device providing said analog signal, • a first comparator circuit for comparing the analog signal with the reference signal (S REF) and for generating a first output signal (S OUT), said first comparator circuit comprising a first input device, a second input device, and an first output for outputting the first output signal (S OUT) generated by the first comparator circuit, and wherein said first input device and said second input device comprise respectively a first and a second CMOS transistor and wherein a gate of the first CMOS transistor is connected with said first input terminal for receiving said reference signal (S REF) and a gate of said second transistor is connected with the second input terminal for receiving the analog signal, wherein said comparator device comprises • a compensating device comprising i) a controlling device configured for sensing an operational parameter of said first input device and wherein a variation (ΔV) of said operational parameter is generating a first variation of an input load to the reference signal, wherein said operational parameter is a drain voltage of said first CMOS transistor, and ii) a third input device operable for generating a second variation of the input load to the reference signal, and wherein said third input device comprises a compensating CMOS transistor having a gate connected to the first input terminal for receiving said reference signal (SREF), wherein the third input device is essentially identical to the first input device and wherein said controlling device is configured for controlling said third input device such that any first variation of the input load through the first input device is cancelled out by a complementary second variation of the input load through the third input device, and wherein the controlling device is operable for increasing a drain current (I COM) flowing through the compensating CMOS transistor if the drain current flowing through the first CMOS transistor of the first input device is decreasing, and vice versa, such that that the sum of the drain current flowing through the first CMOS transistor of the first input device and the drain current flowing through the compensating CMOS transistor of the third input device remains constant. i) a controlling device configured for sensing an operational parameter of said first input device and wherein a variation (ΔV) of said operational parameter is generating a first variation of an input load to the reference signal, wherein said operational parameter is a drain voltage of said first CMOS transistor, and ii) a third input device operable for generating a second variation of the input load to the reference signal, and wherein said third input device comprises a compensating CMOS transistor having a gate connected to the first input terminal for receiving said reference signal (SREF),