A processing device comprising: a core configured to execute instructions; and memory management circuitry coupled to, memory, the core, one or more I/O devices that support page faults, and one or more I/O devices that do not support page faults, the memory management circuitry comprising: an express invalidations circuitry; and a page translation permission circuitry, wherein the memory management circuitry is configured to: receive, by the express invalidations circuitry, a list of the one or more I/O devices that support page faults determined by system software; while the core is executing the instructions: receive a command to pause communication between an I/O device and the memory; and in response to receiving the command to pause the communication: modify permissions of page translation responses by the page translation permission circuitry; look up, by the express invalidations circuitry, the list of the one or more I/O devices that support page faults; and transmit an invalidation request, by the express invalidations circuitry to any of the one or more I/O devices in the list, to cause cached page translations in the I/O devices to be invalidated. a core configured to execute instructions; and memory management circuitry coupled to, memory, the core, one or more I/O devices that support page faults, and one or more I/O devices that do not support page faults, the memory management circuitry comprising: an express invalidations circuitry; and a page translation permission circuitry, wherein the memory management circuitry is configured to: receive, by the express invalidations circuitry, a list of the one or more I/O devices that support page faults determined by system software; while the core is executing the instructions: receive a command to pause communication between an I/O device and the memory; and in response to receiving the command to pause the communication: modify permissions of page translation responses by the page translation permission circuitry; look up, by the express invalidations circuitry, the list of the one or more I/O devices that support page faults; and transmit an invalidation request, by the express invalidations circuitry to any of the one or more I/O devices in the list, to cause cached page translations in the I/O devices to be invalidated. an express invalidations circuitry; and a page translation permission circuitry, wherein the memory management circuitry is configured to: receive, by the express invalidations circuitry, a list of the one or more I/O devices that support page faults determined by system software; while the core is executing the instructions: receive a command to pause communication between an I/O device and the memory; and in response to receiving the command to pause the communication: modify permissions of page translation responses by the page translation permission circuitry; look up, by the express invalidations circuitry, the list of the one or more I/O devices that support page faults; and transmit an invalidation request, by the express invalidations circuitry to any of the one or more I/O devices in the list, to cause cached page translations in the I/O devices to be invalidated. receive, by the express invalidations circuitry, a list of the one or more I/O devices that support page faults determined by system software; while the core is executing the instructions: receive a command to pause communication between an I/O device and the memory; and in response to receiving the command to pause the communication: modify permissions of page translation responses by the page translation permission circuitry; look up, by the express invalidations circuitry, the list of the one or more I/O devices that support page faults; and transmit an invalidation request, by the express invalidations circuitry to any of the one or more I/O devices in the list, to cause cached page translations in the I/O devices to be invalidated. receive a command to pause communication between an I/O device and the memory; and in response to receiving the command to pause the communication: modify permissions of page translation responses by the page translation permission circuitry; look up, by the express invalidations circuitry, the list of the one or more I/O devices that support page faults; and transmit an invalidation request, by the express invalidations circuitry to any of the one or more I/O devices in the list, to cause cached page translations in the I/O devices to be invalidated. modify permissions of page translation responses by the page translation permission circuitry; look up, by the express invalidations circuitry, the list of the one or more I/O devices that support page faults; and transmit an invalidation request, by the express invalidations circuitry to any of the one or more I/O devices in the list, to cause cached page translations in the I/O devices to be invalidated.