An apparatus for storing and providing configuration data to a multi-core processor, the apparatus comprising: a plurality of cores (332, 1102), disposed on a die, wherein each of said plurality of cores (332, 1102) comprises an array control that is programmed with load data within a load data register; a random access memory, disposed on the die; and a fuse array (336, 1101), disposed on said die and coupled to each of said plurality of cores, wherein said fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for said each of said plurality of cores, and wherein said each of said plurality of cores (332, 1102) accesses and decompresses all of said compressed configuration data upon power-up/reset, for initialization of elements within said each of said plurality of cores, wherein said compressed configuration data is compressed using distinct compression algorithms corresponding to each of a plurality of data types, wherein said compressed configuration data corresponds to uncompressed data within a virtual fuse array associated with said plurality of cores, and wherein said fuse array (336, 1101) further comprises another plurality of semiconductor fuses programmed with uncompressed system hardware configuration data that is employed to initialize control circuit elements within said each of said plurality of cores, characterized in that: each of said plurality of cores (332, 1102) is adapted to receive load data within the load data register that indicates a specified load order for data corresponding to the fuse array (336, 1101), the value of contents of the load register designates one of said plurality of cores (332, 1102) as a master core, and the remaining cores as slave cores having a load order associated therewith, upon power-up/reset, the array control is adapted to direct the master core to read the contents of the fuse array (336, 1101) and then to write the contents of the fuse array (336, 1101) to the random access memory, and after the master core has written the contents of said fuse array (336, 1101) to the random access memory, then the array control is adapted to direct heir corresponding slave cores to read the contents from the random access memory in the order specified by contents of the load data register. a plurality of cores (332, 1102), disposed on a die, wherein each of said plurality of cores (332, 1102) comprises an array control that is programmed with load data within a load data register; a random access memory, disposed on the die; and a fuse array (336, 1101), disposed on said die and coupled to each of said plurality of cores, wherein said fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for said each of said plurality of cores, and wherein said each of said plurality of cores (332, 1102) accesses and decompresses all of said compressed configuration data upon power-up/reset, for initialization of elements within said each of said plurality of cores, wherein said compressed configuration data is compressed using distinct compression algorithms corresponding to each of a plurality of data types, wherein said compressed configuration data corresponds to uncompressed data within a virtual fuse array associated with said plurality of cores, and wherein said fuse array (336, 1101) further comprises another plurality of semiconductor fuses programmed with uncompressed system hardware configuration data that is employed to initialize control circuit elements within said each of said plurality of cores, each of said plurality of cores (332, 1102) is adapted to receive load data within the load data register that indicates a specified load order for data corresponding to the fuse array (336, 1101), the value of contents of the load register designates one of said plurality of cores (332, 1102) as a master core, and the remaining cores as slave cores having a load order associated therewith, upon power-up/reset, the array control is adapted to direct the master core to read the contents of the fuse array (336, 1101) and then to write the contents of the fuse array (336, 1101) to the random access memory, and after the master core has written the contents of said fuse array (336, 1101) to the random access memory, then the array control is adapted to direct heir corresponding slave cores to read the contents from the random access memory in the order specified by contents of the load data register.