A logic circuit comprising: a plurality of function blocks (110, 111) forming a redundant system and configured to output pieces of data, each piece of data including a bit string; a plurality of test pattern generation circuits (100, 101) configured to combine test patterns for abnormality detection with the pieces of data outputted from the function blocks (110, 111); and a comparison circuit (30 - 3n) configured to make a comparison between the pieces of data combined with the test patterns, characterized in that: the logic circuit further comprises synchronizing means, wherein: the synchronizing means comprises an element arranged to receive data increment signals (214A, 214B) from each of the plurality of function blocks (110, 111) respectively, and then to output a signal to synchronize the timing for outputting the next data by the plurality of function blocks (110, 111); the synchronizing means further comprises a further element and a counter, wherein the further element is arranged to receive orthogonal waveform increment signals (211A, 211B) from the plurality of function blocks (110, 111), respectively, and to then output a signal that increments the counter for generating an argument x, whereby the counter alternately outputs to the plurality of test pattern generation circuits (100, 101) an argument x indicating the state that a test pattern is to be combined with the pieces of data outputted from the function blocks (110, 111) and an argument x indicating the state that a test pattern is not to be combined with the pieces of data outputted from the function blocks (110, 111). a plurality of function blocks (110, 111) forming a redundant system and configured to output pieces of data, each piece of data including a bit string; a plurality of test pattern generation circuits (100, 101) configured to combine test patterns for abnormality detection with the pieces of data outputted from the function blocks (110, 111); and a comparison circuit (30 - 3n) configured to make a comparison between the pieces of data combined with the test patterns, characterized in that: the logic circuit further comprises synchronizing means, wherein: the synchronizing means comprises an element arranged to receive data increment signals (214A, 214B) from each of the plurality of function blocks (110, 111) respectively, and then to output a signal to synchronize the timing for outputting the next data by the plurality of function blocks (110, 111); the synchronizing means further comprises a further element and a counter, wherein the further element is arranged to receive orthogonal waveform increment signals (211A, 211B) from the plurality of function blocks (110, 111), respectively, and to then output a signal that increments the counter for generating an argument x, whereby the counter alternately outputs to the plurality of test pattern generation circuits (100, 101) an argument x indicating the state that a test pattern is to be combined with the pieces of data outputted from the function blocks (110, 111) and an argument x indicating the state that a test pattern is not to be combined with the pieces of data outputted from the function blocks (110, 111). the synchronizing means comprises an element arranged to receive data increment signals (214A, 214B) from each of the plurality of function blocks (110, 111) respectively, and then to output a signal to synchronize the timing for outputting the next data by the plurality of function blocks (110, 111); the synchronizing means further comprises a further element and a counter, wherein the further element is arranged to receive orthogonal waveform increment signals (211A, 211B) from the plurality of function blocks (110, 111), respectively, and to then output a signal that increments the counter for generating an argument x, whereby the counter alternately outputs to the plurality of test pattern generation circuits (100, 101) an argument x indicating the state that a test pattern is to be combined with the pieces of data outputted from the function blocks (110, 111) and an argument x indicating the state that a test pattern is not to be combined with the pieces of data outputted from the function blocks (110, 111).