A system comprising: a processor arranged to assign a transaction identifier to each memory request issued by the processor; and a module (202, 502) comprising: an assignment module (212, 512R, 512W) arranged to receive memory requests from a cache, wherein the memory requests received from the cache include a transaction identifier assigned by the processor and one or more memory addresses defined in a virtual address space; a transaction tracker module (214, 514R, 514W) arranged to receive a memory request from the assignment module with the assigned transaction identifier, to track the status of the memory request and to receive translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in the memory request to a physical memory address or a pointer to the translation; and an arbiter module (216, 516R, 516W) arranged to receive a memory request from the transaction tracker module with the assigned transaction identifier when the memory request is ready for issue and to issue the memory request to a memory via an external bus and to trigger the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information and wherein the arbiter module is further arranged to receive a memory read request from the memory management unit with a transaction identifier assigned by the memory management unit and to select the memory read request from the memory management unit for issue ahead of any memory requests received from the transaction tracker module which have not yet been issued. a processor arranged to assign a transaction identifier to each memory request issued by the processor; and a module (202, 502) comprising: an assignment module (212, 512R, 512W) arranged to receive memory requests from a cache, wherein the memory requests received from the cache include a transaction identifier assigned by the processor and one or more memory addresses defined in a virtual address space; a transaction tracker module (214, 514R, 514W) arranged to receive a memory request from the assignment module with the assigned transaction identifier, to track the status of the memory request and to receive translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in the memory request to a physical memory address or a pointer to the translation; and an arbiter module (216, 516R, 516W) arranged to receive a memory request from the transaction tracker module with the assigned transaction identifier when the memory request is ready for issue and to issue the memory request to a memory via an external bus and to trigger the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information and wherein the arbiter module is further arranged to receive a memory read request from the memory management unit with a transaction identifier assigned by the memory management unit and to select the memory read request from the memory management unit for issue ahead of any memory requests received from the transaction tracker module which have not yet been issued. an assignment module (212, 512R, 512W) arranged to receive memory requests from a cache, wherein the memory requests received from the cache include a transaction identifier assigned by the processor and one or more memory addresses defined in a virtual address space; a transaction tracker module (214, 514R, 514W) arranged to receive a memory request from the assignment module with the assigned transaction identifier, to track the status of the memory request and to receive translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in the memory request to a physical memory address or a pointer to the translation; and an arbiter module (216, 516R, 516W) arranged to receive a memory request from the transaction tracker module with the assigned transaction identifier when the memory request is ready for issue and to issue the memory request to a memory via an external bus and to trigger the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information and wherein the arbiter module is further arranged to receive a memory read request from the memory management unit with a transaction identifier assigned by the memory management unit and to select the memory read request from the memory management unit for issue ahead of any memory requests received from the transaction tracker module which have not yet been issued.