A continuous-time integrator comprising: a digital-to-analog converter; a plurality of input resistors (510, 512); a differential operational amplifier; characterized by: a first fixed capacitor connected to a non-inverting input of the differential operational amplifier and to a first output of the differential operational amplifier; a second fixed capacitor connected to an inverting input of the differential operational amplifier and to a second output of the differential operational amplifier; a plurality of programmable capacitor arrays (514, 516), a first programmable capacitor array connected to the first fixed capacitor and a second programmable capacitor array connected to the second fixed capacitor; a plurality of switches (506, 508) controllable via a hybrid tuning circuit; said hybrid tuning circuit further comprising an analog control circuit comprising a hybrid tuning circuit programmable capacitor array and a second plurality of switches to generate and adjust an integration control signal via controlling said first plurality of switches (506, 508); said integration control signal controlling an integration time of said continuous-time integrator; and a finite state machine monitoring said integration control signal, said finite state machine decrementing and incrementing capacitor size in said first, second, and hybrid tuning circuit programmable capacitor arrays; wherein said first plurality of switches (506, 508) either connect said input resistors (510, 512) and differential DAC outputs to respective summing junctions at respective differential inputs of said operational amplifier during an integration period, or said first plurality of switches (506, 508) disconnect said resistors (510, 512) and said differential DAC outputs from said operational amplifier and connect said input resistors (510, 512) and said differential DAC outputs to a known voltage (V ref). a digital-to-analog converter; a plurality of input resistors (510, 512); a differential operational amplifier; characterized by: a first fixed capacitor connected to a non-inverting input of the differential operational amplifier and to a first output of the differential operational amplifier; a second fixed capacitor connected to an inverting input of the differential operational amplifier and to a second output of the differential operational amplifier; a plurality of programmable capacitor arrays (514, 516), a first programmable capacitor array connected to the first fixed capacitor and a second programmable capacitor array connected to the second fixed capacitor; a plurality of switches (506, 508) controllable via a hybrid tuning circuit; said hybrid tuning circuit further comprising an analog control circuit comprising a hybrid tuning circuit programmable capacitor array and a second plurality of switches to generate and adjust an integration control signal via controlling said first plurality of switches (506, 508); said integration control signal controlling an integration time of said continuous-time integrator; and a finite state machine monitoring said integration control signal, said finite state machine decrementing and incrementing capacitor size in said first, second, and hybrid tuning circuit programmable capacitor arrays; wherein said first plurality of switches (506, 508) either connect said input resistors (510, 512) and differential DAC outputs to respective summing junctions at respective differential inputs of said operational amplifier during an integration period, or said first plurality of switches (506, 508) disconnect said resistors (510, 512) and said differential DAC outputs from said operational amplifier and connect said input resistors (510, 512) and said differential DAC outputs to a known voltage (V ref). a first fixed capacitor connected to a non-inverting input of the differential operational amplifier and to a first output of the differential operational amplifier; a second fixed capacitor connected to an inverting input of the differential operational amplifier and to a second output of the differential operational amplifier; a plurality of programmable capacitor arrays (514, 516), a first programmable capacitor array connected to the first fixed capacitor and a second programmable capacitor array connected to the second fixed capacitor; a plurality of switches (506, 508) controllable via a hybrid tuning circuit; said hybrid tuning circuit further comprising an analog control circuit comprising a hybrid tuning circuit programmable capacitor array and a second plurality of switches to generate and adjust an integration control signal via controlling said first plurality of switches (506, 508); said integration control signal controlling an integration time of said continuous-time integrator; and a finite state machine monitoring said integration control signal, said finite state machine decrementing and incrementing capacitor size in said first, second, and hybrid tuning circuit programmable capacitor arrays; wherein said first plurality of switches (506, 508) either connect said input resistors (510, 512) and differential DAC outputs to respective summing junctions at respective differential inputs of said operational amplifier during an integration period, or said first plurality of switches (506, 508) disconnect said resistors (510, 512) and said differential DAC outputs from said operational amplifier and connect said input resistors (510, 512) and said differential DAC outputs to a known voltage (V ref).