A device comprising: a splitter configured to receive two input values and, for each input value of the two input values: if the each input value is a signed value, convert the each input value to a sign value and a magnitude value for the each input value; and if the each input value is an unsigned value set the magnitude value of the each input value to be the each input value; a checker configured to convert the magnitude values of the two input values to one or more pairs of input arguments; and a computation unit configured to perform an operation on each pair of the one or more pairs of input arguments and any sign values of the two input values and produce an output according to the operation; wherein input arguments of the one or more pairs of input arguments have N bits, N being a predefined integer; and wherein the checker is further configured to convert the magnitude values of the two input values into the one or more pairs of input arguments by: (a) for a first magnitude of the magnitude values of the two input values: if M1 corresponds to a first input value of the two input values that is signed and is larger than 2^N - 1, represent M1 with arguments Arg1_1 = 2^(N-1) and Arg1_2 = 2^(N-1); and (b) for a second magnitude of the magnitude values of the two input values: if M2 corresponds to a second input value of the two input values that is signed and is larger than 2^N - 1, represent M2 with arguments Arg2_1 = 2^(N-1) and Arg2_2 = 2^(N-1); and wherein the computational unit includes one or more multiplier circuits having two N-1 bit multiplier inputs. a splitter configured to receive two input values and, for each input value of the two input values: if the each input value is a signed value, convert the each input value to a sign value and a magnitude value for the each input value; and if the each input value is an unsigned value set the magnitude value of the each input value to be the each input value; if the each input value is a signed value, convert the each input value to a sign value and a magnitude value for the each input value; and if the each input value is an unsigned value set the magnitude value of the each input value to be the each input value; a checker configured to convert the magnitude values of the two input values to one or more pairs of input arguments; and a computation unit configured to perform an operation on each pair of the one or more pairs of input arguments and any sign values of the two input values and produce an output according to the operation; wherein input arguments of the one or more pairs of input arguments have N bits, N being a predefined integer; and wherein the checker is further configured to convert the magnitude values of the two input values into the one or more pairs of input arguments by: (a) for a first magnitude of the magnitude values of the two input values: if M1 corresponds to a first input value of the two input values that is signed and is larger than 2^N - 1, represent M1 with arguments Arg1_1 = 2^(N-1) and Arg1_2 = 2^(N-1); and (b) for a second magnitude of the magnitude values of the two input values: if M2 corresponds to a second input value of the two input values that is signed and is larger than 2^N - 1, represent M2 with arguments Arg2_1 = 2^(N-1) and Arg2_2 = 2^(N-1); and wherein the computational unit includes one or more multiplier circuits having two N-1 bit multiplier inputs. (a) for a first magnitude of the magnitude values of the two input values: if M1 corresponds to a first input value of the two input values that is signed and is larger than 2^N - 1, represent M1 with arguments Arg1_1 = 2^(N-1) and Arg1_2 = 2^(N-1); and (b) for a second magnitude of the magnitude values of the two input values: if M2 corresponds to a second input value of the two input values that is signed and is larger than 2^N - 1, represent M2 with arguments Arg2_1 = 2^(N-1) and Arg2_2 = 2^(N-1); and wherein the computational unit includes one or more multiplier circuits having two N-1 bit multiplier inputs. if M2 corresponds to a second input value of the two input values that is signed and is larger than 2^N - 1, represent M2 with arguments Arg2_1 = 2^(N-1) and Arg2_2 = 2^(N-1); and wherein the computational unit includes one or more multiplier circuits having two N-1 bit multiplier inputs.