A Complementary Metal-Oxide-Silicon (CMOS) image sensor comprising: a two-dimensional pixel array composed of unit pixels, each unit pixel having a photo diode and transistors (Rx, Dx, Tx, Sx); a row decoder located at an end of the pixel array to assign row addresses; and a column decoder located at another end of the pixel array, which is perpendicular to the row decoder, to assign column addresses to corresponding pixels in a row selected by the row decoder; wherein the row decoder comprises a plurality of row decoder cells, each of the row decoder cells including: an address signal input line; a transfer signal input line; a selection signal input line; a reset signal input line; a reset gate signal output unit configured for outputting a reset gate signal that is generated in response to a reset signal, which is entered through the reset signal input line, and an address signal, which is entered through the address signal input line; a selection gate signal output unit configured for outputting a selection gate signal that is generated in response to a selection signal, which is entered through the selection signal input line, and the address signal, which is entered through the address signal input line; and a transfer signal output line configured for outputting a transfer signal which is entered through the transfer signal input line, wherein the transfer signal is directly output from the transfer signal input line to the transfer signal output line; the CMOS image sensor being characterized in that it further comprises a reduction rate measurement unit configured for measuring a rate of reduction between outputs from first to n-th row data that are sequentially output from the CMOS image sensor according to an operation of the row decoder, where n is a natural number, and wherein the CMOS image sensor further includes a gain compensation unit configured for sequentially adding predetermined amounts of gain, which depends on the reduction rate measured by the reduction rate measurement unit, to outputs from first to n-th row. a two-dimensional pixel array composed of unit pixels, each unit pixel having a photo diode and transistors (Rx, Dx, Tx, Sx); a row decoder located at an end of the pixel array to assign row addresses; and a column decoder located at another end of the pixel array, which is perpendicular to the row decoder, to assign column addresses to corresponding pixels in a row selected by the row decoder; wherein the row decoder comprises a plurality of row decoder cells, each of the row decoder cells including: an address signal input line; a transfer signal input line; a selection signal input line; a reset signal input line; a reset gate signal output unit configured for outputting a reset gate signal that is generated in response to a reset signal, which is entered through the reset signal input line, and an address signal, which is entered through the address signal input line; a selection gate signal output unit configured for outputting a selection gate signal that is generated in response to a selection signal, which is entered through the selection signal input line, and the address signal, which is entered through the address signal input line; and a transfer signal output line configured for outputting a transfer signal which is entered through the transfer signal input line, wherein the transfer signal is directly output from the transfer signal input line to the transfer signal output line; the CMOS image sensor being characterized in that it further comprises a reduction rate measurement unit configured for measuring a rate of reduction between outputs from first to n-th row data that are sequentially output from the CMOS image sensor according to an operation of the row decoder, where n is a natural number, and wherein the CMOS image sensor further includes a gain compensation unit configured for sequentially adding predetermined amounts of gain, which depends on the reduction rate measured by the reduction rate measurement unit, to outputs from first to n-th row. an address signal input line; a transfer signal input line; a selection signal input line; a reset signal input line; a reset gate signal output unit configured for outputting a reset gate signal that is generated in response to a reset signal, which is entered through the reset signal input line, and an address signal, which is entered through the address signal input line; a selection gate signal output unit configured for outputting a selection gate signal that is generated in response to a selection signal, which is entered through the selection signal input line, and the address signal, which is entered through the address signal input line; and a transfer signal output line configured for outputting a transfer signal which is entered through the transfer signal input line, wherein the transfer signal is directly output from the transfer signal input line to the transfer signal output line; the CMOS image sensor being characterized in that it further comprises a reduction rate measurement unit configured for measuring a rate of reduction between outputs from first to n-th row data that are sequentially output from the CMOS image sensor according to an operation of the row decoder, where n is a natural number, and wherein the CMOS image sensor further includes a gain compensation unit configured for sequentially adding predetermined amounts of gain, which depends on the reduction rate measured by the reduction rate measurement unit, to outputs from first to n-th row.