A receiver, comprising: a strong-arm latch configured to sample a differential input voltage (AMP_OP, AMP_OM) according to a sampling clock signal and comprising a differential input pair including first and second input transistors (M1, M2), each of the first and second input transistors (M1, M2) having a gate, a source and a drain, wherein the gates of the first and second input transistors (M1, M2) are configured to receive the differential input voltage (AMP_OP, AMP_OM) and the source of the first input transistor is connected to the source of the second input transistor; a first plurality of offset-compensation segments coupled in parallel between the drain and the source of the first input transistor of the strong-arm latch and a second plurality of offset-compensation segments coupled in parallel between the drain and the source of the second input transistor of the strong-arm latch, wherein each segment (315-1 and 515-1, 315-n and 515-n, 325-1 and 525-1, 325-n and 525-n) of the first and second plurality of offset-compensation segments (510, 520) comprises: a compensation transistor (315-1, 315-n, 325-1, 325-n) having a source connected to the sources of the first and second input transistors (M1, M2); and a step-adjustment transistor (515-1, 515-n, 525-1, 525-n) coupled in series with the compensation transistor (315-1, 315-n, 325-1, 325-n); an offset controller configured to selectively turn on one or more of the compensation transistors (315-1, 315-n, 325-1, 325-n) of the first and second plurality of offset-compensation segments (510, 520) to reduce an offset voltage of the strong-arm latch; and a bias circuit configured to generate a bias voltage based on a common-mode voltage of the differential input voltage (AMP_OP, AMP_OM) and to apply the bias voltage to a gate of each step-adjustment transistor (515-1, 515-n, 525-1, 525-n) of the first and second plurality of offset-compensation segments (510, 520); wherein the bias circuit is configured to adjust the bias voltage to adjust an offset-compensation step size by controlling a channel conductance of each step-adjustment transistor (515-1, 515-n, 525-1, 525-n) of the first and second plurality of offset-compensation segments (510, 520), and thereby configured to control an amount of current that flows into a respective compensation transistor if the respective compensation transistor is turned on. a strong-arm latch configured to sample a differential input voltage (AMP_OP, AMP_OM) according to a sampling clock signal and comprising a differential input pair including first and second input transistors (M1, M2), each of the first and second input transistors (M1, M2) having a gate, a source and a drain, wherein the gates of the first and second input transistors (M1, M2) are configured to receive the differential input voltage (AMP_OP, AMP_OM) and the source of the first input transistor is connected to the source of the second input transistor; a first plurality of offset-compensation segments coupled in parallel between the drain and the source of the first input transistor of the strong-arm latch and a second plurality of offset-compensation segments coupled in parallel between the drain and the source of the second input transistor of the strong-arm latch, wherein each segment (315-1 and 515-1, 315-n and 515-n, 325-1 and 525-1, 325-n and 525-n) of the first and second plurality of offset-compensation segments (510, 520) comprises: a compensation transistor (315-1, 315-n, 325-1, 325-n) having a source connected to the sources of the first and second input transistors (M1, M2); and a step-adjustment transistor (515-1, 515-n, 525-1, 525-n) coupled in series with the compensation transistor (315-1, 315-n, 325-1, 325-n); a compensation transistor (315-1, 315-n, 325-1, 325-n) having a source connected to the sources of the first and second input transistors (M1, M2); and a step-adjustment transistor (515-1, 515-n, 525-1, 525-n) coupled in series with the compensation transistor (315-1, 315-n, 325-1, 325-n); an offset controller configured to selectively turn on one or more of the compensation transistors (315-1, 315-n, 325-1, 325-n) of the first and second plurality of offset-compensation segments (510, 520) to reduce an offset voltage of the strong-arm latch; and a bias circuit configured to generate a bias voltage based on a common-mode voltage of the differential input voltage (AMP_OP, AMP_OM) and to apply the bias voltage to a gate of each step-adjustment transistor (515-1, 515-n, 525-1, 525-n) of the first and second plurality of offset-compensation segments (510, 520); wherein the bias circuit is configured to adjust the bias voltage to adjust an offset-compensation step size by controlling a channel conductance of each step-adjustment transistor (515-1, 515-n, 525-1, 525-n) of the first and second plurality of offset-compensation segments (510, 520), and thereby configured to control an amount of current that flows into a respective compensation transistor if the respective compensation transistor is turned on.