Analogue-to-digital converter implemented as a successive approximation based analogue-to-digital converter arranged to convert an input voltage signal into a digital output signal representing said input voltage signal, said analogue-to-digital converter comprising sampling means arranged to sample said input voltage signal, a digital-to-analogue converter, DAC, comprising circuitry arranged to receive said sampled input voltage signal characterised in that said DAC is arranged to generate a calibration signal in a calibration mode and a search signal approximating said input voltage signal in a subsequent quantisation mode, said circuitry comprising a plurality of capacitances, said analogue-to-digital converter further comprising: one or more comparators arranged to receive said calibration signal in said calibration mode and said search signal in said quantisation mode and to receive said sampled input voltage signal, a block arranged to receive a comparator output signal from said one or more comparators, to produce said digital output signal and, during said quantisation mode, to perform a successive approximation search algorithm on said comparator output signal and to adjust a first control signal which is outputted to said DAC for generating said search signal, whereby said search signal applied to said comparator is successively closer to said sampled input voltage signal, calibration logic block arranged to produce a second control signal during said calibration mode to switch said capacitances of said DAC, wherein said calibration signal in said calibration mode is a common mode voltage for a comparator of said one or more comparators to be calibrated, said calibration logic block comprising processing means arranged to observe said digital output signal of said block, said calibration logic block arranged to compare a probability of said observed digital output signal with a desired output being an equal distribution of positive and negative comparator output signals and to calibrate a comparator offset of said comparator of said one or more comparators, thereby reducing a difference between said digital output signal and said desired output, wherein said circuitry of said DAC is arranged to generate said calibration signal in accordance with said sampled input voltage signal and with said second control signal, whereby said input voltage signal is in said calibration mode a known signal being a common mode voltage for a first comparator to be calibrated of said one or more comparators. one or more comparators arranged to receive said calibration signal in said calibration mode and said search signal in said quantisation mode and to receive said sampled input voltage signal, a block arranged to receive a comparator output signal from said one or more comparators, to produce said digital output signal and, during said quantisation mode, to perform a successive approximation search algorithm on said comparator output signal and to adjust a first control signal which is outputted to said DAC for generating said search signal, whereby said search signal applied to said comparator is successively closer to said sampled input voltage signal, calibration logic block arranged to produce a second control signal during said calibration mode to switch said capacitances of said DAC, wherein said calibration signal in said calibration mode is a common mode voltage for a comparator of said one or more comparators to be calibrated, said calibration logic block comprising processing means arranged to observe said digital output signal of said block, said calibration logic block arranged to compare a probability of said observed digital output signal with a desired output being an equal distribution of positive and negative comparator output signals and to calibrate a comparator offset of said comparator of said one or more comparators, thereby reducing a difference between said digital output signal and said desired output,