A message-based processor system, comprising a first plurality of message based processor system cores, each comprising: - a second plurality of processor elements (Ei), having a respective second addressable storage entry with a respective processor element address EAi storing a respective processor element state, the respective processor element address EAi being associated with at least a first coordinate x along a first coordinate axis, a second coordinate y along a second coordinate axis and a third coordinate z along a third coordinate axis according to the following relationship: EAi = x+W*y+W*H*z, wherein W defines a linewidth and H defines a number of lines in a plane; - respective third pluralities of addressable storage entries specifying pattern information of a respective target pattern, the pattern information comprising for respective pattern elements of said pattern a respective magnitude value (M1, M2, M3, M4) and a respective control value ((c1, c2, c3, c4) selected from a fourth plurality of optional control values, - a processor element controller configured to receive as an input message (Min) an event message comprising a first indication of a subset of said second plurality of processor elements (Ei) as well as a second indication of a target pattern, and to update the state value of respective processor elements (Ei) in the subset in accordance with the magnitude value of respective succeeding pattern elements of said pattern, and wherein the processor element controller is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from said cyclic set dependent on whether the control value of the currently applied pattern element is a first optional control value or a second optional control value respectively, the processor element controller being configured to assume an initial address computation mode selected from said cyclic set upon receipt of the input message, wherein the processor element controller computes the processor element address (EA i+1) of a succeeding processor element by addition of an address step to the processor element address (EA i) of a processor element preceding that succeeding processor element, wherein respective address computation modes correspond to respective mutually different address steps, the cyclic set of computation modes comprising a first address computation mode wherein the address step equals +1, corresponding to a change of the first coordinate (x) in a first direction along the first coordinate axis with a step of 1, a second address computation mode wherein the address step equals +W, corresponding to a change of the second coordinate (y) in a second direction along the second coordinate axis with a step of 1, a third address computation mode wherein the address step equals -1, corresponding to a change of the first coordinate (x) in a direction opposite to the first direction along the first coordinate axis with a step of 1, a fourth address computation mode wherein the address step equals -W, corresponding to a change of the second coordinate (y) in a direction opposite to the second direction along the second coordinate axis with a step of 1. - a second plurality of processor elements (Ei), having a respective second addressable storage entry with a respective processor element address EAi storing a respective processor element state, the respective processor element address EAi being associated with at least a first coordinate x along a first coordinate axis, a second coordinate y along a second coordinate axis and a third coordinate z along a third coordinate axis according to the following relationship: EAi = x+W*y+W*H*z, wherein W defines a linewidth and H defines a number of lines in a plane; - respective third pluralities of addressable storage entries specifying pattern information of a respective target pattern, the pattern information comprising for respective pattern elements of said pattern a respective magnitude value (M1, M2, M3, M4) and a respective control value ((c1, c2, c3, c4) selected from a fourth plurality of optional control values, - a processor element controller configured to receive as an input message (Min) an event message comprising a first indication of a subset of said second plurality of processor elements (Ei) as well as a second indication of a target pattern, and to update the state value of respective processor elements (Ei) in the subset in accordance with the magnitude value of respective succeeding pattern elements of said pattern, and wherein the processor element controller is configurable in an address computation mode selected from a cyclic set of address computation modes,