A method for operating an integrated circuit chip comprising multiple tiles (202a, 202b, 202c, 202d), the method comprising: determining a configuration for the tiles of the integrated circuit for execution of a computation; when the configuration for the tiles satisfies a first criterion, operating the integrated circuit in a first mode, including: concurrently receiving respective input data for the computation at each of the tiles (202a, 202b, 202c, 202d) of the integrated circuit; and when the configuration for the tiles satisfies a second criterion, operating the integrated circuit in a second mode, including: at a first time, concurrently receiving respective first input data for the computation at each tile of a first group of tiles (202a, 202b) of the integrated circuit; at the first time, storing respective second input data for the computation in each of multiple delay registers (212a, 212b), each delay register corresponding to a tile of a second group of tiles (208c, 208d) of the integrated circuit; at a second time, releasing the second input data from the delay registers (212a, 212b) and receiving the released respective second input data at each tile (202c, 202d) of the second group of tiles. determining a configuration for the tiles of the integrated circuit for execution of a computation; when the configuration for the tiles satisfies a first criterion, operating the integrated circuit in a first mode, including: concurrently receiving respective input data for the computation at each of the tiles (202a, 202b, 202c, 202d) of the integrated circuit; and when the configuration for the tiles satisfies a second criterion, operating the integrated circuit in a second mode, including: at a first time, concurrently receiving respective first input data for the computation at each tile of a first group of tiles (202a, 202b) of the integrated circuit; at the first time, storing respective second input data for the computation in each of multiple delay registers (212a, 212b), each delay register corresponding to a tile of a second group of tiles (208c, 208d) of the integrated circuit; at a second time, releasing the second input data from the delay registers (212a, 212b) and receiving the released respective second input data at each tile (202c, 202d) of the second group of tiles. concurrently receiving respective input data for the computation at each of the tiles (202a, 202b, 202c, 202d) of the integrated circuit; and when the configuration for the tiles satisfies a second criterion, operating the integrated circuit in a second mode, including: at a first time, concurrently receiving respective first input data for the computation at each tile of a first group of tiles (202a, 202b) of the integrated circuit; at the first time, storing respective second input data for the computation in each of multiple delay registers (212a, 212b), each delay register corresponding to a tile of a second group of tiles (208c, 208d) of the integrated circuit; at a second time, releasing the second input data from the delay registers (212a, 212b) and receiving the released respective second input data at each tile (202c, 202d) of the second group of tiles.