A receiver circuit, comprising: a conversion circuit (124; 126) configured to down-convert a received radio-frequency signal to a complex baseband signal; analog-to-digital converters configured to sample the complex baseband signal into a complex sampled signal; and a digital compensation circuit configured to compensate for in-phase and quadrature-phase distortion in a frequency domain; characterized in that the digital compensation circuit comprises a first and a second branch, wherein in the first branch: the digital compensation circuit is further configured to multiply the complex sampled signal by a first correction for carrier frequency offset to generate a first multiplied signal; the digital compensation circuit further comprises a first FFT circuit configured to perform a first FFT on the first multiplied signal; and the digital compensation circuit is further configured to multiply a result from the first FFT with a first factor to form first output data; and in the second branch: the digital compensation circuit is further configured to multiply the complex sampled signal by a second correction for carrier frequency offset to generate a second multiplied signal; the digital compensation circuit further comprises a second FFT circuit configured to perform a second FFT on the second multiplied signal; the digital compensation circuit is further configured to perform cyclic inversion and conjugation over an output of the second FFT circuit; and the digital compensation circuit is further configured to multiply a result of cycling inversion and conjugation with a second factor to form second output data; and the digital compensation circuit is further configured to add the first output data and the second output data. a conversion circuit (124; 126) configured to down-convert a received radio-frequency signal to a complex baseband signal; analog-to-digital converters configured to sample the complex baseband signal into a complex sampled signal; and a digital compensation circuit configured to compensate for in-phase and quadrature-phase distortion in a frequency domain; characterized in that the digital compensation circuit comprises a first and a second branch, wherein in the first branch: the digital compensation circuit is further configured to multiply the complex sampled signal by a first correction for carrier frequency offset to generate a first multiplied signal; the digital compensation circuit further comprises a first FFT circuit configured to perform a first FFT on the first multiplied signal; and the digital compensation circuit is further configured to multiply a result from the first FFT with a first factor to form first output data; the digital compensation circuit is further configured to multiply the complex sampled signal by a first correction for carrier frequency offset to generate a first multiplied signal; the digital compensation circuit further comprises a first FFT circuit configured to perform a first FFT on the first multiplied signal; and the digital compensation circuit is further configured to multiply a result from the first FFT with a first factor to form first output data; and in the second branch: the digital compensation circuit is further configured to multiply the complex sampled signal by a second correction for carrier frequency offset to generate a second multiplied signal; the digital compensation circuit further comprises a second FFT circuit configured to perform a second FFT on the second multiplied signal; the digital compensation circuit is further configured to perform cyclic inversion and conjugation over an output of the second FFT circuit; and the digital compensation circuit is further configured to multiply a result of cycling inversion and conjugation with a second factor to form second output data; and the digital compensation circuit is further configured to multiply the complex sampled signal by a second correction for carrier frequency offset to generate a second multiplied signal; the digital compensation circuit further comprises a second FFT circuit configured to perform a second FFT on the second multiplied signal; the digital compensation circuit is further configured to perform cyclic inversion and conjugation over an output of the second FFT circuit; and the digital compensation circuit is further configured to multiply a result of cycling inversion and conjugation with a second factor to form second output data; the digital compensation circuit is further configured to add the first output data and the second output data.