A scan stage (NSTnb) for a scan driver in a display device, the display device comprising a timing controller, a scan driver, a data driver, an emission driver and a plurality of pixels arranged in a matrix of rows and columns, wherein the scan driver comprises a plurality of scan stages, each configured to supply a respective scan signal to a respective row of pixels via a respective scan output, the scan stages being arranged as a shift register, the scan stage comprising: a first scan input (GWNL(n-2)) configured to receive a first scan input from a first previous scan stage; a second scan input (GWPL(n-1)) configured to receive a second scan input from a second previous scan stage; a scan output (GWNLn), configured to output a scan signal to a pixel row; a first power input (VGLL) and a second power input (VGHL); a first clock input (NCLKL3), configured to receive a first clock signal from the timing controller; a second clock input (PCLKL1) configured to receive a second clock signal from the timing controller; a third clock input (PCLK2) configured to receive a third clock signal from the timing controller; a fourth clock input (PCLKL4) configured to receive a fourth clock signal from the timing controller; a first transistor having a first electrode connected to the scan output (GWNLn), a second electrode connected to the first power input (VGLL), and a gate electrode connected to a first node; a second transistor having a first electrode connected to the first clock input (NCLKL3), a second electrode connected to the scan output (GWNLn), and a gate electrode connected to a second node; a third transistor having a first electrode connected to the first node, a second electrode connected to the first scan input (GWNL(n-2)), and a gate electrode connected to the second clock input (PCLKL1); and a fourth transistor having a first electrode connected to the second node and a second electrode and a gate electrode, which are connected to the second scan input (GWPL(n-1)); a fifth transistor having a first electrode connected to the first clock input (NCLK3), a second electrode connected to the second node, and a gate electrode connected to the first node; a first capacitor having a first electrode connected to the first clock input (NCLK3) and a second electrode connected to the second node; a second capacitor having a first electrode connected to a third node and a second electrode connected to the first node; and a sixth transistor having a first electrode connected to the third node, a second electrode connected to the third clock input (PCLKL2), and a gate electrode connected to the first node; and a seventh transistor having a first electrode connected to the second power input (VGHL), a second electrode connected to the third node, and a gate electrode connected to the fourth clock input (PCLKL4). a first scan input (GWNL(n-2)) configured to receive a first scan input from a first previous scan stage; a second scan input (GWPL(n-1)) configured to receive a second scan input from a second previous scan stage; a scan output (GWNLn), configured to output a scan signal to a pixel row; a first power input (VGLL) and a second power input (VGHL); a first clock input (NCLKL3), configured to receive a first clock signal from the timing controller; a second clock input (PCLKL1) configured to receive a second clock signal from the timing controller; a third clock input (PCLK2) configured to receive a third clock signal from the timing controller; a fourth clock input (PCLKL4) configured to receive a fourth clock signal from the timing controller; a first transistor having a first electrode connected to the scan output (GWNLn), a second electrode connected to the first power input (VGLL), and a gate electrode connected to a first node; a second transistor having a first electrode connected to the first clock input (NCLKL3), a second electrode connected to the scan output (GWNLn), and a gate electrode connected to a second node; a third transistor having a first electrode connected to the first node, a second electrode connected to the first scan input (GWNL(n-2)), and a gate electrode connected to the second clock input (PCLKL1); and a fourth transistor having a first electrode connected to the second node and a second electrode and a gate electrode, which are connected to the second scan input (GWPL(n-1)); a fifth transistor having a first electrode connected to the first clock input (NCLK3), a second electrode connected to the second node, and a gate electrode connected to the first node; a first capacitor having a first electrode connected to the first clock input (NCLK3) and a second electrode connected to the second node; a second capacitor having a first electrode connected to a third node and a second electrode connected to the first node; and a sixth transistor having a first electrode connected to the third node, a second electrode connected to the third clock input (PCLKL2), and a gate electrode connected to the first node; and a seventh transistor having a first electrode connected to the second power input (VGHL), a second electrode connected to the third node, and a gate electrode connected to the fourth clock input (PCLKL4).