A method comprising: performing a layout of an integrated circuit, "IC", design, wherein performing the layout includes arranging a master latch of each of a plurality of flops to receive a first clock signal (L_clk) and arranging a slave latch of each of the plurality of flops to receive a second clock signal (Pclk); implementing the IC design; operating the IC in a first mode in which the master latch of each of the plurality of flops is transparent responsive to the first clock signal and wherein the slave latch of each of the plurality of flops is transparent responsive to the second clock signal; operating the IC in a second mode in which the master latch of each of the plurality of flops is held transparent, and wherein the slave latch of each of the plurality of flops is transparent responsive to the second clock signal; determining, based on said operating in the first mode and the second mode, which of the plurality of flops is to operate as a master-slave flip-flop and which flops are to operate as pulse flops for a subsequent revision of the IC arranging a selected one of the plurality of flops to operate as a master-slave flip-flop in the subsequent revision, wherein said arranging comprises revising clock connection for a selected one of the plurality of flops for the subsequent revision, wherein said revising the clock connection comprises: disconnecting a clock input of the master latch of a selected one of the plurality of flops from a first signal path coupled to convey the first clock signal; and connecting the clock input of the master latch of the selected one of the plurality of flops to a second signal path coupled to convey the second clock signal. performing a layout of an integrated circuit, "IC", design, wherein performing the layout includes arranging a master latch of each of a plurality of flops to receive a first clock signal (L_clk) and arranging a slave latch of each of the plurality of flops to receive a second clock signal (Pclk); implementing the IC design; operating the IC in a first mode in which the master latch of each of the plurality of flops is transparent responsive to the first clock signal and wherein the slave latch of each of the plurality of flops is transparent responsive to the second clock signal; operating the IC in a second mode in which the master latch of each of the plurality of flops is held transparent, and wherein the slave latch of each of the plurality of flops is transparent responsive to the second clock signal; determining, based on said operating in the first mode and the second mode, which of the plurality of flops is to operate as a master-slave flip-flop and which flops are to operate as pulse flops for a subsequent revision of the IC arranging a selected one of the plurality of flops to operate as a master-slave flip-flop in the subsequent revision, wherein said arranging comprises revising clock connection for a selected one of the plurality of flops for the subsequent revision, wherein said revising the clock connection comprises: disconnecting a clock input of the master latch of a selected one of the plurality of flops from a first signal path coupled to convey the first clock signal; and connecting the clock input of the master latch of the selected one of the plurality of flops to a second signal path coupled to convey the second clock signal. disconnecting a clock input of the master latch of a selected one of the plurality of flops from a first signal path coupled to convey the first clock signal; and connecting the clock input of the master latch of the selected one of the plurality of flops to a second signal path coupled to convey the second clock signal.