A semiconductor device comprising: a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall; a gate insulating film formed on the sidewall and the bottom wall of the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, wherein the semiconductor layer includes: a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench; a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench; a first conductivity type drift region (13, 72, 82) formed on a side of the body region closer to the rear surface of the semi-conductor layer to be in contact with the body region for forming the bottom wall of the gate trench; the gate trench is formed in a latticed manner, the semiconductor layer includes a plurality of unit cells partitioned by the latticed gate trench and provided in the form of polygonal prisms each having a plurality of corner portions, and each unit cell has the source region, the body region and the drift region, a first breakdown voltage holding region, portion of a second conductivity type breakdown voltage holding region, is selectively formed on a corner edge portion of the gate trench formed on the corner portion of the unit cell and on edge portions of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench, and the first breakdown voltage holding region is formed to reach a portion of the body region immediately above the corner edge portion. a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall; a gate insulating film formed on the sidewall and the bottom wall of the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, wherein the semiconductor layer includes: a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench; a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench; a first conductivity type drift region (13, 72, 82) formed on a side of the body region closer to the rear surface of the semi-conductor layer to be in contact with the body region for forming the bottom wall of the gate trench; the gate trench is formed in a latticed manner, the semiconductor layer includes a plurality of unit cells partitioned by the latticed gate trench and provided in the form of polygonal prisms each having a plurality of corner portions, and each unit cell has the source region, the body region and the drift region, a first breakdown voltage holding region, portion of a second conductivity type breakdown voltage holding region, is selectively formed on a corner edge portion of the gate trench formed on the corner portion of the unit cell and on edge portions of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench, and the first breakdown voltage holding region is formed to reach a portion of the body region immediately above the corner edge portion. a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench; a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench; a first conductivity type drift region (13, 72, 82) formed on a side of the body region closer to the rear surface of the semi-conductor layer to be in contact with the body region for forming the bottom wall of the gate trench; the gate trench is formed in a latticed manner, the semiconductor layer includes a plurality of unit cells partitioned by the latticed gate trench and provided in the form of polygonal prisms each having a plurality of corner portions, and each unit cell has the source region, the body region and the drift region, a first breakdown voltage holding region, portion of a second conductivity type breakdown voltage holding region, is selectively formed on a corner edge portion of the gate trench formed on the corner portion of the unit cell and on edge portions of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench, and the first breakdown voltage holding region is formed to reach a portion of the body region immediately above the corner edge portion.