A source-synchronous data communications link comprising: a data transmission circuit adapted to generate a first data signal (DATA) and a clock signal; a data reception device comprising: a first data input for receiving the first data signal (DATA) and a clock input for receiving the clock signal; and a stability detection circuit adapted to generate: a first error signal (ERROR_EARLY) indicating when a data transition of the first data signal occurs during a first period, the first period being at least partially before a first significant clock edge of the clock signal; and a second error signal (ERROR_LATE) indicating when a data transition of the first data signal occurs during a second period, the second period being at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal (CTRL) for controlling the duration of a time delay applied to the data signal or to the clock signal by the data transmission circuit or data reception device, wherein the time delay is controlled in order to make a sampling time of the first data signal by the clock signal later if the first error signal is asserted and to make the sampling time earlier if the second error signal is asserted. a data transmission circuit adapted to generate a first data signal (DATA) and a clock signal; a data reception device comprising: a first data input for receiving the first data signal (DATA) and a clock input for receiving the clock signal; and a stability detection circuit adapted to generate: a first error signal (ERROR_EARLY) indicating when a data transition of the first data signal occurs during a first period, the first period being at least partially before a first significant clock edge of the clock signal; and a second error signal (ERROR_LATE) indicating when a data transition of the first data signal occurs during a second period, the second period being at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal (CTRL) for controlling the duration of a time delay applied to the data signal or to the clock signal by the data transmission circuit or data reception device, wherein the time delay is controlled in order to make a sampling time of the first data signal by the clock signal later if the first error signal is asserted and to make the sampling time earlier if the second error signal is asserted. a first data input for receiving the first data signal (DATA) and a clock input for receiving the clock signal; and a stability detection circuit adapted to generate: a first error signal (ERROR_EARLY) indicating when a data transition of the first data signal occurs during a first period, the first period being at least partially before a first significant clock edge of the clock signal; and a second error signal (ERROR_LATE) indicating when a data transition of the first data signal occurs during a second period, the second period being at least partially after the first significant clock edge of the clock signal; and a first error signal (ERROR_EARLY) indicating when a data transition of the first data signal occurs during a first period, the first period being at least partially before a first significant clock edge of the clock signal; and a second error signal (ERROR_LATE) indicating when a data transition of the first data signal occurs during a second period, the second period being at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal (CTRL) for controlling the duration of a time delay applied to the data signal or to the clock signal by the data transmission circuit or data reception device, wherein the time delay is controlled in order to make a sampling time of the first data signal by the clock signal later if the first error signal is asserted and to make the sampling time earlier if the second error signal is asserted.