A Schottky barrier diode comprising: a substrate made of silicon carbide, the substrate having a center region (Ac) and a periphery region (Ae) surrounding the center region (Ac) in plan view; a first semiconductor layer included in the substrate, the first semiconductor layer being adjacent to a first surface of the substrate, and the first semiconductor layer being an n-type semiconductor layer; a guard ring layer in the first semiconductor layer, the guard ring layer being in the periphery region (Ae) in plan view and the guard ring layer being a p-type semiconductor layer; a plurality of p-type second semiconductor layers in the first semiconductor layer, the plurality of second semiconductor layers being in the center region (Ac) of the substrate, the plurality of second semiconductor layers including a first layer, a second layer, and remaining layers, the first layer being between the guard ring layer and the second layer, the second layer surrounding the remaining layers in plan view, the first layer surrounding the second layer in plan view, the guard ring layer surrounding the first layer in plan view, the first layer being closest to the guard ring layer among the plurality of second semiconductor layers, the second layer being closest to the first layer among the plurality of second semiconductor layers, and the remaining layers being arranged at a first interval in the center region (Ac) of the substrate; a first insulating layer directly on the first surface of the substrate, covering a periphery portion of the guard ring layer; a second insulating layer directly on the first surface of the substrate, the second insulating layer covering the first surface of the substrate between the guard ring layer and the first layer; a third insulating layer directly on the first surface of the substrate, the third insulating layer covering the first surface of the substrate between the first and second layers (161, 162), the first insulating layer surrounding the second insulating layer in a plan view and the second insulating layer surrounding the third insulating layer in a plan view; and a metal layer over the center region (Ac) and the periphery region (Ae), the metal layer forming a Schottky junction with the first semiconductor layer and forming an ohmic contact with the second semiconductor layer, and the guard ring layer; the metal layer contacting the guard ring layer in the periphery region (Ae) between the first insulating layer and the second insulating layer, the metal layer contacting the first layer between the second insulating layer and the third insulating layer, the metal layer contacting the second layer and the remaining layers; the metal layer covering the second and the third insulating layers (22, 23) and partially overlapping the first insulating layer. a substrate made of silicon carbide, the substrate having a center region (Ac) and a periphery region (Ae) surrounding the center region (Ac) in plan view; a first semiconductor layer included in the substrate, the first semiconductor layer being adjacent to a first surface of the substrate, and the first semiconductor layer being an n-type semiconductor layer; a guard ring layer in the first semiconductor layer, the guard ring layer being in the periphery region (Ae) in plan view and the guard ring layer being a p-type semiconductor layer; a plurality of p-type second semiconductor layers in the first semiconductor layer, the plurality of second semiconductor layers being in the center region (Ac) of the substrate, the plurality of second semiconductor layers including a first layer, a second layer, and remaining layers, the first layer being between the guard ring layer and the second layer, the second layer surrounding the remaining layers in plan view, the first layer surrounding the second layer in plan view, the guard ring layer surrounding the first layer in plan view, the first layer being closest to the guard ring layer among the plurality of second semiconductor layers, the second layer being closest to the first layer among the plurality of second semiconductor layers, and the remaining layers being arranged at a first interval in the center region (Ac) of the substrate; a first insulating layer directly on the first surface of the substrate, covering a periphery portion of the guard ring layer; a second insulating layer directly on the first surface of the substrate, the second insulating layer covering the first surface of the substrate between the guard ring layer and the first layer; a third insulating layer directly on the first surface of the substrate, the third insulating layer covering the first surface of the substrate between the first and second layers (161, 162), the first insulating layer surrounding the second insulating layer in a plan view and the second insulating layer surrounding the third insulating layer in a plan view; and a metal layer over the center region (Ac) and the periphery region (Ae), the metal layer forming a Schottky junction with the first semiconductor layer and forming an ohmic contact with the second semiconductor layer, and the guard ring layer;