An apparatus, comprising: a set of memory cells arranged in a NAND string (700n, 710n, 720n, 730n) and connected to a plurality of word lines (WL0-WL9), the NAND string (700n, 710n, 720n, 730n) extends vertically in a stack comprising alternating conductive and dielectric layers; and a control circuit (110, 122), the control circuit (110, 122) is configured to program a selected memory cell of the set of memory cells in a pre-final program pass, subsequently program a source side memory cell adjacent to the selected memory cell in a final program pass, and subsequently program the selected memory cell in a final program pass; in the pre-final program pass of the selected memory cell, the control circuit (110, 122) is configured to apply a first pass voltage (Vpass _high) to the source side memory cell while applying a program voltage to the selected memory cell; in the final program pass of the selected memory cell, the control circuit (110, 122) is configured to apply a second pass voltage (Vpass_low) to the source side memory cell while applying a program voltage to the selected memory cell; and the second pass voltage is lower than the first pass voltage when the selected memory cell is in a bottom portion of the stack; wherein: in the pre-final program pass of the selected memory cell, the control circuit (110, 122) is configured to apply a third pass voltage to a drain side memory cell adjacent to the selected memory cell while applying the program voltage to the selected memory cell; in the final program pass of the selected memory cell, the control circuit is configured to apply a fourth pass voltage to the drain side memory cell while applying the program voltage to the selected memory cell; and the fourth pass voltage is higher than the third pass voltage when the selected memory cell is in the bottom portion of the stack. a set of memory cells arranged in a NAND string (700n, 710n, 720n, 730n) and connected to a plurality of word lines (WL0-WL9), the NAND string (700n, 710n, 720n, 730n) extends vertically in a stack comprising alternating conductive and dielectric layers; and a control circuit (110, 122), the control circuit (110, 122) is configured to program a selected memory cell of the set of memory cells in a pre-final program pass, subsequently program a source side memory cell adjacent to the selected memory cell in a final program pass, and subsequently program the selected memory cell in a final program pass; in the pre-final program pass of the selected memory cell, the control circuit (110, 122) is configured to apply a first pass voltage (Vpass _high) to the source side memory cell while applying a program voltage to the selected memory cell; in the final program pass of the selected memory cell, the control circuit (110, 122) is configured to apply a second pass voltage (Vpass_low) to the source side memory cell while applying a program voltage to the selected memory cell; and the second pass voltage is lower than the first pass voltage when the selected memory cell is in a bottom portion of the stack; wherein: in the pre-final program pass of the selected memory cell, the control circuit (110, 122) is configured to apply a third pass voltage to a drain side memory cell adjacent to the selected memory cell while applying the program voltage to the selected memory cell; in the final program pass of the selected memory cell, the control circuit is configured to apply a fourth pass voltage to the drain side memory cell while applying the program voltage to the selected memory cell; and the fourth pass voltage is higher than the third pass voltage when the selected memory cell is in the bottom portion of the stack. in the pre-final program pass of the selected memory cell, the control circuit (110, 122) is configured to apply a third pass voltage to a drain side memory cell adjacent to the selected memory cell while applying the program voltage to the selected memory cell; in the final program pass of the selected memory cell, the control circuit is configured to apply a fourth pass voltage to the drain side memory cell while applying the program voltage to the selected memory cell; and the fourth pass voltage is higher than the third pass voltage when the selected memory cell is in the bottom portion of the stack.