A method of converting a digital signal to an analog signal, the method comprising: forming a first plurality of parallel stages associated with most significant bits of the digital data; generating a current of a specific size in each of the first plurality of parallel stages; delivering the current of said specified size generated in each of the first plurality of parallel stages to a pair of current summing nodes (B, B') via a pair of transistor switches (140, 145) responsive to differential data; forming a second plurality of stages associated with least significant bits of the digital data; generating a current of said specified size in each of the second plurality of stages; forming a first plurality of resistive networks each associated with a different one of the second plurality of stages; delivering to each of the first plurality of resistive networks the current of said specified size generated in its associated stage via a pair of transistor switches (140, 145) responsive to differential data; scaling the current received by each of the first plurality of resistive network in accordance with a binary weight of the resistive network's associated stage, delivering the scaled currents to the pair of current summing nodes (B, B'); maintaining an impedance of each of the current summing nodes within a range defined by a gain value; and maintaining a voltage difference between the current summing nodes within a range defined by the gain value, the difference in the currents delivered to the current summing nodes defining a value of the analog signal; the method further comprising: coupling a first resistive element between a first one of the transistor switches of at least one of the first plurality of stages and a first one of the current summing nodes; and coupling a second resistive element between a second one of the transistor switches of the at least one of the first plurality stages and a second (B') one of the current summing nodes; and coupling a third resistive element of the first plurality of resistive networks between a first one of the transistor switches of at least one of the second plurality of stages and the first one of the current summing nodes; and coupling a fourth resistive element of the first plurality of resistive networks between a second one of the transistor switches of the at least one of the second plurality of stages and the second (B') one of the current summing nodes; wherein each of the first resistor, the second resistor, the third resistor and the fourth resistor has the same resistance value. forming a first plurality of parallel stages associated with most significant bits of the digital data; generating a current of a specific size in each of the first plurality of parallel stages; delivering the current of said specified size generated in each of the first plurality of parallel stages to a pair of current summing nodes (B, B') via a pair of transistor switches (140, 145) responsive to differential data; forming a second plurality of stages associated with least significant bits of the digital data; generating a current of said specified size in each of the second plurality of stages; forming a first plurality of resistive networks each associated with a different one of the second plurality of stages; delivering to each of the first plurality of resistive networks the current of said specified size generated in its associated stage via a pair of transistor switches (140, 145) responsive to differential data; scaling the current received by each of the first plurality of resistive network in accordance with a binary weight of the resistive network's associated stage, delivering the scaled currents to the pair of current summing nodes (B, B'); maintaining an impedance of each of the current summing nodes within a range defined by a gain value; and maintaining a voltage difference between the current summing nodes within a range defined by the gain value, the difference in the currents delivered to the current summing nodes defining a value of the analog signal; the method further comprising: coupling a first resistive element between a first one of the transistor switches of at least one of the first plurality of stages and a first one of the current summing nodes; and coupling a second resistive element between a second one of the transistor switches of the at least one of the first plurality stages and a second (B') one of the current summing nodes; and coupling a first resistive element between a first one of the transistor switches of at least one of the first plurality of stages and a first one of the current summing nodes; and coupling a second resistive element between a second one of the transistor switches of the at least one of the first plurality stages and a second (B') one of the current summing nodes; and coupling a third resistive element of the first plurality of resistive networks between a first one of the transistor switches of at least one of the second plurality of stages and the first one of the current summing nodes; and coupling a fourth resistive element of the first plurality of resistive networks between a second one of the transistor switches of the at least one of the second plurality of stages and the second (B') one of the current summing nodes; wherein each of the first resistor, the second resistor, the third resistor and the fourth resistor has the same resistance value.