Physically Unclonable Function circuitry (200, 270) comprising: precharge circuitry for precharging a differential output (N+, N-) of the circuitry having first and second output nodes (N+, N-), wherein the precharge circuitry comprises a first transistor (202, 272) of a first transistor type coupled to the first output node (N+) and a second transistor (202, 272) of said first transistor type coupled to the second output node (N-) of the differential output; wherein the circuitry further comprises: third and fourth transistors (204, 206; 274, 276) of a second transistor type that is different from the first transistor type, wherein the circuitry is adapted to produce a differential output signal at said differential output (N+, N-) of the circuitry; wherein the third transistor (204, 274) has a gate connected to the to the second output node (N-) of the differential output and a drain of the fourth transistor (206, 276); wherein the fourth transistor (206, 274) has a gate connected to the to the first output node (N+) of the differential output and a drain of the third transistor (204, 274); wherein the sources of the third and fourth transistors (204, 206; 274, 276) are connected to a common sink node; characterized in that the differential output signal measures variations between the third and fourth transistors (204, 206; 274, 276) based only on relative current drawn by the third and fourth transistors (204, 206; 274, 276). precharge circuitry for precharging a differential output (N+, N-) of the circuitry having first and second output nodes (N+, N-), wherein the precharge circuitry comprises a first transistor (202, 272) of a first transistor type coupled to the first output node (N+) and a second transistor (202, 272) of said first transistor type coupled to the second output node (N-) of the differential output; wherein the circuitry further comprises: third and fourth transistors (204, 206; 274, 276) of a second transistor type that is different from the first transistor type, wherein the circuitry is adapted to produce a differential output signal at said differential output (N+, N-) of the circuitry; wherein the third transistor (204, 274) has a gate connected to the to the second output node (N-) of the differential output and a drain of the fourth transistor (206, 276); wherein the fourth transistor (206, 274) has a gate connected to the to the first output node (N+) of the differential output and a drain of the third transistor (204, 274); wherein the sources of the third and fourth transistors (204, 206; 274, 276) are connected to a common sink node; characterized in that the differential output signal measures variations between the third and fourth transistors (204, 206; 274, 276) based only on relative current drawn by the third and fourth transistors (204, 206; 274, 276). third and fourth transistors (204, 206; 274, 276) of a second transistor type that is different from the first transistor type, wherein the circuitry is adapted to produce a differential output signal at said differential output (N+, N-) of the circuitry; wherein the third transistor (204, 274) has a gate connected to the to the second output node (N-) of the differential output and a drain of the fourth transistor (206, 276); wherein the fourth transistor (206, 274) has a gate connected to the to the first output node (N+) of the differential output and a drain of the third transistor (204, 274); wherein the sources of the third and fourth transistors (204, 206; 274, 276) are connected to a common sink node; characterized in that the differential output signal measures variations between the third and fourth transistors (204, 206; 274, 276) based only on relative current drawn by the third and fourth transistors (204, 206; 274, 276).