A switching branch for a three-level rectifier, the switching branch comprising: a first diode (D1; D11, D12, D13) and a second diode (D2; D21, D22, D23) connected in series between an AC input pole (AC; AC1, AC2, AC3) of the switching branch and a positive DC output pole (Udc+); a third diode (D3; D31, D32, D33) and a fourth diode (D4; D41, D42, D43) connected in series between the AC input pole (AC; AC1, AC2, AC3) of the switching branch and a negative DC output pole (Udc-); a first controllable switch (S1; S11, S12, S13) connected between a neutral DC output pole and a connection point between the first and the second diode; and a second controllable switch (S2; S21, S22, S23) connected between the neutral DC output pole and a connection point between the third and the fourth diode, characterized in that the switching branch comprises a control arrangement configured to: control the first controllable switch (S1; S11, S12, S13) to be in a conductive state during a reverse blocking state of the first diode (D1; D11, D12, D13) and the second diode (D2; D21, D22, D23), wherein the control arrangement is configured to control the first switch to be in the conductive state for each entire period of the reverse blocking state of the first diode (D1; D11, D12, D13) and the second diode (D2; D21, D22, D23); and control the second controllable switch (S2; S21, S22, S23) to be in a conductive state during a reverse blocking state of the third diode (D3; D31, D32, D33) and the fourth diode (D4; D41, D42, D43), wherein the control arrangement is configured to control the second switch to be in the conductive state for each entire period of the reverse blocking state of the third diode (D3; D31, D32, D33) and the fourth diode (D4; D41, D42, D43). a first diode (D1; D11, D12, D13) and a second diode (D2; D21, D22, D23) connected in series between an AC input pole (AC; AC1, AC2, AC3) of the switching branch and a positive DC output pole (Udc+); a third diode (D3; D31, D32, D33) and a fourth diode (D4; D41, D42, D43) connected in series between the AC input pole (AC; AC1, AC2, AC3) of the switching branch and a negative DC output pole (Udc-); a first controllable switch (S1; S11, S12, S13) connected between a neutral DC output pole and a connection point between the first and the second diode; and a second controllable switch (S2; S21, S22, S23) connected between the neutral DC output pole and a connection point between the third and the fourth diode, characterized in that the switching branch comprises a control arrangement configured to: control the first controllable switch (S1; S11, S12, S13) to be in a conductive state during a reverse blocking state of the first diode (D1; D11, D12, D13) and the second diode (D2; D21, D22, D23), wherein the control arrangement is configured to control the first switch to be in the conductive state for each entire period of the reverse blocking state of the first diode (D1; D11, D12, D13) and the second diode (D2; D21, D22, D23); and control the second controllable switch (S2; S21, S22, S23) to be in a conductive state during a reverse blocking state of the third diode (D3; D31, D32, D33) and the fourth diode (D4; D41, D42, D43), wherein the control arrangement is configured to control the second switch to be in the conductive state for each entire period of the reverse blocking state of the third diode (D3; D31, D32, D33) and the fourth diode (D4; D41, D42, D43). control the first controllable switch (S1; S11, S12, S13) to be in a conductive state during a reverse blocking state of the first diode (D1; D11, D12, D13) and the second diode (D2; D21, D22, D23), wherein the control arrangement is configured to control the first switch to be in the conductive state for each entire period of the reverse blocking state of the first diode (D1; D11, D12, D13) and the second diode (D2; D21, D22, D23); and control the second controllable switch (S2; S21, S22, S23) to be in a conductive state during a reverse blocking state of the third diode (D3; D31, D32, D33) and the fourth diode (D4; D41, D42, D43), wherein the control arrangement is configured to control the second switch to be in the conductive state for each entire period of the reverse blocking state of the third diode (D3; D31, D32, D33) and the fourth diode (D4; D41, D42, D43).