A bidirectional inverter circuit arrangement, comprising: a first terminal, a second terminal (C/Q), a terminal for a first supply potential (V supply) and a terminal for a second supply potential (V gnd); a pull-up resistor (R 3) connected to the first terminal and to a terminal for the first supply potential (V supply); an AB class transistor circuit (Q nc2, Q pc2) connected to the second terminal (C/Q); a first current mirror (Q po1, Q po2) having an input path connected to the terminal for the first supply potential (V supply) and to one end of the AB class transistor circuit (Q nc2, Q pc2) and having an output path connected to the first terminal; a second current mirror (Q no1, Q no2) having an input path connected to the terminal for the second supply potential (V gnd) and to another end of the AB class transistor circuit (Q nc2, Q pc2) and having an output path connected to the first terminal; a bias circuit (R b1, Q b1,..., Q nc1, Q pc1) comprising a bias current source (R b1, Q b1) to provide a bias current (I b), a current mirror (Q pc1, Q pc2) configured to receive the bias current (I b) and having an output path that includes a transistor (Q pc2) of the AB class transistor circuit and having an input path that includes a diode (D 2) connected to the terminal for the first supply potential (V supply) and a transistor (Q pc1) configured as a diode connected to the control terminal of the transistor (Q pc2) of the AB class transistor circuit; another current mirror (Q nc1, Q nc2) configured to receive the bias current (I b) and having an output path that includes another transistor (Q nc2) of the AB class transistor circuit and having an input path that includes a diode (D 1) connected to the terminal for the second supply potential (V gnd) and a transistor (Q nc1) configured as a diode connected to the control terminal of the other transistor (Q nc2) of the AB class transistor circuit; and a comparator connected to the first terminal having an output connected to the second terminal (C/Q) through a third current mirror (Q d2, Q d1). a first terminal, a second terminal (C/Q), a terminal for a first supply potential (V supply) and a terminal for a second supply potential (V gnd); a pull-up resistor (R 3) connected to the first terminal and to a terminal for the first supply potential (V supply); an AB class transistor circuit (Q nc2, Q pc2) connected to the second terminal (C/Q); a first current mirror (Q po1, Q po2) having an input path connected to the terminal for the first supply potential (V supply) and to one end of the AB class transistor circuit (Q nc2, Q pc2) and having an output path connected to the first terminal; a second current mirror (Q no1, Q no2) having an input path connected to the terminal for the second supply potential (V gnd) and to another end of the AB class transistor circuit (Q nc2, Q pc2) and having an output path connected to the first terminal; a bias circuit (R b1, Q b1,..., Q nc1, Q pc1) comprising a bias current source (R b1, Q b1) to provide a bias current (I b), a current mirror (Q pc1, Q pc2) configured to receive the bias current (I b) and having an output path that includes a transistor (Q pc2) of the AB class transistor circuit and having an input path that includes a diode (D 2) connected to the terminal for the first supply potential (V supply) and a transistor (Q pc1) configured as a diode connected to the control terminal of the transistor (Q pc2) of the AB class transistor circuit; another current mirror (Q nc1, Q nc2) configured to receive the bias current (I b) and having an output path that includes another transistor (Q nc2) of the AB class transistor circuit and having an input path that includes a diode (D 1) connected to the terminal for the second supply potential (V gnd) and a transistor (Q nc1) configured as a diode connected to the control terminal of the other transistor (Q nc2) of the AB class transistor circuit; and a comparator connected to the first terminal having an output connected to the second terminal (C/Q) through a third current mirror (Q d2, Q d1).