A non-volatile memory device, comprising an array of multi-state memory cells addressable by a plurality of word lines and bit lines, a bank of read/write circuits arranged to operate on a group of memory cells in parallel via an associated group of bit lines, the memory cells of the group of memory cells connected by a word line of the plurality of word lines, with each read/write circuit being partitioned into a core portion and a common portion; CHARACTERISED BY: the bank of read/write circuits being organized into multiple subgroups thereof, with each subgroup forming a stack of read/write circuits comprising multiple core portions from individual read/write circuits of the subgroup, each of the multiple core portions coupleable to a bit line of the bit lines for simultaneous read or programming access by the multiple core portions in a stack; wherein each core portion has a width extending in a direction orthogonal to a direction in which the bit lines extend and comprises a sense amplifier arranged to sense a conduction current level of an addressed memory cell, wherein a number of core portions in each subgroup is the same as a number of bit lines the multiple core portions are arranged to couple to for simultaneous read or programming access and over which the width of each of the core portions extends; wherein each stack further comprises a common portion including a processor coupled to each of the multiple core portions of the subgroup and arranged to process data associated with the multiple core portions of the subgroup, and wherein the core portions and the common portion are stacked in the direction in which the bit lines extend; and wherein the processor in each common portion is coupled to receive the conduction current level sensed from the sense amplifiers of the respective stack and arranged to compute a set of data bits from the conduction current level sensed; each subgroup including a bus interconnecting each core portion of the subgroup and the common portion among the stack, enabling serial communication between the each core portion and the common portion. the bank of read/write circuits being organized into multiple subgroups thereof, with each subgroup forming a stack of read/write circuits comprising multiple core portions from individual read/write circuits of the subgroup, each of the multiple core portions coupleable to a bit line of the bit lines for simultaneous read or programming access by the multiple core portions in a stack; wherein each core portion has a width extending in a direction orthogonal to a direction in which the bit lines extend and comprises a sense amplifier arranged to sense a conduction current level of an addressed memory cell, wherein a number of core portions in each subgroup is the same as a number of bit lines the multiple core portions are arranged to couple to for simultaneous read or programming access and over which the width of each of the core portions extends; wherein each stack further comprises a common portion including a processor coupled to each of the multiple core portions of the subgroup and arranged to process data associated with the multiple core portions of the subgroup, and wherein the core portions and the common portion are stacked in the direction in which the bit lines extend; and wherein the processor in each common portion is coupled to receive the conduction current level sensed from the sense amplifiers of the respective stack and arranged to compute a set of data bits from the conduction current level sensed; each subgroup including a bus interconnecting each core portion of the subgroup and the common portion among the stack, enabling serial communication between the each core portion and the common portion.