An integrated circuit, comprising: an input/output (I/O) pad; a first supply node; and a transient event detector (202, 204), having: a latch (308/306 or 408/410); and a first transistor (304 or 402) having a first current electrode coupled to the I/O pad, a control electrode coupled to the first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store, in response to a transient event on the I/O pad, an indication that the transient event occurred, characterised in that the integrated circuit further comprises an event level sensor (602 or 604), having: a protection device (302 or 400) having a first terminal coupled to the I/O pad and a second terminal coupled to a first supply node; a first transistor (702 or 804) having a first current electrode coupled to the I/O pad, a control electrode coupled to the second terminal of the protection device, and a second current electrode coupled to a load circuit (704, 705 or 810, 802); a rectifier device (706 or 822) having a first terminal coupled to the second current electrode of the first transistor; a capacitor (708 or 814) coupled to a second terminal of the rectifier device; a second transistor (712 or 816) having a control electrode coupled to the capacitor; and an output circuit (714/716 or 818/820) coupled between a first current electrode of the second transistor and a first sense bus and configured to place a current on the first sense bus proportional to a current through the load circuit. an input/output (I/O) pad; a first supply node; and a transient event detector (202, 204), having: a latch (308/306 or 408/410); and a first transistor (304 or 402) having a first current electrode coupled to the I/O pad, a control electrode coupled to the first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store, in response to a transient event on the I/O pad, an indication that the transient event occurred, characterised in that the integrated circuit further comprises an event level sensor (602 or 604), having: a protection device (302 or 400) having a first terminal coupled to the I/O pad and a second terminal coupled to a first supply node; a first transistor (702 or 804) having a first current electrode coupled to the I/O pad, a control electrode coupled to the second terminal of the protection device, and a second current electrode coupled to a load circuit (704, 705 or 810, 802); a rectifier device (706 or 822) having a first terminal coupled to the second current electrode of the first transistor; a capacitor (708 or 814) coupled to a second terminal of the rectifier device; a second transistor (712 or 816) having a control electrode coupled to the capacitor; and an output circuit (714/716 or 818/820) coupled between a first current electrode of the second transistor and a first sense bus and configured to place a current on the first sense bus proportional to a current through the load circuit. a latch (308/306 or 408/410); and a first transistor (304 or 402) having a first current electrode coupled to the I/O pad, a control electrode coupled to the first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store, in response to a transient event on the I/O pad, an indication that the transient event occurred, characterised in that the integrated circuit further comprises an event level sensor (602 or 604), having: a protection device (302 or 400) having a first terminal coupled to the I/O pad and a second terminal coupled to a first supply node; a first transistor (702 or 804) having a first current electrode coupled to the I/O pad, a control electrode coupled to the second terminal of the protection device, and a second current electrode coupled to a load circuit (704, 705 or 810, 802); a rectifier device (706 or 822) having a first terminal coupled to the second current electrode of the first transistor; a capacitor (708 or 814) coupled to a second terminal of the rectifier device; a second transistor (712 or 816) having a control electrode coupled to the capacitor; and an output circuit (714/716 or 818/820) coupled between a first current electrode of the second transistor and a first sense bus and configured to place a current on the first sense bus proportional to a current through the load circuit. a protection device (302 or 400) having a first terminal coupled to the I/O pad and a second terminal coupled to a first supply node; a first transistor (702 or 804) having a first current electrode coupled to the I/O pad, a control electrode coupled to the second terminal of the protection device, and a second current electrode coupled to a load circuit (704, 705 or 810, 802); a rectifier device (706 or 822) having a first terminal coupled to the second current electrode of the first transistor; a capacitor (708 or 814) coupled to a second terminal of the rectifier device; a second transistor (712 or 816) having a control electrode coupled to the capacitor; and an output circuit (714/716 or 818/820) coupled between a first current electrode of the second transistor and a first sense bus and configured to place a current on the first sense bus proportional to a current through the load circuit.