A three dimensional nonvolatile memory device comprising a plurality of memory cells aligned in rows and columns, comprising: a plurality of first conductors, each of the first conductors extending in a first column direction, each first conductor operably coupling the memory cells in a column of memory cells; and a plurality of second conductors, each of the second conductors extending in a second row direction, the second conductors operably coupling the memory cells in a row of memory cells, wherein each of the plurality of memory cells is located at an intersection of a first conductor and a second conductor, wherein each memory cell comprises: a semiconductor element above the first conductor, the semiconductor element comprising a source, a drain and a channel of a junction field effect transistor JFET; and a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element, wherein said nonvolatile memory device is characterised in that: the JFETs in a plurality of columns and a plurality of rows share a single common gate arranged in direct physical contact with the channels of said JFETs in said plurality of columns and said plurality of rows; the JFET is adapted to be turned on by the application of a gate voltage and a source-drain voltage; the resistivity state of the resistivity switching material switches from a lower resistivity state to a higher resistivity state upon the application of a gate voltage and a forward drain to source bias voltage of a first polarity above a first predetermined threshold voltage to the JFET; and in that the resistivity state of the resistivity switching material switches from a higher resistivity state to a lower resistivity state upon the application of a gate voltage and a reverse drain to source bias voltage of a second polarity opposite to the first polarity above a second predetermined threshold voltage to the JFET. a plurality of first conductors, each of the first conductors extending in a first column direction, each first conductor operably coupling the memory cells in a column of memory cells; and a plurality of second conductors, each of the second conductors extending in a second row direction, the second conductors operably coupling the memory cells in a row of memory cells, wherein each of the plurality of memory cells is located at an intersection of a first conductor and a second conductor, wherein each memory cell comprises: a semiconductor element above the first conductor, the semiconductor element comprising a source, a drain and a channel of a junction field effect transistor JFET; and a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element, a semiconductor element above the first conductor, the semiconductor element comprising a source, a drain and a channel of a junction field effect transistor JFET; and a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element, wherein said nonvolatile memory device is characterised in that: the JFETs in a plurality of columns and a plurality of rows share a single common gate arranged in direct physical contact with the channels of said JFETs in said plurality of columns and said plurality of rows; the JFET is adapted to be turned on by the application of a gate voltage and a source-drain voltage; the resistivity state of the resistivity switching material switches from a lower resistivity state to a higher resistivity state upon the application of a gate voltage and a forward drain to source bias voltage of a first polarity above a first predetermined threshold voltage to the JFET; and in that the resistivity state of the resistivity switching material switches from a higher resistivity state to a lower resistivity state upon the application of a gate voltage and a reverse drain to source bias voltage of a second polarity opposite to the first polarity above a second predetermined threshold voltage to the JFET. the JFETs in a plurality of columns and a plurality of rows share a single common gate arranged in direct physical contact with the channels of said JFETs in said plurality of columns and said plurality of rows; the JFET is adapted to be turned on by the application of a gate voltage and a source-drain voltage; the resistivity state of the resistivity switching material switches from a lower resistivity state to a higher resistivity state upon the application of a gate voltage and a forward drain to source bias voltage of a first polarity above a first predetermined threshold voltage to the JFET; and in that the resistivity state of the resistivity switching material switches from a higher resistivity state to a lower resistivity state upon the application of a gate voltage and a reverse drain to source bias voltage of a second polarity opposite to the first polarity above a second predetermined threshold voltage to the JFET.