An apparatus, comprising: a NAND string (700n-703n, 710n-713n, 720n-723n, 730n-733n) comprising a channel (665, 710a), a drain-end select gate transistor (717, 737, 757, 777) at a drain-end of the NAND string, a selected data memory cell (704-714, 724-734, 744-754, 764-774) and a dummy memory cell (716, 736, 756, 776) adjacent to the drain-end select gate transistor; a bit line (BL0-BL3) connected to the drain-end; a selected word line (WLLO-WLL10) connected to the selected data memory cell; a dummy word line (WLDD0) connected to the dummy memory cell; a select gate line (SGD1) connected to the drain-end select gate transistor; and a control circuit (110, 122) configured to: in a pre-charge phase of a program loop (PLO-PL15), provide a first voltage (Vbl) on the bit line while a voltage (Vsgd_sel) on the select gate line is a first select gate line voltage and a voltage (VddO) on the dummy word line is a first dummy word line voltage; in a program phase of the program loop, provide a program voltage (Vpgm) on the selected word line and a second voltage on the bit line while the voltage on the select gate line is at a second select gate line voltage, lower than the first select gate line voltage, and the voltage on the dummy word line is at a second dummy word line voltage, higher than the first dummy word line voltage, wherein the second dummy word line voltage exceeds the second select gate line voltage by a first difference; and characterized in that the control circuit is configured to: in a transition from the pre-charge phase to the program phase, provide a second difference between the voltage on the dummy word line and the voltage on the select gate line which is greater than the first difference, wherein the voltage on the dummy word line exceeds the voltage on the select gate line by the second difference. a NAND string (700n-703n, 710n-713n, 720n-723n, 730n-733n) comprising a channel (665, 710a), a drain-end select gate transistor (717, 737, 757, 777) at a drain-end of the NAND string, a selected data memory cell (704-714, 724-734, 744-754, 764-774) and a dummy memory cell (716, 736, 756, 776) adjacent to the drain-end select gate transistor; a bit line (BL0-BL3) connected to the drain-end; a selected word line (WLLO-WLL10) connected to the selected data memory cell; a dummy word line (WLDD0) connected to the dummy memory cell; a select gate line (SGD1) connected to the drain-end select gate transistor; and a control circuit (110, 122) configured to: in a pre-charge phase of a program loop (PLO-PL15), provide a first voltage (Vbl) on the bit line while a voltage (Vsgd_sel) on the select gate line is a first select gate line voltage and a voltage (VddO) on the dummy word line is a first dummy word line voltage; in a program phase of the program loop, provide a program voltage (Vpgm) on the selected word line and a second voltage on the bit line while the voltage on the select gate line is at a second select gate line voltage, lower than the first select gate line voltage, and the voltage on the dummy word line is at a second dummy word line voltage, higher than the first dummy word line voltage, wherein the second dummy word line voltage exceeds the second select gate line voltage by a first difference; and characterized in that the control circuit is configured to: in a transition from the pre-charge phase to the program phase, provide a second difference between the voltage on the dummy word line and the voltage on the select gate line which is greater than the first difference, wherein the voltage on the dummy word line exceeds the voltage on the select gate line by the second difference. in a pre-charge phase of a program loop (PLO-PL15), provide a first voltage (Vbl) on the bit line while a voltage (Vsgd_sel) on the select gate line is a first select gate line voltage and a voltage (VddO) on the dummy word line is a first dummy word line voltage; in a program phase of the program loop, provide a program voltage (Vpgm) on the selected word line and a second voltage on the bit line while the voltage on the select gate line is at a second select gate line voltage, lower than the first select gate line voltage, and the voltage on the dummy word line is at a second dummy word line voltage, higher than the first dummy word line voltage, wherein the second dummy word line voltage exceeds the second select gate line voltage by a first difference; and characterized in that the control circuit is configured to: in a transition from the pre-charge phase to the program phase, provide a second difference between the voltage on the dummy word line and the voltage on the select gate line which is greater than the first difference, wherein the voltage on the dummy word line exceeds the voltage on the select gate line by the second difference.