An arithmetic logic unit comprising: an adder, a sum saturator, a logic unit, a multiplier, a shifter, and a product saturator; a first register configured to receive a first operand (OP_1); a second register configured to receive a second operand (OP_2); wherein A) the adder is coupled to the first register and to the second register and configured to generate a sum of the first operand and the second operand; and generate intermediate sums; and wherein B) the sum saturator is coupled to receive the first operand (OP_1), the second operand (OP_2) and the sum and configured to generate a saturated sum of the first operand and the second operand; C) the multiplier is coupled to receive the first operand (OP_1), the second operand (OP_2), and intermediate sums from the adder and configured to determine the product of the first operand (OP_1) and the second operand (OP_2) based at least in part on intermediate sums generated by the adder; D) the shifter is coupled to the first register and the second register and configured to receive a scale factor (M_SCL), an operation code (OP_C), and the product of the first operand (OP_1) and the second operand (OP_2), the shifter being further configured - to generate a shift-result that is based on the value of the first operand (OP_1) and the second operand (OP_2) when the operation code (M_SCL) corresponds to a bitwise shift (LSL, LSR, ASR) and - to generate a scaled product based on the product and the scale factor (M_SCL), when the operation code (M_SCL) corresponds to a multiplication operation (MULT, MULTS); and E) the product saturator is coupled to receive the scaled product and configured to detect underflows and overflows in the scaled product and generate an N-bit saturated product. an adder, a sum saturator, a logic unit, a multiplier, a shifter, and a product saturator; a first register configured to receive a first operand (OP_1); a second register configured to receive a second operand (OP_2); wherein A) the adder is coupled to the first register and to the second register and configured to generate a sum of the first operand and the second operand; and generate intermediate sums; and wherein B) the sum saturator is coupled to receive the first operand (OP_1), the second operand (OP_2) and the sum and configured to generate a saturated sum of the first operand and the second operand; C) the multiplier is coupled to receive the first operand (OP_1), the second operand (OP_2), and intermediate sums from the adder and configured to determine the product of the first operand (OP_1) and the second operand (OP_2) based at least in part on intermediate sums generated by the adder; D) the shifter is coupled to the first register and the second register and configured to receive a scale factor (M_SCL), an operation code (OP_C), and the product of the first operand (OP_1) and the second operand (OP_2), the shifter being further configured - to generate a shift-result that is based on the value of the first operand (OP_1) and the second operand (OP_2) when the operation code (M_SCL) corresponds to a bitwise shift (LSL, LSR, ASR) and - to generate a scaled product based on the product and the scale factor (M_SCL), when the operation code (M_SCL) corresponds to a multiplication operation (MULT, MULTS); and E) the product saturator is coupled to receive the scaled product and configured to detect underflows and overflows in the scaled product and generate an N-bit saturated product. A) the adder is coupled to the first register and to the second register and configured to generate a sum of the first operand and the second operand; and generate intermediate sums; and wherein B) the sum saturator is coupled to receive the first operand (OP_1), the second operand (OP_2) and the sum and configured to generate a saturated sum of the first operand and the second operand; C) the multiplier is coupled to receive the first operand (OP_1), the second operand (OP_2), and intermediate sums from the adder and configured to determine the product of the first operand (OP_1) and the second operand (OP_2) based at least in part on intermediate sums generated by the adder; D) the shifter is coupled to the first register and the second register and configured to receive a scale factor (M_SCL), an operation code (OP_C), and the product of the first operand (OP_1) and the second operand (OP_2), the shifter being further configured - to generate a shift-result that is based on the value of the first operand (OP_1) and the second operand (OP_2) when the operation code (M_SCL) corresponds to a bitwise shift (LSL, LSR, ASR) and - to generate a scaled product based on the product and the scale factor (M_SCL), when the operation code (M_SCL) corresponds to a multiplication operation (MULT, MULTS); and - to generate a shift-result that is based on the value of the first operand (OP_1) and the second operand (OP_2) when the operation code (M_SCL) corresponds to a bitwise shift (LSL, LSR, ASR) and - to generate a scaled product based on the product and the scale factor (M_SCL), when the operation code (M_SCL) corresponds to a multiplication operation (MULT, MULTS); and E) the product saturator is coupled to receive the scaled product and configured to detect underflows and overflows in the scaled product and generate an N-bit saturated product.