A method, comprising: combining, by a combining circuit of a processor of an apparatus, channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme; and coding, by a coding circuit of the processor, second codeblocks of a larger size using the second coding scheme; wherein the combining, by the combining circuit of the processor of the apparatus, channel polarization of the communication channel with the first coding scheme for the first codeblocks of the smaller size to generate the second coding scheme comprises: factoring a large code into a plurality of subcodes with different code rates by a plurality of subcoders; determining a punctured bitmap and a frozen bitmap; performing per-subcode cyclic redundancy check, CRC, by a plurality of CRC circuits (CRC 0,CRC 1,CRC 2,CRC 3) each coupled to an input of a respective one of the plurality of mapping circuits (A 0, A 1, A 2, A 3), each coupled to an input of a respective one of the plurality of subcoders, wherein the punctured bitmap and the frozen bitmap are used to determine information bit locations, and combining retransmitted codeblock(s) as first sub-codeblock(s) and combining new data codeblock(s) as later sub-codeblock(s) for exploiting channel polarization gain; wherein, during operation: each sub-block of a plurality of sub-blocks of a message to be coded is provided to a respective one of the plurality of CRC circuits (CRC 0,CRC 1,CRC 2,CRC 3), and an output of each of the plurality of subcoders is added to an output of each of one or more other subcoders of the plurality of subcoders. combining, by a combining circuit of a processor of an apparatus, channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme; and coding, by a coding circuit of the processor, second codeblocks of a larger size using the second coding scheme; wherein the combining, by the combining circuit of the processor of the apparatus, channel polarization of the communication channel with the first coding scheme for the first codeblocks of the smaller size to generate the second coding scheme comprises: factoring a large code into a plurality of subcodes with different code rates by a plurality of subcoders; determining a punctured bitmap and a frozen bitmap; performing per-subcode cyclic redundancy check, CRC, by a plurality of CRC circuits (CRC 0,CRC 1,CRC 2,CRC 3) each coupled to an input of a respective one of the plurality of mapping circuits (A 0, A 1, A 2, A 3), each coupled to an input of a respective one of the plurality of subcoders, wherein the punctured bitmap and the frozen bitmap are used to determine information bit locations, and combining retransmitted codeblock(s) as first sub-codeblock(s) and combining new data codeblock(s) as later sub-codeblock(s) for exploiting channel polarization gain; factoring a large code into a plurality of subcodes with different code rates by a plurality of subcoders; determining a punctured bitmap and a frozen bitmap; performing per-subcode cyclic redundancy check, CRC, by a plurality of CRC circuits (CRC 0,CRC 1,CRC 2,CRC 3) each coupled to an input of a respective one of the plurality of mapping circuits (A 0, A 1, A 2, A 3), each coupled to an input of a respective one of the plurality of subcoders, wherein the punctured bitmap and the frozen bitmap are used to determine information bit locations, and combining retransmitted codeblock(s) as first sub-codeblock(s) and combining new data codeblock(s) as later sub-codeblock(s) for exploiting channel polarization gain; wherein, during operation: each sub-block of a plurality of sub-blocks of a message to be coded is provided to a respective one of the plurality of CRC circuits (CRC 0,CRC 1,CRC 2,CRC 3), and an output of each of the plurality of subcoders is added to an output of each of one or more other subcoders of the plurality of subcoders. each sub-block of a plurality of sub-blocks of a message to be coded is provided to a respective one of the plurality of CRC circuits (CRC 0,CRC 1,CRC 2,CRC 3), and an output of each of the plurality of subcoders is added to an output of each of one or more other subcoders of the plurality of subcoders.