A method for controlling a pipeline operation of a processor coupled to a higher level memory containing executable computer instructions loaded from a lower level memory by a fill generator, characterized in that, - it includes creating a track table containing a plurality of tracks and each track in the track table corresponds to a row in the track table with a row number, wherein each track includes a plurality of track points, and a track point corresponds to a single instruction or multiple instructions, a track point includes information about an instruction within a track, such as a branch instruction, thus, content of a track point includes information about a type of the corresponding instruction and a branch target address; - it includes determining a branch instruction to be executed by the processor; - it includes providing both an address of a branch target instruction of the branch instruction and an address of a next instruction following the branch instruction in a program sequence; - a branch instruction or a branch point, refers to any appropriate type of instruction which causes the CPU core to change an execution flow; any instruction to be executed by CPU core is filled in higher level memory before it is executed by CPU core, - it includes determining a branch decision with respect to the branch instruction issued by the pipeline operation of the processor before an execution stage operation of the branch instruction; and - it includes based on the track table, selecting at least one of the branch target instruction and the next instruction as an instruction to be executed by an execution unit of the processor, based on the branch decision and before the branch instruction is executed by the execution unit, wherein both the branch target instruction and the next instruction are made available for fetching by the processor such that the pipeline operation is not stalled whether or not a branch is taken with respect to the branch instruction, wherein said making available includes filling the instruction block corresponding to the branch target information into the higher level memory for execution by CPU core while the corresponding track is being built. - it includes creating a track table containing a plurality of tracks and each track in the track table corresponds to a row in the track table with a row number, wherein each track includes a plurality of track points, and a track point corresponds to a single instruction or multiple instructions, a track point includes information about an instruction within a track, such as a branch instruction, thus, content of a track point includes information about a type of the corresponding instruction and a branch target address; - it includes determining a branch instruction to be executed by the processor; - it includes providing both an address of a branch target instruction of the branch instruction and an address of a next instruction following the branch instruction in a program sequence; - a branch instruction or a branch point, refers to any appropriate type of instruction which causes the CPU core to change an execution flow; any instruction to be executed by CPU core is filled in higher level memory before it is executed by CPU core, - it includes determining a branch decision with respect to the branch instruction issued by the pipeline operation of the processor before an execution stage operation of the branch instruction; and - it includes based on the track table, selecting at least one of the branch target instruction and the next instruction as an instruction to be executed by an execution unit of the processor, based on the branch decision and before the branch instruction is executed by the execution unit, wherein both the branch target instruction and the next instruction are made available for fetching by the processor such that the pipeline operation is not stalled whether or not a branch is taken with respect to the branch instruction, wherein said making available includes filling the instruction block corresponding to the branch target information into the higher level memory for execution by CPU core while the corresponding track is being built.