A display panel, characterized by comprising: a base substrate, comprising a plurality of sub-pixels (spx), wherein at least one of the plurality of sub-pixels (spx) comprises a pixel circuit, the pixel circuit comprises a storage capacitor, an initialization transistor and a threshold compensation transistor; a silicon semiconductor layer located on the base substrate, wherein the silicon semiconductor layer comprises a silicon active layer of a driving transistor, the silicon active layer comprises a first electrode area, a second electrode area and a first channel area between the first electrode area and the second electrode area; a first insulating layer located on a side, facing away from the silicon semiconductor layer, of the base substrate; a first conductive layer located on a side, facing away from the base substrate, of the first insulating layer, wherein the first conductive layer comprises a plurality of scanning wires; a second insulating layer located on a side, facing away from the base substrate, of the first conductive layer; an oxide semiconductor layer located on a side, facing away from the base substrate, of the second insulating layer, wherein the oxide semiconductor layer comprises an oxide active layer of the initialization transistor and an oxide active layer of the threshold compensation transistor, the oxide active layer of the threshold compensation transistor comprises a third electrode area, a fourth electrode area and a second channel area between the third electrode area and the fourth electrode area, and in each sub-pixel (spx), a fourth electrode area of the oxide active layer of the initialization transistor and the fourth electrode area of the oxide active layer of the threshold compensation transistor are electrically connected to a gate of the driving transistor, and the third electrode area of the oxide active layer of the threshold compensation transistor is electrically connected to the second electrode area of the silicon active layer of the driving transistor; a third insulating layer located on a side, facing away from the base substrate, of the oxide semiconductor layer; a second conductive layer located on a side, facing away from the base substrate, of the third insulating layer; a fourth insulating layer located on a side, facing away from the base substrate, of the second conductive layer; and a third conductive layer located on a side, facing away from the base substrate, of the fourth insulating layer, wherein the third conductive layer comprises a plurality of data wires arranged at intervals; wherein the storage capacitor comprises three stacked electrode plates, and the three electrode plates are respectively arranged on the same layer together with the first conductive layer, the second conductive layer and the third conductive layer. a base substrate, comprising a plurality of sub-pixels (spx), wherein at least one of the plurality of sub-pixels (spx) comprises a pixel circuit, the pixel circuit comprises a storage capacitor, an initialization transistor and a threshold compensation transistor; a silicon semiconductor layer located on the base substrate, wherein the silicon semiconductor layer comprises a silicon active layer of a driving transistor, the silicon active layer comprises a first electrode area, a second electrode area and a first channel area between the first electrode area and the second electrode area; a first insulating layer located on a side, facing away from the silicon semiconductor layer, of the base substrate; a first conductive layer located on a side, facing away from the base substrate, of the first insulating layer, wherein the first conductive layer comprises a plurality of scanning wires; a second insulating layer located on a side, facing away from the base substrate, of the first conductive layer; an oxide semiconductor layer located on a side, facing away from the base substrate, of the second insulating layer, wherein the oxide semiconductor layer comprises an oxide active layer of the initialization transistor and an oxide active layer of the threshold compensation transistor, the oxide active layer of the threshold compensation transistor comprises a third electrode area, a fourth electrode area and a second channel area between the third electrode area and the fourth electrode area, and in each sub-pixel (spx), a fourth electrode area of the oxide active layer of the initialization transistor and the fourth electrode area of the oxide active layer of the threshold compensation transistor are electrically connected to a gate of the driving transistor, and the third electrode area of the oxide active layer of the threshold compensation transistor is electrically connected to the second electrode area of the silicon active layer of the driving transistor; a third insulating layer located on a side, facing away from the base substrate, of the oxide semiconductor layer; a second conductive layer located on a side, facing away from the base substrate, of the third insulating layer; a fourth insulating layer located on a side, facing away from the base substrate, of the second conductive layer; and a third conductive layer located on a side, facing away from the base substrate, of the fourth insulating layer, wherein the third conductive layer comprises a plurality of data wires arranged at intervals; wherein the storage capacitor comprises three stacked electrode plates, and the three electrode plates are respectively arranged on the same layer together with the first conductive layer, the second conductive layer and the third conductive layer.