Switching circuit for a transmission channel for ultrasound applications inserted between a connection terminal (Xdcr) for connecting an ultrasound transducer and a low voltage output terminal (LVout) and comprising a receiving switch, a high voltage clamp circuit inserted between said connection terminal (Xdcr) and a central node (Vc), a low voltage clamping switch inserted between said central node (Vc) and a terminal connected to a reference voltage, said receiving switch being low voltage and being inserted between said central node (Vc) and said low voltage output terminal (LVout), said low voltage clamping switch and said receiving switch being controlled in a complementary way with respect to each other, characterised in that said high voltage clamp circuit comprises: - a first and a second switching transistor (M1, M2) inserted between said connection terminal (Xdcr) and said central node (Vc) and having respective control terminals (G_M1, GM_2) connected to a driving block, said first and second switching transistors (M1, M2) being high voltage MOS transistors of opposite type; - a third switching transistor being of the same type as the second switching transistor connected to said connection terminal (Xdcr) and to said first switching transistor (M 1) and a fourth switching transistor being of the same type as the first switching transistor connected to said second switching transistor and to said connection terminal (Xdcr), said third and fourth switching transistors (M3 and M4) being high voltage MOS transistors which are adapted to be closed when said high voltage clamp circuit is active and are adapted to be opened to support high positive and negative voltages when said high voltage clamp circuit is not active and in that said driving block comprises an input circuit connected in turn to said clamp circuit through a driving circuit, said input circuit comprising a first circuit branch and a second circuit branch, in parallel to each other, inserted between a first and a second clamp supply voltage reference (Vdd and Vcc), said first circuit branch comprising a first inner node connected to the control terminal (G_M1) of the first switching transistor and the second circuit branch comprising a second inner node connected to said control terminal (G_M2) of the second switching transistor, and said driving circuit having a first and a second driving transistor (Md1 and Md2), said first driving transistor being inserted between the control terminal (G_M1) of said first switching transistor and the control terminal (G_M4) of said fourth switching transistor, and said second driving transistor being inserted between the control terminal (G_M2) of said second switching transistor and the control terminal (G_M3) of said third switching transistor, said first and second driving transistor (Mdl and Md2) having respective control terminals connected to said reference voltage. - a first and a second switching transistor (M1, M2) inserted between said connection terminal (Xdcr) and said central node (Vc) and having respective control terminals (G_M1, GM_2) connected to a driving block, said first and second switching transistors (M1, M2) being high voltage MOS transistors of opposite type; - a third switching transistor being of the same type as the second switching transistor connected to said connection terminal (Xdcr) and to said first switching transistor (M 1) and a fourth switching transistor being of the same type as the first switching transistor connected to said second switching transistor and to said connection terminal (Xdcr), said third and fourth switching transistors (M3 and M4) being high voltage MOS transistors which are adapted to be closed when said high voltage clamp circuit is active and are adapted to be opened to support high positive and negative voltages when said high voltage clamp circuit is not active