A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: performing, by the computing device, a placement operation on a 2D circuit design to generate a 2D circuit layout comprising R rows of circuit cells, where R is an integer equal to at least three; assigning, by the computing device, some of the circuit cells of a first group of circuit cells of the 2D circuit layout to one or more first rows of a first level of the 3D circuit layout and some of the circuit cells of the first group of circuit cells to one or more first rows of a second level of the 3D circuit layout, the first group corresponding to the circuit cells of a first row of the 2D circuit layout, or to the circuit cells of a plurality of first successive rows of the 2D circuit layout; and assigning, by the computing device, some of the circuit cells of a second group of circuit cells of the 2D circuit layout to one or more second rows of the first level of the 3D circuit layout and some of the circuit cells of the second group of circuit cells to one or more second rows of the second level of the 3D circuit layout, the second group corresponding to the circuit cells of a second row of the 2D circuit layout, or to the circuit cells of a plurality of second successive rows of the 2D circuit layout, wherein the assignment of each circuit cell of the first group is performed by: selecting, among at least one of the first rows of each of the first and second levels, the row having the greatest available space; and assigning the circuit cell of the first group to the selected row; and wherein the assignment of each circuit cell of the second group is performed by: selecting, among at least one of the second rows of each of the first and second levels, the row having the greatest available space; and assigning the circuit cell of the second group to the selected row; the method further comprising transmitting the 3D circuit layout to a manufacturing plant for fabrication. performing, by the computing device, a placement operation on a 2D circuit design to generate a 2D circuit layout comprising R rows of circuit cells, where R is an integer equal to at least three; assigning, by the computing device, some of the circuit cells of a first group of circuit cells of the 2D circuit layout to one or more first rows of a first level of the 3D circuit layout and some of the circuit cells of the first group of circuit cells to one or more first rows of a second level of the 3D circuit layout, the first group corresponding to the circuit cells of a first row of the 2D circuit layout, or to the circuit cells of a plurality of first successive rows of the 2D circuit layout; and assigning, by the computing device, some of the circuit cells of a second group of circuit cells of the 2D circuit layout to one or more second rows of the first level of the 3D circuit layout and some of the circuit cells of the second group of circuit cells to one or more second rows of the second level of the 3D circuit layout, the second group corresponding to the circuit cells of a second row of the 2D circuit layout, or to the circuit cells of a plurality of second successive rows of the 2D circuit layout, wherein the assignment of each circuit cell of the first group is performed by: selecting, among at least one of the first rows of each of the first and second levels, the row having the greatest available space; and assigning the circuit cell of the first group to the selected row; and selecting, among at least one of the first rows of each of the first and second levels, the row having the greatest available space; and assigning the circuit cell of the first group to the selected row; and wherein the assignment of each circuit cell of the second group is performed by: selecting, among at least one of the second rows of each of the first and second levels, the row having the greatest available space; and assigning the circuit cell of the second group to the selected row; selecting, among at least one of the second rows of each of the first and second levels, the row having the greatest available space; and assigning the circuit cell of the second group to the selected row;