Harmonic rejection mixer unit, comprising an input comprising a positive RF input (RF+) and a negative RF input (RF-); at least one harmonic rejection unit with at least two transistor units (T3a, T3b, T4a, T4b) for multiplying an input signal from the input with a multiplication signal wherein the at least one harmonic rejection unit further comprises a first output terminal and a second output terminal for connection to an operational amplifier; and a transistor control signal generating unit for generating transistor control signals (GS1-GS4) for the at least two transistor units (T3a, T3b, T4a, T4b) of the at least one harmonic rejection unit by deriving the transistor control signals (GS1-GS4) from a local oscillator signal, wherein the transistor control signals (GS3, GS4) for the at least two transistor units (T3a, T3b, T4a, T4b) are generated with a duty cycle of <50% and are generated such that the shape of the multiplication signal is achieved by a constructive summation of the output signals from the transistor units (T3a, T3b; T4a, T4b), wherein the transistor control signals (GS1-GS4) are generated such that only a summation of output signals from the transistor units (T3a, T3b; T4a, T4b) with the same sign or with zero is performed, wherein the harmonic rejection mixer unit further comprises a conversion gain modulation means (CGU; GM), coupled in series between the input and the at feast one harmonic rejection unit, and comprising at least one conversion gain modulation unit (CGM, V2I1-V2IN) comprising: a second resistor, coupled to the positive RF input (RF+), and coupled in series to a first node and a first transistor (T1b); a third resistor, coupled to the negative RF input (RF-), and coupled in series to a second node and a further first transistor (T1a); a first termination transistor (T2a) coupled between the first node and a ground or termination node and a second termination transistor (T2b) coupled between the second node and the ground or termination node; a first resistor in parallel with the second resistor and the first transistor (T1 b); and a fourth resistor arranged in parallel to the series connection of the third resistor and the first transistor (T1a) wherein the first transistor (T1b) and the further first transistor (T1a) are configured to receive first gate signals at their respective gates and the first and second termination transistors (T2a, T2b) are configured to receive second gate signals at their respective gates for performing a voltage-to-current conversion and for modulating the gain of the voltage-to-current conversion thereby modulating the conversion gain of the harmonic rejection mixer unit; wherein the transistor control signals are configured to avoid providing a connection between the positive RF input (RF+) and respectively the first output terminal or the second output terminal at the same time as providing a connection between the negative RF input (RF-) and the respective first output terminal or the second output terminal. a second resistor, coupled to the positive RF input (RF+), and coupled in series to a first node and a first transistor (T1b); a third resistor, coupled to the negative RF input (RF-), and coupled in series to a second node and a further first transistor (T1a); a first termination transistor (T2a) coupled between the first node and a ground or termination node and a second termination transistor (T2b) coupled between the second node and the ground or termination node; a first resistor in parallel with the second resistor and the first transistor (T1 b); and a fourth resistor arranged in parallel to the series connection of the third resistor and the first transistor (T1a)