A semiconductor device comprising: a silicon substrate having an n-type region; a gate insulating film formed on the n-type region, using nitrogen-containing silicon oxide; a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon; p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode; side wall spacers formed on side walls of said gate electrode, said side wall spacer comprising a lamination of a silicon oxide layer and a silicon nitride layer, the silicon nitride layer directly covering the gate electrode and being located between the gate electrode and the silicon oxide layer; a silicon nitride etch stopper film covering said gate electrode, said side wall spacers, and said p-type source/drain regions, a first interlayer insulating film having a planarized surface and covering said silicon nitride etch stopper film; a conductive plug formed in said first interlayer insulating film and said silicon nitride etch stopper film, and having a bottom end and a top end; a second interlayer insulating film (24, 25) formed over said first interlayer insulating film and having a planarized surface; a wiring trench formed in said interlayer insulating film from the planarized surface of said second interlayer insulating film to an inside thereof; and a copper wiring pattern including an underlying barrier layer of Ta or Ti and an upper level copper region, said copper wiring pattern being filled in said wiring trench, wherein said conductive plug is connected to said gate electrode at the bottom end, and is connected to said copper wiring pattern at the top end. a silicon substrate having an n-type region; a gate insulating film formed on the n-type region, using nitrogen-containing silicon oxide; a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon; p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode; side wall spacers formed on side walls of said gate electrode, said side wall spacer comprising a lamination of a silicon oxide layer and a silicon nitride layer, the silicon nitride layer directly covering the gate electrode and being located between the gate electrode and the silicon oxide layer; a silicon nitride etch stopper film covering said gate electrode, said side wall spacers, and said p-type source/drain regions, a first interlayer insulating film having a planarized surface and covering said silicon nitride etch stopper film; a conductive plug formed in said first interlayer insulating film and said silicon nitride etch stopper film, and having a bottom end and a top end; a second interlayer insulating film (24, 25) formed over said first interlayer insulating film and having a planarized surface; a wiring trench formed in said interlayer insulating film from the planarized surface of said second interlayer insulating film to an inside thereof; and a copper wiring pattern including an underlying barrier layer of Ta or Ti and an upper level copper region, said copper wiring pattern being filled in said wiring trench, wherein said conductive plug is connected to said gate electrode at the bottom end, and is connected to said copper wiring pattern at the top end.