A system comprising: a plurality of memory regions (108, 116, 118, 120), each of said memory regions (108, 116, 118, 120) having at least a low power state and a high power state; a controller configured to manage the power states of said memory regions (108, 116, 118, 120) separately and independently; a processor configured to manage memory contents by a method comprising: monitoring each of a plurality of memory objects to determine an access frequency for each of said memory objects; identifying a first memory region as a candidate for low power operation; identifying a first memory object as a low frequency access object; moving said first memory object to said first memory region; and operating said first memory region in said low power state, the system further comprising calculating a power savings by monitoring said first memory region to determine a length of time said first memory region is operated in said low power state and determining said power savings as a function of said length of time and a mapping engine configured to test at least one of said memory regions (108, 116, 118, 120) to determine a latency for a read query when said memory region is in said low power state, wherein latency is a performance parameter, wherein an optimization algorithm performs a tradeoff between power savings and performance characteristics. a plurality of memory regions (108, 116, 118, 120), each of said memory regions (108, 116, 118, 120) having at least a low power state and a high power state; a controller configured to manage the power states of said memory regions (108, 116, 118, 120) separately and independently; a processor configured to manage memory contents by a method comprising: monitoring each of a plurality of memory objects to determine an access frequency for each of said memory objects; identifying a first memory region as a candidate for low power operation; identifying a first memory object as a low frequency access object; moving said first memory object to said first memory region; and operating said first memory region in said low power state, the system further comprising calculating a power savings by monitoring said first memory region to determine a length of time said first memory region is operated in said low power state and determining said power savings as a function of said length of time and a mapping engine configured to test at least one of said memory regions (108, 116, 118, 120) to determine a latency for a read query when said memory region is in said low power state, wherein latency is a performance parameter, wherein an optimization algorithm performs a tradeoff between power savings and performance characteristics. monitoring each of a plurality of memory objects to determine an access frequency for each of said memory objects; identifying a first memory region as a candidate for low power operation; identifying a first memory object as a low frequency access object; moving said first memory object to said first memory region; and operating said first memory region in said low power state, the system further comprising calculating a power savings by monitoring said first memory region to determine a length of time said first memory region is operated in said low power state and determining said power savings as a function of said length of time and a mapping engine configured to test at least one of said memory regions (108, 116, 118, 120) to determine a latency for a read query when said memory region is in said low power state, wherein latency is a performance parameter, wherein an optimization algorithm performs a tradeoff between power savings and performance characteristics.