A quantum computer, comprising: a quantum processor, comprising: a first plurality of superconducting qubits (112, 114; 208, 210; 706, 708, 710) arranged in a hexagonal lattice pattern such that each qubit of the first plurality of superconducting qubits is substantially located at a hexagon apex of said hexagonal lattice pattern, a second plurality of superconducting qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) each arranged substantially along a hexagon edge of said hexagonal lattice pattern, wherein each of said first plurality of qubits (112, 114; 208, 210; 706, 708, 710) is coupled to three nearest-neighbor qubits of said second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716), wherein each of said second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) is coupled to two nearest-neighbor qubits of said first plurality of qubits (112, 114; 208, 210; 706, 708, 710), wherein each of said second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) is a control qubit at a control frequency determined at fabrication, wherein each of said first plurality of qubits (112, 114; 208, 210; 706, 708, 710) is a target qubit at one of a first target frequency determined at fabrication or a second target frequency determined at fabrication such that a control qubit couples each first target frequency target qubit to a second target frequency target qubit; and an error correction device configured to operate on said hexagonal lattice pattern of said first and second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) so as to detect and correct data errors, wherein said error correction device encodes a plurality of logical qubits into corresponding pluralities of said first and second pluralities of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716), and wherein said error correction device comprises X-type gauge circuits that measure phase flip errors that involve two or four data qubits. a first plurality of superconducting qubits (112, 114; 208, 210; 706, 708, 710) arranged in a hexagonal lattice pattern such that each qubit of the first plurality of superconducting qubits is substantially located at a hexagon apex of said hexagonal lattice pattern, a second plurality of superconducting qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) each arranged substantially along a hexagon edge of said hexagonal lattice pattern, wherein each of said first plurality of qubits (112, 114; 208, 210; 706, 708, 710) is coupled to three nearest-neighbor qubits of said second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716), wherein each of said second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) is coupled to two nearest-neighbor qubits of said first plurality of qubits (112, 114; 208, 210; 706, 708, 710), wherein each of said second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) is a control qubit at a control frequency determined at fabrication, wherein each of said first plurality of qubits (112, 114; 208, 210; 706, 708, 710) is a target qubit at one of a first target frequency determined at fabrication or a second target frequency determined at fabrication such that a control qubit couples each first target frequency target qubit to a second target frequency target qubit; and an error correction device configured to operate on said hexagonal lattice pattern of said first and second plurality of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716) so as to detect and correct data errors, wherein said error correction device encodes a plurality of logical qubits into corresponding pluralities of said first and second pluralities of qubits (100, 102, 104, 106, 108, 110; 200, 202. 204, 206; 712, 714, 716), and wherein said error correction device comprises X-type gauge circuits that measure phase flip errors that involve two or four data qubits.