A method of accessing block data storable within a non-volatile memory - NVM - device in a computer system, the computer system including at least one host processor and at least one memory bus, the method comprising: receiving, at a controller over the memory bus, at least one first command from the host processor, the first command including a memory store command, the first command further including a logical address, the controller including at least one block window defining at least one address range for accessing the block data storable within the NVM device; translating, by the controller, the logical address included in the first command to a physical address within the NVM device, the logical address conforming to at least a portion of the address range defined by the block window; and accessing, by the controller, the block data at the physical address within the NVM device, wherein the controller further includes at least one command register associated with the at least one block window, and wherein the receiving of the at least one first command from the host processor includes receiving the first command at the command register associated with the block window, characterized in that the logical address includes a logical block write base address, and a logical block write offset address defining a relative offset from the logical block write base address, wherein the controller further includes a plurality of base address registers (0-q) containing a plurality of logical base addresses, respectively, each of the plurality of logical base addresses corresponding to a predetermined portion of the address range defined by the block window, and wherein the method further comprises: in response to the memory store command, selecting one of the plurality of base address registers based at least on one or more of the logical block write base address and the logical block write offset address included in the memory store command receiving, at the controller over the memory bus, the block data at the relative offset from the logical block write base address within the address range of the block window. wherein the controller further includes an address translation component, and wherein the translating of the logical address to the physical address within the NVM device includes translating, by the address translation component, the logical base address contained in the selected base address register and the logical block write offset address to the physical address within the NVM device. receiving, at a controller over the memory bus, at least one first command from the host processor, the first command including a memory store command, the first command further including a logical address, the controller including at least one block window defining at least one address range for accessing the block data storable within the NVM device; translating, by the controller, the logical address included in the first command to a physical address within the NVM device, the logical address conforming to at least a portion of the address range defined by the block window; and accessing, by the controller, the block data at the physical address within the NVM device, wherein the controller further includes at least one command register associated with the at least one block window, and wherein the receiving of the at least one first command from the host processor includes receiving the first command at the command register associated with the block window, characterized in that the logical address includes a logical block write base address, and a logical block write offset address defining a relative offset from the logical block write base address, wherein the controller further includes a plurality of base address registers (0-q) containing a plurality of logical base addresses, respectively, each of the plurality of logical base addresses corresponding to a predetermined portion of the address range defined by the block window, and wherein the method further comprises: in response to the memory store command, selecting one of the plurality of base address registers based at least on one or more of the logical block write base address and the logical block write offset address included in the memory store command receiving, at the controller over the memory bus, the block data at the relative offset from the logical block write base address within the address range of the block window. wherein the controller further includes an address translation component, and wherein the translating of the logical address to the physical address within the NVM device includes translating, by the address translation component, the logical base address contained in the selected base address register and the logical block write offset address to the physical address within the NVM device.