A digital interface receiver for receiving a digital signal containing an audio signal, a control signal, a synchronization signal, and a clock signal that are transmitted from a source, comprising: a reception unit ( 2a to 2d) for receiving said digital signal comprising said clock signal transmitted from said source; a detection device ( 1a-1d, 12-17) for detecting an interface state between said digital interface receiver and said source; a mute circuit for muting the audio signal extracted from said digital signal; a controlling device for controlling said mute circuit to be in a mute state or unmute state based on a detection result from said detection device ( 1a-1d, 12-17); a multiplier circuit for multiplying the clock signal received by said reception unit ( 2a to 2d); an audio clock generation circuit that generates an audio clock signal based on said control signal; and a sync separation circuit for separating the synchronization signal from the digital signal received by said reception unit ( 2a to 2d); characterised in that the detection device ( 1a-1d, 12-17) includes a clock detection circuit for detecting as said interface state whether the clock signal transmitted from said source has been input or not, a first lock detection circuit for detecting whether said multiplier circuit is being locked or not as said interface state, a second lock detection circuit for detecting whether said audio clock generation circuit is being locked or not as said interface state, and a synchronization detection circuit for detecting whether the synchronization signal separated by said sync separation circuit is stable or not as said interface state, said controlling device is configured to place said mute circuit in a mute state when said clock detection circuit does not detect the clock signal input, when said first lock detection circuit detects that said multiplier circuit is being unlocked, when said second lock detection circuit detects that said audio clock generation circuit is being unlocked, or when said synchronization detection circuit detects that the synchronization signal is in an unstable state, and said controlling device is configured to place said mute circuit in a mute state when the interface state detected by said detection device ( 1a-1d, 12-17) is in a given defective state, and places said mute circuit in an unmute state when a given period of time ( α) has elapsed since the interface state detected by said detection device ( 1a-1d, 12-17) turned into a given normal state. a reception unit ( 2a to 2d) for receiving said digital signal comprising said clock signal transmitted from said source; a detection device ( 1a-1d, 12-17) for detecting an interface state between said digital interface receiver and said source; a mute circuit for muting the audio signal extracted from said digital signal; a controlling device for controlling said mute circuit to be in a mute state or unmute state based on a detection result from said detection device ( 1a-1d, 12-17); a multiplier circuit for multiplying the clock signal received by said reception unit ( 2a to 2d); an audio clock generation circuit that generates an audio clock signal based on said control signal; and a sync separation circuit for separating the synchronization signal from the digital signal received by said reception unit ( 2a to 2d); characterised in that the detection device ( 1a-1d, 12-17) includes a clock detection circuit for detecting as said interface state whether the clock signal transmitted from said source has been input or not, a first lock detection circuit for detecting whether said multiplier circuit is being locked or not as said interface state, a second lock detection circuit for detecting whether said audio clock generation circuit is being locked or not as said interface state, and a synchronization detection circuit for detecting whether the synchronization signal separated by said sync separation circuit is stable or not as said interface state, said controlling device is configured to place said mute circuit in a mute state when said clock detection circuit does not detect the clock signal input, when said first lock detection circuit detects that said multiplier circuit is being unlocked, when said second lock detection circuit detects that said audio clock generation circuit is being unlocked, or when said synchronization detection circuit detects that the synchronization signal is in an unstable state, and said controlling device is configured to place said mute circuit in a mute state when the interface state detected by said detection device ( 1a-1d, 12-17) is in a given defective state, and places said mute circuit in an unmute state when a given period of time ( α) has elapsed since the interface state detected by said detection device ( 1a-1d, 12-17) turned into a given normal state.