A fabrication method of a field effect device successively comprising: - providing a substrate (1, 15, 16) covered by ∘ a pattern made from semiconductor material comprising a first layer made from a first semiconductor material covering a second layer made from a second semiconductor material, ∘ a gate pattern covering the pattern made from semiconductor material so as to define a source region, a drain region and a conduction channel in the pattern made from semiconductor material, - etching the first layer made from the first semiconductor material using the gate pattern as etch mask, - etching the second layer made from a second semiconductor material so as to form a cavity and to suspend the first layer made from the first semiconductor material, - depositing a electrically insulating filling material so as to fill the cavity, - etching the filling material using the gate pattern as etch mask to form a dividing pattern in the cavity, the pattern made from semiconductor material covering the dividing pattern, the dividing pattern being electrically insulating and comprising at least three consecutive surfaces covered by the pattern made from semiconductor material, - forming the source and drain regions by selective epitaxy, - depositing a covering layer (13a, 13b) so as to cover the substrate, the pattern made from semiconductor material and the gate pattern, - eliminating the substrate (1, 15, 16) so as to release a part of the source region, of the drain region and of the gate pattern, - depositing a metallic material and annealing it to form an alloy by reaction between the metallic material and a semiconductor material of the source and drain regions, - depositing a second covering layer, the first and second covering layers (13a, 13b, 18) being separated by the pattern made from semiconductor material over at least a part thereof, - forming access vias (19, 22, 26) to the source region, the drain region and the gate pattern in the second covering layer, - filling the access vias (19, 22, 26) with an electrical conductor so as to form source and drain contacts arranged on one side of the conduction channel and a gate electrode predominantly arranged on the other side of the conduction channel. - providing a substrate (1, 15, 16) covered by ∘ a pattern made from semiconductor material comprising a first layer made from a first semiconductor material covering a second layer made from a second semiconductor material, ∘ a gate pattern covering the pattern made from semiconductor material so as to define a source region, a drain region and a conduction channel in the pattern made from semiconductor material, ∘ a pattern made from semiconductor material comprising a first layer made from a first semiconductor material covering a second layer made from a second semiconductor material, ∘ a gate pattern covering the pattern made from semiconductor material so as to define a source region, a drain region and a conduction channel in the pattern made from semiconductor material, - etching the first layer made from the first semiconductor material using the gate pattern as etch mask, - etching the second layer made from a second semiconductor material so as to form a cavity and to suspend the first layer made from the first semiconductor material, - depositing a electrically insulating filling material so as to fill the cavity, - etching the filling material using the gate pattern as etch mask to form a dividing pattern in the cavity, the pattern made from semiconductor material covering the dividing pattern, the dividing pattern being electrically insulating and comprising at least three consecutive surfaces covered by the pattern made from semiconductor material, - forming the source and drain regions by selective epitaxy, - depositing a covering layer (13a, 13b) so as to cover the substrate, the pattern made from semiconductor material and the gate pattern, - eliminating the substrate (1, 15, 16) so as to release a part of the source region, of the drain region and of the gate pattern, - depositing a metallic material and annealing it to form an alloy by reaction between the metallic material and a semiconductor material of the source and drain regions, - depositing a second covering layer, the first and second covering layers (13a, 13b, 18) being separated by the pattern made from semiconductor material over at least a part thereof, - forming access vias (19, 22, 26) to the source region, the drain region and the gate pattern in the second covering layer, - filling the access vias (19, 22, 26) with an electrical conductor so as to form source and drain contacts arranged on one side of the conduction channel and a gate electrode predominantly arranged on the other side of the conduction channel.