A shift register, comprising: input terminals of the shift register, comprising a start signal input terminal, a first clock signal input terminal and a second clock signal input terminal; a pre-charging circuit connected to the start signal input terminal to receive a start signal and connected to first clock signal input terminal to receive a first clock signal, for outputting a first turn-on voltage and a second turn-on voltage in response to the start signal and the first clock signal; a first pulling-up circuit connected to a first turn-on voltage outputting terminal of the pre-charging circuit to receive the first turn-on voltage and connected to an external high voltage to receive the external high voltage, for outputting a high level in response to an enable level of the start signal and an enable level of the first clock signal under a control of the first turn-on voltage; a pulling-down circuit connected to the second clock signal input terminal to receive a second clock signal and connected to a second turn-on voltage outputting terminal of the pre-charging circuit to receive the second turn-on voltage, for outputting a low level in response to a disable level of the start signal, a disable level of the first clock signal and an enable level of the second clock signal (CLKB) under a control of the second turn-on voltage; a second pulling-up circuit connected to the second turn-on voltage outputting terminal of the pre-charging circuit to receive the second turn-on voltage and connected to the external high voltage to receive the external high voltage, for outputting the high level when the second turn-on voltage is at a disable level; and an output terminal of the shift register, connected to an output terminal of the first pulling-up circuit, an output terminal of the pulling-down circuit and an output terminal of the second pulling-up circuit, for outputting a voltage signal. input terminals of the shift register, comprising a start signal input terminal, a first clock signal input terminal and a second clock signal input terminal; a pre-charging circuit connected to the start signal input terminal to receive a start signal and connected to first clock signal input terminal to receive a first clock signal, for outputting a first turn-on voltage and a second turn-on voltage in response to the start signal and the first clock signal; a first pulling-up circuit connected to a first turn-on voltage outputting terminal of the pre-charging circuit to receive the first turn-on voltage and connected to an external high voltage to receive the external high voltage, for outputting a high level in response to an enable level of the start signal and an enable level of the first clock signal under a control of the first turn-on voltage; a pulling-down circuit connected to the second clock signal input terminal to receive a second clock signal and connected to a second turn-on voltage outputting terminal of the pre-charging circuit to receive the second turn-on voltage, for outputting a low level in response to a disable level of the start signal, a disable level of the first clock signal and an enable level of the second clock signal (CLKB) under a control of the second turn-on voltage; a second pulling-up circuit connected to the second turn-on voltage outputting terminal of the pre-charging circuit to receive the second turn-on voltage and connected to the external high voltage to receive the external high voltage, for outputting the high level when the second turn-on voltage is at a disable level; and an output terminal of the shift register, connected to an output terminal of the first pulling-up circuit, an output terminal of the pulling-down circuit and an output terminal of the second pulling-up circuit, for outputting a voltage signal.