A signal generator comprising: digital delay circuitry having a delay input and a plurality of output taps, including at least a main tap and a delayed tap; a plurality of driver slices (500, 600) arranged in parallel, each driver slice (500, 600) having a digital driver input and a slice output, each driver slice (500, 600) being operative to generate a signal at a signal level determined by the digital driver input, and wherein each driver slice (500, 600) comprises: a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and, for each resistive element, a voltage switching circuit (501, 502, 503) connected to the second end of the resistive element, the voltage switching circuit configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit being controlled by the digital driver input; a common output node connected to the slice outputs; and for each of the driver slices (500, 600), a pre-driver switching circuit operative to selectively couple the digital input of the respective driver slice (500, 600) to one of a group of driver input sources, the group of driver input sources including at least the main tap and the delayed tap. digital delay circuitry having a delay input and a plurality of output taps, including at least a main tap and a delayed tap; a plurality of driver slices (500, 600) arranged in parallel, each driver slice (500, 600) having a digital driver input and a slice output, each driver slice (500, 600) being operative to generate a signal at a signal level determined by the digital driver input, and wherein each driver slice (500, 600) comprises: a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and, for each resistive element, a voltage switching circuit (501, 502, 503) connected to the second end of the resistive element, the voltage switching circuit configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit being controlled by the digital driver input; a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and, for each resistive element, a voltage switching circuit (501, 502, 503) connected to the second end of the resistive element, the voltage switching circuit configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit being controlled by the digital driver input; a common output node connected to the slice outputs; and for each of the driver slices (500, 600), a pre-driver switching circuit operative to selectively couple the digital input of the respective driver slice (500, 600) to one of a group of driver input sources, the group of driver input sources including at least the main tap and the delayed tap.