A semiconductor device comprising: a first processor; a second processor; a first delay circuit that brings in a signal that is input into the first processor, delays the brought-in signal by the time period of a predefined number of cycles, and inputs the delayed signal into the second processor; a first compression circuit that brings in a signal of n-bit width output from the first processor and compresses the signal of n-bit width into a signal of m-bit width, wherein m<n; a second compression circuit that brings in a signal of n-bit width output from the second processor and compresses the signal of n-bit width into a signal of m-bit width; a second delay circuit that brings in the signal of m-bit width output from the first compressor, delays the signal of m-bit width by the time period of the predefined number of cycles used by the first delay circuit, and outputs the delayed signal; and a coincidence comparison circuit that brings in the signal of m-bit width output from the second delay circuit and the signal of m-bit width output from the second compression circuit, and compares bit-wise the corresponding bits of the two brought-in signals with each other to check whether the corresponding bits of the two brought-in signals coincide with each other or not, wherein each of the first and second compression circuit breaks down the signal of n-bit width into (s+1) groups, wherein (s+1) represents the number of the groups; outputs a signal of d-bit width of one group without changing the d-bit width, wherein d+s=m; and includes s hash function circuits, wherein s represents the number of the hash function circuits, that compress the bit widths of signals of s groups into 1-bit width respectively. a first processor; a second processor; a first delay circuit that brings in a signal that is input into the first processor, delays the brought-in signal by the time period of a predefined number of cycles, and inputs the delayed signal into the second processor; a first compression circuit that brings in a signal of n-bit width output from the first processor and compresses the signal of n-bit width into a signal of m-bit width, wherein m<n; a second compression circuit that brings in a signal of n-bit width output from the second processor and compresses the signal of n-bit width into a signal of m-bit width; a second delay circuit that brings in the signal of m-bit width output from the first compressor, delays the signal of m-bit width by the time period of the predefined number of cycles used by the first delay circuit, and outputs the delayed signal; and a coincidence comparison circuit that brings in the signal of m-bit width output from the second delay circuit and the signal of m-bit width output from the second compression circuit, and compares bit-wise the corresponding bits of the two brought-in signals with each other to check whether the corresponding bits of the two brought-in signals coincide with each other or not, wherein each of the first and second compression circuit breaks down the signal of n-bit width into (s+1) groups, wherein (s+1) represents the number of the groups; outputs a signal of d-bit width of one group without changing the d-bit width, wherein d+s=m; and includes s hash function circuits, wherein s represents the number of the hash function circuits, that compress the bit widths of signals of s groups into 1-bit width respectively.