A semiconductor device comprising: a substrate; a 1 st transistor formed above the substrate, and having a 1 st transistor stack comprising a plurality of 1 st channel structures, a 1 st gate structure surrounding the 1 st channel structures, and 1 st and 2 nd source/drain regions (311, 312) at both ends of the 1 st transistor stack in a 1 st channel length direction; and a 2 nd transistor formed above the 1 st transistor in a vertical direction, and having a 2 nd transistor stack comprising a plurality of 2 nd channel structures, a 2 nd gate structure surrounding the 2 nd channel structures, and 3 rd and 4 th source/drain regions (313, 314) at both ends of the 2 nd transistor stack in a 2 nd channel length direction, wherein the 3 rd source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region, and the 4 th source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region, wherein the 1 st transistor stack is a 1 st nanosheet stack and the plurality of 1 st channel structures comprises a plurality of 1 st nanosheet layers, wherein the 2 nd transistor stack is a 2 nd nanosheet stack and the plurality of 2 nd channel structures comprises a plurality of 2 nd nanosheet layers, wherein widths of the 1 st nanosheet layers in a 1 st channel width direction are the same, and widths of the 2 nd nanosheet layers in a 2 nd channel width direction are the same, wherein lengths of the 1 st nanosheet layers in the 1 st channel length direction are the same, and lengths of the 2 nd nanosheet layers in the 2 nd channel length direction are the same, wherein the widths of the 1 st nanosheet layers in the 1 st channel width direction are the same as the lengths of the 2 nd nanosheet layers in the 2 nd channel length direction, and wherein the 1 st and 2 nd channel length directions are different from each other. a substrate; a 1 st transistor formed above the substrate, and having a 1 st transistor stack comprising a plurality of 1 st channel structures, a 1 st gate structure surrounding the 1 st channel structures, and 1 st and 2 nd source/drain regions (311, 312) at both ends of the 1 st transistor stack in a 1 st channel length direction; and a 2 nd transistor formed above the 1 st transistor in a vertical direction, and having a 2 nd transistor stack comprising a plurality of 2 nd channel structures, a 2 nd gate structure surrounding the 2 nd channel structures, and 3 rd and 4 th source/drain regions (313, 314) at both ends of the 2 nd transistor stack in a 2 nd channel length direction, wherein the 3 rd source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region, and the 4 th source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region, wherein the 1 st transistor stack is a 1 st nanosheet stack and the plurality of 1 st channel structures comprises a plurality of 1 st nanosheet layers, wherein the 2 nd transistor stack is a 2 nd nanosheet stack and the plurality of 2 nd channel structures comprises a plurality of 2 nd nanosheet layers, wherein widths of the 1 st nanosheet layers in a 1 st channel width direction are the same, and widths of the 2 nd nanosheet layers in a 2 nd channel width direction are the same, wherein lengths of the 1 st nanosheet layers in the 1 st channel length direction are the same, and lengths of the 2 nd nanosheet layers in the 2 nd channel length direction are the same, wherein the widths of the 1 st nanosheet layers in the 1 st channel width direction are the same as the lengths of the 2 nd nanosheet layers in the 2 nd channel length direction, and wherein the 1 st and 2 nd channel length directions are different from each other.