A processor comprising: a write buffer having a plurality of write buffer entries for storing data to be stored in external memory to reduce instruction pipeline stalls by providing a resource for storing the data prior to forwarding the data to the external memory, wherein each write buffer entry includes a buffer for storing data to be stored in the external memory and a mask having a bit corresponding to each byte in the buffer, a state of each bit in the mask indicating whether the corresponding byte in the buffer is storing data to be written to the external memory; and a system interface, the system interface comprising: an ordering queue, data stored in the write buffer being sent to external memory via an ordering queue entry in the ordering queue identifying one or more write buffer entries storing the data being sent to the external memory; and an ordering queue logic which upon detecting execution of a store ordering instruction (SYNCW) ensures that write buffer addresses identified by ordering queue entries in the ordering queue are sent to the external memory prior to sending an address for a subsequently issued store instruction, wherein upon detecting execution of the store ordering instruction and detecting active write buffer entries in the write buffer, the system interface allocates the ordering queue entry and identifies all active write buffer entries in the ordering queue entry. a write buffer having a plurality of write buffer entries for storing data to be stored in external memory to reduce instruction pipeline stalls by providing a resource for storing the data prior to forwarding the data to the external memory, wherein each write buffer entry includes a buffer for storing data to be stored in the external memory and a mask having a bit corresponding to each byte in the buffer, a state of each bit in the mask indicating whether the corresponding byte in the buffer is storing data to be written to the external memory; and a system interface, the system interface comprising: an ordering queue, data stored in the write buffer being sent to external memory via an ordering queue entry in the ordering queue identifying one or more write buffer entries storing the data being sent to the external memory; and an ordering queue logic which upon detecting execution of a store ordering instruction (SYNCW) ensures that write buffer addresses identified by ordering queue entries in the ordering queue are sent to the external memory prior to sending an address for a subsequently issued store instruction, wherein upon detecting execution of the store ordering instruction and detecting active write buffer entries in the write buffer, the system interface allocates the ordering queue entry and identifies all active write buffer entries in the ordering queue entry. an ordering queue, data stored in the write buffer being sent to external memory via an ordering queue entry in the ordering queue identifying one or more write buffer entries storing the data being sent to the external memory; and an ordering queue logic which upon detecting execution of a store ordering instruction (SYNCW) ensures that write buffer addresses identified by ordering queue entries in the ordering queue are sent to the external memory prior to sending an address for a subsequently issued store instruction, wherein upon detecting execution of the store ordering instruction and detecting active write buffer entries in the write buffer, the system interface allocates the ordering queue entry and identifies all active write buffer entries in the ordering queue entry.