A compound semiconductor device, comprising: a first electrode; a first compound semiconductor layer formed over the first electrode; a second compound semiconductor layer formed on the first compound semiconductor layer; a third compound semiconductor layer formed on the second compound semiconductor layer; a second electrode formed over the third compound semiconductor layer; a fourth compound semiconductor layer formed in an opening formed in a stack of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer, the fourth compound semiconductor layer being in contact with side surfaces of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer, the side surfaces facing to the opening; a gate electrode that controls an electric potential of an interface between the second compound semiconductor layer and the fourth compound semiconductor layer, the gate electrode being formed in the opening; and a third electrode insulated from the first compound semiconductor layer, the third electrode being in contact with the first electrode and the second compound semiconductor layer, wherein a lattice constant of the second compound semiconductor layer is smaller than both of a lattice constant of the first compound semiconductor layer and a lattice constant of the third compound semiconductor layer, a lattice constant of the fourth compound semiconductor layer is smaller than both of the lattice constant of the first compound semiconductor layer and the lattice constant of the third compound semiconductor layer, and a conduction band energy of the second compound semiconductor layer is higher than a conduction band energy of the third compound semiconductor layer. a first electrode; a first compound semiconductor layer formed over the first electrode; a second compound semiconductor layer formed on the first compound semiconductor layer; a third compound semiconductor layer formed on the second compound semiconductor layer; a second electrode formed over the third compound semiconductor layer; a fourth compound semiconductor layer formed in an opening formed in a stack of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer, the fourth compound semiconductor layer being in contact with side surfaces of the first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer, the side surfaces facing to the opening; a gate electrode that controls an electric potential of an interface between the second compound semiconductor layer and the fourth compound semiconductor layer, the gate electrode being formed in the opening; and a third electrode insulated from the first compound semiconductor layer, the third electrode being in contact with the first electrode and the second compound semiconductor layer, wherein a lattice constant of the second compound semiconductor layer is smaller than both of a lattice constant of the first compound semiconductor layer and a lattice constant of the third compound semiconductor layer, a lattice constant of the fourth compound semiconductor layer is smaller than both of the lattice constant of the first compound semiconductor layer and the lattice constant of the third compound semiconductor layer, and a conduction band energy of the second compound semiconductor layer is higher than a conduction band energy of the third compound semiconductor layer.