A system comprising: a first voltage domain (102, 202) including a first signal driver circuit (106, 206, 208) configured and arranged to receive a first control signal (Control 1, D1) and to generate a first signal with information that is encoded using a presence or an absence of a carrier wave based on the state of the first control signal, and a second signal driver circuit (108, 206, 208) configured and arranged to receive a second control signal (Control 2, D2) and to generate a second signal with information that is encoded using the presence or absence of a carrier wave based on the state of the second control signal; a second voltage domain (104, 204) including a first determination circuit (110, 212) configured and arranged to detect the presence of a carrier wave on a first input and to generate a first control signal in response to detecting the presence of a carrier wave on the first input; a second determination circuit (112, 214) configured and arranged to detect the presence of a carrier wave on a second input and to generate a second control signal in response to detecting the presence of a carrier wave on the second input; a first signal path capacitively coupling the first signal to the first input; a second signal path capacitively coupling the second signal to the second input; a first output circuit configured and arranged to drive, in response to a detection of a carrier wave from the first determination circuit, an output node to a high voltage in the second domain, wherein the first output circuit includes a transistor having a drain and a source, coupled between a first voltage source providing the high voltage and the output node (GATE) and further having a gate configured to receive the first control signal; and a second output circuit configured and arranged to drive, in response to a detection of a carrier wave from the second determination circuit, the output node to a low voltage in the second domain, wherein the second output circuit includes a transistor having a drain and a source, coupled between a voltage source providing the low voltage and the output node (GATE) and further having a gate configured to receive the second control signal. a first voltage domain (102, 202) including a first signal driver circuit (106, 206, 208) configured and arranged to receive a first control signal (Control 1, D1) and to generate a first signal with information that is encoded using a presence or an absence of a carrier wave based on the state of the first control signal, and a second signal driver circuit (108, 206, 208) configured and arranged to receive a second control signal (Control 2, D2) and to generate a second signal with information that is encoded using the presence or absence of a carrier wave based on the state of the second control signal; a first signal driver circuit (106, 206, 208) configured and arranged to receive a first control signal (Control 1, D1) and to generate a first signal with information that is encoded using a presence or an absence of a carrier wave based on the state of the first control signal, and a second signal driver circuit (108, 206, 208) configured and arranged to receive a second control signal (Control 2, D2) and to generate a second signal with information that is encoded using the presence or absence of a carrier wave based on the state of the second control signal; a second voltage domain (104, 204) including a first determination circuit (110, 212) configured and arranged to detect the presence of a carrier wave on a first input and to generate a first control signal in response to detecting the presence of a carrier wave on the first input; a second determination circuit (112, 214) configured and arranged to detect the presence of a carrier wave on a second input and to generate a second control signal in response to detecting the presence of a carrier wave on the second input; a first determination circuit (110, 212) configured and arranged to detect the presence of a carrier wave on a first input and to generate a first control signal in response to detecting the presence of a carrier wave on the first input; a second determination circuit (112, 214) configured and arranged to detect the presence of a carrier wave on a second input and to generate a second control signal in response to detecting the presence of a carrier wave on the second input; a first signal path capacitively coupling the first signal to the first input; a second signal path capacitively coupling the second signal to the second input; a first output circuit configured and arranged to drive, in response to a detection of a carrier wave from the first determination circuit, an output node to a high voltage in the second domain, wherein the first output circuit includes a transistor having a drain and a source, coupled between a first voltage source providing the high voltage and the output node (GATE) and further having a gate configured to receive the first control signal; and a second output circuit configured and arranged to drive, in response to a detection of a carrier wave from the second determination circuit, the output node to a low voltage in the second domain, wherein the second output circuit includes a transistor having a drain and a source, coupled between a voltage source providing the low voltage and the output node (GATE) and further having a gate configured to receive the second control signal.