A memory controller (410, 410a), comprising: a key generator configured to generate a first security key (1ST SEC_KEY) and a second security key (2ND SEC_KEY) based on a write request from a host; an encryption and decryption circuit configured to encrypt write data (WDATA) corresponding to the write request based on the first security key (1ST SEC_KEY) to generate encrypted write data (ENC_WDATA), and configured to encrypt the first security key based on the second security key (2ND SEC_KEY) to generate a first encrypted security key; and a processor configured to control a plurality of nonvolatile memories such that the encrypted write data (ENC_WDATA), the first encrypted security key, and the second security key (2ND SEC_KEY) are programmed in at least one of the plurality of nonvolatile memories, and configured to, based on an erase request for the encrypted write data from the host, control the plurality of nonvolatile memories such that a dummy program operation is performed on a page of the plurality of nonvolatile memories in which the second security key (2ND SEC_KEY) is programmed instead of erasing the encrypted write data, wherein: each of the plurality of nonvolatile memories includes a plurality of memory blocks, and the processor is configured to control the plurality of nonvolatile memories such that the encrypted write data (ENC_WDATA) is programmed in a first memory block among the plurality of memory blocks, and configured to control the plurality of nonvolatile memories such that the first encrypted security key and the second security key (2ND SEC_KEY) are programmed in a second memory block among the plurality of memory blocks, the first memory block being different from the second memory block, wherein the memory controller (410, 410a) is configured to perform a process comprising the dummy program operation in response to the erase request in units of blocks; wherein a change of the first encrypted security key (1 ST ENC_SEC_KEY) and the second security key (2ND SEC_KEY) is performed separately from the encrypted write data (ENC_WDATA); and wherein the dummy program operation consists in invalidating data at the corresponding region by overwriting dummy data into the page where the second security key is stored. a key generator configured to generate a first security key (1ST SEC_KEY) and a second security key (2ND SEC_KEY) based on a write request from a host; an encryption and decryption circuit configured to encrypt write data (WDATA) corresponding to the write request based on the first security key (1ST SEC_KEY) to generate encrypted write data (ENC_WDATA), and configured to encrypt the first security key based on the second security key (2ND SEC_KEY) to generate a first encrypted security key; and a processor configured to control a plurality of nonvolatile memories such that the encrypted write data (ENC_WDATA), the first encrypted security key, and the second security key (2ND SEC_KEY) are programmed in at least one of the plurality of nonvolatile memories, and configured to, based on an erase request for the encrypted write data from the host, control the plurality of nonvolatile memories such that a dummy program operation is performed on a page of the plurality of nonvolatile memories in which the second security key (2ND SEC_KEY) is programmed instead of erasing the encrypted write data, wherein: each of the plurality of nonvolatile memories includes a plurality of memory blocks, and the processor is configured to control the plurality of nonvolatile memories such that the encrypted write data (ENC_WDATA) is programmed in a first memory block among the plurality of memory blocks, and configured to control the plurality of nonvolatile memories such that the first encrypted security key and the second security key (2ND SEC_KEY) are programmed in a second memory block among the plurality of memory blocks, the first memory block being different from the second memory block, wherein the memory controller (410, 410a) is configured to perform a process comprising the dummy program operation in response to the erase request in units of blocks; wherein a change of the first encrypted security key (1 ST ENC_SEC_KEY) and the second security key (2ND SEC_KEY) is performed separately from the encrypted write data (ENC_WDATA); and wherein the dummy program operation consists in invalidating data at the corresponding region by overwriting dummy data into the page where the second security key is stored. each of the plurality of nonvolatile memories includes a plurality of memory blocks, and the processor is configured to control the plurality of nonvolatile memories such that the encrypted write data (ENC_WDATA) is programmed in a first memory block among the plurality of memory blocks, and configured to control the plurality of nonvolatile memories such that the first encrypted security key and the second security key (2ND SEC_KEY) are programmed in a second memory block among the plurality of memory blocks, the first memory block being different from the second memory block, wherein the memory controller (410, 410a) is configured to perform a process comprising the dummy program operation in response to the erase request in units of blocks; wherein a change of the first encrypted security key (1 ST ENC_SEC_KEY) and the second security key (2ND SEC_KEY) is performed separately from the encrypted write data (ENC_WDATA); and wherein the dummy program operation consists in invalidating data at the corresponding region by overwriting dummy data into the page where the second security key is stored.