An extender, for transmitting a plurality of differential signals (D0±, D1±, D2±, CLK±) to a remote end, characterized in that the plurality of differential signals (D0±, D1±, D2±, CLK±) comprises a first differential data signal (D0±), a second differential data signal (D1±), and a differential clock signal (CLK±), the extender comprising: a transmitter, for converting a positive clock signal (CLK +) of the differential clock signal (CLK±) into a pair of positive clock signals (2CLK+) and converting a negative clock signal (CLK-) of the differential clock signal (CLK±) into a pair of negative clock signals (2CLK-) and for combining the converted pair of positive clock signals (2CLK+) with the first differential data signal (D0±) and combining the converted pair of negative clock signals (2CLK-) with the second differential data signal (D1±) to form a first composite differential signal (D0±CLK+) and a second composite differential signal (D1±CLK-) respectively; and a receiver, for extracting the first differential data signal (D0±) and the second differential data signal (D1±) from the first composite differential signal (D0±CLK+) and the second composite differential signal (D1±CLK-), the receiver comprising: a first impedance unit, for extracting the positive clock signal (CLK+) from the first composite differential signal (D0±CLK+); a second impedance unit, for extracting the negative clock signal (CLK-) from the second composite differential signal (D1±CLK-); and a recovery unit, coupled to the first impedance unit and the second impedance unit, for receiving the positive clock signal (CLK+) and the negative clock signal (CLK-) and forming the differential clock signal (CLK-) based on the positive clock signal (CLK+) and the negative clock signal (CLK-); wherein frequencies of the first differential data signal (D0±) and the second differential data signal (D1±) are ten times or more of a frequency of the differential clock signal (CLK±). a transmitter, for converting a positive clock signal (CLK +) of the differential clock signal (CLK±) into a pair of positive clock signals (2CLK+) and converting a negative clock signal (CLK-) of the differential clock signal (CLK±) into a pair of negative clock signals (2CLK-) and for combining the converted pair of positive clock signals (2CLK+) with the first differential data signal (D0±) and combining the converted pair of negative clock signals (2CLK-) with the second differential data signal (D1±) to form a first composite differential signal (D0±CLK+) and a second composite differential signal (D1±CLK-) respectively; and a receiver, for extracting the first differential data signal (D0±) and the second differential data signal (D1±) from the first composite differential signal (D0±CLK+) and the second composite differential signal (D1±CLK-), the receiver comprising: a first impedance unit, for extracting the positive clock signal (CLK+) from the first composite differential signal (D0±CLK+); a second impedance unit, for extracting the negative clock signal (CLK-) from the second composite differential signal (D1±CLK-); and a recovery unit, coupled to the first impedance unit and the second impedance unit, for receiving the positive clock signal (CLK+) and the negative clock signal (CLK-) and forming the differential clock signal (CLK-) based on the positive clock signal (CLK+) and the negative clock signal (CLK-); wherein frequencies of the first differential data signal (D0±) and the second differential data signal (D1±) are ten times or more of a frequency of the differential clock signal (CLK±). a first impedance unit, for extracting the positive clock signal (CLK+) from the first composite differential signal (D0±CLK+); a second impedance unit, for extracting the negative clock signal (CLK-) from the second composite differential signal (D1±CLK-); and a recovery unit, coupled to the first impedance unit and the second impedance unit, for receiving the positive clock signal (CLK+) and the negative clock signal (CLK-) and forming the differential clock signal (CLK-) based on the positive clock signal (CLK+) and the negative clock signal (CLK-); wherein frequencies of the first differential data signal (D0±) and the second differential data signal (D1±) are ten times or more of a frequency of the differential clock signal (CLK±).