A system, comprising: a multi-chip demodulation module, DEMOD; a video processing system-on-chip, SoC; and a multiplexed transport interface configured to communicate a plurality of demodulated video data streams as a multiplexed data signal, the multiplexed transport interface utilized between the multi-chip demodulation module, and the video processing SoC, the multiplexed transport interface including circuitry configured to communicate: a clock signal; a synchronization signal; a multiplexed data signal including packets of multiplexed demodulated video data; a timeslot count increment signal utilized to increment an SoC-side timestamp counter and a DEMOD-side timestamp counter; and a timeslot count reset signal utilized to reset the SoC-side timestamp counter and the DEMOD-side timestamp counter, wherein the system is configured to: generate timestamps based on the DEMOD-side counter in the multi-chip demodulation module, timestamp packets communicated via the multiplexed transport interface with the generated timestamps, receive said timestamp packets at the video processing SoC and compare values of the SoC-side timestamp counter with timestamps in received packets; synchronize operations of the SoC-side timestamp counter with the DEMOD-side timestamp counter by way of the timeslot count reset signal received by the multi-chip demodulation module DEMOD from the video processing SoC. a multi-chip demodulation module, DEMOD; a video processing system-on-chip, SoC; and a multiplexed transport interface configured to communicate a plurality of demodulated video data streams as a multiplexed data signal, the multiplexed transport interface utilized between the multi-chip demodulation module, and the video processing SoC, the multiplexed transport interface including circuitry configured to communicate: a clock signal; a synchronization signal; a multiplexed data signal including packets of multiplexed demodulated video data; a timeslot count increment signal utilized to increment an SoC-side timestamp counter and a DEMOD-side timestamp counter; and a timeslot count reset signal utilized to reset the SoC-side timestamp counter and the DEMOD-side timestamp counter, a clock signal; a synchronization signal; a multiplexed data signal including packets of multiplexed demodulated video data; a timeslot count increment signal utilized to increment an SoC-side timestamp counter and a DEMOD-side timestamp counter; and a timeslot count reset signal utilized to reset the SoC-side timestamp counter and the DEMOD-side timestamp counter, wherein the system is configured to: generate timestamps based on the DEMOD-side counter in the multi-chip demodulation module, timestamp packets communicated via the multiplexed transport interface with the generated timestamps, receive said timestamp packets at the video processing SoC and compare values of the SoC-side timestamp counter with timestamps in received packets; synchronize operations of the SoC-side timestamp counter with the DEMOD-side timestamp counter by way of the timeslot count reset signal received by the multi-chip demodulation module DEMOD from the video processing SoC. generate timestamps based on the DEMOD-side counter in the multi-chip demodulation module, timestamp packets communicated via the multiplexed transport interface with the generated timestamps, receive said timestamp packets at the video processing SoC and compare values of the SoC-side timestamp counter with timestamps in received packets; synchronize operations of the SoC-side timestamp counter with the DEMOD-side timestamp counter by way of the timeslot count reset signal received by the multi-chip demodulation module DEMOD from the video processing SoC.