A method of programming a memory cell using punch-through assisted hot holes injection wherein the memory cell comprises a memory transistor, the memory transistor including a source region, a drain region, a channel in between the first source/drain region and the second source/drain region, and a gate stack covering the channel extending from the first source/drain region to the second source/drain region, wherein the gate stack comprises a charge trapping structure extending from the first source/drain region to the second source/drain region, the memory cell further comprising a first electric terminal being connected to the first source/drain region, a second electric terminal being connected to the gate stack, and a third electric terminal being connected to the second source/drain region, the method comprising: applying a first electric potential to the first electric terminal and a third electric potential, different from the first electric potential, to the third electric terminal of the memory cell to accelerate first charge carriers of a first type of conductivity from the first source/drain region to the second source/drain region to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers; applying a second electric potential to the second electric terminal of the memory cell to accelerate the second charge carriers to thereby inject the second charge carriers in the charge trapping structure of the memory cell; wherein the first charge carriers are electrons, the second charge carriers are holes, the first electric potential is a positive electric potential with respect to a ground potential having an absolute value in a range between 2 V and 6V, the second electrical potential is a negative electric potential with respect to a ground potential having an absolute value in a range between 3 V and 10 V, and the charge trapping structure is made of an electrically insulating material and comprises one of the group consisting of a silicon nitride layer, a silicon nitride layer of an ONO layer sequence, an ONO layer sequence comprising a high-k material, and a nanocrystal structure. applying a first electric potential to the first electric terminal and a third electric potential, different from the first electric potential, to the third electric terminal of the memory cell to accelerate first charge carriers of a first type of conductivity from the first source/drain region to the second source/drain region to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers; applying a second electric potential to the second electric terminal of the memory cell to accelerate the second charge carriers to thereby inject the second charge carriers in the charge trapping structure of the memory cell; wherein the first charge carriers are electrons, the second charge carriers are holes, the first electric potential is a positive electric potential with respect to a ground potential having an absolute value in a range between 2 V and 6V, the second electrical potential is a negative electric potential with respect to a ground potential having an absolute value in a range between 3 V and 10 V, and the charge trapping structure is made of an electrically insulating material and comprises one of the group consisting of a silicon nitride layer, a silicon nitride layer of an ONO layer sequence, an ONO layer sequence comprising a high-k material, and a nanocrystal structure.