A delay circuit comprising: - an input line to which an analog input signal (Vin) is input; - a plurality of analog signal memory devices; - an output line from which an analog output signal is output; - a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices; - a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line; and - a clock generation part that generates sampling switch control signals for respectively controlling the plurality of sampling switches and output switch control signals for respectively controlling the plurality of output switches, said clock generation part including a reference clock with a clock cycle (Tclk), the delay circuit delaying signals by controlling the plurality of sampling switches to accumulate the analog input signal (Vin) in the plurality of analog signal memory devices and controlling the plurality of output switches to output the signals accumulated in the plurality of analog signal memory devices to the output line, wherein a phase of the plurality of sampling switch control signals are arranged be shifted with respect to a phase of the plurality of output switch control signals, wherein the clock generation part includes: - a phase delay control part configured to generate a small delay time (Tdp) less than the clock cycle (Tclk) - a plurality of series-connected buffer circuits each introducing a phase shift amounting to one cycle of the reference clock or less such that a plurality of signals with different phase shifted little by little with respect to the phase of the reference clock are generated by the buffer circuits; and - a first selector that selects one signal from respective outputs of the plurality of buffer circuits (305a - d), wherein a phase delay signal of single phase of the plurality of signals with different phase is selected by the first selector, said phase delay signal being delayed by said small delay time (Tdm) due to the accumulated phase shifts introduced by said series-connected buffer circuits (305a - d), and the sampling switch control signals (S108a - d) are generated based on the phase delay signals, wherein the clock generation part further comprising - a first plurality of series-connected delay elements (308a - d), wherein the phase delay signal is used as input to the first delay element in the plurality of series-connected delay elements (308a - d), and output signals of the first plurality of series-connected delay elements (308a - d) are used as the plurality of sampling switch control signals (S108a - d); - a pulse generation part that generates pulse by dividing the reference clock; - a second plurality of series-connected delay elements (302a-302d); and - a second selector that selects one of outputs of the second plurality of series-connected delay elements (302a - 302d), wherein: - the second plurality of series-connected delay elements (302a - 302d) generate signals delayed by predetermined clock cycles, and - the signal selected by the second selector is input to the buffer circuits (305a - 305d). - an input line to which an analog input signal (Vin) is input; - a plurality of analog signal memory devices; - an output line from which an analog output signal is output; - a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices; - a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line; and - a clock generation part that generates sampling switch control signals for respectively controlling the plurality of sampling switches and output switch control signals for respectively controlling the plurality of output switches, said clock generation part including a reference clock with a clock cycle (Tclk), - a phase delay control part configured to generate a small delay time (Tdp) less than the clock cycle (Tclk) - a plurality of series-connected buffer circuits each introducing a phase shift amounting to one cycle of the reference clock or less such that a plurality of signals with different phase shifted little by little with respect to the phase of the reference clock are generated by the buffer circuits; and - a first selector that selects one signal from respective outputs of the plurality of buffer circuits (305a - d), - a first plurality of series-connected delay elements (308a - d), wherein the phase delay signal is used as input to the first delay element in the plurality of series-connected delay elements (308a - d), and output signals of the first plurality of series-connected delay elements (308a - d) are used as the plurality of sampling switch control signals (S108a - d); - a pulse generation part that generates pulse by dividing the reference clock; - a second plurality of series-connected delay elements (302a-302d); and - a second selector that selects one of outputs of the second plurality of series-connected delay elements (302a - 302d), - the second plurality of series-connected delay elements (302a - 302d) generate signals delayed by predetermined clock cycles, and - the signal selected by the second selector is input to the buffer circuits (305a - 305d).