A memory system comprising: a semiconductor memory device including a first group of memory cells (111_0) and a second group of memory cells (111_1), first (116_0), second (117_0), and third (118_0) caches for storing data before the data are written into the memory cells of the first group, and fourth (116_1), fifth (117_1), and sixth (118_1) caches for storing data before the data are written into the memory cells of the second group; and a memory controller configured to issue commands to the semiconductor memory device, the commands including a first command issued with address data and write data to store the write data in the first (116_0) or fourth (116_1) cache in accordance with the address data, and a second command issued with address data and write data to store the write data in the first (116_0) or fourth (116_1) cache in accordance with the address data and then transfer the write data in the first cache (116_0) to one of the second (117_0) and third (118_0) caches and the write data in the fourth cache to one of the fifth (117_1) and sixth (118_1) caches, wherein the memory controller is configured to issue a third command to write data in the first (116_0) or fourth (116_1) cache in accordance with the address data and then transfer the write data in the first (116_0) cache to one of the second (117_0) and third (118_0) caches and the write data in the fourth (116_1) cache to one of the fifth (117_1) and sixth (118_1) caches and to write the data stored in the second (117_0) and third (118_0) caches into the first group of memory cells (111_0) and the data stored in the fifth (117_1) and sixth (118_1) caches into the second group of memory cells (111_1), and the memory controller is configured to issue the first and second commands addressing different groups of memory cells in a interleaved fashion. a semiconductor memory device including a first group of memory cells (111_0) and a second group of memory cells (111_1), first (116_0), second (117_0), and third (118_0) caches for storing data before the data are written into the memory cells of the first group, and fourth (116_1), fifth (117_1), and sixth (118_1) caches for storing data before the data are written into the memory cells of the second group; and a first group of memory cells (111_0) and a second group of memory cells (111_1), first (116_0), second (117_0), and third (118_0) caches for storing data before the data are written into the memory cells of the first group, and fourth (116_1), fifth (117_1), and sixth (118_1) caches for storing data before the data are written into the memory cells of the second group; and a memory controller configured to issue commands to the semiconductor memory device, the commands including a first command issued with address data and write data to store the write data in the first (116_0) or fourth (116_1) cache in accordance with the address data, and a second command issued with address data and write data to store the write data in the first (116_0) or fourth (116_1) cache in accordance with the address data and then transfer the write data in the first cache (116_0) to one of the second (117_0) and third (118_0) caches and the write data in the fourth cache to one of the fifth (117_1) and sixth (118_1) caches, wherein the memory controller is configured to issue a third command to write data in the first (116_0) or fourth (116_1) cache in accordance with the address data and then transfer the write data in the first (116_0) cache to one of the second (117_0) and third (118_0) caches and the write data in the fourth (116_1) cache to one of the fifth (117_1) and sixth (118_1) caches and to write the data stored in the second (117_0) and third (118_0) caches into the first group of memory cells (111_0) and the data stored in the fifth (117_1) and sixth (118_1) caches into the second group of memory cells (111_1), and the memory controller is configured to issue the first and second commands addressing different groups of memory cells in a interleaved fashion.