A scanline driver (10a, 10b) comprising: a driving circuit (100a; 100b) including a plurality of driving transistor units (110, 120, 130, 140, 150, 160, 170) and further including a plurality of reset transistors (180, 190) for resetting a first and a second driving node to a supply voltage based on a set signal, the plurality of driving transistor units (110, 120, 130, 140, 150, 160, 170) and the plurality of reset transistors (180, 190) being configured to provide a first driving signal to the first driving node and a second driving signal to the second driving node based on a scan input signal (S[N-1]) and a plurality of clock signals; and a buffer circuit (300a; 300b) configured to generate a scan output signal (S) based on the first and second driving signals, wherein the buffer circuit (300a; 300b) includes a plurality of buffer transistor units (310,320),wherein each of the driving transistor units (110,120,130,140,150,160,170) and the buffer transistor units (310,320) includes a floating gate transistor unit, wherein the floating gate transistor unit includes: a floating gate N-MOS transistor comprising a floating gate electrode; and a transferring transistor for transferring, to the floating gate electrode, a voltage corresponding to a second logic low level (VGL') lower than a first logic low level corresponding to a supply voltage applied to the reset transistors (180,190), the transferring transistor having a first terminal and a second terminal, wherein the floating gate electrode is electrically connected to the first terminal of the transferring transistor and the second terminal of the transferring transistor is configured to receive the voltage corresponding to the second logic low level (VGL'), and wherein the transferring transistor is configured to be turned on based on the set signal. a driving circuit (100a; 100b) including a plurality of driving transistor units (110, 120, 130, 140, 150, 160, 170) and further including a plurality of reset transistors (180, 190) for resetting a first and a second driving node to a supply voltage based on a set signal, the plurality of driving transistor units (110, 120, 130, 140, 150, 160, 170) and the plurality of reset transistors (180, 190) being configured to provide a first driving signal to the first driving node and a second driving signal to the second driving node based on a scan input signal (S[N-1]) and a plurality of clock signals; and a buffer circuit (300a; 300b) configured to generate a scan output signal (S) based on the first and second driving signals, wherein the buffer circuit (300a; 300b) includes a plurality of buffer transistor units (310,320),wherein each of the driving transistor units (110,120,130,140,150,160,170) and the buffer transistor units (310,320) includes a floating gate transistor unit, wherein the floating gate transistor unit includes: a floating gate N-MOS transistor comprising a floating gate electrode; and a transferring transistor for transferring, to the floating gate electrode, a voltage corresponding to a second logic low level (VGL') lower than a first logic low level corresponding to a supply voltage applied to the reset transistors (180,190), the transferring transistor having a first terminal and a second terminal, wherein the floating gate electrode is electrically connected to the first terminal of the transferring transistor and the second terminal of the transferring transistor is configured to receive the voltage corresponding to the second logic low level (VGL'), and wherein the transferring transistor is configured to be turned on based on the set signal.