A semiconductor device comprising: a plurality of CPUs (101-104; 200); a router circuit (105; 300); a thread control circuit connected to the router circuit (105; 300) through a first bus; and an external device controller connected to the router circuit (105; 300) through a second bus, wherein each of the plurality of CPUs (101-104; 200) includes: a first wireless circuit which includes a first antenna circuit, a third antenna circuit, a first demodulation circuit, a first modulation circuit, a first power supply circuit, and a second power supply circuit and a CPU core (108-111; 201) which includes a control circuit, an arithmetic circuit, a cache memory, and a general purpose register, wherein the first power supply circuit is configured to generate a power supply voltage from a first wireless signal received by the first antenna circuit, wherein the second power supply circuit includes a step-up circuit and is configured to generate a power supply voltage from a second wireless signal received by the third antenna circuit, wherein the router circuit (105; 300) includes a data processing circuit and a second wireless circuit which includes a second antenna circuit, a second demodulation circuit, and a second modulation circuit, wherein the first wireless circuit and the second wireless circuit are configured to transmit and receive data between a CPU (101-104; 200) and the router circuit (105; 300) wirelessly, wherein the first wireless circuit is configured to transmit data to the second wireless circuit by a backscattering method, wherein the data processing circuit is configured to process and store first data to be transmitted to or received from each of the plurality of CPUs (101-104; 200), second data to be transmitted to or received from the thread control circuit, and third data to be transmitted to or received from the external device controller, wherein the thread control circuit is configured to allocate an instruction to be executed by a CPU core (108-111; 201) to the CPU core (108-111; 201), and wherein the external device controller is configured to transmit and receive data to and from an external device which is connected through an external data input line and an external data output line. a plurality of CPUs (101-104; 200); a router circuit (105; 300); a thread control circuit connected to the router circuit (105; 300) through a first bus; and an external device controller connected to the router circuit (105; 300) through a second bus, wherein each of the plurality of CPUs (101-104; 200) includes: a first wireless circuit which includes a first antenna circuit, a third antenna circuit, a first demodulation circuit, a first modulation circuit, a first power supply circuit, and a second power supply circuit and a CPU core (108-111; 201) which includes a control circuit, an arithmetic circuit, a cache memory, and a general purpose register, wherein the first power supply circuit is configured to generate a power supply voltage from a first wireless signal received by the first antenna circuit, wherein the second power supply circuit includes a step-up circuit and is configured to generate a power supply voltage from a second wireless signal received by the third antenna circuit, a first wireless circuit which includes a first antenna circuit, a third antenna circuit, a first demodulation circuit, a first modulation circuit, a first power supply circuit, and a second power supply circuit and a CPU core (108-111; 201) which includes a control circuit, an arithmetic circuit, a cache memory, and a general purpose register, wherein the first power supply circuit is configured to generate a power supply voltage from a first wireless signal received by the first antenna circuit, wherein the second power supply circuit includes a step-up circuit and is configured to generate a power supply voltage from a second wireless signal received by the third antenna circuit, wherein the router circuit (105; 300) includes a data processing circuit and a second wireless circuit which includes a second antenna circuit, a second demodulation circuit, and a second modulation circuit, wherein the first wireless circuit and the second wireless circuit are configured to transmit and receive data between a CPU (101-104; 200) and the router circuit (105; 300) wirelessly, wherein the first wireless circuit is configured to transmit data to the second wireless circuit by a backscattering method, wherein the data processing circuit is configured to process and store first data to be transmitted to or received from each of the plurality of CPUs (101-104; 200), second data to be transmitted to or received from the thread control circuit, and third data to be transmitted to or received from the external device controller, wherein the thread control circuit is configured to allocate an instruction to be executed by a CPU core (108-111; 201) to the CPU core (108-111; 201), and wherein the external device controller is configured to transmit and receive data to and from an external device which is connected through an external data input line and an external data output line.