A memory circuit configured to increase the speed of memory test operations, the memory circuit comprising: at least one bit cell comprising a spin-orbit-torque magnetic tunnel junction including two ferromagnetic layers (12, 16) and a metal electrode; the memory circuit being characterised by further comprising three electronic switches (N1, N2, N3), wherein: one ferromagnetic layer has a fixed magnetic orientation and the other ferromagnetic layer has a changeable magnetic orientation that is configured to be changed by a current flow through the metal electrode; and the three electronic switches (N1, N2, N3) comprise a write access electronic switch configured to control the access to the bit cell during write operations, a read access electronic switch configured to control the access to the bit cell during read operations and a read-and-write access electronic switch configured to control the access to the bit cell during both read and write operations; and at least one logic circuit comprising three control pins, each pin configured to receive a single input signal, and a plurality of output pins, each output pin connected to a corresponding electronic switch of the three electronic switches (N1, N2, N3), wherein one of the three control pins is a test pin configured to enable or disable simultaneous read and write operations on the at least one bit cell, wherein simultaneous read and write operations are configured to be performed in the same clock cycle and the read access is faster than the write access so that the read operation reads a bit value stored in the at least one bit cell by a previous write operation and not the bit value that is being written by the simultaneous write operation. at least one bit cell comprising a spin-orbit-torque magnetic tunnel junction including two ferromagnetic layers (12, 16) and a metal electrode; the memory circuit being characterised by further comprising three electronic switches (N1, N2, N3), wherein: one ferromagnetic layer has a fixed magnetic orientation and the other ferromagnetic layer has a changeable magnetic orientation that is configured to be changed by a current flow through the metal electrode; and the three electronic switches (N1, N2, N3) comprise a write access electronic switch configured to control the access to the bit cell during write operations, a read access electronic switch configured to control the access to the bit cell during read operations and a read-and-write access electronic switch configured to control the access to the bit cell during both read and write operations; and one ferromagnetic layer has a fixed magnetic orientation and the other ferromagnetic layer has a changeable magnetic orientation that is configured to be changed by a current flow through the metal electrode; and the three electronic switches (N1, N2, N3) comprise a write access electronic switch configured to control the access to the bit cell during write operations, a read access electronic switch configured to control the access to the bit cell during read operations and a read-and-write access electronic switch configured to control the access to the bit cell during both read and write operations; and at least one logic circuit comprising three control pins, each pin configured to receive a single input signal, and a plurality of output pins, each output pin connected to a corresponding electronic switch of the three electronic switches (N1, N2, N3), wherein one of the three control pins is a test pin configured to enable or disable simultaneous read and write operations on the at least one bit cell, wherein simultaneous read and write operations are configured to be performed in the same clock cycle and the read access is faster than the write access so that the read operation reads a bit value stored in the at least one bit cell by a previous write operation and not the bit value that is being written by the simultaneous write operation.