A display apparatus comprising: a display panel comprising a gate line (GLA, GLB1) and a data line; and a plurality of flexible printed circuit boards (220, 220A, 220B, 220C, 220D) connected to one side of the display panel, wherein each of the plurality of flexible printed circuit boards (220, 220A, 220B, 220C, 220D) comprises: a gate driving chip configured to apply a gate signal to the gate line (GLA, GLB1), and a source driving chip configured to apply a data voltage to the data line characterized in that each of the plurality of flexible printed circuit boards (220, 220A, 220B, 220C, 220D) further comprises: a first layer (222, 222A, 222B, 222C) on which a first signal transmitting line group (ST1-ST4) connected to the source driving chip to transmit the data voltage to the data line is disposed; a second layer (224, 224a, 224b, 224c) on which a second signal transmitting line group (GT1-GT2) connected to the gate driving chip to transmit the gate signal to the gate line (GLA, GLB1) is disposed; and a pad part (P1-P6) disposed on the second layer (224, 224a, 224b, 224c), wherein one of the gate driving chip and the source driving chip is connected to a first group of the pad part (P1-P6) through the first signal transmitting line group (ST1-ST4), and the other of the gate driving chip and the source driving chip is connected to a second group of the pad part (P1-P6) through the second signal transmitting line group (GT1-GT2); and the first signal transmitting line group (ST1-ST4) crosses the second signal transmitting line group (GT1-GT2) in a plan view, wherein the second signal transmitting line group (GT1-GT2) is connected to the pad part (P1-P6), crossing the first signal transmitting line group (ST1-ST4). a display panel comprising a gate line (GLA, GLB1) and a data line; and a plurality of flexible printed circuit boards (220, 220A, 220B, 220C, 220D) connected to one side of the display panel, wherein each of the plurality of flexible printed circuit boards (220, 220A, 220B, 220C, 220D) comprises: a gate driving chip configured to apply a gate signal to the gate line (GLA, GLB1), and a source driving chip configured to apply a data voltage to the data line characterized in that each of the plurality of flexible printed circuit boards (220, 220A, 220B, 220C, 220D) further comprises: a first layer (222, 222A, 222B, 222C) on which a first signal transmitting line group (ST1-ST4) connected to the source driving chip to transmit the data voltage to the data line is disposed; a second layer (224, 224a, 224b, 224c) on which a second signal transmitting line group (GT1-GT2) connected to the gate driving chip to transmit the gate signal to the gate line (GLA, GLB1) is disposed; and a pad part (P1-P6) disposed on the second layer (224, 224a, 224b, 224c), wherein one of the gate driving chip and the source driving chip is connected to a first group of the pad part (P1-P6) through the first signal transmitting line group (ST1-ST4), and the other of the gate driving chip and the source driving chip is connected to a second group of the pad part (P1-P6) through the second signal transmitting line group (GT1-GT2); and the first signal transmitting line group (ST1-ST4) crosses the second signal transmitting line group (GT1-GT2) in a plan view, wherein the second signal transmitting line group (GT1-GT2) is connected to the pad part (P1-P6), crossing the first signal transmitting line group (ST1-ST4). a gate driving chip configured to apply a gate signal to the gate line (GLA, GLB1), and a source driving chip configured to apply a data voltage to the data line