A delay circuit, comprising: a first NMOS transistor including a source connected to a ground terminal, and a gate to which an input signal is input; a capacitor connected between a drain of the first NMOS transistor and the ground terminal; a constant current circuit (115,116) configured to cause a current to flow through the capacitor; a first inverter including an input connected to an output terminal of the constant current circuit; a second inverter including an input connected to an output terminal of the first inverter; a first depletion type NMOS transistor including a gate and a back gate each connected to the ground terminal, and a source connected to the drain of the first NMOS transistor; a second NMOS transistor including a source connected to the ground terminal, a drain connected to the output terminal of the constant current circuit, and a gate to which the input signal is input; a third NMOS transistor including a gate connected to the output terminal of the first inverter, a source and a back gate each connected to a drain of the first depletion type NMOS transistor, and a drain connected to the output terminal of the constant current circuit; and a fourth NMOS transistor including a source connected to the ground terminal, a gate connected to an output terminal of the second inverter, and a drain connected to the drain of the first NMOS transistor, the constant current circuit comprising: a second depletion type NMOS transistor; and a resistor connected between each of a gate and a back gate of the second depletion type NMOS transistor and a source of the second depletion type NMOS transistor. a first NMOS transistor including a source connected to a ground terminal, and a gate to which an input signal is input; a capacitor connected between a drain of the first NMOS transistor and the ground terminal; a constant current circuit (115,116) configured to cause a current to flow through the capacitor; a first inverter including an input connected to an output terminal of the constant current circuit; a second inverter including an input connected to an output terminal of the first inverter; a first depletion type NMOS transistor including a gate and a back gate each connected to the ground terminal, and a source connected to the drain of the first NMOS transistor; a second NMOS transistor including a source connected to the ground terminal, a drain connected to the output terminal of the constant current circuit, and a gate to which the input signal is input; a third NMOS transistor including a gate connected to the output terminal of the first inverter, a source and a back gate each connected to a drain of the first depletion type NMOS transistor, and a drain connected to the output terminal of the constant current circuit; and a fourth NMOS transistor including a source connected to the ground terminal, a gate connected to an output terminal of the second inverter, and a drain connected to the drain of the first NMOS transistor, the constant current circuit comprising: a second depletion type NMOS transistor; and a resistor connected between each of a gate and a back gate of the second depletion type NMOS transistor and a source of the second depletion type NMOS transistor. a second depletion type NMOS transistor; and a resistor connected between each of a gate and a back gate of the second depletion type NMOS transistor and a source of the second depletion type NMOS transistor.