A method of processing instructions in a computer system comprising a processor and a co-processor, wherein the processor includes a co-processor interface, the processor being coupled to the co-processor, the method comprising: (a) processing instructions in the processor, in an instruction pipeline wherein instructions are processed sequentially by an instruction fetch stage (310, 510), an instruction decode stage (320, 520), an instruction execute stage (330, 530), a memory access stage (340, 540) wherein in the memory access stage interrupts or exceptions are raised and a result write-back stage (350,550); and (b) if a co-processor instruction is received by the processor, performing the steps of: (b)(i) providing the co-processor instruction to the co-processor interface during the instruction execute stage (330, 530) and holding the co-processor instruction within a buffer located within the co-processor interface; (b)(ii) if there is an interrupt or exception raised before the co-processor instruction reaches the memory access stage (340, 540), cancelling the co-processor instruction in the co-processor interface before it is sent to the co-processor; and (b)(iii) if no interrupt or exception is raised before the co-processor instruction reaches the memory access stage (340, 540), sending the co-processor instruction from the co-processor interface to the co-processor in the memory access stage (340, 540). (a) processing instructions in the processor, in an instruction pipeline wherein instructions are processed sequentially by an instruction fetch stage (310, 510), an instruction decode stage (320, 520), an instruction execute stage (330, 530), a memory access stage (340, 540) wherein in the memory access stage interrupts or exceptions are raised and a result write-back stage (350,550); and (b) if a co-processor instruction is received by the processor, performing the steps of: (b)(i) providing the co-processor instruction to the co-processor interface during the instruction execute stage (330, 530) and holding the co-processor instruction within a buffer located within the co-processor interface; (b)(ii) if there is an interrupt or exception raised before the co-processor instruction reaches the memory access stage (340, 540), cancelling the co-processor instruction in the co-processor interface before it is sent to the co-processor; and (b)(iii) if no interrupt or exception is raised before the co-processor instruction reaches the memory access stage (340, 540), sending the co-processor instruction from the co-processor interface to the co-processor in the memory access stage (340, 540). (b)(i) providing the co-processor instruction to the co-processor interface during the instruction execute stage (330, 530) and holding the co-processor instruction within a buffer located within the co-processor interface; (b)(ii) if there is an interrupt or exception raised before the co-processor instruction reaches the memory access stage (340, 540), cancelling the co-processor instruction in the co-processor interface before it is sent to the co-processor; and (b)(iii) if no interrupt or exception is raised before the co-processor instruction reaches the memory access stage (340, 540), sending the co-processor instruction from the co-processor interface to the co-processor in the memory access stage (340, 540).