A switched-capacitor converter comprising: an input for coupling to an input power supply; an output for providing power to a load; a first switch stage comprising a first switch and a second switch (Q 1, Q 2) connected in series and interposed between the input and the output, the first switch (Q 1) comprising a first terminal that is coupled to the input, a second terminal that is coupled to the second switch (Q 2), and a control terminal; a first capacitor (C 1) coupled to the second terminal of the first switch; a controller operable to generate a first control signal (V PWM_QA) for controlling the first switch (Q 1) and a second control signal (V PWM_QB) for controlling the second switch (Q 2), such that the first and second switches (Q 1, Q 2) are alternately switched; an input activity detector operable to generate an input activation signal (V EN_RAMP) based upon an input voltage (V IN) at the input, wherein the input activation signal (V EN_RAMP) indicates that power is being supplied at the input; a voltage ramp generator operable to generate a ramp voltage (V RAMP) responsive to receiving the input activation signal (V EN_RAMP), wherein the ramp voltage (V RAMP) increases from a minimum ramp voltage to a maximum ramp voltage, and the voltage ramp generator limits a slope of the ramp voltage (V RAMP) to be less than a slope of the input voltage (V IN) occurring at the activation of the input (V IN) voltage; and a soft-start circuit operable to generate a control signal for the first switch based upon the ramp voltage (V RAMP), in order to ramp up the voltage at the second terminal of the first switch such that the power rating of the first switch is not exceeded. an input for coupling to an input power supply; an output for providing power to a load; a first switch stage comprising a first switch and a second switch (Q 1, Q 2) connected in series and interposed between the input and the output, the first switch (Q 1) comprising a first terminal that is coupled to the input, a second terminal that is coupled to the second switch (Q 2), and a control terminal; a first capacitor (C 1) coupled to the second terminal of the first switch; a controller operable to generate a first control signal (V PWM_QA) for controlling the first switch (Q 1) and a second control signal (V PWM_QB) for controlling the second switch (Q 2), such that the first and second switches (Q 1, Q 2) are alternately switched; an input activity detector operable to generate an input activation signal (V EN_RAMP) based upon an input voltage (V IN) at the input, wherein the input activation signal (V EN_RAMP) indicates that power is being supplied at the input; a voltage ramp generator operable to generate a ramp voltage (V RAMP) responsive to receiving the input activation signal (V EN_RAMP), wherein the ramp voltage (V RAMP) increases from a minimum ramp voltage to a maximum ramp voltage, and the voltage ramp generator limits a slope of the ramp voltage (V RAMP) to be less than a slope of the input voltage (V IN) occurring at the activation of the input (V IN) voltage; and a soft-start circuit operable to generate a control signal for the first switch based upon the ramp voltage (V RAMP), in order to ramp up the voltage at the second terminal of the first switch such that the power rating of the first switch is not exceeded.