A differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory, the differential sensing circuit comprising: a dynamic voltage reference generating unit, coupled to an input voltage, for receiving a setting signal to generate the dynamic voltage reference; and a differential sensing amplifying unit, coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly; characterized in that the dynamic voltage reference generating unit comprises: a first switch element (212, 312), having a control terminal, a first terminal coupled to the input voltage, and a second terminal coupled to the differential sensing amplifying unit; and a second switch element (214, 314), having a control terminal, a first terminal coupled to the control terminal of the first switch element (212, 312), and a second terminal; a third switch element (216, 316), having a control terminal coupled to the setting signal, a first terminal coupled to the second terminal of the first switch element (212, 312) and the differential sensing amplifying unit, and a second terminal; and an inverted phase delay unit (218, 318), for generating at least an inverted phase delay signal to the dynamic voltage reference generating unit, wherein the inverted phase delay unit (218, 318) has an input terminal coupled to the second terminal of the second switch element (214, 314) and the second terminal of the third switch element (216, 316), and an output terminal coupled to the control terminal of the second switch element (214, 314). a dynamic voltage reference generating unit, coupled to an input voltage, for receiving a setting signal to generate the dynamic voltage reference; and a differential sensing amplifying unit, coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly; characterized in that the dynamic voltage reference generating unit comprises: a first switch element (212, 312), having a control terminal, a first terminal coupled to the input voltage, and a second terminal coupled to the differential sensing amplifying unit; and a second switch element (214, 314), having a control terminal, a first terminal coupled to the control terminal of the first switch element (212, 312), and a second terminal; a third switch element (216, 316), having a control terminal coupled to the setting signal, a first terminal coupled to the second terminal of the first switch element (212, 312) and the differential sensing amplifying unit, and a second terminal; and an inverted phase delay unit (218, 318), for generating at least an inverted phase delay signal to the dynamic voltage reference generating unit, wherein the inverted phase delay unit (218, 318) has an input terminal coupled to the second terminal of the second switch element (214, 314) and the second terminal of the third switch element (216, 316), and an output terminal coupled to the control terminal of the second switch element (214, 314). a first switch element (212, 312), having a control terminal, a first terminal coupled to the input voltage, and a second terminal coupled to the differential sensing amplifying unit; and a second switch element (214, 314), having a control terminal, a first terminal coupled to the control terminal of the first switch element (212, 312), and a second terminal; a third switch element (216, 316), having a control terminal coupled to the setting signal, a first terminal coupled to the second terminal of the first switch element (212, 312) and the differential sensing amplifying unit, and a second terminal; and an inverted phase delay unit (218, 318), for generating at least an inverted phase delay signal to the dynamic voltage reference generating unit, wherein the inverted phase delay unit (218, 318) has an input terminal coupled to the second terminal of the second switch element (214, 314) and the second terminal of the third switch element (216, 316), and an output terminal coupled to the control terminal of the second switch element (214, 314).