A computing system, comprising: a memory controller including a first queue scheduler configured to issue, in accordance with a first timing scheme, one or more requests in the first queue scheduler to a first memory set via a first memory set interface and over a common channel; a second queue scheduler configured to issue, in accordance with a second timing scheme, one or more requests in the second queue scheduler to a second memory set via a second memory set interface and over the common channel; a clock, wherein the first timing scheme defines a first number of cycles of the clock in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface, and the second timing scheme defines a second number of cycles of the clock in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface; and a global scheduler configured to receive information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler; and modify at least one of the first timing scheme or the second timing scheme based on the information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler, by adjusting at least one of the first number of cycles of the clock in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface or adjusting the second number of cycles of the clock in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface. a first queue scheduler configured to issue, in accordance with a first timing scheme, one or more requests in the first queue scheduler to a first memory set via a first memory set interface and over a common channel; a second queue scheduler configured to issue, in accordance with a second timing scheme, one or more requests in the second queue scheduler to a second memory set via a second memory set interface and over the common channel; a clock, wherein the first timing scheme defines a first number of cycles of the clock in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface, and the second timing scheme defines a second number of cycles of the clock in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface; and a global scheduler configured to receive information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler; and modify at least one of the first timing scheme or the second timing scheme based on the information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler, by adjusting at least one of the first number of cycles of the clock in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface or adjusting the second number of cycles of the clock in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface. receive information about one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler; and modify at least one of the first timing scheme or the second timing scheme based on the information about the one or more requests to be included in at least one of the first queue scheduler or the second queue scheduler, by adjusting at least one of the first number of cycles of the clock in which the one or more requests in the first queue scheduler are to be issued to the first memory set via the first memory set interface or adjusting the second number of cycles of the clock in which the one or more requests in the second queue scheduler are to be issued to the second memory set via the second memory set interface.