A method of operating a modular embedded multi-level converter, MEMC,, the MEMC comprising: a positive direct current, DC, bus; a negative DC bus; a first phase portion comprising: a first switch stack with a plurality of switches (T 1 -T 4), a midpoint of the first switch stack being coupled to a midpoint node, and a first phase branch with a plurality of switching units (S 1 -S 4); a second phase portion comprising: a second switch stack with a plurality of switches T 5 -T 8), a midpoint of the second switch stack being coupled to the midpoint node, and a second phase branch with a plurality of switching units (S 5 -S 8); and a third phase portion comprising: a third switch stack with a plurality of switches (T 9 -T 12), a midpoint of the third switch stack being coupled to the midpoint node, and a third phase branch with a plurality of switching units (S 9 -S 12); the method comprising the steps of: controlling the plurality of switches (T 1 -T 12) of the first, second and third switch stacks (206, 208, 210), e.g., commutating a plurality of thyristors or insulated gate bipolar transistors, IGBTs, of the MEMC to: couple the first phase branch between the positive DC bus and the midpoint node; couple the second phase branch between the midpoint node and the negative DC bus; and couple opposing ends of the third phase branch to the midpoint node; characterised by: regulating an alternating current, AC, component of a midpoint voltage, at the midpoint node, to balance AC current loops among the first phase branch, second phase branch, and the third phase branch; and regulating a DC component of the midpoint voltage to balance DC voltages distributed among the first phase branch and the second phase branch. a positive direct current, DC, bus; a negative DC bus; a first phase portion comprising: a first switch stack with a plurality of switches (T 1 -T 4), a midpoint of the first switch stack being coupled to a midpoint node, and a first phase branch with a plurality of switching units (S 1 -S 4); a first switch stack with a plurality of switches (T 1 -T 4), a midpoint of the first switch stack being coupled to a midpoint node, and a first phase branch with a plurality of switching units (S 1 -S 4); a second phase portion comprising: a second switch stack with a plurality of switches T 5 -T 8), a midpoint of the second switch stack being coupled to the midpoint node, and a second phase branch with a plurality of switching units (S 5 -S 8); and a second switch stack with a plurality of switches T 5 -T 8), a midpoint of the second switch stack being coupled to the midpoint node, and a second phase branch with a plurality of switching units (S 5 -S 8); and a third phase portion comprising: a third switch stack with a plurality of switches (T 9 -T 12), a midpoint of the third switch stack being coupled to the midpoint node, and a third phase branch with a plurality of switching units (S 9 -S 12); a third switch stack with a plurality of switches (T 9 -T 12), a midpoint of the third switch stack being coupled to the midpoint node, and a third phase branch with a plurality of switching units (S 9 -S 12); the method comprising the steps of: controlling the plurality of switches (T 1 -T 12) of the first, second and third switch stacks (206, 208, 210), e.g., commutating a plurality of thyristors or insulated gate bipolar transistors, IGBTs, of the MEMC to: couple the first phase branch between the positive DC bus and the midpoint node; couple the second phase branch between the midpoint node and the negative DC bus; and couple opposing ends of the third phase branch to the midpoint node; characterised by: regulating an alternating current, AC, component of a midpoint voltage, at the midpoint node, to balance AC current loops among the first phase branch, second phase branch, and the third phase branch; and regulating a DC component of the midpoint voltage to balance DC voltages distributed among the first phase branch and the second phase branch. controlling the plurality of switches (T 1 -T 12) of the first, second and third switch stacks (206, 208, 210), e.g., commutating a plurality of thyristors or insulated gate bipolar transistors, IGBTs, of the MEMC to: couple the first phase branch between the positive DC bus and the midpoint node; couple the second phase branch between the midpoint node and the negative DC bus; and couple opposing ends of the third phase branch to the midpoint node; couple the first phase branch between the positive DC bus and the midpoint node; couple the second phase branch between the midpoint node and the negative DC bus; and couple opposing ends of the third phase branch to the midpoint node; characterised by: regulating an alternating current, AC, component of a midpoint voltage, at the midpoint node, to balance AC current loops among the first phase branch, second phase branch, and the third phase branch; and regulating a DC component of the midpoint voltage to balance DC voltages distributed among the first phase branch and the second phase branch. regulating an alternating current, AC, component of a midpoint voltage, at the midpoint node, to balance AC current loops among the first phase branch, second phase branch, and the third phase branch; and regulating a DC component of the midpoint voltage to balance DC voltages distributed among the first phase branch and the second phase branch.