A peak hold circuit capable of operating at a wide temperature range, the peak hold circuit comprising: a long tail pair circuit comprising: a first transistor provided with an input signal; a second transistor, wherein a second emitter of the second transistor is coupled to a first emitter of the first transistor; and a first current source coupled to a low voltage source; a correction circuit comprising: a hold capacitor which holds a hold voltage; an operational amplifier supplied with the hold voltage; and a correction transistor, further comprising a correction base, a correction collector and a correction emitter, wherein the correction collector is coupled to the hold capacitor and the operational amplifier, and the correction emitter is coupled to a high voltage source; a current mirror circuit comprising: a second current source comprising a second input, a second output, and a second common node, wherein the second input is coupled to a third emitter of a third transistor via a first resistor, the second output is coupled to a first collector of the first transistor, and the second common node is coupled to the high voltage source; and a third current source comprising a third input, a third output, and a third common node, wherein the third input is coupled to the third emitter of the third transistor via a second resistor and to ground via a third resistor, and the third output is coupled to a second collector of the second transistor, and the third common node is coupled to the high voltage source; wherein the second output of the second current source and the first collector of the first transistor are coupled to the correction base of the correction transistor. a long tail pair circuit comprising: a first transistor provided with an input signal; a second transistor, wherein a second emitter of the second transistor is coupled to a first emitter of the first transistor; and a first current source coupled to a low voltage source; a first transistor provided with an input signal; a second transistor, wherein a second emitter of the second transistor is coupled to a first emitter of the first transistor; and a first current source coupled to a low voltage source; a correction circuit comprising: a hold capacitor which holds a hold voltage; an operational amplifier supplied with the hold voltage; and a correction transistor, further comprising a correction base, a correction collector and a correction emitter, wherein the correction collector is coupled to the hold capacitor and the operational amplifier, and the correction emitter is coupled to a high voltage source; a hold capacitor which holds a hold voltage; an operational amplifier supplied with the hold voltage; and a correction transistor, further comprising a correction base, a correction collector and a correction emitter, wherein the correction collector is coupled to the hold capacitor and the operational amplifier, and the correction emitter is coupled to a high voltage source; a current mirror circuit comprising: a second current source comprising a second input, a second output, and a second common node, wherein the second input is coupled to a third emitter of a third transistor via a first resistor, the second output is coupled to a first collector of the first transistor, and the second common node is coupled to the high voltage source; and a third current source comprising a third input, a third output, and a third common node, wherein the third input is coupled to the third emitter of the third transistor via a second resistor and to ground via a third resistor, and the third output is coupled to a second collector of the second transistor, and the third common node is coupled to the high voltage source; wherein the second output of the second current source and the first collector of the first transistor are coupled to the correction base of the correction transistor. a second current source comprising a second input, a second output, and a second common node, wherein the second input is coupled to a third emitter of a third transistor via a first resistor, the second output is coupled to a first collector of the first transistor, and the second common node is coupled to the high voltage source; and a third current source comprising a third input, a third output, and a third common node, wherein the third input is coupled to the third emitter of the third transistor via a second resistor and to ground via a third resistor, and the third output is coupled to a second collector of the second transistor, and the third common node is coupled to the high voltage source; wherein the second output of the second current source and the first collector of the first transistor are coupled to the correction base of the correction transistor.