Multiplexer circuitry, comprising: a data transmitter configured to transmit a data signal across a signal line based on a transmission clock signal (CLKT); a control unit comprising a data receiver and a phase detector, wherein the data receiver is configured to receive the data signal from the signal line based on a reception clock signal (CLKM) and to generate an output signal based on the received data signal and synchronized with the reception clock signal, and wherein the phase detector is configured to measure a phase of the received data signal relative to a phase of the reception clock signal based on said output signal and to output a control signal indicative of a difference between the measured phase and a target phase of the received data signal; and a phase rotator configured to adjust the phase of the transmission clock signal based on the control signal to bring the measured phase towards or to the target phase, wherein: the output signal comprises a pulse signal having pulses synchronised with edges of the reception clock signal, each pulse indicative of a data value of the data signal at a corresponding said edge of the reception clock signal; the control unit comprises a pair of said data receivers each configured to receive the data signal from the signal line based on a corresponding reception clock signal (CLKM 1, CLKM 2) and to generate a corresponding said output signal; the corresponding reception clock signals have different relative phases from one another so that the output signals of the pair of said data receivers have associated different relative phases from one another; and the phase detector is configured to determine that an edge of the data signal is between corresponding edges of the reception clock signals of the pair if the pulses from the data receivers of the pair which are synchronised with those edges indicate opposite data values. a data transmitter configured to transmit a data signal across a signal line based on a transmission clock signal (CLKT); a control unit comprising a data receiver and a phase detector, wherein the data receiver is configured to receive the data signal from the signal line based on a reception clock signal (CLKM) and to generate an output signal based on the received data signal and synchronized with the reception clock signal, and wherein the phase detector is configured to measure a phase of the received data signal relative to a phase of the reception clock signal based on said output signal and to output a control signal indicative of a difference between the measured phase and a target phase of the received data signal; and a phase rotator configured to adjust the phase of the transmission clock signal based on the control signal to bring the measured phase towards or to the target phase, wherein: the output signal comprises a pulse signal having pulses synchronised with edges of the reception clock signal, each pulse indicative of a data value of the data signal at a corresponding said edge of the reception clock signal; the control unit comprises a pair of said data receivers each configured to receive the data signal from the signal line based on a corresponding reception clock signal (CLKM 1, CLKM 2) and to generate a corresponding said output signal; the corresponding reception clock signals have different relative phases from one another so that the output signals of the pair of said data receivers have associated different relative phases from one another; and the phase detector is configured to determine that an edge of the data signal is between corresponding edges of the reception clock signals of the pair if the pulses from the data receivers of the pair which are synchronised with those edges indicate opposite data values. the output signal comprises a pulse signal having pulses synchronised with edges of the reception clock signal, each pulse indicative of a data value of the data signal at a corresponding said edge of the reception clock signal; the control unit comprises a pair of said data receivers each configured to receive the data signal from the signal line based on a corresponding reception clock signal (CLKM 1, CLKM 2) and to generate a corresponding said output signal; the corresponding reception clock signals have different relative phases from one another so that the output signals of the pair of said data receivers have associated different relative phases from one another; and the phase detector is configured to determine that an edge of the data signal is between corresponding edges of the reception clock signals of the pair if the pulses from the data receivers of the pair which are synchronised with those edges indicate opposite data values.