A control method for controlling a data processing system including a logic circuit region where circuits are dynamically reconfigurable, the control method comprising: a step of obtaining an architecture code, the architecture code including object circuit information for mapping an object circuit that is at least part of a circuit for executing an application onto part of the logic circuit region, interface circuit information for mapping an interface circuit in contact with the object circuit onto the logic circuit region, and boundary condition to be realized in the interface circuit, wherein the object circuit is one of a plurality of partial circuits of a hardware module for implementing a function, and is a partial circuit of a netlist of the circuit for executing the application, whereby place and route issues including timing closure issues are resolved in the range of the partial circuit, and the object circuit is mapped on the logic circuit region by spatially and/or temporally dividing the logic circuit region, wherein the interface circuit is configured to receive, transmit and store a result of operating the object circuit and a state of the interface circuit comprises the result of operating the object circuit, wherein the interface circuit information includes information for forming boundaries of the partial circuit to contact with another partial circuit, which is mapped adjacent to the partial circuit on the logic circuit region, and wherein the boundary condition includes information of timing control of data supplied to the object circuit; a step of mapping the object circuit and the interface circuit in contact with the object circuit onto the logic circuit region according to the object circuit information and the interface circuit information of the architecture code; an activating step of controlling the interface circuit based on the boundary condition of the architecture code enabling the interface circuit to supply predetermined data to the object circuit at predetermined timing; and operating the hardware module by initializing and executing the plurality of partial circuits according to the state of the interface circuit reflecting a state of an interface circuit of another object circuit mapped by spatially and/or temporally dividing the logic circuit region. a step of obtaining an architecture code, the architecture code including object circuit information for mapping an object circuit that is at least part of a circuit for executing an application onto part of the logic circuit region, interface circuit information for mapping an interface circuit in contact with the object circuit onto the logic circuit region, and boundary condition to be realized in the interface circuit, wherein the object circuit is one of a plurality of partial circuits of a hardware module for implementing a function, and is a partial circuit of a netlist of the circuit for executing the application, whereby place and route issues including timing closure issues are resolved in the range of the partial circuit, and the object circuit is mapped on the logic circuit region by spatially and/or temporally dividing the logic circuit region, wherein the interface circuit is configured to receive, transmit and store a result of operating the object circuit and a state of the interface circuit comprises the result of operating the object circuit, wherein the interface circuit information includes information for forming boundaries of the partial circuit to contact with another partial circuit, which is mapped adjacent to the partial circuit on the logic circuit region, and wherein the boundary condition includes information of timing control of data supplied to the object circuit; a step of mapping the object circuit and the interface circuit in contact with the object circuit onto the logic circuit region according to the object circuit information and the interface circuit information of the architecture code; an activating step of controlling the interface circuit based on the boundary condition of the architecture code enabling the interface circuit to supply predetermined data to the object circuit at predetermined timing; and operating the hardware module by initializing and executing the plurality of partial circuits according to the state of the interface circuit reflecting a state of an interface circuit of another object circuit mapped by spatially and/or temporally dividing the logic circuit region.