An electrostatic discharge circuit, comprising a first signal line, a second signal line and a first thin film transistor, wherein the first TFT comprises a plurality of first sub-TFTs; each first sub-TFT comprises a first source electrode and a first drain electrode; the first sub-TFTs are sequentially arranged; adjacent first sub-TFTs share one first source electrode or first drain electrode; the first signal line is electrically connected with the first drain electrode of each first sub-TFT; and the second signal line is electrically connected with the first source electrode of each first sub-TFT; wherein the ESD circuit further comprises a third signal line and a second TFT, wherein the second TFT comprises a plurality of second sub-TFTs; each second sub-TFT comprises a second source electrode and a second drain electrode; the second sub-TFTs are sequentially arranged; two adjacent second sub-TFTs share one second source electrode or second drain electrode; the first signal line is electrically connected with the second source electrode of each second sub-TFT; and the third signal line is electrically connected with the second drain electrode of each second sub-TFT; wherein each first sub-TFT comprises a first gate electrode which is electrically connected with the first drain electrode or the first source electrode; and each second sub-TFT comprises a second gate electrode which is electrically connected with the second drain electrode or the second source electrode, the first gate electrodes in the plurality of first sub-TFTs of the first TFT are electrically connected with each other; the second gate electrodes in the plurality of second sub-TFTs of the second TFT are electrically connected with each other; and wherein the first gate electrodes in the plurality of first sub-TFTs are connected with the first signal line, and the gate electrodes in the plurality of second sub-TFTs are connected with the third signal line, wherein the first TFT and the second TFT are in series connection, characterized in that: both the first signal line and the second signal line are arranged at a side of the first TFT opposite to a side of the first TFT at which the second TFT is provided, and the third signal line is arranged at a side of the second TFT opposite to a side of the second TFT at which the first TFT is provided. each first sub-TFT comprises a first source electrode and a first drain electrode; the first sub-TFTs are sequentially arranged; adjacent first sub-TFTs share one first source electrode or first drain electrode; the first signal line is electrically connected with the first drain electrode of each first sub-TFT; and the second signal line is electrically connected with the first source electrode of each first sub-TFT; wherein the ESD circuit further comprises a third signal line and a second TFT, wherein the second TFT comprises a plurality of second sub-TFTs; each second sub-TFT comprises a second source electrode and a second drain electrode; the second sub-TFTs are sequentially arranged; two adjacent second sub-TFTs share one second source electrode or second drain electrode; the first signal line is electrically connected with the second source electrode of each second sub-TFT; and the third signal line is electrically connected with the second drain electrode of each second sub-TFT; wherein each first sub-TFT comprises a first gate electrode which is electrically connected with the first drain electrode or the first source electrode; and each second sub-TFT comprises a second gate electrode which is electrically connected with the second drain electrode or the second source electrode, the first gate electrodes in the plurality of first sub-TFTs of the first TFT are electrically connected with each other; the second gate electrodes in the plurality of second sub-TFTs of the second TFT are electrically connected with each other; and wherein the first gate electrodes in the plurality of first sub-TFTs are connected with the first signal line, and the gate electrodes in the plurality of second sub-TFTs are connected with the third signal line, wherein the first TFT and the second TFT are in series connection, characterized in that: both the first signal line and the second signal line are arranged at a side of the first TFT opposite to a side of the first TFT at which the second TFT is provided, and the third signal line is arranged at a side of the second TFT opposite to a side of the second TFT at which the first TFT is provided.