An apparatus, comprising: an array of three-transistor, 3T, memory cells (130, 230, 530, 630) including a first 3T memory cell and a second 3T memory cell, wherein a first transistor of the first 3T memory cell is coupled to a read digit line and a first transistor of the second 3T memory cell is coupled to the read digit line; said array of 3T memory cells coupled to sensing circuitry (150, 350, 550) including a first sense amplifier (306, 506, 606, 706), a second sense amplifier (307, 507, 607, 707), and a logical operation component (311, 511, 611), wherein: the first sense amplifier and the second sense amplifier are coupled to the same read digit line, the first sense amplifier and the second sense amplifier each have a respective enable signal the first sense amplifier and the second sense amplifier each have a different reference voltage, and the sensing circuitry (150, 350, 550) is controlled to: activate two read rows lines concurrently by coupling the first 3T memory cell and the second 3T memory cell to the read digit line; sense, via the first sense amplifier (306, 506, 606, 706), a data value of the read digit line as part of performance of a first logical operation concurrently sense, via the second sense amplifier (307, 507, 607, 707), a data value of the read digit line as part of performance of a second logical operation; and operate the logical operation component (311, 511, 611) to output a result of a third logical operation based on the data value stored in the first sense amplifier (306, 506, 606, 706) and the data value stored in the second sense amplifier (307, 507, 607, 707). an array of three-transistor, 3T, memory cells (130, 230, 530, 630) including a first 3T memory cell and a second 3T memory cell, wherein a first transistor of the first 3T memory cell is coupled to a read digit line and a first transistor of the second 3T memory cell is coupled to the read digit line; said array of 3T memory cells coupled to sensing circuitry (150, 350, 550) including a first sense amplifier (306, 506, 606, 706), a second sense amplifier (307, 507, 607, 707), and a logical operation component (311, 511, 611), wherein: the first sense amplifier and the second sense amplifier are coupled to the same read digit line, the first sense amplifier and the second sense amplifier each have a respective enable signal the first sense amplifier and the second sense amplifier each have a different reference voltage, and the sensing circuitry (150, 350, 550) is controlled to: activate two read rows lines concurrently by coupling the first 3T memory cell and the second 3T memory cell to the read digit line; sense, via the first sense amplifier (306, 506, 606, 706), a data value of the read digit line as part of performance of a first logical operation concurrently sense, via the second sense amplifier (307, 507, 607, 707), a data value of the read digit line as part of performance of a second logical operation; and operate the logical operation component (311, 511, 611) to output a result of a third logical operation based on the data value stored in the first sense amplifier (306, 506, 606, 706) and the data value stored in the second sense amplifier (307, 507, 607, 707). the first sense amplifier and the second sense amplifier are coupled to the same read digit line, the first sense amplifier and the second sense amplifier each have a respective enable signal the first sense amplifier and the second sense amplifier each have a different reference voltage, and the sensing circuitry (150, 350, 550) is controlled to: activate two read rows lines concurrently by coupling the first 3T memory cell and the second 3T memory cell to the read digit line; sense, via the first sense amplifier (306, 506, 606, 706), a data value of the read digit line as part of performance of a first logical operation concurrently sense, via the second sense amplifier (307, 507, 607, 707), a data value of the read digit line as part of performance of a second logical operation; and operate the logical operation component (311, 511, 611) to output a result of a third logical operation based on the data value stored in the first sense amplifier (306, 506, 606, 706) and the data value stored in the second sense amplifier (307, 507, 607, 707). activate two read rows lines concurrently by coupling the first 3T memory cell and the second 3T memory cell to the read digit line; sense, via the first sense amplifier (306, 506, 606, 706), a data value of the read digit line as part of performance of a first logical operation concurrently sense, via the second sense amplifier (307, 507, 607, 707), a data value of the read digit line as part of performance of a second logical operation; and operate the logical operation component (311, 511, 611) to output a result of a third logical operation based on the data value stored in the first sense amplifier (306, 506, 606, 706) and the data value stored in the second sense amplifier (307, 507, 607, 707).