A storage system, comprising: a memory controller configured to provide a clock signal; a buffer configured to receive the clock signal output from the memory controller and re-drive the clock signal, the buffer including a sampler configured to receive a data signal and a data strobe signal regarding the data signal, and to output a data stream; and a nonvolatile memory, including: a first comparator configured to sense a duty ratio of the clock signal and a first logic configured to generate a first digital code regarding the duty ratio of the clock signal; a first duty cycle corrector configured to receive the clock signal through the buffer and output a corrected clock signal by performing a first duty correction operation on the clock signal based on the first digital code; a data strobe signal generator configured to generate the data strobe signal based on the corrected clock signal and provide the data strobe signal to the buffer; and a data signal generator configured to receive odd and even data from a page buffer unit of the non-volatile memory and output the data signal to the buffer by selecting the odd data or the even data based on the corrected clock signal, wherein the buffer further includes: a second comparator configured to sense the duty ratio of the data strobe signal input to the sampler and a second logic configured to generate a second digital code regarding the duty ratio of the data strobe signal; and a second duty cycle corrector configured to receive the clock signal and the second digital code, and perform a second duty correction operation on the clock signal based on the second digital code, wherein a duty correction operation on the duty ratios of the data strobe signal and the data signal received from the nonvolatile memory is performed through the second duty correction operation on the clock signal; a memory controller configured to provide a clock signal; a buffer configured to receive the clock signal output from the memory controller and re-drive the clock signal, the buffer including a sampler configured to receive a data signal and a data strobe signal regarding the data signal, and to output a data stream; and a nonvolatile memory, including: a first comparator configured to sense a duty ratio of the clock signal and a first logic configured to generate a first digital code regarding the duty ratio of the clock signal; a first duty cycle corrector configured to receive the clock signal through the buffer and output a corrected clock signal by performing a first duty correction operation on the clock signal based on the first digital code; a data strobe signal generator configured to generate the data strobe signal based on the corrected clock signal and provide the data strobe signal to the buffer; and a data signal generator configured to receive odd and even data from a page buffer unit of the non-volatile memory and output the data signal to the buffer by selecting the odd data or the even data based on the corrected clock signal, a first comparator configured to sense a duty ratio of the clock signal and a first logic configured to generate a first digital code regarding the duty ratio of the clock signal; a first duty cycle corrector configured to receive the clock signal through the buffer and output a corrected clock signal by performing a first duty correction operation on the clock signal based on the first digital code; a data strobe signal generator configured to generate the data strobe signal based on the corrected clock signal and provide the data strobe signal to the buffer; and a data signal generator configured to receive odd and even data from a page buffer unit of the non-volatile memory and output the data signal to the buffer by selecting the odd data or the even data based on the corrected clock signal, wherein the buffer further includes: a second comparator configured to sense the duty ratio of the data strobe signal input to the sampler and a second logic configured to generate a second digital code regarding the duty ratio of the data strobe signal; and a second duty cycle corrector configured to receive the clock signal and the second digital code, and perform a second duty correction operation on the clock signal based on the second digital code, wherein a duty correction operation on the duty ratios of the data strobe signal and the data signal received from the nonvolatile memory is performed through the second duty correction operation on the clock signal; a second comparator configured to sense the duty ratio of the data strobe signal input to the sampler and a second logic configured to generate a second digital code regarding the duty ratio of the data strobe signal; and a second duty cycle corrector configured to receive the clock signal and the second digital code, and perform a second duty correction operation on the clock signal based on the second digital code, wherein a duty correction operation on the duty ratios of the data strobe signal and the data signal received from the nonvolatile memory is performed through the second duty correction operation on the clock signal;