A display substrate, comprising a display region, a barrier region and an opening region, wherein the display region and the barrier region surround the opening region, and the barrier region is located between the display region and the opening region, the barrier region comprises a first barrier wall, a first intercepting wall, and a second barrier wall, which are sequentially arranged from the display region to the opening region, and the first barrier wall, the first intercepting wall, and the second barrier wall surround the opening region; the first barrier wall comprises a first metal layer structure, and at least one lateral surface of the first metal layer structure surrounding the opening region is provided with a notch, the first metal layer structure comprises three metal layers (2023/2024/2025) which are superimposed on each other, wherein the middle layer is shorter than the two other layers (2023/2025) to form the notch; the first intercepting wall comprises a first insulating layer structure; and the second barrier wall comprises a second metal layer structure and a first stacked structure, the second metal layer structure is located on the first stacked structure, at least one lateral surface of the second metal layer structure surrounding the opening region is provided with a notch, the first stacked structure comprises a stacked layer of a metal layer and an insulating layer, the second layer structure comprises three metal layers (2045/2046/2047), which are superimposed on each other, wherein the middle layer is shorter than the two other layers (2045/2047) to form the notch, the display substrate further comprises a base substrate, wherein the display region comprises a thin film transistor and a storage capacitor, and the thin film transistor comprises a gate electrode, a gate insulating layer, and a source-drain electrode (1023, 1024), which are sequentially disposed on the base substrate; the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is disposed on the same layer with the gate electrode; the first metal layer structure and the second metal layer structure are disposed on the same layer with the source-drain electrode (1023, 1024); and the display substrate further comprises an interlayer insulating layer, the interlayer insulating layer is at least partially located between the source-drain electrode (1023, 1024) and the gate insulating layer, and the second electrode plate is disposed between the gate insulating layer and the interlayer insulating layer, wherein the first barrier wall further comprises a second insulating layer structure, and the first metal layer structure is located on the second insulating layer structure, the second insulating layer structure is disposed at least on the same layer with the gate insulating layer and the interlayer insulating layer. the barrier region comprises a first barrier wall, a first intercepting wall, and a second barrier wall, which are sequentially arranged from the display region to the opening region, and the first barrier wall, the first intercepting wall, and the second barrier wall surround the opening region; the first barrier wall comprises a first metal layer structure, and at least one lateral surface of the first metal layer structure surrounding the opening region is provided with a notch, the first metal layer structure comprises three metal layers (2023/2024/2025) which are superimposed on each other, wherein the middle layer is shorter than the two other layers (2023/2025) to form the notch; the first intercepting wall comprises a first insulating layer structure; and the second barrier wall comprises a second metal layer structure and a first stacked structure, the second metal layer structure is located on the first stacked structure, at least one lateral surface of the second metal layer structure surrounding the opening region is provided with a notch, the first stacked structure comprises a stacked layer of a metal layer and an insulating layer, the second layer structure comprises three metal layers (2045/2046/2047), which are superimposed on each other, wherein the middle layer is shorter than the two other layers (2045/2047) to form the notch, the display substrate further comprises a base substrate, wherein the display region comprises a thin film transistor and a storage capacitor, and the thin film transistor comprises a gate electrode, a gate insulating layer, and a source-drain electrode (1023, 1024), which are sequentially disposed on the base substrate; the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is disposed on the same layer with the gate electrode; the first metal layer structure and the second metal layer structure are disposed on the same layer with the source-drain electrode (1023, 1024); and the display substrate further comprises an interlayer insulating layer, the interlayer insulating layer is at least partially located between the source-drain electrode (1023, 1024) and the gate insulating layer, and the second electrode plate is disposed between the gate insulating layer and the interlayer insulating layer, wherein the first barrier wall further comprises a second insulating layer structure, and the first metal layer structure is located on the second insulating layer structure, the second insulating layer structure is disposed at least on the same layer with the gate insulating layer and the interlayer insulating layer.