An apparatus comprising: a decoder to decode an instruction having fields for a first and a second packed data source operand, and a packed data destination operand, and execution circuitry to execute the decoded instruction to: broadcast a data value from a least significant packed data element position of the first packed data source operand to a plurality of arithmetic circuits, for each packed data element position of the second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance and the broadcast data value from the least significant packed data element position of the first packed data source operand, and store a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand used in a corresponding arithmetic operation. a decoder to decode an instruction having fields for a first and a second packed data source operand, and a packed data destination operand, and execution circuitry to execute the decoded instruction to: broadcast a data value from a least significant packed data element position of the first packed data source operand to a plurality of arithmetic circuits, for each packed data element position of the second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance and the broadcast data value from the least significant packed data element position of the first packed data source operand, and store a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand used in a corresponding arithmetic operation. broadcast a data value from a least significant packed data element position of the first packed data source operand to a plurality of arithmetic circuits, for each packed data element position of the second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance and the broadcast data value from the least significant packed data element position of the first packed data source operand, and store a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand used in a corresponding arithmetic operation.