A thin film transistor array substrate, comprising: a substrate (301, 701, 801); a plurality of pixel elements disposed on the substrate (301, 701, 801), each of the pixel elements comprising a thin film transistor and a pixel electrode (306, 710, 820) electrically connected with a drain/source of the thin film transistor; a light shielding electrode disposed between the substrate (301, 701, 801) and the thin film transistor and configured to shield a channel (302c, 809c) of the thin film transistor, wherein the light shielding electrode comprises a transparent electrically-conductive layer (307, 702a, 802, 806) and a non-transparent electrically-conductive layer (308, 702b, 803, 807) stacked on top of each other; and a storage capacitor comprising a first electrode (309, 711, 805) and a second electrode (310, 501, 712, 809d) disposed opposite to each other, the first electrode (309, 711, 805) of the storage capacitor being disposed in a same layer and of a same material as the transparent electrically-conductive layer (307, 702a, 802, 806) of the light shielding electrode, characterized in that, the thin film transistor array substrate further comprises a peripheral drive circuit to provide the first electrode (309, 711, 805) of the storage capacitor with a potential, wherein the peripheral drive circuit includes the substrate (301, 701, 801), a peripheral transparent electrically-conductive layer (401, 804), a first insulation layer (311, 703, 808), a second insulation layer (312, 705, 811), a first connection metal (402, 812) connected with a common electrode, the third insulation layer (313, 111, 814), a second connection metal (403, 815), the passivation layer (112, 314, 708, 818) and the planarization layer (113, 315, 709, 819), wherein the peripheral transparent electrically-conductive layer (401,804) and the first electrode (309, 711, 805) of the storage capacitor are electrically connected, and the second connection metal (403, 815) and the first connection metal (402, 812) are electrically connected through a via, and the second connection metal (403, 815) and the peripheral transparent electrically-conductive layer (401,804) are electrically connected through a via. a substrate (301, 701, 801); a plurality of pixel elements disposed on the substrate (301, 701, 801), each of the pixel elements comprising a thin film transistor and a pixel electrode (306, 710, 820) electrically connected with a drain/source of the thin film transistor; a light shielding electrode disposed between the substrate (301, 701, 801) and the thin film transistor and configured to shield a channel (302c, 809c) of the thin film transistor, wherein the light shielding electrode comprises a transparent electrically-conductive layer (307, 702a, 802, 806) and a non-transparent electrically-conductive layer (308, 702b, 803, 807) stacked on top of each other; and a storage capacitor comprising a first electrode (309, 711, 805) and a second electrode (310, 501, 712, 809d) disposed opposite to each other, the first electrode (309, 711, 805) of the storage capacitor being disposed in a same layer and of a same material as the transparent electrically-conductive layer (307, 702a, 802, 806) of the light shielding electrode, characterized in that, the thin film transistor array substrate further comprises a peripheral drive circuit to provide the first electrode (309, 711, 805) of the storage capacitor with a potential, wherein the peripheral drive circuit includes the substrate (301, 701, 801), a peripheral transparent electrically-conductive layer (401, 804), a first insulation layer (311, 703, 808), a second insulation layer (312, 705, 811), a first connection metal (402, 812) connected with a common electrode, the third insulation layer (313, 111, 814), a second connection metal (403, 815), the passivation layer (112, 314, 708, 818) and the planarization layer (113, 315, 709, 819), wherein the peripheral transparent electrically-conductive layer (401,804) and the first electrode (309, 711, 805) of the storage capacitor are electrically connected, and the second connection metal (403, 815) and the first connection metal (402, 812) are electrically connected through a via, and the second connection metal (403, 815) and the peripheral transparent electrically-conductive layer (401,804) are electrically connected through a via.