A non-volatile semiconductor storage device, comprising: a non-volatile semiconductor storage element array for storing m data bits (RD[31:0]) and n check bits (C[5:0]), the non-volatile semiconductor storage element array comprising, as a basic unit, a one unit including an m-data-bit storage element and an n-check-bit storage element; an error correction code generating circuit for generating an error correction code (S[5:0]) based on the m data bits (RD[31:0]) and the n check bits (C[5:0]) of the one unit read out (UD[37:0]) from the non-volatile semiconductor storage element array; and a control signal generating circuit for outputting a control signal for switching between a first state and a second state; characterised by a multiplexer for inputting second state data (C[5:0], C[7:6]) including at least the n check bits (C[5:0]) and for inputting first state data (RD[7:0]) including bits of the m data bits (RD[31:0]), the first state data having the same number of bits as the second state data (C[5:0], C[7:6]), and the multiplexer selecting between the first state data (RD[7:0]) and the second state data (C[5:0], C[7:6]) based on the control signal to output selected one of the first state data (RD[7:0]) and the second state data (C[5:0], C[7:6]); and an error correction circuit coupled to the multiplexer for performing error correction of data having m data bits (RD[31:0]) using the error correction code (S[5:0]) in the first state and the second state, wherein: in the first state, the multiplexer outputs the first state data (RD[7:0]) to the error correction circuit and the error correction circuit performs error correction based on the bits of the m data bits that are not included in the first state data (RD[31:8]), the first state data outputted by the multiplexer (RD[7:0]) and the error correction code (S[5:0]), and in the second state, the multiplexer outputs the second state data (C[5:0], C[7:6]) to the error correction circuit and the error correction circuit performs error correction based on the bits of the m data bits that are not included in the first state data (RD[31:8]), the second state data outputted by the multiplexer (C[5:0], C[7:6]) and the error correction code (S[5:0]). a non-volatile semiconductor storage element array for storing m data bits (RD[31:0]) and n check bits (C[5:0]), the non-volatile semiconductor storage element array comprising, as a basic unit, a one unit including an m-data-bit storage element and an n-check-bit storage element; an error correction code generating circuit for generating an error correction code (S[5:0]) based on the m data bits (RD[31:0]) and the n check bits (C[5:0]) of the one unit read out (UD[37:0]) from the non-volatile semiconductor storage element array; and a control signal generating circuit for outputting a control signal for switching between a first state and a second state; characterised by a multiplexer for inputting second state data (C[5:0], C[7:6]) including at least the n check bits (C[5:0]) and for inputting first state data (RD[7:0]) including bits of the m data bits (RD[31:0]), the first state data having the same number of bits as the second state data (C[5:0], C[7:6]), and the multiplexer selecting between the first state data (RD[7:0]) and the second state data (C[5:0], C[7:6]) based on the control signal to output selected one of the first state data (RD[7:0]) and the second state data (C[5:0], C[7:6]); and an error correction circuit coupled to the multiplexer for performing error correction of data having m data bits (RD[31:0]) using the error correction code (S[5:0]) in the first state and the second state, wherein: in the first state, the multiplexer outputs the first state data (RD[7:0]) to the error correction circuit and the error correction circuit performs error correction based on the bits of the m data bits that are not included in the first state data (RD[31:8]), the first state data outputted by the multiplexer (RD[7:0]) and the error correction code (S[5:0]), and in the second state, the multiplexer outputs the second state data (C[5:0], C[7:6]) to the error correction circuit and the error correction circuit performs error correction based on the bits of the m data bits that are not included in the first state data (RD[31:8]), the second state data outputted by the multiplexer (C[5:0], C[7:6]) and the error correction code (S[5:0]). in the first state, the multiplexer outputs the first state data (RD[7:0]) to the error correction circuit and the error correction circuit performs error correction based on the bits of the m data bits that are not included in the first state data (RD[31:8]), the first state data outputted by the multiplexer (RD[7:0]) and the error correction code (S[5:0]), and in the second state, the multiplexer outputs the second state data (C[5:0], C[7:6]) to the error correction circuit and the error correction circuit performs error correction based on the bits of the m data bits that are not included in the first state data (RD[31:8]), the second state data outputted by the multiplexer (C[5:0], C[7:6]) and the error correction code (S[5:0]).