An apparatus comprising: a substrate layer with a surface having a substrate layer wire attach pad; and a plurality of tiled semiconductor devices mounted upon the substrate layer surface, each of the semiconductor device comprising: a top planar surface (220, 320, 420, 520, 620, 920, 1020) further comprising an electrically active region; a bottom planar surface (260, 360, 460, 560, 660, 960, 1060) disposed substantially parallel to the top planar surface, separated from the top planar surface by a device height; a shelf region 230 disposed between the top planar surface and the bottom planar surface, the shelf region having a shelf surface having shelf height less than the device height; an edge via formed by removing a portion of the shelf region; and a device wire attach pad (235, 335, 435, 535, 635, 935, 945, 1035, 1045) in electrical communication with the active region; wherein the device wire attach pad is at least partially disposed upon the shelf region, wherein the bottom planar surface is disposed adjacent to the substrate layer, the bottom planar surface covers a portion of the substrate layer surface excluding the substrate layer wire attach pad (295, 395, 495, 595, 695, 995a, 995b, 1095a, 1095b), characterized in that the edge via of a first one of the semiconductor devices is adjacent to the edge via of a second one of the semiconductor devices, and an electrical connection is provided between the device wire attach pad and the substrate layer wire attach pad. a substrate layer with a surface having a substrate layer wire attach pad; and a plurality of tiled semiconductor devices mounted upon the substrate layer surface, each of the semiconductor device comprising: a top planar surface (220, 320, 420, 520, 620, 920, 1020) further comprising an electrically active region; a bottom planar surface (260, 360, 460, 560, 660, 960, 1060) disposed substantially parallel to the top planar surface, separated from the top planar surface by a device height; a shelf region 230 disposed between the top planar surface and the bottom planar surface, the shelf region having a shelf surface having shelf height less than the device height; an edge via formed by removing a portion of the shelf region; and a device wire attach pad (235, 335, 435, 535, 635, 935, 945, 1035, 1045) in electrical communication with the active region; wherein the device wire attach pad is at least partially disposed upon the shelf region, wherein the bottom planar surface is disposed adjacent to the substrate layer, the bottom planar surface covers a portion of the substrate layer surface excluding the substrate layer wire attach pad (295, 395, 495, 595, 695, 995a, 995b, 1095a, 1095b), characterized in that the edge via of a first one of the semiconductor devices is adjacent to the edge via of a second one of the semiconductor devices, and an electrical connection is provided between the device wire attach pad and the substrate layer wire attach pad. a top planar surface (220, 320, 420, 520, 620, 920, 1020) further comprising an electrically active region; a bottom planar surface (260, 360, 460, 560, 660, 960, 1060) disposed substantially parallel to the top planar surface, separated from the top planar surface by a device height; a shelf region 230 disposed between the top planar surface and the bottom planar surface, the shelf region having a shelf surface having shelf height less than the device height; an edge via formed by removing a portion of the shelf region; and a device wire attach pad (235, 335, 435, 535, 635, 935, 945, 1035, 1045) in electrical communication with the active region; wherein the device wire attach pad is at least partially disposed upon the shelf region, a bottom planar surface (260, 360, 460, 560, 660, 960, 1060) disposed substantially parallel to the top planar surface, separated from the top planar surface by a device height; a shelf region 230 disposed between the top planar surface and the bottom planar surface, the shelf region having a shelf surface having shelf height less than the device height; an edge via formed by removing a portion of the shelf region; and a device wire attach pad (235, 335, 435, 535, 635, 935, 945, 1035, 1045) in electrical communication with the active region; wherein the device wire attach pad is at least partially disposed upon the shelf region, wherein the bottom planar surface is disposed adjacent to the substrate layer, the bottom planar surface covers a portion of the substrate layer surface excluding the substrate layer wire attach pad (295, 395, 495, 595, 695, 995a, 995b, 1095a, 1095b), characterized in that the edge via of a first one of the semiconductor devices is adjacent to the edge via of a second one of the semiconductor devices, and an electrical connection is provided between the device wire attach pad and the substrate layer wire attach pad.