A composite finite field multiplier apt to selectively perform 3-input GF (2 n) or GF ((2 n) 2) multiplication, comprising: - an input port, configured to input an operand a ( x), an operand b ( x), an operand c ( x), an irreducible polynomial p ( x), an irreducible polynomial q ( x) and a control signal k, wherein the irreducible polynomial p(x) has the form of: p x = x n + p n − 1 x n − 1 + p n − 2 x n − 2 +... + p 1 x + 1 and the irreducible polynomial q(x) has the form of: q x = q 2 x 2 + q 1 x + q 0; - a GF (2 n) standard basis multiplier, configured to implement the multiplication (a(x) × b(x) × c ( x)) mod(p(x)) of the three operands a(x), b(x) and c(x) on the standard basis over GF(2 n); - a GF (2 n) look-up table multiplier, configured to implement the multiplication (a(x) × b ( x) × c ( x)) mod(p(x)) of the three operands a(x), b(x) and c(x) based on the look-up table over GF(2 n); - a GF ((2 n) 2) multiplier, comprising a first processor and a scheduler interconnected with each other; the first processor is configured to implement the multiplication (a(x) × b(x) × c ( x)) mod(q(x)) of the three operands a(x), b(x) and c(x) over GF((2 n) 2); the first processor comprising an XOR gate circuit for processing addition operations over the GF (2 n) field, the scheduler being adapted to call the GF (2 n) look-up table multiplier or GF (2 n) standard basis multiplier in order to obtain intermediate calculation results, the first processor being apt to add said intermediate calculation results using its XOR gate circuit, and wherein the scheduler is adapted to call the GF (2 n) look-up table multiplier or the GF (2 n) standard basis multiplier according to a value of said control signal k; - a controller, configured to parse the control signal k and control the GF ((2 n) 2) multiplier, the GF (2 n) standard basis multiplier and the GF (2 n) look-up table multiplier to selectively implement 3-input GF (2 n) multiplication or 3-input GF ((2 n) 2) multiplication based on the parsing result; - an output port, configured to output the results; wherein the controller is connected respectively to the input port, the output port, the GF ((2 n) 2) multiplier, the GF (2 n) standard basis multiplier and the GF (2 n) look-up table multiplier; and the GF ((2 n) 2) multiplier is connected respectively to the GF (2 n) standard basis multiplier and the GF (2 n) look-up table multiplier. - an input port, configured to input an operand a ( x), an operand b ( x), an operand c ( x), an irreducible polynomial p ( x), an irreducible polynomial q ( x) and a control signal k, wherein the irreducible polynomial p(x) has the form of: p x = x n + p n − 1 x n − 1 + p n − 2 x n − 2 +... + p 1 x + 1 and the irreducible polynomial q(x) has the form of: q x = q 2 x 2 + q 1 x + q 0; - a GF (2 n) standard basis multiplier, configured to implement the multiplication (a(x) × b(x) × c ( x)) mod(p(x)) of the three operands a(x), b(x) and c(x) on the standard basis over GF(2 n); - a GF (2 n) look-up table multiplier, configured to implement the multiplication (a(x) × b ( x) × c ( x)) mod(p(x)) of the three operands a(x), b(x) and c(x) based on the look-up table over GF(2 n); - a GF ((2 n) 2) multiplier, comprising a first processor and a scheduler interconnected with each other; the first processor is configured to implement the multiplication (a(x) × b(x) × c ( x)) mod(q(x)) of the three operands a(x), b(x) and c(x) over GF((2 n) 2); the first processor comprising an XOR gate circuit for processing addition operations over the GF (2 n) field, the scheduler being adapted to call the GF (2 n) look-up table multiplier or GF (2 n) standard basis multiplier in order to obtain intermediate calculation results, the first processor being apt to add said intermediate calculation results using its XOR gate circuit, and wherein the scheduler is adapted to call the GF (2 n) look-up table multiplier or the GF (2 n) standard basis multiplier according to a value of said control signal k; - a controller, configured to parse the control signal k and control the GF ((2 n) 2) multiplier, the GF (2 n) standard basis multiplier and the GF (2 n) look-up table multiplier to selectively implement 3-input GF (2 n) multiplication or 3-input GF ((2 n) 2) multiplication based on the parsing result; - an output port, configured to output the results;