A compressed memory controller, comprising: a memory interface configured to access a system memory via a system bus; and a compression indicator, CI, cache comprising a plurality of CI cache entries each configured to store a previously read master directory memory block of a master directory in the system memory; wherein the master directory contains one CI per entry to denote if the memory line is stored as compressed, and if so, a compression pattern indicating a compression length of data; the compressed memory controller configured to: receive a memory read request comprising a physical address of a memory block to be accessed within a memory line in the system memory; determine whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache; responsive to determining that the physical address does not correspond to a CI cache entry of the plurality of CI cache entries of the CI cache: read a master directory memory block containing a CI corresponding to the physical address from the master directory; write the master directory memory block to a CI cache entry of the CI cache; and read the CI from the CI cache entry of the CI cache; responsive to determining that the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache, read the CI from the CI cache entry of the CI cache; determine, based on the CI, a number of memory blocks within the memory line in the system memory to read for the memory read request; and read the determined number of memory blocks within the memory line in the system memory beginning at the physical address. a memory interface configured to access a system memory via a system bus; and a compression indicator, CI, cache comprising a plurality of CI cache entries each configured to store a previously read master directory memory block of a master directory in the system memory; wherein the master directory contains one CI per entry to denote if the memory line is stored as compressed, and if so, a compression pattern indicating a compression length of data; the compressed memory controller configured to: receive a memory read request comprising a physical address of a memory block to be accessed within a memory line in the system memory; determine whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache; responsive to determining that the physical address does not correspond to a CI cache entry of the plurality of CI cache entries of the CI cache: read a master directory memory block containing a CI corresponding to the physical address from the master directory; write the master directory memory block to a CI cache entry of the CI cache; and read the CI from the CI cache entry of the CI cache; responsive to determining that the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache, read the CI from the CI cache entry of the CI cache; determine, based on the CI, a number of memory blocks within the memory line in the system memory to read for the memory read request; and read the determined number of memory blocks within the memory line in the system memory beginning at the physical address. receive a memory read request comprising a physical address of a memory block to be accessed within a memory line in the system memory; determine whether the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache; responsive to determining that the physical address does not correspond to a CI cache entry of the plurality of CI cache entries of the CI cache: read a master directory memory block containing a CI corresponding to the physical address from the master directory; write the master directory memory block to a CI cache entry of the CI cache; and read the CI from the CI cache entry of the CI cache; read a master directory memory block containing a CI corresponding to the physical address from the master directory; write the master directory memory block to a CI cache entry of the CI cache; and read the CI from the CI cache entry of the CI cache; responsive to determining that the physical address corresponds to a CI cache entry of the plurality of CI cache entries of the CI cache, read the CI from the CI cache entry of the CI cache; determine, based on the CI, a number of memory blocks within the memory line in the system memory to read for the memory read request; and read the determined number of memory blocks within the memory line in the system memory beginning at the physical address.