A precoding circuit, comprising: an input arranged to receive n parallel input binary data signals (101 to 101(n)) each having bit values provided sequentially in time-slots at a bit rate equal to R/n, where n is an integer greater than or equal to two; a precoder arranged to carry out a precoding with respect to the n parallel input binary data signals (101 to 101(n)) to obtain n parallel precoded signals; and an output arranged to output the parallel precoded signals obtained by the precoder (100, characterised by the precoder comprising: a first EXOR circuit for calculating an exclusive OR value of the bit values of all of the n parallel input binary data signals received in a time-slot; a differential encoder for generating an encoded signal, said differential encoder being arranged to: maintain a logical value of the encoded signal in response to each input logical value of a first type calculated by the first EXOR circuit; invert the logical value of the encoded signal in response to each input logical value of a second type calculated by the first EXOR circuit; delay the encoded signal for one time-slot time with respect to the parallel input binary data signals; and output the delayed encoded signal; and (n-1) second EXOR circuits provided in correspondence to all but one of the n parallel input binary data signals, a first one of the second EXOR circuits being arranged to calculate a second exclusive OR value of a corresponding one of the parallel input binary data signals and the encoded signal output by the differential encoder and, where n>2, each of the remaining second EXOR circuits being arranged to calculate a second exclusive OR value of a corresponding one of the parallel input binary data signals and an output of an immediately previous second EXOR circuit; wherein the encoded signal generated by the differential encoder and the second exclusive OR values calculated by the second EXOR circuits are outputted as the parallel precoded signals. an input arranged to receive n parallel input binary data signals (101 to 101(n)) each having bit values provided sequentially in time-slots at a bit rate equal to R/n, where n is an integer greater than or equal to two; a precoder arranged to carry out a precoding with respect to the n parallel input binary data signals (101 to 101(n)) to obtain n parallel precoded signals; and an output arranged to output the parallel precoded signals obtained by the precoder (100, characterised by the precoder comprising: a first EXOR circuit for calculating an exclusive OR value of the bit values of all of the n parallel input binary data signals received in a time-slot; a differential encoder for generating an encoded signal, said differential encoder being arranged to: maintain a logical value of the encoded signal in response to each input logical value of a first type calculated by the first EXOR circuit; invert the logical value of the encoded signal in response to each input logical value of a second type calculated by the first EXOR circuit; delay the encoded signal for one time-slot time with respect to the parallel input binary data signals; and output the delayed encoded signal; and a first EXOR circuit for calculating an exclusive OR value of the bit values of all of the n parallel input binary data signals received in a time-slot; a differential encoder for generating an encoded signal, said differential encoder being arranged to: maintain a logical value of the encoded signal in response to each input logical value of a first type calculated by the first EXOR circuit; invert the logical value of the encoded signal in response to each input logical value of a second type calculated by the first EXOR circuit; delay the encoded signal for one time-slot time with respect to the parallel input binary data signals; and output the delayed encoded signal; and maintain a logical value of the encoded signal in response to each input logical value of a first type calculated by the first EXOR circuit; invert the logical value of the encoded signal in response to each input logical value of a second type calculated by the first EXOR circuit; delay the encoded signal for one time-slot time with respect to the parallel input binary data signals; and output the delayed encoded signal; and (n-1) second EXOR circuits provided in correspondence to all but one of the n parallel input binary data signals, a first one of the second EXOR circuits being arranged to calculate a second exclusive OR value of a corresponding one of the parallel input binary data signals and the encoded signal output by the differential encoder and, where n>2, each of the remaining second EXOR circuits being arranged to calculate a second exclusive OR value of a corresponding one of the parallel input binary data signals and an output of an immediately previous second EXOR circuit; wherein the encoded signal generated by the differential encoder and the second exclusive OR values calculated by the second EXOR circuits are outputted as the parallel precoded signals.