A system, comprising: a plurality of processors, each comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; each of said dynamically configurable communication elements further comprising a plurality of input ports and a crossbar coupled to receive data from one or more of said plurality of input ports wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement; wherein, for each of the processors, the plurality of processor ports are configured for coupling to a first subset of the plurality of dynamically configurable communication elements; wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise communication ports configured for coupling to a subset of the plurality of the processors characterized in that each of said dynamically configurable communication elements further comprises a plurality of output registers, wherein its crossbar is further coupled to transmit data to a selected one or more of said plurality of output registers; and wherein each said output register selectively operates in a synchronous data transfer mode or a transparent data transfer mode, in which an input to a register may pass directly to an output of that register without being gated by or synchronized to a clock or any other signal. a plurality of processors, each comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; each of said dynamically configurable communication elements further comprising a plurality of input ports and a crossbar coupled to receive data from one or more of said plurality of input ports wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement; wherein, for each of the processors, the plurality of processor ports are configured for coupling to a first subset of the plurality of dynamically configurable communication elements; wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise communication ports configured for coupling to a subset of the plurality of the processors characterized in that each of said dynamically configurable communication elements further comprises a plurality of output registers, wherein its crossbar is further coupled to transmit data to a selected one or more of said plurality of output registers; and wherein each said output register selectively operates in a synchronous data transfer mode or a transparent data transfer mode, in which an input to a register may pass directly to an output of that register without being gated by or synchronized to a clock or any other signal.