A Class D power amplifier for driving a load between first and second output nodes, comprising: a first output half-bridge comprising first, highside, and second. lowside, transistors (M HA,M LA) in series between power rails, with the first output node (V OUTA) between the first and second transistors; a second output half-bridge comprising third, highside, and fourth, lowside, transistors (M HB,M LB) in series between power rails, with the second output node (V OUTB) between the third and fourth transistors; a first controller of the first output half-bridge for generating gate drive signals for the highside and lowside transistors in the first output half-bridge; and a second controller of the second output half-bridge for generating the gate drive signals for the highside and lowside transistors in the second output half-bridge; wherein the controllers are adapted to: derive an amplifier hold signal (hold) when an overcurrent state is detected in one output half-bridge, and to prevent switching of the other output half-bridge based on the hold signal, and wherein the controllers each comprise an asynchronous logic circuit for generating the amplifier hold signal, the asynchronous logic circuit comprising, for each output half-bridge, a first latch for generating a first output if overcurrent is detected in the lowside transistor and the output state of the amplifier is a first state (S 0) in which the half-bridge pulls its output node down, and a second latch for generating a second output if overcurrent is detected in the highside transistor and the output state of the half-bridge is a second state (S 2) in which the half-bridge pulls its output node up, wherein an output half-bridge hold signal (hold) comprises the logical OR of the first and second outputs. a first output half-bridge comprising first, highside, and second. lowside, transistors (M HA,M LA) in series between power rails, with the first output node (V OUTA) between the first and second transistors; a second output half-bridge comprising third, highside, and fourth, lowside, transistors (M HB,M LB) in series between power rails, with the second output node (V OUTB) between the third and fourth transistors; a first controller of the first output half-bridge for generating gate drive signals for the highside and lowside transistors in the first output half-bridge; and a second controller of the second output half-bridge for generating the gate drive signals for the highside and lowside transistors in the second output half-bridge; wherein the controllers are adapted to: derive an amplifier hold signal (hold) when an overcurrent state is detected in one output half-bridge, and to prevent switching of the other output half-bridge based on the hold signal, and wherein the controllers each comprise an asynchronous logic circuit for generating the amplifier hold signal, the asynchronous logic circuit comprising, for each output half-bridge, a first latch for generating a first output if overcurrent is detected in the lowside transistor and the output state of the amplifier is a first state (S 0) in which the half-bridge pulls its output node down, and a second latch for generating a second output if overcurrent is detected in the highside transistor and the output state of the half-bridge is a second state (S 2) in which the half-bridge pulls its output node up, wherein an output half-bridge hold signal (hold) comprises the logical OR of the first and second outputs. derive an amplifier hold signal (hold) when an overcurrent state is detected in one output half-bridge, and to prevent switching of the other output half-bridge based on the hold signal, and wherein the controllers each comprise an asynchronous logic circuit for generating the amplifier hold signal, the asynchronous logic circuit comprising, for each output half-bridge, a first latch for generating a first output if overcurrent is detected in the lowside transistor and the output state of the amplifier is a first state (S 0) in which the half-bridge pulls its output node down, and a second latch for generating a second output if overcurrent is detected in the highside transistor and the output state of the half-bridge is a second state (S 2) in which the half-bridge pulls its output node up, wherein an output half-bridge hold signal (hold) comprises the logical OR of the first and second outputs.