A driver circuit, comprising: an output stage arranged between high and low voltage rails (16,18); at least one buffer stage (4,6) having a high side buffer and a low side buffer wherein an output of a last buffer stage is connected to the output stage and an input of a first buffer stage is connected to an circuit input; wherein, for each buffer stage, the respective high side buffer and low side buffer are arranged in series between the high and low voltage rails, and are connected by a self-biasing bias line such that each buffer stage is a self-biasing differential buffer stage; wherein the output stage is a differential output stage having a pair of high side differential inputs, a pair of low side differential inputs and a pair of differential stage outputs; and in each buffer stage the high side buffer and the low side buffer are each differential buffers with a respective pair of differential inputs and a respective pair of differential outputs; wherein the circuit input is connected to one of the differential inputs (34,36) of the low side buffer of the first buffer stage and through an inverter to the other of the differential inputs (36,34) of the low side buffer of the first buffer stage; the circuit input is connected to the input of a level shift circuit; and the output of the level shift circuit is connected to one of the differential inputs (30,32) of the high side buffer of the first buffer stage and through an inverter to the other of the differential inputs (32,30) of the high side buffer of the first buffer stage; wherein the pair of high side and pair of low side differential outputs from the last buffer stage are connected to the respective pair of differential inputs of the output stage; wherein, in the case that there is a plurality of buffer stages, the buffer stages are in series and the pair of high side and pair of low side differential outputs from each buffer stage other than the last buffer stage are connected to the respective pair of high side and low side differential inputs of a respective subsequent buffer stage; and each of the high side buffers is implemented by transistors with an isolated well. an output stage arranged between high and low voltage rails (16,18); at least one buffer stage (4,6) having a high side buffer and a low side buffer wherein an output of a last buffer stage is connected to the output stage and an input of a first buffer stage is connected to an circuit input; wherein, for each buffer stage, the respective high side buffer and low side buffer are arranged in series between the high and low voltage rails, and are connected by a self-biasing bias line such that each buffer stage is a self-biasing differential buffer stage; wherein the output stage is a differential output stage having a pair of high side differential inputs, a pair of low side differential inputs and a pair of differential stage outputs; and in each buffer stage the high side buffer and the low side buffer are each differential buffers with a respective pair of differential inputs and a respective pair of differential outputs; wherein the circuit input is connected to one of the differential inputs (34,36) of the low side buffer of the first buffer stage and through an inverter to the other of the differential inputs (36,34) of the low side buffer of the first buffer stage; the circuit input is connected to the input of a level shift circuit; and the output of the level shift circuit is connected to one of the differential inputs (30,32) of the high side buffer of the first buffer stage and through an inverter to the other of the differential inputs (32,30) of the high side buffer of the first buffer stage; wherein the pair of high side and pair of low side differential outputs from the last buffer stage are connected to the respective pair of differential inputs of the output stage; wherein, in the case that there is a plurality of buffer stages, the buffer stages are in series and the pair of high side and pair of low side differential outputs from each buffer stage other than the last buffer stage are connected to the respective pair of high side and low side differential inputs of a respective subsequent buffer stage; and each of the high side buffers is implemented by transistors with an isolated well.