An apparatus comprising: a first processing sub-system, including: a plurality of processor circuits; a shared circuit; and an interrupt control circuit configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits, wherein the first processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits; a second processing sub-system, including: a plurality of processor circuits, wherein the second processing sub-system is configured to perform one or more operations using the shared circuit of the first processing sub-system; a proxy interrupt control circuit configured and arranged to generate a power-up control signal in response to receiving a peripheral interrupt and power to the first processing sub-system being disabled; and a power management circuit configured and arranged to: disable power to the first processing sub-system, including the interrupt control circuit, in response to the power-down control signal and the shared circuit being unused by the second processing sub-system; provide an enable signal according to which the proxy interrupt controller circuit is enabled/disabled; and enable power to the first processing sub-system in response to the power-up control signal. a first processing sub-system, including: a plurality of processor circuits; a shared circuit; and an interrupt control circuit configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits, wherein the first processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits; a plurality of processor circuits; a shared circuit; and an interrupt control circuit configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits, wherein the first processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits; a second processing sub-system, including: a plurality of processor circuits, wherein the second processing sub-system is configured to perform one or more operations using the shared circuit of the first processing sub-system; a plurality of processor circuits, wherein the second processing sub-system is configured to perform one or more operations using the shared circuit of the first processing sub-system; a proxy interrupt control circuit configured and arranged to generate a power-up control signal in response to receiving a peripheral interrupt and power to the first processing sub-system being disabled; and a power management circuit configured and arranged to: disable power to the first processing sub-system, including the interrupt control circuit, in response to the power-down control signal and the shared circuit being unused by the second processing sub-system; provide an enable signal according to which the proxy interrupt controller circuit is enabled/disabled; and enable power to the first processing sub-system in response to the power-up control signal. disable power to the first processing sub-system, including the interrupt control circuit, in response to the power-down control signal and the shared circuit being unused by the second processing sub-system; provide an enable signal according to which the proxy interrupt controller circuit is enabled/disabled; and enable power to the first processing sub-system in response to the power-up control signal.