A memory device comprising: a first phase change memory cell connected between a first bit line and a first word line; an X-decoder configured to provide a selection word line voltage to the first word line during a reset write operation for changing a state of the first phase change memory cell from a set state to a reset state; a Y-decoder configured to provide a selection bit line voltage to the first bit line during the reset write operation; a voltage bias circuit configured to: generate the selection word line voltage and the selection bit line voltage based on a first voltage bias during a first period of the reset write operation, generate the selection word line voltage and the selection bit line voltage based on a second voltage bias greater than the first voltage bias during a second period of the reset write operation, and generate the selection word line voltage and the selection bit line voltage based on a third voltage bias smaller than the first voltage bias and the second voltage bias during a third period of the reset write operation; and a current bias circuit configured to: provide a first current bias to the first bit line during the first period of the reset write operation, wherein the first current bias corresponds to a magnitude of a set write current; provide a second current bias to the first bit line during the second period of the reset write operation, wherein the second current bias corresponds to a magnitude of a reset write current; and provide a third current bias to the first bit line during the third period of the reset write operation, wherein the third current bias is equal to or smaller than a magnitude of a hold current, which is a minimum current for maintaining a turn-on state of the first phase change memory cell. a first phase change memory cell connected between a first bit line and a first word line; an X-decoder configured to provide a selection word line voltage to the first word line during a reset write operation for changing a state of the first phase change memory cell from a set state to a reset state; a Y-decoder configured to provide a selection bit line voltage to the first bit line during the reset write operation; a voltage bias circuit configured to: generate the selection word line voltage and the selection bit line voltage based on a first voltage bias during a first period of the reset write operation, generate the selection word line voltage and the selection bit line voltage based on a second voltage bias greater than the first voltage bias during a second period of the reset write operation, and generate the selection word line voltage and the selection bit line voltage based on a third voltage bias smaller than the first voltage bias and the second voltage bias during a third period of the reset write operation; and a current bias circuit configured to: generate the selection word line voltage and the selection bit line voltage based on a first voltage bias during a first period of the reset write operation, generate the selection word line voltage and the selection bit line voltage based on a second voltage bias greater than the first voltage bias during a second period of the reset write operation, and generate the selection word line voltage and the selection bit line voltage based on a third voltage bias smaller than the first voltage bias and the second voltage bias during a third period of the reset write operation; and a current bias circuit configured to: provide a first current bias to the first bit line during the first period of the reset write operation, wherein the first current bias corresponds to a magnitude of a set write current; provide a second current bias to the first bit line during the second period of the reset write operation, wherein the second current bias corresponds to a magnitude of a reset write current; and provide a third current bias to the first bit line during the third period of the reset write operation, wherein the third current bias is equal to or smaller than a magnitude of a hold current, which is a minimum current for maintaining a turn-on state of the first phase change memory cell.