A non-volatile memory device including: a matrix of multilevel memory cells and associated reading and programming circuits, a row decoder associated to said matrix, and a power supply circuit structure for said row decoder, wherein said power supply circuit structure comprises: a plurality of supply voltage generators (4, 5) for generating different voltage values; a plurality of conduction paths that are enabled according to a hierarchic-mode decoding; and switching means (8, 13) connected to said supply voltage generators (4, 5) for transferring said different voltage values through said plurality of conduction paths onto corresponding nodes (A, B, C; D, E, F) according to reading, programming or erasing phases to be performed, wherein said plurality of conduction paths comprise hierarchic levels of main and local wordlines (MWL, LWL) for receiving the supply voltages produced by the power supply circuit structure to bias the memory cells to a higher or lower level by enabling said switching means (8, 13), said switching means (8, 13) comprising a hierarchic switch structure connected between said hierarchic levels of main and local wordlines (MWL,LWL) and being independently enabled by the respective enabling signals, characterised in that each hierarchic switch structure comprises at least one pair of P-Channel transistors connected in series between a first and a second main wordline and a node interconnecting said P-Channel transistors is coupled to a local wordline. a matrix of multilevel memory cells and associated reading and programming circuits, a row decoder associated to said matrix, and a power supply circuit structure for said row decoder, wherein said power supply circuit structure comprises: a plurality of supply voltage generators (4, 5) for generating different voltage values; a plurality of conduction paths that are enabled according to a hierarchic-mode decoding; and switching means (8, 13) connected to said supply voltage generators (4, 5) for transferring said different voltage values through said plurality of conduction paths onto corresponding nodes (A, B, C; D, E, F) according to reading, programming or erasing phases to be performed, wherein said plurality of conduction paths comprise hierarchic levels of main and local wordlines (MWL, LWL) for receiving the supply voltages produced by the power supply circuit structure to bias the memory cells to a higher or lower level by enabling said switching means (8, 13), said switching means (8, 13) comprising a hierarchic switch structure connected between said hierarchic levels of main and local wordlines (MWL,LWL) and being independently enabled by the respective enabling signals, characterised in that each hierarchic switch structure comprises at least one pair of P-Channel transistors connected in series between a first and a second main wordline and a node interconnecting said P-Channel transistors is coupled to a local wordline. a plurality of supply voltage generators (4, 5) for generating different voltage values; a plurality of conduction paths that are enabled according to a hierarchic-mode decoding; and switching means (8, 13) connected to said supply voltage generators (4, 5) for transferring said different voltage values through said plurality of conduction paths onto corresponding nodes (A, B, C; D, E, F) according to reading, programming or erasing phases to be performed, wherein said plurality of conduction paths comprise hierarchic levels of main and local wordlines (MWL, LWL) for receiving the supply voltages produced by the power supply circuit structure to bias the memory cells to a higher or lower level by enabling said switching means (8, 13), said switching means (8, 13) comprising a hierarchic switch structure connected between said hierarchic levels of main and local wordlines (MWL,LWL) and being independently enabled by the respective enabling signals, characterised in that each hierarchic switch structure comprises at least one pair of P-Channel transistors connected in series between a first and a second main wordline and a node interconnecting said P-Channel transistors is coupled to a local wordline.