An interleaved power supply comprising: a master converter including a master switch configured to perform switching operation; a slave converter including a slave switch configured to perform switching operation while maintaining a predetermined phase difference with respect to the switching operation of the master switch, the master converter and the slave converter having a master-slave relationship: and a control circuit (60a, 60b, 60c) configured to control the switching operation of the slave switch, the control circuit comprising: a clock generator configured to generate a clock pulse having a predetermined frequency; a signal doubler (120, 260) configured to generate a master switch on-interval pulse signal indicating an on-interval of the master switch, using the clock pulse and a master drive pulse signal that switch-drives the master switch of the master converter, and generate a doubled duty pulse signal having a duty that is double that of the master switch on-interval pulse signal; an edge pulse generator configured to generate a first edge pulse signal in synchronization with a negative edge timing of the master drive pulse signal or a timing of the first clock pulse after the negative edge timing of the master drive pulse signal, and generate a second edge pulse signal in synchronization with a negative edge timing of the doubled duty pulse signal; and a slave drive pulse signal generator configured to generate a slave drive pulse signal that switch-drives the slave switch so that an on-interval of the slave switch is identical to an on-interval of the master switch, the slave drive pulse signal having a start point at a timing when the first edge pulse signal is generated, and an end point at a timing when the second edge pulse signal is generated. a master converter including a master switch configured to perform switching operation; a slave converter including a slave switch configured to perform switching operation while maintaining a predetermined phase difference with respect to the switching operation of the master switch, the master converter and the slave converter having a master-slave relationship: and a control circuit (60a, 60b, 60c) configured to control the switching operation of the slave switch, the control circuit comprising: a clock generator configured to generate a clock pulse having a predetermined frequency; a signal doubler (120, 260) configured to generate a master switch on-interval pulse signal indicating an on-interval of the master switch, using the clock pulse and a master drive pulse signal that switch-drives the master switch of the master converter, and generate a doubled duty pulse signal having a duty that is double that of the master switch on-interval pulse signal; an edge pulse generator configured to generate a first edge pulse signal in synchronization with a negative edge timing of the master drive pulse signal or a timing of the first clock pulse after the negative edge timing of the master drive pulse signal, and generate a second edge pulse signal in synchronization with a negative edge timing of the doubled duty pulse signal; and a slave drive pulse signal generator configured to generate a slave drive pulse signal that switch-drives the slave switch so that an on-interval of the slave switch is identical to an on-interval of the master switch, the slave drive pulse signal having a start point at a timing when the first edge pulse signal is generated, and an end point at a timing when the second edge pulse signal is generated. a clock generator configured to generate a clock pulse having a predetermined frequency; a signal doubler (120, 260) configured to generate a master switch on-interval pulse signal indicating an on-interval of the master switch, using the clock pulse and a master drive pulse signal that switch-drives the master switch of the master converter, and generate a doubled duty pulse signal having a duty that is double that of the master switch on-interval pulse signal; generate a master switch on-interval pulse signal indicating an on-interval of the master switch, using the clock pulse and a master drive pulse signal that switch-drives the master switch of the master converter, and generate a doubled duty pulse signal having a duty that is double that of the master switch on-interval pulse signal; an edge pulse generator configured to generate a first edge pulse signal in synchronization with a negative edge timing of the master drive pulse signal or a timing of the first clock pulse after the negative edge timing of the master drive pulse signal, and generate a second edge pulse signal in synchronization with a negative edge timing of the doubled duty pulse signal; and generate a first edge pulse signal in synchronization with a negative edge timing of the master drive pulse signal or a timing of the first clock pulse after the negative edge timing of the master drive pulse signal, and generate a second edge pulse signal in synchronization with a negative edge timing of the doubled duty pulse signal; and a slave drive pulse signal generator configured to generate a slave drive pulse signal that switch-drives the slave switch so that an on-interval of the slave switch is identical to an on-interval of the master switch, the slave drive pulse signal having a start point at a timing when the first edge pulse signal is generated, and an end point at a timing when the second edge pulse signal is generated.