A method of manufacturing a semiconductor device, comprising: forming a first epitaxial semiconductor material on an epitaxial substrate to form a first semiconductor material; forming a second epitaxial semiconductor material on the first semiconductor material to form a second semiconductor material, wherein the first and second semiconductor materials define a heterojunction between the first and second semiconductor materials; forming conductive regions (111, 112) adjacent the heterojunction to provide a conductive path to the heterojunction; forming a dielectric material that is coupled to the first and second semiconductor materials; forming interconnects extending through the dielectric material; removing material from the epitaxial substrate and thereby removing material through which parasitic conduction between the conductive regions can occur; and coupling the first and second semiconductor materials, the dielectric material and the interconnects to a carrier that is separate from the epitaxial substrate, wherein the carrier includes a metal material that structurally supports the first and second semiconductor materials, wherein the dielectric material is between the carrier and the first and second semiconductor materials; while the carrier is coupled to the first and second semiconductor materials, patterning the metal material to define electrical contacts, such that the electrical contacts are electrically coupled with the interconnects, the interconnects thereby providing an electrical coupling between the heterojunction and the metal material, wherein the semiconductor device is configured as a transistor device having a gate region, wherein the conductive regions (111 and 112) adjacent to the heterojunction provide a source and a drain of the transistor device, wherein patterning the metal material forms source, drain and gate contacts (841, 842, 843), wherein the gate, source and drain contacts are electrically coupled via one of said interconnects to the gate region, source and drain, respectively. forming a first epitaxial semiconductor material on an epitaxial substrate to form a first semiconductor material; forming a second epitaxial semiconductor material on the first semiconductor material to form a second semiconductor material, wherein the first and second semiconductor materials define a heterojunction between the first and second semiconductor materials; forming conductive regions (111, 112) adjacent the heterojunction to provide a conductive path to the heterojunction; forming a dielectric material that is coupled to the first and second semiconductor materials; forming interconnects extending through the dielectric material; removing material from the epitaxial substrate and thereby removing material through which parasitic conduction between the conductive regions can occur; and coupling the first and second semiconductor materials, the dielectric material and the interconnects to a carrier that is separate from the epitaxial substrate, wherein the carrier includes a metal material that structurally supports the first and second semiconductor materials, wherein the dielectric material is between the carrier and the first and second semiconductor materials; while the carrier is coupled to the first and second semiconductor materials, patterning the metal material to define electrical contacts, such that the electrical contacts are electrically coupled with the interconnects, the interconnects thereby providing an electrical coupling between the heterojunction and the metal material, wherein the semiconductor device is configured as a transistor device having a gate region, wherein the conductive regions (111 and 112) adjacent to the heterojunction provide a source and a drain of the transistor device, wherein patterning the metal material forms source, drain and gate contacts (841, 842, 843), wherein the gate, source and drain contacts are electrically coupled via one of said interconnects to the gate region, source and drain, respectively.