A method for producing a semiconductor integrated circuit device comprising a memory circuit region and a peripheral circuit region, the memory circuit region including a memory cell (3a, 3b, 3c, 3d, 3e, 3f) in which a memory gate structure (4a, 4b) is disposed between a first select gate structure (5a, 5b) and a second select gate structure (6a, 6b) through a sidewall spacer, the first select gate structure including a first select gate electrode (G2a, G2b), the second select gate structure including a second select gate electrode (G3a, G3b), the peripheral circuit region including a logic gate structure (7a, 7b) of a peripheral circuit (18, 19), the method comprising: a sidewall spacer formation step of forming the memory gate structure in the memory circuit region and then forming the sidewall spacer covering the memory gate structure, the memory gate structure including a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode (G1a, G1b) stacked in this order; a conductive layer formation step of forming a gate insulating film (25a, 25b, 29a, 29b) in the memory circuit region in which the memory gate structure is formed and in the peripheral circuit region, and then forming an N-type or P-type conductive layer on the gate insulating film; an electrode insulating portion formation step of forming, in the peripheral circuit region, an opposite-conductivity layer of a conductivity type opposite to a conductivity type of the conductive layer, and forming, along a part of a sidewall of the memory gate electrode through the sidewall spacer, a select gate electrode insulating portion (13, 14, 15, 16) including at least an intrinsic semiconductor layer (I1 and 12) or an opposite-conductivity-type electrode insulating layer (Rev) of the conductivity type opposite to the conductivity type of the conductive layer; and a gate electrode formation step of etching back each of the conductive layer and the opposite-conductivity layer in the peripheral circuit region and the memory circuit region by using a resist (Rr1a, Rr1b) patterned by using a photomask, so as to allow the conductive layer and the opposite-conductivity layer to remain on the gate insulating film by using the resist and form a logic gate electrode (G5 and G6) of the logic gate structure in the peripheral circuit region, and to allow the sidewall-shaped first select gate electrode to remain along one sidewall of the memory gate electrode through the sidewall spacer and to allow the sidewall-shaped second select gate electrode to remain along the sidewall on another side of the memory gate electrode through the sidewall spacer in the memory circuit region, wherein the first select gate electrode and the second select gate electrode are electrically insulated from each other by the select gate electrode insulating portion, the select gate electrode insulating portion being disposed between the first select gate electrode and the second select gate electrode and characterised by forming a PIN junction structure, an NIN junction structure, a PIP junction structure, an NPN junction structure, or a PNP junction structure together with the first and second select gate electrodes. a sidewall spacer formation step of forming the memory gate structure in the memory circuit region and then forming the sidewall spacer covering the memory gate structure, the memory gate structure including a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode (G1a, G1b) stacked in this order; a conductive layer formation step of forming a gate insulating film (25a, 25b, 29a, 29b) in the memory circuit region in which the memory gate structure is formed and in the peripheral circuit region, and then forming an N-type or P-type conductive layer on the gate insulating film; an electrode insulating portion formation step of forming, in the peripheral circuit region, an opposite-conductivity layer of a conductivity type opposite to a conductivity type of the conductive layer, and forming, along a part of a sidewall of the memory gate electrode through the sidewall spacer, a select gate electrode insulating portion (13, 14, 15, 16) including at least an intrinsic semiconductor layer (I1 and 12) or an opposite-conductivity-type electrode insulating layer (Rev) of the conductivity type opposite to the conductivity type of the conductive layer; and a gate electrode formation step of etching back each of the conductive layer and the opposite-conductivity layer in the peripheral circuit region and the memory circuit region by using a resist (Rr1a, Rr1b) patterned by using a photomask, so as to allow the conductive layer and the opposite-conductivity layer to remain on the gate insulating film by using the resist and form a logic gate electrode (G5 and G6) of the logic gate structure in the peripheral circuit region, and to allow the sidewall-shaped first select gate electrode to remain along one sidewall of the memory gate electrode through the sidewall spacer and to allow the sidewall-shaped second select gate electrode to remain along the sidewall on another side of the memory gate electrode through the sidewall spacer in the memory circuit region,