A reconfigurable computer accelerator comprising: a microcontroller adapted to receive instructions and data to control other components of the accelerator; a stream processor receiving instructions from the microcontroller to autonomously read multiple input values stored in a memory according to a selected set of predefined memory access patterns and to autonomously write multiple output values from the accelerator to the memory according to a selected set of predefined memory access patterns; a scratchpad memory communicating with the stream processor to read data from the memory or write data to the memory as controlled by the stream processor; a reconfigurable dataflow processor comprising a plurality of input points and a plurality of output points, and configured by the microcontroller to receive the multiple input values to provide output values according to the configuration; and a set of first-in, first-out buffers adapted to communicate data between the memory and the reconfigurable dataflow processor, the buffers being emptied or filled under the control of the stream processor asynchronously with respect to the reconfigurable dataflow processor and with respect to the stream processor, wherein each of the input points and output points is associated with a respective buffer; wherein the stream processor is configured to move data, according to a predefined pattern: between the memory and the scratchpad memory between the memory and the buffers; between the scratchpad memory and the buffers; and between a buffer associated with an output point and a buffer associated with an input point. a microcontroller adapted to receive instructions and data to control other components of the accelerator; a stream processor receiving instructions from the microcontroller to autonomously read multiple input values stored in a memory according to a selected set of predefined memory access patterns and to autonomously write multiple output values from the accelerator to the memory according to a selected set of predefined memory access patterns; a scratchpad memory communicating with the stream processor to read data from the memory or write data to the memory as controlled by the stream processor; a reconfigurable dataflow processor comprising a plurality of input points and a plurality of output points, and configured by the microcontroller to receive the multiple input values to provide output values according to the configuration; and a set of first-in, first-out buffers adapted to communicate data between the memory and the reconfigurable dataflow processor, the buffers being emptied or filled under the control of the stream processor asynchronously with respect to the reconfigurable dataflow processor and with respect to the stream processor, wherein each of the input points and output points is associated with a respective buffer; wherein the stream processor is configured to move data, according to a predefined pattern: between the memory and the scratchpad memory between the memory and the buffers; between the scratchpad memory and the buffers; and between a buffer associated with an output point and a buffer associated with an input point. between the memory and the scratchpad memory between the memory and the buffers; between the scratchpad memory and the buffers; and between a buffer associated with an output point and a buffer associated with an input point.