A computing system comprising: a plurality of processing nodes (220A, 220B, 220C, 220D), each comprising: one or more processing units configured to process applications; a plurality of links (240, 242, 244, 246) coupled to other processing nodes of the plurality of processing nodes; and a power controller; and wherein in response to receiving a broadcast probe for a most recent valid copy of a cache line from a first processing node of the plurality of processing nodes, a second processing node of the plurality of processing nodes is configured to: generate a miss response on behalf of a third processing node of the plurality of processing nodes, directly connected to the second processing node, responsive to determining that the third processing node is in a powered down state, and send the miss response to the first processing node; wherein the third processing node is configured to flush its caches and invalidate each entry of a probe filter of the third processing node before entering the powered down state, so that in the powered down state its caches are empty; and the miss response indicates that the third processing node does not store the cache line requested by the probe. a plurality of processing nodes (220A, 220B, 220C, 220D), each comprising: one or more processing units configured to process applications; a plurality of links (240, 242, 244, 246) coupled to other processing nodes of the plurality of processing nodes; and a power controller; and one or more processing units configured to process applications; a plurality of links (240, 242, 244, 246) coupled to other processing nodes of the plurality of processing nodes; and a power controller; and wherein in response to receiving a broadcast probe for a most recent valid copy of a cache line from a first processing node of the plurality of processing nodes, a second processing node of the plurality of processing nodes is configured to: generate a miss response on behalf of a third processing node of the plurality of processing nodes, directly connected to the second processing node, responsive to determining that the third processing node is in a powered down state, and send the miss response to the first processing node; wherein the third processing node is configured to flush its caches and invalidate each entry of a probe filter of the third processing node before entering the powered down state, so that in the powered down state its caches are empty; and the miss response indicates that the third processing node does not store the cache line requested by the probe. generate a miss response on behalf of a third processing node of the plurality of processing nodes, directly connected to the second processing node, responsive to determining that the third processing node is in a powered down state, and send the miss response to the first processing node; wherein the third processing node is configured to flush its caches and invalidate each entry of a probe filter of the third processing node before entering the powered down state, so that in the powered down state its caches are empty; and the miss response indicates that the third processing node does not store the cache line requested by the probe.