A semiconductor device comprising: a first semiconductor wafer having a light incident side and including a pixel region and a control circuit, the pixel region including a photodiode and a plurality of transistors (Tr1, Tr2); a second semiconductor wafer including a logic circuit, the logic circuit including a signal processing unit; a first multi-wiring layer formed at a side opposite to the light incident side of the first semiconductor wafer and comprising a first metal wiring layer and a plurality of further metal wiring layers, wherein the first metal wiring layer is connected to die pixel region; at least two transistors of the pixel region, which are connected to metal wirings among said plurality of further metal wiring layers of the first multi-wiring layer, a first cap layer formed on the first multi-wiring layer; a first layer formed on a bonding surface of the first semiconductor wafer; a second multi-wiring layer formed at a first side of the second semiconductor wafer and comprising a metal wiring layer, wherein the side opposite to the light incident side of the first semiconductor wafer and the first side of the second semiconductor wafer face each other; a second cap layer formed on the second multi-wiring layer; a second layer formed on a bonding surface of the second semiconductor wafer; a connection through-hole penetrating the first semiconductor wafer, the first multi-wiring layer, the first and the second cap layers, and the first and the second layers so as to expose the metal wiring layer of the second multi-wiring layer and so as to expose the first metal wiring layer; and a through-connection conductor embedded in the connection through-hole extending from the light incident side of the first semiconductor wafer to the second multi-wiring layer through the first semiconductor wafer in a peripheral section other than the pixel region; wherein the first semiconductor wafer and the second semiconductor wafer are bonded to each other such that the first multi-wiring layer and the second multi-wiring layer face each other, the through-connection conductor extends to the second multi-wiring layer by penetrating the first semiconductor wafer, the through-connection conductor is electrically connected to the metal wiring layer and the first metal wiring layer so as to electrically connect the pixel region and the control circuit to the logic circuit, and wherein the first metal wiring layer of the first multi-wiring layer is in direct contact with the first cap layer, wherein the first cap layer is in direct contact with the first layer, and the metal wiring layer of the second multi-wiring layer is in direct contact with the second cap layer, wherein the second cap layer is in direct contact with the second layer. a first semiconductor wafer having a light incident side and including a pixel region and a control circuit, the pixel region including a photodiode and a plurality of transistors (Tr1, Tr2); a second semiconductor wafer including a logic circuit, the logic circuit including a signal processing unit; a first multi-wiring layer formed at a side opposite to the light incident side of the first semiconductor wafer and comprising a first metal wiring layer and a plurality of further metal wiring layers, wherein the first metal wiring layer is connected to die pixel region; at least two transistors of the pixel region, which are connected to metal wirings among said plurality of further metal wiring layers of the first multi-wiring layer, a first cap layer formed on the first multi-wiring layer; a first layer formed on a bonding surface of the first semiconductor wafer; a second multi-wiring layer formed at a first side of the second semiconductor wafer and comprising a metal wiring layer, wherein the side opposite to the light incident side of the first semiconductor wafer and the first side of the second semiconductor wafer face each other; a second cap layer formed on the second multi-wiring layer; a second layer formed on a bonding surface of the second semiconductor wafer; a connection through-hole penetrating the first semiconductor wafer, the first multi-wiring layer, the first and the second cap layers, and the first and the second layers so as to expose the metal wiring layer of the second multi-wiring layer and so as to expose the first metal wiring layer; and a through-connection conductor embedded in the connection through-hole extending from the light incident side of the first semiconductor wafer to the second multi-wiring layer through the first semiconductor wafer in a peripheral section other than the pixel region; wherein the first semiconductor wafer and the second semiconductor wafer are bonded to each other such that the first multi-wiring layer and the second multi-wiring layer face each other, the through-connection conductor extends to the second multi-wiring layer by penetrating the first semiconductor wafer, the through-connection conductor is electrically connected to the metal wiring layer and the first metal wiring layer so as to electrically connect the pixel region and the control circuit to the logic circuit, and wherein the first metal wiring layer of the first multi-wiring layer is in direct contact with the first cap layer, wherein the first cap layer is in direct contact with the first layer, and the metal wiring layer of the second multi-wiring layer is in direct contact with the second cap layer, wherein the second cap layer is in direct contact with the second layer.