A cache controller that writes data to a cache memory, comprising: an external bus controlling unit operable to control data flowing into the cache controller from a plurality of external buses, a first buffer unit configured to retain data flowing in from the external buses to be written to the cache memory; a bypass unit configured to allow data flowing in from the external buses to bypass the first buffer unit; a selecting unit configured to selectively output either data output from the first buffer unit or data output from the bypass unit; a second buffer unit configured to have a plurality of areas in association with respective ones of the external buses, each of the areas respectively configured to retain a data piece to be written to the cache memory; a monitoring unit configured to monitor the areas of the second buffer unit and report whether an area in the second buffer unit corresponding to a predetermined one of the external buses is available; and an input and output controller configured to cause the selecting unit to output to the second buffer unit the data output from the bypass unit when it is reported by the monitoring unit that an area in the second buffer unit is available and the first buffer unit stores therein no data, and configured to cause the selecting unit to output to the second buffer unit the data output from the first buffer unit when it is reported by the monitoring unit that an area in the second buffer unit is available and the first buffer unit stores the data; wherein the second buffer unit is operable such that, while the data piece output from the selecting unit is being retrieved in an available area, another data piece stored in another area in the second buffer unit corresponding to the predetermined external bus may be written to the cache memory. an external bus controlling unit operable to control data flowing into the cache controller from a plurality of external buses, a first buffer unit configured to retain data flowing in from the external buses to be written to the cache memory; a bypass unit configured to allow data flowing in from the external buses to bypass the first buffer unit; a selecting unit configured to selectively output either data output from the first buffer unit or data output from the bypass unit; a second buffer unit configured to have a plurality of areas in association with respective ones of the external buses, each of the areas respectively configured to retain a data piece to be written to the cache memory; a monitoring unit configured to monitor the areas of the second buffer unit and report whether an area in the second buffer unit corresponding to a predetermined one of the external buses is available; and an input and output controller configured to cause the selecting unit to output to the second buffer unit the data output from the bypass unit when it is reported by the monitoring unit that an area in the second buffer unit is available and the first buffer unit stores therein no data, and configured to cause the selecting unit to output to the second buffer unit the data output from the first buffer unit when it is reported by the monitoring unit that an area in the second buffer unit is available and the first buffer unit stores the data; wherein the second buffer unit is operable such that, while the data piece output from the selecting unit is being retrieved in an available area, another data piece stored in another area in the second buffer unit corresponding to the predetermined external bus may be written to the cache memory.