A vertical-conduction MOSFET device comprising: a body of silicon carbide having a first and a second face (52A, 52B) and a peripheral zone, the body accommodating: a first current conduction region, of a first conductivity type, extending in the body from the second face and having a superficial portion facing the first face; a body region, of a second conductivity type, extending in the body from the first face; and a second current conduction region, of the first conductivity type, extending to the inside of the body region from the first face of the body, the second current conduction region delimiting in the body region, together with the superficial portion, a channel portion; an insulated gate region, extending on the first face of the body and overlying the channel portion, the insulated gate region comprising a gate conductive region; and a surface edge structure comprising an edge insulated region, extending on the first face of the body, in the peripheral zone of the body, a connection region, of conductive material, extending in an annular way only along the inner edge of the edge insulation region and not having portions extending between active areas. wherein: the gate conductive region and the annular connection region are formed by a gate bias layer including a silicon layer and a metal silicide layer overlying the silicon layer, the gate conductive region comprises a gate semiconductor portion formed by the silicon layer and a gate metal portion formed by the metal silicide layer, the annular connection region comprises a semiconductor connection portion formed by the silicon layer and a metal connection portion formed by the metal silicide layer, and the surface edge structure comprises a passivation layer completely covering the metal connection portion of the annular connection region. a body of silicon carbide having a first and a second face (52A, 52B) and a peripheral zone, the body accommodating: a first current conduction region, of a first conductivity type, extending in the body from the second face and having a superficial portion facing the first face; a body region, of a second conductivity type, extending in the body from the first face; and a second current conduction region, of the first conductivity type, extending to the inside of the body region from the first face of the body, the second current conduction region delimiting in the body region, together with the superficial portion, a channel portion; a first current conduction region, of a first conductivity type, extending in the body from the second face and having a superficial portion facing the first face; a body region, of a second conductivity type, extending in the body from the first face; and a second current conduction region, of the first conductivity type, extending to the inside of the body region from the first face of the body, the second current conduction region delimiting in the body region, together with the superficial portion, a channel portion; an insulated gate region, extending on the first face of the body and overlying the channel portion, the insulated gate region comprising a gate conductive region; and a surface edge structure comprising an edge insulated region, extending on the first face of the body, in the peripheral zone of the body, a connection region, of conductive material, extending in an annular way only along the inner edge of the edge insulation region and not having portions extending between active areas. wherein: the gate conductive region and the annular connection region are formed by a gate bias layer including a silicon layer and a metal silicide layer overlying the silicon layer, the gate conductive region comprises a gate semiconductor portion formed by the silicon layer and a gate metal portion formed by the metal silicide layer, the annular connection region comprises a semiconductor connection portion formed by the silicon layer and a metal connection portion formed by the metal silicide layer, and the surface edge structure comprises a passivation layer completely covering the metal connection portion of the annular connection region. the gate conductive region and the annular connection region are formed by a gate bias layer including a silicon layer and a metal silicide layer overlying the silicon layer, the gate conductive region comprises a gate semiconductor portion formed by the silicon layer and a gate metal portion formed by the metal silicide layer, the annular connection region comprises a semiconductor connection portion formed by the silicon layer and a metal connection portion formed by the metal silicide layer, and the surface edge structure comprises a passivation layer completely covering the metal connection portion of the annular connection region.