A charge redistribution digital-to-analog converter for use in a successive approximation analog-to-digital converter (SAR ADC), the charge redistribution DAC configured to operate in a first and a second phase of operation, comprising: a plurality of pairs of first and second capacitors (202, 204), each having a first side and a second side; a group of first switches, each first switch selectively controlling connection of the first side of a respective first capacitor to one of a pair of output signal lines, the group of first switches being controlled by a DAC input word; a group of second switches, each second switch selectively controlling connection of the first side of a respective second capacitor to one of the pair of output signal lines, the group of second switches being controlled by the DAC input word; a plurality of switches (222, 224) switchable to connect the first sides of the plurality of pairs of first and second capacitors to a common-mode voltage VCM; and a pair of switches configured to connect the pair of output signal lines to the common mode voltage VCM; first and second sets of sampling switches (604.1, 604.2), each first sampling switch (604.1) switchable to connect the second side of a respective first capacitor to a first reference voltage source and each second sampling switch (604.2) switchable to connect the second side of a respective second capacitor to a second reference voltage source; and a plurality of third switches, each third switch connecting the second sides of respective first and second capacitors to an on-chip reservoir capacitor, a pair of switches (608.1, 608.2) switchable to connect first and second sides of the on-chip reservoir capacitor to third and fourth reference voltage sources, respectively, wherein during the first phase of operation, the first sides of the first and second capacitors (202, 204) are connected to the common-mode voltage VCM, the second sides of the first capacitors are connected to the first reference voltage source, the second sides of the second capacitors are connected to the second reference voltage source, the first and second sides of the on-chip reservoir capacitor are respectively connected to the third and fourth reference voltage sources, and the pair of output signal lines are connected to the common mode voltage VCM; and wherein during the second phase of operation, the groups of first and second switches (206, 208) connect the first sides of the first and second capacitors (202, 204) to the first or second signal lines according to the DAC input word, and the third switches connect the second sides of the respective first and second capacitors (202, 204) to the on-chip reservoir capacitor. a plurality of pairs of first and second capacitors (202, 204), each having a first side and a second side; a group of first switches, each first switch selectively controlling connection of the first side of a respective first capacitor to one of a pair of output signal lines, the group of first switches being controlled by a DAC input word; a group of second switches, each second switch selectively controlling connection of the first side of a respective second capacitor to one of the pair of output signal lines, the group of second switches being controlled by the DAC input word; a plurality of switches (222, 224) switchable to connect the first sides of the plurality of pairs of first and second capacitors to a common-mode voltage VCM; and a pair of switches configured to connect the pair of output signal lines to the common mode voltage VCM; first and second sets of sampling switches (604.1, 604.2), each first sampling switch (604.1) switchable to connect the second side of a respective first capacitor to a first reference voltage source and each second sampling switch (604.2) switchable to connect the second side of a respective second capacitor to a second reference voltage source; and a plurality of third switches, each third switch connecting the second sides of respective first and second capacitors to an on-chip reservoir capacitor, a pair of switches (608.1, 608.2) switchable to connect first and second sides of the on-chip reservoir capacitor to third and fourth reference voltage sources, respectively, wherein during the first phase of operation, the first sides of the first and second capacitors (202, 204) are connected to the common-mode voltage VCM, the second sides of the first capacitors are connected to the first reference voltage source, the second sides of the second capacitors are connected to the second reference voltage source, the first and second sides of the on-chip reservoir capacitor are respectively connected to the third and fourth reference voltage sources, and the pair of output signal lines are connected to the common mode voltage VCM; and wherein during the second phase of operation, the groups of first and second switches (206, 208) connect the first sides of the first and second capacitors (202, 204) to the first or second signal lines according to the DAC input word, and the third switches connect the second sides of the respective first and second capacitors (202, 204) to the on-chip reservoir capacitor.