An oscillator circuit arrangement, comprising: a gain stage; a feedback loop including a crystal device connected to the gain stage; and a clock signal monitor circuit detecting at least one of a frequency shift and a loss of oscillation, the clock signal monitor circuit coupled to an output terminal of the gain stage and configured to generate a control signal, the control signal controlling the current through the gain stage; characterized in that the oscillator circuit arrangement additionally comprises: a current mirror circuit including an input path including a diode connected MOS transistor and an output path, the output path connected to the gain stage to supply current to the gain stage; and a controllable current source being a MOS transistor and connected in parallel to the diode connected MOS transistor such that drain terminals and source terminals of the MOS transistor of the controllable current source and of the diode connected MOS transistor are connected together respectively, wherein the current through the gain stage is generated in response to the current through the controllable current source, wherein the controllable current source is switched into a conductive state or a non-conductive state in response to the control signal, and wherein the clock signal monitor circuit comprises: a first path coupled to the clock signal and a second path coupled to the inverted clock signal, the first and second paths each comprising: a capacitor supplied by a current source, a switch connected in parallel to the capacitor, a Schmitt-Trigger device connected downstream the capacitor, and a gate coupling the output terminals of the Schmitt-Trigger devices of the first and second paths. a gain stage; a feedback loop including a crystal device connected to the gain stage; and a clock signal monitor circuit detecting at least one of a frequency shift and a loss of oscillation, the clock signal monitor circuit coupled to an output terminal of the gain stage and configured to generate a control signal, the control signal controlling the current through the gain stage; characterized in that the oscillator circuit arrangement additionally comprises: a current mirror circuit including an input path including a diode connected MOS transistor and an output path, the output path connected to the gain stage to supply current to the gain stage; and a controllable current source being a MOS transistor and connected in parallel to the diode connected MOS transistor such that drain terminals and source terminals of the MOS transistor of the controllable current source and of the diode connected MOS transistor are connected together respectively, wherein the current through the gain stage is generated in response to the current through the controllable current source, wherein the controllable current source is switched into a conductive state or a non-conductive state in response to the control signal, and wherein the clock signal monitor circuit comprises: a first path coupled to the clock signal and a second path coupled to the inverted clock signal, the first and second paths each comprising: a capacitor supplied by a current source, a switch connected in parallel to the capacitor, a Schmitt-Trigger device connected downstream the capacitor, and a gate coupling the output terminals of the Schmitt-Trigger devices of the first and second paths. a current mirror circuit including an input path including a diode connected MOS transistor and an output path, the output path connected to the gain stage to supply current to the gain stage; and a controllable current source being a MOS transistor and connected in parallel to the diode connected MOS transistor such that drain terminals and source terminals of the MOS transistor of the controllable current source and of the diode connected MOS transistor are connected together respectively, wherein the current through the gain stage is generated in response to the current through the controllable current source, wherein the controllable current source is switched into a conductive state or a non-conductive state in response to the control signal, and wherein the clock signal monitor circuit comprises: a first path coupled to the clock signal and a second path coupled to the inverted clock signal, the first and second paths each comprising: a capacitor supplied by a current source, a switch connected in parallel to the capacitor, a Schmitt-Trigger device connected downstream the capacitor, and a gate coupling the output terminals of the Schmitt-Trigger devices of the first and second paths.