A data processing device comprising: a receiving circuit configured to receive communication frames each including a plurality of data pieces; a temporary memory circuit configured to temporarily store the communication frames; a rule memory circuit configured to store a descriptor chain that includes successive descriptors, each descriptor including a transferring rule, the transferring rule specifying a size of data to transfer next and a destination of a memory circuit; a memory control circuit configured to sequentially refer to the descriptors of the descriptor chain stored in the rule memory circuit, and transfer, per data piece, the temporarily stored data pieces to the memory circuit in accordance with the transferring rules; wherein the descriptor corresponding to the last data piece of a communication frame indicates a last data piece transfer, wherein, in the case that the descriptor referred to indicates the last data piece transfer, i) if one of the data pieces temporarily stored and to be transferred next is the last data piece of a communication frame, and the size of the one of the data pieces is within the size of data specified in the corresponding transferring rule, the memory control circuit is configured to transfer the one of the data pieces to a destination, specified in the corresponding transferring rule, of the memory circuit, and ii) if the descriptor referred to indicates the last data piece transfer, and one of the data pieces temporarily stored and to be transferred next is not the last data piece of a communication frame or the size of the one of the data pieces excesses the size of data specified in the corresponding transferring rule, the memory control circuit is configured to output an error detection signal. a receiving circuit configured to receive communication frames each including a plurality of data pieces; a temporary memory circuit configured to temporarily store the communication frames; a rule memory circuit configured to store a descriptor chain that includes successive descriptors, each descriptor including a transferring rule, the transferring rule specifying a size of data to transfer next and a destination of a memory circuit; a memory control circuit configured to sequentially refer to the descriptors of the descriptor chain stored in the rule memory circuit, and transfer, per data piece, the temporarily stored data pieces to the memory circuit in accordance with the transferring rules; wherein the descriptor corresponding to the last data piece of a communication frame indicates a last data piece transfer, wherein, in the case that the descriptor referred to indicates the last data piece transfer, i) if one of the data pieces temporarily stored and to be transferred next is the last data piece of a communication frame, and the size of the one of the data pieces is within the size of data specified in the corresponding transferring rule, the memory control circuit is configured to transfer the one of the data pieces to a destination, specified in the corresponding transferring rule, of the memory circuit, and ii) if the descriptor referred to indicates the last data piece transfer, and one of the data pieces temporarily stored and to be transferred next is not the last data piece of a communication frame or the size of the one of the data pieces excesses the size of data specified in the corresponding transferring rule, the memory control circuit is configured to output an error detection signal. i) if one of the data pieces temporarily stored and to be transferred next is the last data piece of a communication frame, and the size of the one of the data pieces is within the size of data specified in the corresponding transferring rule, the memory control circuit is configured to transfer the one of the data pieces to a destination, specified in the corresponding transferring rule, of the memory circuit, and ii) if the descriptor referred to indicates the last data piece transfer, and one of the data pieces temporarily stored and to be transferred next is not the last data piece of a communication frame or the size of the one of the data pieces excesses the size of data specified in the corresponding transferring rule, the memory control circuit is configured to output an error detection signal.