A single-trigger low-energy flip-flop circuit, comprising: a trigger sub-circuit (301,302,303,304,305,306,307,308,309,323,237) that includes a first clock-activated transistor connectable between a power supply and ground and is configured to set a trigger signal to high level when an input signal to the single-trigger low-energy flip-flop circuit is at a different level than a level of an output signal generated by the single-trigger low-energy flip-flop circuit and a clock signal is at a first level, and is configured to reset the trigger signal to low level when the input signal to the single-trigger low-energy flip-flop circuit is at a same level as a level of the output signal generated by the single-trigger low-energy flip-flop circuit; and a latch sub-circuit (310,311,312,313,314,315,316,317,318,319,320,321,322,324) that includes a second clock-activated transistor connectable between the power supply and ground, wherein an output of the latch sub-circuit controls the output signal of the single-trigger low-energy flip-flop and the latch sub-circuit is configured to be enabled via the second clock-activated transistor and the trigger signal to change the level of the output signal based on the input signal when the trigger signal is at a high level and the clock signal transitions from the first level to a second level and to be disabled to maintain the level of the output signal when the trigger signal is at a low level, wherein a gate of the first clock-activated transistor and a gate of the second clock-activated transistor are directly coupled to the clock signal, wherein the latch sub-circuit further comprises a third clock-activated transistor that is configured as a pull-up transistor to keep the state of latch sub-circuit when the clock signal is at the second level, and wherein the third clock-activated transistor is enabled for every Nth clock cycle and N is greater than ten. a trigger sub-circuit (301,302,303,304,305,306,307,308,309,323,237) that includes a first clock-activated transistor connectable between a power supply and ground and is configured to set a trigger signal to high level when an input signal to the single-trigger low-energy flip-flop circuit is at a different level than a level of an output signal generated by the single-trigger low-energy flip-flop circuit and a clock signal is at a first level, and is configured to reset the trigger signal to low level when the input signal to the single-trigger low-energy flip-flop circuit is at a same level as a level of the output signal generated by the single-trigger low-energy flip-flop circuit; and a latch sub-circuit (310,311,312,313,314,315,316,317,318,319,320,321,322,324) that includes a second clock-activated transistor connectable between the power supply and ground, wherein an output of the latch sub-circuit controls the output signal of the single-trigger low-energy flip-flop and the latch sub-circuit is configured to be enabled via the second clock-activated transistor and the trigger signal to change the level of the output signal based on the input signal when the trigger signal is at a high level and the clock signal transitions from the first level to a second level and to be disabled to maintain the level of the output signal when the trigger signal is at a low level, wherein a gate of the first clock-activated transistor and a gate of the second clock-activated transistor are directly coupled to the clock signal, wherein the latch sub-circuit further comprises a third clock-activated transistor that is configured as a pull-up transistor to keep the state of latch sub-circuit when the clock signal is at the second level, and wherein the third clock-activated transistor is enabled for every Nth clock cycle and N is greater than ten.