A multi-channel controller comprising: a) a first control channel having a first primary controller with first and second overspeed detection output signals and having a first protection device with an overspeed detection output signal, without sharing a microprocessor bus with the first primary controller; b) a second control channel having a second primary controller with first and second overspeed detection output signals and a second protection device with an overspeed detection output signal without sharing a microprocessor bus with the second primary controller; and characterised in that the multi-channel controller further comprises: c) a plurality of logic gates (164, 166, 168, 170) combining the outputs of the primary controllers and the protection devices of both channels (12,14), said logic gates comprising primary OR gates (168,170) and alternate OR gates (164,166); d) wherein each primary OR gate (168, 170) accepts one input from the corresponding primary controller in the same channel (12,14) and one input from the alternate OR gate (164,166) being located in the other channel (14,12); and e) wherein each of the alternate OR gates (164,166) has three inputs (190, 192, 194): - the first alternate OR gate input is an overspeed detection output signal of the primary controller of the same channel (12,14) as the considered alternate OR gate (164,166), - the second alternate OR gate input is the overspeed detection output signal from the protection device of the same channel (12,14) as the alternate OR gate (164,166), - the third alternate OR gate input is a health signal representative of the health of the controller and of the protection device of the same channel (12,14) as the considered alternate OR gate (164,166); f) wherein said primary OR gate (168,170) outputs a command signal to a controlled device whenever the corresponding primary controller or the alternate OR gate (164,166) indicates an overspeed condition. a) a first control channel having a first primary controller with first and second overspeed detection output signals and having a first protection device with an overspeed detection output signal, without sharing a microprocessor bus with the first primary controller; b) a second control channel having a second primary controller with first and second overspeed detection output signals and a second protection device with an overspeed detection output signal without sharing a microprocessor bus with the second primary controller; and c) a plurality of logic gates (164, 166, 168, 170) combining the outputs of the primary controllers and the protection devices of both channels (12,14), said logic gates comprising primary OR gates (168,170) and alternate OR gates (164,166); d) wherein each primary OR gate (168, 170) accepts one input from the corresponding primary controller in the same channel (12,14) and one input from the alternate OR gate (164,166) being located in the other channel (14,12); and e) wherein each of the alternate OR gates (164,166) has three inputs (190, 192, 194): - the first alternate OR gate input is an overspeed detection output signal of the primary controller of the same channel (12,14) as the considered alternate OR gate (164,166), - the second alternate OR gate input is the overspeed detection output signal from the protection device of the same channel (12,14) as the alternate OR gate (164,166), - the third alternate OR gate input is a health signal representative of the health of the controller and of the protection device of the same channel (12,14) as the considered alternate OR gate (164,166); - the first alternate OR gate input is an overspeed detection output signal of the primary controller of the same channel (12,14) as the considered alternate OR gate (164,166), - the second alternate OR gate input is the overspeed detection output signal from the protection device of the same channel (12,14) as the alternate OR gate (164,166), - the third alternate OR gate input is a health signal representative of the health of the controller and of the protection device of the same channel (12,14) as the considered alternate OR gate (164,166); f) wherein said primary OR gate (168,170) outputs a command signal to a controlled device whenever the corresponding primary controller or the alternate OR gate (164,166) indicates an overspeed condition.