An electrical component, comprising: one or more semiconductor dies; a flat no-lead package, such as a quad flat no-lead 'QFN' package, a power quad flat no-lead 'PQFN' package, or a dual flat no-lead 'DFN' package, comprising: a thermal pad on which the semiconductor die(s) is/are mounted and which is configured to be electrically grounded; a plurality of leads arranged spaced apart from the thermal pad; a first circuit arranged inside the package and comprising a first input terminal, a first output terminal, and one or more signal processing elements for processing a signal received at the first input terminal and for supplying said processed signal at the first output terminal; a second circuit arranged inside the package and comprising a second input terminal, a second output terminal, and one or more signal processing elements for processing a signal received at the second input terminal and for supplying said processed signal at the second output terminal; and an electrical isolation configured for preventing crosstalk between the first circuit and the second circuit; wherein the first and second circuits are realized on the one or more semiconductor dies; wherein the first input terminal, the second input terminal, the first output terminal, and the second output terminal are each connected to a respective lead; wherein the flat no-lead package comprises a plurality of further leads that are integrally connected to the thermal pad, and the electrical isolation comprises a first and second isolation terminal of which at least one is connected to a respective further lead; wherein the lead that is connected to the first output terminal and the lead that is connected to the second output terminal are separated by a further lead that is connected to the second isolation terminal; wherein the first input terminal, the first output terminal, the second input terminal, the second output terminal, and the second isolation terminal are connected to the corresponding leads and further lead using one or more bondwires. one or more semiconductor dies; a flat no-lead package, such as a quad flat no-lead 'QFN' package, a power quad flat no-lead 'PQFN' package, or a dual flat no-lead 'DFN' package, comprising: a thermal pad on which the semiconductor die(s) is/are mounted and which is configured to be electrically grounded; a plurality of leads arranged spaced apart from the thermal pad; a thermal pad on which the semiconductor die(s) is/are mounted and which is configured to be electrically grounded; a plurality of leads arranged spaced apart from the thermal pad; a first circuit arranged inside the package and comprising a first input terminal, a first output terminal, and one or more signal processing elements for processing a signal received at the first input terminal and for supplying said processed signal at the first output terminal; a second circuit arranged inside the package and comprising a second input terminal, a second output terminal, and one or more signal processing elements for processing a signal received at the second input terminal and for supplying said processed signal at the second output terminal; and an electrical isolation configured for preventing crosstalk between the first circuit and the second circuit; wherein the first and second circuits are realized on the one or more semiconductor dies; wherein the first input terminal, the second input terminal, the first output terminal, and the second output terminal are each connected to a respective lead; wherein the flat no-lead package comprises a plurality of further leads that are integrally connected to the thermal pad, and the electrical isolation comprises a first and second isolation terminal of which at least one is connected to a respective further lead; wherein the lead that is connected to the first output terminal and the lead that is connected to the second output terminal are separated by a further lead that is connected to the second isolation terminal; wherein the first input terminal, the first output terminal, the second input terminal, the second output terminal, and the second isolation terminal are connected to the corresponding leads and further lead using one or more bondwires.