A multiple-stage amplifier (400, 500) comprising: a driver stage transistor (440, 540) with a first gate terminal, a first drain terminal and a first source terminal, wherein the driver stage transistor has a first power density, the first gate terminal is configured to receive an input RF signal, and the first source terminal is electrically coupled to a ground node; a first drain bias circuit (460, 560) coupled to the first drain terminal of the driver stage transistor, and configured to provide a first drain bias voltage from a first bias input terminal (458, 558) to the first drain terminal, wherein the driver stage transistor and the first drain bias circuit are integrally formed in a first semiconductor die (410, 510); a final stage transistor (472, 572) with a second gate terminal, a second drain terminal and a second source terminal, wherein the final stage transistor is integrally formed in a second semiconductor die, the second source terminal is electrically coupled to a ground node, and wherein the highest ratio of the first power density of the driver stage transistor to a second power density of the final stage transistor is 1:2; a second drain bias circuit (462, 562) coupled to the second drain terminal of the final stage transistor (472, 572), and configured to provide a second drain bias voltage from a second bias input terminal (478, 578) to the second drain terminal, wherein the second drain bias voltage equals the first drain bias voltage; and an interstage impedance matching circuit (450, 550) coupled between the first drain terminal and the second gate terminal; wherein the multiple-stage amplifier is characterized in that the second drain bias circuit (462, 562) is integrally formed in the second semiconductor die (470, 570). a driver stage transistor (440, 540) with a first gate terminal, a first drain terminal and a first source terminal, wherein the driver stage transistor has a first power density, the first gate terminal is configured to receive an input RF signal, and the first source terminal is electrically coupled to a ground node; a first drain bias circuit (460, 560) coupled to the first drain terminal of the driver stage transistor, and configured to provide a first drain bias voltage from a first bias input terminal (458, 558) to the first drain terminal, wherein the driver stage transistor and the first drain bias circuit are integrally formed in a first semiconductor die (410, 510); a final stage transistor (472, 572) with a second gate terminal, a second drain terminal and a second source terminal, wherein the final stage transistor is integrally formed in a second semiconductor die, the second source terminal is electrically coupled to a ground node, and wherein the highest ratio of the first power density of the driver stage transistor to a second power density of the final stage transistor is 1:2; a second drain bias circuit (462, 562) coupled to the second drain terminal of the final stage transistor (472, 572), and configured to provide a second drain bias voltage from a second bias input terminal (478, 578) to the second drain terminal, wherein the second drain bias voltage equals the first drain bias voltage; and an interstage impedance matching circuit (450, 550) coupled between the first drain terminal and the second gate terminal;