A driver control method being applied to a timer controller that communicates with a plurality of source driver chips connected in parallel through a first signal line, the method comprising: generating a point-to-point configuration instruction that comprises n configuration data, n≥2; sending the generated point-to-point configuration instruction to a first source driver chip through the first signal line, the first source driver chip being any one of the plurality of source driver chips; and receiving a configuration response instruction sent by the first source driver chip according to the sent point-to-point configuration instruction through the first signal line, the configuration response instruction comprising configuration response data for each of the n configuration data; wherein the received configuration response data for each configuration data indicates whether the configuration operation indicated by each configuration data is completed; the method being characterized in that the point-to-point configuration instruction comprises addresses used for the n configuration data, a first indicator, a second indicator and a data portion, wherein the first indicator is configured to indicate whether the addresses used for the n configuration data are consecutive, the second indicator is configured to indicate the number of configuration data in the point-to-point configuration instruction, and the data portion carries the n configuration data, and wherein the point-to-point configuration instruction comprises at least five bytes, the first indicator comprises the fifth bit of the third byte among the at least five bytes and the second indicator comprises the sixth bit to the eighth bit of the third byte; wherein target addresses indicating register address used for storing the n configuration data are acquired from the addresses used for the n configuration data according to a value of the first indicator, and when the value of the first indicator indicates the addresses used for the n configuration data are consecutive, the addresses used for the n configuration data comprised in the point-to-point configuration instruction are the first address and the last address of the consecutive addresses, and the acquired target addresses comprise a segment of consecutive addresses delimited by the first address and the last address, and when the value of first indicator indicates the addresses used for the n configuration data are not consecutive, the acquired target addresses comprise the address of each of the n configuration data. generating a point-to-point configuration instruction that comprises n configuration data, n≥2; sending the generated point-to-point configuration instruction to a first source driver chip through the first signal line, the first source driver chip being any one of the plurality of source driver chips; and receiving a configuration response instruction sent by the first source driver chip according to the sent point-to-point configuration instruction through the first signal line, the configuration response instruction comprising configuration response data for each of the n configuration data; wherein the received configuration response data for each configuration data indicates whether the configuration operation indicated by each configuration data is completed; the method being characterized in that the point-to-point configuration instruction comprises addresses used for the n configuration data, a first indicator, a second indicator and a data portion, wherein the first indicator is configured to indicate whether the addresses used for the n configuration data are consecutive, the second indicator is configured to indicate the number of configuration data in the point-to-point configuration instruction, and the data portion carries the n configuration data, and wherein the point-to-point configuration instruction comprises at least five bytes, the first indicator comprises the fifth bit of the third byte among the at least five bytes and the second indicator comprises the sixth bit to the eighth bit of the third byte; wherein target addresses indicating register address used for storing the n configuration data are acquired from the addresses used for the n configuration data according to a value of the first indicator, and when the value of the first indicator indicates the addresses used for the n configuration data are consecutive, the addresses used for the n configuration data comprised in the point-to-point configuration instruction are the first address and the last address of the consecutive addresses, and the acquired target addresses comprise a segment of consecutive addresses delimited by the first address and the last address, and when the value of first indicator indicates the addresses used for the n configuration data are not consecutive, the acquired target addresses comprise the address of each of the n configuration data.