An error compensator adapted to receive an input signal at its input and to provide an error compensated signal at its output, the error compensator comprising: a first operational amplifier and a second operational amplifier; a first switch and a first capacitor, connected in parallel between a first input terminal and an output terminal of the first operational amplifier; a second switch connected between a first input terminal and an output terminal of the second operational amplifier; a third switch connected between the first input terminal of the first operational amplifier and the input of the error compensator; a fourth switch connected between the output terminal of the second operational amplifier and the output of the error compensator; a first storage unit connected between the output terminal of the first operational amplifier and the first input terminal of the second operational amplifier; and a second storage unit connected between the first input terminal and the output terminal of the second operational amplifier, wherein the first storage unit includes: a fifth switch, a third capacitor and a sixth switch, coupled in series between the output terminal of the first operational amplifier and the first input terminal of the second operational amplifier; and a seventh switch, a fourth capacitor and an eighth switch, coupled in parallel to the fifth switch, the third capacitor and the sixth switch, between the output terminal of the first operational amplifier and the first input terminal of the second operational amplifier, wherein the fifth and sixth switches (SW5 and SW6) are configured to be turned on during a first period in the period in which the first and second switches (SW1 and SW2) are turned on, and the seventh and eighth switches (SW7 and SW8) are configured to be turned on during a second period not overlapping with the first period in the period in which the first and second switches (SW1 and SW2) are turned on and/or wherein the fourth switch is configured to be also set to be in a turn-on state during the first and second periods; and wherein the second storage unit includes: a second capacitor coupled between first and second nodes (N10 and N11); a ninth switch coupled between the second node and the first input terminal of the second operational amplifier; a tenth switch coupled between the first node and the output terminal of the second operational amplifier; an eleventh switch coupled between the first node and the first input terminal of the second operational amplifier; and a twelfth switch coupled between the second node and the output terminal of the second operational amplifier. a first operational amplifier and a second operational amplifier; a first switch and a first capacitor, connected in parallel between a first input terminal and an output terminal of the first operational amplifier; a second switch connected between a first input terminal and an output terminal of the second operational amplifier; a third switch connected between the first input terminal of the first operational amplifier and the input of the error compensator; a fourth switch connected between the output terminal of the second operational amplifier and the output of the error compensator; a first storage unit connected between the output terminal of the first operational amplifier and the first input terminal of the second operational amplifier; and a second storage unit connected between the first input terminal and the output terminal of the second operational amplifier, a fifth switch, a third capacitor and a sixth switch, coupled in series between the output terminal of the first operational amplifier and the first input terminal of the second operational amplifier; and a seventh switch, a fourth capacitor and an eighth switch, coupled in parallel to the fifth switch, the third capacitor and the sixth switch, between the output terminal of the first operational amplifier and the first input terminal of the second operational amplifier, wherein the fifth and sixth switches (SW5 and SW6) are configured to be turned on during a first period in the period in which the first and second switches (SW1 and SW2) are turned on, and the seventh and eighth switches (SW7 and SW8) are configured to be turned on during a second period not overlapping with the first period in the period in which the first and second switches (SW1 and SW2) are turned on and/or wherein the fourth switch is configured to be also set to be in a turn-on state during the first and second periods; and a second capacitor coupled between first and second nodes (N10 and N11); a ninth switch coupled between the second node and the first input terminal of the second operational amplifier; a tenth switch coupled between the first node and the output terminal of the second operational amplifier; an eleventh switch coupled between the first node and the first input terminal of the second operational amplifier; and a twelfth switch coupled between the second node and the output terminal of the second operational amplifier.