A non-volatile semiconductor storage device, comprising: a memory array; a plurality of data holding circuits (120-0∼120-7), wherein in the data holding circuits (120-0∼120-7), each of the data holding circuits (120-0∼120-7) comprises a circuit connected to the memory array through a bit line and holding data to be programmed in a selected page, and an output circuit outputting whether a verification is qualified or not in a programming verification; and a determination circuit, connected to the output circuit of each of the data holding circuits (120-0∼120-7), and determining whether verification results of the plurality of data holding circuits (120-0∼120-7) match a permissible number of unqualified bits, wherein the determination circuit comprises: a first circuit generating a detection voltage corresponding to whether the verifications of the data holding circuits (120-0∼120-7) are qualified or not based on reference currents (Iref) corresponding to the number of unqualified bits, a second circuit generating a reference voltage (Vref) based on reference currents (Iref) corresponding to the permissible number of unqualified bits, and a comparison circuit comparing the detection voltage with the reference voltage (Vref), wherein the comparison circuit outputs a signal indicating whether the verification results of the data holding circuits (120-0∼120-7) are the permissible number of unqualified bits, wherein the output circuit of the data holding circuit (120-0∼120-7) comprises a transistor that a current equivalent to the reference current (Iref) of the second circuit when the result of the verification is unqualified flows through, the non-volatile semiconductor storage device being characterised in that one of the first circuit and the second circuit comprises a plurality of transistors that the reference current (Iref) flows through, and that the number of operable transistors of the plurality of transistors is selected in correspondence with the permissible number of unqualified bits. a memory array; a plurality of data holding circuits (120-0∼120-7), wherein in the data holding circuits (120-0∼120-7), each of the data holding circuits (120-0∼120-7) comprises a circuit connected to the memory array through a bit line and holding data to be programmed in a selected page, and an output circuit outputting whether a verification is qualified or not in a programming verification; and a determination circuit, connected to the output circuit of each of the data holding circuits (120-0∼120-7), and determining whether verification results of the plurality of data holding circuits (120-0∼120-7) match a permissible number of unqualified bits, wherein the determination circuit comprises: a first circuit generating a detection voltage corresponding to whether the verifications of the data holding circuits (120-0∼120-7) are qualified or not based on reference currents (Iref) corresponding to the number of unqualified bits, a second circuit generating a reference voltage (Vref) based on reference currents (Iref) corresponding to the permissible number of unqualified bits, and a comparison circuit comparing the detection voltage with the reference voltage (Vref), wherein the comparison circuit outputs a signal indicating whether the verification results of the data holding circuits (120-0∼120-7) are the permissible number of unqualified bits, wherein the output circuit of the data holding circuit (120-0∼120-7) comprises a transistor that a current equivalent to the reference current (Iref) of the second circuit when the result of the verification is unqualified flows through, the non-volatile semiconductor storage device being characterised in that one of the first circuit and the second circuit comprises a plurality of transistors that the reference current (Iref) flows through, and that the number of operable transistors of the plurality of transistors is selected in correspondence with the permissible number of unqualified bits.