A back contact structure of a solar cell, the back contact structure comprising: a silicon substrate, the silicon substrate comprising a back surface comprising a plurality of recesses disposed at intervals; a plurality of first conductive regions and a plurality of second conductive regions disposed alternately on the back surface of the silicon substrate; each first conductive region comprising a first dielectric layer and a first doped region which are disposed successively, and each second conductive region comprising a second doped region; a second dielectric layer disposed between the plurality of first conductive regions and the plurality of second conductive regions, wherein the second dielectric layer is at least one in number; and a conductive layer disposed on the plurality of first conductive regions and the plurality of second conductive regions; wherein: the first doped region is a P-type doped region, and the second doped region is an N-type doped layer; or the first doped region is an N-type doped region, and the second doped region is a P-type doped layer; the first doped region comprises doped polycrystalline silicon; and the first dielectric layer comprises a tunnelling oxide layer; wherein the plurality of first conductive regions is respectively disposed inside the plurality of recesses and the plurality of second conductive regions is disposed outside the plurality of recesses; characterized in that a depth of the plurality of recesses is greater than a thickness of each first conductive region, whereby each first conductive region and both the first dielectric layer and the first doped layer are enclosed inside each recess, and the second conductive regions are disposed only on parts of the regions outside the recesses such that the first conductive regions and the second conductive regions are spaced apart from each other in a horizontal direction by portions of the silicon substrate and the second dielectric layer over the portions of the silicon substrate. a silicon substrate, the silicon substrate comprising a back surface comprising a plurality of recesses disposed at intervals; a plurality of first conductive regions and a plurality of second conductive regions disposed alternately on the back surface of the silicon substrate; each first conductive region comprising a first dielectric layer and a first doped region which are disposed successively, and each second conductive region comprising a second doped region; a second dielectric layer disposed between the plurality of first conductive regions and the plurality of second conductive regions, wherein the second dielectric layer is at least one in number; and a conductive layer disposed on the plurality of first conductive regions and the plurality of second conductive regions; wherein: the first doped region is a P-type doped region, and the second doped region is an N-type doped layer; or the first doped region is an N-type doped region, and the second doped region is a P-type doped layer; the first doped region comprises doped polycrystalline silicon; and the first dielectric layer comprises a tunnelling oxide layer; wherein the plurality of first conductive regions is respectively disposed inside the plurality of recesses and the plurality of second conductive regions is disposed outside the plurality of recesses; characterized in that a depth of the plurality of recesses is greater than a thickness of each first conductive region, whereby each first conductive region and both the first dielectric layer and the first doped layer are enclosed inside each recess, and the second conductive regions are disposed only on parts of the regions outside the recesses such that the first conductive regions and the second conductive regions are spaced apart from each other in a horizontal direction by portions of the silicon substrate and the second dielectric layer over the portions of the silicon substrate. the first doped region is a P-type doped region, and the second doped region is an N-type doped layer; or the first doped region is an N-type doped region, and the second doped region is a P-type doped layer; the first doped region comprises doped polycrystalline silicon; and the first dielectric layer comprises a tunnelling oxide layer; wherein the plurality of first conductive regions is respectively disposed inside the plurality of recesses and the plurality of second conductive regions is disposed outside the plurality of recesses; characterized in that a depth of the plurality of recesses is greater than a thickness of each first conductive region, whereby each first conductive region and both the first dielectric layer and the first doped layer are enclosed inside each recess, and the second conductive regions are disposed only on parts of the regions outside the recesses such that the first conductive regions and the second conductive regions are spaced apart from each other in a horizontal direction by portions of the silicon substrate and the second dielectric layer over the portions of the silicon substrate.