A shift register unit, comprising a shift drive sub-circuit, a pull-down sub-circuit and an output sub-circuit, wherein the shift drive sub-circuit is coupled to a signal input terminal (INPUT), a first clock signal terminal, a second clock signal terminal and a first signal output terminal, and the shift drive sub-circuit is configured to store a voltage of the signal input terminal (INPUT) under a control of the first clock signal terminal, and to output a voltage of the second clock signal terminal to the first signal output terminal under a control of the signal input terminal (INPUT), the first clock signal terminal, and the second clock signal terminal; the output sub-circuit is coupled to the first signal output terminal, a first voltage terminal and a second signal output terminal, and the output sub-circuit is configured to output a voltage of the first voltage terminal to the second signal output terminal under a control of the first signal output terminal; the pull-down sub-circuit is coupled to the first clock signal terminal, a second voltage terminal (VSSL), a third voltage terminal, the first signal output terminal and the second signal output terminal, and the pull-down sub-circuit is configured to pull down voltages of the first signal output terminal and the second signal output terminal to the second voltage terminal (VSSL) and the third voltage terminal respectively under the control of the first clock signal terminal; wherein the shift drive sub-circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a capacitor; a gate of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the signal input terminal (INPUT), and a second electrode of the first transistor is coupled to a second electrode of the second transistor; a gate of the second transistor is coupled to the first clock signal terminal, and a first electrode of the second transistor is coupled to a gate of the fourth transistor; a gate of the third transistor is coupled to the gate of the fourth transistor, a first electrode of the third transistor is coupled to the second clock signal terminal, and a second electrode of the third transistor is coupled to the second electrode of the first transistor; a first electrode of the fourth transistor is coupled to the second clock signal terminal and a second electrode of the fourth transistor is coupled to the first signal output terminal; one end of the capacitor is coupled to the gate of the fourth transistor, and another end of the capacitor is coupled to the second electrode of the fourth transistor; the pull-down sub-circuit comprises a seventh transistor and an eighth transistor; a gate of the seventh transistor is coupled to the first clock signal terminal, a first electrode of the seventh transistor is coupled to the first signal output terminal, and a second electrode of the seventh transistor is coupled to the second voltage terminal (VSSL); a gate of the eighth transistor is coupled to the first clock signal terminal, a first electrode of the eighth transistor is coupled to the second signal output terminal, and a second electrode of the eighth transistor is coupled to the third voltage terminal; the output sub-circuit comprises a ninth transistor, a gate of the ninth transistor is coupled to the first signal output terminal, a first electrode of the ninth transistor is coupled to the first voltage terminal, and a second electrode of the ninth transistor is coupled to the second signal output terminal; an amplitude of a voltage output from the second voltage terminal (VSSL) is higher than an amplitude of a voltage output from the third voltage terminal; the shift register unit is configured to output a signal to a next-stage of shift register unit via the first signal output terminal, and to output a gate scanning signal via the second signal output terminal; characterized in that: the shift register unit further comprises a repair sub-circuit, wherein the repair sub-circuit is coupled to the signal input terminal (INPUT), the first clock signal terminal, the second clock signal terminal and the first signal output terminal; the repair sub-circuit is configured to output a voltage of the second clock signal terminal to the first signal output terminal under a control of the signal input terminal (INPUT), the first clock signal terminal and the second clock signal terminal; wherein the repair sub-circuit comprises a fifth transistor and a sixth transistor; a gate of the fifth transistor is coupled to the first clock signal terminal, a first electrode of the fifth transistor is coupled to the signal input terminal (INPUT), and a second electrode of the fifth transistor is coupled to a gate of the sixth transistor; a first electrode of the sixth transistor is coupled to the second clock signal terminal, and a second electrode of the sixth transistor is coupled to the first signal output terminal; a width to length ratio of each of the fifth transistor and the sixth transistor is 18% to 22% of a width to length ratio of the fourth transistor