A polar coder circuit (600, 1600) comprising one or more datapaths, the polar coder circuit (600, 1600) configured to perform one of a polar encoding operation or a polar Successive Cancellation, SC, decoding operation, wherein the polar coder circuit (600, 1600) is characterised by: a decomposition of a polar code graph into multiple columns, each column comprising a different set of one or more consecutive stages, s d, and where each column is further decomposed into one or more sub-graphs and each operation of the one or more datapaths (601, 701, 1601, 1602, 1603) processes one sub-graph of one column, where the one or more sub-graphs in a particular column contain mutually exclusive sets of XORs and interconnections; at least one logical three-dimensional, 3D, memory block (602, 603, 1605) coupled to the one or more datapaths (601, 1601, 1602, 1603) and comprising two or more random access memories, RAMs, (1107, 2807) of the at least one logical 3D memory block as a first dimension, wherein the two or more RAMs (1107, 2807) comprise(s) a width of two or more bits as a second dimension and a depth of two or more addresses as a third dimension and wherein the first dimension or the second dimension has a size 2 s d, wherein the other of the first dimension and second dimension has a size n d, where n d is a number of bits in an input or an output of the one or more datapaths (601, 1601, 1602, 1603); and a controller (604, 1606) coupled to the at least one logical 3D memory block (602, 603, 1605) and configured to direct the one or more datapaths (601, 1601, 1602, 1603) to process bits that are read from the at least one logical 3D memory block (602, 603, 1605) across one of the first dimension and the second dimension, and configured to direct the one or more datapaths (601, 1601, 1602, 1603) to write processed bits to the at least one logical 3D memory block (602, 603, 1605) across the other of the first dimension and the second dimension, and: wherein each group of processed n d bits provided at an output of the one or more datapaths is seamlessly written in a single write operation to the at least one logical 3D memory block (602, 603); wherein each group of processed n d bits required at an input of the datapath of the one or more datapaths is seamlessly obtainable in a single read operation from the at least one logical 3D memory block (602, 603). a decomposition of a polar code graph into multiple columns, each column comprising a different set of one or more consecutive stages, s d, and where each column is further decomposed into one or more sub-graphs and each operation of the one or more datapaths (601, 701, 1601, 1602, 1603) processes one sub-graph of one column, where the one or more sub-graphs in a particular column contain mutually exclusive sets of XORs and interconnections; at least one logical three-dimensional, 3D, memory block (602, 603, 1605) coupled to the one or more datapaths (601, 1601, 1602, 1603) and comprising two or more random access memories, RAMs, (1107, 2807) of the at least one logical 3D memory block as a first dimension, wherein the two or more RAMs (1107, 2807) comprise(s) a width of two or more bits as a second dimension and a depth of two or more addresses as a third dimension and wherein the first dimension or the second dimension has a size 2 s d, wherein the other of the first dimension and second dimension has a size n d, where n d is a number of bits in an input or an output of the one or more datapaths (601, 1601, 1602, 1603); and a controller (604, 1606) coupled to the at least one logical 3D memory block (602, 603, 1605) and configured to direct the one or more datapaths (601, 1601, 1602, 1603) to process bits that are read from the at least one logical 3D memory block (602, 603, 1605) across one of the first dimension and the second dimension, and configured to direct the one or more datapaths (601, 1601, 1602, 1603) to write processed bits to the at least one logical 3D memory block (602, 603, 1605) across the other of the first dimension and the second dimension, and: wherein each group of processed n d bits provided at an output of the one or more datapaths is seamlessly written in a single write operation to the at least one logical 3D memory block (602, 603); wherein each group of processed n d bits required at an input of the datapath of the one or more datapaths is seamlessly obtainable in a single read operation from the at least one logical 3D memory block (602, 603).