A sigma-delta modulator comprising at least first (101-MOD1) and second (101-MOD2) analog integration circuits each comprising at least one analog integrator (Ia 1, Ia 2), each analog integrator (Ia 1, Ia 2) comprising an operational amplifier having its input coupled to its output by an integration capacitor (Ci1, Ci2, Ci3), the first analog integration circuit (101-MOD1) having an output node connected to an input node of the second analog integration circuit (101-MOD2), the modulator further comprising a coupling capacitor (Cc) different from said integration capacitors (Ci1, Ci2, Ci3), the coupling capacitor (Cc) having a first electrode connected to an output node of the second analog integration circuit (101-MOD2), and a comparator having its input coupled to the first electrode of the coupling capacitor (Cc) by a first switch (Φ1d) and to a second electrode of the coupling capacitor (Cc) by a second switch (Φ2d), the modulator being capable of implementing a phase of conversion of an analog input signal into an output bit train, the conversion phase comprising a plurality of operating cycles, each divided into first and second successive phases, wherein, for each cycle (k) of the conversion phase: during the first phase of the cycle: - the first analog integration circuit (101-MOD1) integrates a signal representative of the difference between the analog input signal and a first feedback signal, and supplies an output signal S1 on its output node; - the second analog integration circuit (101-MOD2) only integrates signal S1; - the first (Φ1d) and second (Φ2d) switches are respectively turned off and on, so that only signal S1 is transmitted to the input of the comparator via the coupling capacitor (Cc); and - a binary value Y1 corresponding to 1-bit quantized signal S1 is read from the output of the comparator, and, during the second phase of the cycle: - the second analog integration circuit (101-MOD2) integrates a signal representative of the difference between a second feedback signal and binary value Y1; the first (Φ1d) and second (Φ2d) switches are respectively turned on and off, so that the output signal of the second analog integration circuit (101-MOD2) is applied to the input of the comparator; and a binary value Y2 corresponding to the 1-bit quantized output signal of the second analog integration circuit (101-MOD2) is read from the output of the comparator, values Y1 and Y2 being then combined into one output bit of the modulator. during the first phase of the cycle: - the first analog integration circuit (101-MOD1) integrates a signal representative of the difference between the analog input signal and a first feedback signal, and supplies an output signal S1 on its output node; - the second analog integration circuit (101-MOD2) only integrates signal S1; - the first (Φ1d) and second (Φ2d) switches are respectively turned off and on, so that only signal S1 is transmitted to the input of the comparator via the coupling capacitor (Cc); and - a binary value Y1 corresponding to 1-bit quantized signal S1 is read from the output of the comparator, - the first analog integration circuit (101-MOD1) integrates a signal representative of the difference between the analog input signal and a first feedback signal, and supplies an output signal S1 on its output node; - the second analog integration circuit (101-MOD2) only integrates signal S1; - the first (Φ1d) and second (Φ2d) switches are respectively turned off and on, so that only signal S1 is transmitted to the input of the comparator via the coupling capacitor (Cc); and - a binary value Y1 corresponding to 1-bit quantized signal S1 is read from the output of the comparator, and, during the second phase of the cycle: - the second analog integration circuit (101-MOD2) integrates a signal representative of the difference between a second feedback signal and binary value Y1; - the second analog integration circuit (101-MOD2) integrates a signal representative of the difference between a second feedback signal and binary value Y1; the first (Φ1d) and second (Φ2d) switches are respectively turned on and off, so that the output signal of the second analog integration circuit (101-MOD2) is applied to the input of the comparator; and a binary value Y2 corresponding to the 1-bit quantized output signal of the second analog integration circuit (101-MOD2) is read from the output of the comparator, values Y1 and Y2 being then combined into one output bit of the modulator.