A substrate having an overlay mark for determining the relative shift between two or more successive layers of the substrate or between two or more separately generated patterns on a single layer of the substrate, said layer(s) comprising integrated circuit pattern features, the overlay mark comprising: at least one test pattern for determining the relative shift between a first and a second layer of the substrate, or between a first and a second separately generated pattern on the single layer of the substrate, in a first direction, the test pattern having a first set of working zones (72A, 72D) and a second set of working zones (72B, 72C), the first set of working zones (72A, 72D) being disposed on the first layer of the substrate, or formed by the first pattern on the single layer, and having at least two working zones (72A, 72D) diagonally opposed and spatially offset relative to one another, the second set of working zones (72B, 72C) being disposed on the second layer of the substrate, or formed by the second pattern on the single layer, and having at least two working zones (72B, 72C) diagonally opposed and spatially offset relative to one another; wherein the substrate further includes a periodic structure positioned within each of the working zones, each of the periodic structures including a plurality of coarsely segmented elements; characterised in that: the plurality of coarsely segmented elements are formed by a plurality of finely segmented elements that have dimensions comparable to the integrated circuit critical dimensions; and the coarsely and finely segmented elements (76, 78) comprise coarsely segmented lines that are formed by a plurality of finely segmented bars and at least one dark field, the plurality of coarsely segmented lines being separated by a plurality of finely segmented bars and at least one clear field. at least one test pattern for determining the relative shift between a first and a second layer of the substrate, or between a first and a second separately generated pattern on the single layer of the substrate, in a first direction, the test pattern having a first set of working zones (72A, 72D) and a second set of working zones (72B, 72C), the first set of working zones (72A, 72D) being disposed on the first layer of the substrate, or formed by the first pattern on the single layer, and having at least two working zones (72A, 72D) diagonally opposed and spatially offset relative to one another, the second set of working zones (72B, 72C) being disposed on the second layer of the substrate, or formed by the second pattern on the single layer, and having at least two working zones (72B, 72C) diagonally opposed and spatially offset relative to one another; wherein the substrate further includes a periodic structure positioned within each of the working zones, each of the periodic structures including a plurality of coarsely segmented elements; characterised in that: the plurality of coarsely segmented elements are formed by a plurality of finely segmented elements that have dimensions comparable to the integrated circuit critical dimensions; and the coarsely and finely segmented elements (76, 78) comprise coarsely segmented lines that are formed by a plurality of finely segmented bars and at least one dark field, the plurality of coarsely segmented lines being separated by a plurality of finely segmented bars and at least one clear field. the plurality of coarsely segmented elements are formed by a plurality of finely segmented elements that have dimensions comparable to the integrated circuit critical dimensions; and the coarsely and finely segmented elements (76, 78) comprise coarsely segmented lines that are formed by a plurality of finely segmented bars and at least one dark field, the plurality of coarsely segmented lines being separated by a plurality of finely segmented bars and at least one clear field.