A memory system comprising: a memory controller; and a first memory device and a second memory device, each comprising: a transmitter; and circuitry operable in a write calibration mode as a phase detector, the circuitry comprising: a first input to receive a clock signal; a second input to receive a calibration sequence from the memory controller; and an output to generate a signal representing a phase difference between the clock signal and the received calibration sequence; wherein the transmitter transmits the generated signal to the memory controller; wherein the memory controller is coupled to the first and second memory devices (12a, 12b), the memory controller including calibration circuitry to adjust a write timing offset for each of the first memory device and the second memory device, wherein each write timing offset corresponds to the respective signals representing the phase difference, received from the respective first and second memory devices (12a, 12b), wherein the memory controller is further operable in a read calibration mode to determine a phase difference between a received clock signal and a second calibration sequence received from the respective first and second memory devices (12a, 12b) and to adjust a read timing offset for each of the first memory device and the second memory device based on the respective phase differences. a memory controller; and a first memory device and a second memory device, each comprising: a transmitter; and circuitry operable in a write calibration mode as a phase detector, the circuitry comprising: a first input to receive a clock signal; a second input to receive a calibration sequence from the memory controller; and an output to generate a signal representing a phase difference between the clock signal and the received calibration sequence; wherein the transmitter transmits the generated signal to the memory controller; wherein the memory controller is coupled to the first and second memory devices (12a, 12b), the memory controller including calibration circuitry to adjust a write timing offset for each of the first memory device and the second memory device, wherein each write timing offset corresponds to the respective signals representing the phase difference, received from the respective first and second memory devices (12a, 12b), wherein the memory controller is further operable in a read calibration mode to determine a phase difference between a received clock signal and a second calibration sequence received from the respective first and second memory devices (12a, 12b) and to adjust a read timing offset for each of the first memory device and the second memory device based on the respective phase differences. a transmitter; and circuitry operable in a write calibration mode as a phase detector, the circuitry comprising: a first input to receive a clock signal; a second input to receive a calibration sequence from the memory controller; and an output to generate a signal representing a phase difference between the clock signal and the received calibration sequence; wherein the transmitter transmits the generated signal to the memory controller; wherein the memory controller is coupled to the first and second memory devices (12a, 12b), the memory controller including calibration circuitry to adjust a write timing offset for each of the first memory device and the second memory device, wherein each write timing offset corresponds to the respective signals representing the phase difference, received from the respective first and second memory devices (12a, 12b), wherein the memory controller is further operable in a read calibration mode to determine a phase difference between a received clock signal and a second calibration sequence received from the respective first and second memory devices (12a, 12b) and to adjust a read timing offset for each of the first memory device and the second memory device based on the respective phase differences. a first input to receive a clock signal; a second input to receive a calibration sequence from the memory controller; and an output to generate a signal representing a phase difference between the clock signal and the received calibration sequence; wherein the transmitter transmits the generated signal to the memory controller; wherein the memory controller is coupled to the first and second memory devices (12a, 12b), the memory controller including calibration circuitry to adjust a write timing offset for each of the first memory device and the second memory device, wherein each write timing offset corresponds to the respective signals representing the phase difference, received from the respective first and second memory devices (12a, 12b), wherein the memory controller is further operable in a read calibration mode to determine a phase difference between a received clock signal and a second calibration sequence received from the respective first and second memory devices (12a, 12b) and to adjust a read timing offset for each of the first memory device and the second memory device based on the respective phase differences.