A memory circuit comprising a plurality of elementary cells (10, 70, 80) arranged in an array of rows and columns and a control circuit, wherein each elementary cell comprises: a first data bit storage node (BLTI); a first transistor coupling the first storage node (BLTI) to a first conductive track (HBLT_VWLT) and having its gate coupled to a second conductive track (HWL_VBL); and second and third transistors series-coupled between a first node (VGNDT) of application of a reference potential and a third conductive track, the gate of the second transistor being coupled to the first storage node (BLTI) and the gate of the third transistor being coupled to a fourth conductive track (RWLT), wherein the elementary cells of a same row share a same second conductive track (HWL VBL) and a same third conductive track and the cells of a same column share a same first conductive track (HBLT VWLT) and a same fourth conductive track (RWLT), and wherein the control circuit is capable of implementing an operation of vertical reading of a word from a column of the array, comprising: applying a signal for controlling to the on state the third transistor to the fourth conductive track (RWLT) of the column containing the word to be read; and reading the bits of the word from the third conductive tracks of the rows containing the word to be read, characterized in that the control circuit is further capable of implementing an operation of horizontal reading of a word from a row of the array, comprising: applying a signal for controlling to the on state the first transistor to the second conductive track (HWL_VBL) of the row containing the word to be read; and reading the bits of the word from the first conductive tracks (HBLT_VWLT) of the columns containing the word to be read. a first data bit storage node (BLTI); a first transistor coupling the first storage node (BLTI) to a first conductive track (HBLT_VWLT) and having its gate coupled to a second conductive track (HWL_VBL); and second and third transistors series-coupled between a first node (VGNDT) of application of a reference potential and a third conductive track, the gate of the second transistor being coupled to the first storage node (BLTI) and the gate of the third transistor being coupled to a fourth conductive track (RWLT), wherein the elementary cells of a same row share a same second conductive track (HWL VBL) and a same third conductive track and the cells of a same column share a same first conductive track (HBLT VWLT) and a same fourth conductive track (RWLT), and wherein the control circuit is capable of implementing an operation of vertical reading of a word from a column of the array, comprising: applying a signal for controlling to the on state the third transistor to the fourth conductive track (RWLT) of the column containing the word to be read; and reading the bits of the word from the third conductive tracks of the rows containing the word to be read, applying a signal for controlling to the on state the third transistor to the fourth conductive track (RWLT) of the column containing the word to be read; and reading the bits of the word from the third conductive tracks of the rows containing the word to be read, characterized in that the control circuit is further capable of implementing an operation of horizontal reading of a word from a row of the array, comprising: applying a signal for controlling to the on state the first transistor to the second conductive track (HWL_VBL) of the row containing the word to be read; and reading the bits of the word from the first conductive tracks (HBLT_VWLT) of the columns containing the word to be read. applying a signal for controlling to the on state the first transistor to the second conductive track (HWL_VBL) of the row containing the word to be read; and reading the bits of the word from the first conductive tracks (HBLT_VWLT) of the columns containing the word to be read.