A level shifter configured to control a high voltage device capable of withstanding a voltage higher than a first voltage, comprising: a circuital arrangement comprising transistor devices, each transistor device configured to withstand a second voltage substantially lower than the first voltage, the circuital arrangement configured to operate between a first switching voltage and a second switching voltage (Vdd2+SW); a first supply terminal of the circuital arrangement, configured to carry the first switching voltage, the first switching voltage switching between a reference voltage and the first voltage; a second supply terminal of the circuital arrangement, configured to carry the second switching voltage as a function of the first switching voltage, the second switching voltage substantially corresponding to a sum of the first switching voltage and the second voltage; a first and second input terminals of the circuital arrangement, the first and second input terminals configured to receive a first (CUb) and a second (CDb) input timing control signals, respectively, for controlling the high voltage device, the first and second input timing control signals being coupled to the transistor devices of the circuital arrangement by way of respective first (C1A, C1B) and second (C2A, C2B) capacitive couplings configured to detect transitions of the first and second input timing control signals, respectively, wherein each of the respective first and second capacitive couplings comprises two series connected capacitors and a common node between the series connected capacitors, the common node configured to receive a respective one of the first and second input timing control signals; and an output terminal of the circuital arrangement, the output terminal configured to provide an output timing control signal (DN, UP, HS_out) at a voltage higher than the first switching voltage to the high voltage device, the output timing control signal being based on the coupled input timing control signals, wherein the second input timing control signal is an inverted version of the first input timing control signal. a circuital arrangement comprising transistor devices, each transistor device configured to withstand a second voltage substantially lower than the first voltage, the circuital arrangement configured to operate between a first switching voltage and a second switching voltage (Vdd2+SW); a first supply terminal of the circuital arrangement, configured to carry the first switching voltage, the first switching voltage switching between a reference voltage and the first voltage; a second supply terminal of the circuital arrangement, configured to carry the second switching voltage as a function of the first switching voltage, the second switching voltage substantially corresponding to a sum of the first switching voltage and the second voltage; a first and second input terminals of the circuital arrangement, the first and second input terminals configured to receive a first (CUb) and a second (CDb) input timing control signals, respectively, for controlling the high voltage device, the first and second input timing control signals being coupled to the transistor devices of the circuital arrangement by way of respective first (C1A, C1B) and second (C2A, C2B) capacitive couplings configured to detect transitions of the first and second input timing control signals, respectively, wherein each of the respective first and second capacitive couplings comprises two series connected capacitors and a common node between the series connected capacitors, the common node configured to receive a respective one of the first and second input timing control signals; and an output terminal of the circuital arrangement, the output terminal configured to provide an output timing control signal (DN, UP, HS_out) at a voltage higher than the first switching voltage to the high voltage device, the output timing control signal being based on the coupled input timing control signals, wherein the second input timing control signal is an inverted version of the first input timing control signal.