A decision feedback equalization circuit (100, 300) comprising: a data input (DQIN, dq) to receive a data signal; a clock input to receive a clock signal; a complementary clock input to receive a complement of the clock signal; a set (vref<3:0>) of reference inputs; a first set (305-0-i, i = 1, 2, 3, 4) of sense amplifier latches, the first set comprising at least two sense amplifier latches, each sense amplifier latch (305-0-i) of the first set (305-0-i, i = 1, 2, 3, 4) coupled to the data input (dq) and coupled to a respective reference input of the set (vref<3:0>) of the reference inputs, each sense amplifier latch (305-0-i) of the first set (305-0-i, i = 1, 2, 3, 4)coupled by a respective logic circuit (303-0-i) to receive the clock signal in response to enablement by the respective logic circuit(303-0-i), each sense amplifier latch of the first set having two outputs yp and ym, wherein the yp outputs for each sense amplifier latch of the first set are wired together to provide output yp0 and the outputs ym from the sense amplifier latches of the first set are wired together to provide output ym0; a second set (305-1-i, i = 1, 2, 3, 4) of sense amplifier latches, the second set comprising at least two sense amplifier latches, each sense amplifier latch (305-1-i) of the second set (305-1-i, i = 1, 2, 3, 4) coupled to the data input (dq) and coupled to a respective reference input of the set (vref<3:0>) of the reference inputs, each sense amplifier latch (305-1- i) of the second set (305-1- i, i = 1, 2, 3, 4) coupled by a respective logic circuit (303-1- i) to receive the complement of the clock signal in response to enablement by the respective logic circuit(303-1- i), each sense amplifier latch of the second set having two outputs yp and ym, wherein the yp outputs for each sense amplifier latch of the second set are wired together to provide output yp1 and the outputs ym from the sense amplifier latches of the second set are wired together to provide output ym1; and feedback loops to provide first enable signals (en0<3:0>) to the logic circuits (303-0- i) to the first set (305-0- i, i = 1, 2, 3, 4) of sense amplifier latches based on outputs yp1 and ym1 of the second set (305-1- i, i = 1, 2, 3, 4) of sense amplifier latches and to provide second enable signals (en1<3:0>) to the logic circuits (303-1- i) to the second set (305-1- i, i = 1, 2, 3, 4) of sense amplifier latches based on outputs yp0 and ym0 of the first set (305-0- i, i = 1, 2, 3, 4) of sense amplifier latches, the outputs of the first set (305-0- i, i = 1, 2, 3, 4) and the second set (305-1- i, i = 1, 2, 3, 4) of sense amplifier latches corresponding to previous bits output from the decision feedback equalizer circuit (100, 300). a data input (DQIN, dq) to receive a data signal; a clock input to receive a clock signal; a complementary clock input to receive a complement of the clock signal; a set (vref<3:0>) of reference inputs; a first set (305-0-i, i = 1, 2, 3, 4) of sense amplifier latches, the first set comprising at least two sense amplifier latches, each sense amplifier latch (305-0-i) of the first set (305-0-i, i = 1, 2, 3, 4) coupled to the data input (dq) and coupled to a respective reference input of the set (vref<3:0>) of the reference inputs, each sense amplifier latch (305-0-i) of the first set (305-0-i, i = 1, 2, 3, 4)coupled by a respective logic circuit (303-0-i) to receive the clock signal in response to enablement by the respective logic circuit(303-0-i), each sense amplifier latch of the first set having two outputs yp and ym, wherein the yp outputs for each sense amplifier latch of the first set are wired together to provide output yp0 and the outputs ym from the sense amplifier latches of the first set are wired together to provide output ym0; a second set (305-1-i, i = 1, 2, 3, 4) of sense amplifier latches, the second set comprising at least two sense amplifier latches, each sense amplifier latch (305-1-i) of the second set (305-1-i, i = 1, 2, 3, 4) coupled to the data input (dq) and coupled to a respective reference input of the set (vref<3:0>) of the reference inputs, each sense amplifier latch (305-1- i) of the second set (305-1- i, i = 1, 2, 3, 4) coupled by a respective logic circuit (303-1- i) to receive the complement of the clock signal in response to enablement by the respective logic circuit(303-1- i), each sense amplifier latch of the second set having two outputs yp and ym, wherein the yp outputs for each sense amplifier latch of the second set are wired together to provide output yp1 and the outputs ym from the sense amplifier latches of the second set are wired together to provide output ym1; and feedback loops to provide first enable signals (en0<3:0>) to the logic circuits (303-0- i) to the first set (305-0- i, i = 1, 2, 3, 4) of sense amplifier latches based on outputs yp1 and ym1 of the second set (305-1- i, i = 1, 2, 3, 4) of sense amplifier latches and to provide second enable signals (en1<3:0>) to the logic circuits (303-1- i) to the second set (305-1- i, i = 1, 2, 3, 4) of sense amplifier latches based on outputs yp0 and ym0 of the first set (305-0- i, i = 1, 2, 3, 4) of sense amplifier latches, the outputs of the first set (305-0- i, i = 1, 2, 3, 4) and the second set (305-1- i, i = 1, 2, 3, 4) of sense amplifier latches corresponding to previous bits output from the decision feedback equalizer circuit (100, 300).