An apparatus (100/200) comprising a memory controller, said memory controller comprising: a command queue for receiving and storing decoded memory access requests, said decoded memory access requests including a row; and an arbiter for picking said memory access requests from said command queue based on a plurality of criteria and for providing picked memory access requests to a memory channel (130/140), wherein: said arbiter comprises a first streak counter for keeping track of a number of consecutive memory access requests of a first type, that said arbiter picks from said command queue, said first type being page hit accesses to a single bank in the presence of other page conflicts to said single bank, said arbiter determining the presence of said other page conflicts by examining said row of memory access requests in said command queue; and when said first streak counter reaches a first threshold, said arbiter suspends picking requests of said first type and picks at least one memory access request of a second type, wherein said second type comprises page conflict requests to said single bank, and provides said at least one memory access request of said second type to said memory channel (130/140), characterized in that said number of memory access requests of said first type is a total number of write requests of a certain priority, wherein said certain priority is one of a low priority, a medium priority, and a high priority, and said memory controller stores thresholds for the number of memory access requests of said certain priority in a set of programmable registers corresponding to said low priority, said medium priority, and said high priority. a command queue for receiving and storing decoded memory access requests, said decoded memory access requests including a row; and an arbiter for picking said memory access requests from said command queue based on a plurality of criteria and for providing picked memory access requests to a memory channel (130/140), wherein: said arbiter comprises a first streak counter for keeping track of a number of consecutive memory access requests of a first type, that said arbiter picks from said command queue, said first type being page hit accesses to a single bank in the presence of other page conflicts to said single bank, said arbiter determining the presence of said other page conflicts by examining said row of memory access requests in said command queue; and when said first streak counter reaches a first threshold, said arbiter suspends picking requests of said first type and picks at least one memory access request of a second type, wherein said second type comprises page conflict requests to said single bank, and provides said at least one memory access request of said second type to said memory channel (130/140), characterized in that said number of memory access requests of said first type is a total number of write requests of a certain priority, wherein said certain priority is one of a low priority, a medium priority, and a high priority, and said memory controller stores thresholds for the number of memory access requests of said certain priority in a set of programmable registers corresponding to said low priority, said medium priority, and said high priority. said arbiter comprises a first streak counter for keeping track of a number of consecutive memory access requests of a first type, that said arbiter picks from said command queue, said first type being page hit accesses to a single bank in the presence of other page conflicts to said single bank, said arbiter determining the presence of said other page conflicts by examining said row of memory access requests in said command queue; and when said first streak counter reaches a first threshold, said arbiter suspends picking requests of said first type and picks at least one memory access request of a second type, wherein said second type comprises page conflict requests to said single bank, and provides said at least one memory access request of said second type to said memory channel (130/140), characterized in that said number of memory access requests of said first type is a total number of write requests of a certain priority, wherein said certain priority is one of a low priority, a medium priority, and a high priority, and said memory controller stores thresholds for the number of memory access requests of said certain priority in a set of programmable registers corresponding to said low priority, said medium priority, and said high priority.