A digital system comprising a processing engine, wherein the processing engine comprises: an instruction buffer operable to buffer single and compound instructions pending execution thereof; a decode mechanism (512, 514) configured to decode instructions from the instruction buffer, the decode mechanism (512, 514) being responsive to a predetermined tag in an instruction, the predetermined tag being representative of the instruction being a compound instruction formed from separate programmed memory instructions (721, 722), to decode at least first data flow control for a first programmed instruction and at least second data flow control for a second programmed instruction; and wherein the compound instruction is a compound memory access instruction formed by combining separate first and second programmed I memory access instructions (721, 722) such that a compound address field (703/704) of the compound instruction (Fig. 10) is formed at the same bit positions as an address field for a hard programmed dual memory instruction, wherein the compound address field (703/704) is decoded into first and second memory addresses (725, 728) for first and second memory address instructions respectively (721, 722), wherein combining eliminates redundant bits from the first and second programmed memory instructions equal in number to the number of bits of the predetermined tag whereby the compound instruction is exactly as long as the first and second programmed instructions, and wherein: the memory addresses in the compound address field of the compound instruction are indirect addresses and the decode mechanism (512, 514) is operable to decode the indirect addresses. an instruction buffer operable to buffer single and compound instructions pending execution thereof; a decode mechanism (512, 514) configured to decode instructions from the instruction buffer, the decode mechanism (512, 514) being responsive to a predetermined tag in an instruction, the predetermined tag being representative of the instruction being a compound instruction formed from separate programmed memory instructions (721, 722), to decode at least first data flow control for a first programmed instruction and at least second data flow control for a second programmed instruction; and wherein the compound instruction is a compound memory access instruction formed by combining separate first and second programmed I memory access instructions (721, 722) such that a compound address field (703/704) of the compound instruction (Fig. 10) is formed at the same bit positions as an address field for a hard programmed dual memory instruction, wherein the compound address field (703/704) is decoded into first and second memory addresses (725, 728) for first and second memory address instructions respectively (721, 722), wherein combining eliminates redundant bits from the first and second programmed memory instructions equal in number to the number of bits of the predetermined tag whereby the compound instruction is exactly as long as the first and second programmed instructions, and wherein: the memory addresses in the compound address field of the compound instruction are indirect addresses and the decode mechanism (512, 514) is operable to decode the indirect addresses.