An interrupt controller comprising: a plurality of group interrupt controllers (100a, 100b,...100n), the plurality of group interrupt controllers (100a, 100b...100n) comprising a plurality of first group interrupt controllers, wherein a plurality of first interrupt sources is assigned to each of the plurality of first group interrupt controllers, and wherein each of the plurality of first group interrupt controllers comprises: a group interrupt register unit receiving a plurality of interrupt source signals from said first interrupt sources; an interrupt detector coupled to the group interrupt register unit; a counter unit coupled to the interrupt detector, wherein on the first occurrence of any received interrupt source signal the counter unit, depending on a latency value assigned for the first group interrupt controller, defines a time window during which the interrupt register stores further interrupt source signals; and a group interrupt request unit coupled to the counter unit for generating a first group interrupt request signal after expiration of the time window; a group interrupt arbiter receiving the group interrupt signals from the plurality of interrupt group controllers (100a, 100b,...100n); and an interrupt request unit coupled to the group interrupt arbiter for generating an interrupt request signal. a plurality of group interrupt controllers (100a, 100b,...100n), the plurality of group interrupt controllers (100a, 100b...100n) comprising a plurality of first group interrupt controllers, wherein a plurality of first interrupt sources is assigned to each of the plurality of first group interrupt controllers, and wherein each of the plurality of first group interrupt controllers comprises: a group interrupt register unit receiving a plurality of interrupt source signals from said first interrupt sources; an interrupt detector coupled to the group interrupt register unit; a counter unit coupled to the interrupt detector, wherein on the first occurrence of any received interrupt source signal the counter unit, depending on a latency value assigned for the first group interrupt controller, defines a time window during which the interrupt register stores further interrupt source signals; and a group interrupt request unit coupled to the counter unit for generating a first group interrupt request signal after expiration of the time window; a group interrupt register unit receiving a plurality of interrupt source signals from said first interrupt sources; an interrupt detector coupled to the group interrupt register unit; a counter unit coupled to the interrupt detector, wherein on the first occurrence of any received interrupt source signal the counter unit, depending on a latency value assigned for the first group interrupt controller, defines a time window during which the interrupt register stores further interrupt source signals; and a group interrupt request unit coupled to the counter unit for generating a first group interrupt request signal after expiration of the time window; a group interrupt arbiter receiving the group interrupt signals from the plurality of interrupt group controllers (100a, 100b,...100n); and an interrupt request unit coupled to the group interrupt arbiter for generating an interrupt request signal.