An apparatus for converting a differential input signal to a single output signal (V out); said differential input signal including a first signal component and a second signal component; the apparatus comprising: (a) a first buffer structure configured for receiving said first signal component at a first input locus; said first buffer structure configured for presenting a first buffer output signal representative of said first signal component at a first buffer output locus; said first buffer structure configured for generating at least one first representative signal related to said first signal component; (b) a second buffer structure configured for receiving said second signal component at a second input locus; said second buffer structure configured for presenting a second buffer output signal representative of said second signal component at a second buffer output locus; said second buffer structure configured for generating at least one second representative signal related to said second signal component; (c) an output unit coupled for receiving said at least one first representative signal from said first buffer structure and for receiving said at least one second representative signal from said second buffer structure; said output unit configured for combining said at least one first representative signal and said at least one second representative signal to present said single output signal (Vout) at a signal output locus; said single output signal being related to a sum of said first representative signal and said second representative signal; said single output signal (Vout) having a variance range limit substantially between a first signal limit and a second signal limit; characterised in that it further comprises: (d) a control unit coupled with at least one buffer output locus of said first buffer output locus and said second buffer output locus; said control unit configured for comparing said at least one buffer output signal with a reference signal (Vref) to generate at least one control signal; said at least one control signal configured for affecting at least one signal component of said first signal component and said second signal component to reduce drift of said at least one signal component. (a) a first buffer structure configured for receiving said first signal component at a first input locus; said first buffer structure configured for presenting a first buffer output signal representative of said first signal component at a first buffer output locus; said first buffer structure configured for generating at least one first representative signal related to said first signal component; (b) a second buffer structure configured for receiving said second signal component at a second input locus; said second buffer structure configured for presenting a second buffer output signal representative of said second signal component at a second buffer output locus; said second buffer structure configured for generating at least one second representative signal related to said second signal component; (c) an output unit coupled for receiving said at least one first representative signal from said first buffer structure and for receiving said at least one second representative signal from said second buffer structure; said output unit configured for combining said at least one first representative signal and said at least one second representative signal to present said single output signal (Vout) at a signal output locus; said single output signal being related to a sum of said first representative signal and said second representative signal; said single output signal (Vout) having a variance range limit substantially between a first signal limit and a second signal limit;