A multilayer structure comprising: a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a bulk region between the front and back surfaces, and a central plane of the single crystal semiconductor handle substrate between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of 100 Ohm-cm; a charge trapping layer in interfacial contact with the front surface layer of the single crystal semiconductor handle substrate, the charge trapping layer comprising: more than one passivated semiconductor layers, wherein each of the passivated semiconductor layers comprises: (i) a semiconductor layer comprising a polycrystalline structure or an amorphous structure and comprising a material selected from the group consisting of silicon, SiGe, SiC, and Ge, and (ii) a passivation layer comprising a semiconductor nitride or a semiconductor oxide, wherein the thickness of each of the passivation layers is between about 1 Ångström and about 20 Ångströms; and a semiconductor oxide layer in interfacial contact with the charge trapping layer, the semiconductor oxide layer comprising a first bonding surface; a dielectric 2. player, the dielectric layer comprising a second bonding surface, the second bonding surface of the dielectric layer in interfacial contact with the first bonding surface of the semi conductor oxide layer; and a single crystal semiconductor device layer in interfacial contact with the dielectric layer. a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a bulk region between the front and back surfaces, and a central plane of the single crystal semiconductor handle substrate between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of 100 Ohm-cm; a charge trapping layer in interfacial contact with the front surface layer of the single crystal semiconductor handle substrate, the charge trapping layer comprising: more than one passivated semiconductor layers, wherein each of the passivated semiconductor layers comprises: (i) a semiconductor layer comprising a polycrystalline structure or an amorphous structure and comprising a material selected from the group consisting of silicon, SiGe, SiC, and Ge, and (ii) a passivation layer comprising a semiconductor nitride or a semiconductor oxide, wherein the thickness of each of the passivation layers is between about 1 Ångström and about 20 Ångströms; and (i) a semiconductor layer comprising a polycrystalline structure or an amorphous structure and comprising a material selected from the group consisting of silicon, SiGe, SiC, and Ge, and (ii) a passivation layer comprising a semiconductor nitride or a semiconductor oxide, wherein the thickness of each of the passivation layers is between about 1 Ångström and about 20 Ångströms; and a semiconductor oxide layer in interfacial contact with the charge trapping layer, the semiconductor oxide layer comprising a first bonding surface; a dielectric 2. player, the dielectric layer comprising a second bonding surface, the second bonding surface of the dielectric layer in interfacial contact with the first bonding surface of the semi conductor oxide layer; and a single crystal semiconductor device layer in interfacial contact with the dielectric layer.