Receiver configured to receive a load modulated analog input signal and to output digital data detected in the input signal, which receiver comprises: an in-phase mixer configured to mix the input signal with an in-phase carrier frequency and to provide an in-phase component of the down-converted input signal and a quadrature-phase mixer configured to mix the input signal with a quadrature-phase carrier frequency and to provide a quadrature-phase component of the down-converted input signal; an amplifier (29, 30) to amplify the in-phase component and the quadrature-phase component of the down-converted input signal; a DC block filter to remove the DC component of the in-phase component and the quadrature-phase component, characterized in that the receiver furthermore comprises: an in-phase correlator (33, 34) and a quadrature-phase correlator (35, 36) for each of the in-phase component and the quadrature-phase component to correlate the in-phase component and the quadrature-component with an in-phase component and a quadrature-phase component of a subcarrier or code clock frequency of the input signal; a combiner to combine four output signals (48 to 51) of the two in-phase correlators (33, 34) and the two quadrature-phase correlators (35, 36); a slicer to sample an output signal of the combiner at maximum energy levels to output the digital data detected in the input signal. an in-phase mixer configured to mix the input signal with an in-phase carrier frequency and to provide an in-phase component of the down-converted input signal and a quadrature-phase mixer configured to mix the input signal with a quadrature-phase carrier frequency and to provide a quadrature-phase component of the down-converted input signal; an amplifier (29, 30) to amplify the in-phase component and the quadrature-phase component of the down-converted input signal; a DC block filter to remove the DC component of the in-phase component and the quadrature-phase component, characterized in that the receiver furthermore comprises: an in-phase correlator (33, 34) and a quadrature-phase correlator (35, 36) for each of the in-phase component and the quadrature-phase component to correlate the in-phase component and the quadrature-component with an in-phase component and a quadrature-phase component of a subcarrier or code clock frequency of the input signal; a combiner to combine four output signals (48 to 51) of the two in-phase correlators (33, 34) and the two quadrature-phase correlators (35, 36); a slicer to sample an output signal of the combiner at maximum energy levels to output the digital data detected in the input signal. an in-phase correlator (33, 34) and a quadrature-phase correlator (35, 36) for each of the in-phase component and the quadrature-phase component to correlate the in-phase component and the quadrature-component with an in-phase component and a quadrature-phase component of a subcarrier or code clock frequency of the input signal; a combiner to combine four output signals (48 to 51) of the two in-phase correlators (33, 34) and the two quadrature-phase correlators (35, 36); a slicer to sample an output signal of the combiner at maximum energy levels to output the digital data detected in the input signal.