A semiconductor device comprising: first and second cores (11, 21) configured to receive power from a common power supply (POW_1), the first and second core (11, 12) being master and checker cores configured to perform a lock step; first and second power switch circuits (SW_10, SW_20) provided so as to correspond to each of the first and second cores (11, 21) and configured to control ON and OFF of the power supplied to the corresponding cores (11, 21); a compare circuit (COM_50) configured to compare output data of the first and second cores (11, 21) to detect a lock step error; a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply (POW_1) to an always-on domain to which the power from the power supply (POW_1) is constantly supplied to detect a failure of the power supply (POW_1), the core voltage monitor circuit being configured to receive power from another power supply (POW_2); first and second power switch controllers (CNT_10, CNT_20) provided so as to correspond to each of the first and second power switch circuits (SW_10, SW_20) and configured to control the corresponding power switch circuits (SW_10, SW_20); first and second monitor circuits (MON_10, MON_20) provided so as to correspond to each of the first and second power switch circuits (SW_10, SW_20) and configured to detect a failure of the corresponding power switch circuits (SW_10, SW_20); and a system controller (SYSC) configured to control the first and second power switch controllers (CNT_10, CNT_20) and receive a monitoring result of the corresponding power switch circuits (SW_10, SW_20) by the first and second monitor circuits (MON_10, MON_20), wherein the compare circuit (COM_50) and the system controller (SYSC) are located in the always-on domain. first and second cores (11, 21) configured to receive power from a common power supply (POW_1), the first and second core (11, 12) being master and checker cores configured to perform a lock step; first and second power switch circuits (SW_10, SW_20) provided so as to correspond to each of the first and second cores (11, 21) and configured to control ON and OFF of the power supplied to the corresponding cores (11, 21); a compare circuit (COM_50) configured to compare output data of the first and second cores (11, 21) to detect a lock step error; a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply (POW_1) to an always-on domain to which the power from the power supply (POW_1) is constantly supplied to detect a failure of the power supply (POW_1), the core voltage monitor circuit being configured to receive power from another power supply (POW_2); first and second power switch controllers (CNT_10, CNT_20) provided so as to correspond to each of the first and second power switch circuits (SW_10, SW_20) and configured to control the corresponding power switch circuits (SW_10, SW_20); first and second monitor circuits (MON_10, MON_20) provided so as to correspond to each of the first and second power switch circuits (SW_10, SW_20) and configured to detect a failure of the corresponding power switch circuits (SW_10, SW_20); and a system controller (SYSC) configured to control the first and second power switch controllers (CNT_10, CNT_20) and receive a monitoring result of the corresponding power switch circuits (SW_10, SW_20) by the first and second monitor circuits (MON_10, MON_20), wherein the compare circuit (COM_50) and the system controller (SYSC) are located in the always-on domain.