A control circuit for a switch mode power supply (SMPS) for eliminating an overvoltage at an output of the SMPS, comprising: an overvoltage discharge circuit comprising: an overvoltage detection circuit connectable to the SMPS for receiving an indication of output voltage (Vout) of the SMPS and for receiving a target input voltage (Vtarget), and configured for determining that the output voltage (Vout) is greater than the target input voltage (Vtarget) and providing an overvoltage indication signal; a zero crossing comparator circuit having a first input connected to the overvoltage detection circuit for receiving the overvoltage indication signal, and having a second input for receiving a voltage level present at a common connection between a first switch (PMOS) and a second switch (NMOS) of said switch mode power supply (SMPS), and having an output for outputting a negative current limit/active diode select signal that has a first voltage level when the overvoltage indication signal is larger than the voltage level present at the common connection and outputting the negative current limit/active diode select signal with a second voltage level when the overvoltage indication signal is less than the voltage level present at the common connection; and a switch control circuit comprising a first input connected to an output of the zero crossing comparator circuit, a second input connected to receive a switching signal of the first switch (PMOS), and an output connectable to a gate terminal of the second switch (NMOS) and configured for generating a switch activation/deactivation signal by transferring said switch signal to the gate terminal of the second switch (NMOS) only if the negative current limit/active diode select signal has the first voltage level; such that when the overvoltage indication signal indicates an overvoltage at the output (Vout) of the SMPS, the second switch (NMOS) can sink negative current to decrease the overvoltage at the output (Vout) of the SMPS; characterized in the control circuit is arranged to activate a local oscillator when an overvoltage (Vout) at the output of the SMPS is detected, for activating and deactivating the first and second switches (PMOS, NMOS) until the output voltage (Vout) is less than an upper limit voltage level (Vupper) for the output voltage (Vout) of the SMPS; wherein the control circuit is arranged to activate, in each clock cycle of the local oscillator, the second switch (NMOS) prior to activating the first switch (PMOS); and wherein the frequency of the local oscillator is controlled by the magnitude of the overvoltage at the output (Vout) of the SMPS. an overvoltage detection circuit connectable to the SMPS for receiving an indication of output voltage (Vout) of the SMPS and for receiving a target input voltage (Vtarget), and configured for determining that the output voltage (Vout) is greater than the target input voltage (Vtarget) and providing an overvoltage indication signal; a zero crossing comparator circuit having a first input connected to the overvoltage detection circuit for receiving the overvoltage indication signal, and having a second input for receiving a voltage level present at a common connection between a first switch (PMOS) and a second switch (NMOS) of said switch mode power supply (SMPS), and having an output for outputting a negative current limit/active diode select signal that has a first voltage level when the overvoltage indication signal is larger than the voltage level present at the common connection and outputting the negative current limit/active diode select signal with a second voltage level when the overvoltage indication signal is less than the voltage level present at the common connection; and a switch control circuit comprising a first input connected to an output of the zero crossing comparator circuit, a second input connected to receive a switching signal of the first switch (PMOS), and an output connectable to a gate terminal of the second switch (NMOS) and configured for generating a switch activation/deactivation signal by transferring said switch signal to the gate terminal of the second switch (NMOS) only if the negative current limit/active diode select signal has the first voltage level; such that when the overvoltage indication signal indicates an overvoltage at the output (Vout) of the SMPS, the second switch (NMOS) can sink negative current to decrease the overvoltage at the output (Vout) of the SMPS; characterized in the control circuit is arranged to activate a local oscillator when an overvoltage (Vout) at the output of the SMPS is detected, for activating and deactivating the first and second switches (PMOS, NMOS) until the output voltage (Vout) is less than an upper limit voltage level (Vupper) for the output voltage (Vout) of the SMPS; wherein the control circuit is arranged to activate, in each clock cycle of the local oscillator, the second switch (NMOS) prior to activating the first switch (PMOS); and wherein the frequency of the local oscillator is controlled by the magnitude of the overvoltage at the output (Vout) of the SMPS.