A circuit, comprising: a page buffer (504, 1001) comprising a plurality of portions, each of the portions being configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal; a clock path coupled to the plurality of portions of the page buffer (504, 1001) and configured to merge the plurality of clock return signals; characterized by a clock level set module coupled to the page buffer (504, 1001) and configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals, the first clock return signal corresponding to the first clock signal, wherein the clock path includes either an OR gate or a NAND gate configured to merge two clock return signals, wherein the clock level set module is further configured to set the start level of the first clock return signal based on the parity and whether the clock return signals are merged by the OR gate or the NAND gate, the circuit further characterized by a frequency divider comprising a D flip-flop with set/reset coupled to the clock level set module and configured to receive a respective clock signal (1010, clk_dp_q0 or clk _dp_q1) and generate the respective clock return signal (clk_rtn_q0, clk_rtn_q1, clk _rtn_q2, or clk _rtn_q3) based on the respective clock signal (1010, clk_dp_q0 or clk_dp_q1), wherein the clock level set module comprises an address unit configured to receive a read instruction or a read command (RD INSTR/CMD) including the starting address of the data to be read from page buffer (504, 1001) and determine the parity of the number of cycles in the respective clock signal (1010, clk_dp_q0 or clk_dp_q1) based on an address of the page buffer associated with the respective clock signal (1010, clk_dp_q0 or clk_dp_q1) and an SR unit coupled to the address unit and configured to generate an SR signal to an SR input of D flip-flop based on the parity of the number of cycles in the respective clock signal (1010, clk_dp_q0 or clk_dp_q1), wherein the number of cycles in the respective clock signal (1010, clk_dp_q0 or clk_dp_q1) corresponds to the number of data units transferred in the corresponding portion of page buffer with the respective clock signal (1010, clk_dp_q0 or clk_dp_q1). a page buffer (504, 1001) comprising a plurality of portions, each of the portions being configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal; a clock path coupled to the plurality of portions of the page buffer (504, 1001) and configured to merge the plurality of clock return signals; characterized by a clock level set module coupled to the page buffer (504, 1001) and configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals, the first clock return signal corresponding to the first clock signal, wherein the clock path includes either an OR gate or a NAND gate configured to merge two clock return signals, wherein the clock level set module is further configured to set the start level of the first clock return signal based on the parity and whether the clock return signals are merged by the OR gate or the NAND gate, the circuit further characterized by a frequency divider comprising a D flip-flop with set/reset coupled to the clock level set module and configured to receive a respective clock signal (1010, clk_dp_q0 or clk _dp_q1) and generate the respective clock return signal (clk_rtn_q0, clk_rtn_q1, clk _rtn_q2, or clk _rtn_q3) based on the respective clock signal (1010, clk_dp_q0 or clk_dp_q1), wherein the clock level set module comprises an address unit configured to receive a read instruction or a read command (RD INSTR/CMD) including the starting address of the data to be read from page buffer (504, 1001) and determine the parity of the number of cycles in the respective clock signal (1010, clk_dp_q0 or clk_dp_q1) based on an address of the page buffer associated with the respective clock signal (1010, clk_dp_q0 or clk_dp_q1) and an SR unit coupled to the address unit and configured to generate an SR signal to an SR input of D flip-flop based on the parity of the number of cycles in the respective clock signal (1010, clk_dp_q0 or clk_dp_q1), wherein the number of cycles in the respective clock signal (1010, clk_dp_q0 or clk_dp_q1) corresponds to the number of data units transferred in the corresponding portion of page buffer with the respective clock signal (1010, clk_dp_q0 or clk_dp_q1).