A method of rejecting spurs within a chip containing at least one analog function (200, 400) and at least one digital function, the spurs being timed by an associated clock signal derived from the output signal of a High Frequency, HF, fractional Phase Locked Loop, PLL, the method comprising: - determining original analog rejection bandwidths (510, 520) associated with the operation of analog functions; - identifying original spurs (512, 522) associated with the operation of at least the digital functions and capable of affecting the original analog rejection bandwidths directly or indirectly; - obtaining a final analog rejection bandwidth, representative of the aggregated original analog rejection bandwidths, based on the original analog rejection bandwidths; - obtaining final spurs (532, 533), representative of the aggregated original spurs, based on the original spurs; - determining a frequency shift of the output frequency of the HF fractional PLL adapted to reject the final spurs from the final analog rejection bandwidth; and, - controlling the HF fractional PLL so as to shift the output frequency of said HF fractional PLL by said frequency shift; wherein: - the determined shift corresponds to the shift that is obtained by shifting the final spurs within the given range P such that a weighted power spectral density, PSD, calculated on the final spurs inside the final analog rejection bandwidth is minimal; and wherein the weighted PSD calculation on the final spurs inside the final analog rejection bandwidth is based on at least one of the amplitude of the final spurs, the type of analog signal conveyed in the given analog bandwidth, physical proximity between analog and digital functions on the chip. - determining original analog rejection bandwidths (510, 520) associated with the operation of analog functions; - identifying original spurs (512, 522) associated with the operation of at least the digital functions and capable of affecting the original analog rejection bandwidths directly or indirectly; - obtaining a final analog rejection bandwidth, representative of the aggregated original analog rejection bandwidths, based on the original analog rejection bandwidths; - obtaining final spurs (532, 533), representative of the aggregated original spurs, based on the original spurs; - determining a frequency shift of the output frequency of the HF fractional PLL adapted to reject the final spurs from the final analog rejection bandwidth; and, - controlling the HF fractional PLL so as to shift the output frequency of said HF fractional PLL by said frequency shift; wherein: - the determined shift corresponds to the shift that is obtained by shifting the final spurs within the given range P such that a weighted power spectral density, PSD, calculated on the final spurs inside the final analog rejection bandwidth is minimal; and wherein the weighted PSD calculation on the final spurs inside the final analog rejection bandwidth is based on at least one of the amplitude of the final spurs, the type of analog signal conveyed in the given analog bandwidth, physical proximity between analog and digital functions on the chip. - the determined shift corresponds to the shift that is obtained by shifting the final spurs within the given range P such that a weighted power spectral density, PSD, calculated on the final spurs inside the final analog rejection bandwidth is minimal; and wherein the weighted PSD calculation on the final spurs inside the final analog rejection bandwidth is based on at least one of the amplitude of the final spurs, the type of analog signal conveyed in the given analog bandwidth, physical proximity between analog and digital functions on the chip.