A bitcell (450, 850) for a Static Random Access Memory, SRAM comprising a first pFET having a gate, a source and a drain; a second pFET having a gate, a source and a drain; a first nFET transistor having a gate, a source and a drain; a second nFET transistor having a gate, a source and a drain; a first nFET passgate transistor (440, 830) having a gate, a source and a drain; a second nFET passgate transistor (442,832) having a gate, a source and a drain; a driver; and a header pFET (430, 810) having a gate, a source and a drain; wherein the driver output port is connected to the gate of the first passgate transistor (440, 830) and the gate of the second passgate transistor, the gate of the header pFET (430, 810) is connected to the output port of the driver and the drain of the header pFET is connected to the source of the first pFET and the source of the second pFET; the drain of the first pFET is connected to the drain of the first nFET transistor and the gate of the second pFET; the gate of the first pFET is connected to the gate of the first nFET transistor and the drain of the second pFET; the drain of the second pFET is connected to the drain of the second nFET; and the gate of the second pFET is connected to the gate of the second nFET; the drain of the first passgate transistor (440, 830) is connected to the drain of the first pFET and the gate of the second pFET; the drain of the second passgate transistor (442,832) is connected to the gate of the first pFET and the drain of the second pFET; characterized by the bitcell further comprising a third pFET having a gate, a source and a drain, the drain of the third pFET is connected to the drain of the header pFET (430, 810) wherein when the gate of the third pFET is held LOW, the third pFET is configured to be connected in parallel to the header pFET (430, 810). a first pFET having a gate, a source and a drain; a second pFET having a gate, a source and a drain; a first nFET transistor having a gate, a source and a drain; a second nFET transistor having a gate, a source and a drain; a first nFET passgate transistor (440, 830) having a gate, a source and a drain; a second nFET passgate transistor (442,832) having a gate, a source and a drain; a driver; and a header pFET (430, 810) having a gate, a source and a drain; wherein the driver output port is connected to the gate of the first passgate transistor (440, 830) and the gate of the second passgate transistor, the gate of the header pFET (430, 810) is connected to the output port of the driver and the drain of the header pFET is connected to the source of the first pFET and the source of the second pFET; the drain of the first pFET is connected to the drain of the first nFET transistor and the gate of the second pFET; the gate of the first pFET is connected to the gate of the first nFET transistor and the drain of the second pFET; the drain of the second pFET is connected to the drain of the second nFET; and the gate of the second pFET is connected to the gate of the second nFET; the drain of the first passgate transistor (440, 830) is connected to the drain of the first pFET and the gate of the second pFET; the drain of the second passgate transistor (442,832) is connected to the gate of the first pFET and the drain of the second pFET; characterized by the bitcell further comprising a third pFET having a gate, a source and a drain, the drain of the third pFET is connected to the drain of the header pFET (430, 810) wherein when the gate of the third pFET is held LOW, the third pFET is configured to be connected in parallel to the header pFET (430, 810).