A server comprising a plurality of modules, each module comprising: - a communication element (16, 26) capable of ensuring the consistency of a memory shared between modules; - a plurality of CPU processors (10, 11, 20, 21) connected to each other and to the communication element (16, 26); - a system-on-a-chip SOC (12, 22) connected to the plurality of CPU processors (10, 11, 20, 21) and to the communication element (16, 26), the system-on-a-chip SOC (12, 22) running firmware; - a field-programmable gate array (FPGA) (13, 23, 33, 43, 53, 63, 73, 83) connects to the system-on-a-chip SOC (12, 22), the communication element (16, 26) and the plurality of CPU processors (10, 11, 20, 21); the modules being interconnected by: - an interconnection between each communication element (16, 26) via an XQPI (extended QuickPath Interconnect) network; - an interconnection between each system-on-a-chip SOC (12, 22) via a private Ethernet protocol network, encapsulating a communication protocol in accordance with the IPMB standard; the firmware running on each system-on-a-chip SOC (12, 22) of each module implementing two software components, namely: - a satellite management controller component (15, 25) of the system, capable of measuring the physical parameters of its module and managing the local functions of this module; - a baseboard management controller component (14, 24, 34, 44, 54, 64, 74, 84) capable of supervising all the SMCs (15, 25) of all the modules, in particular by receiving measurements or any other data sent back by said SMCs and by transmitting control messages to said SMCs, centrally managing all the functions of the server, and exchanging data with each of the BMC components (14, 24, 34, 44, 54, 64, 74, 84) via the interconnection between each system-on-a-chip SOC (12, 22), each of the modules further comprising a clock signal generator (130, 230, 330, 430, 530, 630, 730, 830), adapted to synchronize the CPU processors (10, 11, 20, 21) of its module; and its FPGA (13, 23, 33, 43, 53, 63, 73, 83) being programmed to partition and group into subsets the modules according to a same operating system supported by said modules; and said interconnection via an XQPI network being configured to route said clock signal between different modules depending on said subsets. - a communication element (16, 26) capable of ensuring the consistency of a memory shared between modules; - a plurality of CPU processors (10, 11, 20, 21) connected to each other and to the communication element (16, 26); - a system-on-a-chip SOC (12, 22) connected to the plurality of CPU processors (10, 11, 20, 21) and to the communication element (16, 26), the system-on-a-chip SOC (12, 22) running firmware; - a field-programmable gate array (FPGA) (13, 23, 33, 43, 53, 63, 73, 83) connects to the system-on-a-chip SOC (12, 22), the communication element (16, 26) and the plurality of CPU processors (10, 11, 20, 21); the modules being interconnected by: - an interconnection between each communication element (16, 26) via an XQPI (extended QuickPath Interconnect) network; - an interconnection between each system-on-a-chip SOC (12, 22) via a private Ethernet protocol network, encapsulating a communication protocol in accordance with the IPMB standard; - an interconnection between each communication element (16, 26) via an XQPI (extended QuickPath Interconnect) network; - an interconnection between each system-on-a-chip SOC (12, 22) via a private Ethernet protocol network, encapsulating a communication protocol in accordance with the IPMB standard; the firmware running on each system-on-a-chip SOC (12, 22) of each module implementing two software components, namely: - a satellite management controller component (15, 25) of the system, capable of measuring the physical parameters of its module and managing the local functions of this module; - a baseboard management controller component (14, 24, 34, 44, 54, 64, 74, 84) capable of supervising all the SMCs (15, 25) of all the modules, in particular by receiving measurements or any other data sent back by said SMCs and by transmitting control messages to said SMCs, centrally managing all the functions of the server, and exchanging data with each of the BMC components (14, 24, 34, 44, 54, 64, 74, 84) via the interconnection between each system-on-a-chip SOC (12, 22), - a satellite management controller component (15, 25) of the system, capable of measuring the physical parameters of its module and managing the local functions of this module; - a baseboard management controller component (14, 24, 34, 44, 54, 64, 74, 84) capable of supervising all the SMCs (15, 25) of all the modules, in particular by receiving measurements or any other data sent back by said SMCs and by transmitting control messages to said SMCs, centrally managing all the functions of the server, and exchanging data with each of the BMC components (14, 24, 34, 44, 54, 64, 74, 84) via the interconnection between each system-on-a-chip SOC (12, 22), each of the modules further comprising a clock signal generator (130, 230, 330, 430, 530, 630, 730, 830), adapted to synchronize the CPU processors (10, 11, 20, 21) of its module; and its FPGA (13, 23, 33, 43, 53, 63, 73, 83) being programmed to partition and group into subsets the modules according to a same operating system supported by said modules; and said interconnection via an XQPI network being configured to route said clock signal between different modules depending on said subsets.