A memory controller, comprising: logic for receiving a user transaction; logic (202, 204) for determining one or more memory commands based on the user transaction, the one or more determined memory commands including one or more row and/or one or more column memory commands; a memory command pool that includes a plurality of pool slots, each pool slot for temporarily storing a memory command; characterized by further comprising logic for: assigning each of the determined memory commands to a respective pool slot in the memory command pool; determining one or more command dependencies based on the determined memory commands and one or more other memory commands previously assigned to the memory command pool for one or more previously received user transactions; generating one or more bit vectors based on the determined command dependencies, each bit vector being generated for a respective one of the determined memory commands, each bit vector including a plurality of bits, each bit indicating whether the respective one of the determined memory commands is dependent on an issuance of a respective one of the other determined memory commands or a respective one of the previously assigned memory commands associated with the bit; and reordering issuances of one or more of the determined memory commands and the previously assigned memory commands based on the one or more bit vectors to prevent the issuance of any memory command from the memory command pool prior to the issuance of all other ones of the memory commands in the memory command pool on which it depends; and logic for issuing the memory commands to a memory device based on the reordering. logic for receiving a user transaction; logic (202, 204) for determining one or more memory commands based on the user transaction, the one or more determined memory commands including one or more row and/or one or more column memory commands; a memory command pool that includes a plurality of pool slots, each pool slot for temporarily storing a memory command; characterized by further comprising logic for: assigning each of the determined memory commands to a respective pool slot in the memory command pool; determining one or more command dependencies based on the determined memory commands and one or more other memory commands previously assigned to the memory command pool for one or more previously received user transactions; generating one or more bit vectors based on the determined command dependencies, each bit vector being generated for a respective one of the determined memory commands, each bit vector including a plurality of bits, each bit indicating whether the respective one of the determined memory commands is dependent on an issuance of a respective one of the other determined memory commands or a respective one of the previously assigned memory commands associated with the bit; and reordering issuances of one or more of the determined memory commands and the previously assigned memory commands based on the one or more bit vectors to prevent the issuance of any memory command from the memory command pool prior to the issuance of all other ones of the memory commands in the memory command pool on which it depends; and assigning each of the determined memory commands to a respective pool slot in the memory command pool; determining one or more command dependencies based on the determined memory commands and one or more other memory commands previously assigned to the memory command pool for one or more previously received user transactions; generating one or more bit vectors based on the determined command dependencies, each bit vector being generated for a respective one of the determined memory commands, each bit vector including a plurality of bits, each bit indicating whether the respective one of the determined memory commands is dependent on an issuance of a respective one of the other determined memory commands or a respective one of the previously assigned memory commands associated with the bit; and reordering issuances of one or more of the determined memory commands and the previously assigned memory commands based on the one or more bit vectors to prevent the issuance of any memory command from the memory command pool prior to the issuance of all other ones of the memory commands in the memory command pool on which it depends; and logic for issuing the memory commands to a memory device based on the reordering.