A processing device (100, 200, 300) comprising: a controller (102, 202, 302); a first clock circuit (106, 206, 306), the first clock circuit generating a first clock signal (110, 210, 310, 402), the first clock signal being a main clock signal provided for operation of the processing device; and a built-in-test circuit, wherein the built-in-test circuit comprises: a second clock circuit (108, 208, 308) that is integrated with the processing device and that generates a second clock signal (112, 212, 312, 404); and a logic circuit (114, 214, 314) that is integrated with the processing device and that processes the first and second clock signals and outputs a third clock signal (116, 216, 316, 406) that is used to determine a system timing margin of the processing device, wherein the third clock signal is based on the processing of the first and second clock signals; wherein the system timing margin is the timing variation of a system clock (116, 216, 316, 406) that the processing device is capable of handling without exhibiting an unhealthy condition; wherein the processing device is configured to adjust the frequency of the second clock signal; wherein the second clock signal has a higher frequency than that of the first clock signal; and wherein the system clock (116, 216, 316, 406) corresponds to the third clock signal (116, 216, 316, 406). a controller (102, 202, 302); a first clock circuit (106, 206, 306), the first clock circuit generating a first clock signal (110, 210, 310, 402), the first clock signal being a main clock signal provided for operation of the processing device; and a built-in-test circuit, wherein the built-in-test circuit comprises: a second clock circuit (108, 208, 308) that is integrated with the processing device and that generates a second clock signal (112, 212, 312, 404); and a logic circuit (114, 214, 314) that is integrated with the processing device and that processes the first and second clock signals and outputs a third clock signal (116, 216, 316, 406) that is used to determine a system timing margin of the processing device, wherein the third clock signal is based on the processing of the first and second clock signals; wherein the system timing margin is the timing variation of a system clock (116, 216, 316, 406) that the processing device is capable of handling without exhibiting an unhealthy condition; wherein the processing device is configured to adjust the frequency of the second clock signal; wherein the second clock signal has a higher frequency than that of the first clock signal; and wherein the system clock (116, 216, 316, 406) corresponds to the third clock signal (116, 216, 316, 406). a second clock circuit (108, 208, 308) that is integrated with the processing device and that generates a second clock signal (112, 212, 312, 404); and a logic circuit (114, 214, 314) that is integrated with the processing device and that processes the first and second clock signals and outputs a third clock signal (116, 216, 316, 406) that is used to determine a system timing margin of the processing device, wherein the third clock signal is based on the processing of the first and second clock signals; wherein the system timing margin is the timing variation of a system clock (116, 216, 316, 406) that the processing device is capable of handling without exhibiting an unhealthy condition; wherein the processing device is configured to adjust the frequency of the second clock signal; wherein the second clock signal has a higher frequency than that of the first clock signal; and wherein the system clock (116, 216, 316, 406) corresponds to the third clock signal (116, 216, 316, 406).