A GaN-on-Si epiwafer (100, 300, 400, 800) forming a layer stack comprising along a stacking direction (108, 304, 402, 711): - a substrate (102, 306, 403) having a diameter of 150 mm or more, preferably, of 150 mm to 450 mm, in at least one direction that is perpendicular to the stacking direction and a substrate surface along the stacking direction that is at least partly formed by silicon, - a strain-decoupling sub-stack (111, 311, 411) comprising - a self-organized template layer (110, 308, 410) arranged directly on the substrate, the self-organized template layer comprising pits (310, 415), said pits having a pit density of 1x10 7 cm -2 to 1x10 11 cm -2, and - a surface recovery layer (114, 312, 412) arranged directly on the self-organized template layer and comprising GaN, the surface recovery layer having a smooth surface (116, 413) with a reflectivity of 35 % to 50 % or a surface roughness of 1 nm or less that points along the stacking direction, and - a strain-engineering sub-stack (118, 316, 414) arranged on the surface recovery layer and comprising at least one GaN layer (120, 318, 404, 416) and at least one Al x Ga 1-x N intermediate layer (122, 320, 408), with x ≥ 0.5, the GaN layer having a thickness of 0.5 μm to 4.0 μm, the Al x Ga 1-x N intermediate layer having a thickness of 5 nm to 25 nm, wherein - the GaN-on-Si epiwafer has a bow of at most 100 μm at room temperature. - a substrate (102, 306, 403) having a diameter of 150 mm or more, preferably, of 150 mm to 450 mm, in at least one direction that is perpendicular to the stacking direction and a substrate surface along the stacking direction that is at least partly formed by silicon, - a strain-decoupling sub-stack (111, 311, 411) comprising - a self-organized template layer (110, 308, 410) arranged directly on the substrate, the self-organized template layer comprising pits (310, 415), said pits having a pit density of 1x10 7 cm -2 to 1x10 11 cm -2, and - a surface recovery layer (114, 312, 412) arranged directly on the self-organized template layer and comprising GaN, the surface recovery layer having a smooth surface (116, 413) with a reflectivity of 35 % to 50 % or a surface roughness of 1 nm or less that points along the stacking direction, and - a self-organized template layer (110, 308, 410) arranged directly on the substrate, the self-organized template layer comprising pits (310, 415), said pits having a pit density of 1x10 7 cm -2 to 1x10 11 cm -2, and - a surface recovery layer (114, 312, 412) arranged directly on the self-organized template layer and comprising GaN, the surface recovery layer having a smooth surface (116, 413) with a reflectivity of 35 % to 50 % or a surface roughness of 1 nm or less that points along the stacking direction, and - a strain-engineering sub-stack (118, 316, 414) arranged on the surface recovery layer and comprising at least one GaN layer (120, 318, 404, 416) and at least one Al x Ga 1-x N intermediate layer (122, 320, 408), with x ≥ 0.5, the GaN layer having a thickness of 0.5 μm to 4.0 μm, the Al x Ga 1-x N intermediate layer having a thickness of 5 nm to 25 nm, wherein - the GaN-on-Si epiwafer has a bow of at most 100 μm at room temperature.