A memory device, comprising: a non-volatile memory; and a secure-programming circuit configured to: receive a program-NVM instruction to program a given data word in a given location of the NVM; and responsively to receiving the program-NVM instruction, program bits of the given data word in the NVM in a random order, wherein the memory device is characterized in that the given data word consists of two to the power of N bits, the SPC comprises a scrambler and a counter and is configured to generate a random permutation of two to the power of N values, and to program the bits of the given data word in an order that follows the random permutation, and is configured to generate the random permutation by: generating a vector (Vn) of random bits through the scrambler; generating an invertible binary matrix; clearing a count register of the counter, thereby setting a count to zero; a) generating a vector (Vc) comprising respective bits of the count; b) multiplying the invertible binary matrix by the vector (Vc) comprising the respective bits of the count to produce a product; c) adding the vector (Vn) of the random bits to the product; d) checking if the count equals to 2 N -1; e) if the count is not equal to 2 N -1, incrementing the counter and repeating steps a)-e). a non-volatile memory; and a secure-programming circuit configured to: receive a program-NVM instruction to program a given data word in a given location of the NVM; and responsively to receiving the program-NVM instruction, program bits of the given data word in the NVM in a random order, wherein the memory device is characterized in that the given data word consists of two to the power of N bits, the SPC comprises a scrambler and a counter and is configured to generate a random permutation of two to the power of N values, and to program the bits of the given data word in an order that follows the random permutation, and is configured to generate the random permutation by: generating a vector (Vn) of random bits through the scrambler; generating an invertible binary matrix; clearing a count register of the counter, thereby setting a count to zero; a) generating a vector (Vc) comprising respective bits of the count; b) multiplying the invertible binary matrix by the vector (Vc) comprising the respective bits of the count to produce a product; c) adding the vector (Vn) of the random bits to the product; d) checking if the count equals to 2 N -1; e) if the count is not equal to 2 N -1, incrementing the counter and repeating steps a)-e). receive a program-NVM instruction to program a given data word in a given location of the NVM; and responsively to receiving the program-NVM instruction, program bits of the given data word in the NVM in a random order, wherein the memory device is characterized in that the given data word consists of two to the power of N bits, the SPC comprises a scrambler and a counter and is configured to generate a random permutation of two to the power of N values, and to program the bits of the given data word in an order that follows the random permutation, and is configured to generate the random permutation by: generating a vector (Vn) of random bits through the scrambler; generating an invertible binary matrix; clearing a count register of the counter, thereby setting a count to zero; a) generating a vector (Vc) comprising respective bits of the count; b) multiplying the invertible binary matrix by the vector (Vc) comprising the respective bits of the count to produce a product; c) adding the vector (Vn) of the random bits to the product; d) checking if the count equals to 2 N -1; e) if the count is not equal to 2 N -1, incrementing the counter and repeating steps a)-e). generating a vector (Vn) of random bits through the scrambler; generating an invertible binary matrix; clearing a count register of the counter, thereby setting a count to zero; a) generating a vector (Vc) comprising respective bits of the count; b) multiplying the invertible binary matrix by the vector (Vc) comprising the respective bits of the count to produce a product; c) adding the vector (Vn) of the random bits to the product; d) checking if the count equals to 2 N -1; e) if the count is not equal to 2 N -1, incrementing the counter and repeating steps a)-e). a) generating a vector (Vc) comprising respective bits of the count; b) multiplying the invertible binary matrix by the vector (Vc) comprising the respective bits of the count to produce a product; c) adding the vector (Vn) of the random bits to the product; d) checking if the count equals to 2 N -1; e) if the count is not equal to 2 N -1, incrementing the counter and repeating steps a)-e).