A memory system that operates in response to a clock signal, the memory system comprising: an array of memory cells, wherein each of the memory cells must be periodically refreshed to retain a data value; a memory array sequencer coupled to the array of memory cells, wherein the memory array sequencer is configured to control external accesses and refresh accesses to the array of memory cells, the memory array sequencer enabling sense amplifier operation supporting N said external accesses and one said refresh access to be performed consecutively during N cycles of the clock signal, wherein N is an integer equal to two or more; and a refresh controller configured to periodically activate a refresh request signal, wherein the refresh request signal is provided to the memory array sequencer; and wherein the memory array sequencer comprises: a first sequential logic circuit for activating a refresh pending signal when the refresh request signal is activated and the clock signal transitions to a first state; a divider circuit for dividing the clock signal, thereby providing a divided clock signal that is activated for one period of every N periods of the clock signal; and a first combinational logic circuit for initiating a refresh access when the refresh pending signal is activated and the divided clock signal is activated, the memory system further comprising: a terminal [ADS#] for receiving an external access signal that is activated to indicate a requested external access to the array; and wherein the memory array sequencer is configured to implement an external access to the array when the external access signal is activated and the clock signal transitions to the first state, the memory array sequencer further being configured to implement a refresh access to the array when the refresh request signal is activated and the clock signal transitions to a second state. an array of memory cells, wherein each of the memory cells must be periodically refreshed to retain a data value; a memory array sequencer coupled to the array of memory cells, wherein the memory array sequencer is configured to control external accesses and refresh accesses to the array of memory cells, the memory array sequencer enabling sense amplifier operation supporting N said external accesses and one said refresh access to be performed consecutively during N cycles of the clock signal, wherein N is an integer equal to two or more; and a refresh controller configured to periodically activate a refresh request signal, wherein the refresh request signal is provided to the memory array sequencer; and wherein the memory array sequencer comprises: a first sequential logic circuit for activating a refresh pending signal when the refresh request signal is activated and the clock signal transitions to a first state; a divider circuit for dividing the clock signal, thereby providing a divided clock signal that is activated for one period of every N periods of the clock signal; and a first combinational logic circuit for initiating a refresh access when the refresh pending signal is activated and the divided clock signal is activated, the memory system further comprising: a terminal [ADS#] for receiving an external access signal that is activated to indicate a requested external access to the array; and wherein the memory array sequencer is configured to implement an external access to the array when the external access signal is activated and the clock signal transitions to the first state, the memory array sequencer further being configured to implement a refresh access to the array when the refresh request signal is activated and the clock signal transitions to a second state. a first sequential logic circuit for activating a refresh pending signal when the refresh request signal is activated and the clock signal transitions to a first state; a divider circuit for dividing the clock signal, thereby providing a divided clock signal that is activated for one period of every N periods of the clock signal; and a first combinational logic circuit for initiating a refresh access when the refresh pending signal is activated and the divided clock signal is activated, the memory system further comprising: a terminal [ADS#] for receiving an external access signal that is activated to indicate a requested external access to the array; and wherein the memory array sequencer is configured to implement an external access to the array when the external access signal is activated and the clock signal transitions to the first state, the memory array sequencer further being configured to implement a refresh access to the array when the refresh request signal is activated and the clock signal transitions to a second state. a terminal [ADS#] for receiving an external access signal that is activated to indicate a requested external access to the array; and wherein the memory array sequencer is configured to implement an external access to the array when the external access signal is activated and the clock signal transitions to the first state, the memory array sequencer further being configured to implement a refresh access to the array when the refresh request signal is activated and the clock signal transitions to a second state.