A method for testing a multiprocessor machine, this machine comprising several processors (2, 3, 4, 5) interconnected to a memory comprising a common memory zone, the processors being able to execute sequences of instructions simultaneously, characterised in that it comprises the following steps of: a. booting a single-processor operating system on a first processor, controlling the memory; b. booting, under the command of the first processor, the execution of at least one sequence of instructions (17, 18, 19) by at least one other processor (3, 4, 5), said booting comprising: b1. loading at a first address in the common memory zone, a first sequence of instructions executable by at least one other processor (3, 4, 5) to be initialised, and at least one second address of said common memory zone, a second sequence of instructions of test code executable by said other processors (3, 4, 5) after initialisation; b2. building by said first processor in the common memory zone of the machine, an application table with several rows accessible by each of the other processors via a respective processor identifier, the processor associating with each of the rows of the application table, a private memory zone (22, 23, 24) of the memory which is specific to each of the other processors (3, 4, 5), respectively, and stores therein data required for establishing an execution context for each of said other processors (3, 4, 5) and comprising the second address, respectively; b3. allocating respective private memory zones (22, 23, 24) to said other processors (3, 4, 5); b4. storing said first address in a processor start table; b5. sending an interrupt (25, 26, 27) to at least one other processor (3, 4, 5) which causes a connection of this other processor to the first address contained in the start table, such that said other processor (3, 4, 5) executes the first sequence of instructions at the end of which this other processor connects to the second address contained in the row of the application table accessible by the identifier of said other processor. a. booting a single-processor operating system on a first processor, controlling the memory; b. booting, under the command of the first processor, the execution of at least one sequence of instructions (17, 18, 19) by at least one other processor (3, 4, 5), said booting comprising: b1. loading at a first address in the common memory zone, a first sequence of instructions executable by at least one other processor (3, 4, 5) to be initialised, and at least one second address of said common memory zone, a second sequence of instructions of test code executable by said other processors (3, 4, 5) after initialisation; b2. building by said first processor in the common memory zone of the machine, an application table with several rows accessible by each of the other processors via a respective processor identifier, the processor associating with each of the rows of the application table, a private memory zone (22, 23, 24) of the memory which is specific to each of the other processors (3, 4, 5), respectively, and stores therein data required for establishing an execution context for each of said other processors (3, 4, 5) and comprising the second address, respectively; b3. allocating respective private memory zones (22, 23, 24) to said other processors (3, 4, 5); b4. storing said first address in a processor start table; b5. sending an interrupt (25, 26, 27) to at least one other processor (3, 4, 5) which causes a connection of this other processor to the first address contained in the start table, b1. loading at a first address in the common memory zone, a first sequence of instructions executable by at least one other processor (3, 4, 5) to be initialised, and at least one second address of said common memory zone, a second sequence of instructions of test code executable by said other processors (3, 4, 5) after initialisation; b2. building by said first processor in the common memory zone of the machine, an application table with several rows accessible by each of the other processors via a respective processor identifier, the processor associating with each of the rows of the application table, a private memory zone (22, 23, 24) of the memory which is specific to each of the other processors (3, 4, 5), respectively, and stores therein data required for establishing an execution context for each of said other processors (3, 4, 5) and comprising the second address, respectively; b3. allocating respective private memory zones (22, 23, 24) to said other processors (3, 4, 5); b4. storing said first address in a processor start table; b5. sending an interrupt (25, 26, 27) to at least one other processor (3, 4, 5) which causes a connection of this other processor to the first address contained in the start table,