A method of fabricating a thin film transistor for an active matrix display with reduced masking operations, the method comprising the steps of: providing a transparent substrate with a surface; patterning gate metal on the surface of the substrate to define a thin film transistor gate; forming a layer of transparent gate dielectric over the gate and surrounding substrate surface; depositing a layer of transparent semiconducting metal oxide on the layer of gate dielectric; patterning a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide; depositing at least a source/drain metal layer on the channel protection layer and the exposed semiconducting metal oxide; in a single etching step, etching through the source/drain metal layer to the channel protection layer above the gate to separate the source/drain metal layer into thin film transistor source and drain terminals and etching through the source/drain metal layer and the semiconducting metal oxide at the periphery to isolate the thin film transistor; and patterning a nonconductive spacer layer on the isolated thin film transistor and portions of the surrounding source/drain metal layer, the spacer layer defining a light transmission area adjacent the channel area designed to receive a light transmitting device in overlying relationship; and spacer using the patterned nonconductive spacer layer as mask, etching through the source/drain metal layer in the light transmission area to expose the semiconducting metal oxide as a transparent pixel terminal contacting or forming one terminal of the overlying light transmitting device. providing a transparent substrate with a surface; patterning gate metal on the surface of the substrate to define a thin film transistor gate; forming a layer of transparent gate dielectric over the gate and surrounding substrate surface; depositing a layer of transparent semiconducting metal oxide on the layer of gate dielectric; patterning a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide; depositing at least a source/drain metal layer on the channel protection layer and the exposed semiconducting metal oxide; in a single etching step, etching through the source/drain metal layer to the channel protection layer above the gate to separate the source/drain metal layer into thin film transistor source and drain terminals and etching through the source/drain metal layer and the semiconducting metal oxide at the periphery to isolate the thin film transistor; and patterning a nonconductive spacer layer on the isolated thin film transistor and portions of the surrounding source/drain metal layer, the spacer layer defining a light transmission area adjacent the channel area designed to receive a light transmitting device in overlying relationship; and spacer using the patterned nonconductive spacer layer as mask, etching through the source/drain metal layer in the light transmission area to expose the semiconducting metal oxide as a transparent pixel terminal contacting or forming one terminal of the overlying light transmitting device.