An apparatus for reduction of unwanted idle tones by dithering a variable resolution quantizer of a multi-bit sigma-delta analog-to-digital converter, comprising: an M-bit sigma-delta modulator, wherein M>1, compri.sing an M-bit digital-to-analog converter, an analog voltage summation circuit receiving an analog input signal and being operable to add an output signal of the M-bit DAC to the analog input signal, an analog loop filter coupled to an output of the analog voltage summation circuit generating a filtered sum of the output of the analog voltage summation circuit, characterized by a variable resolution quantizer (626, 628, 630) receiving the filtered sum of the analog loop filter and generating output signals in a sequence, an encoder coupled to the variable resolution quantizer (626,628, 630), wherein the encoder converts the respective output signal from the variable resolution quantizer (626,628, 630) into a respective M-bit binary representations thereof and the respective M-bit binary representation is applied to the M-bit DAC, and a random sequence generator coupled to the variable resolution quantizer (626,628, 630) wherein the random sequence generator generates a plurality of random numbers N(n) in a sequence, where N(n) are random integer numbers and wherein 2<=N(n)<=nl.ev, wherein nlev is a predefined maximum resolution, whereby a resolution of the variable resolution quantizer (626,628, 630) is determined by a respective one of the plurality of random numbers N(n) for each respective analog voltage sample taken from the analog input signal; a voltage reference coupled to the variable resolution quantizer (626,628, 630); and a digital filter coupled to the encoder and receiving the M-bit binary representation therefrom. an M-bit sigma-delta modulator, wherein M>1, compri.sing an M-bit digital-to-analog converter, an analog voltage summation circuit receiving an analog input signal and being operable to add an output signal of the M-bit DAC to the analog input signal, an analog loop filter coupled to an output of the analog voltage summation circuit generating a filtered sum of the output of the analog voltage summation circuit, characterized by a variable resolution quantizer (626, 628, 630) receiving the filtered sum of the analog loop filter and generating output signals in a sequence, an encoder coupled to the variable resolution quantizer (626,628, 630), wherein the encoder converts the respective output signal from the variable resolution quantizer (626,628, 630) into a respective M-bit binary representations thereof and the respective M-bit binary representation is applied to the M-bit DAC, and a random sequence generator coupled to the variable resolution quantizer (626,628, 630) wherein the random sequence generator generates a plurality of random numbers N(n) in a sequence, where N(n) are random integer numbers and wherein 2<=N(n)<=nl.ev, wherein nlev is a predefined maximum resolution, whereby a resolution of the variable resolution quantizer (626,628, 630) is determined by a respective one of the plurality of random numbers N(n) for each respective analog voltage sample taken from the analog input signal; a voltage reference coupled to the variable resolution quantizer (626,628, 630); and a digital filter coupled to the encoder and receiving the M-bit binary representation therefrom. an M-bit digital-to-analog converter, an analog voltage summation circuit receiving an analog input signal and being operable to add an output signal of the M-bit DAC to the analog input signal, an analog loop filter coupled to an output of the analog voltage summation circuit generating a filtered sum of the output of the analog voltage summation circuit, a variable resolution quantizer (626, 628, 630) receiving the filtered sum of the analog loop filter and generating output signals in a sequence, an encoder coupled to the variable resolution quantizer (626,628, 630), wherein the encoder converts the respective output signal from the variable resolution quantizer (626,628, 630) into a respective M-bit binary representations thereof and the respective M-bit binary representation is applied to the M-bit DAC, and a random sequence generator coupled to the variable resolution quantizer (626,628, 630) wherein the random sequence generator generates a plurality of random numbers N(n) in a sequence, where N(n) are random integer numbers and wherein 2<=N(n)<=nl.ev, wherein nlev is a predefined maximum resolution, whereby a resolution of the variable resolution quantizer (626,628, 630) is determined by a respective one of the plurality of random numbers N(n) for each respective analog voltage sample taken from the analog input signal; a voltage reference coupled to the variable resolution quantizer (626,628, 630); and a digital filter coupled to the encoder and receiving the M-bit binary representation therefrom.