A memory system comprising: a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array; a bl transistor electrically connected via its gate terminal to the first bitline, wherein the bl transistor is configured to receive as input to the gate terminal a first electrical signal from the first bitline based on the first bitline being discharged; and a blb transistor electrically connected via its gate terminal to the second bitline, wherein the blb transistor is configured to receive as input to the gate terminal a second electrical signal from the second bitline based on the second bitline being discharged, wherein an output of the bl transistor which corresponds to its drain terminal and an output of the blb transistor which also corresponds to its drain terminal are electrically coupled together as a common output, wherein the source terminals of the bl and of the blb transistors are coupled together to a power supply node, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor, wherein the common output of the bl transistor and the blb transistor comprises a sense amplifier enable signal (saen) configured to be input to the sense amplifier, wherein the sense amplifier is configured to measure a voltage differential across the first bitline and the second bitline based on reception of the sense amplifier enable signal (saen); and characterized in that a discharge transistor is coupled to the common output of the bl transistor and the blb transistor and is configured to bring down a node which corresponds to the common output of the bl transistor and the blb transistor based on a discharge signal applied to a gate terminal of the discharge transistor, the discharge signal having an inverse polarity to a signal of a word line of the memory array which is selected for a sensing operation and which is associated with the first bitline and the second bitline. a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array; a bl transistor electrically connected via its gate terminal to the first bitline, wherein the bl transistor is configured to receive as input to the gate terminal a first electrical signal from the first bitline based on the first bitline being discharged; and a blb transistor electrically connected via its gate terminal to the second bitline, wherein the blb transistor is configured to receive as input to the gate terminal a second electrical signal from the second bitline based on the second bitline being discharged, wherein an output of the bl transistor which corresponds to its drain terminal and an output of the blb transistor which also corresponds to its drain terminal are electrically coupled together as a common output, wherein the source terminals of the bl and of the blb transistors are coupled together to a power supply node, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor, wherein the common output of the bl transistor and the blb transistor comprises a sense amplifier enable signal (saen) configured to be input to the sense amplifier, wherein the sense amplifier is configured to measure a voltage differential across the first bitline and the second bitline based on reception of the sense amplifier enable signal (saen); and characterized in that a discharge transistor is coupled to the common output of the bl transistor and the blb transistor and is configured to bring down a node which corresponds to the common output of the bl transistor and the blb transistor based on a discharge signal applied to a gate terminal of the discharge transistor, the discharge signal having an inverse polarity to a signal of a word line of the memory array which is selected for a sensing operation and which is associated with the first bitline and the second bitline.