A memory device comprising: a plurality of non-volatile memory cells, wherein each of the memory cells comprises: spaced apart source and drain regions (14, 16) formed in a semiconductor substrate, with a channel region of the substrate extending there between, a floating gate disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region, and a control gate disposed vertically over and insulated from the floating gate; and a controller configured to: receive a first command for erasing and programming a first group of the memory cells, determine that the first group of the memory cells can be programmed within substantially 10 seconds of erasure of the first group of the memory cells, erase the first group of memory cells in a group erase operation, program the first group of memory cells within substantially 10 seconds of the group erase operation, receive a second command for erasing and programming a second group of the memory cells, determine that the second group of the memory cells cannot be programmed within substantially 10 seconds of erasure of the second group of the memory cells, divide the second group of the memory cells into a plurality of subgroups of the memory cells, wherein each one of the subgroups can be programmed within substantially 10 seconds of erasure of the respective one subgroup of the memory cells, and for each of the subgroups of the memory cells: erase the subgroup of memory cells in a subgroup erase operation, and program the subgroup of memory cells within substantially 10 seconds of the subgroup erase operation. spaced apart source and drain regions (14, 16) formed in a semiconductor substrate, with a channel region of the substrate extending there between, a floating gate disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region, and a control gate disposed vertically over and insulated from the floating gate; and a controller configured to: receive a first command for erasing and programming a first group of the memory cells, determine that the first group of the memory cells can be programmed within substantially 10 seconds of erasure of the first group of the memory cells, erase the first group of memory cells in a group erase operation, program the first group of memory cells within substantially 10 seconds of the group erase operation, receive a second command for erasing and programming a second group of the memory cells, determine that the second group of the memory cells cannot be programmed within substantially 10 seconds of erasure of the second group of the memory cells, divide the second group of the memory cells into a plurality of subgroups of the memory cells, wherein each one of the subgroups can be programmed within substantially 10 seconds of erasure of the respective one subgroup of the memory cells, and for each of the subgroups of the memory cells: erase the subgroup of memory cells in a subgroup erase operation, and program the subgroup of memory cells within substantially 10 seconds of the subgroup erase operation. receive a first command for erasing and programming a first group of the memory cells, determine that the first group of the memory cells can be programmed within substantially 10 seconds of erasure of the first group of the memory cells, erase the first group of memory cells in a group erase operation, program the first group of memory cells within substantially 10 seconds of the group erase operation, receive a second command for erasing and programming a second group of the memory cells, determine that the second group of the memory cells cannot be programmed within substantially 10 seconds of erasure of the second group of the memory cells, divide the second group of the memory cells into a plurality of subgroups of the memory cells, wherein each one of the subgroups can be programmed within substantially 10 seconds of erasure of the respective one subgroup of the memory cells, and for each of the subgroups of the memory cells: erase the subgroup of memory cells in a subgroup erase operation, and program the subgroup of memory cells within substantially 10 seconds of the subgroup erase operation. erase the subgroup of memory cells in a subgroup erase operation, and program the subgroup of memory cells within substantially 10 seconds of the subgroup erase operation.