An emission driving unit, comprising: an input signal generating circuit configured to receive a frame line mark signal according to a first clock signal, to receive a second clock signal according to the FLM signal, and to output a sequential input signal (NEXT IN); an inverter circuit configured to receive the FLM signal according to the first clock signal, and to invert the FLM signal to generate an inverter output signal (IVT_OUT); and an output switching circuit configured to output a first voltage having a logic high level or a second voltage having a logic low level as an emission signal in response to the inverter output signal (IVT_OUT), wherein the input signal generating circuit, the inverter circuit, and the output switching circuit are implemented with only N-channel metal-oxide semiconductor (NMOS) transistors characterized in that the inverter circuit includes a first transistor having a source electrode, a drain electrode that receives the FLM signal, and a gate electrode that receives the first clock signal, the FLM signal being transmitted from the drain electrode of the first transistor to the source electrode of the first transistor in response to the first clock signal; a second transistor having a drain electrode that receives the second clock signal, a gate electrode coupled to the source electrode of the first transistor, and a source electrode that outputs the sequential input signal (NEXT IN); and a first capacitor coupled between the source electrode of the first transistor and the source electrode of the second transistor; a third transistor configured to transmit the FLM signal to a first node in response to the first clock signal; a fourth transistor having a gate electrode coupled to the first node, a source electrode coupled to a second voltage supply terminal, and a drain electrode coupled to a second node; a second capacitor coupled between the first node and the second voltage supply terminal; a fifth transistor having a drain electrode coupled to the source electrode of the second transistor, a source electrode coupled to the second voltage supply terminal, and a gate electrode coupled to the second node; a sixth transistor having a source electrode coupled to the second node, a drain electrode coupled to a third node, and a gate electrode that receives the second clock signal; a seventh transistor having a source electrode coupled to the third node, a drain electrode coupled to a first voltage supply terminal, and a gate electrode that receives the first clock signal; an eighth transistor having a gate electrode coupled to the third node, a drain electrode that receives the second clock signal, and a source electrode coupled to a fourth node; and a third capacitor coupled between the third node and the fourth node. an input signal generating circuit configured to receive a frame line mark signal according to a first clock signal, to receive a second clock signal according to the FLM signal, and to output a sequential input signal (NEXT IN); an inverter circuit configured to receive the FLM signal according to the first clock signal, and to invert the FLM signal to generate an inverter output signal (IVT_OUT); and an output switching circuit configured to output a first voltage having a logic high level or a second voltage having a logic low level as an emission signal in response to the inverter output signal (IVT_OUT), wherein the input signal generating circuit, the inverter circuit, and the output switching circuit are implemented with only N-channel metal-oxide semiconductor (NMOS) transistors characterized in that the inverter circuit includes a first transistor having a source electrode, a drain electrode that receives the FLM signal, and a gate electrode that receives the first clock signal, the FLM signal being transmitted from the drain electrode of the first transistor to the source electrode of the first transistor in response to the first clock signal; a second transistor having a drain electrode that receives the second clock signal, a gate electrode coupled to the source electrode of the first transistor, and a source electrode that outputs the sequential input signal (NEXT IN); and a first capacitor coupled between the source electrode of the first transistor and the source electrode of the second transistor; a third transistor configured to transmit the FLM signal to a first node in response to the first clock signal; a fourth transistor having a gate electrode coupled to the first node, a source electrode coupled to a second voltage supply terminal, and a drain electrode coupled to a second node; a second capacitor coupled between the first node and the second voltage supply terminal; a fifth transistor having a drain electrode coupled to the source electrode of the second transistor, a source electrode coupled to the second voltage supply terminal, and a gate electrode coupled to the second node; a sixth transistor having a source electrode coupled to the second node, a drain electrode coupled to a third node, and a gate electrode that receives the second clock signal; a seventh transistor having a source electrode coupled to the third node, a drain electrode coupled to a first voltage supply terminal, and a gate electrode that receives the first clock signal; an eighth transistor having a gate electrode coupled to the third node, a drain electrode that receives the second clock signal, and a source electrode coupled to a fourth node; and a third capacitor coupled between the third node and the fourth node.