A layout pattern of a two-port ternary content addressable memory, cell, comprising: a first comparison circuit (420_a), positioned in a first side area of a side of the layout pattern; a second comparison circuit (420_b), positioned in a second side area of another side of the layout pattern; a set of first search terminals (SV_a, SVB_a), coupled to the first comparison circuit (420_a); a set of second search terminals (SV_b, SVB_b), coupled to the second comparison circuit (420_b); a first match terminal (MV_a), coupled to the first comparison circuit (420_a); a second match terminal (MV_b), coupled to the second comparison circuit (420_b); a first storage unit (400_1), positioned in a first middle area between the first side area and the second side area, wherein the first storage unit (400_1) is connected to the first comparison circuit (420_a) through a first gate structure (POLY1) of the layout pattern and connected to the second comparison circuit (420_b) through a second gate structure (POLY2) of the layout pattern; and a second storage unit (400_2), positioned in a second middle area between the first side area and the second side area, wherein the second storage unit (400_2) is connected to the first comparison circuit (420_a) through a third gate structure (POLY3) of the layout pattern and connected to the second comparison circuit (420_b) through a fourth gate structure (POLY4) of the layout pattern; wherein the first storage unit (400_1) comprises a first inverter and a second inverter, an input terminal and an output terminal of the first inverter being respectively connected to the first gate structure (POLY1) and the second gate structure (POLY2), and an input terminal and an output terminal of the second inverter being respectively connected to the second gate structure (POLY2) and the first gate structure (POLY1); and the second storage unit (400_2) comprises a third inverter and a fourth inverter, an input terminal and an output terminal of the third inverter being respectively connected to the third gate structure (POLY3) and the fourth gate structure (POLY4), and an input terminal and an output terminal of the fourth inverter being respectively connected to the fourth gate structure (POLY4) and the third gate structure (POLY3). a first comparison circuit (420_a), positioned in a first side area of a side of the layout pattern; a second comparison circuit (420_b), positioned in a second side area of another side of the layout pattern; a set of first search terminals (SV_a, SVB_a), coupled to the first comparison circuit (420_a); a set of second search terminals (SV_b, SVB_b), coupled to the second comparison circuit (420_b); a first match terminal (MV_a), coupled to the first comparison circuit (420_a); a second match terminal (MV_b), coupled to the second comparison circuit (420_b); a first storage unit (400_1), positioned in a first middle area between the first side area and the second side area, wherein the first storage unit (400_1) is connected to the first comparison circuit (420_a) through a first gate structure (POLY1) of the layout pattern and connected to the second comparison circuit (420_b) through a second gate structure (POLY2) of the layout pattern; and a second storage unit (400_2), positioned in a second middle area between the first side area and the second side area, wherein the second storage unit (400_2) is connected to the first comparison circuit (420_a) through a third gate structure (POLY3) of the layout pattern and connected to the second comparison circuit (420_b) through a fourth gate structure (POLY4) of the layout pattern; wherein the first storage unit (400_1) comprises a first inverter and a second inverter, an input terminal and an output terminal of the first inverter being respectively connected to the first gate structure (POLY1) and the second gate structure (POLY2), and an input terminal and an output terminal of the second inverter being respectively connected to the second gate structure (POLY2) and the first gate structure (POLY1); and the second storage unit (400_2) comprises a third inverter and a fourth inverter, an input terminal and an output terminal of the third inverter being respectively connected to the third gate structure (POLY3) and the fourth gate structure (POLY4), and an input terminal and an output terminal of the fourth inverter being respectively connected to the fourth gate structure (POLY4) and the third gate structure (POLY3).