A multiple-processor system, comprising: a plurality of central processing unit cores (602a, 602b, 602c, 602d), wherein each of the plurality of CPU cores (602a, 602b, 602c, 602d) is configured to operate in at least one of a plurality of CPU states, the plurality of CPU states including a low-voltage memory retention state, an active state, and a shut-off state, wherein the NAP state comprises a sleep state that retains state memory; a plurality of switches (S1, S2, S3, S4), wherein each of the plurality of switches (S1, S2, S3, S4) is configured to connect one of the plurality of CPU cores (602A, 602B, 602C, 602D) to a voltage source that is configured to provide an active state voltage; a voltage regulator that is configured to provide a NAP voltage to the plurality of CPU cores (602a, 602b, 602c, 602d), wherein the NAP voltage is sufficient for at least one of the plurality of CPU cores to retain state information and the NAP voltage is lower than an active state voltage; a plurality of state control switches (L1S1, L1S2, L1S3, L1S4), wherein each of the plurality of state control switches (L1S1, L1S2, L1S3, L1S4) is configured to connect the voltage regulator to one of the plurality of CPU cores (602a, 602b, 602c, 602d); and a digital NAP state controller that is configured to provide a control signal to the voltage regulator and to each of the plurality of state control switches (L1S1, L1S2, L1S3, L1S4) to control an open/close position of each of the plurality of state control switches (L1S1, L1S2, L1S3, L1S4) based on a combined CPU state of the cores (602a, 602b, 602c 602d), wherein the voltage regulator is further configured to provide a bypass voltage to the plurality of CPU cores (602a, 602b, 602c, 602d) when transitioning from the active state to the NAP state or from the NAP state to the active state, the bypass voltage being supplied to a corresponding one or more of the state control switches (L1S1, L1S2, L1S3, L1S4) while the one or more state control switches (L1S1, L1S2, L1S3, L1S4) and one or more of the plurality of switches (S1, S2, S3, S4) corresponding to the one or more state control switches (L1S1, L1S2, L1S3, L1S4) are closed for a prescribed time interval, the bypass voltage being at or close to the active state voltage, the voltage regulator being connected to the voltage source. a plurality of central processing unit cores (602a, 602b, 602c, 602d), wherein each of the plurality of CPU cores (602a, 602b, 602c, 602d) is configured to operate in at least one of a plurality of CPU states, the plurality of CPU states including a low-voltage memory retention state, an active state, and a shut-off state, wherein the NAP state comprises a sleep state that retains state memory; a plurality of switches (S1, S2, S3, S4), wherein each of the plurality of switches (S1, S2, S3, S4) is configured to connect one of the plurality of CPU cores (602A, 602B, 602C, 602D) to a voltage source that is configured to provide an active state voltage; a voltage regulator that is configured to provide a NAP voltage to the plurality of CPU cores (602a, 602b, 602c, 602d), wherein the NAP voltage is sufficient for at least one of the plurality of CPU cores to retain state information and the NAP voltage is lower than an active state voltage; a plurality of state control switches (L1S1, L1S2, L1S3, L1S4), wherein each of the plurality of state control switches (L1S1, L1S2, L1S3, L1S4) is configured to connect the voltage regulator to one of the plurality of CPU cores (602a, 602b, 602c, 602d); and a digital NAP state controller that is configured to provide a control signal to the voltage regulator and to each of the plurality of state control switches (L1S1, L1S2, L1S3, L1S4) to control an open/close position of each of the plurality of state control switches (L1S1, L1S2, L1S3, L1S4) based on a combined CPU state of the cores (602a, 602b, 602c 602d), wherein the voltage regulator is further configured to provide a bypass voltage to the plurality of CPU cores (602a, 602b, 602c, 602d) when transitioning from the active state to the NAP state or from the NAP state to the active state, the bypass voltage being supplied to a corresponding one or more of the state control switches (L1S1, L1S2, L1S3, L1S4) while the one or more state control switches (L1S1, L1S2, L1S3, L1S4) and one or more of the plurality of switches (S1, S2, S3, S4) corresponding to the one or more state control switches (L1S1, L1S2, L1S3, L1S4) are closed for a prescribed time interval, the bypass voltage being at or close to the active state voltage, the voltage regulator being connected to the voltage source.