A process for fabricating an insulated-gate transistor (100;300), including the steps of: providing a semiconductor material layer having a front surface; forming a body region of a first conductivity type in the semiconductor material layer at the front surface; forming an insulated gate in an insulative way disposed over the body region with interposition of a dielectric; forming a trench extending within the semiconductor material layer from the front surface; and forming a source region (120, 145; 320, 145) and a drain region (125,150) of a second conductivity type opposite to the first conductivity type, the source region being formed in the body region and the drain region being formed in the semiconductor material layer, the source and the drain region being spaced apart from each other by: a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, wherein the charge carriers drift portion is of the second conductivity type and the insulated gate extends over the charge carriers drift portion, the drain region being formed in the semiconductor material layer at a bottom of the trench at a depth compared to the front surface, thereby causing charge carriers to move in the charge carriers drift region away from an interface between the semiconductor material layer and the gate dielectric when a conduction current flows towards the drain region; wherein forming the trench includes performing a selective anisotropic trench etching of the semiconductor layer from the front surface; and forming the insulated gate comprises obtaining a silicon dioxide layer at the front surface of the semiconductor material layer and depositing a polycristalline silicon layer over the silicon dioxide layer; characterized in that performing a selective anisotropic trench etching includes using a mask for etching portions of the polycristalline silicon layer and of the silicon dioxide layer, thereby defining the insulated gate and the dielectric, and using the mask for etching portions of the underlying semiconductor layer in the intended portion of the active area where the drain region has to be formed. providing a semiconductor material layer having a front surface; forming a body region of a first conductivity type in the semiconductor material layer at the front surface; forming an insulated gate in an insulative way disposed over the body region with interposition of a dielectric; forming a trench extending within the semiconductor material layer from the front surface; and forming a source region (120, 145; 320, 145) and a drain region (125,150) of a second conductivity type opposite to the first conductivity type, the source region being formed in the body region and the drain region being formed in the semiconductor material layer, the source and the drain region being spaced apart from each other by: a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, wherein the charge carriers drift portion is of the second conductivity type and the insulated gate extends over the charge carriers drift portion, a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, wherein the charge carriers drift portion is of the second conductivity type and the insulated gate extends over the charge carriers drift portion, the drain region being formed in the semiconductor material layer at a bottom of the trench at a depth compared to the front surface, thereby causing charge carriers to move in the charge carriers drift region away from an interface between the semiconductor material layer and the gate dielectric when a conduction current flows towards the drain region; wherein forming the trench includes performing a selective anisotropic trench etching of the semiconductor layer from the front surface; and forming the insulated gate comprises obtaining a silicon dioxide layer at the front surface of the semiconductor material layer and depositing a polycristalline silicon layer over the silicon dioxide layer; characterized in that performing a selective anisotropic trench etching includes using a mask for etching portions of the polycristalline silicon layer and of the silicon dioxide layer, thereby defining the insulated gate and the dielectric, and using the mask for etching portions of the underlying semiconductor layer in the intended portion of the active area where the drain region has to be formed.