Apparatus for processing data, said apparatus comprising: a register data store configured to store a plurality of data elements; and processing logic responsive to a data processing instruction to perform a data processing operation in parallel upon a selected plurality of data elements accessed as a register of said register data store and disposed contiguously therein; wherein all data elements of said selected plurality of data elements of a register share one of a plurality of different data element sizes, said register has one of a plurality of different register sizes; said data processing instruction specifies one or more source registers each with a respective source register size and source data element size specified by said data processing instruction; and said data processing instruction specifies one or more destination registers with a destination register size and destination data element size specified by said data processing instruction; and further comprising register accessing logic configured to map said register to a portion of said register data store dependent upon said register size of said register such that a data element stored within said portion of said register data store is accessible as a part of respective different registers of differing register size.; wherein said register accessing logic is configured to map registers to said register data store such that a set of contiguous data elements written to adjacent portions of said register data store with two different registers can together all be read from said register data store within a single further register which has been aliased to the same location in the register data store as the two different registers. a register data store configured to store a plurality of data elements; and processing logic responsive to a data processing instruction to perform a data processing operation in parallel upon a selected plurality of data elements accessed as a register of said register data store and disposed contiguously therein; wherein all data elements of said selected plurality of data elements of a register share one of a plurality of different data element sizes, said register has one of a plurality of different register sizes; said data processing instruction specifies one or more source registers each with a respective source register size and source data element size specified by said data processing instruction; and said data processing instruction specifies one or more destination registers with a destination register size and destination data element size specified by said data processing instruction; and further comprising register accessing logic configured to map said register to a portion of said register data store dependent upon said register size of said register such that a data element stored within said portion of said register data store is accessible as a part of respective different registers of differing register size.; wherein said register accessing logic is configured to map registers to said register data store such that a set of contiguous data elements written to adjacent portions of said register data store with two different registers can together all be read from said register data store within a single further register which has been aliased to the same location in the register data store as the two different registers.