An electronic device (100, 300, 400, 500), comprising: a power input (103, 303) configured to receive a source voltage (VSRC, VBAT); a capacitor input (109, 309) configured to receive capacitor voltage (VCAP) from a capacitor; a primary regulator circuit (110, 310) having an input configured to receive said source voltage (VSRC, VBAT) and having an output (105, 305) configured to be coupled to the capacitor and to maintain a charge on said capacitor during an active mode and not to contribute to said charge on said capacitor during a low power mode; an always-on load (120, 320) that is active during said active mode and low power mode; a secondary regulator having an input configured to receive said capacitor voltage (VCAP) and having an output configured to provide a regulated voltage on a regulated voltage node coupled to an intrinsic capacitance that charges to said regulated voltage during said active mode; and a recycle control circuit (516, 616) that is active during said low power mode, comprising: a select circuit (332, 632) configured to select, based on a control signal, between said capacitor voltage (VCAP) and at least said regulated voltage on said regulated voltage node and optionally said source voltage (VSRC, VBAT) to provide power to said always-on load (120, 320) during said low power mode; and a select control circuit (330, 430, 630, 631) configured to provide said control signal to control power provided to said always-on load (120, 320) during said low power mode; and wherein said select control circuit comprises a first comparator (330, 630) that is configured to compare said regulated voltage on said regulated voltage node with a first predetermined reference voltage (VREF, VREF1) and that is configured to provide a first select signal (S,S1) indicative thereof; wherein said control signal comprises said first select signal (S, S1). a power input (103, 303) configured to receive a source voltage (VSRC, VBAT); a capacitor input (109, 309) configured to receive capacitor voltage (VCAP) from a capacitor; a primary regulator circuit (110, 310) having an input configured to receive said source voltage (VSRC, VBAT) and having an output (105, 305) configured to be coupled to the capacitor and to maintain a charge on said capacitor during an active mode and not to contribute to said charge on said capacitor during a low power mode; an always-on load (120, 320) that is active during said active mode and low power mode; a secondary regulator having an input configured to receive said capacitor voltage (VCAP) and having an output configured to provide a regulated voltage on a regulated voltage node coupled to an intrinsic capacitance that charges to said regulated voltage during said active mode; and a recycle control circuit (516, 616) that is active during said low power mode, comprising: a select circuit (332, 632) configured to select, based on a control signal, between said capacitor voltage (VCAP) and at least said regulated voltage on said regulated voltage node and optionally said source voltage (VSRC, VBAT) to provide power to said always-on load (120, 320) during said low power mode; and a select control circuit (330, 430, 630, 631) configured to provide said control signal to control power provided to said always-on load (120, 320) during said low power mode; and a select circuit (332, 632) configured to select, based on a control signal, between said capacitor voltage (VCAP) and at least said regulated voltage on said regulated voltage node and optionally said source voltage (VSRC, VBAT) to provide power to said always-on load (120, 320) during said low power mode; and a select control circuit (330, 430, 630, 631) configured to provide said control signal to control power provided to said always-on load (120, 320) during said low power mode; and wherein said select control circuit comprises a first comparator (330, 630) that is configured to compare said regulated voltage on said regulated voltage node with a first predetermined reference voltage (VREF, VREF1) and that is configured to provide a first select signal (S,S1) indicative thereof; wherein said control signal comprises said first select signal (S, S1).