A semiconductor package assembly (500b; 500c; 500d), comprising: a first semiconductor package (300b; 300c; 300d), comprising: a first semiconductor die; a first molding compound covering and surrounding the first semiconductor die, wherein the molding compound has opposite surfaces (352, 354) that are respectively close to a front surface and a back surface of the semiconductor die; a first redistribution layer structure disposed over the front surface of the semiconductor die and on one of the surfaces of the molding compound and coupled to the first semiconductor die, wherein the first redistribution layer structure comprises: a first conductive trace at a first layer-level; a second conductive trace at a second layer-level; and a first inter-metal dielectric layer and a second inter-metal dielectric layer, wherein the second inter-metal dielectric layer is beside the first inter-metal dielectric layer; wherein the first inter-metal dielectric layer and the second inter-metal dielectric layer are disposed between the first conductive trace and the second conductive trace, thereby forming a metal-insulator-metal capacitor structure, wherein the metal-insulator-metal capacitor structure includes a first electrode (452b-1), a second electrode (454b-1) and the second inter-metal dielectric layer, wherein the first electrode (452b-1) is a portion of the first conductive trace, wherein the second electrode (454b-1) is a portion of the second conductive trace; wherein the second inter-metal dielectric layer is zigzag shape in a cross-sectional view; wherein said portion of the first conductive trace and said portion of the second conductive trace, which are in contact with the second inter-metal dielectric layer, are zigzag shapes in the cross-sectional view: wherein the thickness of the second inter-metal dielectric layer is less than or equal to those (T1, T2) of the first conductive trace and the second conductive trace, and wherein the thickness of the second inter-metal dielectric layer is less than the thickness of the first inter-metal dielectric layer. a first semiconductor die; a first molding compound covering and surrounding the first semiconductor die, wherein the molding compound has opposite surfaces (352, 354) that are respectively close to a front surface and a back surface of the semiconductor die; a first redistribution layer structure disposed over the front surface of the semiconductor die and on one of the surfaces of the molding compound and coupled to the first semiconductor die, wherein the first redistribution layer structure comprises: a first conductive trace at a first layer-level; a second conductive trace at a second layer-level; and a first inter-metal dielectric layer and a second inter-metal dielectric layer, wherein the second inter-metal dielectric layer is beside the first inter-metal dielectric layer; wherein the first inter-metal dielectric layer and the second inter-metal dielectric layer are disposed between the first conductive trace and the second conductive trace, thereby forming a metal-insulator-metal capacitor structure, wherein the metal-insulator-metal capacitor structure includes a first electrode (452b-1), a second electrode (454b-1) and the second inter-metal dielectric layer, wherein the first electrode (452b-1) is a portion of the first conductive trace, wherein the second electrode (454b-1) is a portion of the second conductive trace; wherein the second inter-metal dielectric layer is zigzag shape in a cross-sectional view; wherein said portion of the first conductive trace and said portion of the second conductive trace, which are in contact with the second inter-metal dielectric layer, are zigzag shapes in the cross-sectional view: wherein the thickness of the second inter-metal dielectric layer is less than or equal to those (T1, T2) of the first conductive trace and the second conductive trace, and wherein the thickness of the second inter-metal dielectric layer is less than the thickness of the first inter-metal dielectric layer. a first conductive trace at a first layer-level; a second conductive trace at a second layer-level; and a first inter-metal dielectric layer and a second inter-metal dielectric layer, wherein the second inter-metal dielectric layer is beside the first inter-metal dielectric layer; wherein the first inter-metal dielectric layer and the second inter-metal dielectric layer are disposed between the first conductive trace and the second conductive trace, thereby forming a metal-insulator-metal capacitor structure, wherein the metal-insulator-metal capacitor structure includes a first electrode (452b-1), a second electrode (454b-1) and the second inter-metal dielectric layer, wherein the first electrode (452b-1) is a portion of the first conductive trace, wherein the second electrode (454b-1) is a portion of the second conductive trace; wherein the second inter-metal dielectric layer is zigzag shape in a cross-sectional view; wherein said portion of the first conductive trace and said portion of the second conductive trace, which are in contact with the second inter-metal dielectric layer, are zigzag shapes in the cross-sectional view: wherein the thickness of the second inter-metal dielectric layer is less than or equal to those (T1, T2) of the first conductive trace and the second conductive trace, and wherein the thickness of the second inter-metal dielectric layer is less than the thickness of the first inter-metal dielectric layer.