An integrated circuit comprising: a plurality of interconnects (16C, 16D, 16E) operable to route signals throughout the integrated circuit; a logic region comprising: a plurality of inputs, a register, processing circuitry having look-up table circuitry, adder circuitry or multiplier circuitry, wherein the processing circuitry is operable to receive the signals from a selected subset of selected interconnects of the plurality of interconnects (16C, 16D, 16E) and wherein the processing circuitry is further operable to process the received signals and to produce output signals, and a multiplexer operable to receive at least one of the output signals from the processing circuitry and receive signals from the selected interconnects from the plurality of interconnects (16C, 16D, 16E) from a bypass circuitry, and to provide a portion of the received signals to the register; input selection circuitry operable to provide signals from the selected interconnects from the plurality of interconnects (16C, 16D, 16E) to the inputs of the logic region; and the bypass circuitry coupled between the plurality of interconnects (16C, 16D, 16E) and the inputs of the logic region, wherein the bypass circuitry is operable to bypass the input selection circuitry by selectively routing signals from the selected interconnects to the inputs of the multiplexer of the logic region. a plurality of interconnects (16C, 16D, 16E) operable to route signals throughout the integrated circuit; a logic region comprising: a plurality of inputs, a register, processing circuitry having look-up table circuitry, adder circuitry or multiplier circuitry, wherein the processing circuitry is operable to receive the signals from a selected subset of selected interconnects of the plurality of interconnects (16C, 16D, 16E) and wherein the processing circuitry is further operable to process the received signals and to produce output signals, and a multiplexer operable to receive at least one of the output signals from the processing circuitry and receive signals from the selected interconnects from the plurality of interconnects (16C, 16D, 16E) from a bypass circuitry, and to provide a portion of the received signals to the register; a plurality of inputs, a register, processing circuitry having look-up table circuitry, adder circuitry or multiplier circuitry, wherein the processing circuitry is operable to receive the signals from a selected subset of selected interconnects of the plurality of interconnects (16C, 16D, 16E) and wherein the processing circuitry is further operable to process the received signals and to produce output signals, and a multiplexer operable to receive at least one of the output signals from the processing circuitry and receive signals from the selected interconnects from the plurality of interconnects (16C, 16D, 16E) from a bypass circuitry, and to provide a portion of the received signals to the register; input selection circuitry operable to provide signals from the selected interconnects from the plurality of interconnects (16C, 16D, 16E) to the inputs of the logic region; and the bypass circuitry coupled between the plurality of interconnects (16C, 16D, 16E) and the inputs of the logic region, wherein the bypass circuitry is operable to bypass the input selection circuitry by selectively routing signals from the selected interconnects to the inputs of the multiplexer of the logic region.