A semiconductor device, comprising: - a semiconductor substrate; - a drift region of first conductivity type which is provided on the semiconductor substrate; - a plurality of first well regions of second conductivity type which are provided within the drift region and are partially exposed in a major surface of the drift region; - a plurality of source regions of the first conductivity type which are located within the first well regions and are partially exposed in the major surface; - three or more insulating gate portions (6 to 8) which form channels reversed to the first conductivity type in part of the first well regions located between the drift region and source regions; and - a first main electrode (9, 11, 12) which forms a contact with the drift region exposed in the major surface to constitute a unipolar diode and is connected to the first well regions and the source regions, wherein - each of the insulating gate portions (6 to 8) includes: - a gate insulating film provided on an inner wall of a trench formed in the major surface (F S) of the drift region, the trench being formed in contact with the drift region, the first well regions, and of the source regions, and - a gate electrode provided within the trench surrounded by the gate insulating film, - the plurality of insulating gate portions (6 to 8) have linear patterns parallel to each other when viewed in the normal direction of the major surface, - between each pair of adjacent insulating gate portions (6 to 8), the first well regions and junction portions in which the first main electrode (9, 11, 12) forms junctions with the drift region are alternately arrayed at the major surface along the direction that the insulating gate portions (6 to 8) extend, and the first well regions and the junction portions in which the first main electrode (9, 11, 12) form junctions with the drift region are arranged in line along a direction vertical to the direction that the insulating gate portions (6 to 8) extend and vertical to the normal direction, - the channels are formed in the normal direction of the major surface and in a direction vertical to the normal of the major surface and parallel to the direction that the insulating gate portions extend, and - length of the channels formed in the vertical direction to the normal of the major surface is longer than length of the channels formed in the normal direction of the major surface. - a semiconductor substrate; - a drift region of first conductivity type which is provided on the semiconductor substrate; - a plurality of first well regions of second conductivity type which are provided within the drift region and are partially exposed in a major surface of the drift region; - a plurality of source regions of the first conductivity type which are located within the first well regions and are partially exposed in the major surface; - three or more insulating gate portions (6 to 8) which form channels reversed to the first conductivity type in part of the first well regions located between the drift region and source regions; and - a first main electrode (9, 11, 12) which forms a contact with the drift region exposed in the major surface to constitute a unipolar diode and is connected to the first well regions and the source regions, - each of the insulating gate portions (6 to 8) includes: - a gate insulating film provided on an inner wall of a trench formed in the major surface (F S) of the drift region, the trench being formed in contact with the drift region, the first well regions, and of the source regions, and - a gate electrode provided within the trench surrounded by the gate insulating film, - a gate insulating film provided on an inner wall of a trench formed in the major surface (F S) of the drift region, the trench being formed in contact with the drift region, the first well regions, and of the source regions, and - a gate electrode provided within the trench surrounded by the gate insulating film, - the plurality of insulating gate portions (6 to 8) have linear patterns parallel to each other when viewed in the normal direction of the major surface, - between each pair of adjacent insulating gate portions (6 to 8), the first well regions and junction portions in which the first main electrode (9, 11, 12) forms junctions with the drift region are alternately arrayed at the major surface along the direction that the insulating gate portions (6 to 8) extend, and the first well regions and the junction portions in which the first main electrode (9, 11, 12) form junctions with the drift region are arranged in line along a direction vertical to the direction that the insulating gate portions (6 to 8) extend and vertical to the normal direction, - the channels are formed in the normal direction of the major surface and in a direction vertical to the normal of the major surface and parallel to the direction that the insulating gate portions extend, and - length of the channels formed in the vertical direction to the normal of the major surface is longer than length of the channels formed in the normal direction of the major surface.