A communication device, comprising: transmission and reception circuitry configured to communicate with external communication device, including transmitting and receiving data via a data signal line and transmitting a clock via a clock signal line; and control circuitry configured to detect an occurrence of an error in a signal by comparing a first bit sequence of a signal received following a preamble of the data to a second bit sequence corresponding to a data type designated for transmission by the preamble, wherein when the preamble of the data specifies transmission of a cyclic redundancy check, CRC, word, the CRC word including a token and a CRC-5, the control circuitry is configured to detect an occurrence of at least one of a token error or a CRC error on the basis of the first bit sequence, and in a case where the occurrence of the error is detected the transmission and reception circuitry is configured to transmit a clock for a first duration corresponding to at least a predetermined number of bits following the preamble, wherein the transmission and reception circuitry is configured to transmit a high data rate, HDR, exit command signal or an HDR restart command signal after transmitting the clock for a second duration corresponding to at least the number of bits in the CRC word and after receiving an additional clock for the first duration, said first duration having length corresponding to the difference between the number of bits in the CRC word and the number of bits in the read data, wherein the control circuitry is configured to ignore the data for at least a period during transmission of the additional clock. transmission and reception circuitry configured to communicate with external communication device, including transmitting and receiving data via a data signal line and transmitting a clock via a clock signal line; and control circuitry configured to detect an occurrence of an error in a signal by comparing a first bit sequence of a signal received following a preamble of the data to a second bit sequence corresponding to a data type designated for transmission by the preamble, wherein when the preamble of the data specifies transmission of a cyclic redundancy check, CRC, word, the CRC word including a token and a CRC-5, the control circuitry is configured to detect an occurrence of at least one of a token error or a CRC error on the basis of the first bit sequence, and in a case where the occurrence of the error is detected the transmission and reception circuitry is configured to transmit a clock for a first duration corresponding to at least a predetermined number of bits following the preamble, wherein the transmission and reception circuitry is configured to transmit a high data rate, HDR, exit command signal or an HDR restart command signal after transmitting the clock for a second duration corresponding to at least the number of bits in the CRC word and after receiving an additional clock for the first duration, said first duration having length corresponding to the difference between the number of bits in the CRC word and the number of bits in the read data, wherein the control circuitry is configured to ignore the data for at least a period during transmission of the additional clock. detect an occurrence of an error in a signal by comparing a first bit sequence of a signal received following a preamble of the data to a second bit sequence corresponding to a data type designated for transmission by the preamble, wherein when the preamble of the data specifies transmission of a cyclic redundancy check, CRC, word, the CRC word including a token and a CRC-5, the control circuitry is configured to detect an occurrence of at least one of a token error or a CRC error on the basis of the first bit sequence, and in a case where the occurrence of the error is detected the transmission and reception circuitry is configured to transmit a clock for a first duration corresponding to at least a predetermined number of bits following the preamble, wherein the transmission and reception circuitry is configured to transmit a high data rate, HDR, exit command signal or an HDR restart command signal after transmitting the clock for a second duration corresponding to at least the number of bits in the CRC word and after receiving an additional clock for the first duration, said first duration having length corresponding to the difference between the number of bits in the CRC word and the number of bits in the read data, wherein the control circuitry is configured to ignore the data for at least a period during transmission of the additional clock.