A semiconductor device comprising a first NTFT and a second NTFT on a substrate, each of the first NTFT and the second NTFT comprising: a semiconductor layer having a channel forming region, a first impurity region, a second impurity region, and a third impurity region formed between the first impurity region and the second impurity region, wherein the first impurity region is an n-type impurity region; and a gate electrode adjacent to the semiconductor layer with a gate insulating film interposed therebetween, wherein the film thickness of the gate electrode decreases linearly or stepwise from a central flat section, at the periphery of the gate electrode, outward; wherein the first impurity region functions as a source region or a drain region, wherein the second impurity region is located in the semiconductor layer so as to overlap the gate electrode with the gate insulating film interposed therebetween, wherein a portion of the gate electrode that overlaps the second impurity region has a tapered shape wherein the third impurity region does not overlap the gate electrode, wherein a concentration of an impurity element included in the second impurity region increases with decreasing distance from the third impurity region, the concentration gradient reflecting the inclination of the side face of the gate electrode, and the concentration of the impurity element in the second and third impurity regions is less than that of the first impurity region, wherein the impurity element is almost uniformly doped throughout the third impurity region, and wherein a length of the second impurity region formed in the second NTFT is longer than a length of the second impurity region formed in the first NTFT. a semiconductor layer having a channel forming region, a first impurity region, a second impurity region, and a third impurity region formed between the first impurity region and the second impurity region, wherein the first impurity region is an n-type impurity region; and a gate electrode adjacent to the semiconductor layer with a gate insulating film interposed therebetween, wherein the film thickness of the gate electrode decreases linearly or stepwise from a central flat section, at the periphery of the gate electrode, outward; wherein the first impurity region functions as a source region or a drain region, wherein the second impurity region is located in the semiconductor layer so as to overlap the gate electrode with the gate insulating film interposed therebetween, wherein a portion of the gate electrode that overlaps the second impurity region has a tapered shape wherein the third impurity region does not overlap the gate electrode, wherein a concentration of an impurity element included in the second impurity region increases with decreasing distance from the third impurity region, the concentration gradient reflecting the inclination of the side face of the gate electrode, and the concentration of the impurity element in the second and third impurity regions is less than that of the first impurity region, wherein the impurity element is almost uniformly doped throughout the third impurity region, and wherein a length of the second impurity region formed in the second NTFT is longer than a length of the second impurity region formed in the first NTFT.