A method for actuating the switching elements of three-phase inverter stages switched in parallel, wherein each of the six switching elements of an inverter stage has two switching states (0, 1) each, and the total switching state of an inverter stage is determined by a combination of the switching states (0, 1) of its switching elements, which combination can be represented as a switching state bit sequence of six bits, and by switching the switching elements with a switching frequency a time sequence of total switching states of the inverter stage selected from a number of permitted total switching states is realized for forming a desired output current of the inverter stage, wherein - the actuation of the switching elements of an inverter stage occurs via a central control unit connected to the respective inverter stage via a serial data transmission path, - wherein the central control unit unambiguously assigns a transmission bit sequence consisting of ten bits to each switching state bit sequence which corresponds to a permitted total switching state of the inverter stages, wherein each transmission bit sequence, which is assigned to a permitted total switching state of the inverter stage, differs by at least four bits from another transmission bit sequence which is assigned to another permitted total switching state of the inverter stage, - and the central control unit for actuating a selected total switching state transmits the transmission bit sequence assigned to said selected total switching state to the respective inverter stage, and the transmitted transmission bit sequence is received by the inverter stage as at least one receiving bit sequence and assigned to a switching state bit sequence, - wherein the transmission bit sequence is transmitted at a transmission rate measured in bits per second, whose ratio to the switching frequency of the switching elements measured in Hertz is at least 1000, - and a change in the total switching state of an inverter stage is only carried out when the receiving bit sequence received in the respective inverter stage corresponds to a bit sequence from a predetermined bit sequence group which is formed by transmission bit sequences which are respectively unambiguously assigned to a permitted total switching state of the inverter stage and by bit sequences which differ from said transmission bit sequences by not more than one bit. - the actuation of the switching elements of an inverter stage occurs via a central control unit connected to the respective inverter stage via a serial data transmission path, - wherein the central control unit unambiguously assigns a transmission bit sequence consisting of ten bits to each switching state bit sequence which corresponds to a permitted total switching state of the inverter stages, wherein each transmission bit sequence, which is assigned to a permitted total switching state of the inverter stage, differs by at least four bits from another transmission bit sequence which is assigned to another permitted total switching state of the inverter stage, - and the central control unit for actuating a selected total switching state transmits the transmission bit sequence assigned to said selected total switching state to the respective inverter stage, and the transmitted transmission bit sequence is received by the inverter stage as at least one receiving bit sequence and assigned to a switching state bit sequence, - wherein the transmission bit sequence is transmitted at a transmission rate measured in bits per second, whose ratio to the switching frequency of the switching elements measured in Hertz is at least 1000, - and a change in the total switching state of an inverter stage is only carried out when the receiving bit sequence received in the respective inverter stage corresponds to a bit sequence from a predetermined bit sequence group which is formed by transmission bit sequences which are respectively unambiguously assigned to a permitted total switching state of the inverter stage and by bit sequences which differ from said transmission bit sequences by not more than one bit.