A semiconductor memory device, comprising: a memory cell array with a plurality of memory cells storing data disposed therein; a processing circuit (202, 203, 204) decoding a plurality of command signals corresponding to a plurality of external access requests to said memory cell array supplied from an outside of the semiconductor memory device and an address signal, and instructing an operation to be executed in said memory cell array based on a decoded result; and an array control circuit executing an operation for said memory cell array based on an instruction from said processing circuit, wherein said processing circuit (202, 203, 204) comprises a chip control circuit, an address decoder and an address control circuit, said address decoder is adapted to selectively decode one of the address signal from the outside and a refresh address signal (REFA) from the address control circuit of the semiconductor memory device in accordance with a refresh command (REFC), and the plurality of command signals includes a chip enable signal, an output enable signal and a write enable signal, when the plurality of command signals and the address signal are in a predetermined combination, said processing circuit is adapted to instruct to execute a refresh operation to hold data stored in the memory cells in said memory cell array, wherein the chip control circuit is adapted to decode the command signals and the address signal from an outside of the device, and to instruct to execute the refresh operation, based on the decoded result; the address control circuit generates the refresh address signal (REFA); and the address decoder is adapted to decode the refresh address signal generated by the address control circuit, in the case in which the chip control circuit instructs to execute the refresh operation; characterised in that when the command signals and the address signal from the outside are in the predetermined combination, which is set as the external access request for data read or write operation for a predetermined specified address, the chip control circuit instructs to execute the refresh operation and the data read or write operation is not performed. a memory cell array with a plurality of memory cells storing data disposed therein; a processing circuit (202, 203, 204) decoding a plurality of command signals corresponding to a plurality of external access requests to said memory cell array supplied from an outside of the semiconductor memory device and an address signal, and instructing an operation to be executed in said memory cell array based on a decoded result; and an array control circuit executing an operation for said memory cell array based on an instruction from said processing circuit, wherein said processing circuit (202, 203, 204) comprises a chip control circuit, an address decoder and an address control circuit, said address decoder is adapted to selectively decode one of the address signal from the outside and a refresh address signal (REFA) from the address control circuit of the semiconductor memory device in accordance with a refresh command (REFC), and the plurality of command signals includes a chip enable signal, an output enable signal and a write enable signal, when the plurality of command signals and the address signal are in a predetermined combination, said processing circuit is adapted to instruct to execute a refresh operation to hold data stored in the memory cells in said memory cell array, wherein the chip control circuit is adapted to decode the command signals and the address signal from an outside of the device, and to instruct to execute the refresh operation, based on the decoded result; the address control circuit generates the refresh address signal (REFA); and the address decoder is adapted to decode the refresh address signal generated by the address control circuit, in the case in which the chip control circuit instructs to execute the refresh operation; characterised in that when the command signals and the address signal from the outside are in the predetermined combination, which is set as the external access request for data read or write operation for a predetermined specified address, the chip control circuit instructs to execute the refresh operation and the data read or write operation is not performed.