A clock data restoration device which restores a clock signal and data on the basis of an inputted digital signal, comprising: an equalizer which adjusts the level of a high frequency component of the inputted digital signal and outputs the adjusted digital signal; a sampler which receives an input of a clock signal CK and a clock signal CKX which have a same cycle T, and receives an input of the adjusted digital signal outputted by said equalizer, and which samples, holds, and outputs a value D(n) of said adjusted digital signal at a time tC indicated by said clock signal CK, and samples, holds, and outputs a value DX(n) of said adjusted digital signal at a time tX indicated by said clock signal CKX, in each n-th period T(n) of the cycle; a clock generator which, in each period T(n), adjusts the cycle T or a phase on the basis of the value D(n) and the value DX(n) outputted by said sampler, in such a manner that a phase difference between said clock signal CK and said digital signal decreases, and outputs to said sampler said clock signal CK and said clock signal CKX satisfying a relationship tX-tC = T/2; and an equalizer controller which, in each period T(n), determines a value EQLCTL on the basis of the value D(n) and the value DX(n) outputted by said sampler and outputs the value EQLCTL to control a level adjustment amount of the high frequency component of said digital signal by said equalizer; wherein tC<tX and n is an integer; characterised in that: the equalizer comprises a high pass filter circuit, an amplifier circuit and an adder circuit; the high pass filter circuit selectively allows a high frequency component of the input digital signal to pass, and outputs the resulting signal to the amplifier circuit; the amplifier circuit amplifies the signal outputted by the high pass filter circuit in accordance with a gain which is set on the basis of the value EQLCTL outputted by the equalizer controller, and outputs the amplified signal to the adder circuit; and the adder circuit receives the input of the input digital signal and the amplified signal outputted by the amplifier circuit, and outputs to the sampler the result of adding the input digital signal and the amplified signal. an equalizer which adjusts the level of a high frequency component of the inputted digital signal and outputs the adjusted digital signal; a sampler which receives an input of a clock signal CK and a clock signal CKX which have a same cycle T, and receives an input of the adjusted digital signal outputted by said equalizer, and which samples, holds, and outputs a value D(n) of said adjusted digital signal at a time tC indicated by said clock signal CK, and samples, holds, and outputs a value DX(n) of said adjusted digital signal at a time tX indicated by said clock signal CKX, in each n-th period T(n) of the cycle; a clock generator which, in each period T(n), adjusts the cycle T or a phase on the basis of the value D(n) and the value DX(n) outputted by said sampler, in such a manner that a phase difference between said clock signal CK and said digital signal decreases, and outputs to said sampler said clock signal CK and said clock signal CKX satisfying a relationship tX-tC = T/2; and an equalizer controller which, in each period T(n), determines a value EQLCTL on the basis of the value D(n) and the value DX(n) outputted by said sampler and outputs the value EQLCTL to control a level adjustment amount of the high frequency component of said digital signal by said equalizer; wherein tC<tX and n is an integer; characterised in that: the equalizer comprises a high pass filter circuit, an amplifier circuit and an adder circuit; the high pass filter circuit selectively allows a high frequency component of the input digital signal to pass, and outputs the resulting signal to the amplifier circuit; the amplifier circuit amplifies the signal outputted by the high pass filter circuit in accordance with a gain which is set on the basis of the value EQLCTL outputted by the equalizer controller, and outputs the amplified signal to the adder circuit; and the adder circuit receives the input of the input digital signal and the amplified signal outputted by the amplifier circuit, and outputs to the sampler the result of adding the input digital signal and the amplified signal. the equalizer comprises a high pass filter circuit, an amplifier circuit and an adder circuit; the high pass filter circuit selectively allows a high frequency component of the input digital signal to pass, and outputs the resulting signal to the amplifier circuit; the amplifier circuit amplifies the signal outputted by the high pass filter circuit in accordance with a gain which is set on the basis of the value EQLCTL outputted by the equalizer controller, and outputs the amplified signal to the adder circuit; and the adder circuit receives the input of the input digital signal and the amplified signal outputted by the amplifier circuit, and outputs to the sampler the result of adding the input digital signal and the amplified signal.