An integrated circuit device, comprising: a read only memory matrix, comprising cells organized in columns with associated bit lines and rows with associated word lines, the matrix comprising data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells; a differential sense amplifier, having a first input, a second input, and a control input (SNS, SNSn) for controlling activation and deactivation of amplification by the sense amplifier; a coupling circuit coupled between the bit lines and the first input, for controllably permitting charge sharing between a selectable one of the bit lines and the first input; a reference circuit coupled to the second input, and arranged to controllably activate driving of a reference voltage at the second input; a timing circuit arranged to signal operation in a first phase, when the word lines have selected a row of the matrix, followed by a second phase, the timing circuit controlling the coupling circuit to permit charge sharing between the first input and the selectable one of the bit lines in the first phase, and the timing circuit in the second phase controlling the coupling circuit to prevent said charge sharing, making the reference circuit deactivate driving the reference voltage, and subsequently activating amplification by the differential sense amplifier, wherein the timing circuit comprises: a dummy bit line with a capacitive load substantially corresponding to the capacitive load of any of the bit lines with a maximum number of data transistors coupled thereto; a dummy data transistor coupled to the dummy bit line; a trigger circuit for triggering the second phase, the trigger circuit activating the dummy data transistor in the first phase and starting the second phase when a potential swing on the dummy bit line due to activation of the dummy data transistor in the first phase exceeds a threshold value larger than a potential swing that is needed on the bit line to cross the reference voltage. a read only memory matrix, comprising cells organized in columns with associated bit lines and rows with associated word lines, the matrix comprising data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells; a differential sense amplifier, having a first input, a second input, and a control input (SNS, SNSn) for controlling activation and deactivation of amplification by the sense amplifier; a coupling circuit coupled between the bit lines and the first input, for controllably permitting charge sharing between a selectable one of the bit lines and the first input; a reference circuit coupled to the second input, and arranged to controllably activate driving of a reference voltage at the second input; a timing circuit arranged to signal operation in a first phase, when the word lines have selected a row of the matrix, followed by a second phase, the timing circuit controlling the coupling circuit to permit charge sharing between the first input and the selectable one of the bit lines in the first phase, and the timing circuit in the second phase controlling the coupling circuit to prevent said charge sharing, making the reference circuit deactivate driving the reference voltage, and subsequently activating amplification by the differential sense amplifier, wherein the timing circuit comprises: a dummy bit line with a capacitive load substantially corresponding to the capacitive load of any of the bit lines with a maximum number of data transistors coupled thereto; a dummy data transistor coupled to the dummy bit line; a trigger circuit for triggering the second phase, the trigger circuit activating the dummy data transistor in the first phase and starting the second phase when a potential swing on the dummy bit line due to activation of the dummy data transistor in the first phase exceeds a threshold value larger than a potential swing that is needed on the bit line to cross the reference voltage. a dummy bit line with a capacitive load substantially corresponding to the capacitive load of any of the bit lines with a maximum number of data transistors coupled thereto; a dummy data transistor coupled to the dummy bit line; a trigger circuit for triggering the second phase, the trigger circuit activating the dummy data transistor in the first phase and starting the second phase when a potential swing on the dummy bit line due to activation of the dummy data transistor in the first phase exceeds a threshold value larger than a potential swing that is needed on the bit line to cross the reference voltage.