An array substrate, comprising: a base substrate, a pixel array and an auxiliary conductive structure which are on the base substrate; wherein the pixel array comprises a plurality of pixel units distributed in an array and a plurality of pixel electrodes, and each of the plurality of pixel units comprises at least one of the plurality of pixel electrodes; the auxiliary conductive structure surrounds at least one of the plurality of pixel electrodes and is insulated from the plurality of pixel electrodes, and a planar shape, viewed in a direction perpendicular to the base substrate, of the auxiliary conductive structure comprises a closed loop surrounding the at least one of the plurality of pixel electrodes; the array substrate further comprises: a plurality of gate lines and a plurality of data lines, provided on the base substrate and crossing each other to define the plurality of pixel units, and the auxiliary conductive structure comprises a plurality of strip portions respectively extending along an extension direction of the plurality of data lines and an extension direction of the plurality of gate lines; the plurality of strip portions of the auxiliary conductive structure overlap at least a part of the plurality of gate lines and/or overlap at least a part of the plurality of data lines in a direction perpendicular to the base substrate; the array substrate further comprises a common electrode in a layer different from a layer where the plurality of pixel electrodes are located, characterized in that: at least one strip portion among the plurality of strip portions of the auxiliary conductive structure comprises a plurality of hollow regions which are spaced apart from each other and penetrate through the at least one strip portion; and each of the plurality of hollow regions overlaps at least a part of at least one of the plurality of gate lines, the plurality of data lines and the common electrode in the direction perpendicular to the base substrate. a base substrate, a pixel array and an auxiliary conductive structure which are on the base substrate; wherein the pixel array comprises a plurality of pixel units distributed in an array and a plurality of pixel electrodes, and each of the plurality of pixel units comprises at least one of the plurality of pixel electrodes; the auxiliary conductive structure surrounds at least one of the plurality of pixel electrodes and is insulated from the plurality of pixel electrodes, and a planar shape, viewed in a direction perpendicular to the base substrate, of the auxiliary conductive structure comprises a closed loop surrounding the at least one of the plurality of pixel electrodes; the array substrate further comprises: a plurality of gate lines and a plurality of data lines, provided on the base substrate and crossing each other to define the plurality of pixel units, and the auxiliary conductive structure comprises a plurality of strip portions respectively extending along an extension direction of the plurality of data lines and an extension direction of the plurality of gate lines; the plurality of strip portions of the auxiliary conductive structure overlap at least a part of the plurality of gate lines and/or overlap at least a part of the plurality of data lines in a direction perpendicular to the base substrate; the array substrate further comprises a common electrode in a layer different from a layer where the plurality of pixel electrodes are located, characterized in that: at least one strip portion among the plurality of strip portions of the auxiliary conductive structure comprises a plurality of hollow regions which are spaced apart from each other and penetrate through the at least one strip portion; and each of the plurality of hollow regions overlaps at least a part of at least one of the plurality of gate lines, the plurality of data lines and the common electrode in the direction perpendicular to the base substrate. at least one strip portion among the plurality of strip portions of the auxiliary conductive structure comprises a plurality of hollow regions which are spaced apart from each other and penetrate through the at least one strip portion; and each of the plurality of hollow regions overlaps at least a part of at least one of the plurality of gate lines, the plurality of data lines and the common electrode in the direction perpendicular to the base substrate.