A circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes ( Q, Z), the second storage node forming an output node of the C-element; and a non-volatile memory characterized by: a first resistive element (202, 602) having a first terminal coupled to the first storage node; a second resistive element (204, 604) having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to have one of at least two resistive states (R min, R max), a data value being represented by the relative resistances of the first and second resistive elements, wherein a second terminal of the first resistive element (202, 602) is coupled to a second terminal of the second resistive element (204, 604) via a first transistor; and a control circuit adapted, during a backup phase of a data bit stored at the first and second storage nodes to the non-volatile memory, to render conductive the first transistor while different logic levels are applied to the first and second input nodes of the C-element. a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes ( Q, Z), the second storage node forming an output node of the C-element; and a non-volatile memory characterized by: a first resistive element (202, 602) having a first terminal coupled to the first storage node; a second resistive element (204, 604) having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to have one of at least two resistive states (R min, R max), a data value being represented by the relative resistances of the first and second resistive elements, wherein a second terminal of the first resistive element (202, 602) is coupled to a second terminal of the second resistive element (204, 604) via a first transistor; and a control circuit adapted, during a backup phase of a data bit stored at the first and second storage nodes to the non-volatile memory, to render conductive the first transistor while different logic levels are applied to the first and second input nodes of the C-element. a first resistive element (202, 602) having a first terminal coupled to the first storage node; a second resistive element (204, 604) having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to have one of at least two resistive states (R min, R max), a data value being represented by the relative resistances of the first and second resistive elements, wherein a second terminal of the first resistive element (202, 602) is coupled to a second terminal of the second resistive element (204, 604) via a first transistor; and a control circuit adapted, during a backup phase of a data bit stored at the first and second storage nodes to the non-volatile memory, to render conductive the first transistor while different logic levels are applied to the first and second input nodes of the C-element.