A power converter, comprising: - a first transistor, coupled between a supply voltage and a common node; - a second transistor, coupled between the common node and a ground voltage, wherein the common node has a reactive voltage, and a reactive current flows through the common node; - a pulse width modulation controller, selectively enabling and disabling the first transistor and the second transistor according to a second control signal and a first transistor control signal; - a low-pass filter, coupled between the common node and an output node (NOUT); and - a delay controller, generating the second control signal according to the reactive voltage, characterized in that - the delay controller comprising - a first comparator, comparing the reactive voltage with a reference voltage (VREF) so as to generate a first control signal; - a delay unit, delaying the first control signal for a first delay time so as to generate the second control signal, delaying the second control signal for a second delay time so as to generate a third control signal, and delaying the third control signal for a third delay time so as to generate a fourth control signal; - a second comparator, comparing the reactive voltage with the ground voltage so as to generate an evaluation signal; - a sampling unit, sampling the evaluation signal at a transition edge of the third control signal so as to generate a first digital signal, and sampling the evaluation signal at a transition edge of the fourth control signal so as to generate a second digital signal - wherein the delay unit adjusts the first delay time to the time when the first digital signal and the second digital signals have different logical levels. - a first transistor, coupled between a supply voltage and a common node; - a second transistor, coupled between the common node and a ground voltage, wherein the common node has a reactive voltage, and a reactive current flows through the common node; - a pulse width modulation controller, selectively enabling and disabling the first transistor and the second transistor according to a second control signal and a first transistor control signal; - a low-pass filter, coupled between the common node and an output node (NOUT); and - a delay controller, generating the second control signal according to the reactive voltage, - the delay controller comprising - a first comparator, comparing the reactive voltage with a reference voltage (VREF) so as to generate a first control signal; - a delay unit, delaying the first control signal for a first delay time so as to generate the second control signal, delaying the second control signal for a second delay time so as to generate a third control signal, and delaying the third control signal for a third delay time so as to generate a fourth control signal; - a second comparator, comparing the reactive voltage with the ground voltage so as to generate an evaluation signal; - a sampling unit, sampling the evaluation signal at a transition edge of the third control signal so as to generate a first digital signal, and sampling the evaluation signal at a transition edge of the fourth control signal so as to generate a second digital signal - wherein the delay unit adjusts the first delay time to the time when the first digital signal and the second digital signals have different logical levels. - a first comparator, comparing the reactive voltage with a reference voltage (VREF) so as to generate a first control signal; - a delay unit, delaying the first control signal for a first delay time so as to generate the second control signal, delaying the second control signal for a second delay time so as to generate a third control signal, and delaying the third control signal for a third delay time so as to generate a fourth control signal; - a second comparator, comparing the reactive voltage with the ground voltage so as to generate an evaluation signal; - a sampling unit, sampling the evaluation signal at a transition edge of the third control signal so as to generate a first digital signal, and sampling the evaluation signal at a transition edge of the fourth control signal so as to generate a second digital signal - wherein the delay unit adjusts the first delay time to the time when the first digital signal and the second digital signals have different logical levels.