An electronic device (102, 104) comprising: a first cache memory at a first hierarchical level; a supplemental cache memory at a second hierarchical level, the supplemental cache memory communicatively coupled to the first cache memory and configured to attempt to handle cache misses of the first cache memory, the second hierarchical level lower than the first hierarchical level, and wherein the first cache memory is larger and is configured to store more information than the supplemental cache memory; a main memory at a third hierarchical level, the main memory communicatively coupled to the first cache memory and the supplemental cache memory, the third hierarchical level lower than the second hierarchical level; and control circuitry coupled to the supplemental cache memory and the main memory, the control circuitry configured to cause a transition between two or more functional memory states, the two or more functional memory states including: a first functional memory state in which the supplemental cache memory is in an inactive operational mode and the main memory is in a regular power mode; and a second functional memory state in which the supplemental cache memory is in an active operational mode and the main memory is in a low-power mode; wherein: the inactive operational mode corresponds to the supplemental cache memory being bypassed for memory requests that miss in the first cache memory; the active operational mode corresponds to the supplemental cache memory storing information to handle the memory requests that miss in the first cache memory; the regular power mode corresponds to information in the main memory being preserved and accessible to handle the memory requests that miss in the first cache memory; and the low-power mode corresponds to information in the main memory being preserved but inaccessible until the main memory is awakened. a first cache memory at a first hierarchical level; a supplemental cache memory at a second hierarchical level, the supplemental cache memory communicatively coupled to the first cache memory and configured to attempt to handle cache misses of the first cache memory, the second hierarchical level lower than the first hierarchical level, and wherein the first cache memory is larger and is configured to store more information than the supplemental cache memory; a main memory at a third hierarchical level, the main memory communicatively coupled to the first cache memory and the supplemental cache memory, the third hierarchical level lower than the second hierarchical level; and control circuitry coupled to the supplemental cache memory and the main memory, the control circuitry configured to cause a transition between two or more functional memory states, the two or more functional memory states including: a first functional memory state in which the supplemental cache memory is in an inactive operational mode and the main memory is in a regular power mode; and a second functional memory state in which the supplemental cache memory is in an active operational mode and the main memory is in a low-power mode; wherein: the inactive operational mode corresponds to the supplemental cache memory being bypassed for memory requests that miss in the first cache memory; the active operational mode corresponds to the supplemental cache memory storing information to handle the memory requests that miss in the first cache memory; the regular power mode corresponds to information in the main memory being preserved and accessible to handle the memory requests that miss in the first cache memory; and the low-power mode corresponds to information in the main memory being preserved but inaccessible until the main memory is awakened. a first functional memory state in which the supplemental cache memory is in an inactive operational mode and the main memory is in a regular power mode; and a second functional memory state in which the supplemental cache memory is in an active operational mode and the main memory is in a low-power mode; wherein: the inactive operational mode corresponds to the supplemental cache memory being bypassed for memory requests that miss in the first cache memory; the active operational mode corresponds to the supplemental cache memory storing information to handle the memory requests that miss in the first cache memory; the regular power mode corresponds to information in the main memory being preserved and accessible to handle the memory requests that miss in the first cache memory; and the low-power mode corresponds to information in the main memory being preserved but inaccessible until the main memory is awakened. the inactive operational mode corresponds to the supplemental cache memory being bypassed for memory requests that miss in the first cache memory; the active operational mode corresponds to the supplemental cache memory storing information to handle the memory requests that miss in the first cache memory; the regular power mode corresponds to information in the main memory being preserved and accessible to handle the memory requests that miss in the first cache memory; and the low-power mode corresponds to information in the main memory being preserved but inaccessible until the main memory is awakened.