An ultra-wideband, UWB, device comprising: a processing circuit managing power consumption of the UWB device; and a low power UWB wireless circuit comprising a UWB transceiver; and characterised by comprising: a receiver circuit of the UWB transceiver comprising: a first squaring mixer configured to convert the ultra-wideband wireless signals to intermediate frequency signals and a second squaring mixer configured to convert the amplified intermediate frequency signals to baseband frequency signals; wherein an output of the first squaring mixer is coupled to an input of the second squaring mixer and an output of the second squaring mixer is coupled to a digital processor within the receiver circuit; each of the first squaring mixer and second squaring mixer receive a pair of differential signals; each of the first squaring mixer and the second squaring mixer comprise a first transistor pair cross-coupled with a second transistor pair; a first differential signal of the pair of differential signals is coupled to a gate of a first transistor within each of the first transistor pair and the second pair and to a gate of a third transistor; a second differential signal of the pair of differential signals is coupled to a gate of a second transistor within each of the first cross-coupled transistor pair and the second cross-coupled transistor pair and to a gate of a fourth transistor; the sources of the first cross-coupled transistor pair are connected and coupled to the drain of the third transistor; and the sources of the second cross-coupled transistor pair are connected and coupled to the drain of the fourth transistor. a processing circuit managing power consumption of the UWB device; and a low power UWB wireless circuit comprising a UWB transceiver; and characterised by comprising: a receiver circuit of the UWB transceiver comprising: a first squaring mixer configured to convert the ultra-wideband wireless signals to intermediate frequency signals and a second squaring mixer configured to convert the amplified intermediate frequency signals to baseband frequency signals; wherein an output of the first squaring mixer is coupled to an input of the second squaring mixer and an output of the second squaring mixer is coupled to a digital processor within the receiver circuit; each of the first squaring mixer and second squaring mixer receive a pair of differential signals; each of the first squaring mixer and the second squaring mixer comprise a first transistor pair cross-coupled with a second transistor pair; a first differential signal of the pair of differential signals is coupled to a gate of a first transistor within each of the first transistor pair and the second pair and to a gate of a third transistor; a second differential signal of the pair of differential signals is coupled to a gate of a second transistor within each of the first cross-coupled transistor pair and the second cross-coupled transistor pair and to a gate of a fourth transistor; the sources of the first cross-coupled transistor pair are connected and coupled to the drain of the third transistor; and the sources of the second cross-coupled transistor pair are connected and coupled to the drain of the fourth transistor. a first squaring mixer configured to convert the ultra-wideband wireless signals to intermediate frequency signals and a second squaring mixer configured to convert the amplified intermediate frequency signals to baseband frequency signals; wherein an output of the first squaring mixer is coupled to an input of the second squaring mixer and an output of the second squaring mixer is coupled to a digital processor within the receiver circuit; each of the first squaring mixer and second squaring mixer receive a pair of differential signals; each of the first squaring mixer and the second squaring mixer comprise a first transistor pair cross-coupled with a second transistor pair; a first differential signal of the pair of differential signals is coupled to a gate of a first transistor within each of the first transistor pair and the second pair and to a gate of a third transistor; a second differential signal of the pair of differential signals is coupled to a gate of a second transistor within each of the first cross-coupled transistor pair and the second cross-coupled transistor pair and to a gate of a fourth transistor; the sources of the first cross-coupled transistor pair are connected and coupled to the drain of the third transistor; and the sources of the second cross-coupled transistor pair are connected and coupled to the drain of the fourth transistor.