A memory system comprising: a nonvolatile semiconductor memory having a plurality of channel parallel operation elements (10a, 10b, 10c, 10d), each of the channel parallel operation elements (10a, 10b, 10c, 10d) including a plurality of memory chips, each of the memory chips including a plurality of planes capable of operating in parallel, each plane including a plurality of physical blocks, each of the physical blocks being a unit of data erasing, the plurality of memory chips in the respective channel parallel operation elements (10a, 10b, 10c, 10d) being divided into a plurality of banks, each of the plurality of banks grouping a respective subset of the plurality of memory chips across the plurality of channel parallel operation elements (10a, 10b, 10c, 10d), whereby all of the memory chips belonging to the same bank share a ready/busy signal over the plurality of channel parallel operation elements (10a, 10b, 10c, 10d); and a controller(104, 113); characterized in that the controller (104, 113) obtains a plurality of free blocks from a plurality of logical blocks, each of the logical blocks being associated with the plurality of physical blocks selected from the channel parallel operation elements (10a, 10b, 10c, 10d) operated in parallel, a free block being a first logical block, which does not include valid data and to which use is not allocated yet, among the plurality of logical blocks, and the controller (104, 113) controls a parallel operation by the planes, banks, or channel parallel operation elements (10a, 10b, 10c, 10d), wherein the controller includes: a plurality of free-block management lists, each of the free-block management lists managing the logical blocks with a same bank number, a same memory chip number, and a same plane number as the plurality of free blocks; and a free-block selecting unit that selects a required number of free-block management lists from the plurality of free-block management lists to obtain the free blocks capable of performing a parallel operation from selected free-block management lists. a nonvolatile semiconductor memory having a plurality of channel parallel operation elements (10a, 10b, 10c, 10d), each of the channel parallel operation elements (10a, 10b, 10c, 10d) including a plurality of memory chips, each of the memory chips including a plurality of planes capable of operating in parallel, each plane including a plurality of physical blocks, each of the physical blocks being a unit of data erasing, the plurality of memory chips in the respective channel parallel operation elements (10a, 10b, 10c, 10d) being divided into a plurality of banks, each of the plurality of banks grouping a respective subset of the plurality of memory chips across the plurality of channel parallel operation elements (10a, 10b, 10c, 10d), whereby all of the memory chips belonging to the same bank share a ready/busy signal over the plurality of channel parallel operation elements (10a, 10b, 10c, 10d); and a controller(104, 113); characterized in that the controller (104, 113) obtains a plurality of free blocks from a plurality of logical blocks, each of the logical blocks being associated with the plurality of physical blocks selected from the channel parallel operation elements (10a, 10b, 10c, 10d) operated in parallel, a free block being a first logical block, which does not include valid data and to which use is not allocated yet, among the plurality of logical blocks, and the controller (104, 113) controls a parallel operation by the planes, banks, or channel parallel operation elements (10a, 10b, 10c, 10d), wherein the controller includes: a plurality of free-block management lists, each of the free-block management lists managing the logical blocks with a same bank number, a same memory chip number, and a same plane number as the plurality of free blocks; and a free-block selecting unit that selects a required number of free-block management lists from the plurality of free-block management lists to obtain the free blocks capable of performing a parallel operation from selected free-block management lists. a plurality of free-block management lists, each of the free-block management lists managing the logical blocks with a same bank number, a same memory chip number, and a same plane number as the plurality of free blocks; and a free-block selecting unit that selects a required number of free-block management lists from the plurality of free-block management lists to obtain the free blocks capable of performing a parallel operation from selected free-block management lists.