A graphics vertex processing device, characterized by comprising: a microcode storing unit that stores microcodes including an instruction sequence and a composite instruction sequence, the instruction sequence including one or more micro instructions, the composite instruction sequence containing successive instruction sequences configured to be executed in a parallel manner and combined together after the micro instructions included in the successive instruction sequences are re-ordered; a buffer that stores vertex data subjected to an arithmetic processing and an instruction sequence index for identifying the instruction sequence for the arithmetic processing for the vertex data; an address table containing an instruction sequence index for identifying the instruction sequence included in each microcode, and header addresses for identifying the microcodes stored in the microcode storing unit; instruction determining means for referring to the address table based on one instruction sequence index and two or more successive instruction sequence indices stored in the buffer, to determine whether the two or more instruction sequence indices correspond to a composite instruction sequence stored in the microcode storing unit, and to select a header address for a stored microcode corresponding to the one instruction sequence index, or the two or more instruction sequence indices; decoding means for acquiring from the microcode storing unit the one or more micro instructions of the microcode indicated by the header address selected by the instruction determining means, and decoding the acquired micro instruction; and arithmetic processing means for executing the arithmetic processing on the vertex data by executing the micro instruction decoded by the decoding means. a microcode storing unit that stores microcodes including an instruction sequence and a composite instruction sequence, the instruction sequence including one or more micro instructions, the composite instruction sequence containing successive instruction sequences configured to be executed in a parallel manner and combined together after the micro instructions included in the successive instruction sequences are re-ordered; a buffer that stores vertex data subjected to an arithmetic processing and an instruction sequence index for identifying the instruction sequence for the arithmetic processing for the vertex data; an address table containing an instruction sequence index for identifying the instruction sequence included in each microcode, and header addresses for identifying the microcodes stored in the microcode storing unit; instruction determining means for referring to the address table based on one instruction sequence index and two or more successive instruction sequence indices stored in the buffer, to determine whether the two or more instruction sequence indices correspond to a composite instruction sequence stored in the microcode storing unit, and to select a header address for a stored microcode corresponding to the one instruction sequence index, or the two or more instruction sequence indices; decoding means for acquiring from the microcode storing unit the one or more micro instructions of the microcode indicated by the header address selected by the instruction determining means, and decoding the acquired micro instruction; and arithmetic processing means for executing the arithmetic processing on the vertex data by executing the micro instruction decoded by the decoding means.