Method for time-to-digital conversion for determining the point in time when a signal arrives at a measuring device (10, 20); - wherein the signal arriving at the measuring device (10, 20) is fed into a delay circuit (100, 200) consisting of a plurality of delay elements (101, 201) connected in series, comprising an input (102; 202, 203) and an output (103; 204, 205), wherein the output (103; 204) of one of the delay elements (101, 201) is respectively connected to the input (102, 203) of the subsequent delay element is such a way that, after an inherent delay time, a signal applied to the input (102; 202, 203) of one of the delay elements (101, 201) is transmitted via its output (103; 204) to the input (102, 203) of the subsequent delay element (101, 201), - wherein the input signal at the input (102; 202, 203) of one of the delay elements (101, 201) causes a level change between a first discrete signal value and a second discrete signal value, and wherein this level change is respectively transmitted via the output (103; 204) of the delay element (101, 201) to the input (102; 203) of the subsequent delay element (101, 201), and - wherein the output (103; 205) of each delay element (101, 201) is also connected to an input of a register (105, 206) and the discrete signal value present at the input of the register (105, 206) is stored in a system clock specified by a clock signal occurring in a given clock period and is output via an output of the register (105, 206). - wherein the incoming signal is fed into the delay circuit (100, 200) by means of a pulse generator (130', 230) as a sequence of level changes, characterized in that the output of each level change at the end of the delay elements connected in series (101, 201) is counted in an output counter. - wherein the signal arriving at the measuring device (10, 20) is fed into a delay circuit (100, 200) consisting of a plurality of delay elements (101, 201) connected in series, comprising an input (102; 202, 203) and an output (103; 204, 205), wherein the output (103; 204) of one of the delay elements (101, 201) is respectively connected to the input (102, 203) of the subsequent delay element is such a way that, after an inherent delay time, a signal applied to the input (102; 202, 203) of one of the delay elements (101, 201) is transmitted via its output (103; 204) to the input (102, 203) of the subsequent delay element (101, 201), - wherein the input signal at the input (102; 202, 203) of one of the delay elements (101, 201) causes a level change between a first discrete signal value and a second discrete signal value, and wherein this level change is respectively transmitted via the output (103; 204) of the delay element (101, 201) to the input (102; 203) of the subsequent delay element (101, 201), and - wherein the output (103; 205) of each delay element (101, 201) is also connected to an input of a register (105, 206) and the discrete signal value present at the input of the register (105, 206) is stored in a system clock specified by a clock signal occurring in a given clock period and is output via an output of the register (105, 206). - wherein the incoming signal is fed into the delay circuit (100, 200) by means of a pulse generator (130', 230) as a sequence of level changes,