A voltage regulator having current foldback based upon load impedance, comprising: a power transistor having a gate, a source and a drain, wherein the power transistor is coupled between a power source (V BAT) and a load (120; 122); a voltage divider (114, 116) coupled in parallel with the load (120; 122) and providing a feedback voltage (V fb) that represents an output voltage (V OUT) from the power transistor to the load (120; 122); an error amplifier having a first input coupled to a reference voltage (V ref), a second input coupled to the feedback voltage (V fb), and an output coupled to the gate of and controlling the power transistor, wherein the error amplifier causes the power transistor to maintain the feedback voltage (V fb) at substantially the same voltage as the reference voltage (V ref); a current sensing circuit for measuring current to the load (120; 122) by providing a sense current (I sense) that represents a fraction of the load current through the power transistor; characterized by a current limit and foldback circuit having a first input coupled to the feedback voltage (V fb), a second input coupled to the reference voltage (V ref), a third input coupled to the sense current (I sense) from the current sensing circuit, and an output providing a foldback bias current (I bias_current_foldback), wherein the foldback bias current (I bias_current_foldback) generates an offset voltage (V offset) at or in the differential input stage of the error amplifier; wherein the current limit and foldback circuit is configured to operate in a current limit mode when the load current is less than or equal to a current limit value, and in a foldback mode when an output load impedance is less than a foldback load impedance value; wherein the current limit and foldback circuit is configured to set the foldback bias current to substantially zero volts when the load current is less than a current limit value and an output load impedance is greater than a foldback load impedance value, and wherein the current limit and foldback circuit is configured to increase the foldback bias current when the output load impedance is less than or equal to the foldback load impedance value, thereby reducing the output voltage (V OUT) and the output current proportionally until the output voltage (V OUT) is at substantially zero volts and the output current is at a foldback current value. a power transistor having a gate, a source and a drain, wherein the power transistor is coupled between a power source (V BAT) and a load (120; 122); a voltage divider (114, 116) coupled in parallel with the load (120; 122) and providing a feedback voltage (V fb) that represents an output voltage (V OUT) from the power transistor to the load (120; 122); an error amplifier having a first input coupled to a reference voltage (V ref), a second input coupled to the feedback voltage (V fb), and an output coupled to the gate of and controlling the power transistor, wherein the error amplifier causes the power transistor to maintain the feedback voltage (V fb) at substantially the same voltage as the reference voltage (V ref); a current sensing circuit for measuring current to the load (120; 122) by providing a sense current (I sense) that represents a fraction of the load current through the power transistor; characterized by a current limit and foldback circuit having a first input coupled to the feedback voltage (V fb), a second input coupled to the reference voltage (V ref), a third input coupled to the sense current (I sense) from the current sensing circuit, and an output providing a foldback bias current (I bias_current_foldback), wherein the foldback bias current (I bias_current_foldback) generates an offset voltage (V offset) at or in the differential input stage of the error amplifier; wherein the current limit and foldback circuit is configured to operate in a current limit mode when the load current is less than or equal to a current limit value, and in a foldback mode when an output load impedance is less than a foldback load impedance value; wherein the current limit and foldback circuit is configured to set the foldback bias current to substantially zero volts when the load current is less than a current limit value and an output load impedance is greater than a foldback load impedance value, and wherein the current limit and foldback circuit is configured to increase the foldback bias current when the output load impedance is less than or equal to the foldback load impedance value, thereby reducing the output voltage (V OUT) and the output current proportionally until the output voltage (V OUT) is at substantially zero volts and the output current is at a foldback current value.