An oscillator, comprising: charging/discharging circuitry that controls voltage at a comparator input node, and comprising first and second capacitors (C1, C2) and a resistor connected to the comparator input node (Vcap), wherein the second capacitor is connected between the comparator input node (Vcap) and a relatively low supply voltage, and switches (SW1, SW2, SW3, SW4) configured to selectively connect the first capacitor and the resistor to either a relatively high supply voltage (Vref) or the low supply voltage; a comparator that generates a comparator output signal indicative of whether the voltage at the comparator input node is greater than or less than a comparator reference voltage; and logic circuitry (204, 206) that generates an oscillator output signal and controls the charging/discharging circuitry based on the comparator output signal, wherein: the logic circuit is arranged to reconfigure the switches at the end of a discharging cycle of the oscillator, so that (i) the resistor is connected to the high supply voltage and (ii) the first capacitor is connected to the low supply voltage, such that during a charging cycle of the oscillator, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively low initial charging voltage level up to the comparator reference voltage; and the logic circuit is further arranged to reconfigure the switches at the end of a charging cycle, such that (i) the resistor is connected to the low supply voltage and (ii) the first capacitor is connected to the high supply voltage during a discharging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively high initial discharging voltage level down to the comparator reference voltage; wherein the initial charging and discharging voltage levels are dependent upon the comparator reference voltage such that a comparator offset voltage directly affects the initial charging and discharging voltage levels. charging/discharging circuitry that controls voltage at a comparator input node, and comprising first and second capacitors (C1, C2) and a resistor connected to the comparator input node (Vcap), wherein the second capacitor is connected between the comparator input node (Vcap) and a relatively low supply voltage, and switches (SW1, SW2, SW3, SW4) configured to selectively connect the first capacitor and the resistor to either a relatively high supply voltage (Vref) or the low supply voltage; first and second capacitors (C1, C2) and a resistor connected to the comparator input node (Vcap), wherein the second capacitor is connected between the comparator input node (Vcap) and a relatively low supply voltage, and switches (SW1, SW2, SW3, SW4) configured to selectively connect the first capacitor and the resistor to either a relatively high supply voltage (Vref) or the low supply voltage; a comparator that generates a comparator output signal indicative of whether the voltage at the comparator input node is greater than or less than a comparator reference voltage; and logic circuitry (204, 206) that generates an oscillator output signal and controls the charging/discharging circuitry based on the comparator output signal, wherein: the logic circuit is arranged to reconfigure the switches at the end of a discharging cycle of the oscillator, so that (i) the resistor is connected to the high supply voltage and (ii) the first capacitor is connected to the low supply voltage, such that during a charging cycle of the oscillator, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively low initial charging voltage level up to the comparator reference voltage; and the logic circuit is further arranged to reconfigure the switches at the end of a charging cycle, such that (i) the resistor is connected to the low supply voltage and (ii) the first capacitor is connected to the high supply voltage during a discharging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively high initial discharging voltage level down to the comparator reference voltage; wherein the initial charging and discharging voltage levels are dependent upon the comparator reference voltage such that a comparator offset voltage directly affects the initial charging and discharging voltage levels. the logic circuit is arranged to reconfigure the switches at the end of a discharging cycle of the oscillator, so that (i) the resistor is connected to the high supply voltage and (ii) the first capacitor is connected to the low supply voltage, such that during a charging cycle of the oscillator, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively low initial charging voltage level up to the comparator reference voltage; and the logic circuit is further arranged to reconfigure the switches at the end of a charging cycle, such that (i) the resistor is connected to the low supply voltage and (ii) the first capacitor is connected to the high supply voltage during a discharging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively high initial discharging voltage level down to the comparator reference voltage; wherein the initial charging and discharging voltage levels are dependent upon the comparator reference voltage such that a comparator offset voltage directly affects the initial charging and discharging voltage levels.