A memory circuit comprising K*P*M*N elementary cells distributed in K*P local arrays (A1, A2; A; A11, A12, A21, A22) each comprising M rows and N columns, the K*P arrays being arranged in a global array of K rows and P columns, with: - K, P, M and N integers greater than or equal to 2, - 1 integer in the range from 0 to K-1 and q integer in the range from 0 to P-1 designating respectively the rank of the row and the rank of the column of each local array in the global array, - i integer in the range from 0 to M-1 and j integer in the range from 0 to N-1 designating respectively the rank of the row and the rank of the column of each elementary cell in the local array to which it belongs, wherein: each column of each local array comprises a vertical local bit line (LRBL<j>; LRBLT<j>; VLRBL<j>) directly connected to each of the cells in the column; each column of each local array comprises a vertical global bit line (VGRBL<j>) coupled to the vertical local bit line (LRBL<j>; LRBLT<j>; VLRBL<j>) of the column by a local coupling circuit, the local coupling circuit being controllable to: - isolate the vertical local bit line from the vertical global bit line, - transmit over the vertical global bit line a binary signal present on the vertical local bit line, or - transmit over the vertical local bit line a binary signal present on the vertical global bit line; in each column of rank q in the global array, for each column rank j of the local arrays, the K vertical global bit lines (VGRBL<j>) having the same rank j are coupled together; characterized in that the memory circuit further comprises, for each column of each local array, an horizontal global bit line (HGRBL<j>) connected to the vertical global bit line of the column; and in each row of rank 1 in the global array, for each column rank j of the local arrays, the P horizontal global bit lines (HGRBL<j>) having the same rank j are coupled together. - K, P, M and N integers greater than or equal to 2, - 1 integer in the range from 0 to K-1 and q integer in the range from 0 to P-1 designating respectively the rank of the row and the rank of the column of each local array in the global array, - i integer in the range from 0 to M-1 and j integer in the range from 0 to N-1 designating respectively the rank of the row and the rank of the column of each elementary cell in the local array to which it belongs, wherein: each column of each local array comprises a vertical local bit line (LRBL<j>; LRBLT<j>; VLRBL<j>) directly connected to each of the cells in the column; each column of each local array comprises a vertical global bit line (VGRBL<j>) coupled to the vertical local bit line (LRBL<j>; LRBLT<j>; VLRBL<j>) of the column by a local coupling circuit, the local coupling circuit being controllable to: - isolate the vertical local bit line from the vertical global bit line, - transmit over the vertical global bit line a binary signal present on the vertical local bit line, or - transmit over the vertical local bit line a binary signal present on the vertical global bit line; in each column of rank q in the global array, for each column rank j of the local arrays, the K vertical global bit lines (VGRBL<j>) having the same rank j are coupled together; characterized in that the memory circuit further comprises, for each column of each local array, an horizontal global bit line (HGRBL<j>) connected to the vertical global bit line of the column; and in each row of rank 1 in the global array, for each column rank j of the local arrays, the P horizontal global bit lines (HGRBL<j>) having the same rank j are coupled together. each column of each local array comprises a vertical local bit line (LRBL<j>; LRBLT<j>; VLRBL<j>) directly connected to each of the cells in the column; each column of each local array comprises a vertical global bit line (VGRBL<j>) coupled to the vertical local bit line (LRBL<j>; LRBLT<j>; VLRBL<j>) of the column by a local coupling circuit, the local coupling circuit being controllable to: - isolate the vertical local bit line from the vertical global bit line, - transmit over the vertical global bit line a binary signal present on the vertical local bit line, or - transmit over the vertical local bit line a binary signal present on the vertical global bit line; - isolate the vertical local bit line from the vertical global bit line, - transmit over the vertical global bit line a binary signal present on the vertical local bit line, or - transmit over the vertical local bit line a binary signal present on the vertical global bit line; in each column of rank q in the global array, for each column rank j of the local arrays, the K vertical global bit lines (VGRBL<j>) having the same rank j are coupled together; characterized in that the memory circuit further comprises, for each column of each local array, an horizontal global bit line (HGRBL<j>) connected to the vertical global bit line of the column; and in each row of rank 1 in the global array, for each column rank j of the local arrays, the P horizontal global bit lines (HGRBL<j>) having the same rank j are coupled together.