Search circuit for a piece of information within a data matrix, comprising: - the data matrix arranged in a plurality of data lines, each data line comprising a plurality of data storage nodes, each data storage node being configured so as to store a first state or a second state, the data storage nodes being mainly in the second state, - a first circuit performing a first test of the state of one data line, the first circuit being configured so as to determine whether the tested data line has no data storage node in the first state or whether the tested data line has at least one data storage node in the first state, the first circuit sending a first code when the data line has at least one data storage node in a first state or a second code when the data line has no data storage node in the first state, - a second circuit performing a second test of the state of the data storage nodes in one data line, the second circuit being configured so as to send a third code when the data storage node is in the first state or a fourth code when the data storage node is in the second state, the second circuit being configured so as to test one data line when the first circuit has sent a first code relative to said data line, - a receiver configured so as to contain a signal representative of the analysis of the data matrix, characterized in that: - the first circuit tests all the data lines of the data matrix with a predefined sequence, - the second circuit is configured to consecutively test all the data storage nodes of said data line and send a third code or a fourth code depending on the data storage node is in the first state or not when the first circuit has sent a first code relating to said data line, the second circuit being configured to test consecutively all the data storage nodes of said data line at least until a third code occurs, - the receiver receives the result from the first test circuit for each data line of the data matrix and receives the result from the second test circuit for all tested data storage nodes so that the receiver contains a signal comprising as many first and second codes (A, B) as tested data lines, the signal comprising a succession of first, second, third and fourth codes. - the data matrix arranged in a plurality of data lines, each data line comprising a plurality of data storage nodes, each data storage node being configured so as to store a first state or a second state, the data storage nodes being mainly in the second state, - a first circuit performing a first test of the state of one data line, the first circuit being configured so as to determine whether the tested data line has no data storage node in the first state or whether the tested data line has at least one data storage node in the first state, the first circuit sending a first code when the data line has at least one data storage node in a first state or a second code when the data line has no data storage node in the first state, - a second circuit performing a second test of the state of the data storage nodes in one data line, the second circuit being configured so as to send a third code when the data storage node is in the first state or a fourth code when the data storage node is in the second state, the second circuit being configured so as to test one data line when the first circuit has sent a first code relative to said data line, - a receiver configured so as to contain a signal representative of the analysis of the data matrix, - the first circuit tests all the data lines of the data matrix with a predefined sequence, - the second circuit is configured to consecutively test all the data storage nodes of said data line and send a third code or a fourth code depending on the data storage node is in the first state or not when the first circuit has sent a first code relating to said data line, the second circuit being configured to test consecutively all the data storage nodes of said data line at least until a third code occurs, - the receiver receives the result from the first test circuit for each data line of the data matrix and receives the result from the second test circuit for all tested data storage nodes so that the receiver contains a signal comprising as many first and second codes (A, B) as tested data lines, the signal comprising a succession of first, second, third and fourth codes.