An integrated circuit comprising: a dual port modulator having a first input for receiving a transmitter modulation signal (TX MODULATION), a first output for providing a fractional portion of a high port modulation signal (HIGH PORT FRACTION), a second output for providing an integer portion of the high port modulation signal (HIGH PORT INTEGER), and a third output for providing a low port signal (LOW PORT) the fractional portion of the high port modulation signal generated using a signed single bit signal having three states; a sigma delta modulator configured to generate a low port modulation signal, the sigma delta modulator having an input for receiving a signal comprising the sum of a target frequency signal value with the low port signal value, and an output for providing the low port modulation signal; a voltage controlled oscillator coupled to the dual port modulator and a loop filter, the voltage controlled oscillator having a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal (VTUNE) from the loop filter based on the low port modulation signal, and a first output for outputting an RF signal (RF OUTPUT); a fractional divider having an input coupled to the first output of the voltage controlled oscillator, and an output coupled to the second input of a phase detector, the phase detector having a first input for receiving a reference clock signal a second input for receiving a feedback signal from fractional divider, and an output coupled to an input of the loop filter. a dual port modulator having a first input for receiving a transmitter modulation signal (TX MODULATION), a first output for providing a fractional portion of a high port modulation signal (HIGH PORT FRACTION), a second output for providing an integer portion of the high port modulation signal (HIGH PORT INTEGER), and a third output for providing a low port signal (LOW PORT) the fractional portion of the high port modulation signal generated using a signed single bit signal having three states; a sigma delta modulator configured to generate a low port modulation signal, the sigma delta modulator having an input for receiving a signal comprising the sum of a target frequency signal value with the low port signal value, and an output for providing the low port modulation signal; a voltage controlled oscillator coupled to the dual port modulator and a loop filter, the voltage controlled oscillator having a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal (VTUNE) from the loop filter based on the low port modulation signal, and a first output for outputting an RF signal (RF OUTPUT); a fractional divider having an input coupled to the first output of the voltage controlled oscillator, and an output coupled to the second input of a phase detector, the phase detector having a first input for receiving a reference clock signal a second input for receiving a feedback signal from fractional divider, and an output coupled to an input of the loop filter.