A memory including a structure in lines and columns over several superimposed memory levels, each memory level comprising at least one array of memory elements and gate-all-around access transistors, each access transistor including a semiconductor nanowire at least one portion of which is embedded by a gate (124, 126), each gate (124, 126) being electrically insulated from the gates (124, 126) of the access transistors of the other memory levels, the memory comprising: - first electrically-conductive portions, each crossing at least two memory levels and being electrically coupled to first ends of the semiconductor nanowires of access transistors belonging to at least one column and one line of each of said at least two memory levels; - memory stacks, each crossing said at least two memory levels and forming memory elements belonging to at least one column and one line of each of said at least two memory levels, each memory stack comprising at least one memory material layer disposed between at least one second electrically-conductive portion forming a first electrode of said memory elements and at least one electrically-conductive layer forming a second electrode of said memory elements, the electrically-conductive layer being disposed against second ends of the semiconductor nanowires of said access transistors; - first electrically-conductive lines, each being electrically connected to the first electrically-conductive portions of the same column of the memory; - second electrically-conductive lines, each being electrically connected to the second electrically-conductive portions of the same column of the memory; - word lines each extending in the same memory level corresponding to one of said at least two memory levels while electrically coupling together the gates (124, 126) of the access transistors of the same line of the memory and located in said memory level. - first electrically-conductive portions, each crossing at least two memory levels and being electrically coupled to first ends of the semiconductor nanowires of access transistors belonging to at least one column and one line of each of said at least two memory levels; - memory stacks, each crossing said at least two memory levels and forming memory elements belonging to at least one column and one line of each of said at least two memory levels, each memory stack comprising at least one memory material layer disposed between at least one second electrically-conductive portion forming a first electrode of said memory elements and at least one electrically-conductive layer forming a second electrode of said memory elements, the electrically-conductive layer being disposed against second ends of the semiconductor nanowires of said access transistors; - first electrically-conductive lines, each being electrically connected to the first electrically-conductive portions of the same column of the memory; - second electrically-conductive lines, each being electrically connected to the second electrically-conductive portions of the same column of the memory; - word lines each extending in the same memory level corresponding to one of said at least two memory levels while electrically coupling together the gates (124, 126) of the access transistors of the same line of the memory and located in said memory level.