A semiconductor memory device (100; 1000; 1001; 3100; 4300; 4400), comprising: an interface semiconductor die (200; 1010) including a plurality of command pins configured to receive a plurality of command signals, which are transferred from a memory controller, and including an interface command decoder configured to decode the plurality of command signals; a memory semiconductor die (300; 1070, 1080; 1100, 1200, 1300, 1400) stacked with the interface semiconductor die, the memory semiconductor die including a memory integrated circuit (1071, 1081; 1401-1404) configured to store data, and including a memory command decoder configured to decode the plurality of command signals, which are transferred from the interface semiconductor die; and a plurality of through-silicon vias electrically connecting the interface semiconductor die and the memory semiconductor die, wherein: the interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller, the interface command decoder is configured to generate an interface clock enable signal to control a first clock supply with respect to the interface semiconductor die based on a power mode command, which is transferred through the plurality of command pins from the memory controller, and the memory command decoder is configured to generate a memory clock enable signal to control a second clock supply with respect to the memory semiconductor die based on the power mode command, which is transferred through the plurality of through-silicon vias from the interface semiconductor die. an interface semiconductor die (200; 1010) including a plurality of command pins configured to receive a plurality of command signals, which are transferred from a memory controller, and including an interface command decoder configured to decode the plurality of command signals; a memory semiconductor die (300; 1070, 1080; 1100, 1200, 1300, 1400) stacked with the interface semiconductor die, the memory semiconductor die including a memory integrated circuit (1071, 1081; 1401-1404) configured to store data, and including a memory command decoder configured to decode the plurality of command signals, which are transferred from the interface semiconductor die; and a plurality of through-silicon vias electrically connecting the interface semiconductor die and the memory semiconductor die, wherein: the interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller, the interface command decoder is configured to generate an interface clock enable signal to control a first clock supply with respect to the interface semiconductor die based on a power mode command, which is transferred through the plurality of command pins from the memory controller, and the memory command decoder is configured to generate a memory clock enable signal to control a second clock supply with respect to the memory semiconductor die based on the power mode command, which is transferred through the plurality of through-silicon vias from the interface semiconductor die. the interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller, the interface command decoder is configured to generate an interface clock enable signal to control a first clock supply with respect to the interface semiconductor die based on a power mode command, which is transferred through the plurality of command pins from the memory controller, and the memory command decoder is configured to generate a memory clock enable signal to control a second clock supply with respect to the memory semiconductor die based on the power mode command, which is transferred through the plurality of through-silicon vias from the interface semiconductor die.