An integrated circuit, comprising: a first interface for receiving higher-speed-type data; a second interface for receiving lower-speed-type data; a first logic circuit coupled to the first interface, comprising a first logic subcircuit and a second logic subcircuit; a second logic circuit coupled to the second interface, comprising a third logic subcircuit and a fourth logic subcircuit; and a driving circuit comprising: a data output; one or more first driving subcircuits each comprising two first-type transistors (312a, 312b) coupled in series between a supply voltage and the data output; and one or more second driving subcircuits each comprising two second-type transistors (314a, 314b) coupled in series between the data output and an electrical ground; wherein each of the first logic subcircuit and the third logic subcircuit is coupled to a respective first-type transistor (312a, 312b) of the two first-type transistors in each of the one or more first driving subcircuits, wherein each of the second logic subcircuit and the fourth logic subcircuit is coupled to a respective second-type transistor (314a, 314b) of the two second-type transistors in each of the one or more second driving subcircuits, wherein the driving circuit is configured to output i) data corresponding to the higher-speed-type data if the first interface receives the higher-speed-type data, and ii) data corresponding to the lower-speed-type data if the second interface receives the lower-speed-type data, and wherein the first interface, the first logic circuit, and the driving circuit are arranged to form a first data path for transferring the higher-speed-type data with a first speed, and wherein the second interface, the second logic circuit, and the driving circuit are arranged to form a second data path for transferring the lower-speed-type data with a second speed, the first speed being higher the second speed. a first interface for receiving higher-speed-type data; a second interface for receiving lower-speed-type data; a first logic circuit coupled to the first interface, comprising a first logic subcircuit and a second logic subcircuit; a second logic circuit coupled to the second interface, comprising a third logic subcircuit and a fourth logic subcircuit; and a driving circuit comprising: a data output; one or more first driving subcircuits each comprising two first-type transistors (312a, 312b) coupled in series between a supply voltage and the data output; and one or more second driving subcircuits each comprising two second-type transistors (314a, 314b) coupled in series between the data output and an electrical ground; wherein each of the first logic subcircuit and the third logic subcircuit is coupled to a respective first-type transistor (312a, 312b) of the two first-type transistors in each of the one or more first driving subcircuits, wherein each of the second logic subcircuit and the fourth logic subcircuit is coupled to a respective second-type transistor (314a, 314b) of the two second-type transistors in each of the one or more second driving subcircuits, wherein the driving circuit is configured to output i) data corresponding to the higher-speed-type data if the first interface receives the higher-speed-type data, and ii) data corresponding to the lower-speed-type data if the second interface receives the lower-speed-type data, and wherein the first interface, the first logic circuit, and the driving circuit are arranged to form a first data path for transferring the higher-speed-type data with a first speed, and wherein the second interface, the second logic circuit, and the driving circuit are arranged to form a second data path for transferring the lower-speed-type data with a second speed, the first speed being higher the second speed. a data output; one or more first driving subcircuits each comprising two first-type transistors (312a, 312b) coupled in series between a supply voltage and the data output; and one or more second driving subcircuits each comprising two second-type transistors (314a, 314b) coupled in series between the data output and an electrical ground; wherein each of the first logic subcircuit and the third logic subcircuit is coupled to a respective first-type transistor (312a, 312b) of the two first-type transistors in each of the one or more first driving subcircuits, wherein each of the second logic subcircuit and the fourth logic subcircuit is coupled to a respective second-type transistor (314a, 314b) of the two second-type transistors in each of the one or more second driving subcircuits, wherein the driving circuit is configured to output i) data corresponding to the higher-speed-type data if the first interface receives the higher-speed-type data, and ii) data corresponding to the lower-speed-type data if the second interface receives the lower-speed-type data, and wherein the first interface, the first logic circuit, and the driving circuit are arranged to form a first data path for transferring the higher-speed-type data with a first speed, and wherein the second interface, the second logic circuit, and the driving circuit are arranged to form a second data path for transferring the lower-speed-type data with a second speed, the first speed being higher the second speed.