An image decoding circuit comprising: an intra prediction unit for, when a coding mode for a coding block is an intra coding mode, carrying out an intra-frame prediction process on each of processing blocks to generate a prediction value for each of pixels of a prediction image, each of said processing blocks being said coding block or a sub-block obtained by dividing said coding block, a motion-compensated prediction unit for, when a coding mode for a coding block is an inter coding mode, carrying out a motion-compensated prediction process on each of processing blocks to generate an inter prediction image, wherein, when an intra prediction parameter indicates a vertical prediction process, the intra prediction unit adds, at each column within a predetermined number of a column or columns from a left end of the processing block, a value to a luminance value of a pixel adjacent to top of each of said processing blocks and sets a result of the addition as a predicted value of the prediction image, the value being proportional to an amount of change in a vertical direction of luminance values of pixels adjacent to left of each of said processing blocks, the value being obtained by scaling the amount of change; and the intra prediction unit sets, at remaining columns of the processing block, a luminance value of a pixel adjacent to top of the processing block as a predicted value of the prediction image, wherein the intra prediction unit calculates a predicted value of each pixel in the processing block according to, S ′ x y = S x, − 1 + S − 1, y − S − 1, − 1 / t x < B S x, − 1 x ≥ B wherein S'(x,y) is the predicted value at the coordinates (x,y), S(x,y) is the luminance value of the already-encoded pixel at the coordinates (x,y), 1/t is a scaling value used for vertical prediction and B is an integer larger than 0, wherein said decoding circuit obtain reference image from a frame memory storing reference image used to generate said inter prediction image. an intra prediction unit for, when a coding mode for a coding block is an intra coding mode, carrying out an intra-frame prediction process on each of processing blocks to generate a prediction value for each of pixels of a prediction image, each of said processing blocks being said coding block or a sub-block obtained by dividing said coding block, a motion-compensated prediction unit for, when a coding mode for a coding block is an inter coding mode, carrying out a motion-compensated prediction process on each of processing blocks to generate an inter prediction image, wherein, when an intra prediction parameter indicates a vertical prediction process, the intra prediction unit adds, at each column within a predetermined number of a column or columns from a left end of the processing block, a value to a luminance value of a pixel adjacent to top of each of said processing blocks and sets a result of the addition as a predicted value of the prediction image, the value being proportional to an amount of change in a vertical direction of luminance values of pixels adjacent to left of each of said processing blocks, the value being obtained by scaling the amount of change; and the intra prediction unit sets, at remaining columns of the processing block, a luminance value of a pixel adjacent to top of the processing block as a predicted value of the prediction image, wherein the intra prediction unit calculates a predicted value of each pixel in the processing block according to, S ′ x y = S x, − 1 + S − 1, y − S − 1, − 1 / t x < B S x, − 1 x ≥ B wherein S'(x,y) is the predicted value at the coordinates (x,y), S(x,y) is the luminance value of the already-encoded pixel at the coordinates (x,y), 1/t is a scaling value used for vertical prediction and B is an integer larger than 0, wherein said decoding circuit obtain reference image from a frame memory storing reference image used to generate said inter prediction image.