A liquid crystal display device comprising: a plurality of parallel gate lines formed on a transparent insulating substrate, said gate lines having a first reflectivity; a plurality of parallel data lines formed on said transparent insulating substrate such that the plurality of said parallel data lines and the plurality of said parallel gate lines cross each other with the plurality of said parallel data lines being electrically insulated from the plurality of said parallel gate lines; a plurality of transistors provided on said transparent insulating substrate in positions corresponding to pixel regions partitioned in matrix by said gate lines and said data lines, respectively; an upper light shielding layer configured to shield said data lines, said gate lines, and said transistors from light incident normal to the device; a lower light shielding layer having a second reflectivity, said lower light shielding layer disposed on said substrate below said transistors; wherein each of the plurality of said transistors includes a data line side Lightly Doped Drain, LDD, region and a pixel electrode side LDD region, and each of the plurality of said transistors is positioned along a gate line to which the transistor is connected, and closer to a data line to which the transistor is connected than a data line of an adjacent pixel; and wherein the device is configured such that said data line side LDD region of a transistor is located a distance from the data line to which the transistor is connected so that the intensity of light incident on data line side LDD region is at most 1/1000 of the value of light incident at angles other than normal to the device, through repetitive reflections along a path between said lower light shielding layer and said gate line to which the transistor is connected, toward the data line side LDD region. a plurality of parallel gate lines formed on a transparent insulating substrate, said gate lines having a first reflectivity; a plurality of parallel data lines formed on said transparent insulating substrate such that the plurality of said parallel data lines and the plurality of said parallel gate lines cross each other with the plurality of said parallel data lines being electrically insulated from the plurality of said parallel gate lines; a plurality of transistors provided on said transparent insulating substrate in positions corresponding to pixel regions partitioned in matrix by said gate lines and said data lines, respectively; an upper light shielding layer configured to shield said data lines, said gate lines, and said transistors from light incident normal to the device; a lower light shielding layer having a second reflectivity, said lower light shielding layer disposed on said substrate below said transistors; wherein each of the plurality of said transistors includes a data line side Lightly Doped Drain, LDD, region and a pixel electrode side LDD region, and each of the plurality of said transistors is positioned along a gate line to which the transistor is connected, and closer to a data line to which the transistor is connected than a data line of an adjacent pixel; and wherein the device is configured such that said data line side LDD region of a transistor is located a distance from the data line to which the transistor is connected so that the intensity of light incident on data line side LDD region is at most 1/1000 of the value of light incident at angles other than normal to the device, through repetitive reflections along a path between said lower light shielding layer and said gate line to which the transistor is connected, toward the data line side LDD region.