A processor implemented method of user performance evaluation, comprising: tracking, via one or more hardware processors, a plurality of user actions when a user is engaged in an activity, wherein the plurality of user actions comprise navigation within an application in which the activity is being performed, and execution of one or more functions of the application; determining, via the one or more hardware processors, a state change representing a sequence of traversal of the plurality of user actions, wherein the state change is identified when the plurality of user actions is executed by the user; determining, via the one or more hardware processors, extent of deviation of the determined state change in comparison with a reference state change of the application, comprising: comparing the sequence of traversal of the plurality of user actions corresponding to the determined state change with a reference sequence of traversal of user actions corresponding to the reference state change; generating a user efficiency matrix, wherein the user efficiency matrix represents a percentage similarity of the sequence of traversal of the plurality of user actions corresponding to the determined state change with the reference sequence of traversal of the user actions corresponding to the reference state change; and generating a user inefficiency matrix, wherein the user inefficiency matrix represents a) a percentage dissimilarity of the sequence of traversal of the plurality of user actions corresponding to the determined state change with the reference sequence of traversal of the user actions corresponding to the reference state change, and b) instances of the user activity resulting in a failure condition; calculating, via the one or more hardware processors, a user performance score as a function of the user efficiency matrix and the user inefficiency matrix; and determining, via the one or more hardware processors, a performance level of the user, based on the calculated user performance score. tracking, via one or more hardware processors, a plurality of user actions when a user is engaged in an activity, wherein the plurality of user actions comprise navigation within an application in which the activity is being performed, and execution of one or more functions of the application; determining, via the one or more hardware processors, a state change representing a sequence of traversal of the plurality of user actions, wherein the state change is identified when the plurality of user actions is executed by the user; determining, via the one or more hardware processors, extent of deviation of the determined state change in comparison with a reference state change of the application, comprising: comparing the sequence of traversal of the plurality of user actions corresponding to the determined state change with a reference sequence of traversal of user actions corresponding to the reference state change; generating a user efficiency matrix, wherein the user efficiency matrix represents a percentage similarity of the sequence of traversal of the plurality of user actions corresponding to the determined state change with the reference sequence of traversal of the user actions corresponding to the reference state change; and generating a user inefficiency matrix, wherein the user inefficiency matrix represents a) a percentage dissimilarity of the sequence of traversal of the plurality of user actions corresponding to the determined state change with the reference sequence of traversal of the user actions corresponding to the reference state change, and b) instances of the user activity resulting in a failure condition; comparing the sequence of traversal of the plurality of user actions corresponding to the determined state change with a reference sequence of traversal of user actions corresponding to the reference state change; generating a user efficiency matrix, wherein the user efficiency matrix represents a percentage similarity of the sequence of traversal of the plurality of user actions corresponding to the determined state change with the reference sequence of traversal of the user actions corresponding to the reference state change; and generating a user inefficiency matrix, wherein the user inefficiency matrix represents a) a percentage dissimilarity of the sequence of traversal of the plurality of user actions corresponding to the determined state change with the reference sequence of traversal of the user actions corresponding to the reference state change, and b) instances of the user activity resulting in a failure condition; calculating, via the one or more hardware processors, a user performance score as a function of the user efficiency matrix and the user inefficiency matrix; and determining, via the one or more hardware processors, a performance level of the user, based on the calculated user performance score.