A cache memory apparatus comprising: a data holding unit (21, 22) comprising a plurality of ways (21, 22) that have a plurality of cache lines and operable to hold data in the cache lines; an alternation data register operable to hold data of one line of the cache lines or of a part of the cache lines held by the data holding unit (21, 22); an alternation address register operable to hold an index address that is used for cache access and indicates a faulty cache line in which a fault has occurred in the data holding unit (21, 22) and a part in which the fault has occurred in the faulty cache line; an alternation way register operable to hold information of a way (21, 22) in the data holding unit (21, 22) including a faulty bit in the data holding unit (21, 22); an address match circuit operable to compare, when an access is performed to the data holding unit (21, 22), an index address used for the access and the index address held by the alternation address register; a way match circuit operable to compare, when an access is performed to the data holding unit (21, 22), way information used for the access and way information held by the alternation way register, and further comprising means (37, 38) such that when a reading-out reference access is made to the data holding unit (21, 22) and the comparison by the address match circuit results in a match, data read out from a way corresponding to the way information held by the alternation way register are replaced with contents of the alternation data register, to be read-out data from the data holding unit (21, 22); and such that when a writing-in reference access is made to the data holding unit (21, 22) and the comparisons by the address match circuit and the way match circuit both result in a match, data are written into a writing-in target way in the data holding unit (21, 22) while the data are also written into the alternation data register, matching contents of the alternation data register with a latest state of the data holding unit (21, 22). a data holding unit (21, 22) comprising a plurality of ways (21, 22) that have a plurality of cache lines and operable to hold data in the cache lines; an alternation data register operable to hold data of one line of the cache lines or of a part of the cache lines held by the data holding unit (21, 22); an alternation address register operable to hold an index address that is used for cache access and indicates a faulty cache line in which a fault has occurred in the data holding unit (21, 22) and a part in which the fault has occurred in the faulty cache line; an alternation way register operable to hold information of a way (21, 22) in the data holding unit (21, 22) including a faulty bit in the data holding unit (21, 22); an address match circuit operable to compare, when an access is performed to the data holding unit (21, 22), an index address used for the access and the index address held by the alternation address register; a way match circuit operable to compare, when an access is performed to the data holding unit (21, 22), way information used for the access and way information held by the alternation way register, and further comprising means (37, 38) such that when a reading-out reference access is made to the data holding unit (21, 22) and the comparison by the address match circuit results in a match, data read out from a way corresponding to the way information held by the alternation way register are replaced with contents of the alternation data register, to be read-out data from the data holding unit (21, 22); and such that when a writing-in reference access is made to the data holding unit (21, 22) and the comparisons by the address match circuit and the way match circuit both result in a match, data are written into a writing-in target way in the data holding unit (21, 22) while the data are also written into the alternation data register, matching contents of the alternation data register with a latest state of the data holding unit (21, 22).