A crystal oscillator (50, 80), comprising: a crystal oscillator core circuit, configured to generate a sinusoidal wave; a first bias circuit, coupled to an output terminal of the crystal oscillator core circuit, configured to provide a first voltage level to be a bias voltage of the sinusoidal wave; and a phase noise reduction circuit (190, 190M), coupled to the output terminal of the crystal oscillator core circuit, configured to reset noise of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range, the phase noise reduction circuit (190, 190M) comprising: a second bias circuit, configured to control a second voltage level; a third bias circuit, configured to control a third voltage level; a first control switch (D1, M1), coupled between the output terminal of the crystal oscillator core circuit and the second bias circuit, configured to be conductive in response to the voltage level of the sinusoidal wave being greater than an upper bound level; and a second control switch (D2, M2), coupled between the output terminal of the crystal oscillator core circuit and the third bias circuit, configured to be conductive in response to the voltage level of the sinusoidal wave being less than a lower bound level, wherein the specific voltage range is determined according to the second voltage level and the third voltage level, and wherein the upper bound level and the lower bound level correspond to the second voltage level and the third voltage level, respectively. a crystal oscillator core circuit, configured to generate a sinusoidal wave; a first bias circuit, coupled to an output terminal of the crystal oscillator core circuit, configured to provide a first voltage level to be a bias voltage of the sinusoidal wave; and a phase noise reduction circuit (190, 190M), coupled to the output terminal of the crystal oscillator core circuit, configured to reset noise of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range, the phase noise reduction circuit (190, 190M) comprising: a second bias circuit, configured to control a second voltage level; a third bias circuit, configured to control a third voltage level; a first control switch (D1, M1), coupled between the output terminal of the crystal oscillator core circuit and the second bias circuit, configured to be conductive in response to the voltage level of the sinusoidal wave being greater than an upper bound level; and a second control switch (D2, M2), coupled between the output terminal of the crystal oscillator core circuit and the third bias circuit, configured to be conductive in response to the voltage level of the sinusoidal wave being less than a lower bound level, wherein the specific voltage range is determined according to the second voltage level and the third voltage level, and wherein the upper bound level and the lower bound level correspond to the second voltage level and the third voltage level, respectively. a second bias circuit, configured to control a second voltage level; a third bias circuit, configured to control a third voltage level; a first control switch (D1, M1), coupled between the output terminal of the crystal oscillator core circuit and the second bias circuit, configured to be conductive in response to the voltage level of the sinusoidal wave being greater than an upper bound level; and a second control switch (D2, M2), coupled between the output terminal of the crystal oscillator core circuit and the third bias circuit, configured to be conductive in response to the voltage level of the sinusoidal wave being less than a lower bound level, wherein the specific voltage range is determined according to the second voltage level and the third voltage level, and wherein the upper bound level and the lower bound level correspond to the second voltage level and the third voltage level, respectively.