A microprocessor, comprising functional units (104, 108, 112, 114, 116, 118, 138), wherein the microprocessor further comprises: control registers to cause the functional units to institute one or more actions that reduce the instructions-per-clock, IPC, rate of the microprocessor to reduce power consumption when the microprocessor is running in a non-sleeping state at its lowest supported clock frequency; performance state duration counters configured to count the amount of time in a most recent predetermined amount of time the microprocessor has been running in each possible performance state it supports; microcode configured within the microprocessor to examine whether a set of predetermined conditions exist, the set of predetermined conditions including: whether an operating system running on the microprocessor supports multiple performance states; and whether the microprocessor is running in a non-sleeping state at its lowest supported clock frequency; wherein the microprocessor determines whether the operating system supports multiple performance states by detecting whether the operating system has requested at least one performance state transition since it was booted or since the microprocessor was reset; the set of predetermined conditions further including: whether the microprocessor was running in a non-sleeping state at its lowest supported clock frequency at least a predetermined percentage of time over a most recent predetermined time period; whether prior to the most recent transition to running in a non-sleeping state at its lowest supported clock frequency, the microprocessor was running at a higher clock frequency than the lowest supported clock frequency for no more than a predetermined time period; or whether a calculated score is less than a predetermined score, wherein the microprocessor calculates the score based on a weighted average of time spent running in a non-sleeping state at each of a plurality of clock frequencies higher than the lowest supported clock frequency prior to the most recent transition to running in a non-sleeping state at its lowest supported clock frequency; wherein the microprocessor determines the amount of time in the most recent predetermined amount of time the microprocessor has been running in each performance state by examining the performance state duration counters; wherein if the set of predetermined conditions exist, then the microcode is configured to write values to the control register to cause the functional units to institute the one or more IPC-rate-reducing actions. control registers to cause the functional units to institute one or more actions that reduce the instructions-per-clock, IPC, rate of the microprocessor to reduce power consumption when the microprocessor is running in a non-sleeping state at its lowest supported clock frequency; performance state duration counters configured to count the amount of time in a most recent predetermined amount of time the microprocessor has been running in each possible performance state it supports; microcode configured within the microprocessor to examine whether a set of predetermined conditions exist, the set of predetermined conditions including: whether an operating system running on the microprocessor supports multiple performance states; and whether the microprocessor is running in a non-sleeping state at its lowest supported clock frequency; whether an operating system running on the microprocessor supports multiple performance states; and whether the microprocessor is running in a non-sleeping state at its lowest supported clock frequency; wherein the microprocessor determines whether the operating system supports multiple performance states by detecting whether the operating system has requested at least one performance state transition since it was booted or since the microprocessor was reset; whether the microprocessor was running in a non-sleeping state at its lowest supported clock frequency at least a predetermined percentage of time over a most recent predetermined time period; whether prior to the most recent transition to running in a non-sleeping state at its lowest supported clock frequency, the microprocessor was running at a higher clock frequency than the lowest supported clock frequency for no more than a predetermined time period; or whether a calculated score is less than a predetermined score, wherein the microprocessor calculates the score based on a weighted average of time spent running in a non-sleeping state at each of a plurality of clock frequencies higher than the lowest supported clock frequency prior to the most recent transition to running in a non-sleeping state at its lowest supported clock frequency;