A nonvolatile memory device (100, 200, 1100) comprising: at least one memory block including a plurality of cell strings (STR1 - STRm), each of the plurality of cell strings (STR1 - STRm) including a string selection transistor (SST1 - SSTm), a plurality of memory cells (MC1 - MC8), and a ground selection transistor (GST1 - GSTm), the string selection transistor (SST1 - SSTm), the plurality of memory cells (MC1 - MC8), and the ground selection transistors (GST1 - GSTm) between a source line and a bit-line and connected in series in a vertical direction; and a control circuitry configured to control a program operation, the program operation comprising a plurality of program loops, each program loop including the sequentially performed periods of a bit-line set-up period (PBLS), a program execution period (PGME), a program recovery period (PGMRC) and a verification read period (VFRD), by: by, precharging channels of the plurality of cell strings (STR1 - STRm) to a first voltage during a bit-line set-up period (PBLS) of the program loop, applying a program voltage (VPGM) to a selected word-line (WL_SEL) of the plurality of cell strings (STR1 - STRm) during the program execution period (PGME) of the program loop, and after lowering voltages of the selected word-line (WL_SEL) and of unselected word-lines (WL_ULS) of the plurality of cell strings (STR1 - STRm) to a same voltage level (VNEG1) less than a ground voltage, recovering the voltages of the selected word-line (WL_SEL) and of the unselected word-lines (WL_ULS) to a same second voltage level greater than the ground voltage during the program recovery period (PGMRC) of the program loop. at least one memory block including a plurality of cell strings (STR1 - STRm), each of the plurality of cell strings (STR1 - STRm) including a string selection transistor (SST1 - SSTm), a plurality of memory cells (MC1 - MC8), and a ground selection transistor (GST1 - GSTm), the string selection transistor (SST1 - SSTm), the plurality of memory cells (MC1 - MC8), and the ground selection transistors (GST1 - GSTm) between a source line and a bit-line and connected in series in a vertical direction; and a control circuitry configured to control a program operation, the program operation comprising a plurality of program loops, each program loop including the sequentially performed periods of a bit-line set-up period (PBLS), a program execution period (PGME), a program recovery period (PGMRC) and a verification read period (VFRD), by: by, precharging channels of the plurality of cell strings (STR1 - STRm) to a first voltage during a bit-line set-up period (PBLS) of the program loop, applying a program voltage (VPGM) to a selected word-line (WL_SEL) of the plurality of cell strings (STR1 - STRm) during the program execution period (PGME) of the program loop, and after lowering voltages of the selected word-line (WL_SEL) and of unselected word-lines (WL_ULS) of the plurality of cell strings (STR1 - STRm) to a same voltage level (VNEG1) less than a ground voltage, recovering the voltages of the selected word-line (WL_SEL) and of the unselected word-lines (WL_ULS) to a same second voltage level greater than the ground voltage during the program recovery period (PGMRC) of the program loop. precharging channels of the plurality of cell strings (STR1 - STRm) to a first voltage during a bit-line set-up period (PBLS) of the program loop, applying a program voltage (VPGM) to a selected word-line (WL_SEL) of the plurality of cell strings (STR1 - STRm) during the program execution period (PGME) of the program loop, and after lowering voltages of the selected word-line (WL_SEL) and of unselected word-lines (WL_ULS) of the plurality of cell strings (STR1 - STRm) to a same voltage level (VNEG1) less than a ground voltage, recovering the voltages of the selected word-line (WL_SEL) and of the unselected word-lines (WL_ULS) to a same second voltage level greater than the ground voltage during the program recovery period (PGMRC) of the program loop.