A MEMS chip, wherein the MEMS chip comprises a MEMS device layer, a first isolating layer, and a first conducting layer, wherein the MEMS device layer comprises a first region and at least one second region, the first region comprises MEMS movable structures and conductive structures on an upper surface of the MEMS chip, the conductive structures are distributed among the MEMS movable structures, the second region is an electrode arrangement region, and on the upper surface of the MEMS chip, the conductive structures are electrically isolated from electrodes in the second region; the first isolating layer is located under the MEMS device layer, and at the first isolating layer, there are corresponding quantities of first conductive through holes in locations corresponding to the conductive structures in the first region and in locations corresponding to the electrodes in the second region; the first conducting layer is located under the first isolating layer, and at the first conducting layer, there are M electrodes independent of each other, and the M electrodes are respectively connected to M first conductive through holes, wherein M is a positive integer, and M is set based on a quantity of the conductive structures and a quantity of the electrodes in the second region; and at the first conducting layer, electrodes in locations corresponding to the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to the electrodes in the second region, characterized by an n th isolating layer located under the (n-1) th conducting layer and an n th conducting layer located under the n th isolating layer for each n with 2≤n≤N, wherein N is a positive integer greater than or equal to 2; wherein at the first conducting layer, in a region excluding the M electrodes, there are second conductive through holes connected to the first conductive through holes in a one-to-one correspondence, wherein M is less than a sum of the quantity of the conductive structures and the quantity of the electrodes in the second region; at the n th isolating layer, in locations corresponding to (2n-2) th conductive through holes, there are (2n-1) th conductive through holes connected to the (2n-2) th conductive through holes in a one-to-one correspondence; at the n th conducting layer, there are Q electrodes that are independent of each other and connected to the (2n-1) th conductive through holes, wherein Q is less than or equal to a quantity of the (2n-1) th conductive through holes; and at the n th conducting layer, electrodes in locations corresponding to the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to the electrodes in the second region. the MEMS device layer comprises a first region and at least one second region, the first region comprises MEMS movable structures and conductive structures on an upper surface of the MEMS chip, the conductive structures are distributed among the MEMS movable structures, the second region is an electrode arrangement region, and on the upper surface of the MEMS chip, the conductive structures are electrically isolated from electrodes in the second region; the first isolating layer is located under the MEMS device layer, and at the first isolating layer, there are corresponding quantities of first conductive through holes in locations corresponding to the conductive structures in the first region and in locations corresponding to the electrodes in the second region; the first conducting layer is located under the first isolating layer, and at the first conducting layer, there are M electrodes independent of each other, and the M electrodes are respectively connected to M first conductive through holes, wherein M is a positive integer, and M is set based on a quantity of the conductive structures and a quantity of the electrodes in the second region; and at the first conducting layer, electrodes in locations corresponding to the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to the electrodes in the second region, characterized by an n th isolating layer located under the (n-1) th conducting layer and an n th conducting layer located under the n th isolating layer for each n with 2≤n≤N, wherein N is a positive integer greater than or equal to 2; wherein at the first conducting layer, in a region excluding the M electrodes, there are second conductive through holes connected to the first conductive through holes in a one-to-one correspondence, wherein M is less than a sum of the quantity of the conductive structures and the quantity of the electrodes in the second region; at the n th isolating layer, in locations corresponding to (2n-2) th conductive through holes, there are (2n-1) th conductive through holes connected to the (2n-2) th conductive through holes in a one-to-one correspondence; at the n th conducting layer, there are Q electrodes that are independent of each other and connected to the (2n-1) th conductive through holes, wherein Q is less than or equal to a quantity of the (2n-1) th conductive through holes; and at the n th conducting layer, electrodes in locations corresponding to the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to the electrodes in the second region.