A memory device, comprising: an array of resistive random access memory cells, each of the resistive random access memory cells including a variable state material to represent data as the variable state; a column driver coupled to the array of resistive random access memory cells to provide set, reset, and inhibit voltages to different resistive random access memory cells in the array at the same time, wherein a source line is commonly coupled to an inhibit voltage line; and a set node, a reset node, and an inhibit node coupled to the column driver, wherein the reset node is associated with a reset voltage, the set node is associated with a set voltage and the inhibit node is associated with an inhibit voltage, wherein the column driver includes a plurality of individually selectable selector circuits (405a-405c) to select which of the set node, the reset node or the inhibit node to couple to the different memory cells at the same time, the selector circuits comprising, for each of a plurality of address lines, a NOT gate operable to receive a first input which, in one logic state, causes generation of an output which is operable to close a first switch to couple the address line with a first one of the set node, the reset node or the inhibit node, a first AND gate operable to receive a second input and a third input which, in one logic state, cause the generation of an output which is operable to close a second switch to couple the address line with a second of the set node, the reset node or the inhibit node, and a second AND gate operable to receive the third input and the inverse of the third input, to cause the generation of an output which is operable to close a third switch to couple the address line with a third of the set node, the reset node or the inhibit node, the first, second and third inputs being configured so as to drive one of the switches closed to couple the address line with a corresponding one of the set node, the reset node or the inhibit node, while holding the other switches open. an array of resistive random access memory cells, each of the resistive random access memory cells including a variable state material to represent data as the variable state; a column driver coupled to the array of resistive random access memory cells to provide set, reset, and inhibit voltages to different resistive random access memory cells in the array at the same time, wherein a source line is commonly coupled to an inhibit voltage line; and a set node, a reset node, and an inhibit node coupled to the column driver, wherein the reset node is associated with a reset voltage, the set node is associated with a set voltage and the inhibit node is associated with an inhibit voltage, wherein the column driver includes a plurality of individually selectable selector circuits (405a-405c) to select which of the set node, the reset node or the inhibit node to couple to the different memory cells at the same time, the selector circuits comprising, for each of a plurality of address lines, a NOT gate operable to receive a first input which, in one logic state, causes generation of an output which is operable to close a first switch to couple the address line with a first one of the set node, the reset node or the inhibit node, a first AND gate operable to receive a second input and a third input which, in one logic state, cause the generation of an output which is operable to close a second switch to couple the address line with a second of the set node, the reset node or the inhibit node, and a second AND gate operable to receive the third input and the inverse of the third input, to cause the generation of an output which is operable to close a third switch to couple the address line with a third of the set node, the reset node or the inhibit node, the first, second and third inputs being configured so as to drive one of the switches closed to couple the address line with a corresponding one of the set node, the reset node or the inhibit node, while holding the other switches open.