A method of producing a delay output in a memory system, comprising: receiving an input signal from a sense path traversing a first portion of a plurality of voltage domains, wherein the sense path has a first delay responsive to the first portion, wherein an access path traversing a second portion of the plurality of voltage domains has a second delay responsive to the second portion, wherein the plurality of voltage domains comprises a lower voltage domain (V L) and a higher voltage domain (V H), and wherein each of the sense path and the access path traverses both the lower voltage domain (V L) and the higher voltage domain (V H); generating a delay output related to the first and second delays from one or more delay circuits provided in the sense path and that receive the input signal, wherein generating the delay output comprises: delaying input signal using one or more first delay elements (82, 88) whose voltages are supplied by a first voltage supply among the plurality of voltage domains; delaying the input signal using one or more second delay elements (84, 90) whose voltages are supplied by a second voltage supply among the plurality of voltage domains; the method characterised in that it further comprises: combining the delayed input signal from the one or more first delay elements (82, 88) and the delayed input signal from the one or more second delay elements (84, 90) to generate the delay output; and receiving the delay output at a plurality of sense amplifiers configured to sense data from bit lines output from at least one memory cell coupled to the access path. receiving an input signal from a sense path traversing a first portion of a plurality of voltage domains, wherein the sense path has a first delay responsive to the first portion, wherein an access path traversing a second portion of the plurality of voltage domains has a second delay responsive to the second portion, wherein the plurality of voltage domains comprises a lower voltage domain (V L) and a higher voltage domain (V H), and wherein each of the sense path and the access path traverses both the lower voltage domain (V L) and the higher voltage domain (V H); generating a delay output related to the first and second delays from one or more delay circuits provided in the sense path and that receive the input signal, wherein generating the delay output comprises: delaying input signal using one or more first delay elements (82, 88) whose voltages are supplied by a first voltage supply among the plurality of voltage domains; delaying the input signal using one or more second delay elements (84, 90) whose voltages are supplied by a second voltage supply among the plurality of voltage domains; the method characterised in that it further comprises: combining the delayed input signal from the one or more first delay elements (82, 88) and the delayed input signal from the one or more second delay elements (84, 90) to generate the delay output; and delaying input signal using one or more first delay elements (82, 88) whose voltages are supplied by a first voltage supply among the plurality of voltage domains; delaying the input signal using one or more second delay elements (84, 90) whose voltages are supplied by a second voltage supply among the plurality of voltage domains; the method characterised in that it further comprises: combining the delayed input signal from the one or more first delay elements (82, 88) and the delayed input signal from the one or more second delay elements (84, 90) to generate the delay output; and combining the delayed input signal from the one or more first delay elements (82, 88) and the delayed input signal from the one or more second delay elements (84, 90) to generate the delay output; and receiving the delay output at a plurality of sense amplifiers configured to sense data from bit lines output from at least one memory cell coupled to the access path.