An amplifier adapted for noise suppression, comprising: a first input for receiving a first input signal and a second input for receiving a second input signal, the first and second input signals constituting a differential pair; a first output for delivering a first output signal and a second output for delivering a second output signal, the first and second output signals constituting a differential pair; a first NMOS transistor (M CG1) having a first drain coupled to the first output such that all signal current, except parasitic losses, flowing through the first drain flows through the first output, and the first NMOS transistor (M CG1) further having a first source coupled to the first input; a second NMOS transistor (Mcsi) having a second gate coupled to the first input, a second drain coupled to the second output such that all signal current, except parasitic losses, flowing through the second drain flows through the second output, and the second NMOS transistor (Mcsi) further having a second source coupled to a first voltage rail; a third NMOS transistor (M CS2) having a third gate coupled to the second input, a third drain coupled to the first output such that all signal current, except parasitic losses, flowing through the third drain flows through the first output, and the third NMOS transistor (M CS2) further having a third source coupled to the first voltage rail; a fourth NMOS transistor (M CG2) having a fourth drain coupled to the second output such that all signal current, except parasitic losses, flowing through the fourth drain flows through the second output, and the fourth NMOS transistor (M CG2) further having a fourth source coupled to the second input; a first load (Z L1) coupled between the first output and a second voltage rail; a second load (Z L2) coupled between the second output and the second voltage rail; a first inductive element (L 1) coupled between the first input and a third voltage rail; and a second inductive element (L 2) coupled between the second input and the third voltage rail; wherein transconductance of the first NMOS transistor (M CG1) is substantially equal to transconductance of the fourth NMOS transistor (M CG2) within ±5%; wherein transconductance of the second NMOS transistor (Mcsi) is substantially equal to transconductance of the third NMOS transistor (M CS2)within ±5%; and characterised in that the transconductance of the second NMOS transistor (Mcsi) exceeds the transconductance of the first NMOS transistor (M CG1), and the transconductance of the third NMOS transistor (M CS2) exceeds the transconductance of the fourth NMOS transistor. a first input for receiving a first input signal and a second input for receiving a second input signal, the first and second input signals constituting a differential pair; a first output for delivering a first output signal and a second output for delivering a second output signal, the first and second output signals constituting a differential pair; a first NMOS transistor (M CG1) having a first drain coupled to the first output such that all signal current, except parasitic losses, flowing through the first drain flows through the first output, and the first NMOS transistor (M CG1) further having a first source coupled to the first input; a second NMOS transistor (Mcsi) having a second gate coupled to the first input, a second drain coupled to the second output such that all signal current, except parasitic losses, flowing through the second drain flows through the second output, and the second NMOS transistor (Mcsi) further having a second source coupled to a first voltage rail; a third NMOS transistor (M CS2) having a third gate coupled to the second input, a third drain coupled to the first output such that all signal current, except parasitic losses, flowing through the third drain flows through the first output, and the third NMOS transistor (M CS2) further having a third source coupled to the first voltage rail; a fourth NMOS transistor (M CG2) having a fourth drain coupled to the second output such that all signal current, except parasitic losses, flowing through the fourth drain flows through the second output, and the fourth NMOS transistor (M CG2) further having a fourth source coupled to the second input; a first load (Z L1) coupled between the first output and a second voltage rail; a second load (Z L2) coupled between the second output and the second voltage rail; a first inductive element (L 1) coupled between the first input and a third voltage rail; and a second inductive element (L 2) coupled between the second input and the third voltage rail; wherein transconductance of the first NMOS transistor (M CG1) is substantially equal to transconductance of the fourth NMOS transistor (M CG2) within ±5%; wherein transconductance of the second NMOS transistor (Mcsi) is substantially equal to transconductance of the third NMOS transistor (M CS2)within ±5%; and characterised in that the transconductance of the second NMOS transistor (Mcsi) exceeds the transconductance of the first NMOS transistor (M CG1), and the transconductance of the third NMOS transistor (M CS2) exceeds the transconductance of the fourth NMOS transistor.