A cryptographic device comprising: a tamper detection circuit having a physical security boundary; a low battery detection circuit located within the physical security boundary; a volatile memory device (42a, 42b, 42c) located within the physical security boundary; a battery, external to the physical security boundary, coupled to a power input of the memory device for providing power to the memory device (42a, 42b, 42c) under normal operating conditions; a latch having an input coupled to the tamper detection circuit and the low battery detection circuit and an output coupled to a clear input of the memory device, the latch, in response to receiving a signal from the tamper detection circuit or the low battery detection circuit indicating a tamper event, causing a clear signal to be input to the clear input of the memory device; a capacitor, located within the physical security boundary, having a first node coupled to the power input of the memory device and a second node coupled to ground, the capacitor storing charge from the battery under normal operating conditions, the capacitor, when the battery is shorted, providing the stored charge to the memory device (42a, 42b, 42c), thereby allowing the memory device to use the stored charge to perform an active clearing operation of the memory device (42a, 42b, 42c) when the latch responds to either the low battery detection circuit or to the tamper detection circuit detecting a tamper event; and a discharge prevention means, located within the physical security boundary, having a first node coupled to the first node of the capacitor and a second node coupled to the battery, the discharge prevention means preventing the stored charge from the capacitor from discharging through the battery when the battery is shorted. a tamper detection circuit having a physical security boundary; a low battery detection circuit located within the physical security boundary; a volatile memory device (42a, 42b, 42c) located within the physical security boundary; a battery, external to the physical security boundary, coupled to a power input of the memory device for providing power to the memory device (42a, 42b, 42c) under normal operating conditions; a latch having an input coupled to the tamper detection circuit and the low battery detection circuit and an output coupled to a clear input of the memory device, the latch, in response to receiving a signal from the tamper detection circuit or the low battery detection circuit indicating a tamper event, causing a clear signal to be input to the clear input of the memory device; a capacitor, located within the physical security boundary, having a first node coupled to the power input of the memory device and a second node coupled to ground, the capacitor storing charge from the battery under normal operating conditions, the capacitor, when the battery is shorted, providing the stored charge to the memory device (42a, 42b, 42c), thereby allowing the memory device to use the stored charge to perform an active clearing operation of the memory device (42a, 42b, 42c) when the latch responds to either the low battery detection circuit or to the tamper detection circuit detecting a tamper event; and a discharge prevention means, located within the physical security boundary, having a first node coupled to the first node of the capacitor and a second node coupled to the battery, the discharge prevention means preventing the stored charge from the capacitor from discharging through the battery when the battery is shorted.