An apparatus comprising: a set of graphics cores (3100A, 3100B,... 3100N) configured to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores (3100A, 3100B,... 3100N) and the scalar cluster; the set of graphics cores (3100A, 3100B,... 3100N) configured to offload execution of a second set of instructions, which is based on the first set of instructions, associated with ray traversal or intersection operations to the scalar cluster; the scalar cluster comprising: instruction fetch circuitry configured to fetch the second set of instructions from a specified region in memory; scheduler/dispatcher circuitry configured to schedule and dispatch the second set of instructions for execution across all or a subset of the plurality of scalar execution engines; a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is configured to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines being configured to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores (3100A, 3100B,... 3100N); wherein the set of graphics cores (3100A, 3100B,... 3100N) are configured to process the results within the primary graphics thread, the hierarchical acceleration data structure comprises a bounding volume hierarchy, BVH, and node data associated with nodes of the BVH are to be stored in the local memories, and wherein a scheduler provides BVH pointers to portions of the BVH to each scalar compute engine. a set of graphics cores (3100A, 3100B,... 3100N) configured to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores (3100A, 3100B,... 3100N) and the scalar cluster; the set of graphics cores (3100A, 3100B,... 3100N) configured to offload execution of a second set of instructions, which is based on the first set of instructions, associated with ray traversal or intersection operations to the scalar cluster; the scalar cluster comprising: instruction fetch circuitry configured to fetch the second set of instructions from a specified region in memory; scheduler/dispatcher circuitry configured to schedule and dispatch the second set of instructions for execution across all or a subset of the plurality of scalar execution engines; a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is configured to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines being configured to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores (3100A, 3100B,... 3100N); wherein the set of graphics cores (3100A, 3100B,... 3100N) are configured to process the results within the primary graphics thread, the hierarchical acceleration data structure comprises a bounding volume hierarchy, BVH, and node data associated with nodes of the BVH are to be stored in the local memories, and wherein a scheduler provides BVH pointers to portions of the BVH to each scalar compute engine. instruction fetch circuitry configured to fetch the second set of instructions from a specified region in memory; scheduler/dispatcher circuitry configured to schedule and dispatch the second set of instructions for execution across all or a subset of the plurality of scalar execution engines; a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is configured to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines being configured to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores (3100A, 3100B,... 3100N); wherein the set of graphics cores (3100A, 3100B,... 3100N) are configured to process the results within the primary graphics thread, the hierarchical acceleration data structure comprises a bounding volume hierarchy, BVH, and node data associated with nodes of the BVH are to be stored in the local memories, and wherein a scheduler provides BVH pointers to portions of the BVH to each scalar compute engine.