An integrated circuit, IC, device comprising: a stacked-die memory device comprising: a set of stacked memory dies (206, 208, 210, 212; 306, 308, 310, 312) providing a memory having a plurality of regions, each region comprising one of a cell-based region, a bank-based region, and a row-based region; and a set of one or more logic dies (202, 204; 302, 304) electrically coupled to the stacked memory dies, the set of one or more logic dies comprising: a processor; and a memory controller (102; 314, 316) to schedule memory accesses to regions of the memory based on identified memory timing parameters specific to the regions, characterized in that the memory controller comprises: profiling logic (110, 318, 320, 410) to identify one or more memory timing parameters for at least one region of the memory, wherein the profiling logic is configured to: measure a type of memory timing parameter of a plurality of types of memory timing parameters for each sub-region of a plurality of sub-regions of each region; and identify the fastest measured memory timing parameter corresponding to each measured type of memory timing parameter of the sub-regions as a memory timing parameter for each corresponding type of memory timing parameter for each region. a stacked-die memory device comprising: a set of stacked memory dies (206, 208, 210, 212; 306, 308, 310, 312) providing a memory having a plurality of regions, each region comprising one of a cell-based region, a bank-based region, and a row-based region; and a set of one or more logic dies (202, 204; 302, 304) electrically coupled to the stacked memory dies, the set of one or more logic dies comprising: a set of stacked memory dies (206, 208, 210, 212; 306, 308, 310, 312) providing a memory having a plurality of regions, each region comprising one of a cell-based region, a bank-based region, and a row-based region; and a set of one or more logic dies (202, 204; 302, 304) electrically coupled to the stacked memory dies, the set of one or more logic dies comprising: a processor; and a memory controller (102; 314, 316) to schedule memory accesses to regions of the memory based on identified memory timing parameters specific to the regions, characterized in that the memory controller comprises: profiling logic (110, 318, 320, 410) to identify one or more memory timing parameters for at least one region of the memory, wherein the profiling logic is configured to: measure a type of memory timing parameter of a plurality of types of memory timing parameters for each sub-region of a plurality of sub-regions of each region; and identify the fastest measured memory timing parameter corresponding to each measured type of memory timing parameter of the sub-regions as a memory timing parameter for each corresponding type of memory timing parameter for each region. measure a type of memory timing parameter of a plurality of types of memory timing parameters for each sub-region of a plurality of sub-regions of each region; and identify the fastest measured memory timing parameter corresponding to each measured type of memory timing parameter of the sub-regions as a memory timing parameter for each corresponding type of memory timing parameter for each region.