An apparatus comprising: decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, one or more fields to reference a first source operand, one or more fields to reference a second source operand, one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding, by one or more first adders (123, 125, 127) of the execution circuitry, a data element of that data element position to each data element of preceding non-masked data element positions and adding, by a second adder of the execution circuitry, at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and execution circuitry configured to execute the decoded instruction according to the opcode, wherein the opcode indicates a datatype and size of the data elements and the decoder circuitry provides control information indicating the datatype and the size to an operation control circuitry of the apparatus, the operation control circuitry configuring the execution circuitry according to the control information to use the one or more first adders (123, 125, 127) and the second adder, which are configured to operate on the data elements of the datatype and the size. decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, one or more fields to reference a first source operand, one or more fields to reference a second source operand, one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding, by one or more first adders (123, 125, 127) of the execution circuitry, a data element of that data element position to each data element of preceding non-masked data element positions and adding, by a second adder of the execution circuitry, at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and perform a prefix sum by for each non-masked data element position of the second source operand adding, by one or more first adders (123, 125, 127) of the execution circuitry, a data element of that data element position to each data element of preceding non-masked data element positions and adding, by a second adder of the execution circuitry, at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and execution circuitry configured to execute the decoded instruction according to the opcode, wherein the opcode indicates a datatype and size of the data elements and the decoder circuitry provides control information indicating the datatype and the size to an operation control circuitry of the apparatus, the operation control circuitry configuring the execution circuitry according to the control information to use the one or more first adders (123, 125, 127) and the second adder, which are configured to operate on the data elements of the datatype and the size.