A process comprising: depositing a top mask onto a silicon wafer, the top mask comprising a first silicon dioxide layer; depositing a bottom mask onto the bottom of the silicon wafer; photopatterning a through silicon via pattern for etching a through silicon via into the top mask; etching the through silicon via, using the through silicon via pattern, through the silicon wafer to the bottom mask; removing the top mask and the bottom mask from the silicon wafer; growing a second thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; etching the second thermal silicon dioxide layer off the silicon wafer; growing a third thermal silicon oxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via, thereby forming a passivation layer; sputter depositing an adhesion layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; depositing a plating seed layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; electroplating a copper layer in the through silicon via; depositing a second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer; depositing a fourth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; etching the fourth silicon dioxide layer to remove a portion of the fourth silicon dioxide layer; depositing a fifth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; etching the fifth silicon dioxide layer to remove a portion of the fifth silicon dioxide layer; depositing a sixth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer; chemomechanically polishing the sixth silicon dioxide layer down to the copper layer on the top of the silicon wafer and the bottom of the silicon wafer; and chemomechanically polishing the copper layer, the first adhesion layer, and the second adhesion layer down to the third silicon dioxide layer. depositing a top mask onto a silicon wafer, the top mask comprising a first silicon dioxide layer; depositing a bottom mask onto the bottom of the silicon wafer; photopatterning a through silicon via pattern for etching a through silicon via into the top mask; etching the through silicon via, using the through silicon via pattern, through the silicon wafer to the bottom mask; removing the top mask and the bottom mask from the silicon wafer; growing a second thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; etching the second thermal silicon dioxide layer off the silicon wafer; growing a third thermal silicon oxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via, thereby forming a passivation layer; sputter depositing an adhesion layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; depositing a plating seed layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; electroplating a copper layer in the through silicon via; depositing a second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer; depositing a fourth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; etching the fourth silicon dioxide layer to remove a portion of the fourth silicon dioxide layer; depositing a fifth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via; etching the fifth silicon dioxide layer to remove a portion of the fifth silicon dioxide layer; depositing a sixth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer; chemomechanically polishing the sixth silicon dioxide layer down to the copper layer on the top of the silicon wafer and the bottom of the silicon wafer; and chemomechanically polishing the copper layer, the first adhesion layer, and the second adhesion layer down to the third silicon dioxide layer.