An optoelectronic device (110; 210; 410; 610; 710; 810; 910; 1010) comprising: a substrate (112; 212; 412; 612; 712; 812; 912) comprising a groove (114; 214; 414; 614; 714; 814a, 814b; 914; 1014) having a first side (113; 216; 316; 416; 613; 716; 813a, 813b; 916) comprising a first face (113a; 216a; 416a; 613a; 716a; 916a) of the groove and a first surface (113b; 216b; 416b; 613b; 716b; 813ab, 813bb; 916b) of the substrate (112; 212; 412; 612; 712; 812; 912) adjacent the groove, and a second side (116; 213; 413; 616; 713; 816a, 816b; 913) comprising a second face (116a; 213a; 413a; 616a; 713a; 913a) of the groove and a second surface (116b; 213b; 413b; 616b; 713b; 816ab, 816bb; 913b) of the substrate adjacent the groove, the first and second surfaces adjacent the groove being in the same plane as the substrate; the first and second sides of the groove are each coated with both a conductor material (118; 218; 418; 618; 718; 818; 918; 1018) and a semiconductor material (120; 220; 420; 620; 720; 820; 920; 1020); wherein the conductor material (118; 218; 418; 618; 718; 818; 918; 1018) is coated on first and second surfaces of the substrate adjacent the groove, and coats from 20% to 80% of the second face (116a; 213a; 413a; 616a; 713a; 913a) of the groove; wherein the semiconductor material (120; 220; 420; 620; 720; 820; 920; 1020) is coated on top of the conductor material (118; 218; 418; 618; 718; 818; 918; 1018) on the first and second surfaces of the substrate adjacent the groove, and coats from 20% to 80% of the first face (113a; 216a; 416a; 613a; 716a; 916a) of the groove; another semiconductor (122; 222; 422; 622; 722; 822; 922) partially fills the groove (114; 214; 414; 614; 714; 814a, 814b; 914; 1014) between the first (113a; 216a; 416a; 613a; 716a; 916a) and second (116a; 213a; 413a; 616a; 713a; 913a) faces of the groove; wherein the semiconductor material on the first face of the groove is in contact with the another semiconductor so as to form a p-n junction, wherein the conductor material on the second face of the groove is in contact with the another semiconductor material (122; 222; 422; 622; 722; 822; 922; 1022) in the groove; and wherein at the second side of the groove there is a gap (169; 269; 469; 669; 769; 969) between the semiconductor material on the second side of the groove and the another semiconductor material in the groove; characterised in that the surface (123; 223; 423; 626; 723; 923; 1023) of the another semiconductor is tilted with respect to the plane of the substrate so that the size of the gap is increased compared to the size of the gap if the surface would not be tilted. a substrate (112; 212; 412; 612; 712; 812; 912) comprising a groove (114; 214; 414; 614; 714; 814a, 814b; 914; 1014) having a first side (113; 216; 316; 416; 613; 716; 813a, 813b; 916) comprising a first face (113a; 216a; 416a; 613a; 716a; 916a) of the groove and a first surface (113b; 216b; 416b; 613b; 716b; 813ab, 813bb; 916b) of the substrate (112; 212; 412; 612; 712; 812; 912) adjacent the groove, and a second side (116; 213; 413; 616; 713; 816a, 816b; 913) comprising a second face (116a; 213a; 413a; 616a; 713a; 913a) of the groove and a second surface (116b; 213b; 413b; 616b; 713b; 816ab, 816bb; 913b) of the substrate adjacent the groove, the first and second surfaces adjacent the groove being in the same plane as the substrate; the first and second sides of the groove are each coated with both a conductor material (118; 218; 418; 618; 718; 818; 918; 1018) and a semiconductor material (120; 220; 420; 620; 720; 820; 920; 1020); wherein the conductor material (118; 218; 418; 618; 718; 818; 918; 1018) is coated on first and second surfaces of the substrate adjacent the groove, and coats from 20% to 80% of the second face (116a; 213a; 413a; 616a; 713a; 913a) of the groove; wherein the semiconductor material (120; 220; 420; 620; 720; 820; 920; 1020) is coated on top of the conductor material (118; 218; 418; 618; 718; 818; 918; 1018) on the first and second surfaces of the substrate adjacent the groove, and coats from 20% to 80% of the first face (113a; 216a; 416a; 613a; 716a; 916a) of the groove; another semiconductor (122; 222; 422; 622; 722; 822; 922) partially fills the groove (114; 214; 414; 614; 714; 814a, 814b; 914; 1014) between the first (113a; 216a; 416a; 613a; 716a; 916a) and second (116a; 213a; 413a; 616a; 713a; 913a) faces of the groove; wherein the semiconductor material on the first face of the groove is in contact with the another semiconductor so as to form a p-n junction, wherein the conductor material on the second face of the groove is in contact with the another semiconductor material (122; 222; 422; 622; 722; 822; 922; 1022) in the groove; and wherein at the second side of the groove there is a gap (169; 269; 469; 669; 769; 969) between the semiconductor material on the second side of the groove and the another semiconductor material in the groove; characterised in that the surface (123; 223; 423; 626; 723; 923; 1023) of the another semiconductor is tilted with respect to the plane of the substrate so that the size of the gap is increased compared to the size of the gap if the surface would not be tilted.