An apparatus, comprising: a first power transistor (B_FET) having a first current conduction path between a first current conduction terminal and a second current conduction terminal, the first current conduction path of the first power transistor (B_FET) coupled between an input for receiving a supply voltage and a node (VMID), the first power transistor (B_FET) having a first gate terminal for controlling the first power transistor (B_FET) coupled to a first gate control signal (BGATE); a second power transistor (HS-FET) having a second current conduction path between a third current conduction terminal and a fourth current conduction terminal, the second current conduction path of the second power transistor (HS-FET) coupled between the node (VMID) and an output terminal for supplying a load current to a load; the second power transistor (HS-FET) having a second gate terminal coupled to a second gate control signal; a current sense transistor (SENSE FET) having one current conduction terminal coupled to the node (VMID) and the first power transistor (B _FET), having a third gate terminal coupled to the first gate control signal (BGATE), and outputting a sense current at another current conduction terminal; a differential amplifier having a first input coupled to one of the first and second current conduction terminals of the first power transistor (B_FET) and having a second input coupled to the other one of the first and second current conduction terminals, and having an output signal responsive to a voltage difference between the first input and the second input; a feedback transistor (FB-FET) having another current conduction path coupled in series between the current sense transistor and a monitor node (VMON), having a feedback transistor gate terminal coupled to the output of the differential amplifier; and a resistor (RMON) coupled between the monitor node (VMON) and ground, the sense current flowing through the resistor, the sense current being proportional to the load current flowing through the second power transistor (HS-FET). a first power transistor (B_FET) having a first current conduction path between a first current conduction terminal and a second current conduction terminal, the first current conduction path of the first power transistor (B_FET) coupled between an input for receiving a supply voltage and a node (VMID), the first power transistor (B_FET) having a first gate terminal for controlling the first power transistor (B_FET) coupled to a first gate control signal (BGATE); a second power transistor (HS-FET) having a second current conduction path between a third current conduction terminal and a fourth current conduction terminal, the second current conduction path of the second power transistor (HS-FET) coupled between the node (VMID) and an output terminal for supplying a load current to a load; the second power transistor (HS-FET) having a second gate terminal coupled to a second gate control signal; a current sense transistor (SENSE FET) having one current conduction terminal coupled to the node (VMID) and the first power transistor (B _FET), having a third gate terminal coupled to the first gate control signal (BGATE), and outputting a sense current at another current conduction terminal; a differential amplifier having a first input coupled to one of the first and second current conduction terminals of the first power transistor (B_FET) and having a second input coupled to the other one of the first and second current conduction terminals, and having an output signal responsive to a voltage difference between the first input and the second input; a feedback transistor (FB-FET) having another current conduction path coupled in series between the current sense transistor and a monitor node (VMON), having a feedback transistor gate terminal coupled to the output of the differential amplifier; and a resistor (RMON) coupled between the monitor node (VMON) and ground, the sense current flowing through the resistor, the sense current being proportional to the load current flowing through the second power transistor (HS-FET).