A processor comprising: a plurality of processing engines (1715A-N); a first performance counter and a second performance counter configured to determine a first interrupt rate metric and a second interrupt rate metric for a first processing engine of said plurality of processing engines (1715A-N), respectively, wherein the first performance counter is configured to count first interrupts occurring during a sliding time window, wherein the first interrupts are interrupts that cannot be ignored by the processor, and wherein the first interrupt rate metric is based on a proportion of processing load used to handle the first interrupts, and the second interrupt counter is configured to count the first interrupts and second interrupts, wherein the second interrupts are interrupts that can be temporarily ignored by the processor, occurring during the sliding time window, and wherein the second interrupt rate metric is based on a proportion of processing load used to handle the first and the second interrupts; and a power control circuit (1720, 1850) configured to: determine, using the first and second performance counters (1730, 1810, 1814), whether the at least one of the first and second interrupt rate metrics is equal to or greater than a respective threshold (1820, 1825) associated with the respective one of the first and second performance counters (1810, 1815) while the first processing engine is operating at a first frequency level; and in response to a determination that at least one of the first and second interrupt rate metrics is equal to or greater than the respective threshold (1820, 1825) while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level. a plurality of processing engines (1715A-N); a first performance counter and a second performance counter configured to determine a first interrupt rate metric and a second interrupt rate metric for a first processing engine of said plurality of processing engines (1715A-N), respectively, wherein the first performance counter is configured to count first interrupts occurring during a sliding time window, wherein the first interrupts are interrupts that cannot be ignored by the processor, and wherein the first interrupt rate metric is based on a proportion of processing load used to handle the first interrupts, and the second interrupt counter is configured to count the first interrupts and second interrupts, wherein the second interrupts are interrupts that can be temporarily ignored by the processor, occurring during the sliding time window, and wherein the second interrupt rate metric is based on a proportion of processing load used to handle the first and the second interrupts; and a power control circuit (1720, 1850) configured to: determine, using the first and second performance counters (1730, 1810, 1814), whether the at least one of the first and second interrupt rate metrics is equal to or greater than a respective threshold (1820, 1825) associated with the respective one of the first and second performance counters (1810, 1815) while the first processing engine is operating at a first frequency level; and in response to a determination that at least one of the first and second interrupt rate metrics is equal to or greater than the respective threshold (1820, 1825) while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level. determine, using the first and second performance counters (1730, 1810, 1814), whether the at least one of the first and second interrupt rate metrics is equal to or greater than a respective threshold (1820, 1825) associated with the respective one of the first and second performance counters (1810, 1815) while the first processing engine is operating at a first frequency level; and in response to a determination that at least one of the first and second interrupt rate metrics is equal to or greater than the respective threshold (1820, 1825) while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.