A single photon counting detector system, comprising in a chip design: a) a layer of photosensitive material; b) an NxM array of photo-detector diodes arranged in said layer of photosensitive material; each of said photo-detector diodes having a bias potential interface and a diode output interface, said bias potential interface of each photo-detector diode being connected to a bias potential (V bias); c) a readout chip comprising an NxM array of high gain, low noise readout unit cells, one readout unit cell for each photo-detector diode; d) each readout unit cell comprising: d1) an input interface connected to said diode output interface, a high-gain voltage amplifying means (amp) connected to said input interface and comprising an integration capacitor (C int) and an output of said high-gain voltage amplifying means connected to at least two parallel counter lines (30, 32), each counter line (30, 32) having a digital counter (34, 36), d2) each counter line (30, 32) comprising a comparator (comp1, comp2) having an individually selectable threshold (threshold1, threshold2) and a gateable section (gate1, gate2, gate 4) to determine the counting intervals of the digital counters individually for each counter line; e) a multiplexing means allowing to access the readout unit cells either on a per pixel basis or for several pixels in parallel to read out the digital counters (34, 36) to a data processing means transferring the count of the digital counters (34, 36) off the readout chip to the data processing means. a) a layer of photosensitive material; b) an NxM array of photo-detector diodes arranged in said layer of photosensitive material; each of said photo-detector diodes having a bias potential interface and a diode output interface, said bias potential interface of each photo-detector diode being connected to a bias potential (V bias); c) a readout chip comprising an NxM array of high gain, low noise readout unit cells, one readout unit cell for each photo-detector diode; d) each readout unit cell comprising: d1) an input interface connected to said diode output interface, a high-gain voltage amplifying means (amp) connected to said input interface and comprising an integration capacitor (C int) and an output of said high-gain voltage amplifying means connected to at least two parallel counter lines (30, 32), each counter line (30, 32) having a digital counter (34, 36), d2) each counter line (30, 32) comprising a comparator (comp1, comp2) having an individually selectable threshold (threshold1, threshold2) and a gateable section (gate1, gate2, gate 4) to determine the counting intervals of the digital counters individually for each counter line; d1) an input interface connected to said diode output interface, a high-gain voltage amplifying means (amp) connected to said input interface and comprising an integration capacitor (C int) and an output of said high-gain voltage amplifying means connected to at least two parallel counter lines (30, 32), each counter line (30, 32) having a digital counter (34, 36), d2) each counter line (30, 32) comprising a comparator (comp1, comp2) having an individually selectable threshold (threshold1, threshold2) and a gateable section (gate1, gate2, gate 4) to determine the counting intervals of the digital counters individually for each counter line; e) a multiplexing means allowing to access the readout unit cells either on a per pixel basis or for several pixels in parallel to read out the digital counters (34, 36) to a data processing means transferring the count of the digital counters (34, 36) off the readout chip to the data processing means.