A method of fabricating an integrated circuit on a substrate, comprising: depositing a local interconnect layer of a metal, that is suitable for fabrication of local interconnects, over a substrate and directly over drain regions, source regions and gate electrodes of a plurality of transistors, the plurality of transistors separated from each other by one or more shallow trench isolation regions; forming a silicide layer in portions of the local interconnect layer by reacting the local interconnect layer with silicon of the drain regions and the source regions and with polysilicon present in the gate electrodes through a rapid thermal anneal; depositing a hard mask layer on the local interconnect layer; applying a polymer over the hard mask layer; removing the polymer from over each of the gate electrodes of the plurality of transistors by etching back the polymer, down to about a top of the gate electrodes, the gate electrodes positioned in a side-by side manner; removing the polymer from around dielectric spacers formed alongside each of the gate electrodes of the plurality of transistors through an isotropic etch, wherein the polymer remains self-aligned between the dielectric spacers of adjacent ones of said gate electrodes; removing the hard mask layer and the local interconnect layer from the dielectric spacers and the top of the gate electrodes of the plurality of transistors; and patterning and etching away portions of the local interconnect layer so that portions of the local interconnect layer remain to make electrical connection to the silicide layer of the source regions and the drain regions of the plurality of transistors. depositing a local interconnect layer of a metal, that is suitable for fabrication of local interconnects, over a substrate and directly over drain regions, source regions and gate electrodes of a plurality of transistors, the plurality of transistors separated from each other by one or more shallow trench isolation regions; forming a silicide layer in portions of the local interconnect layer by reacting the local interconnect layer with silicon of the drain regions and the source regions and with polysilicon present in the gate electrodes through a rapid thermal anneal; depositing a hard mask layer on the local interconnect layer; applying a polymer over the hard mask layer; removing the polymer from over each of the gate electrodes of the plurality of transistors by etching back the polymer, down to about a top of the gate electrodes, the gate electrodes positioned in a side-by side manner; removing the polymer from around dielectric spacers formed alongside each of the gate electrodes of the plurality of transistors through an isotropic etch, wherein the polymer remains self-aligned between the dielectric spacers of adjacent ones of said gate electrodes; removing the hard mask layer and the local interconnect layer from the dielectric spacers and the top of the gate electrodes of the plurality of transistors; and patterning and etching away portions of the local interconnect layer so that portions of the local interconnect layer remain to make electrical connection to the silicide layer of the source regions and the drain regions of the plurality of transistors.