A class D audio amplifier comprising a load driving assembly connectable to a loudspeaker load via an output terminal, wherein the load driving assembly comprises: a plurality of stacked N-channel field effect transistors (SW1, SW2, SW3, SW4) with an upper leg formed between a first DC supply voltage (V S) and the output terminal and a lower leg formed between the output terminal and a second DC supply voltage, wherein the upper leg comprises a plurality of stacked N-channel field effect transistors (SW1, SW2) and the lower leg comprises a plurality of stacked N-channel field effect transistors (SW3, SW4), the output terminal being electrically coupled between the upper and lower legs, each of the plurality of N-channel field effect transistors having a gate terminal electrically connected to respective first nodes of a first and a second charging paths (211, 209) of a gate driver (111, 113, 115, 117), each of the plurality of N-channel field effect transistors having a drain terminal electrically coupled to a second node of the first charging path to provide a first supply voltage for the power transistor, a plurality of assembly input terminals each coupled to a respective input (PWM_1, (PWM_2, PWM_3, PWM_4) of the gate driver (111, 113, 115, 117) associated to each of the plurality of N-channel field effect transistors to supply modulated input signals thereto; and each gate driver comprises: the first charging path electrically connected between the first supply voltage and the gate terminal of the N-channel field effect transistor for charging the gate terminal to a first gate voltage, the second charging path electrically connected between a second voltage supply (HVboot) and the gate terminal of the N-channel field effect transistor for charging the gate terminal from the first gate voltage to a second gate voltage larger than the first gate voltage; wherein a voltage of the second voltage supply (HVboot) is higher than a voltage of the first supply voltage. a plurality of stacked N-channel field effect transistors (SW1, SW2, SW3, SW4) with an upper leg formed between a first DC supply voltage (V S) and the output terminal and a lower leg formed between the output terminal and a second DC supply voltage, wherein the upper leg comprises a plurality of stacked N-channel field effect transistors (SW1, SW2) and the lower leg comprises a plurality of stacked N-channel field effect transistors (SW3, SW4), the output terminal being electrically coupled between the upper and lower legs, each of the plurality of N-channel field effect transistors having a gate terminal electrically connected to respective first nodes of a first and a second charging paths (211, 209) of a gate driver (111, 113, 115, 117), each of the plurality of N-channel field effect transistors having a drain terminal electrically coupled to a second node of the first charging path to provide a first supply voltage for the power transistor, a plurality of assembly input terminals each coupled to a respective input (PWM_1, (PWM_2, PWM_3, PWM_4) of the gate driver (111, 113, 115, 117) associated to each of the plurality of N-channel field effect transistors to supply modulated input signals thereto; and each gate driver comprises: the first charging path electrically connected between the first supply voltage and the gate terminal of the N-channel field effect transistor for charging the gate terminal to a first gate voltage, the second charging path electrically connected between a second voltage supply (HVboot) and the gate terminal of the N-channel field effect transistor for charging the gate terminal from the first gate voltage to a second gate voltage larger than the first gate voltage; wherein a voltage of the second voltage supply (HVboot) is higher than a voltage of the first supply voltage. the first charging path electrically connected between the first supply voltage and the gate terminal of the N-channel field effect transistor for charging the gate terminal to a first gate voltage, the second charging path electrically connected between a second voltage supply (HVboot) and the gate terminal of the N-channel field effect transistor for charging the gate terminal from the first gate voltage to a second gate voltage larger than the first gate voltage; wherein a voltage of the second voltage supply (HVboot) is higher than a voltage of the first supply voltage.