A semiconductor device of an npn-type heterostructure bipolar transistor comprising a laminate structure comprising: - a first semiconductor layer which is an InGaAs collector layer provided on one side of an InP-substrate in parallel with a surface of the substrate surface, - a p + -type second semiconductor layer which is an InGaAs base layer, - an n-type third semiconductor layer which is an InP sub-collector layer, - an n-type fourth semiconductor layer which is an InGaAsP intermediate layer, - an n-type sixth semiconductor layer which is an InP emitter layer, and - an n-type InGaAsP electric field control layer disposed between the first semiconductor layer and the fourth semiconductor layer, wherein the first semiconductor layer is disposed between the second semiconductor layer and the third semiconductor layer and has an impurity concentration lower than impurity concentrations of the second semiconductor layer and the third semiconductor layer, wherein the second semiconductor layer is far from the substrate relative to the third semiconductor, wherein the fourth semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer and has a bandgap larger than the bandgap of the first semiconductor layer, wherein the sixth semiconductor layer is adjacent to the second semiconductor opposite to the fourth semiconductor layer with respect to the second semiconductor layer, wherein an outer circumference of an emitter mesa including the sixth semiconductor layer is provided inside an outer circumference of a base mesa including the second semiconductor layer, the outer circumference of the base mesa is provided inside an outer circumference of a collector mesa including the first semiconductor layer, the n-type InGaAsP electric field control layer and the fourth semiconductor layer, and the outer circumference of the collector mesa is provided inside an outer circumference of a sub collector mesa including the third semiconductor layer, and wherein the n-type InGaAsP electric-field control layer has a thickness which is regulated to 20 to 40 nm and a doping concentration which is regulated to 2 to 5 × 10 17 /cm 3 so that each layer from a part of the second semiconductor layer to a part of the third semiconductor layer is depleted. - a first semiconductor layer which is an InGaAs collector layer provided on one side of an InP-substrate in parallel with a surface of the substrate surface, - a p + -type second semiconductor layer which is an InGaAs base layer, - an n-type third semiconductor layer which is an InP sub-collector layer, - an n-type fourth semiconductor layer which is an InGaAsP intermediate layer, - an n-type sixth semiconductor layer which is an InP emitter layer, and - an n-type InGaAsP electric field control layer disposed between the first semiconductor layer and the fourth semiconductor layer, wherein the second semiconductor layer is far from the substrate relative to the third semiconductor, wherein the fourth semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer and has a bandgap larger than the bandgap of the first semiconductor layer, wherein the sixth semiconductor layer is adjacent to the second semiconductor opposite to the fourth semiconductor layer with respect to the second semiconductor layer, wherein an outer circumference of an emitter mesa including the sixth semiconductor layer is provided inside an outer circumference of a base mesa including the second semiconductor layer, the outer circumference of the base mesa is provided inside an outer circumference of a collector mesa including the first semiconductor layer, the n-type InGaAsP electric field control layer and the fourth semiconductor layer, and the outer circumference of the collector mesa is provided inside an outer circumference of a sub collector mesa including the third semiconductor layer, and wherein the n-type InGaAsP electric-field control layer has a thickness which is regulated to 20 to 40 nm and a doping concentration which is regulated to 2 to 5 × 10 17 /cm 3 so that each layer from a part of the second semiconductor layer to a part of the third semiconductor layer is depleted.