A signal processor, comprising: a first signal processing unit and a second signal processing unit preceding the first signal processing unit, the second signal processing unit configured to provide an analog residue and an integer number to the first signal processing unit; wherein the first signal processing unit and the second signal processing unit each comprise: an analog input configured to receive an analog input signal; a node configured to sum an analog residue from a preceding signal processing unit and the analog input signal received by the analog input; a quantizer comprising an integrator and a comparator and configured to quantize the received analog input signal summed with the analog residue from the preceding signal processing unit into an integer number determined with respect to a predetermined value, and to output the integer number; wherein the integrator is configured to integrate the output of the node, and wherein the comparator is configured to determine whether the integrated analog input signal summed with the analog residue from the preceding signal processing unit is greater than or equal to the predetermined value and is configured to output the integer number based on the determination; an analog output configured to provide an analog residue, which is remaining after quantization of the received analog input signal summed with the analog residue from the preceding signal processing unit, a summer configured to sum an integer number output by the preceding signal processing unit and the outputted integer number of the quantizer, a digital-to-analog converter configured to convert the integer number to an analog value, and a subtractor configured to subtract the analog value from the analog input signal. a first signal processing unit and a second signal processing unit preceding the first signal processing unit, the second signal processing unit configured to provide an analog residue and an integer number to the first signal processing unit; wherein the first signal processing unit and the second signal processing unit each comprise: an analog input configured to receive an analog input signal; a node configured to sum an analog residue from a preceding signal processing unit and the analog input signal received by the analog input; a quantizer comprising an integrator and a comparator and configured to quantize the received analog input signal summed with the analog residue from the preceding signal processing unit into an integer number determined with respect to a predetermined value, and to output the integer number; wherein the integrator is configured to integrate the output of the node, and wherein the comparator is configured to determine whether the integrated analog input signal summed with the analog residue from the preceding signal processing unit is greater than or equal to the predetermined value and is configured to output the integer number based on the determination; an analog output configured to provide an analog residue, which is remaining after quantization of the received analog input signal summed with the analog residue from the preceding signal processing unit, a summer configured to sum an integer number output by the preceding signal processing unit and the outputted integer number of the quantizer, a digital-to-analog converter configured to convert the integer number to an analog value, and a subtractor configured to subtract the analog value from the analog input signal. an analog input configured to receive an analog input signal; a node configured to sum an analog residue from a preceding signal processing unit and the analog input signal received by the analog input; a quantizer comprising an integrator and a comparator and configured to quantize the received analog input signal summed with the analog residue from the preceding signal processing unit into an integer number determined with respect to a predetermined value, and to output the integer number; wherein the integrator is configured to integrate the output of the node, and wherein the comparator is configured to determine whether the integrated analog input signal summed with the analog residue from the preceding signal processing unit is greater than or equal to the predetermined value and is configured to output the integer number based on the determination; an analog output configured to provide an analog residue, which is remaining after quantization of the received analog input signal summed with the analog residue from the preceding signal processing unit, a summer configured to sum an integer number output by the preceding signal processing unit and the outputted integer number of the quantizer, a digital-to-analog converter configured to convert the integer number to an analog value, and a subtractor configured to subtract the analog value from the analog input signal.