A memory device comprising: a first bitline; a second bitline; a memory element disposed to be selectively and reversibly configured in a first of a plurality of different resistive states by conduction of a current in a first direction through the memory element and a second of the different resistive states by conduction of a current in a second direction through the memory element which is opposite to the first direction; the first and second bitlines being selectively electrically connected to the memory element; a first diode connected between the first bitline and a first electrode of the memory element; a second diode connected between the second bitline and the first electrode of the memory element; and a wordline connected to a second electrode of the memory element; and a write circuit configured to switch the memory element in the first of the plurality of different resistive states by biasing the first and second diodes so as to conduct current from the first bitline through the memory element to the wordline while preventing current from flowing from the second bit line to the memory element and from the memory element to the second bitline so that the memory element is not electrically connected to the second bit line and to switch memory element in the second of the plurality of different resistive states by biasing the first and second diodes to conduct current through the memory element from the wordline to the second bit line while preventing current from flowing from the memory element to the first bitline and from the first bitline to the memory element so that the memory element is not electrically connected to the first bit line. a first bitline; a second bitline; a memory element disposed to be selectively and reversibly configured in a first of a plurality of different resistive states by conduction of a current in a first direction through the memory element and a second of the different resistive states by conduction of a current in a second direction through the memory element which is opposite to the first direction; the first and second bitlines being selectively electrically connected to the memory element; a first diode connected between the first bitline and a first electrode of the memory element; a second diode connected between the second bitline and the first electrode of the memory element; and a wordline connected to a second electrode of the memory element; and a write circuit configured to switch the memory element in the first of the plurality of different resistive states by biasing the first and second diodes so as to conduct current from the first bitline through the memory element to the wordline while preventing current from flowing from the second bit line to the memory element and from the memory element to the second bitline so that the memory element is not electrically connected to the second bit line and to switch memory element in the second of the plurality of different resistive states by biasing the first and second diodes to conduct current through the memory element from the wordline to the second bit line while preventing current from flowing from the memory element to the first bitline and from the first bitline to the memory element so that the memory element is not electrically connected to the first bit line.