A device comprising: cache RAM comprising first RAM and second RAM; and caching circuitry arranged to perform caching operations in response to memory access operations, each caching operation caching a respective cacheline and corresponding tag in the cache RAM; wherein: the first RAM comprises a plurality of fields of an architecturally defined width, and the second RAM comprises a plurality of respective fields also of architecturally defined width, each field in the first RAM together with the respective field in the second RAM forming a respective entry of the cache RAM; the caching circuitry is operable to make a selection between applying a first mode and a second mode in at least one of the entries in the cache RAM; when the first mode is applied, the respective field in the first RAM is used to hold a first portion of a single cacheline in a first format, and the respective field in the second RAM is used to hold the corresponding tag of the single cacheline and a remaining portion of the single cacheline; and when the second mode is applied, the first RAM is used to hold a plural number of cachelines in a second format shorter than the first format, and the corresponding entry in the second RAM is used to hold the corresponding tags of the plural number of cachelines. cache RAM comprising first RAM and second RAM; and caching circuitry arranged to perform caching operations in response to memory access operations, each caching operation caching a respective cacheline and corresponding tag in the cache RAM; wherein: the first RAM comprises a plurality of fields of an architecturally defined width, and the second RAM comprises a plurality of respective fields also of architecturally defined width, each field in the first RAM together with the respective field in the second RAM forming a respective entry of the cache RAM; the caching circuitry is operable to make a selection between applying a first mode and a second mode in at least one of the entries in the cache RAM; when the first mode is applied, the respective field in the first RAM is used to hold a first portion of a single cacheline in a first format, and the respective field in the second RAM is used to hold the corresponding tag of the single cacheline and a remaining portion of the single cacheline; and when the second mode is applied, the first RAM is used to hold a plural number of cachelines in a second format shorter than the first format, and the corresponding entry in the second RAM is used to hold the corresponding tags of the plural number of cachelines. the first RAM comprises a plurality of fields of an architecturally defined width, and the second RAM comprises a plurality of respective fields also of architecturally defined width, each field in the first RAM together with the respective field in the second RAM forming a respective entry of the cache RAM; the caching circuitry is operable to make a selection between applying a first mode and a second mode in at least one of the entries in the cache RAM; when the first mode is applied, the respective field in the first RAM is used to hold a first portion of a single cacheline in a first format, and the respective field in the second RAM is used to hold the corresponding tag of the single cacheline and a remaining portion of the single cacheline; and when the second mode is applied, the first RAM is used to hold a plural number of cachelines in a second format shorter than the first format, and the corresponding entry in the second RAM is used to hold the corresponding tags of the plural number of cachelines.