A semiconductor structure comprising: a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, wherein the first-tier alternating stack comprises a first terrace region; memory stack structures extending through the first-tier alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film; a first retro-stepped dielectric material portion (165, 165L) comprising a compressive-stress-generating dielectric material, contacting stepped surfaces of the first terrace region, and laterally surrounding the first-tier alternating stack; a tensile-stress-generating material layer (182, 186) overlying the first retro-stepped dielectric material portion (165, 165L), laterally spaced outward from an outer periphery of a topmost layer within the first-tier alternating stack, and applying a tensile stress to the first retro-stepped dielectric material portion (165, 165L) and to the first-tier alternating stack, characterised in that, the tensile-stress-generating material layer (182, 186) is patterned; the patterned tensile-stress-generating material layer (182, 186) has continuous closed inner periphery that is defined by an opening therethrough; and a dielectric material layer (183, 165L) overlying the first-tier alternating stack, contacting the continuous closed inner periphery of the patterned tensile-stress-generating material layer (182, 186), and applying a compressive stress to the first-tier alternating stack and to the patterned tensile-stress-generating material layer (182, 186). a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, wherein the first-tier alternating stack comprises a first terrace region; memory stack structures extending through the first-tier alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film; a first retro-stepped dielectric material portion (165, 165L) comprising a compressive-stress-generating dielectric material, contacting stepped surfaces of the first terrace region, and laterally surrounding the first-tier alternating stack; a tensile-stress-generating material layer (182, 186) overlying the first retro-stepped dielectric material portion (165, 165L), laterally spaced outward from an outer periphery of a topmost layer within the first-tier alternating stack, and applying a tensile stress to the first retro-stepped dielectric material portion (165, 165L) and to the first-tier alternating stack, characterised in that, the tensile-stress-generating material layer (182, 186) is patterned; the patterned tensile-stress-generating material layer (182, 186) has continuous closed inner periphery that is defined by an opening therethrough; and a dielectric material layer (183, 165L) overlying the first-tier alternating stack, contacting the continuous closed inner periphery of the patterned tensile-stress-generating material layer (182, 186), and applying a compressive stress to the first-tier alternating stack and to the patterned tensile-stress-generating material layer (182, 186).