A method of operating a semiconductor device that is powered by a first power supply potential, the device having a sensing portion comprising a sense amplifier latch formed of cross-coupled IGFET inverters (M302, M306, M304, M308), a first said inverter (M302, M306) comprising a first IGFET and a second said inverter (M304 M308) comprising a second IGFET, the latch having a first precharging node coupled to a gate terminal of the first IGFET and a second precharging node coupled to a gate terminal of the second IGFET, the method comprising a read operation including: using the first and second nodes (N1, N2) to sense differential data signals (LIO, LlO_) received from an SRAM cell; and outputting complementary data signals (Dout, Dout_) respectively based on potentials of the first and second nodes, the method including: generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read assist signal (SENAS) having a read assist enable logic level in response to the first latched voltage signal; and altering a read operation to the static random access memory, SRAM cell in response to the at least one read assist signal (SENAS) having the read assist enable logic level as compared to when the at least one read assist signal (SENAS) has a read assist disable logic level, wherein the altering the read operation includes enabling a threshold voltage compensation circuit included in a sense amplifier circuit, the threshold compensation circuit configured to compensate for differences in threshold voltages in the first insulated gate field effect transistor, IGFET, and the second IGFET during a said read operation of data from the SRAM cell, wherein the compensation comprises, before using the latch to sense the differential data, precharging the first and second nodes (N1, N2) to the first power supply potential. the method comprising a read operation including: using the first and second nodes (N1, N2) to sense differential data signals (LIO, LlO_) received from an SRAM cell; and outputting complementary data signals (Dout, Dout_) respectively based on potentials of the first and second nodes, using the first and second nodes (N1, N2) to sense differential data signals (LIO, LlO_) received from an SRAM cell; and outputting complementary data signals (Dout, Dout_) respectively based on potentials of the first and second nodes, the method including: generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read assist signal (SENAS) having a read assist enable logic level in response to the first latched voltage signal; and altering a read operation to the static random access memory, SRAM cell in response to the at least one read assist signal (SENAS) having the read assist enable logic level as compared to when the at least one read assist signal (SENAS) has a read assist disable logic level, wherein the altering the read operation includes enabling a threshold voltage compensation circuit included in a sense amplifier circuit, the threshold compensation circuit configured to compensate for differences in threshold voltages in the first insulated gate field effect transistor, IGFET, and the second IGFET during a said read operation of data from the SRAM cell, wherein the compensation comprises, before using the latch to sense the differential data, precharging the first and second nodes (N1, N2) to the first power supply potential. generating a first voltage signal having a first logic level in response to a voltage detector circuit detecting that the first power supply potential is essentially lower than a predetermined voltage; latching the first voltage signal to provide a first latched voltage signal; generating at least one read assist signal (SENAS) having a read assist enable logic level in response to the first latched voltage signal; and altering a read operation to the static random access memory, SRAM cell in response to the at least one read assist signal (SENAS) having the read assist enable logic level as compared to when the at least one read assist signal (SENAS) has a read assist disable logic level, wherein the altering the read operation includes enabling a threshold voltage compensation circuit included in a sense amplifier circuit, the threshold compensation circuit configured to compensate for differences in threshold voltages in the first insulated gate field effect transistor, IGFET, and the second IGFET during a said read operation of data from the SRAM cell, wherein the compensation comprises, before using the latch to sense the differential data, precharging the first and second nodes (N1, N2) to the first power supply potential.