Data processing apparatus comprising: branch prediction circuitry to predict an outcome of a branch instruction, the branch prediction circuitry having a Branch Target Buffer, BTB, to store a plurality of BTB entries, each BTB entry comprising both a branch indexing address and a predicted branch target address for a branch instruction, the branch indexing address to map to a program counter of an instruction being fetched wherein a BTB hit returns a predicted branch target address corresponding to the program counter; a fetch target queue having a plurality of storage slots to receive entries corresponding to a sequence of instruction addresses, at least one of the sequence having been predicted using the branch prediction circuitry; a fetch engine to fetch and return from a memory, for execution by a processor, instructions corresponding to instruction addresses taken from a top of the fetch target queue, wherein the fetch target queue is to decouple the branch prediction circuitry from the fetch engine to allow the branch prediction circuitry to run ahead of the fetch engine; a prefetch engine to read an entry from the fetch target queue and to send a prefetch probe to the memory to determine if at least one corresponding instruction is stored in an instruction cache of the memory; and a predecoder having decode circuitry; wherein when the BTB detects a BTB miss for the program counter when attempting to populate a storage slot of the fetch target queue, the BTB is to trigger issuance of a BTB miss probe to the memory to fetch at least one instruction from the memory to resolve the BTB miss and wherein, in response to the BTB miss probe, the decode circuitry of the predecoder is to decode instructions of a cache block selected depending upon the program counter corresponding to the BTB miss, to extract at least one branch instruction and any corresponding branch target to resolve the BTB miss. branch prediction circuitry to predict an outcome of a branch instruction, the branch prediction circuitry having a Branch Target Buffer, BTB, to store a plurality of BTB entries, each BTB entry comprising both a branch indexing address and a predicted branch target address for a branch instruction, the branch indexing address to map to a program counter of an instruction being fetched wherein a BTB hit returns a predicted branch target address corresponding to the program counter; a fetch target queue having a plurality of storage slots to receive entries corresponding to a sequence of instruction addresses, at least one of the sequence having been predicted using the branch prediction circuitry; a fetch engine to fetch and return from a memory, for execution by a processor, instructions corresponding to instruction addresses taken from a top of the fetch target queue, wherein the fetch target queue is to decouple the branch prediction circuitry from the fetch engine to allow the branch prediction circuitry to run ahead of the fetch engine; a prefetch engine to read an entry from the fetch target queue and to send a prefetch probe to the memory to determine if at least one corresponding instruction is stored in an instruction cache of the memory; and a predecoder having decode circuitry; wherein when the BTB detects a BTB miss for the program counter when attempting to populate a storage slot of the fetch target queue, the BTB is to trigger issuance of a BTB miss probe to the memory to fetch at least one instruction from the memory to resolve the BTB miss and wherein, in response to the BTB miss probe, the decode circuitry of the predecoder is to decode instructions of a cache block selected depending upon the program counter corresponding to the BTB miss, to extract at least one branch instruction and any corresponding branch target to resolve the BTB miss.