An image sensor comprising a plurality of pixel circuits each comprising: a photodiode connected between ground and a floating diffusion node, a reset transistor (MRST), wherein its drain is configured to be connected to a first voltage supply and its source is connected to the floating diffusion node, a source follower transistor, wherein its drain is configured to be connected to a second voltage supply, its gate is connected to the floating diffusion node and its source is connected to a row select transistor (MSEL), and the row select transistor (MSEL) is connected between the source of the source follower transistor and a common column output, wherein each pixel circuit is configured to output an output signal corresponding to a light incident on the photodiode; and wherein each pixel circuit includes at least one additional transistor for configuring each pixel circuit to selectively output a linear integration signal or a logarithmic signal, wherein each pixel circuit further comprises a first additional bias transistor, wherein its source is connected to the second voltage supply and its drain is connected to the drain of the source follower transistor, and a second additional transistor configured to connect the drain of the bias transistor to the drain of the reset transistor (MRST), and a third additional transistor configured to connect the drain of the reset transistor (MRST) to the first power supply, and a fourth additional transistor configured to connect the drain of the reset transistor (MRST) to the gate of the reset transistor (MRST), wherein in each pixel circuit when being configured to generate a logarithmic output signal: the second additional transistor is connecting the drain of the bias transistor to the drain of the reset transistor (MRST), and the third additional transistor is open, and the fourth additional transistor is connecting the drain and gate of the reset transistor (MRST), the row select transistor (MSEL) is closed and the column output is connected to ground; and wherein each pixel circuit comprises an output (vlg_out) connected between the bias transistor and the source follower transistor. a photodiode connected between ground and a floating diffusion node, a reset transistor (MRST), wherein its drain is configured to be connected to a first voltage supply and its source is connected to the floating diffusion node, a source follower transistor, wherein its drain is configured to be connected to a second voltage supply, its gate is connected to the floating diffusion node and its source is connected to a row select transistor (MSEL), and the row select transistor (MSEL) is connected between the source of the source follower transistor and a common column output, wherein each pixel circuit is configured to output an output signal corresponding to a light incident on the photodiode; and wherein each pixel circuit includes at least one additional transistor for configuring each pixel circuit to selectively output a linear integration signal or a logarithmic signal, wherein each pixel circuit further comprises a first additional bias transistor, wherein its source is connected to the second voltage supply and its drain is connected to the drain of the source follower transistor, and a second additional transistor configured to connect the drain of the bias transistor to the drain of the reset transistor (MRST), and a third additional transistor configured to connect the drain of the reset transistor (MRST) to the first power supply, and a fourth additional transistor configured to connect the drain of the reset transistor (MRST) to the gate of the reset transistor (MRST), wherein in each pixel circuit when being configured to generate a logarithmic output signal: the second additional transistor is connecting the drain of the bias transistor to the drain of the reset transistor (MRST), and the third additional transistor is open, and the fourth additional transistor is connecting the drain and gate of the reset transistor (MRST), the row select transistor (MSEL) is closed and the column output is connected to ground; and wherein each pixel circuit comprises an output (vlg_out) connected between the bias transistor and the source follower transistor. the second additional transistor is connecting the drain of the bias transistor to the drain of the reset transistor (MRST), and the third additional transistor is open, and the fourth additional transistor is connecting the drain and gate of the reset transistor (MRST), the row select transistor (MSEL) is closed and the column output is connected to ground; and wherein each pixel circuit comprises an output (vlg_out) connected between the bias transistor and the source follower transistor.