A semiconductor structure, comprising: semiconductor stacks (M1 G, M2 G) over a substrate, wherein each of the semiconductor stacks (M1 G, M2 G) extends in a first direction, and adjacent semiconductor stacks (M1 G, M2 G) are spaced apart from each other in a second direction, which is different from the first direction, wherein each of the semiconductor stacks (M1 G, M2 G) comprises: channel layers above the substrate and spaced apart from each other in a third direction, wherein the third direction is vertical to the first direction and the second direction; and a gate structure, comprising: gate dielectric layers around the respective channel layers; and a gate electrode along sidewalls of the gate dielectric layers and a top surface of an uppermost gate dielectric layer of the gate dielectric layers, wherein a space in the third direction between the two lowermost channel layers (12-1, 12-2) of the channel layers is greater than a space in the third direction between the two uppermost channel layers (12-2, 12-3) of the channel layers; characterised in that a lowermost channel layer of the channel layers in one of the semiconductor stacks (M1 G, M2 G) includes a higher germanium content than a germanium content of the other respective channel layers (12-2, 12-3) in said semiconductor stack, wherein the channel layers in said one of the semiconductor stacks (M1 G, M2 G) comprise silicon germanium, and wherein molar ratios of silicon and germanium in each of the channel layers in said one of the semiconductor stacks (M1 G, M2 G) are different. semiconductor stacks (M1 G, M2 G) over a substrate, wherein each of the semiconductor stacks (M1 G, M2 G) extends in a first direction, and adjacent semiconductor stacks (M1 G, M2 G) are spaced apart from each other in a second direction, which is different from the first direction, wherein each of the semiconductor stacks (M1 G, M2 G) comprises: channel layers above the substrate and spaced apart from each other in a third direction, wherein the third direction is vertical to the first direction and the second direction; and a gate structure, comprising: gate dielectric layers around the respective channel layers; and a gate electrode along sidewalls of the gate dielectric layers and a top surface of an uppermost gate dielectric layer of the gate dielectric layers, wherein a space in the third direction between the two lowermost channel layers (12-1, 12-2) of the channel layers is greater than a space in the third direction between the two uppermost channel layers (12-2, 12-3) of the channel layers; channel layers above the substrate and spaced apart from each other in a third direction, wherein the third direction is vertical to the first direction and the second direction; and a gate structure, comprising: gate dielectric layers around the respective channel layers; and a gate electrode along sidewalls of the gate dielectric layers and a top surface of an uppermost gate dielectric layer of the gate dielectric layers, wherein a space in the third direction between the two lowermost channel layers (12-1, 12-2) of the channel layers is greater than a space in the third direction between the two uppermost channel layers (12-2, 12-3) of the channel layers; gate dielectric layers around the respective channel layers; and a gate electrode along sidewalls of the gate dielectric layers and a top surface of an uppermost gate dielectric layer of the gate dielectric layers, wherein a space in the third direction between the two lowermost channel layers (12-1, 12-2) of the channel layers is greater than a space in the third direction between the two uppermost channel layers (12-2, 12-3) of the channel layers; characterised in that a lowermost channel layer of the channel layers in one of the semiconductor stacks (M1 G, M2 G) includes a higher germanium content than a germanium content of the other respective channel layers (12-2, 12-3) in said semiconductor stack, wherein the channel layers in said one of the semiconductor stacks (M1 G, M2 G) comprise silicon germanium, and wherein molar ratios of silicon and germanium in each of the channel layers in said one of the semiconductor stacks (M1 G, M2 G) are different.