A memory device, comprising: a current injector having a plurality of injection outputs, each of the plurality of injection outputs providing the same amount of current; a plurality of clamps (20, 30, 40, 50), each clamp connected to a different one of the plurality of injection outputs; two or more reference cells (120, 130, 140), wherein each reference cell is connected to a different one of the plurality of clamps and each of the two or more reference cells draws a different amount of current; a selected memory cell connected to one of the plurality of clamps different from the clamps to which the one or more reference cells are connected, wherein the selected memory cell is configured to draw an amount of current indicative of a value stored in the selected memory cell; and a comparator characterised by comprising: a plurality of NMOS transistors (71, 72, 73, 74), wherein the gate of each of the plurality of NMOS transistors is connected to a node between the injection output and the clamp connected to the selected memory cell, the source of each of the plurality of NMOS transistors is coupled to ground, the drain of one of the plurality of NMOS transistors is coupled to the node between the injection output and the clamp connected to the selected memory cell, and the drains of the other ones of the plurality of NMOS transistors is each coupled to a different one of the nodes between the injection outputs and the clamps connected to the two or more reference cells; a plurality of equalization blocks (75, 76, 77), an input of each of the plurality of equalization blocks being coupled to a different one of the nodes between the injection outputs and the clamps connected to the two or more reference cells; and a plurality of DC shunt elimination circuits (78, 79, 81), wherein an output of each of the plurality of equalization blocks is coupled to an input of a different one of the DC shunt elimination circuits, and the output (80, 90, 100) of the DC shunt elimination circuits are for indicating a value stored in the selected memory cell. a current injector having a plurality of injection outputs, each of the plurality of injection outputs providing the same amount of current; a plurality of clamps (20, 30, 40, 50), each clamp connected to a different one of the plurality of injection outputs; two or more reference cells (120, 130, 140), wherein each reference cell is connected to a different one of the plurality of clamps and each of the two or more reference cells draws a different amount of current; a selected memory cell connected to one of the plurality of clamps different from the clamps to which the one or more reference cells are connected, wherein the selected memory cell is configured to draw an amount of current indicative of a value stored in the selected memory cell; and a comparator characterised by comprising: a plurality of NMOS transistors (71, 72, 73, 74), wherein the gate of each of the plurality of NMOS transistors is connected to a node between the injection output and the clamp connected to the selected memory cell, the source of each of the plurality of NMOS transistors is coupled to ground, the drain of one of the plurality of NMOS transistors is coupled to the node between the injection output and the clamp connected to the selected memory cell, and the drains of the other ones of the plurality of NMOS transistors is each coupled to a different one of the nodes between the injection outputs and the clamps connected to the two or more reference cells; a plurality of equalization blocks (75, 76, 77), an input of each of the plurality of equalization blocks being coupled to a different one of the nodes between the injection outputs and the clamps connected to the two or more reference cells; and a plurality of DC shunt elimination circuits (78, 79, 81), wherein an output of each of the plurality of equalization blocks is coupled to an input of a different one of the DC shunt elimination circuits, and the output (80, 90, 100) of the DC shunt elimination circuits are for indicating a value stored in the selected memory cell. a plurality of NMOS transistors (71, 72, 73, 74), wherein the gate of each of the plurality of NMOS transistors is connected to a node between the injection output and the clamp connected to the selected memory cell, the source of each of the plurality of NMOS transistors is coupled to ground, the drain of one of the plurality of NMOS transistors is coupled to the node between the injection output and the clamp connected to the selected memory cell, and the drains of the other ones of the plurality of NMOS transistors is each coupled to a different one of the nodes between the injection outputs and the clamps connected to the two or more reference cells; a plurality of equalization blocks (75, 76, 77), an input of each of the plurality of equalization blocks being coupled to a different one of the nodes between the injection outputs and the clamps connected to the two or more reference cells; and a plurality of DC shunt elimination circuits (78, 79, 81), wherein an output of each of the plurality of equalization blocks is coupled to an input of a different one of the DC shunt elimination circuits, and the output (80, 90, 100) of the DC shunt elimination circuits are for indicating a value stored in the selected memory cell.