A neural network unit, comprising: a register programmable with a control value; and a plurality of neural processing units, each comprising: an arithmetic logic unit that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results; an accumulator into which the ALU accumulates the sequence of results as an accumulated value; and an activation function unit, comprising: a first module that performs a first activation function on the accumulated value to generate a first output, the first activation function operating to non-linearly normalize the accumulated value to generate the first output within a first expected range; a second module that performs a second activation function on the accumulated value to generate a second output, the first activation function is distinct from the second activation function, and the second activation function operates to effectively divide the accumulated value by a divisor; and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register; wherein the multiplexer also receives the accumulated value and selects one of: the two outputs and multiple portions of the accumulated value, wherein the accumulated value is divided into non-overlapping portions each having a size of a specified size of the operands to produce the multiple portions of the accumulated value, and wherein the specified size of the operands is less than a size, in bits, of the accumulated value. a register programmable with a control value; and a plurality of neural processing units, each comprising: an arithmetic logic unit that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results; an accumulator into which the ALU accumulates the sequence of results as an accumulated value; and an activation function unit, comprising: a first module that performs a first activation function on the accumulated value to generate a first output, the first activation function operating to non-linearly normalize the accumulated value to generate the first output within a first expected range; a second module that performs a second activation function on the accumulated value to generate a second output, the first activation function is distinct from the second activation function, and the second activation function operates to effectively divide the accumulated value by a divisor; and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register; wherein the multiplexer also receives the accumulated value and selects one of: the two outputs and multiple portions of the accumulated value, wherein the accumulated value is divided into non-overlapping portions each having a size of a specified size of the operands to produce the multiple portions of the accumulated value, and wherein the specified size of the operands is less than a size, in bits, of the accumulated value. an arithmetic logic unit that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results; an accumulator into which the ALU accumulates the sequence of results as an accumulated value; and an activation function unit, comprising: a first module that performs a first activation function on the accumulated value to generate a first output, the first activation function operating to non-linearly normalize the accumulated value to generate the first output within a first expected range; a second module that performs a second activation function on the accumulated value to generate a second output, the first activation function is distinct from the second activation function, and the second activation function operates to effectively divide the accumulated value by a divisor; and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register; wherein the multiplexer also receives the accumulated value and selects one of: the two outputs and multiple portions of the accumulated value, wherein the accumulated value is divided into non-overlapping portions each having a size of a specified size of the operands to produce the multiple portions of the accumulated value, and wherein the specified size of the operands is less than a size, in bits, of the accumulated value. a first module that performs a first activation function on the accumulated value to generate a first output, the first activation function operating to non-linearly normalize the accumulated value to generate the first output within a first expected range; a second module that performs a second activation function on the accumulated value to generate a second output, the first activation function is distinct from the second activation function, and the second activation function operates to effectively divide the accumulated value by a divisor; and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register; wherein the multiplexer also receives the accumulated value and selects one of: the two outputs and multiple portions of the accumulated value, wherein the accumulated value is divided into non-overlapping portions each having a size of a specified size of the operands to produce the multiple portions of the accumulated value, and wherein the specified size of the operands is less than a size, in bits, of the accumulated value.