A detection system for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal, characterized by comprising; - at least one pseudorandom bit sequence generator for generatingan n-bit wide pseudorandom bit sequence using said PLL reference clock signal; - at least one first shift register for sampling the generated n-bit wide pseudorandom bit sequence by said PLL reference clock signal; at least one second shift register for sampling the generated n-bit wide pseudorandom bit sequence by said PLL feedback clock signal; at least one third shift register for sampling the generated n-bit wide pseudorandom bit sequence by the inverse of said PLL feedback clock signal wherein depths of first shift register, second shift register and third shift register are equal, - at least one first synchronizer for re-sampling and re-synchronizing output of first shift register with the PLL reference clock signal; - at least one second synchronizer for re-sampling and -re-synchronizing output of second shift register with the PLL reference clock signal; - at least one third synchronizer for re-sampling and re-synchronizing output of third shift register with the PLL reference clock signal; - at least one first comparator for bit-wise comparing output of the first synchronizer with the output of the second synchronizer; - at least one second comparator for bit-wise comparing output of the first synchronizer with the output of the third synchronizer; - at least one alarm control unit for generating a flag signal if said first comparator and second comparator indicates that output of the first synchronizer is not a replica of output of the second synchronizer or output of the third synchronizer. - at least one pseudorandom bit sequence generator for generatingan n-bit wide pseudorandom bit sequence using said PLL reference clock signal; - at least one first shift register for sampling the generated n-bit wide pseudorandom bit sequence by said PLL reference clock signal; at least one second shift register for sampling the generated n-bit wide pseudorandom bit sequence by said PLL feedback clock signal; at least one third shift register for sampling the generated n-bit wide pseudorandom bit sequence by the inverse of said PLL feedback clock signal wherein depths of first shift register, second shift register and third shift register are equal, - at least one first synchronizer for re-sampling and re-synchronizing output of first shift register with the PLL reference clock signal; - at least one second synchronizer for re-sampling and -re-synchronizing output of second shift register with the PLL reference clock signal; - at least one third synchronizer for re-sampling and re-synchronizing output of third shift register with the PLL reference clock signal; - at least one first comparator for bit-wise comparing output of the first synchronizer with the output of the second synchronizer; - at least one second comparator for bit-wise comparing output of the first synchronizer with the output of the third synchronizer; - at least one alarm control unit for generating a flag signal if said first comparator and second comparator indicates that output of the first synchronizer is not a replica of output of the second synchronizer or output of the third synchronizer.