A transistor device comprising: - A III-nitride stack, comprising at least two layers (7,8) with a heterojunction therebetween, so that a 2DEG layer may be formed in one of said two layers, said III-nitride stack having a front side surface and a back side surface, - On the front side surface of said III-nitride stack: a set of a source electrode, a gate electrode and a drain electrode, the gate electrode being located in between the source and drain electrodes, - On said III-nitride stack and on said source, gate and drain electrodes: an insulation layer, - Attached to said insulation layer: a carrier substrate, - On the back side surface of said III-nitride stack, for said set of source, gate and drain electrodes: an electrically conductive plate that is electrically connected to the source electrode, said plate covering at least an area of said back side surface that is directly facing an area, said latter area being situated between the gate and the drain electrodes and directly adjacent to the gate electrode, - On areas of said back side surface of the III-nitride stack not covered by said plate, a backside passivation layer, - Means for connecting said source, gate and drain electrodes (4,6,5) to external contact terminals, wherein said electrically conductive plate is covering an area of said back side surface that is directly facing an area consisting of the source electrode, the area between the source and the gate electrodes, the gate electrode, and said area between the gate and the drain electrodes and directly adjacent to the gate electrode, and wherein said electrically conductive plate is not covering the area corresponding to the drain electrode, and wherein said plate is on and in contact with the back side surface of said III-nitride stack or wherein said plate is on and in contact with a passivation layer which covers the totality of said back side surface, the passivation layer being on and in contact with said back side surface. - A III-nitride stack, comprising at least two layers (7,8) with a heterojunction therebetween, so that a 2DEG layer may be formed in one of said two layers, said III-nitride stack having a front side surface and a back side surface, - On the front side surface of said III-nitride stack: a set of a source electrode, a gate electrode and a drain electrode, the gate electrode being located in between the source and drain electrodes, - On said III-nitride stack and on said source, gate and drain electrodes: an insulation layer, - Attached to said insulation layer: a carrier substrate, - On the back side surface of said III-nitride stack, for said set of source, gate and drain electrodes: an electrically conductive plate that is electrically connected to the source electrode, said plate covering at least an area of said back side surface that is directly facing an area, said latter area being situated between the gate and the drain electrodes and directly adjacent to the gate electrode, - On areas of said back side surface of the III-nitride stack not covered by said plate, a backside passivation layer, - Means for connecting said source, gate and drain electrodes (4,6,5) to external contact terminals,