A microprocessor, comprising: a plurality of memories, each configured to hold microcode instructions; wherein at least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions; wherein at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions, wherein M and N are integers greater than zero and N is greater than M; and a decompression unit, configured to decompress the compressed microcode instructions into the uncompressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed; wherein at least one of the plurality of memories is writable and is a patch microcode memory configured to provide words of patch microcode instructions for patching one or more of the microcode instructions of other of the plurality of memories; wherein the patch microcode memory is one of the at least a second of the plurality of memories configured to provide words of uncompressed microcode instructions; and wherein the other of the plurality of memories is one of the at least a first of the plurality of memories configured to provide compressed microcode instructions; characterized in that: to decompress the M-bit wide word to generate an N-bit wide word, the decompression unit is configured to: output unique L-bit values in response to unique values included in a predetermined K bits of the M-bit wide word according to a predetermined mapping, wherein K is an integer greater than zero and less than M and L is an integer greater than zero and less than N; and pass through the remaining M minus K bits of the M-bit wide word as the remaining N minus L bits of the N-bit wide word: wherein the passed through M minus K bits comprise an immediate value field of the compressed microcode instruction. a plurality of memories, each configured to hold microcode instructions; wherein at least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions; wherein at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions, wherein M and N are integers greater than zero and N is greater than M; and a decompression unit, configured to decompress the compressed microcode instructions into the uncompressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed; wherein at least one of the plurality of memories is writable and is a patch microcode memory configured to provide words of patch microcode instructions for patching one or more of the microcode instructions of other of the plurality of memories; wherein the patch microcode memory is one of the at least a second of the plurality of memories configured to provide words of uncompressed microcode instructions; and wherein the other of the plurality of memories is one of the at least a first of the plurality of memories configured to provide compressed microcode instructions; to decompress the M-bit wide word to generate an N-bit wide word, the decompression unit is configured to: output unique L-bit values in response to unique values included in a predetermined K bits of the M-bit wide word according to a predetermined mapping, wherein K is an integer greater than zero and less than M and L is an integer greater than zero and less than N; and pass through the remaining M minus K bits of the M-bit wide word as the remaining N minus L bits of the N-bit wide word: output unique L-bit values in response to unique values included in a predetermined K bits of the M-bit wide word according to a predetermined mapping, wherein K is an integer greater than zero and less than M and L is an integer greater than zero and less than N; and pass through the remaining M minus K bits of the M-bit wide word as the remaining N minus L bits of the N-bit wide word: wherein the passed through M minus K bits comprise an immediate value field of the compressed microcode instruction.