An integrated circuit structure, comprising: a fin comprising semiconductor material; a source or drain region in the fin, the source or drain region comprising epitaxial silicon, and the source or drain region having a first source or drain interface with the fin and a second source or drain interface with the fin, the second source or drain interface with the fin opposite the first source or drain interface with the fin; a contact member on the source or drain region, the contact member having a top surface co-planar with a top of the fin, and the contact member having a curved bottom surface; a conductive interconnect on the contact member, the conductive interconnect having a first side and a second side, the second side opposite the first side; a first dielectric layer having a planar interface with the first side of the conductive interconnect, the first dielectric layer having a first composition, and the first dielectric layer having an upper surface; a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having a second composition different than the first composition, and the second dielectric layer having an upper surface, wherein the first source or drain interface with the fin is laterally between the conductive interconnect and the vertical interface of the first and second dielectric layers; a first gate electrode over the fin, the first gate electrode having an upper surface co-planar with the upper surface of the first dielectric layer and co-planar with the upper surface of the second dielectric layer, wherein the second dielectric layer is between the first gate electrode and the first dielectric layer; a third dielectric layer having a planar interface with the second side of the conductive interconnect, the third dielectric layer having the first composition, and the third dielectric layer having an upper surface; a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having the second composition, and the fourth dielectric layer having an upper surface, wherein the second source or drain interface with the fin is laterally between the conductive interconnect and the vertical interface of the third and fourth dielectric layers; and a second gate electrode over the fin, the second gate electrode having an upper surface co-planar with the upper surface of the third dielectric layer and co-planar with the upper surface of the fourth dielectric layer, wherein the fourth dielectric layer is between the second gate electrode and the third dielectric layer; and wherein the contact member having an interface with the source or drain region in the fin situated laterally between the conductive interconnect and the vertical interface of the first and second dielectric layers. a fin comprising semiconductor material; a source or drain region in the fin, the source or drain region comprising epitaxial silicon, and the source or drain region having a first source or drain interface with the fin and a second source or drain interface with the fin, the second source or drain interface with the fin opposite the first source or drain interface with the fin; a contact member on the source or drain region, the contact member having a top surface co-planar with a top of the fin, and the contact member having a curved bottom surface; a conductive interconnect on the contact member, the conductive interconnect having a first side and a second side, the second side opposite the first side; a first dielectric layer having a planar interface with the first side of the conductive interconnect, the first dielectric layer having a first composition, and the first dielectric layer having an upper surface; a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having a second composition different than the first composition, and the second dielectric layer having an upper surface, wherein the first source or drain interface with the fin is laterally between the conductive interconnect and the vertical interface of the first and second dielectric layers; a first gate electrode over the fin, the first gate electrode having an upper surface co-planar with the upper surface of the first dielectric layer and co-planar with the upper surface of the second dielectric layer, wherein the second dielectric layer is between the first gate electrode and the first dielectric layer; a third dielectric layer having a planar interface with the second side of the conductive interconnect, the third dielectric layer having the first composition, and the third dielectric layer having an upper surface; a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having the second composition, and the fourth dielectric layer having an upper surface, wherein the second source or drain interface with the fin is laterally between the conductive interconnect and the vertical interface of the third and fourth dielectric layers; and a second gate electrode over the fin, the second gate electrode having an upper surface co-planar with the upper surface of the third dielectric layer and co-planar with the upper surface of the fourth dielectric layer, wherein the fourth dielectric layer is between the second gate electrode and the third dielectric layer; and wherein the contact member having an interface with the source or drain region in the fin situated laterally between the conductive interconnect and the vertical interface of the first and second dielectric layers.