A processor having a plurality of cores, including a core that, in response to an instruction having a first operand including a plurality of pairs of 16-bit floating point data elements, a second operand including a plurality of pairs of 16-bit floating point data elements, and a third operand including a plurality of floating point data elements, is configured to: multiply the plurality of pairs of 16-bit floating point data elements from the first operand with corresponding ones of the plurality of pairs of 16-bit floating point data elements from the second operand to generate a plurality of corresponding products, wherein a 16-bit floating point data element from the first operand and a 16-bit floating point data element from the second operand each have a sign bit, an 8-bit exponent, and seven explicit mantissa bits; generate a plurality of result floating point data elements by accumulation of the plurality of products with corresponding ones from the plurality of floating point data elements from the third operand; and store the plurality of result floating point data elements, wherein the core is configured to multiply the plurality of pairs of 16-bit floating point data elements from the first operand with the corresponding ones of the plurality of pairs of 16-bit floating point data elements from the second operand with infinite precision without saturation, wherein the core is configured to saturate only the result floating point data elements to zero, wherein each pair of 16-bit floating point data elements from the first operand make a 32-bit element of the first operand and each pair of 16-bit floating point data elements from the second operand make a 32-bit element of the second operand, and wherein the first, second and third operands are balanced in size, each having 32-bit elements. multiply the plurality of pairs of 16-bit floating point data elements from the first operand with corresponding ones of the plurality of pairs of 16-bit floating point data elements from the second operand to generate a plurality of corresponding products, wherein a 16-bit floating point data element from the first operand and a 16-bit floating point data element from the second operand each have a sign bit, an 8-bit exponent, and seven explicit mantissa bits; generate a plurality of result floating point data elements by accumulation of the plurality of products with corresponding ones from the plurality of floating point data elements from the third operand; and store the plurality of result floating point data elements, wherein the core is configured to multiply the plurality of pairs of 16-bit floating point data elements from the first operand with the corresponding ones of the plurality of pairs of 16-bit floating point data elements from the second operand with infinite precision without saturation, wherein the core is configured to saturate only the result floating point data elements to zero, wherein each pair of 16-bit floating point data elements from the first operand make a 32-bit element of the first operand and each pair of 16-bit floating point data elements from the second operand make a 32-bit element of the second operand, and wherein the first, second and third operands are balanced in size, each having 32-bit elements.