A method for operating a memory device, comprising: performing a full programming operation involving a set of memory cells, the full programming operation programs memory cells using an initial verify voltage (VvA, VvB, VvC) of one target data state (A, B, C); the method characterised by further comprising the steps of: after completion of the full programming operation, making a determination of whether a criterion is met for checking a data retention of the set of memory cells; in response to the determination that the criterion is met, performing sensing operations for memory cells of the one target data state to identify, in the set of memory cells, a plurality of subsets of memory cells comprising first (Asub1, Bsub1, Csub1), second (Asub2, Bsub2, Csub2) and third (Bsub3, Csub3) subsets of memory cells, the first subset of memory cells is in a first threshold voltage range (Vth>VrC1; VrB1<Vth<VrB/C; VrA1<Vth<VrA/B) which encompasses the initial verify voltage (VvC), the second subset of memory cells is in a second threshold voltage range (VrC2<Vth<VrC1; VrB2<Vth<VrB1; VrE/A<Vth<VrA1) below the first threshold voltage range, and the third subset of memory cells is in a third threshold voltage range (VrB/C<Vth<VrC2; VrA/B<Vth<VrB2; Vth<VrE/A) below the second threshold voltage range; and performing refresh programming for the second subset of memory cells and refresh programming for the third subset of memory cells but not for the first subset of memory cells, wherein a threshold voltage upshift (VvC3-VrB/C; VvB3-VrA/B) of the third subset of memory cells due to the refresh programming for the third subset of memory cells is larger than a threshold voltage upshift (VvC2-VrC2; VvB2-VrB2) of the second subset of memory cells due to the refresh programming for the second subset of memory cells. performing a full programming operation involving a set of memory cells, the full programming operation programs memory cells using an initial verify voltage (VvA, VvB, VvC) of one target data state (A, B, C); the method characterised by further comprising the steps of: after completion of the full programming operation, making a determination of whether a criterion is met for checking a data retention of the set of memory cells; in response to the determination that the criterion is met, performing sensing operations for memory cells of the one target data state to identify, in the set of memory cells, a plurality of subsets of memory cells comprising first (Asub1, Bsub1, Csub1), second (Asub2, Bsub2, Csub2) and third (Bsub3, Csub3) subsets of memory cells, the first subset of memory cells is in a first threshold voltage range (Vth>VrC1; VrB1<Vth<VrB/C; VrA1<Vth<VrA/B) which encompasses the initial verify voltage (VvC), the second subset of memory cells is in a second threshold voltage range (VrC2<Vth<VrC1; VrB2<Vth<VrB1; VrE/A<Vth<VrA1) below the first threshold voltage range, and the third subset of memory cells is in a third threshold voltage range (VrB/C<Vth<VrC2; VrA/B<Vth<VrB2; Vth<VrE/A) below the second threshold voltage range; and performing refresh programming for the second subset of memory cells and refresh programming for the third subset of memory cells but not for the first subset of memory cells, wherein a threshold voltage upshift (VvC3-VrB/C; VvB3-VrA/B) of the third subset of memory cells due to the refresh programming for the third subset of memory cells is larger than a threshold voltage upshift (VvC2-VrC2; VvB2-VrB2) of the second subset of memory cells due to the refresh programming for the second subset of memory cells. after completion of the full programming operation, making a determination of whether a criterion is met for checking a data retention of the set of memory cells; in response to the determination that the criterion is met, performing sensing operations for memory cells of the one target data state to identify, in the set of memory cells, a plurality of subsets of memory cells comprising first (Asub1, Bsub1, Csub1), second (Asub2, Bsub2, Csub2) and third (Bsub3, Csub3) subsets of memory cells, the first subset of memory cells is in a first threshold voltage range (Vth>VrC1; VrB1<Vth<VrB/C; VrA1<Vth<VrA/B) which encompasses the initial verify voltage (VvC), the second subset of memory cells is in a second threshold voltage range (VrC2<Vth<VrC1; VrB2<Vth<VrB1; VrE/A<Vth<VrA1) below the first threshold voltage range, and the third subset of memory cells is in a third threshold voltage range (VrB/C<Vth<VrC2; VrA/B<Vth<VrB2; Vth<VrE/A) below the second threshold voltage range; and performing refresh programming for the second subset of memory cells and refresh programming for the third subset of memory cells but not for the first subset of memory cells, wherein a threshold voltage upshift (VvC3-VrB/C; VvB3-VrA/B) of the third subset of memory cells due to the refresh programming for the third subset of memory cells is larger than a threshold voltage upshift (VvC2-VrC2; VvB2-VrB2) of the second subset of memory cells due to the refresh programming for the second subset of memory cells.