A multi-channel demodulator comprising: a data buffer configured to store channel data corresponding to a plurality of channels; and a demodulation engine configured to provide demodulation processing on data corresponding to a first channel of the plurality of channels, the demodulation engine further configured to store the data corresponding to the first channel into the data buffer and load data corresponding to a second channel of the plurality of channels from the data buffer for demodulation processing; a parallel low pass FIR filter configured to process multiple identical input data streams in parallel comprising: a plurality of multipliers configured to respectively receive a corresponding one of the multiple input data streams and a corresponding one of a plurality of coefficients, the multiple input data streams generated from channel data from a single channel of the plurality of channels, the size of each multiplier i is a x b i wherein a is the bit width of its input data stream and b i is the bit width of its corresponding coefficient, b i being different from the bit width of any other one of the coefficients and b i ≤ a; and a plurality of adders configured to sum up the respective output of the plurality of multipliers to generate an output data stream; wherein the parallel low pass FIR filter is deployed within one or more components of the demodulation engine. a data buffer configured to store channel data corresponding to a plurality of channels; and a demodulation engine configured to provide demodulation processing on data corresponding to a first channel of the plurality of channels, the demodulation engine further configured to store the data corresponding to the first channel into the data buffer and load data corresponding to a second channel of the plurality of channels from the data buffer for demodulation processing; a parallel low pass FIR filter configured to process multiple identical input data streams in parallel comprising: a plurality of multipliers configured to respectively receive a corresponding one of the multiple input data streams and a corresponding one of a plurality of coefficients, the multiple input data streams generated from channel data from a single channel of the plurality of channels, the size of each multiplier i is a x b i wherein a is the bit width of its input data stream and b i is the bit width of its corresponding coefficient, b i being different from the bit width of any other one of the coefficients and b i ≤ a; and a plurality of adders configured to sum up the respective output of the plurality of multipliers to generate an output data stream; a plurality of multipliers configured to respectively receive a corresponding one of the multiple input data streams and a corresponding one of a plurality of coefficients, the multiple input data streams generated from channel data from a single channel of the plurality of channels, the size of each multiplier i is a x b i wherein a is the bit width of its input data stream and b i is the bit width of its corresponding coefficient, b i being different from the bit width of any other one of the coefficients and b i ≤ a; and a plurality of adders configured to sum up the respective output of the plurality of multipliers to generate an output data stream; wherein the parallel low pass FIR filter is deployed within one or more components of the demodulation engine.