A stackup of a plurality of display pixels, the stackup comprising: a first layer of conductive material including gate lines; a second layer of conductive material including data lines; a third layer of conductive material including: a first, second and third region (1301, 1303) each having circuit elements of the display pixels (515, 517), the third region disposed between the first and second regions, wherein circuit elements of the display pixels in the first region are electrically connected together in a first direction by a first plurality of first line portions, and the circuit elements of the display pixels in the first region are electrically connected together in a second direction transverse to the first direction by a first plurality of second line portions; wherein circuit elements of the display pixels in the second region are electrically connected together in the first direction by a second plurality of the first line portions and the circuit elements of the display pixels in the second region are electrically connected together in the second direction by a second plurality of the second line portions; and wherein at least one conductive pathway (613, 615) connects circuit elements of the first region to circuit elements of the second region wherein the at least one conductive pathway electrically bypasses circuit elements of the third region. a first layer of conductive material including gate lines; a second layer of conductive material including data lines; a third layer of conductive material including: a first, second and third region (1301, 1303) each having circuit elements of the display pixels (515, 517), the third region disposed between the first and second regions, wherein circuit elements of the display pixels in the first region are electrically connected together in a first direction by a first plurality of first line portions, and the circuit elements of the display pixels in the first region are electrically connected together in a second direction transverse to the first direction by a first plurality of second line portions; wherein circuit elements of the display pixels in the second region are electrically connected together in the first direction by a second plurality of the first line portions and the circuit elements of the display pixels in the second region are electrically connected together in the second direction by a second plurality of the second line portions; and wherein at least one conductive pathway (613, 615) connects circuit elements of the first region to circuit elements of the second region wherein the at least one conductive pathway electrically bypasses circuit elements of the third region. a first, second and third region (1301, 1303) each having circuit elements of the display pixels (515, 517), the third region disposed between the first and second regions, wherein circuit elements of the display pixels in the first region are electrically connected together in a first direction by a first plurality of first line portions, and the circuit elements of the display pixels in the first region are electrically connected together in a second direction transverse to the first direction by a first plurality of second line portions; wherein circuit elements of the display pixels in the second region are electrically connected together in the first direction by a second plurality of the first line portions and the circuit elements of the display pixels in the second region are electrically connected together in the second direction by a second plurality of the second line portions; and wherein at least one conductive pathway (613, 615) connects circuit elements of the first region to circuit elements of the second region wherein the at least one conductive pathway electrically bypasses circuit elements of the third region.