An apparatus for processing data comprising: a first parallel machine (100, 302, 402, 502, 602, 702, 800) implemented with a first set of programmable hardware elements and having a first data input port (110, 302A, 402A, 502A, 602A, 702A, 809) and a first output port (114, 302C, 402C, 502C, 602C, 702C, 813), the first parallel machine configured to: receive first data at the first data input port; and output second data at the first output port based on whether a first pattern is recognized in the first data; and a second parallel machine (100, 304, 404, 504, 604, 704, 800) implemented with a second set of programmable hardware elements and having a second data input port (110, 304A, 404A, 504A, 604A, 704A, 809) and a second output port (114, 304C, 404C, 504C, 604C, 704C, 813), wherein the second data input port is coupled to the first output port of the first parallel machine, the second parallel machine configured to: receive the second data at the second data input port; and output an indication of whether a second pattern is recognized in the second data at the second output port wherein the second pattern is a combination of the first patterns identified by the first parallel machine; wherein the first set of programmable hardware elements and the second set of programmable hardware elements are state machine elements, a state machine element comprising a plurality of memory cells and a detect circuit, the memory cells in the first set of programmable elements configured to receive the first data and the memory cells in the second set of programmable elements configured to receive the second data, the outputs from the memory cells in a state machine element configured to be sensed by the detect circuit, wherein an active programmable element in the first parallel state machine is adapted to react to first data and activate a downstream programmable element in the first parallel state machine when the first data matches the programmable setting of the said active programmable element by setting the detect circuit of the downstream programmable element to an active state, and wherein an active programmable element in the second parallel state machine is adapted to react to second data and activate a downstream programmable element in the second parallel state machine when the second data matches the programmable setting of the said active programmable element, by setting the detect circuit of the downstream programmable element to an active state. a first parallel machine (100, 302, 402, 502, 602, 702, 800) implemented with a first set of programmable hardware elements and having a first data input port (110, 302A, 402A, 502A, 602A, 702A, 809) and a first output port (114, 302C, 402C, 502C, 602C, 702C, 813), the first parallel machine configured to: receive first data at the first data input port; and output second data at the first output port based on whether a first pattern is recognized in the first data; and receive first data at the first data input port; and output second data at the first output port based on whether a first pattern is recognized in the first data; and a second parallel machine (100, 304, 404, 504, 604, 704, 800) implemented with a second set of programmable hardware elements and having a second data input port (110, 304A, 404A, 504A, 604A, 704A, 809) and a second output port (114, 304C, 404C, 504C, 604C, 704C, 813), wherein the second data input port is coupled to the first output port of the first parallel machine, the second parallel machine configured to: receive the second data at the second data input port; and output an indication of whether a second pattern is recognized in the second data at the second output port wherein the second pattern is a combination of the first patterns identified by the first parallel machine; receive the second data at the second data input port; and output an indication of whether a second pattern is recognized in the second data at the second output port wherein the second pattern is a combination of the first patterns identified by the first parallel machine; wherein the first set of programmable hardware elements and the second set of programmable hardware elements are state machine elements, a state machine element comprising a plurality of memory cells and a detect circuit, the memory cells in the first set of programmable elements configured to receive the first data and the memory cells in the second set of programmable elements configured to receive the second data, the outputs from the memory cells in a state machine element configured to be sensed by the detect circuit, wherein an active programmable element in the first parallel state machine is adapted to react to first data and activate a downstream programmable element in the first parallel state machine when the first data matches the programmable setting of the said active programmable element by setting the detect circuit of the downstream programmable element to an active state, and wherein an active programmable element in the second parallel state machine is adapted to react to second data and activate a downstream programmable element in the second parallel state machine when the second data matches the programmable setting of the said active programmable element, by setting the detect circuit of the downstream programmable element to an active state.