An array of memory cells (200, 301-303, 401, 402, 501, 502, 601, 602) on an integrated circuit device, comprising: a plurality of memory cells (200, 301-303, 401, 402, 501, 502, 601, 602) arranged in at least one column, wherein: each of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602) comprises a plurality of transistors forming two complementary memory nodes (101, 102), one of said complementary memory nodes (101, 102) storing a value and another of said complementary memory nodes (101, 102) storing a complement of said value; each respective one of said complementary memory nodes (101, 102) is connected to a respective pair of pull-up or pull-down transistors (111, 112; 121, 122; 211, 212; 221, 222; 411, 412; 421, 422), said respective pair of pull-up or pull-down transistors (111, 112; 121, 122; 211, 212; 221, 222; 411, 412; 421, 422) being connected in series and having a respective shared node (231, 232) therebetween; characterized in that for a particular one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602), one of said respective shared nodes associated with one of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602), and another of said respective shared nodes associated with another of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a third one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602). a plurality of memory cells (200, 301-303, 401, 402, 501, 502, 601, 602) arranged in at least one column, wherein: each of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602) comprises a plurality of transistors forming two complementary memory nodes (101, 102), one of said complementary memory nodes (101, 102) storing a value and another of said complementary memory nodes (101, 102) storing a complement of said value; each respective one of said complementary memory nodes (101, 102) is connected to a respective pair of pull-up or pull-down transistors (111, 112; 121, 122; 211, 212; 221, 222; 411, 412; 421, 422), said respective pair of pull-up or pull-down transistors (111, 112; 121, 122; 211, 212; 221, 222; 411, 412; 421, 422) being connected in series and having a respective shared node (231, 232) therebetween; characterized in that for a particular one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602), one of said respective shared nodes associated with one of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602), and another of said respective shared nodes associated with another of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a third one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602). each of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602) comprises a plurality of transistors forming two complementary memory nodes (101, 102), one of said complementary memory nodes (101, 102) storing a value and another of said complementary memory nodes (101, 102) storing a complement of said value; each respective one of said complementary memory nodes (101, 102) is connected to a respective pair of pull-up or pull-down transistors (111, 112; 121, 122; 211, 212; 221, 222; 411, 412; 421, 422), said respective pair of pull-up or pull-down transistors (111, 112; 121, 122; 211, 212; 221, 222; 411, 412; 421, 422) being connected in series and having a respective shared node (231, 232) therebetween; characterized in that for a particular one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602), one of said respective shared nodes associated with one of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602), and another of said respective shared nodes associated with another of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a third one of said memory cells (200, 301-303, 401, 402, 501, 502, 601, 602).