A method for personalizing at least one chip, intended to be integrated into a smart card, involving a tester associated to a FPGA device connected to the chip, the chip being part of a wafer comprising an arrangement of a plurality of chips, comprising steps of: sending by the tester a first secret code to the FPGA device, said first secret code being stored permanently in a memory of the tester, sending by the FPGA device a command to the chip to initiate a sequence of a test mode activation, sending by the chip a signal (s) to a disposable hardware module arranged on the wafer, said hardware module returning a response (r) indicating presence of the chip on the wafer, generating and sending by the chip a random number to the FPGA device, encrypting by the FPGA device a second secret code by using a secret encryption algorithm parameterized with the random number and the first secret code, obtaining a first cryptogram M1=E R,S1, sending by the FPGA device the first cryptogram M1=E R,S1, to the chip, determining by the chip a second cryptogram M2 = F(E -1 R, S1) by carrying out a Boolean function F over a result E -1 R,S obtained by decrypting the first cryptogram using the inverse (E -1) of the secret encryption algorithm parameterized with the random number and the first secret code, comparing by the chip the second cryptogram with a result F obtained by carrying the Boolean function F over the second secret code temporarily stored on the chip, if the second cryptogram corresponds with the result F obtained by carrying out the Boolean function F over the second secret code, enabling the test mode, sending by the chip a response message to the FPGA device, performing, by the FPGA device, personalization of the chip if the message includes a positive response. sending by the tester a first secret code to the FPGA device, said first secret code being stored permanently in a memory of the tester, sending by the FPGA device a command to the chip to initiate a sequence of a test mode activation, sending by the chip a signal (s) to a disposable hardware module arranged on the wafer, said hardware module returning a response (r) indicating presence of the chip on the wafer, generating and sending by the chip a random number to the FPGA device, encrypting by the FPGA device a second secret code by using a secret encryption algorithm parameterized with the random number and the first secret code, obtaining a first cryptogram M1=E R,S1, sending by the FPGA device the first cryptogram M1=E R,S1, to the chip, determining by the chip a second cryptogram M2 = F(E -1 R, S1) by carrying out a Boolean function F over a result E -1 R,S obtained by decrypting the first cryptogram using the inverse (E -1) of the secret encryption algorithm parameterized with the random number and the first secret code, comparing by the chip the second cryptogram with a result F obtained by carrying the Boolean function F over the second secret code temporarily stored on the chip, if the second cryptogram corresponds with the result F obtained by carrying out the Boolean function F over the second secret code, enabling the test mode, sending by the chip a response message to the FPGA device, performing, by the FPGA device, personalization of the chip if the message includes a positive response.