A memory cell comprising: first and second resistive elements (202, 204), at least one of which is programmable to have one of at least two resistive states (R min, R max), a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second storage node and a second intermediate node; a first transistor coupled between said first storage node and a first supply voltage (GND, V DD); a second transistor coupled between said second storage node and said first supply voltage, wherein a control node of said first transistor is coupled to said second storage node and a control node of said second transistor is coupled to said first storage node; a third transistor coupled between the first and second intermediate nodes; characterized by: a fourth transistor (226, 826) connected between the first storage node and a second supply voltage (V DD, GND); a fifth transistor (230, 830) connected between the second storage node and the second supply voltage; and control circuitry (226 to 234, 826 to 834) configured to active said third transistor while applying, by activating the fourth or fifth transistor, the second supply voltage (V DD, GND) to said first or second storage node to generate a programming current in a selected direction through said first and second resistive elements to program the resistive state of at least one of said elements. first and second resistive elements (202, 204), at least one of which is programmable to have one of at least two resistive states (R min, R max), a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second storage node and a second intermediate node; a first transistor coupled between said first storage node and a first supply voltage (GND, V DD); a second transistor coupled between said second storage node and said first supply voltage, wherein a control node of said first transistor is coupled to said second storage node and a control node of said second transistor is coupled to said first storage node; a third transistor coupled between the first and second intermediate nodes; characterized by: a fourth transistor (226, 826) connected between the first storage node and a second supply voltage (V DD, GND); a fifth transistor (230, 830) connected between the second storage node and the second supply voltage; and control circuitry (226 to 234, 826 to 834) configured to active said third transistor while applying, by activating the fourth or fifth transistor, the second supply voltage (V DD, GND) to said first or second storage node to generate a programming current in a selected direction through said first and second resistive elements to program the resistive state of at least one of said elements. a fourth transistor (226, 826) connected between the first storage node and a second supply voltage (V DD, GND); a fifth transistor (230, 830) connected between the second storage node and the second supply voltage; and control circuitry (226 to 234, 826 to 834) configured to active said third transistor while applying, by activating the fourth or fifth transistor, the second supply voltage (V DD, GND) to said first or second storage node to generate a programming current in a selected direction through said first and second resistive elements to program the resistive state of at least one of said elements.