A digitally tuned capacitor for use in an integrated circuit device, comprising: (a) a first RF terminal; (b) a second RF terminal; and (c) a control logic block adapted to receive a digital control word having a selected plurality of b digital control word bits, wherein the control logic block is adapted, via the digital control word, to selectively control a capacitance applied between the first and second RF terminals; characterized in that the digitally tuned capacitor further comprises: (d) a plurality of sub-circuits coupled in parallel between the first and second RF terminals, wherein each sub-circuit comprises: (i) a FET stack comprising n stacked field-effect-transistor switches, n being equal to or larger than one, each FET switch of the FET stack having a same size, the same size defining a size of the each sub-circuit; (ii) at least one capacitor in series connection with the n stacked FET switches having a capacitance value (C MIM) that is proportional to the size of the each sub-circuit; (iii) n gate resistors (Rg) each having a same resistance value that is inversely proportional to the size of the each sub-circuit, each gate resistor (Rg) coupled, by way of a first terminal of the gate resistor (Rg), to a gate of a FET switch of the FET stack; and (iv) n drain-to-source resistors (Rds) each having a same resistance value that is inversely proportional to the size of the each sub-circuit, each drain-to-source resistor (Rds) coupled between a drain and a source of a FET switch of the FET stack, wherein each sub-circuit is coupled, by way of second terminals of the n gate resistors (Rg), to an associated and corresponding bit of the digital control word, in a one-to-one relationship, and wherein the control logic block is adapted, via the digital control word, to selectively control the capacitance applied between the first and second RF terminals by selectively controlling switching operation of the FET stacked switches. (a) a first RF terminal; (b) a second RF terminal; and (c) a control logic block adapted to receive a digital control word having a selected plurality of b digital control word bits, wherein the control logic block is adapted, via the digital control (d) a plurality of sub-circuits coupled in parallel between the first and second RF terminals, (i) a FET stack comprising n stacked field-effect-transistor switches, n being equal to or larger than one, each FET switch of the FET stack having a same size, the same size defining a size of the each sub-circuit; (ii) at least one capacitor in series connection with the n stacked FET switches having a capacitance value (C MIM) that is proportional to the size of the each sub-circuit; (iii) n gate resistors (Rg) each having a same resistance value that is inversely proportional to the size of the each sub-circuit, each gate resistor (Rg) coupled, by way of a first terminal of the gate resistor (Rg), to a gate of a FET switch of the FET stack; and (iv) n drain-to-source resistors (Rds) each having a same resistance value that is inversely proportional to the size of the each sub-circuit, each drain-to-source resistor (Rds) coupled between a drain and a source of a FET switch of the FET stack,