A method for forming a three-dimensional, 3D, memory device (100, 200), comprising: subsequently forming a sacrificial layer above a second N-type doped semiconductor layer (122, 304) at a first side of a substrate (101, 302) and a dielectric stack, which includes interleaved stack sacrificial layers and stack dielectric layers, on the sacrificial layer; forming a channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer (122, 304); replacing the sacrificial layer with a first N-doped semiconductor layer (120, 326) in contact with the second semiconductor layer (122, 304); replacing the dielectric stack with a memory stack (114, 330) including a plurality of interleaved conductive layers and the stack dielectric layers, such that the channel structure extends vertically through the memory stack (114, 330) and the first semiconductor layer (120, 326) into the second semiconductor layer (122, 304), the method characterised in that it further comprises: forming a source contact at a second side opposite to the first side of the substrate (101, 302) to be in contact with the second semiconductor layer (122, 304), wherein the substrate (101, 302) is thinned from the second side to expose second N-type doped semiconductor layer (122, 304), wherein at least two ILD layers are formed on second N-type doped semiconductor layer (122, 304), wherein a source contact opening is formed through the at least two ILD layers into N-type doped semiconductor layer (122, 304), wherein the source contact is formed in source contact opening at the second side of second N-type doped semiconductor layer (122, 304), wherein the first semiconductor layer surrounds part of channel structure and is in contact with a semiconductor channel of the channel structure, wherein a peripheral circuit is formed on a further substrate, wherein the substrate (101, 302) and the further substrate are bonded, such that the memory stack (114, 330) is between the substrate (101, 302) and the further substrate. subsequently forming a sacrificial layer above a second N-type doped semiconductor layer (122, 304) at a first side of a substrate (101, 302) and a dielectric stack, which includes interleaved stack sacrificial layers and stack dielectric layers, on the sacrificial layer; forming a channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer (122, 304); replacing the sacrificial layer with a first N-doped semiconductor layer (120, 326) in contact with the second semiconductor layer (122, 304); replacing the dielectric stack with a memory stack (114, 330) including a plurality of interleaved conductive layers and the stack dielectric layers, such that the channel structure extends vertically through the memory stack (114, 330) and the first semiconductor layer (120, 326) into the second semiconductor layer (122, 304), the method characterised in that it further comprises: forming a source contact at a second side opposite to the first side of the substrate (101, 302) to be in contact with the second semiconductor layer (122, 304), wherein the substrate (101, 302) is thinned from the second side to expose second N-type doped semiconductor layer (122, 304), wherein at least two ILD layers are formed on second N-type doped semiconductor layer (122, 304), wherein a source contact opening is formed through the at least two ILD layers into N-type doped semiconductor layer (122, 304), wherein the source contact is formed in source contact opening at the second side of second N-type doped semiconductor layer (122, 304), wherein the first semiconductor layer surrounds part of channel structure and is in contact with a semiconductor channel of the channel structure, wherein a peripheral circuit is formed on a further substrate, wherein the substrate (101, 302) and the further substrate are bonded, such that the memory stack (114, 330) is between the substrate (101, 302) and the further substrate. forming a source contact at a second side opposite to the first side of the substrate (101, 302) to be in contact with the second semiconductor layer (122, 304), wherein the substrate (101, 302) is thinned from the second side to expose second N-type doped semiconductor layer (122, 304), wherein at least two ILD layers are formed on second N-type doped semiconductor layer (122, 304), wherein a source contact opening is formed through the at least two ILD layers into N-type doped semiconductor layer (122, 304), wherein the source contact is formed in source contact opening at the second side of second N-type doped semiconductor layer (122, 304), wherein the first semiconductor layer surrounds part of channel structure and is in contact with a semiconductor channel of the channel structure, wherein a peripheral circuit is formed on a further substrate, wherein the substrate (101, 302) and the further substrate are bonded, such that the memory stack (114, 330) is between the substrate (101, 302) and the further substrate.