A chip surface base device structure (100, 200, 300, 400, 500, 600, 700, 800, 900, 1000) comprising: a superconducting material (114, 214A, 214B, 214C, 314D, 314E, 1014A, 1014B, 1014C, 1014D) located on a first side of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006); a second superconducting material (104, 704A, 704B, 704C) located on a second side of the substrate (106A, 106B, 706A, 706B, 706C, 706D, 806, 1006) and stacked on a second substrate, wherein the first side of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and the second side of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) are opposite sides; a transmon qubit comprising: a capacitor; and a Josephson junction formed in a via of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and comprising a tunnel barrier (110, 1016); and a microstrip line formed by a portion of the superconducting material (214B, 214C) and electrically coupled to the transmon qubit, characterised in that the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006), the second superconducting material (104, 704A, 704B, 704C), and the second substrate comprise a silicon-on-metal, SOM, base and the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and the second substrate comprise crystalline silicon. a superconducting material (114, 214A, 214B, 214C, 314D, 314E, 1014A, 1014B, 1014C, 1014D) located on a first side of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006); a second superconducting material (104, 704A, 704B, 704C) located on a second side of the substrate (106A, 106B, 706A, 706B, 706C, 706D, 806, 1006) and stacked on a second substrate, wherein the first side of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and the second side of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) are opposite sides; a transmon qubit comprising: a capacitor; and a Josephson junction formed in a via of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and comprising a tunnel barrier (110, 1016); and a microstrip line formed by a portion of the superconducting material (214B, 214C) and electrically coupled to the transmon qubit, characterised in that the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006), the second superconducting material (104, 704A, 704B, 704C), and the second substrate comprise a silicon-on-metal, SOM, base and the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and the second substrate comprise crystalline silicon. a capacitor; and a Josephson junction formed in a via of the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and comprising a tunnel barrier (110, 1016); and a microstrip line formed by a portion of the superconducting material (214B, 214C) and electrically coupled to the transmon qubit, characterised in that the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006), the second superconducting material (104, 704A, 704B, 704C), and the second substrate comprise a silicon-on-metal, SOM, base and the substrate (106A, 106B, 306, 706A, 706B, 706C, 706D, 806, 1006) and the second substrate comprise crystalline silicon.