A memory device comprising: a substrate; a common source line; a first cell string (CS1a), second cell string (CS1b), and third cell string (CS1c), each connected at an end to a first bit line and at another end to the common source line and formed in a direction perpendicular to a top surface of the substrate, each of the first to third cell strings comprising memory cells (MC1 - MC4), a lower ground selection transistor and an upper ground selection transistor, the lower ground selection transistor and the upper ground selection transistor being connected between the memory cells (MC1 - MC4) and the common source line; a first upper ground selection line (GSLua) connected to the upper ground selection transistor of the first cell string (CS1a); a second upper ground selection line (GSLub) separated from the first upper ground selection line (GSLua), and connected to the upper ground selection transistor of the second cell string (CS1b) and to the upper ground selection transistor of the third cell string (CS1c); a first lower ground selection line (GSLda) connected to the lower ground selection transistor of the first cell string (CS1a) and the lower ground selection transistor of the second cell string (CS1b); and a second lower ground selection line (GSLdb) separated from the first lower ground selection line (GSLda), and connected to the ground selection transistor of the third cell string (CS1c), wherein: the first lower ground selection line (GSLda) is closer to the surface of the substrate than the first upper ground selection line (GSLua); the second lower ground selection line (GSLdb) is closer to the surface of the substrate than the second upper ground selection line (GSLub); and for each cell string, the lower ground selection transistor of the cell string is closer to the substrate than the upper ground selection transistor of the cell string. a substrate; a common source line; a first cell string (CS1a), second cell string (CS1b), and third cell string (CS1c), each connected at an end to a first bit line and at another end to the common source line and formed in a direction perpendicular to a top surface of the substrate, each of the first to third cell strings comprising memory cells (MC1 - MC4), a lower ground selection transistor and an upper ground selection transistor, the lower ground selection transistor and the upper ground selection transistor being connected between the memory cells (MC1 - MC4) and the common source line; a first upper ground selection line (GSLua) connected to the upper ground selection transistor of the first cell string (CS1a); a second upper ground selection line (GSLub) separated from the first upper ground selection line (GSLua), and connected to the upper ground selection transistor of the second cell string (CS1b) and to the upper ground selection transistor of the third cell string (CS1c); a first lower ground selection line (GSLda) connected to the lower ground selection transistor of the first cell string (CS1a) and the lower ground selection transistor of the second cell string (CS1b); and a second lower ground selection line (GSLdb) separated from the first lower ground selection line (GSLda), and connected to the ground selection transistor of the third cell string (CS1c), a first upper ground selection line (GSLua) connected to the upper ground selection transistor of the first cell string (CS1a); a second upper ground selection line (GSLub) separated from the first upper ground selection line (GSLua), and connected to the upper ground selection transistor of the second cell string (CS1b) and to the upper ground selection transistor of the third cell string (CS1c); a first lower ground selection line (GSLda) connected to the lower ground selection transistor of the first cell string (CS1a) and the lower ground selection transistor of the second cell string (CS1b); and a second lower ground selection line (GSLdb) separated from the first lower ground selection line (GSLda), and connected to the ground selection transistor of the third cell string (CS1c), wherein: the first lower ground selection line (GSLda) is closer to the surface of the substrate than the first upper ground selection line (GSLua); the second lower ground selection line (GSLdb) is closer to the surface of the substrate than the second upper ground selection line (GSLub); and for each cell string, the lower ground selection transistor of the cell string is closer to the substrate than the upper ground selection transistor of the cell string. the first lower ground selection line (GSLda) is closer to the surface of the substrate than the first upper ground selection line (GSLua); the second lower ground selection line (GSLdb) is closer to the surface of the substrate than the second upper ground selection line (GSLub); and for each cell string, the lower ground selection transistor of the cell string is closer to the substrate than the upper ground selection transistor of the cell string.