A non-volatile storage system, comprising: a set of non-volatile storage elements formed in NAND strings on a substrate, including at least one selected NAND string in a program-verify iteration and at least one unselected NAND string in the program-verify iteration, the set of non-volatile storage elements is addressable by a plurality of word lines, including a selected word line (WLn) in the program-verify iteration, and unselected word lines (WLO to WLn-1; WLn+1 to WLf) in the program-verify iteration; and at least one control circuit (110, 150), the at least one control circuit being configured to, in connection with a program portion of the program-verify iteration: (a) render a drain-side select gate of the at least one unselected NAND string non-conductive to allow boosting in at least one channel region in the substrate below the at least one unselected NAND string, and (b) step up a voltage of the selected word line from a respective pre-program pulse voltage (Vpass) to a program pulse voltage (Vpgm) at a step up time which is before a program pulse time period (t5-t8), and maintains the program pulse voltage during the program pulse time period (t5-t8), wherein said non-volatile storage system is characterised in that the at least one control circuit, in connection with a program portion of the program-verify iteration, is further configured to: (c) in order to boost the at least one channel region, during the program pulse time period (t5- t8): apply a voltage (Vpass-Isb) to at least one of the unselected word lines (WLn-4 to WLn-1; WLn+1 to WLn+4), the voltage applied to the at least one of the unselected word lines increases at a rate which is a function of temperature. a set of non-volatile storage elements formed in NAND strings on a substrate, including at least one selected NAND string in a program-verify iteration and at least one unselected NAND string in the program-verify iteration, the set of non-volatile storage elements is addressable by a plurality of word lines, including a selected word line (WLn) in the program-verify iteration, and unselected word lines (WLO to WLn-1; WLn+1 to WLf) in the program-verify iteration; and at least one control circuit (110, 150), the at least one control circuit being configured to, in connection with a program portion of the program-verify iteration: (a) render a drain-side select gate of the at least one unselected NAND string non-conductive to allow boosting in at least one channel region in the substrate below the at least one unselected NAND string, and (b) step up a voltage of the selected word line from a respective pre-program pulse voltage (Vpass) to a program pulse voltage (Vpgm) at a step up time which is before a program pulse time period (t5-t8), and maintains the program pulse voltage during the program pulse time period (t5-t8), wherein said non-volatile storage system is characterised in that the at least one control circuit, in connection with a program portion of the program-verify iteration, is further configured to: (c) in order to boost the at least one channel region, during the program pulse time period (t5- t8): apply a voltage (Vpass-Isb) to at least one of the unselected word lines (WLn-4 to WLn-1; WLn+1 to WLn+4), the voltage applied to the at least one of the unselected word lines increases at a rate which is a function of temperature. (c) in order to boost the at least one channel region, during the program pulse time period (t5- t8): apply a voltage (Vpass-Isb) to at least one of the unselected word lines (WLn-4 to WLn-1; WLn+1 to WLn+4), the voltage applied to the at least one of the unselected word lines increases at a rate which is a function of temperature.