An amplifier module comprising: a multi-layer printed circuit board, PCB; a first power transistor die mounted at a top surface of the multi-layer PCB, the first power transistor die being a carrier amplifier die; a second power transistor die mounted at the top surface of the multi-layer PCB, the second power transistor die being a peaking amplifier die; an impedance inversion element coupled between an output of the first power transistor die and an output of the second power transistor die, a combining node (150, 350) formed at and coupled to the output of the second power transistor die; a first stub circuit coupled to the combining node, the first stub circuit comprising a first stripline (202, 302) having a first end coupled to the combining node at the output of the second power transistor die and formed from a first inner conductive layer of the multi-layer PCB; a second stub circuit coupled at the combining node in parallel with the first stub circuit, the second stub circuit comprising a second stripline (212, 312) formed from a different inner conductive layer of the multi-layer PCB than the first stripline and having a first end coupled to the combining node at the output of the second power transistor die, characterized in that: the first stub circuit is a 90 degree shorting stub configured to function as an open circuit at a fundamental frequency F 0 and as a shunt to a ground reference voltage supply terminal to the outputs of both the second power transistor die and the first power transistor die at a second harmonic frequency 2*F 0; and the second stub circuit is a 60 degree shorting stub configured to function as a shunt to the ground reference voltage supply terminal to the output of the second power transistor die at a third harmonic frequency 3*F 0 and as an open circuit to the output of the first power transistor die; and wherein the first stub circuit further comprises a first capacitor (206, 306), a first terminal of the first capacitor (206,306) coupled to a second end of the first stripline; and the second stub circuit further comprises a second capacitor (216, 316), a first terminal of the second capacitor (216,316) coupled to a second end of the second stripline (212, 312). a multi-layer printed circuit board, PCB; a first power transistor die mounted at a top surface of the multi-layer PCB, the first power transistor die being a carrier amplifier die; a second power transistor die mounted at the top surface of the multi-layer PCB, the second power transistor die being a peaking amplifier die; an impedance inversion element coupled between an output of the first power transistor die and an output of the second power transistor die, a combining node (150, 350) formed at and coupled to the output of the second power transistor die; a first stub circuit coupled to the combining node, the first stub circuit comprising a first stripline (202, 302) having a first end coupled to the combining node at the output of the second power transistor die and formed from a first inner conductive layer of the multi-layer PCB; a second stub circuit coupled at the combining node in parallel with the first stub circuit, the second stub circuit comprising a second stripline (212, 312) formed from a different inner conductive layer of the multi-layer PCB than the first stripline and having a first end coupled to the combining node at the output of the second power transistor die, characterized in that: the first stub circuit is a 90 degree shorting stub configured to function as an open circuit at a fundamental frequency F 0 and as a shunt to a ground reference voltage supply terminal to the outputs of both the second power transistor die and the first power transistor die at a second harmonic frequency 2*F 0; and the second stub circuit is a 60 degree shorting stub configured to function as a shunt to the ground reference voltage supply terminal to the output of the second power transistor die at a third harmonic frequency 3*F 0 and as an open circuit to the output of the first power transistor die; and wherein the first stub circuit further comprises a first capacitor (206, 306), a first terminal of the first capacitor (206,306) coupled to a second end of the first stripline; and the second stub circuit further comprises a second capacitor (216, 316), a first terminal of the second capacitor (216,316) coupled to a second end of the second stripline (212, 312). the first stub circuit is a 90 degree shorting stub configured to function as an open circuit at a fundamental frequency F 0 and as a shunt to a ground reference voltage supply terminal to the outputs of both the second power transistor die and the first power transistor die at a second harmonic frequency 2*F 0; and the second stub circuit is a 60 degree shorting stub configured to function as a shunt to the ground reference voltage supply terminal to the output of the second power transistor die at a third harmonic frequency 3*F 0 and as an open circuit to the output of the first power transistor die; and wherein the first stub circuit further comprises a first capacitor (206, 306), a first terminal of the first capacitor (206,306) coupled to a second end of the first stripline; and the second stub circuit further comprises a second capacitor (216, 316), a first terminal of the second capacitor (216,316) coupled to a second end of the second stripline (212, 312).