A semiconductor device (100, 101, 400, 401, 500, 501), comprising: a first semiconductor structure (102, 300, 402, 405, 502, 505, 906, 1006, 1100, 1201) comprising a processor (202, 412, 435, 512, 535, 608), an array of static random-access memory, SRAM, cells (414, 437, 514, 537, 610) forming an SRAM, a first bonding layer (422, 451, 522, 616) comprising a plurality of first bonding contacts (424, 453, 524, 527, 618), a first interconnect layer (420, 457, 520, 529, 614) vertically between the first bonding layer (422, 451, 522, 616) and the processor (202, 412, 435, 512, 535, 608), all peripheral circuits for controlling and sensing a NAND memory, wherein the SRAM and the peripheral circuits are disposed outside of the processor, wherein the array of SRAM cells (414, 437, 514, 537, 610) are distributed in a plurality of separate regions in the first semiconductor structure, which is outside of processor,wherein a cache module formed by the SRAM is divided into smaller cache regions, distributed randomly, and wherein the first interconnect layer (420, 457, 520, 529, 614) is configured to transfer electrical signals between the processor (202, 412, 435, 512, 535, 608) and one or more of the array of SRAM cells (414, 437, 514, 537, 610) and the peripheral circuits, wherein the SRAM and the processor (202, 412, 435, 512, 535, 608) are stacked one over another; a second semiconductor structure (104, 301, 403, 404, 503, 504, 908, 1008, 1101, 1203) comprising an array of NAND memory cells (536, 551, 703), a second bonding layer (426, 429, 515, 526, 715, 722) comprising a plurality of second bonding contacts (428, 455, 517, 528, 717, 724), and a second interconnect layer vertically between the second bonding layer (426, 429, 515, 526, 715, 722) and the array of NAND memory cells; and a bonding interface (106, 406, 407, 506, 507, 802, 803, 1014) between the first bonding layer (422, 451, 522, 616) and the second bonding layer (426, 429, 515, 526, 715, 722), wherein the first bonding contacts (424, 453, 524, 527, 618) are in contact with the second bonding contacts (428, 455, 517, 528, 717, 724) at the bonding interface (106, 406, 407, 506, 507, 802, 803, 1014). a first semiconductor structure (102, 300, 402, 405, 502, 505, 906, 1006, 1100, 1201) comprising a processor (202, 412, 435, 512, 535, 608), an array of static random-access memory, SRAM, cells (414, 437, 514, 537, 610) forming an SRAM, a first bonding layer (422, 451, 522, 616) comprising a plurality of first bonding contacts (424, 453, 524, 527, 618), a first interconnect layer (420, 457, 520, 529, 614) vertically between the first bonding layer (422, 451, 522, 616) and the processor (202, 412, 435, 512, 535, 608), all peripheral circuits for controlling and sensing a NAND memory, wherein the SRAM and the peripheral circuits are disposed outside of the processor, wherein the array of SRAM cells (414, 437, 514, 537, 610) are distributed in a plurality of separate regions in the first semiconductor structure, which is outside of processor,wherein a cache module formed by the SRAM is divided into smaller cache regions, distributed randomly, and wherein the first interconnect layer (420, 457, 520, 529, 614) is configured to transfer electrical signals between the processor (202, 412, 435, 512, 535, 608) and one or more of the array of SRAM cells (414, 437, 514, 537, 610) and the peripheral circuits, wherein the SRAM and the processor (202, 412, 435, 512, 535, 608) are stacked one over another; a second semiconductor structure (104, 301, 403, 404, 503, 504, 908, 1008, 1101, 1203) comprising an array of NAND memory cells (536, 551, 703), a second bonding layer (426, 429, 515, 526, 715, 722) comprising a plurality of second bonding contacts (428, 455, 517, 528, 717, 724), and a second interconnect layer vertically between the second bonding layer (426, 429, 515, 526, 715, 722) and the array of NAND memory cells; and a bonding interface (106, 406, 407, 506, 507, 802, 803, 1014) between the first bonding layer (422, 451, 522, 616) and the second bonding layer (426, 429, 515, 526, 715, 722), wherein the first bonding contacts (424, 453, 524, 527, 618) are in contact with the second bonding contacts (428, 455, 517, 528, 717, 724) at the bonding interface (106, 406, 407, 506, 507, 802, 803, 1014). an array of NAND memory cells (536, 551, 703), a second bonding layer (426, 429, 515, 526, 715, 722) comprising a plurality of second bonding contacts (428, 455, 517, 528, 717, 724), and a second interconnect layer vertically between the second bonding layer (426, 429, 515, 526, 715, 722) and the array of NAND memory cells; and a plurality of second bonding contacts (428, 455, 517, 528, 717, 724), and a second interconnect layer vertically between the second bonding layer (426, 429, 515, 526, 715, 722) and the array of NAND memory cells; and a bonding interface (106, 406, 407, 506, 507, 802, 803, 1014) between the first bonding layer (422, 451, 522, 616) and the second bonding layer (426, 429, 515, 526, 715, 722), wherein the first bonding contacts (424, 453, 524, 527, 618) are in contact with the second bonding contacts (428, 455, 517, 528, 717, 724) at the bonding interface (106, 406, 407, 506, 507, 802, 803, 1014).