A pixel structure, comprising a plurality of sub-pixels arranged in a matrix, a plurality of gate lines (VGa1, VGa2, VGb1, VGb2) and a plurality of data lines (Vd1, Vd2), the plurality of data lines crossing with the plurality of gate lines, wherein the gate lines (VGa1, VGa2, VGb1, VGb2) comprise a plurality of first gate lines (VGa1, VGa2) and a plurality of second gate lines (VGb1, VGb2), each sub-pixel comprises a first part and a second part, and a first thin film transistor and a second thin film transistor, the first parts and the second parts of the plurality of sub-pixels are respectively arranged in rows, and the rows consisting of the first parts are alternatively arranged with the rows consisting of the second parts, wherein for each sub-pixel, the first part is connected to a corresponding data line (Vd1, Vd2) through the first thin film transistor, a gate of the first film transistor is connected to a corresponding first gate line (VGa1, VGa2), the first part and the second part are connected with each other through the second thin film transistor, and each of the first part and the second part comprises a pixel electrode, the pixel electrode of the first part is connected to the corresponding data lines (Vd1, Vd2) through the first thin film transistor, and the pixel electrode of the second part is connected to the pixel electrode of the first part through the second thin film transistor, characterized in that: for each sub-pixel, a gate of the second thin film transistor is connected to a corresponding second gate line (VGb1, VGb2), wherein the second gate lines (VGb1, VGb2) used for each sub-pixel in the pixel structure are electrically connected with one another through a wire, wherein in a planar display mode, the pixel structure is configured to provide the second gate lines (VGb1, VGb2) with a first level, so as to make the second thin film transistor in each sub-pixel turned on; wherein in a stereoscopic display mode, the pixel structure is configured to provide the second gate lines (VGb1, VGb2) with a second level, so as to make the second thin film transistor in each the sub-pixel turned off, wherein the first level is higher than the second level; and wherein, upon switching from the planar display mode to the stereoscopic display mode, the pixel structure is configured to provide all of the first gate lines (VGa1, VGa2) and the second gate lines (VGb1, VGb2) with higher levels and to provide the data lines (Vd1, Vd2) with black image signals so that both of the first part and the second part of each sub-pixel display black. for each sub-pixel, a gate of the second thin film transistor is connected to a corresponding second gate line (VGb1, VGb2), wherein the second gate lines (VGb1, VGb2) used for each sub-pixel in the pixel structure are electrically connected with one another through a wire, wherein in a planar display mode, the pixel structure is configured to provide the second gate lines (VGb1, VGb2) with a first level, so as to make the second thin film transistor in each sub-pixel turned on; wherein in a stereoscopic display mode, the pixel structure is configured to provide the second gate lines (VGb1, VGb2) with a second level, so as to make the second thin film transistor in each the sub-pixel turned off, wherein the first level is higher than the second level; and wherein, upon switching from the planar display mode to the stereoscopic display mode, the pixel structure is configured to provide all of the first gate lines (VGa1, VGa2) and the second gate lines (VGb1, VGb2) with higher levels and to provide the data lines (Vd1, Vd2) with black image signals so that both of the first part and the second part of each sub-pixel display black.