A power supply system (10/150) comprising: a phase-shift controller configured to generate a plurality of clock signals (CLK_1...CLK_N), each of the plurality of clock signals (CLK_1...CLK_N) being phase-shifted relative to each other; and a plurality of power supplies (12/152) configured to generate at least one output voltage (V OUT_X) and being substantially spatially distributed, each of the plurality of power supplies (12/152) comprising: a power stage (20/160) configured to control at least one switch (SW 1, SW 2) based on a pulse-width modulation switching signal (PWM_1...PWM_N) to generate the respective at least one output voltage (V OUT_X); a PWM generator (18/158) configured to generate the PWM switching signal (PWM_1...PWM_N) in response to one of the plurality of clock signals (CLK_1...CLK_N); an error amplifier configured to generate an error voltage (V ERR_X) based on a feedback voltage (V FB_X) of a corresponding power supply (12/152) relative to a reference voltage (V REF_X); characterized in that the error voltage (V ERR_X) is provided from the output of an error amplifier system (16/52) of each of the power supplies (12/152) onto a comparison node (24/60) across a forward-biased diode within the error amplifier system (16/52) as an error voltage (V ERR) at the comparison node (24/60), such that the outputs of the error amplifier systems (16/52) are electrically coupled together, and the error voltage (V ERR) at the comparison node (24/60) can be applied from a given one of the error amplifier systems (16/52) having the greatest magnitude to each of the PWM generators (18/158) via the comparison node (24/60). a phase-shift controller configured to generate a plurality of clock signals (CLK_1...CLK_N), each of the plurality of clock signals (CLK_1...CLK_N) being phase-shifted relative to each other; and a plurality of power supplies (12/152) configured to generate at least one output voltage (V OUT_X) and being substantially spatially distributed, each of the plurality of power supplies (12/152) comprising: a power stage (20/160) configured to control at least one switch (SW 1, SW 2) based on a pulse-width modulation switching signal (PWM_1...PWM_N) to generate the respective at least one output voltage (V OUT_X); a PWM generator (18/158) configured to generate the PWM switching signal (PWM_1...PWM_N) in response to one of the plurality of clock signals (CLK_1...CLK_N); an error amplifier configured to generate an error voltage (V ERR_X) based on a feedback voltage (V FB_X) of a corresponding power supply (12/152) relative to a reference voltage (V REF_X); a power stage (20/160) configured to control at least one switch (SW 1, SW 2) based on a pulse-width modulation switching signal (PWM_1...PWM_N) to generate the respective at least one output voltage (V OUT_X); a PWM generator (18/158) configured to generate the PWM switching signal (PWM_1...PWM_N) in response to one of the plurality of clock signals (CLK_1...CLK_N); an error amplifier configured to generate an error voltage (V ERR_X) based on a feedback voltage (V FB_X) of a corresponding power supply (12/152) relative to a reference voltage (V REF_X); characterized in that the error voltage (V ERR_X) is provided from the output of an error amplifier system (16/52) of each of the power supplies (12/152) onto a comparison node (24/60) across a forward-biased diode within the error amplifier system (16/52) as an error voltage (V ERR) at the comparison node (24/60), such that the outputs of the error amplifier systems (16/52) are electrically coupled together, and the error voltage (V ERR) at the comparison node (24/60) can be applied from a given one of the error amplifier systems (16/52) having the greatest magnitude to each of the PWM generators (18/158) via the comparison node (24/60).