A gate driving circuit comprising: a shift register including a plurality of stages connected to each other by a cascade connection and sequentially outputting a gate voltage using a high level power voltage, a low level power voltage, a start voltage at the first stage, a gate voltage from a previous stage at the second to nth stages (SRS2 to SRSn), a next stage gate voltage (VNEXT) and a clock, each of the plurality of stages comprising: a first thin film transistor switched by the start voltage or the previous stage gate voltage and transmitting the high level power voltage to a Q node; a second TFT switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage to the Q node; an eighth TFT switched by a voltage of the Q node and transmitting the clock to an output node; second and third resistor (R2, R3) connected between the output node and the low level power voltage in series; a third TFT switched by a voltage of a QB node and transmitting the low level power voltage to the Q node; a fourth TFT switched by the next stage gate voltage (VNEXT) and transmitting the high level power voltage to the QB node; a fifth TFT switched by the voltage of the Q node and transmitting the low level power voltage to the QB node; a sixth TFT switched by the high level power voltage and transmitting the high level power voltage to the QB node; and a seventh TFT switched by the start voltage in the first stage and the gate voltage from a previous stage in the second to nth stages (SRS2 to SRSn) and transmitting the low level power voltage to the QB node; a ninth TFT switched by a voltage of the output node and transmitting the high level power voltage to a first node between the second and third resistors (R2, R3); and a tenth TFT switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage to the first node. a first thin film transistor switched by the start voltage or the previous stage gate voltage and transmitting the high level power voltage to a Q node; a second TFT switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage to the Q node; an eighth TFT switched by a voltage of the Q node and transmitting the clock to an output node; second and third resistor (R2, R3) connected between the output node and the low level power voltage in series; a third TFT switched by a voltage of a QB node and transmitting the low level power voltage to the Q node; a fourth TFT switched by the next stage gate voltage (VNEXT) and transmitting the high level power voltage to the QB node; a fifth TFT switched by the voltage of the Q node and transmitting the low level power voltage to the QB node; a sixth TFT switched by the high level power voltage and transmitting the high level power voltage to the QB node; and a seventh TFT switched by the start voltage in the first stage and the gate voltage from a previous stage in the second to nth stages (SRS2 to SRSn) and transmitting the low level power voltage to the QB node; a ninth TFT switched by a voltage of the output node and transmitting the high level power voltage to a first node between the second and third resistors (R2, R3); and a tenth TFT switched by the next stage gate voltage (VNEXT) and transmitting the low level power voltage to the first node.