A semiconductor package substrate comprising: an insulating substrate; a circuit pattern on a first side and an opposite side of the insulating substrate; a solder resist formed on the insulating substrate to cover the circuit pattern on the first side and partially covering the circuit pattern on the opposite side of the insulating substrate, wherein the solder resist on the opposite side of the insulating substrate, has at least one opening to expose a surface of the circuit pattern on the opposite side of the insulating substrate, characterized by further comprising: a plating seed layer on the solder resist on the first side of the insulating substrate while protruding from a surface of the solder resist having a lower width and an upper width equal to each other; a first pad on the plating seed layer and having a lower width and an upper width equal to each other; a second pad on the first pad and having a lower width and an upper width equal to each other; and an adhesive member on the second pad, wherein a bottom surface of the plating seed layer is directly brought into contact with the top surface of the solder resist; wherein the opening of the solder resist on the opposite side of the insulation substrate has a width narrower than that of the circuit pattern, and an edge region of the circuit pattern is covered by the solder resist, wherein the solder resist on the opposite side of the insulating substrate is exposed to an outside, wherein a memory chip is attached on the adhesive member and supported by the first pad and the second pad, wherein the plating seed layer and the first pad has a first width, wherein the second pad has a second width narrower than the first width. an insulating substrate; a circuit pattern on a first side and an opposite side of the insulating substrate; a solder resist formed on the insulating substrate to cover the circuit pattern on the first side and partially covering the circuit pattern on the opposite side of the insulating substrate, wherein the solder resist on the opposite side of the insulating substrate, has at least one opening to expose a surface of the circuit pattern on the opposite side of the insulating substrate, characterized by further comprising: a plating seed layer on the solder resist on the first side of the insulating substrate while protruding from a surface of the solder resist having a lower width and an upper width equal to each other; a first pad on the plating seed layer and having a lower width and an upper width equal to each other; a second pad on the first pad and having a lower width and an upper width equal to each other; and an adhesive member on the second pad, wherein a bottom surface of the plating seed layer is directly brought into contact with the top surface of the solder resist; wherein the opening of the solder resist on the opposite side of the insulation substrate has a width narrower than that of the circuit pattern, and an edge region of the circuit pattern is covered by the solder resist, wherein the solder resist on the opposite side of the insulating substrate is exposed to an outside, wherein a memory chip is attached on the adhesive member and supported by the first pad and the second pad, wherein the plating seed layer and the first pad has a first width, wherein the second pad has a second width narrower than the first width. a plating seed layer on the solder resist on the first side of the insulating substrate while protruding from a surface of the solder resist having a lower width and an upper width equal to each other; a first pad on the plating seed layer and having a lower width and an upper width equal to each other; a second pad on the first pad and having a lower width and an upper width equal to each other; and an adhesive member on the second pad, wherein a bottom surface of the plating seed layer is directly brought into contact with the top surface of the solder resist; wherein the opening of the solder resist on the opposite side of the insulation substrate has a width narrower than that of the circuit pattern, and an edge region of the circuit pattern is covered by the solder resist, wherein the solder resist on the opposite side of the insulating substrate is exposed to an outside, wherein a memory chip is attached on the adhesive member and supported by the first pad and the second pad, wherein the plating seed layer and the first pad has a first width, wherein the second pad has a second width narrower than the first width.