An integrated circuit comprising: a programmable high-speed serial interface including a plurality of data channels; a plurality of channel circuits, each channel circuit being associated with a data channel of the plurality of data channels of the programmable high-speed serial interface, wherein each channel circuit comprises a physical media attachment, PMA, channel circuit and a physical coding sublayer, PCS, channel circuit; a plurality of PCS modules, wherein each PCS channel circuit is associated with one of the PCS modules, wherein each PCS module includes: a data aggregation module; a channel multiplexer circuit which connects the PCS channel circuits of multiple of the channel circuits to channel inputs of the data aggregation module, wherein the channel multiplexer circuit is programmable to provide data from a subset of the multiple channel circuits to the inputs of the data aggregation module; and a channel demultiplexer circuit which connects channel outputs of the data aggregation module to the PCS channel circuits of the multiple channel circuits, wherein the channel demultiplexer circuit is programmable to provide data from the outputs of the data aggregation module to said subset of the multiple channel circuits, wherein the multiple channel circuits include PCS channel circuits associated with the PCS module and further include one or more PCS channel circuits associated with a different PCS module of the plural PCS modules. a programmable high-speed serial interface including a plurality of data channels; a plurality of channel circuits, each channel circuit being associated with a data channel of the plurality of data channels of the programmable high-speed serial interface, wherein each channel circuit comprises a physical media attachment, PMA, channel circuit and a physical coding sublayer, PCS, channel circuit; a plurality of PCS modules, wherein each PCS channel circuit is associated with one of the PCS modules, wherein each PCS module includes: a data aggregation module; a channel multiplexer circuit which connects the PCS channel circuits of multiple of the channel circuits to channel inputs of the data aggregation module, wherein the channel multiplexer circuit is programmable to provide data from a subset of the multiple channel circuits to the inputs of the data aggregation module; and a channel demultiplexer circuit which connects channel outputs of the data aggregation module to the PCS channel circuits of the multiple channel circuits, wherein the channel demultiplexer circuit is programmable to provide data from the outputs of the data aggregation module to said subset of the multiple channel circuits, wherein the multiple channel circuits include PCS channel circuits associated with the PCS module and further include one or more PCS channel circuits associated with a different PCS module of the plural PCS modules. a data aggregation module; a channel multiplexer circuit which connects the PCS channel circuits of multiple of the channel circuits to channel inputs of the data aggregation module, wherein the channel multiplexer circuit is programmable to provide data from a subset of the multiple channel circuits to the inputs of the data aggregation module; and a channel demultiplexer circuit which connects channel outputs of the data aggregation module to the PCS channel circuits of the multiple channel circuits, wherein the channel demultiplexer circuit is programmable to provide data from the outputs of the data aggregation module to said subset of the multiple channel circuits, wherein the multiple channel circuits include PCS channel circuits associated with the PCS module and further include one or more PCS channel circuits associated with a different PCS module of the plural PCS modules.