A communication unit comprising: a plurality of cascaded devices wherein the plurality of cascaded devices comprises at least one master device and at least one slave device (920, 923) configured in a master-slave arrangement; wherein the communication unit is characterized in that the at least one master device and at least one slave device (920, 923) each comprise: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal, wherein the distributed reference clock signal comprises a system clock signal modulated with a frame start signal and re-create a system clock signal (988, 990) therefrom by demodulating the system clock signal from the frame start signal; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal based on an expected duty cycle and the frame start signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use the master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device and at least one slave device (920, 923). a plurality of cascaded devices wherein the plurality of cascaded devices comprises at least one master device and at least one slave device (920, 923) configured in a master-slave arrangement; wherein the communication unit is characterized in that the at least one master device and at least one slave device (920, 923) each comprise: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal, wherein the distributed reference clock signal comprises a system clock signal modulated with a frame start signal and re-create a system clock signal (988, 990) therefrom by demodulating the system clock signal from the frame start signal; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal based on an expected duty cycle and the frame start signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use the master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device and at least one slave device (920, 923). a demodulator circuit (964, 965) configured to receive a distributed reference clock signal, wherein the distributed reference clock signal comprises a system clock signal modulated with a frame start signal and re-create a system clock signal (988, 990) therefrom by demodulating the system clock signal from the frame start signal; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal based on an expected duty cycle and the frame start signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use the master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device and at least one slave device (920, 923).