A receiver circuit for extracting data from a serial data signal containing a data packet, wherein said data packet has a first or a second data packet format based on a selection signal, wherein said first data packet format has a first number of bits and said second data packet format has a second number of bits, wherein said second data packet format comprises the bits of said first data packet format followed by one or more additional bits, wherein said receiver circuit comprises: - one or more shift registers (REG; REGa, REGb) having a total number of bits being equal or greater than the number of bits of said second data packet format, each said shift register comprising at least one serial input; - a switching circuit (200; 200a, 200b) associated with said one or more shift registers (REG; REGa, REGb) and configured to selectively connect said serial data signal to one of said serial inputs of said one or more shift registers (REG; REGa, REGb) as a function of said selection signal, wherein: a) when said selection signal indicates that said first data packet format has been selected and once having received the bits of said first data packet format, the bits of said first data packet format are stored in given positions of said one or more shift registers (REG; REGa, REGb), and b) when said selection signal indicates that said second data packet format has been selected and once having received the bits of said second data packet format, the bits of said first data packet format included in said second data packet format are stored in said given positions of said one or more shift registers (REG; REGa, REGb). - one or more shift registers (REG; REGa, REGb) having a total number of bits being equal or greater than the number of bits of said second data packet format, each said shift register comprising at least one serial input; - a switching circuit (200; 200a, 200b) associated with said one or more shift registers (REG; REGa, REGb) and configured to selectively connect said serial data signal to one of said serial inputs of said one or more shift registers (REG; REGa, REGb) as a function of said selection signal, wherein: a) when said selection signal indicates that said first data packet format has been selected and once having received the bits of said first data packet format, the bits of said first data packet format are stored in given positions of said one or more shift registers (REG; REGa, REGb), and b) when said selection signal indicates that said second data packet format has been selected and once having received the bits of said second data packet format, the bits of said first data packet format included in said second data packet format are stored in said given positions of said one or more shift registers (REG; REGa, REGb). a) when said selection signal indicates that said first data packet format has been selected and once having received the bits of said first data packet format, the bits of said first data packet format are stored in given positions of said one or more shift registers (REG; REGa, REGb), and b) when said selection signal indicates that said second data packet format has been selected and once having received the bits of said second data packet format, the bits of said first data packet format included in said second data packet format are stored in said given positions of said one or more shift registers (REG; REGa, REGb).