A system on chip, SoC, with a configurable accelerator framework device arranged as a coprocessor, the configurable accelerator framework device comprising: a stream switch having a plurality of selectable input ports and a plurality of selectable output ports, each of the input ports of the plurality of input ports configurable at run time to unidirectionally pass data to any one or more of the output ports of the plurality of output ports via a stream link; a plurality of convolution accelerators (600, 600A, 600B), each one convolution accelerator of the plurality of convolution accelerators (600, 600A, 600B) configurable at run time to unidirectionally: receive input data via at least two of the plurality of stream switch output ports, and communicate output data via an input port of the stream switch, the configurable accelerator framework device further comprising: a plurality of direct memory access, DMA, engines, each of the DMA engines of the plurality of DMA engines coupled to said stream switch and configurable at run time to autonomously communicate data into the stream switch and thereby be coupled to an input port of the stream switch or out from the stream switch and thereby be coupled to an output port of the stream switch, and a memory device integrated in the SoC and arranged to store kernel data and feature data, wherein the kernel data and the feature data are associated with a convolutional neural network, the kernel data and the feature data communicated between the memory and at least one convolution accelerator of the plurality of convolution accelerators (600, 600A, 600B) via the plurality of DMA engines, control registers comprising first and second control registers, wherein said first control registers are arranged to control operations of the stream switch at run time, and said second control registers are arranged to control operations of the plurality of convolution accelerators (600, 600A, 600B) at run time. a stream switch having a plurality of selectable input ports and a plurality of selectable output ports, each of the input ports of the plurality of input ports configurable at run time to unidirectionally pass data to any one or more of the output ports of the plurality of output ports via a stream link; a plurality of convolution accelerators (600, 600A, 600B), each one convolution accelerator of the plurality of convolution accelerators (600, 600A, 600B) configurable at run time to unidirectionally: receive input data via at least two of the plurality of stream switch output ports, and communicate output data via an input port of the stream switch, receive input data via at least two of the plurality of stream switch output ports, and communicate output data via an input port of the stream switch, the configurable accelerator framework device further comprising: a plurality of direct memory access, DMA, engines, each of the DMA engines of the plurality of DMA engines coupled to said stream switch and configurable at run time to autonomously communicate data into the stream switch and thereby be coupled to an input port of the stream switch or out from the stream switch and thereby be coupled to an output port of the stream switch, and a memory device integrated in the SoC and arranged to store kernel data and feature data, wherein the kernel data and the feature data are associated with a convolutional neural network, the kernel data and the feature data communicated between the memory and at least one convolution accelerator of the plurality of convolution accelerators (600, 600A, 600B) via the plurality of DMA engines, control registers comprising first and second control registers, wherein said first control registers are arranged to control operations of the stream switch at run time, and said second control registers are arranged to control operations of the plurality of convolution accelerators (600, 600A, 600B) at run time. a plurality of direct memory access, DMA, engines, each of the DMA engines of the plurality of DMA engines coupled to said stream switch and configurable at run time to autonomously communicate data into the stream switch and thereby be coupled to an input port of the stream switch or out from the stream switch and thereby be coupled to an output port of the stream switch, and a memory device integrated in the SoC and arranged to store kernel data and feature data, wherein the kernel data and the feature data are associated with a convolutional neural network, the kernel data and the feature data communicated between the memory and at least one convolution accelerator of the plurality of convolution accelerators (600, 600A, 600B) via the plurality of DMA engines, control registers comprising first and second control registers, wherein said first control registers are arranged to control operations of the stream switch at run time, and said second control registers are arranged to control operations of the plurality of convolution accelerators (600, 600A, 600B) at run time.