A solid-state image sensor comprising: a pixel unit in which a plurality of pixels that performs photoelectric conversion is arranged in a matrix; and a pixel signal readout circuit that reads out pixel signals in units of a plurality of pixels from the pixel unit, wherein the pixel signal readout circuit includes: a plurality of comparators that is arranged in association with a column arrangement of the pixels, and is configured to compare a readout signal potential and a reference voltage, and further configured to make determination on the comparison and to output a determination signal; a plurality of counters configured to be controlled by outputs from the comparators and configured to count a comparison time of each associated comparators; through contact vias, TCVs for pixel signals are inserted between the plurality of comparators and the plurality of counters, wherein the through contact vias are arranged in a line adjacent to a longer edge of a circuit block of the plurality of comparators, and are adjacent to a longer edge of a circuit block of the plurality of counters; a first chip having mounted thereon an analog circuit; and a second chip having mounted thereon a digital circuit, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has mounted thereon at least the pixel unit and the circuit block of the plurality of comparators of the pixel signal readout circuit, the second chip has mounted thereon at least the circuit block of the plurality of counters of the pixel signal readout circuit. a pixel unit in which a plurality of pixels that performs photoelectric conversion is arranged in a matrix; and a pixel signal readout circuit that reads out pixel signals in units of a plurality of pixels from the pixel unit, wherein the pixel signal readout circuit includes: a plurality of comparators that is arranged in association with a column arrangement of the pixels, and is configured to compare a readout signal potential and a reference voltage, and further configured to make determination on the comparison and to output a determination signal; a plurality of counters configured to be controlled by outputs from the comparators and configured to count a comparison time of each associated comparators; a plurality of comparators that is arranged in association with a column arrangement of the pixels, and is configured to compare a readout signal potential and a reference voltage, and further configured to make determination on the comparison and to output a determination signal; a plurality of counters configured to be controlled by outputs from the comparators and configured to count a comparison time of each associated comparators; through contact vias, TCVs for pixel signals are inserted between the plurality of comparators and the plurality of counters, wherein the through contact vias are arranged in a line adjacent to a longer edge of a circuit block of the plurality of comparators, and are adjacent to a longer edge of a circuit block of the plurality of counters; a first chip having mounted thereon an analog circuit; and a second chip having mounted thereon a digital circuit, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has mounted thereon at least the pixel unit and the circuit block of the plurality of comparators of the pixel signal readout circuit, the second chip has mounted thereon at least the circuit block of the plurality of counters of the pixel signal readout circuit.