A multi-phase switched-mode power supply, the power supply comprising: a pair of input terminals (102, 104) for receiving an alternating current or direct current voltage input from an input power source; a pair of output terminals for supplying a direct current voltage output to a load; a first phase circuit coupled between the pair of input terminals (102, 104) and the pair of output terminals, the first phase circuit including a first inductor coupled with a first switch; a second phase circuit interleaved with the first phase circuit between the pair of input terminals (102, 104) and the pair of output terminals, the second phase circuit including a second inductor coupled with a second switch; and a control circuit configured to: output a first PWM signal to the first switch, the first PWM signal comprising a plurality of pulses, each pulse starting at a detection of a zero crossing of a current flowing through the first inductor; output a second PWM signal to the second switch, the second PWM signal comprising a plurality of pulses, each pulse starting at a detection of a zero crossing of a current flowing through the second inductor, wherein an on time of the second PWM signal is equal to an on time of the first PWM signal plus a fixed offset time period to allow the current reset point of the second phase to shift slowly over subsequent cycles; determine a period between two subsequent rising edges of the first PWM signal; generate an off trigger PWM signal between subsequent pulses of the first PWM signal, such that the start of a pulse of the off trigger PWM signal is at a phase shift, determined based on the previous determined period, from the start of a pulse of the first PWM signal; and change the second PWM signal to a logical low value when a falling edge of the off trigger PWM signal occurs while the second PWM signal has a logical high value. a pair of input terminals (102, 104) for receiving an alternating current or direct current voltage input from an input power source; a pair of output terminals for supplying a direct current voltage output to a load; a first phase circuit coupled between the pair of input terminals (102, 104) and the pair of output terminals, the first phase circuit including a first inductor coupled with a first switch; a second phase circuit interleaved with the first phase circuit between the pair of input terminals (102, 104) and the pair of output terminals, the second phase circuit including a second inductor coupled with a second switch; and a control circuit configured to: output a first PWM signal to the first switch, the first PWM signal comprising a plurality of pulses, each pulse starting at a detection of a zero crossing of a current flowing through the first inductor; output a second PWM signal to the second switch, the second PWM signal comprising a plurality of pulses, each pulse starting at a detection of a zero crossing of a current flowing through the second inductor, wherein an on time of the second PWM signal is equal to an on time of the first PWM signal plus a fixed offset time period to allow the current reset point of the second phase to shift slowly over subsequent cycles; determine a period between two subsequent rising edges of the first PWM signal; generate an off trigger PWM signal between subsequent pulses of the first PWM signal, such that the start of a pulse of the off trigger PWM signal is at a phase shift, determined based on the previous determined period, from the start of a pulse of the first PWM signal; and change the second PWM signal to a logical low value when a falling edge of the off trigger PWM signal occurs while the second PWM signal has a logical high value. output a first PWM signal to the first switch, the first PWM signal comprising a plurality of pulses, each pulse starting at a detection of a zero crossing of a current flowing through the first inductor; output a second PWM signal to the second switch, the second PWM signal comprising a plurality of pulses, each pulse starting at a detection of a zero crossing of a current flowing through the second inductor, wherein an on time of the second PWM signal is equal to an on time of the first PWM signal plus a fixed offset time period to allow the current reset point of the second phase to shift slowly over subsequent cycles; determine a period between two subsequent rising edges of the first PWM signal; generate an off trigger PWM signal between subsequent pulses of the first PWM signal, such that the start of a pulse of the off trigger PWM signal is at a phase shift, determined based on the previous determined period, from the start of a pulse of the first PWM signal; and change the second PWM signal to a logical low value when a falling edge of the off trigger PWM signal occurs while the second PWM signal has a logical high value.