A telecommunications satellite payload processing system comprising one or more identical generic integrated processor modules, each integrated processor module comprises a digital processing stage, wherein the number of individual integrated processor modules in the telecommunications satellite payload processing system is a function of the uplink (36, 50) and downlink (40, 52) antenna ports and the respective uplink and downlink bandwidth relative to the number of input and output ports (14 1-N, 22 1-M) and the respective input and output port bandwidth of the digital processor stage, wherein each digital processing stage comprises: a plurality of input ports (14 1-N) adapted to receive signals corresponding to an uplink (36, 50), each input port (14 1-N) having a predetermined bandwidth; a plurality of output ports (22 1-M) adapted to output signals corresponding to a downlink (40, 52), each output port (22 1-M) having a predetermined bandwidth; an A/D converter associated with each input port (14 1-N) and arranged to convert the uplink signal of a predetermined bandwidth (36, 50) to digital sample form; a D/A converter associated with each of the output ports (22 1-M) and arranged to convert a processed digital signal of a predetermined bandwidth to an analogue downlink signal (40, 52), said digital processing stage being characterised by further comprising digital processing means (42, 44, 46) comprising a plurality of frequency demultiplexers, each connected to one or more of the plurality of A/D converters and arranged to separate the sampled bandwidth of one or more of the sampled uplink signals (36, 50) into a plurality of channels, channel level processing means associated with each of the channels and arranged to route processed channels to any of the plurality of output ports (22 1-M), and a plurality of frequency multiplexers, each connected to the channel level processing means and to one or more of the plurality of D/A converters and arranged to combine a plurality of routed channels. a plurality of input ports (14 1-N) adapted to receive signals corresponding to an uplink (36, 50), each input port (14 1-N) having a predetermined bandwidth; a plurality of output ports (22 1-M) adapted to output signals corresponding to a downlink (40, 52), each output port (22 1-M) having a predetermined bandwidth; an A/D converter associated with each input port (14 1-N) and arranged to convert the uplink signal of a predetermined bandwidth (36, 50) to digital sample form; a D/A converter associated with each of the output ports (22 1-M) and arranged to convert a processed digital signal of a predetermined bandwidth to an analogue downlink signal (40, 52), said digital processing stage being characterised by further comprising digital processing means (42, 44, 46) comprising a plurality of frequency demultiplexers, each connected to one or more of the plurality of A/D converters and arranged to separate the sampled bandwidth of one or more of the sampled uplink signals (36, 50) into a plurality of channels, channel level processing means associated with each of the channels and arranged to route processed channels to any of the plurality of output ports (22 1-M), and a plurality of frequency multiplexers, each connected to the channel level processing means and to one or more of the plurality of D/A converters and arranged to combine a plurality of routed channels. a plurality of frequency demultiplexers, each connected to one or more of the plurality of A/D converters and arranged to separate the sampled bandwidth of one or more of the sampled uplink signals (36, 50) into a plurality of channels, channel level processing means associated with each of the channels and arranged to route processed channels to any of the plurality of output ports (22 1-M), and a plurality of frequency multiplexers, each connected to the channel level processing means and to one or more of the plurality of D/A converters and arranged to combine a plurality of routed channels.