A multi-level memory system comprising: a processor (100; 310) having a plurality of cores (101-104; 501) for executing instructions and processing data and one or more processor caches (120;150A; 503) for caching instructions and data according to a first cache management policy; a first-level memory (121,106-109; 144,150B,151A; 403-406; 510,518; 654,655,660,661) having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and a second-level memory (122,116-119; 142,151B,450-451; 519,530) having a second set of characteristics associated therewith, the second set of characteristics including: - second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, - non-volatility such that the second level memory maintains its content when power is removed, - random access and memory subsystem addressability such that instructions or data stored therein may be accessed at a granularity equivalent to a memory subsystem of the computer system; a memory controller (124; 512,515) to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller operable to designate a plurality of different modes of operation for the first level memory including: - a first mode in which the first-level memory operates as a memory cache for the second-level memory; and - a second mode in which the first-level memory is allocated a first address range of a system address space with the second-level memory being allocated a second address range of the system address space, wherein the first range and the second range represent the entire system address space, wherein in the first mode, the first-level memory (121; 144; 403-406; 510,518; 654,655,660,661) is organised into different caches dedicated to a particular system memory address range or a set of non-contiguous address ranges. a processor (100; 310) having a plurality of cores (101-104; 501) for executing instructions and processing data and one or more processor caches (120;150A; 503) for caching instructions and data according to a first cache management policy; a first-level memory (121,106-109; 144,150B,151A; 403-406; 510,518; 654,655,660,661) having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and a second-level memory (122,116-119; 142,151B,450-451; 519,530) having a second set of characteristics associated therewith, the second set of characteristics including: - second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, - non-volatility such that the second level memory maintains its content when power is removed, - random access and memory subsystem addressability such that instructions or data stored therein may be accessed at a granularity equivalent to a memory subsystem of the computer system; - second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, - non-volatility such that the second level memory maintains its content when power is removed, - random access and memory subsystem addressability such that instructions or data stored therein may be accessed at a granularity equivalent to a memory subsystem of the computer system; a memory controller (124; 512,515) to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller operable to designate a plurality of different modes of operation for the first level memory including: - a first mode in which the first-level memory operates as a memory cache for the second-level memory; and - a second mode in which the first-level memory is allocated a first address range of a system address space with the second-level memory being allocated a second address range of the system address space, - a first mode in which the first-level memory operates as a memory cache for the second-level memory; and - a second mode in which the first-level memory is allocated a first address range of a system address space with the second-level memory being allocated a second address range of the system address space, wherein the first range and the second range represent the entire system address space, wherein in the first mode, the first-level memory (121; 144; 403-406; 510,518; 654,655,660,661) is organised into different caches dedicated to a particular system memory address range or a set of non-contiguous address ranges.