A digital isolator for receiving a digital signal D, with reference to a first ground G1, and providing corresponding signals to output node R and output node S with reference to a second ground G2, comprising - a logic module for receiving said digital signal D, and for providing first and second command signal, said logic module comprising a clock generator generating a clock signal CLK having a period T0; - a first sawtooth modulator STM1 for receiving said first command signals, and configured for providing a first sawtooth signal at a node A1, said first sawtooth signal having a fast rising edge triggered by a rising edge of the clock signal CLK, followed by a slow falling edge, when D equals 1 and said first sawtooth signal having a fast falling edge triggered by a rising edge of the clock signal CLK, followed by a slow rising edge, when D equals 0; - a second sawtooth modulator STM2 for receiving said second command signals, and configured for providing a second sawtooth signal at a node A2, said second sawtooth signal having a fast falling edge triggered by a rising edge of the clock signal CLK, followed by a slow rising edge, when D equals 1 and a fast rising edge triggered by a rising edge of the clock signal CLK, followed by a slow falling edge, when D equals 0; - a first isolation capacitor connected to said node A1, and to a node B1; - a first dipole Z1 connected between said node B1 and a bias voltage source with reference to a second ground G2; - a second isolation capacitor connected to said node A2, and to a node B2; - a second dipole Z2 connected between said node B2 and said bias voltage source; - a first threshold comparator having a first input connected to said node B1, and a second input connected to said node B2, producing a logical 1 output S when its first input exceeds its second input by a threshold Th1, and logical 0 output otherwise; - a second threshold comparator having a first input connected to said node B2, and a second input connected to said node B1, producing a logical 1 output R when its first input exceeds its second input by a threshold Th2, and a logical 0 output otherwise. - a logic module for receiving said digital signal D, and for providing first and second command signal, said logic module comprising a clock generator generating a clock signal CLK having a period T0; - a first sawtooth modulator STM1 for receiving said first command signals, and configured for providing a first sawtooth signal at a node A1, said first sawtooth signal having a fast rising edge triggered by a rising edge of the clock signal CLK, followed by a slow falling edge, when D equals 1 and said first sawtooth signal having a fast falling edge triggered by a rising edge of the clock signal CLK, followed by a slow rising edge, when D equals 0; - a second sawtooth modulator STM2 for receiving said second command signals, and configured for providing a second sawtooth signal at a node A2, said second sawtooth signal having a fast falling edge triggered by a rising edge of the clock signal CLK, followed by a slow rising edge, when D equals 1 and a fast rising edge triggered by a rising edge of the clock signal CLK, followed by a slow falling edge, when D equals 0; - a first isolation capacitor connected to said node A1, and to a node B1; - a first dipole Z1 connected between said node B1 and a bias voltage source with reference to a second ground G2; - a second isolation capacitor connected to said node A2, and to a node B2; - a second dipole Z2 connected between said node B2 and said bias voltage source; - a first threshold comparator having a first input connected to said node B1, and a second input connected to said node B2, producing a logical 1 output S when its first input exceeds its second input by a threshold Th1, and logical 0 output otherwise; - a second threshold comparator having a first input connected to said node B2, and a second input connected to said node B1, producing a logical 1 output R when its first input exceeds its second input by a threshold Th2, and a logical 0 output otherwise.