A method of manufacturing a thin film transistor, comprising: preparing a substrate (100, 300, 400); forming an amorphous silicon layer on the substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a metal catalyst; patterning the polycrystalline silicon layer to form a semiconductor layer (210, 320, 420); forming a gate insulating layer (220, 330, 430) on the semiconductor layer (210, 320, 420); forming a gate electrode (250, 350, 450) on the gate insulating layer (220, 330, 430); forming an interlayer insulating layer (260, 360, 460) which covers the gate electrode (250, 350, 450); etching the gate insulating layer (220, 330, 430) and the interlayer insulating layer (260, 360, 460) to form contact holes (270, 370, 470) exposing source and drain regions (211, 213, 321, 323, 421, 423) of the semiconductor layer (210, 320, 420); characterized in that forming a metal containing layer (280, 380, 480) which is formed of a metal layer, a metal silicide layer, or a double layer thereof, wherein the metal containing layer (280, 380, 480) is formed on the interlayer insulating layer (260, 360, 460) to cover a region where the contact holes (270, 370, 470) are formed; and annealing the substrate (100, 300, 400) such to form a metal silicide comprising a metal that is different from the metal catalyst within a region of the semiconductor layer (210, 320, 420) under the contact hole (270, 370, 470) from the surface of the semiconductor layer (210, 320, 420) to a predetermined depth thereby gettering the metal catalyst present in a channel region (212, 322, 422) of the semiconductor layer (210, 320, 420) into regions of the semiconductor layer (210, 320, 420) being in direct contact with the metal containing layer (280, 380, 480), further comprising forming a thermal oxidation (290, 385, 490) barrier on the metal containing layer (280, 380, 480) before annealing the substrate (100, 300, 400) and, after gettering the metal catalyst, removing the metal containing layer(280, 380, 480) and forming source and drain electrodes in contact with the source and drain regions of the semiconductor layer on the interlayer insulating layer. preparing a substrate (100, 300, 400); forming an amorphous silicon layer on the substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a metal catalyst; patterning the polycrystalline silicon layer to form a semiconductor layer (210, 320, 420); forming a gate insulating layer (220, 330, 430) on the semiconductor layer (210, 320, 420); forming a gate electrode (250, 350, 450) on the gate insulating layer (220, 330, 430); forming an interlayer insulating layer (260, 360, 460) which covers the gate electrode (250, 350, 450); etching the gate insulating layer (220, 330, 430) and the interlayer insulating layer (260, 360, 460) to form contact holes (270, 370, 470) exposing source and drain regions (211, 213, 321, 323, 421, 423) of the semiconductor layer (210, 320, 420); characterized in that forming a metal containing layer (280, 380, 480) which is formed of a metal layer, a metal silicide layer, or a double layer thereof, wherein the metal containing layer (280, 380, 480) is formed on the interlayer insulating layer (260, 360, 460) to cover a region where the contact holes (270, 370, 470) are formed; and annealing the substrate (100, 300, 400) such to form a metal silicide comprising a metal that is different from the metal catalyst within a region of the semiconductor layer (210, 320, 420) under the contact hole (270, 370, 470) from the surface of the semiconductor layer (210, 320, 420) to a predetermined depth thereby gettering the metal catalyst present in a channel region (212, 322, 422) of the semiconductor layer (210, 320, 420) into regions of the semiconductor layer (210, 320, 420) being in direct contact with the metal containing layer (280, 380, 480), further comprising forming a thermal oxidation (290, 385, 490) barrier on the metal containing layer (280, 380, 480) before annealing the substrate (100, 300, 400) and, after gettering the metal catalyst, removing the metal containing layer(280, 380, 480) and forming source and drain electrodes in contact with the source and drain regions of the semiconductor layer on the interlayer insulating layer.