A correlated double sampling integrating circuit, comprising: a sampling and holding module, an integrating capacitor (Cf) and a feedback module; wherein the sampling and holding module comprises a third switch unit, a fourth switch unit, and a holding capacitor (Ci), a first terminal of the holding capacitor (Ci) being connected to a second terminal of the third switch unit and the fourth switch unit; and the feedback module comprises a first amplifier (112, 152) that is a first differential amplifier or a single-input and single-output amplifier, a second differential amplifier, a first switch unit and a second switch unit, wherein in a first connection mode, an input terminal of the first amplifier (112, 152) is respectively connected to a second terminal of the holding capacitor (Ci) and a first terminal of the integrating capacitor (Cf), a second terminal of the integrating capacitor (Cf) is connected to a first terminal of the second switch unit, a second terminal of the second switch unit is connected to an output terminal of the first amplifier (112, 152), an inverting input terminal of the second differential amplifier is connected to the first terminal of the second switch unit, a non-inverting input terminal of the second differential amplifier is connected to the second terminal of the second switch unit, and an output terminal of the second differential amplifier is connected to the input terminal of the first amplifier (112, 152) via the first switch unit; or wherein in a second connection mode, the input terminal of the first amplifier (112, 152) is respectively connected to the second terminal of the holding capacitor (Ci) and the first terminal of the second switch unit, and the second terminal of the second switch unit is connected to the first terminal of the integrating capacitor (Cf), the second terminal of the integrating capacitor (Cf) is connected to the output terminal of the first amplifier (112, 152), the inverting input terminal of the second differential amplifier is connected to the first terminal of the second switch unit, and the non-inverting input terminal of the second differential amplifier is connected to the second terminal of the second switch unit, and the output terminal of the second differential amplifier is connected to the input terminal of the first amplifier (112, 152) via the first switch unit; wherein at a resetting stage in which the first switch unit and the third switch unit are turned on, and the second switch unit and the fourth switch unit are turned off, a first input signal is sampled, and the sampled first input signal is held by the holding capacitor (Ci); at an integrating stage in which the first switch unit and the third switch unit are turned off, and the second switch unit and the fourth switch unit are turned on, a second input signal is sampled and charges corresponding to a difference between the sampled first input signal and the sampled second input signal are transferred to the integrating capacitor (Cf); and wherein at the resetting stage: in the first connection mode, a first feedback loop is formed by the second differential amplifier, the first switch unit and the integrating capacitor (Cf), and a second feedback loop is formed by the first amplifier (112, 152), the second differential amplifier, the first switch unit and the integrating capacitor (Cf), to control a node voltage generated at the resetting stage to be substantially equal to the node voltage generated at the integrating stage at nodes (1A, 1B, 2A, 2B) at which the integrating capacitor (Cf) and the feedback module are connected; in the second connection mode, a fourth feedback loop is formed by the second differential amplifier and the first switch unit, and a fifth feedback loop is formed by the first amplifier (112, 152), the integrating capacitor (Cf), the second differential amplifier and the first switch unit to control the node voltage generated at the resetting stage to be substantially equal to the node voltage generated at the integrating stage. in the first connection mode, a first feedback loop is formed by the second differential amplifier, the first switch unit and the integrating capacitor (Cf), and a second feedback loop is formed by the first amplifier (112, 152), the second differential amplifier, the first switch unit and the integrating capacitor (Cf), to control a node voltage generated at the resetting stage to be substantially equal to the node voltage generated at the integrating stage at nodes (1A, 1B, 2A, 2B) at which the integrating capacitor (Cf) and the feedback module are connected; in the second connection mode, a fourth feedback loop is formed by the second differential amplifier and the first switch unit, and a fifth feedback loop is formed by the first amplifier (112, 152), the integrating capacitor (Cf), the second differential amplifier and the first switch unit to control the node voltage generated at the resetting stage to be substantially equal to the node voltage generated at the integrating stage.