A non-volatile storage system, comprising: a substrate; a monolithic three dimensional array of variable resistance memory cells positioned above and not in the substrate; a plurality of signal lines (1002, 1006); a plurality of vertically oriented bit lines (1040, 1042, 1044, 1046, 1048) that are above and not in the substrate, the vertically oriented bit lines are connected to the array of memory cells; and a plurality of vertically oriented select devices (1010, 1012, 1014, 1016, 1018) that are above the substrate but not in the substrate, the vertically oriented select devices are connected to the vertically oriented bit lines and the signal lines; wherein: a first subset of the vertically oriented select devices (1016, 1018) are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (1010, 1012, 1014) are positioned below the vertically oriented bit lines, and characterised in that: each of the vertically oriented bit lines is connected to either a vertically oriented select device of the first subset or a vertically oriented select device of the second subset, such that every other vertically oriented bit line along a horizontal direction is connected to a vertically oriented select device of the first subset with the intervening vertically oriented bit lines along the horizontal direction being connected to vertically oriented select devices of the second subset and such that every other vertically oriented select device along the horizontal direction are positioned above the vertically oriented bit lines with intervening vertically oriented select devices positioned below the vertically oriented bit lines; and when the vertically oriented select devices are actuated the vertically oriented bit lines are in communication with the signal lines. a substrate; a monolithic three dimensional array of variable resistance memory cells positioned above and not in the substrate; a plurality of signal lines (1002, 1006); a plurality of vertically oriented bit lines (1040, 1042, 1044, 1046, 1048) that are above and not in the substrate, the vertically oriented bit lines are connected to the array of memory cells; and a plurality of vertically oriented select devices (1010, 1012, 1014, 1016, 1018) that are above the substrate but not in the substrate, the vertically oriented select devices are connected to the vertically oriented bit lines and the signal lines; wherein: a first subset of the vertically oriented select devices (1016, 1018) are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (1010, 1012, 1014) are positioned below the vertically oriented bit lines, and characterised in that: each of the vertically oriented bit lines is connected to either a vertically oriented select device of the first subset or a vertically oriented select device of the second subset, such that every other vertically oriented bit line along a horizontal direction is connected to a vertically oriented select device of the first subset with the intervening vertically oriented bit lines along the horizontal direction being connected to vertically oriented select devices of the second subset and such that every other vertically oriented select device along the horizontal direction are positioned above the vertically oriented bit lines with intervening vertically oriented select devices positioned below the vertically oriented bit lines; and when the vertically oriented select devices are actuated the vertically oriented bit lines are in communication with the signal lines. a first subset of the vertically oriented select devices (1016, 1018) are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (1010, 1012, 1014) are positioned below the vertically oriented bit lines, and characterised in that: each of the vertically oriented bit lines is connected to either a vertically oriented select device of the first subset or a vertically oriented select device of the second subset, such that every other vertically oriented bit line along a horizontal direction is connected to a vertically oriented select device of the first subset with the intervening vertically oriented bit lines along the horizontal direction being connected to vertically oriented select devices of the second subset and such that every other vertically oriented select device along the horizontal direction are positioned above the vertically oriented bit lines with intervening vertically oriented select devices positioned below the vertically oriented bit lines; and when the vertically oriented select devices are actuated the vertically oriented bit lines are in communication with the signal lines. each of the vertically oriented bit lines is connected to either a vertically oriented select device of the first subset or a vertically oriented select device of the second subset, such that every other vertically oriented bit line along a horizontal direction is connected to a vertically oriented select device of the first subset with the intervening vertically oriented bit lines along the horizontal direction being connected to vertically oriented select devices of the second subset and such that every other vertically oriented select device along the horizontal direction are positioned above the vertically oriented bit lines with intervening vertically oriented select devices positioned below the vertically oriented bit lines; and when the vertically oriented select devices are actuated the vertically oriented bit lines are in communication with the signal lines.