Apparatus for processing data comprising: one or more translation buffers (16, 18, 20) to store respective address translation data to map received virtual addresses to translated addresses; and processing circuitry (4, 6, 8) to execute program instructions; wherein said processing circuitry is responsive to a translation buffer invalidation instruction within a sequence of program instructions executing using a given address translation context to broadcast translation buffer invalidation signals to said one or more translation buffers, and said translation buffer invalidation signals specify said given address translation context; wherein a given translation buffer among said one or more translation buffers stores a given buffer context data specifying an address translation context of a given address translation data stored within said given translation buffer; the apparatus for processing data further comprising context comparison circuitry associated with said given translation buffer to perform a comparison of said given buffer context data with said signals specifying said given address translation context; characterized in that said processing circuitry comprises a processing element using said given address translation data stored within said given translation buffer, said processing element supports transactional memory accesses whereby a transaction comprising program instructions bounded by a transaction start point and a transaction commit point is atomically executed and may be aborted prior to reaching said transaction commit point and return said apparatus to a state corresponding to said transaction start point; said processing element selectively aborts a pending transaction in dependence upon said comparison; and said processing element continues with said pending transaction when said given buffer context data differs from said signals specifying said given address translation context. one or more translation buffers (16, 18, 20) to store respective address translation data to map received virtual addresses to translated addresses; and processing circuitry (4, 6, 8) to execute program instructions; wherein said processing circuitry is responsive to a translation buffer invalidation instruction within a sequence of program instructions executing using a given address translation context to broadcast translation buffer invalidation signals to said one or more translation buffers, and said translation buffer invalidation signals specify said given address translation context; wherein a given translation buffer among said one or more translation buffers stores a given buffer context data specifying an address translation context of a given address translation data stored within said given translation buffer; the apparatus for processing data further comprising context comparison circuitry associated with said given translation buffer to perform a comparison of said given buffer context data with said signals specifying said given address translation context; characterized in that said processing circuitry comprises a processing element using said given address translation data stored within said given translation buffer, said processing element supports transactional memory accesses whereby a transaction comprising program instructions bounded by a transaction start point and a transaction commit point is atomically executed and may be aborted prior to reaching said transaction commit point and return said apparatus to a state corresponding to said transaction start point; said processing element selectively aborts a pending transaction in dependence upon said comparison; and said processing element continues with said pending transaction when said given buffer context data differs from said signals specifying said given address translation context.