A transmitter in a communication system, comprising: an interleaver for interleaving Low Density Parity Check, LDPC, codeword bits included in an LDPC codeword using an interleaving scheme and outputting the interleaved LDPC codeword bits, wherein a modulation symbol is being generated using a modulation scheme, wherein the modulation symbol has a difference in reliability characteristics between modulation symbol-constituting bits included in the modulation symbol, and the LDPC codeword bits are sequentially ordered beginning from a higher-degree; and a bit mapper for mapping the interleaved LDPC codeword bits using a mapping scheme to the modulation symbol-constituting bits, wherein the mapping scheme takes into account degrees of the interleaved LDPC codeword bits, the degrees being degrees of variable nodes which are mapped one-to-one to the interleaved LDPC codeword bits, and reliability characteristics of the modulation symbol-constituting bits, and wherein the mapping scheme maps the two highest-degree bits among the interleaved LDPC codeword bits to the two lowest-reliability bits among the modulation symbol-constituting bits, whereafter the mapping scheme maps, in an iterative manner, the two highest-degree bits among the still non-mapped interleaved LDPC codeword bits to the two highest-reliability bits among the remaining modulation symbol constituting bits until there are no non-mapped interleaved LDPC codeword bits, wherein the interleaver has N columns and M rows, N is equal to the size of the modulation symbol, and M is equal to a value obtained by dividing a size of the LDPC codeword by N, and wherein the LDPC codeword bits are written column-wise and the written LDPC codeword bits are read from the M rows in a forward direction, where the forward direction is in ascending column order, or in a reverse direction, where the reverse direction is in descending column order, and wherein the modulation scheme is 64-QAM or 256-QAM. an interleaver for interleaving Low Density Parity Check, LDPC, codeword bits included in an LDPC codeword using an interleaving scheme and outputting the interleaved LDPC codeword bits, wherein a modulation symbol is being generated using a modulation scheme, wherein the modulation symbol has a difference in reliability characteristics between modulation symbol-constituting bits included in the modulation symbol, and the LDPC codeword bits are sequentially ordered beginning from a higher-degree; and a bit mapper for mapping the interleaved LDPC codeword bits using a mapping scheme to the modulation symbol-constituting bits, wherein the mapping scheme takes into account degrees of the interleaved LDPC codeword bits, the degrees being degrees of variable nodes which are mapped one-to-one to the interleaved LDPC codeword bits, and reliability characteristics of the modulation symbol-constituting bits, and wherein the mapping scheme maps the two highest-degree bits among the interleaved LDPC codeword bits to the two lowest-reliability bits among the modulation symbol-constituting bits, whereafter the mapping scheme maps, in an iterative manner, the two highest-degree bits among the still non-mapped interleaved LDPC codeword bits to the two highest-reliability bits among the remaining modulation symbol constituting bits until there are no non-mapped interleaved LDPC codeword bits, wherein the interleaver has N columns and M rows, N is equal to the size of the modulation symbol, and M is equal to a value obtained by dividing a size of the LDPC codeword by N, and wherein the LDPC codeword bits are written column-wise and the written LDPC codeword bits are read from the M rows in a forward direction, where the forward direction is in ascending column order, or in a reverse direction, where the reverse direction is in descending column order, and wherein the modulation scheme is 64-QAM or 256-QAM.