An apparatus to control an external interface in an integrated circuit, the apparatus comprising: a first command queue configured to store a first plurality of commands, wherein the first command queue is further configured to store one or more indications identifying points within the first plurality of commands at which interruption of the first plurality of commands is permissible; and a second command queue configured to store a second plurality of commands; a control circuit coupled to the first command queue and the second command queue, characterized in that: the control circuit is configured to interrupt processing of the first plurality of commands at a first command identified as an interruptible point in response to detecting at least a second command in the second command queue, and wherein the control circuit is configured to initiate processing of the second command responsive to the interrupting; and a plurality of control registers coupled to the control circuit, wherein the control circuit is configured to update one of the plurality of control registers to indicate that the second plurality of commands are being processed, and wherein the control circuit is configured to inhibit processing of the first plurality of commands, even if the second command queue is empty of the second plurality of commands, until the one of the plurality of control registers is updated again to indicate that processing of the first plurality of commands is to be continued. a first command queue configured to store a first plurality of commands, wherein the first command queue is further configured to store one or more indications identifying points within the first plurality of commands at which interruption of the first plurality of commands is permissible; and a second command queue configured to store a second plurality of commands; a control circuit coupled to the first command queue and the second command queue, characterized in that: the control circuit is configured to interrupt processing of the first plurality of commands at a first command identified as an interruptible point in response to detecting at least a second command in the second command queue, and wherein the control circuit is configured to initiate processing of the second command responsive to the interrupting; and a plurality of control registers coupled to the control circuit, wherein the control circuit is configured to update one of the plurality of control registers to indicate that the second plurality of commands are being processed, and wherein the control circuit is configured to inhibit processing of the first plurality of commands, even if the second command queue is empty of the second plurality of commands, until the one of the plurality of control registers is updated again to indicate that processing of the first plurality of commands is to be continued. the control circuit is configured to interrupt processing of the first plurality of commands at a first command identified as an interruptible point in response to detecting at least a second command in the second command queue, and wherein the control circuit is configured to initiate processing of the second command responsive to the interrupting; and a plurality of control registers coupled to the control circuit, wherein the control circuit is configured to update one of the plurality of control registers to indicate that the second plurality of commands are being processed, and wherein the control circuit is configured to inhibit processing of the first plurality of commands, even if the second command queue is empty of the second plurality of commands, until the one of the plurality of control registers is updated again to indicate that processing of the first plurality of commands is to be continued.