A network receiver for a network (390, NW) using distributed clock synchronization, the network receiver comprising - an input configured to receive an input signal from the network, the input signal representing a series of bits, - an internal clock configured to generate a clock signal, the internal clock being configured to receive a frequency adjustment signal for adjusting a frequency of the clock signal, - a clock bit comparator configured to compare a length of a first time period lapsed while receiving at least five consecutive bits of the input signal with a length of an internal clock time interval being a sub-interval of the clock signal and representing the same number of bits as a number of bits of the first time period and the clock bit comparator being configured to generate a difference signal indicating a difference between the lengths of the first time period and the internal clock time interval, - an adjustment signal generator configured to receive the difference signal and configured to generate the frequency adjustment signal based on the difference signal for controlling the frequency of the clock signal towards a frequency which reduces the difference between the lengths of the first time period and the internal clock time interval, wherein the clock bit comparator comprises: - an edge distance measurer configured to determine a difference between a length of a second time period (406, 408) and a length of a third time period (412, 414) and configured to generate an error signal, the second time period being a period of time which starts when a falling edge is received in the input signal and ends when a consecutive falling edge is received in the input signal or which starts when a raising edge is received in the input signal and ends when a consecutive raising edge is received in the input signal, the third time period being a sub-interval of the clock signal and representing the same number of bits as the number of bits of the second time period, the error signal representing the difference between the lengths of the second time period and the third time period, - an error accumulator configured to receive the error signal and to generate the difference signal, wherein the error accumulator is configured to accumulate differences indicated by the error signals until the first time period of at least five consecutive bits of the signal is compared to the internal clock time interval that represents the same number of bits as the number of bits of the first time period, thereby the first time period being formed by a plurality of second time periods and the internal clock interval being formed by a plurality of third time periods. - an input configured to receive an input signal from the network, the input signal representing a series of bits, - an internal clock configured to generate a clock signal, the internal clock being configured to receive a frequency adjustment signal for adjusting a frequency of the clock signal, - a clock bit comparator configured to compare a length of a first time period lapsed while receiving at least five consecutive bits of the input signal with a length of an internal clock time interval being a sub-interval of the clock signal and representing the same number of bits as a number of bits of the first time period and the clock bit comparator being configured to generate a difference signal indicating a difference between the lengths of the first time period and the internal clock time interval, - an adjustment signal generator configured to receive the difference signal and configured to generate the frequency adjustment signal based on the difference signal for controlling the frequency of the clock signal towards a frequency which reduces the difference between the lengths of the first time period and the internal clock time interval, wherein the clock bit comparator comprises: - an edge distance measurer configured to determine a difference between a length of a second time period (406, 408) and a length of a third time period (412, 414) and configured to generate an error signal, the second time period being a period of time which starts when a falling edge is received in the input signal and ends when a consecutive falling edge is received in the input signal or which starts when a raising edge is received in the input signal and ends when a consecutive raising edge is received in the input signal, the third time period being a sub-interval of the clock signal and representing the same number of bits as the number of bits of the second time period, the error signal representing the difference between the lengths of the second time period and the third time period, - an error accumulator configured to receive the error signal and to generate the difference signal, wherein the error accumulator is configured to accumulate differences indicated by the error signals until the first time period of at least five consecutive bits of the signal is compared to the internal clock time interval that represents the same number of bits as the number of bits of the first time period, thereby the first time period being formed by a plurality of second time periods and the internal clock interval being formed by a plurality of third time periods.