A shifting register, comprising: a first thin film transistor, having a gate and a drain connected together to a signal input terminal(Input), and a source connected to a first node which is a pull-up node; a second thin film transistor, having a gate connected to a reset signal terminal(Reset), a drain connected to the first node, and a source connected to a low level signal terminal; a third thin film transistor, having a gate connected to the first node, a drain connected to a first clock signal terminal of a clock signal port(CLK, CLKB), and a source connected to a signal output terminal(Output); a fourth thin film transistor, having a gate connected to the reset signal terminal, a drain connected to the signal output terminal, and a source connected to the low level signal terminal; a capacitor, being connected between the first node and the signal output terminal; and a pull-down module, being connected to the clock signal port, the first node and the signal output terminal, and further connected to the low level signal terminal, configured to maintain the first node and the signal output terminal to be at low level during a non-working period of the shifting register; wherein the pull-down module comprises: a fifth thin film transistor, having a gate and a drain connected together to the clock signal port, and a source connected to a second node which is a pull-down node; a sixth thin film transistor, having a gate connected to the first node, a drain connected to the second node, and a source connected to the low level signal terminal; a seventh thin film transistor, having a gate connected to the second node, a drain connected to the first node, and a source connected to the low level signal terminal; and an eighth thin film transistor, having a gate connected to the second node, a drain connected to the signal output terminal, and a source connected to the low level signal terminal; characterized in that the shifting register further comprises: a ninth thin film transistor, having a gate directly connected to the drain of the third thin film transistor, a drain connected to the second node, and a source connected to the low level signal terminal, the first clock signal terminal being at a low level when the signal input terminal is at a high level. a first thin film transistor, having a gate and a drain connected together to a signal input terminal(Input), and a source connected to a first node which is a pull-up node; a second thin film transistor, having a gate connected to a reset signal terminal(Reset), a drain connected to the first node, and a source connected to a low level signal terminal; a third thin film transistor, having a gate connected to the first node, a drain connected to a first clock signal terminal of a clock signal port(CLK, CLKB), and a source connected to a signal output terminal(Output); a fourth thin film transistor, having a gate connected to the reset signal terminal, a drain connected to the signal output terminal, and a source connected to the low level signal terminal; a capacitor, being connected between the first node and the signal output terminal; and a pull-down module, being connected to the clock signal port, the first node and the signal output terminal, and further connected to the low level signal terminal, configured to maintain the first node and the signal output terminal to be at low level during a non-working period of the shifting register; wherein the pull-down module comprises: a fifth thin film transistor, having a gate and a drain connected together to the clock signal port, and a source connected to a second node which is a pull-down node; a sixth thin film transistor, having a gate connected to the first node, a drain connected to the second node, and a source connected to the low level signal terminal; a seventh thin film transistor, having a gate connected to the second node, a drain connected to the first node, and a source connected to the low level signal terminal; and an eighth thin film transistor, having a gate connected to the second node, a drain connected to the signal output terminal, and a source connected to the low level signal terminal; a fifth thin film transistor, having a gate and a drain connected together to the clock signal port, and a source connected to a second node which is a pull-down node; a sixth thin film transistor, having a gate connected to the first node, a drain connected to the second node, and a source connected to the low level signal terminal; a seventh thin film transistor, having a gate connected to the second node, a drain connected to the first node, and a source connected to the low level signal terminal; and an eighth thin film transistor, having a gate connected to the second node, a drain connected to the signal output terminal, and a source connected to the low level signal terminal; characterized in that the shifting register further comprises: a ninth thin film transistor, having a gate directly connected to the drain of the third thin film transistor, a drain connected to the second node, and a source connected to the low level signal terminal, the first clock signal terminal being at a low level when the signal input terminal is at a high level.