A method in a data processing system for managing the execution of a plurality of memory instructions associated with a program, the program having a plurality of instructions organized in program order, whereby the data processing system may execute the instructions in an execution order which does not correspond to, but is at least consistent with, the program order, the method comprising the steps of: assigning a first group identifier to a first memory instruction and to a second memory instruction, wherein the second memory instruction appears in the program after the first memory instruction and is related to the first memory instruction because it accesses the same memory location, address or bank of addresses, but wherein the second memory instruction is not dependent on the first memory instruction, in that executing the first and second memory instructions out of program order does not generate a result that is inconsistent with execution in program order; assigning a second group identifier to a third memory instruction appearing in the program after the first memory instruction of the plurality of memory instructions, wherein the third memory instruction is not related to the first and second memory instructions; wherein the second group identifier is different from the first group identifier; and providing a memory barrier instruction associated with the first memory instruction and having the first group identifier such that one or more processors with access to the program execute the plurality of memory instructions of the program in accordance with the memory barrier instruction having the first group identifier, wherein the memory barrier instruction provides an order constraint between memory instructions such that the second memory instruction having the same first group identifier as the first memory instruction is blocked until the first memory instruction has completed, while the third memory instruction having the second, different group identifier can be performed in parallel with the first memory instruction rather than being blocked. assigning a first group identifier to a first memory instruction and to a second memory instruction, wherein the second memory instruction appears in the program after the first memory instruction and is related to the first memory instruction because it accesses the same memory location, address or bank of addresses, but wherein the second memory instruction is not dependent on the first memory instruction, in that executing the first and second memory instructions out of program order does not generate a result that is inconsistent with execution in program order; assigning a second group identifier to a third memory instruction appearing in the program after the first memory instruction of the plurality of memory instructions, wherein the third memory instruction is not related to the first and second memory instructions; wherein the second group identifier is different from the first group identifier; and providing a memory barrier instruction associated with the first memory instruction and having the first group identifier such that one or more processors with access to the program execute the plurality of memory instructions of the program in accordance with the memory barrier instruction having the first group identifier, wherein the memory barrier instruction provides an order constraint between memory instructions such that the second memory instruction having the same first group identifier as the first memory instruction is blocked until the first memory instruction has completed, while the third memory instruction having the second, different group identifier can be performed in parallel with the first memory instruction rather than being blocked.