A method for forming a photonic integrated circuit (400, 500) comprising at least three photonic heterogeneous devices, the method comprising: forming, for the at least three heterogeneous devices, at least three respective silicon device waveguides (106, 451, 452, 453, 551, 552, 553) on a silicon semiconductor layer of a silicon-on-insulator wafer substrate (100, 402, 502); forming, for each of the at least three heterogeneous devices, a respective material stack (311, 312, 313, 314, 315, 410, 420, 430, 510, 520, 530) made from non-silicon semiconductor wafer substrates (201, 202, 203, 204, 205) comprising different respective non-silicon materials, each material stack including a plurality of nonsilicon device component layers, the plurality of nonsilicon device component layers of each material stack including a top contact layer (411, 421, 431, 511, 521, 531), a cladding layer (412, 422, 432, 512, 522, 532), an active layer (413, 423, 433, 513, 523, 533), and a bottom contact layer (414, 424, 434, 15 514, 524, 534); bonding, for each of the at least three heterogeneous devices, the respective material stack (410, 420, 430, 510, 520, 530) to the respective silicon device component of the silicon-on-insulator wafer substrate (100, 402, 502), thereby forming a plurality of bonded material stacks on the silicon-on-insulator wafer substrate (100, 402, 502); and performing, after bonding the respective materials stacks (410, 420, 430, 510, 520, 530) to the respective silicon device components of the silicon-on-insulator wafer substrate (100, 402, 502), a shared processing operation to process all of the plurality of bonded non-silicon device component layers to form the at least three heterogeneous devices, wherein the shared processing operation comprises a dry-etch operation, and wherein the compositions and layer thicknesses of the top contact layer (411, 421, 431), cladding layer (412, 422, 432), active layer (413, 423, 433), and bottom contact layer (414, 424, 434) of the plurality of bonded materials stacks (410, 420, 430) are configured such that when the shared processing operation is applied there are simultaneously defined combinations of deep and surface-type ridge structures in the device component stacks. forming, for the at least three heterogeneous devices, at least three respective silicon device waveguides (106, 451, 452, 453, 551, 552, 553) on a silicon semiconductor layer of a silicon-on-insulator wafer substrate (100, 402, 502); forming, for each of the at least three heterogeneous devices, a respective material stack (311, 312, 313, 314, 315, 410, 420, 430, 510, 520, 530) made from non-silicon semiconductor wafer substrates (201, 202, 203, 204, 205) comprising different respective non-silicon materials, each material stack including a plurality of nonsilicon device component layers, the plurality of nonsilicon device component layers of each material stack including a top contact layer (411, 421, 431, 511, 521, 531), a cladding layer (412, 422, 432, 512, 522, 532), an active layer (413, 423, 433, 513, 523, 533), and a bottom contact layer (414, 424, 434, 15 514, 524, 534); bonding, for each of the at least three heterogeneous devices, the respective material stack (410, 420, 430, 510, 520, 530) to the respective silicon device component of the silicon-on-insulator wafer substrate (100, 402, 502), thereby forming a plurality of bonded material stacks on the silicon-on-insulator wafer substrate (100, 402, 502); and performing, after bonding the respective materials stacks (410, 420, 430, 510, 520, 530) to the respective silicon device components of the silicon-on-insulator wafer substrate (100, 402, 502), a shared processing operation to process all of the plurality of bonded non-silicon device component layers to form the at least three heterogeneous devices, wherein the shared processing operation comprises a dry-etch operation, and wherein the compositions and layer thicknesses of the top contact layer (411, 421, 431), cladding layer (412, 422, 432), active layer (413, 423, 433), and bottom contact layer (414, 424, 434) of the plurality of bonded materials stacks (410, 420, 430) are configured such that when the shared processing operation is applied there are simultaneously defined combinations of deep and surface-type ridge structures in the device component stacks.