A method of facilitating instruction execution in a processing environment which is based on a first architecture, referred to as a native architecture, which emulates a second architecture, referred to as a guest architecture wherein the processing environment has a system architecture which includes a plurality of implementation layers including hardware, memory, a native operating system, an emulator, a guest operating system and one or more guest applications, wherein the emulator includes a central processing unit implementation which includes an interpretation unit which obtains, from memory, one or more instructions developed to be executed on the guest architecture, provides one or more instructions developed to be executed on the native architecture, and executes the one or more instructions developed to be executed on the native architecture, said method comprising: (a) initializing the interpretation unit by inputting to the interpretation unit: (i) a pointer which indicates a particular file or memory area that includes an instruction stream to be executed; (ii) an instruction counter for the instruction stream; and (iii) state information associated with the second architecture, including registers and flags; (b) evaluating the state information; (c) selecting one of a plurality of test sets (510, 511, 512, 514, 516, 518) to be processed based on the evaluate step; (d) performing the selected test set; (e) in response to the step (d), executing an instruction routine in mainline processing; (f) when the instruction routine completes, processing continues with a decode/dispatch routine, where a test is performed to determine whether mainline processing is to continue or whether one of the plurality of test sets is to be executed, where the test is a check as to whether the value of an end-of-range variable has been met; (g) if it is determined from the test that one of the plurality of test sets is to be executed, determining whether an instruction, to be handled by the test set is an execute instruction which specifies a target instruction that can be modified prior to execution, or an instruction crossing a page boundary; (h) in response to the step (g), providing a buffer with the instruction; (i) determining whether an aspect of the instruction in the buffer is to be modified; (j) modifying the aspect, in response to the determining step; and (k) redirecting an instruction pointer to the buffer in order to enable execution of the instruction from the buffer. (a) initializing the interpretation unit by inputting to the interpretation unit: (i) a pointer which indicates a particular file or memory area that includes an instruction stream to be executed; (ii) an instruction counter for the instruction stream; and (iii) state information associated with the second architecture, including registers and flags; (i) a pointer which indicates a particular file or memory area that includes an instruction stream to be executed; (ii) an instruction counter for the instruction stream; and (iii) state information associated with the second architecture, including registers and flags; (b) evaluating the state information; (c) selecting one of a plurality of test sets (510, 511, 512, 514, 516, 518) to be processed based on the evaluate step; (d) performing the selected test set; (e) in response to the step (d), executing an instruction routine in mainline processing; (f) when the instruction routine completes, processing continues with a decode/dispatch routine, where a test is performed to determine whether mainline processing is to continue or whether one of the plurality of test sets is to be executed, where the test is a check as to whether the value of an end-of-range variable has been met; (g) if it is determined from the test that one of the plurality of test sets is to be executed, determining whether an instruction, to be handled by the test set is an execute instruction which specifies a target instruction that can be modified prior to execution, or an instruction crossing a page boundary; (h) in response to the step (g), providing a buffer with the instruction; (i) determining whether an aspect of the instruction in the buffer is to be modified; (j) modifying the aspect, in response to the determining step; and (k) redirecting an instruction pointer to the buffer in order to enable execution of the instruction from the buffer.