A memory sharing circuit for sharing a memory (10, 100, 1000) of a controller for an electrical power system, the memory sharing circuit comprising: a plurality of processor units (20, 30, 200, 300, 2000, 3000), a memory (10, 100, 1000); and a logic circuit unit (41, 410, 4100); wherein each of the processor units (20, 30, 200, 300, 2000, 3000) includes a buffer (21, 31, 210, 310, 2100, 3100) configured to be connected to the memory through a buffering address and a data bus; and a processor (22, 32, 220, 320, 2200, 3200) configured to be connected to the buffer for access to the memory through the buffer, the memory sharing circuit characterized in that the buffer and the processor are configured to be paired through connecting to an address bus and a data bus of the processor, and where a particular bus among these buses may be used to receive and transmit an access request signal relative to the memory; wherein the processor outputs an access request into the buffer in advance of an access to the memory, and the buffer is connected to the logic circuit unit configured to allow only one of the processor units at a time to access to the memory by generating a logic value of a grant signal into an applicable processor (22, 32, 220, 320, 2200, 3200) to allow an access of the applicable processor to the memory and a logic value of an enable signal into an applicable buffer (21, 31, 210, 310, 2100, 3100) to activate an output of the access request of the applicable buffer, and wherein the enable signal of each of the buffer and the grant signal of each of the processor is determined using buffered access request signal outputted from the buffer to the logic circuit unit. a plurality of processor units (20, 30, 200, 300, 2000, 3000), a memory (10, 100, 1000); and a logic circuit unit (41, 410, 4100); wherein each of the processor units (20, 30, 200, 300, 2000, 3000) includes a buffer (21, 31, 210, 310, 2100, 3100) configured to be connected to the memory through a buffering address and a data bus; and a processor (22, 32, 220, 320, 2200, 3200) configured to be connected to the buffer for access to the memory through the buffer, the memory sharing circuit characterized in that the buffer and the processor are configured to be paired through connecting to an address bus and a data bus of the processor, and where a particular bus among these buses may be used to receive and transmit an access request signal relative to the memory; wherein the processor outputs an access request into the buffer in advance of an access to the memory, and the buffer is connected to the logic circuit unit configured to allow only one of the processor units at a time to access to the memory by generating a logic value of a grant signal into an applicable processor (22, 32, 220, 320, 2200, 3200) to allow an access of the applicable processor to the memory and a logic value of an enable signal into an applicable buffer (21, 31, 210, 310, 2100, 3100) to activate an output of the access request of the applicable buffer, and wherein the enable signal of each of the buffer and the grant signal of each of the processor is determined using buffered access request signal outputted from the buffer to the logic circuit unit.