A computer-implemented method for placing cells within a logic block area of a semiconductor chip, comprising: defining a first virtual grate for a first chip level within the logic block area of the semiconductor chip; defining a second virtual grate for a second chip level within the logic block area of the semiconductor chip, wherein the first and second virtual grates of the first and second chip levels are defined to have a rational spatial relationship, wherein each of a number of cell phases is defined by a first index value for the first chip level and by a second index value for the second chip level, wherein the first index value is equal to a first distance extending perpendicularly in a rightward direction from a left boundary of a given cell to a nearest virtual line of the first virtual grate, and wherein the second index value is equal to a second distance extending perpendicularly in the rightward direction from the left boundary of the given cell to a nearest virtual line of the second virtual grate; for each cell to be placed within the logic block area of the semiconductor chip, calculating index values for the first and second chip levels of the cell to be placed; comparing the calculated index values to corresponding index values of variants of the cell to be placed that exist within a cell library to identify a particular variant of the cell to be placed that has matching index values; and placing the identified particular variant of the cell within the logic block area of the semiconductor chip, such that layout features in each of the first and second chip levels within the particular variant of the cell align with the first and second virtual grates, respectively, of the first and second chip levels. defining a first virtual grate for a first chip level within the logic block area of the semiconductor chip; defining a second virtual grate for a second chip level within the logic block area of the semiconductor chip, wherein the first and second virtual grates of the first and second chip levels are defined to have a rational spatial relationship, wherein each of a number of cell phases is defined by a first index value for the first chip level and by a second index value for the second chip level, wherein the first index value is equal to a first distance extending perpendicularly in a rightward direction from a left boundary of a given cell to a nearest virtual line of the first virtual grate, and wherein the second index value is equal to a second distance extending perpendicularly in the rightward direction from the left boundary of the given cell to a nearest virtual line of the second virtual grate; for each cell to be placed within the logic block area of the semiconductor chip, calculating index values for the first and second chip levels of the cell to be placed; comparing the calculated index values to corresponding index values of variants of the cell to be placed that exist within a cell library to identify a particular variant of the cell to be placed that has matching index values; and placing the identified particular variant of the cell within the logic block area of the semiconductor chip, such that layout features in each of the first and second chip levels within the particular variant of the cell align with the first and second virtual grates, respectively, of the first and second chip levels.