A monolithic three dimensional memory array comprising at least two device levels disposed above a substrate wherein: a first device level comprises: a first plurality of spaced-apart conductive bit lines disposed at a first height above the substrate in a first direction; and characterised by a second plurality of spaced-apart rail-stacks disposed at a second height in a second direction different from the first direction, each rail-stack including: a plurality of semiconductor islands whose first surface is in contact with said first plurality of spaced-apart conductive bit lines; a first conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the first conductive word line; and source and drain regions (5243A, 5243B) located at contacting intersections between the first plurality of spaced-apart conductive bit lines and the second plurality of spaced-apart rail stacks; a second device level comprises: a third plurality of spaced-apart conductive bit lines disposed at a third height above the substrate in the first direction; and a fourth plurality of spaced-apart rail-stacks disposed at a fourth height in the second direction different from the first direction, each rail-stack including: a plurality of semiconductor Islands whose first surface Is in contact with said third plurality of spaced-apart conductive bit lines; a second conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the second conductive word line; and source and drain regions (5243A, 5243B) located at contacting intersections between the third plurality of spaced-apart conductive bit lines and the fourth plurality of spaced-apart rail stacks. a first device level comprises: a first plurality of spaced-apart conductive bit lines disposed at a first height above the substrate in a first direction; and characterised by a second plurality of spaced-apart rail-stacks disposed at a second height in a second direction different from the first direction, each rail-stack including: a plurality of semiconductor islands whose first surface is in contact with said first plurality of spaced-apart conductive bit lines; a first conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the first conductive word line; and source and drain regions (5243A, 5243B) located at contacting intersections between the first plurality of spaced-apart conductive bit lines and the second plurality of spaced-apart rail stacks; a first plurality of spaced-apart conductive bit lines disposed at a first height above the substrate in a first direction; and characterised by a second plurality of spaced-apart rail-stacks disposed at a second height in a second direction different from the first direction, each rail-stack including: a plurality of semiconductor islands whose first surface is in contact with said first plurality of spaced-apart conductive bit lines; a first conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the first conductive word line; and a plurality of semiconductor islands whose first surface is in contact with said first plurality of spaced-apart conductive bit lines; a first conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the first conductive word line; and source and drain regions (5243A, 5243B) located at contacting intersections between the first plurality of spaced-apart conductive bit lines and the second plurality of spaced-apart rail stacks; a second device level comprises: a third plurality of spaced-apart conductive bit lines disposed at a third height above the substrate in the first direction; and a fourth plurality of spaced-apart rail-stacks disposed at a fourth height in the second direction different from the first direction, each rail-stack including: a plurality of semiconductor Islands whose first surface Is in contact with said third plurality of spaced-apart conductive bit lines; a second conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the second conductive word line; and source and drain regions (5243A, 5243B) located at contacting intersections between the third plurality of spaced-apart conductive bit lines and the fourth plurality of spaced-apart rail stacks. a third plurality of spaced-apart conductive bit lines disposed at a third height above the substrate in the first direction; and a fourth plurality of spaced-apart rail-stacks disposed at a fourth height in the second direction different from the first direction, each rail-stack including: a plurality of semiconductor Islands whose first surface Is in contact with said third plurality of spaced-apart conductive bit lines; a second conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the second conductive word line; and a plurality of semiconductor Islands whose first surface Is in contact with said third plurality of spaced-apart conductive bit lines; a second conductive word line; and charge storage regions disposed between a second surface of the semiconductor islands and the second conductive word line; and source and drain regions (5243A, 5243B) located at contacting intersections between the third plurality of spaced-apart conductive bit lines and the fourth plurality of spaced-apart rail stacks.