A method for fabricating a semiconductor device, comprising: forming an interlayer dielectric layer on a base substrate, the base substrate having a PMOS region and an NMOS region; forming a plurality of first openings and second openings in the interlayer dielectric layer, each first opening connecting to a corresponding second opening, each first opening being between the corresponding second opening and the base substrate to expose the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming (s104-s108) an amorphous silicon layer on the cap layer; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K gate dielectric layer to cause the oxygen ions to diffuse into the high-K gate dielectric layer; removing the amorphous silicon layer; and forming a metal layer to fill the first openings and the second openings; characterised in that: the amorphous silicon layer is formed on the cap layer at least on the bottoms of the first openings; and forming the amorphous silicon layer comprises: forming an amorphous silicon film on the cap layer on the side and bottom surfaces of the first openings and the side surfaces of the second openings; forming (s105, s106) a filling layer to fill the first openings; etching portions of the amorphous silicon film on the side surfaces of the second openings using the filling layer as an etching mask; and removing the filling layer. forming an interlayer dielectric layer on a base substrate, the base substrate having a PMOS region and an NMOS region; forming a plurality of first openings and second openings in the interlayer dielectric layer, each first opening connecting to a corresponding second opening, each first opening being between the corresponding second opening and the base substrate to expose the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming (s104-s108) an amorphous silicon layer on the cap layer; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K gate dielectric layer to cause the oxygen ions to diffuse into the high-K gate dielectric layer; removing the amorphous silicon layer; and forming a metal layer to fill the first openings and the second openings; characterised in that: the amorphous silicon layer is formed on the cap layer at least on the bottoms of the first openings; and forming the amorphous silicon layer comprises: forming an amorphous silicon film on the cap layer on the side and bottom surfaces of the first openings and the side surfaces of the second openings; forming (s105, s106) a filling layer to fill the first openings; etching portions of the amorphous silicon film on the side surfaces of the second openings using the filling layer as an etching mask; and removing the filling layer. forming an amorphous silicon film on the cap layer on the side and bottom surfaces of the first openings and the side surfaces of the second openings; forming (s105, s106) a filling layer to fill the first openings; etching portions of the amorphous silicon film on the side surfaces of the second openings using the filling layer as an etching mask; and removing the filling layer.