A semiconductor device comprising a semiconductor substrate having an upper main surface and a lower main surface, said semiconductor substrate including: a drain layer of a first conductivity type formed in said upper main surface; a main base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface; and a source region of a first conductivity type selectively formed in said main base region to be shallower than said main base region and exposed to said upper main surface, said semiconductor device further comprising: a peripheral base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer, not having a semiconductor region of a first conductivity type provided therein and exposed to said upper main surface; a first main electrode connected to said main base region and said source region and said peripheral base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an underpad drain region, which is a region in said upper main surface to which said drain layer is exposed, with an insulating layer interposed therebetween, and connected to said gate electrode; a conductive layer buried in said insulating layer to be opposed to said upper main surface in a position closer to said upper main surface than said gate pad and connected to said gate pad; and a second main electrode connected to said lower main surface, characterized in that said peripheral base region is interposed between said main base region and said underpad drain region and said peripheral base region includes an annular portion formed continuously along an outer periphery of a region in said upper main surface which corresponds to a portion provided under said gate pad, wherein said conductive layer is opposed to said underpad drain region and is not opposed to said main base region and said conductive layer is extended to reach a portion provided above said peripheral base region. a drain layer of a first conductivity type formed in said upper main surface; a main base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface; and a source region of a first conductivity type selectively formed in said main base region to be shallower than said main base region and exposed to said upper main surface, said semiconductor device further comprising: a peripheral base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer, not having a semiconductor region of a first conductivity type provided therein and exposed to said upper main surface; a first main electrode connected to said main base region and said source region and said peripheral base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an underpad drain region, which is a region in said upper main surface to which said drain layer is exposed, with an insulating layer interposed therebetween, and connected to said gate electrode; a conductive layer buried in said insulating layer to be opposed to said upper main surface in a position closer to said upper main surface than said gate pad and connected to said gate pad; and a second main electrode connected to said lower main surface, characterized in that a peripheral base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer, not having a semiconductor region of a first conductivity type provided therein and exposed to said upper main surface; a first main electrode connected to said main base region and said source region and said peripheral base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an underpad drain region, which is a region in said upper main surface to which said drain layer is exposed, with an insulating layer interposed therebetween, and connected to said gate electrode; a conductive layer buried in said insulating layer to be opposed to said upper main surface in a position closer to said upper main surface than said gate pad and connected to said gate pad; and a second main electrode connected to said lower main surface, characterized in that said peripheral base region is interposed between said main base region and said underpad drain region and said peripheral base region includes an annular portion formed continuously along an outer periphery of a region in said upper main surface which corresponds to a portion provided under said gate pad, wherein said conductive layer is opposed to said underpad drain region and is not opposed to said main base region and said conductive layer is extended to reach a portion provided above said peripheral base region.