A processing system comprising: a microcontroller device; an external memory device external to the microcontroller device, the external memory device coupled to the microcontroller device; the microcontroller device including: bus masters (202, 204, 206, 207) configured to execute application codes; a random access memory, RAM, device internal to the microcontroller device and coupled to the bus masters via an interconnect, the RAM device including a system memory portion and an instruction portion, the instruction portion configured to store copies of a subset of load units from the external memory device for use by the application codes, wherein the load units include executable instructions and/or data, and are associated with a corresponding one of the application codes; wherein each load unit is specified by an address range corresponding to an address range in the external memory and at least two of the load units have different lengths; a cache controller device coupled to the random access memory and the external memory device and including load entity queues, each of the load entity queues is associated with one of the bus masters, the cache controller device configured to: manage a set of eviction candidates; periodically select an eviction candidate from the copies of the load units in the instruction portion; discard the eviction candidate if at least one of the load entity queues vetoes the eviction candidate; and replace the eviction candidate in the instruction portion with a copy of a requested load unit; wherein the load entity queues are adapted to store load unit information to identify relevant information for at least one load unit that is currently managed by a corresponding load entity queue. a microcontroller device; an external memory device external to the microcontroller device, the external memory device coupled to the microcontroller device; the microcontroller device including: bus masters (202, 204, 206, 207) configured to execute application codes; a random access memory, RAM, device internal to the microcontroller device and coupled to the bus masters via an interconnect, the RAM device including a system memory portion and an instruction portion, the instruction portion configured to store copies of a subset of load units from the external memory device for use by the application codes, wherein the load units include executable instructions and/or data, and are associated with a corresponding one of the application codes; wherein each load unit is specified by an address range corresponding to an address range in the external memory and at least two of the load units have different lengths; a cache controller device coupled to the random access memory and the external memory device and including load entity queues, each of the load entity queues is associated with one of the bus masters, the cache controller device configured to: manage a set of eviction candidates; periodically select an eviction candidate from the copies of the load units in the instruction portion; discard the eviction candidate if at least one of the load entity queues vetoes the eviction candidate; and replace the eviction candidate in the instruction portion with a copy of a requested load unit; wherein the load entity queues are adapted to store load unit information to identify relevant information for at least one load unit that is currently managed by a corresponding load entity queue. bus masters (202, 204, 206, 207) configured to execute application codes; a random access memory, RAM, device internal to the microcontroller device and coupled to the bus masters via an interconnect, the RAM device including a system memory portion and an instruction portion, the instruction portion configured to store copies of a subset of load units from the external memory device for use by the application codes, wherein the load units include executable instructions and/or data, and are associated with a corresponding one of the application codes; wherein each load unit is specified by an address range corresponding to an address range in the external memory and at least two of the load units have different lengths; a cache controller device coupled to the random access memory and the external memory device and including load entity queues, each of the load entity queues is associated with one of the bus masters, the cache controller device configured to: manage a set of eviction candidates; periodically select an eviction candidate from the copies of the load units in the instruction portion; discard the eviction candidate if at least one of the load entity queues vetoes the eviction candidate; and replace the eviction candidate in the instruction portion with a copy of a requested load unit; manage a set of eviction candidates; periodically select an eviction candidate from the copies of the load units in the instruction portion; discard the eviction candidate if at least one of the load entity queues vetoes the eviction candidate; and replace the eviction candidate in the instruction portion with a copy of a requested load unit; wherein the load entity queues are adapted to store load unit information to identify relevant information for at least one load unit that is currently managed by a corresponding load entity queue.