A unit pixel structure, comprising: a semiconductive stack having a front side and a back side opposite the front side, the semiconductive stack comprising: a first doped layer (11, 110); a second doped layer (12, 120) disposed over the first doped layer (11, 110); a third doped layer (13, 130) disposed over the second doped layer (12, 120); and a fourth doped layer (14, 140) disposed over the third doped layer (13, 130); a sensor well region formed within the fourth doped layer (14, 140); a floating diffusion region formed within the fourth doped layer (14, 140) and separate from the sensor well region; a first gate structure disposed over the semiconductive stack and positioned between the sensor well region and the floating diffusion region; and a second gate structure arranged around the floating diffusion region and extending through the third doped layer (13, 130), wherein the second gate structure comprises a gate electrode and a gate insulating layer surrounding the gate electrode; and wherein a doping concentration of the third doped layer (13, 130) is heavier than the fourth doped layer (14, 140); wherein the third doped layer is arranged between the floating diffusion region and the first photodiode so as to build a potential hump between the floating diffusion region and the first photodiode, wherein the first doped layer, the third doped layer, and the fourth doped layer are of a first dopant type and wherein the second layer is of a second dopant type, and wherein the third doped layer is entirely p-type or entirely n-type. a semiconductive stack having a front side and a back side opposite the front side, the semiconductive stack comprising: a first doped layer (11, 110); a second doped layer (12, 120) disposed over the first doped layer (11, 110); a third doped layer (13, 130) disposed over the second doped layer (12, 120); and a fourth doped layer (14, 140) disposed over the third doped layer (13, 130); a first doped layer (11, 110); a second doped layer (12, 120) disposed over the first doped layer (11, 110); a third doped layer (13, 130) disposed over the second doped layer (12, 120); and a fourth doped layer (14, 140) disposed over the third doped layer (13, 130); a sensor well region formed within the fourth doped layer (14, 140); a floating diffusion region formed within the fourth doped layer (14, 140) and separate from the sensor well region; a first gate structure disposed over the semiconductive stack and positioned between the sensor well region and the floating diffusion region; and a second gate structure arranged around the floating diffusion region and extending through the third doped layer (13, 130), wherein the second gate structure comprises a gate electrode and a gate insulating layer surrounding the gate electrode; and wherein a doping concentration of the third doped layer (13, 130) is heavier than the fourth doped layer (14, 140); wherein the third doped layer is arranged between the floating diffusion region and the first photodiode so as to build a potential hump between the floating diffusion region and the first photodiode, wherein the first doped layer, the third doped layer, and the fourth doped layer are of a first dopant type and wherein the second layer is of a second dopant type, and wherein the third doped layer is entirely p-type or entirely n-type.