A power source management method, used to suppress input disturbance of a power source and prevent a power source transformer biasing, wherein the power source comprises a full-bridge (Q1,Q2,Q3,Q4) topology circuit and a control circuit; the control circuit comprises a logic control circuit, a feedforward circuit, and a feedback circuit, a secondary side of the full-bridge topology circuit uses a full-wave rectifier circuit (S1, S2); characterized in that the feedforward circuit is configured to sample a center tap voltage of the full-wave rectifier circuit, charge a capacitor in the feedforward circuit by using the center tap voltage, and control, by using the logic control circuit, a feedforward circuit switching transistor to periodically discharge the capacitor in the feedforward circuit, to generate a sawtooth wave that corresponds to two bridge arms of the full-bridge topology circuit, and the sawtooth wave represents an input voltage of the power source; wherein different slopes of the sawtooth wave correspond to different input voltages of the power source; the feedforward circuit uses the sawtooth wave as a feedforward control signal; and the power source management method comprises: modulating, by using the sawtooth signal, a feedback control signal of the feedback circuit by using the logic control circuit, and performing matching, to obtain feedforward performance and additionally prevent biasing, which is specifically: comparing, the feedforward control signal with the feedback control signal by using the logic control circuit, and performing matching, to obtain control signals of switching transistors of the full-bridge topology circuit; and adjusting, the control signals of the switching transistors of the full-bridge topology circuit by using the logic control circuit, so that operating duty cycles of two bridge arms on a primary side match, to prevent the transformer biasing; wherein, the two bridge arms comprise a first bridge arm and a second bridge arm, wherein the first bridge arm is conducted within a first half period of a switch period of the logic control circuit, and the second bridge arm is conducted within a second half period of the switch period of the logic control circuit, and wherein the adjusting the control signals of the switching transistors of the full-bridge topology circuit by using the logic control circuit, so that operating duty cycles of two bridge arms on a primary side match comprises: within two adjacent switch periods of the logic control circuit, where the two adjacent switch periods of the logic control circuit are respectively a first period and a second period in a time sequence, if an operating duty cycle of the first bridge arm within a first half period of the second period is less than an operating duty cycle of the second bridge arm within a second half period of the first period, adjusting the control signal of the switching transistor of the first bridge arm by using the logic control circuit and based on a center tap voltage sampled within the second half period of the first period by the feedforward circuit, so that the operating duty cycle of the first bridge arm within the first half period of the second period is the same as the operating duty cycle of the second bridge arm within the second half period of the first period. comparing, the feedforward control signal with the feedback control signal by using the logic control circuit, and performing matching, to obtain control signals of switching transistors of the full-bridge topology circuit; and adjusting, the control signals of the switching transistors of the full-bridge topology circuit by using the logic control circuit, so that operating duty cycles of two bridge arms on a primary side match, to prevent the transformer biasing; wherein, the two bridge arms comprise a first bridge arm and a second bridge arm, wherein the first bridge arm is conducted within a first half period of a switch period of the logic control circuit, and the second bridge arm is conducted within a second half period of the switch period of the logic control circuit, and wherein the adjusting the control signals of the switching transistors of the full-bridge topology circuit by using the logic control circuit, so that operating duty cycles of two bridge arms on a primary side match comprises: within two adjacent switch periods of the logic control circuit, where the two adjacent switch periods of the logic control circuit are respectively a first period and a second period in a time sequence, if an operating duty cycle of the first bridge arm within a first half period of the second period is less than an operating duty cycle of the second bridge arm within a second half period of the first period, adjusting the control signal of the switching transistor of the first bridge arm by using the logic control circuit and based on a center tap voltage sampled within the second half period of the first period by the feedforward circuit, so that the operating duty cycle of the first bridge arm within the first half period of the second period is the same as the operating duty cycle of the second bridge arm within the second half period of the first period.