A direct memory access controller (22 i,j) intended to be placed in a computing node (C i,j) of a system on chip, comprising: - an input buffer (32 i,j) for receiving packets of data to be processed, coming from an input/output interface (14 i,j) of the computing node (C i,j), - a module (36 i,j) for controlling the writing of the data to be processed, extracted from each packet, in a local address space (20 i,j) of the computing node (C i,j), said local address space (20 i,j) being shared by at least one processor (16 i,j, 18 i,j) for processing said data other than the direct memory access controller (22 i,j), - an arithmetic logic unit (42 i,j) for executing microprograms, and - a storage register (44 i,j) for storing at least one microprogram, comprising at least one microprogram (46 i,j, 46 i,j, 46 i,j), stored in the register (44 i,j), consisting of instruction lines for arithmetic and/or logical calculation, the write control module (36 i,j) being designed to control the execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) by the arithmetic logic unit (42 i,j), wherein the instruction lines of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) concern only storage addresses (@d) for storing the data to be processed, received by the input buffer (32 i,j), for a reorganization of same in the shared local address space (20 i,j), and wherein at least two operating modes of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) stored in the register (44 i,j) are configurable: - a first restart mode in which each execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) on a packet of data to be processed starts in a new execution context, and - a second pause mode in which each execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) on a packet of data to be processed starts in an execution context of the preceding packet of data to be processed in the order of receipt of the packets by the input buffer (32 i,j). - an input buffer (32 i,j) for receiving packets of data to be processed, coming from an input/output interface (14 i,j) of the computing node (C i,j), - a module (36 i,j) for controlling the writing of the data to be processed, extracted from each packet, in a local address space (20 i,j) of the computing node (C i,j), said local address space (20 i,j) being shared by at least one processor (16 i,j, 18 i,j) for processing said data other than the direct memory access controller (22 i,j), - an arithmetic logic unit (42 i,j) for executing microprograms, and - a storage register (44 i,j) for storing at least one microprogram, comprising at least one microprogram (46 i,j, 46 i,j, 46 i,j), stored in the register (44 i,j), consisting of instruction lines for arithmetic and/or logical calculation, the write control module (36 i,j) being designed to control the execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) by the arithmetic logic unit (42 i,j), wherein the instruction lines of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) concern only storage addresses (@d) for storing the data to be processed, received by the input buffer (32 i,j), for a reorganization of same in the shared local address space (20 i,j), and wherein at least two operating modes of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) stored in the register (44 i,j) are configurable: - a first restart mode in which each execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) on a packet of data to be processed starts in a new execution context, and - a second pause mode in which each execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) on a packet of data to be processed starts in an execution context of the preceding packet of data to be processed in the order of receipt of the packets by the input buffer (32 i,j). - a first restart mode in which each execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) on a packet of data to be processed starts in a new execution context, and - a second pause mode in which each execution of said at least one microprogram (46 i,j, 46 i,j, 46 i,j) on a packet of data to be processed starts in an execution context of the preceding packet of data to be processed in the order of receipt of the packets by the input buffer (32 i,j).