An apparatus, comprising: a detector circuit to receive a time-varying differential communication signal, and including switched capacitors and an inverter to provide an indication of whether a level of the received communication signal is above or below a threshold value (Vth), wherein the capacitors include a first capacitor coupled to receive the communication signal and a second capacitor coupled to the inverter, the detector circuit further including: a first set of switches (S2, S3, S5), responsive to a first phase (Φ1) of a clock, to close to enable the first capacitor to store a voltage corresponding to the difference of first (Vin) and second (Vinb) signals of the communication signal and to enable the second capacitor to store a voltage corresponding to a difference between the threshold value (Vth) and a trip level (Vtrip) of the inverter; and a second set of switches (S1, S4), responsive to a second phase (Φ2) of the clock and that is an inverse to the first phase, to close to couple the first capacitor to the second capacitor to enable a difference between the stored voltages to be provided to the inverter, wherein the first set of switches is closed while the second set of switches is open and vice versa, and, optionally, wherein the first capacitor has a larger capacitance than a capacitance of the second capacitor. a detector circuit to receive a time-varying differential communication signal, and including switched capacitors and an inverter to provide an indication of whether a level of the received communication signal is above or below a threshold value (Vth), wherein the capacitors include a first capacitor coupled to receive the communication signal and a second capacitor coupled to the inverter, the detector circuit further including: a first set of switches (S2, S3, S5), responsive to a first phase (Φ1) of a clock, to close to enable the first capacitor to store a voltage corresponding to the difference of first (Vin) and second (Vinb) signals of the communication signal and to enable the second capacitor to store a voltage corresponding to a difference between the threshold value (Vth) and a trip level (Vtrip) of the inverter; and a second set of switches (S1, S4), responsive to a second phase (Φ2) of the clock and that is an inverse to the first phase, to close to couple the first capacitor to the second capacitor to enable a difference between the stored voltages to be provided to the inverter, wherein the first set of switches is closed while the second set of switches is open and vice versa, and, optionally, wherein the first capacitor has a larger capacitance than a capacitance of the second capacitor. a first set of switches (S2, S3, S5), responsive to a first phase (Φ1) of a clock, to close to enable the first capacitor to store a voltage corresponding to the difference of first (Vin) and second (Vinb) signals of the communication signal and to enable the second capacitor to store a voltage corresponding to a difference between the threshold value (Vth) and a trip level (Vtrip) of the inverter; and a second set of switches (S1, S4), responsive to a second phase (Φ2) of the clock and that is an inverse to the first phase, to close to couple the first capacitor to the second capacitor to enable a difference between the stored voltages to be provided to the inverter, wherein the first set of switches is closed while the second set of switches is open and vice versa, and, optionally, wherein the first capacitor has a larger capacitance than a capacitance of the second capacitor.