An integrated circuit, comprising: an analog-to-digital converter (104, 203a, 203b, 203c) operated according to a first clock signal, the first clock signal having a first frequency, the analog-to-digital converter (104, 203a, 203b, 203c) being a sigma-delta analog-to-digital converter, a digital filter of the analog-to-digital converter (104, 203a, 203b, 203c) having a frequency rejection band and the analog-to digital converter (104, 203a, 203b, 203c) producing a digital output signal based on an analog input signal; and a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a second frequency that is different from the first frequency of the first clock signal, wherein the second frequency, for operating the charge pump circuit, is selected to be within the frequency rejection band of the analog-to-digital converter's (104, 203a, 203b, 203c) digital filter and within rejection nulls of the analog-to-digital converter's (104, 203a, 203b, 203c) digital filter, such that a noise effect on the digital output signal of noise introduced by the charge pump circuit is attenuated by the frequency rejection of the analog-to-digital converter (104, 203a, 203b, 203c); wherein the integrated circuit further comprises a frequency divider circuit that receives a master clock signal and that, based on the master clock signal, generates both the first clock signal and the second clock signal; and wherein the ratio of the master clock signal frequency to the frequency of the second clock signal is a prime number. an analog-to-digital converter (104, 203a, 203b, 203c) operated according to a first clock signal, the first clock signal having a first frequency, the analog-to-digital converter (104, 203a, 203b, 203c) being a sigma-delta analog-to-digital converter, a digital filter of the analog-to-digital converter (104, 203a, 203b, 203c) having a frequency rejection band and the analog-to digital converter (104, 203a, 203b, 203c) producing a digital output signal based on an analog input signal; and a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a second frequency that is different from the first frequency of the first clock signal, wherein the second frequency, for operating the charge pump circuit, is selected to be within the frequency rejection band of the analog-to-digital converter's (104, 203a, 203b, 203c) digital filter and within rejection nulls of the analog-to-digital converter's (104, 203a, 203b, 203c) digital filter, such that a noise effect on the digital output signal of noise introduced by the charge pump circuit is attenuated by the frequency rejection of the analog-to-digital converter (104, 203a, 203b, 203c); wherein the integrated circuit further comprises a frequency divider circuit that receives a master clock signal and that, based on the master clock signal, generates both the first clock signal and the second clock signal; and wherein the ratio of the master clock signal frequency to the frequency of the second clock signal is a prime number.