A computer-implemented method of scheduling threads on a plurality of processing units (102-0, 102-1,..., 102-3) of a processor package, the computer-implemented method comprising: obtaining an idle state table of three or more idle states, C-states (C o, C 1,..., C n), including respective exit latencies for exiting from the C-states (C o, C 1,..., C n) to a C-state C o representing an operating state, and respective power requirements of processing units of the processor package at the C-states (C o, C 1,..., C n), wherein the C-states (C o, C 1,..., C n) include the C-state C o representing an operating state; obtaining a performance state table of three or more performance states, P-states (P o, P 1,..., P m) at the C-state C o, including respective performance levels representing an operating frequency and/or voltage of the processing units (102-0, 102-1,..., 102-3) at the P-states (P o, P 1,..., P m), and respective power requirements of the processing units (102-0, 102-1,..., 102-3) of the processor package at the P-states (P o, P 1,..., P m), for each processing unit (102-0, 102-1,..., 102-3) of the processor package, obtaining information about the current P-state (P o, P 1,..., P m) and the current C-state (C o, C 1,..., C n) of each of the processing units (102-0, 102-1,..., 102-3); creating a multi-level description of the processing units (102-0, 102-1,..., 102-3) of the processor package, wherein the multi-level description comprises, for each of the processing units (102-0, 102-1,..., 102-3), the current P-state (P o, P 1,..., P m) and the current C-state (C o, C 1,..., C n) of the respective processing unit (102-0, 102-1,..., 102-3), wherein the current P-state (P o, P 1,..., P m) is the current P-state (P o, P 1,..., P m) of the respective processing unit (102-0, 102-1,..., 102-3), if the current C-state (C o, C 1,..., C n) of the respective processing unit (102-0, 102-1,..., 102-3) is the C-state C o, and is the most recent P-state (P o, P 1,..., P m) of the respective processing unit (102-0, 102-1,..., 102-3), when the respective processing unit (102-0, 102-1,..., 102-3) was in the C-state C o last, if the current C-state (C o, C 1,..., C n) of the respective processing unit (102-0, 102-1,..., 102-3) is not the C-state C o; and scheduling a thread from a thread scheduler to a processing unit of the plurality of processing units (102-0, 102-1,..., 102-3) based on the current P-states (P o, P 1,..., P m) and current C-states (C o, C 1,..., C n) of the plurality of processing units (102-0, 102-1,..., 102-3) comprised by the multi-level description and based on the idle state table and the performance state table. obtaining an idle state table of three or more idle states, C-states (C o, C 1,..., C n), including respective exit latencies for exiting from the C-states (C o, C 1,..., C n) to a C-state C o representing an operating state, and respective power requirements of processing units of the processor package at the C-states (C o, C 1,..., C n), wherein the C-states (C o, C 1,..., C n) include the C-state C o representing an operating state; obtaining a performance state table of three or more performance states, P-states (P o, P 1,..., P m) at the C-state C o, including respective performance levels representing an operating frequency and/or voltage of the processing units (102-0, 102-1,..., 102-3) at the P-states (P o, P 1,..., P m), and respective power requirements of the processing units (102-0, 102-1,..., 102-3) of the processor package at the P-states (P o, P 1,..., P m), for each processing unit (102-0, 102-1,..., 102-3) of the processor package, obtaining information about the current P-state (P o, P 1,..., P m) and the current C-state (C o, C 1,..., C n) of each of the processing units (102-0, 102-1,..., 102-3); creating a multi-level description of the processing units (102-0, 102-1,..., 102-3) of the processor package, wherein the multi-level description comprises, for each of the processing units (102-0, 102-1,..., 102-3), the current P-state (P o, P 1,..., P m) and the current C-state (C o, C 1,..., C n) of the respective processing unit (102-0, 102-1,..., 102-3), wherein the current P-state (P o, P 1,..., P m) is the current P-state (P o, P 1,..., P m) of the respective processing unit (102-0, 102-1,..., 102-3), if the current C-state (C o, C 1,..., C n) of the respective processing unit (102-0, 102-1,..., 102-3) is the C-state C o, and is the most recent P-state (P o, P 1,..., P m) of the respective processing unit (102-0, 102-1,..., 102-3), when the respective processing unit (102-0, 102-1,..., 102-3) was in the C-state C o last, if the current C-state (C o, C 1,..., C n) of the respective processing unit (102-0, 102-1,..., 102-3) is not the C-state C o; and scheduling a thread from a thread scheduler to a processing unit of the plurality of processing units (102-0, 102-1,..., 102-3) based on the current P-states (P o, P 1,..., P m) and current C-states (C o, C 1,..., C n) of the plurality of processing units (102-0, 102-1,..., 102-3) comprised by the multi-level description and based on the idle state table and the performance state table.