A processor, comprising: a front end to receive an instruction specifying a size or a number of data elements in a data structure, wherein the data structure is organized in a tuple or an array of data elements as components; a source vector register configured to store data elements in multiple lanes including a first lane and a second lane within the source vector register, wherein each lane is configured to store at least two data elements; and wherein each lane stores like components from multiple data structures; a decoder to decode the instruction; a core configured to execute the instruction to: extract a respective first data element from each of the first and second lanes within the source vector register; extract a respective second data element from each of the first and second lanes within the source vector register, wherein: the first data element extracted from the first lane and the first data element extracted from the second lane represent a first component and a second component of a first data structure; and the second data element extracted from the first lane and the second data element extracted from the second lane represent a first component and a second component of a second data structure; write to the memory, including: compute, dependent on a value of a first element in an index register specified in the instruction, a first location in the memory at which to write the first and second components of the first data structure in contiguous locations; compute, dependent on a value of a second element in the index register, a second location in the memory at which to write the first and second components of the second data structure in contiguous locations; and write the first and second data structures out to the memory, beginning at the first and the second location respectively; a retirement unit configured to retire the instruction. a front end to receive an instruction specifying a size or a number of data elements in a data structure, wherein the data structure is organized in a tuple or an array of data elements as components; a source vector register configured to store data elements in multiple lanes including a first lane and a second lane within the source vector register, wherein each lane is configured to store at least two data elements; and wherein each lane stores like components from multiple data structures; a decoder to decode the instruction; a core configured to execute the instruction to: extract a respective first data element from each of the first and second lanes within the source vector register; extract a respective second data element from each of the first and second lanes within the source vector register, wherein: the first data element extracted from the first lane and the first data element extracted from the second lane represent a first component and a second component of a first data structure; and the second data element extracted from the first lane and the second data element extracted from the second lane represent a first component and a second component of a second data structure; write to the memory, including: compute, dependent on a value of a first element in an index register specified in the instruction, a first location in the memory at which to write the first and second components of the first data structure in contiguous locations; compute, dependent on a value of a second element in the index register, a second location in the memory at which to write the first and second components of the second data structure in contiguous locations; and extract a respective first data element from each of the first and second lanes within the source vector register; extract a respective second data element from each of the first and second lanes within the source vector register, wherein: the first data element extracted from the first lane and the first data element extracted from the second lane represent a first component and a second component of a first data structure; and the second data element extracted from the first lane and the second data element extracted from the second lane represent a first component and a second component of a second data structure; the first data element extracted from the first lane and the first data element extracted from the second lane represent a first component and a second component of a first data structure; and the second data element extracted from the first lane and the second data element extracted from the second lane represent a first component and a second component of a second data structure; write to the memory, including: compute, dependent on a value of a first element in an index register specified in the instruction, a first location in the memory at which to write the first and second components of the first data structure in contiguous locations; compute, dependent on a value of a second element in the index register, a second location in the memory at which to write the first and second components of the second data structure in contiguous locations; and compute, dependent on a value of a first element in an index register specified in the instruction, a first location in the memory at which to write the first and second components of the first data structure in contiguous locations; compute, dependent on a value of a second element in the index register, a second location in the memory at which to write the first and second components of the second data structure in contiguous locations; and write the first and second data structures out to the memory, beginning at the first and the second location respectively; a retirement unit configured to retire the instruction.