A memory, comprising: a first memory portion configured to store a first bit and generate a first data bit output, the first data bit output being a function of the first bit when a first read enable is active; a second memory portion configured to store a second bit and generate a second data bit output, the second data bit output being a function of the second bit when a second read enable is active; and a switch configured to select between the first and second bits for a read operation based on the first data bit output, the second data bit output, and feedback (708, 710) internal to the switch, wherein the switch comprises a latch including a first NAND gate having a first NAND gate first input, a first NAND gate second input, a first NAND gate third input, and a first NAND gate output, and a second NAND gate having a second NAND gate first input, a second NAND gate second input, a second NAND gate third input, and a second NAND gate output, the first NAND gate output coupled to the second NAND gate third input, and the second NAND gate output coupled to the first NAND gate third input to provide the feedback (708, 710) internal to the switch, the second NAND gate output coupled to an input of an inverter, the output of the inverter configured to output read data, the first NAND gate first input coupled to the inverted first data bit output (208,/DATAOUT1), the first NAND gate second input coupled to the second inverted data bit output (210,/DATAOUT2), the second NAND gate first input coupled to the first data bit output (208,DATAOUT1), the second NAND gate second input coupled to the second data bit output (210,DATAOUT2). a first memory portion configured to store a first bit and generate a first data bit output, the first data bit output being a function of the first bit when a first read enable is active; a second memory portion configured to store a second bit and generate a second data bit output, the second data bit output being a function of the second bit when a second read enable is active; and a switch configured to select between the first and second bits for a read operation based on the first data bit output, the second data bit output, and feedback (708, 710) internal to the switch, wherein the switch comprises a latch including a first NAND gate having a first NAND gate first input, a first NAND gate second input, a first NAND gate third input, and a first NAND gate output, and a second NAND gate having a second NAND gate first input, a second NAND gate second input, a second NAND gate third input, and a second NAND gate output, the first NAND gate output coupled to the second NAND gate third input, and the second NAND gate output coupled to the first NAND gate third input to provide the feedback (708, 710) internal to the switch, the second NAND gate output coupled to an input of an inverter, the output of the inverter configured to output read data, the first NAND gate first input coupled to the inverted first data bit output (208,/DATAOUT1), the first NAND gate second input coupled to the second inverted data bit output (210,/DATAOUT2), the second NAND gate first input coupled to the first data bit output (208,DATAOUT1), the second NAND gate second input coupled to the second data bit output (210,DATAOUT2).