Memory comprising a field effect transistor, said field effect transistor comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers (120, 125), wherein the inner semiconductor layer consists of Ga(As, Sb) and the two outer semiconductor layers (120, 125) consist of (Al, Ga)As, and a gate electrode adapted to apply a voltage to the strained double-heterostructure, said gate electrode facing one of said outer semiconductor layers, - wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers (120, 125), the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and - wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1,15 eV or higher and, - wherein the memory comprises a 2-dimensional hole gas layer capable of transporting holes for charging or discharging the at least one quantum dot, characterized in that - the at least one quantum dot provides an energy state density of at least three energy states per 1000 nm 3, all said at least three energy states being located in an energy band of 50 meV or less, - wherein a semiconductor superlattice is arranged between said 2-dimensional hole gas layer and the other one of said outer semiconductor layers, - wherein said semiconductor superlattice comprises at least two quantum wells (210, 220), each of which providing at least one energy state, - wherein the energetic positions of the energy states of the at least two quantum wells (210, 220) differ from another if the strained double-heterostructure is unbiased, - wherein the energy states of the at least two quantum wells (210, 220) are shiftable relative to each other and relative to the energy states of the at least one quantum dot in response to an external bias voltage to the strained double-heterostructure via said gate electrode, - wherein, in response to an erase voltage applied to the strained double-heterostructure via said gate electrode, the energy states of the at least two quantum wells (210, 220) are alignable such that holes can tunnel from the at least one quantum dot through the semiconductor superlattice based on resonant tunneling, and - wherein, in an unbiased state, the energy levels of the at least two quantum wells (210, 220) mismatch and resonance tunneling of holes is disabled. - wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers (120, 125), the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and - wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1,15 eV or higher and, - wherein the memory comprises a 2-dimensional hole gas layer capable of transporting holes for charging or discharging the at least one quantum dot, - the at least one quantum dot provides an energy state density of at least three energy states per 1000 nm 3, all said at least three energy states being located in an energy band of 50 meV or less, - wherein a semiconductor superlattice is arranged between said 2-dimensional hole gas layer and the other one of said outer semiconductor layers, - wherein said semiconductor superlattice comprises at least two quantum wells (210, 220), each of which providing at least one energy state, - wherein the energetic positions of the energy states of the at least two quantum wells (210, 220) differ from another if the strained double-heterostructure is unbiased, - wherein the energy states of the at least two quantum wells (210, 220) are shiftable relative to each other and relative to the energy states of the at least one quantum dot in response to an external bias voltage to the strained double-heterostructure via said gate electrode, - wherein, in response to an erase voltage applied to the strained double-heterostructure via said gate electrode, the energy states of the at least two quantum wells (210, 220) are alignable such that holes can tunnel from the at least one quantum dot through the semiconductor superlattice based on resonant tunneling, and - wherein, in an unbiased state, the energy levels of the at least two quantum wells (210, 220) mismatch and resonance tunneling of holes is disabled.