An apparatus comprising: an instruction decoder to decode instructions; and processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction within a thread of data processing by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions of the transaction until the transaction end instruction is reached, and to abort processing of the transaction when an abort event occurs before reaching the transaction end instruction; wherein in response to decoding of a transaction nesting depth testing instruction by the instruction decoder, the processing circuitry is configured to set at least one status value to one of a plurality of states selected dependent on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth equals a predetermined number greater than zero, and at least one further state selected when the transaction nesting depth is greater than or less than the predetermined number; and the instruction decoder is configured to support an instruction set architecture comprising at least one type of conditional branch instruction enabling the instruction decoder, in response to a single transaction nesting depth testing instruction followed by a single conditional branch instruction, to control the processing circuitry to set the at least one status value dependent on the transaction nesting depth and perform a conditional branch conditional on the at least one status value being in the first state. an instruction decoder to decode instructions; and processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction within a thread of data processing by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions of the transaction until the transaction end instruction is reached, and to abort processing of the transaction when an abort event occurs before reaching the transaction end instruction; wherein in response to decoding of a transaction nesting depth testing instruction by the instruction decoder, the processing circuitry is configured to set at least one status value to one of a plurality of states selected dependent on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth equals a predetermined number greater than zero, and at least one further state selected when the transaction nesting depth is greater than or less than the predetermined number; and the instruction decoder is configured to support an instruction set architecture comprising at least one type of conditional branch instruction enabling the instruction decoder, in response to a single transaction nesting depth testing instruction followed by a single conditional branch instruction, to control the processing circuitry to set the at least one status value dependent on the transaction nesting depth and perform a conditional branch conditional on the at least one status value being in the first state.