A high-electron-mobility transistor "HEMT" power device operating in enhancement mode "E-mode" comprising a depletion mode "D-mode" HEMT (2; 102; 202; 302) and a MOSFET transistor (3; 103; 203; 303) in cascade to the D-mode HEMT, the D-mode HEMT and the MOSFET transistor being integrated in a chip (51; 151; 251; 351), the power device comprising a base body (16; 116; 216; 316) of semiconductor material and a heterostructure layer (17; 117; 217; 317) superimposed on the base body, wherein the D-mode HEMT (2; 102; 202; 302) comprises a channel area formed in the heterostructure layer, and the MOSFET transistor (3; 103; 203; 303) comprises a first and a second conduction region (20, 21; 120, 220, 121; 221; 320,321), formed in the base body, and an insulated-gate region (33A, 33B; 133A, 133B, 233A, 233B; 333A, 333B), laterally and electrically insulated from the D-mode HEMT, the power device further comprising a first metal region (25; 125; 225; 325) laterally adjacent to the channel area and in electrical contact with the channel area and the first conduction region (20; 120; 220; 320), wherein: the heterostructure layer (17; 117; 217; 317) comprises a dielectric layer (12; 112; 212; 312) extending over the base body (16; 116; 216; 316); a channel layer (13; 113; 213; 313), extending over the dielectric layer; and a barrier layer (14; 114; 214; 314), extending over the channel layer; the base body has a first conductivity type and the first and the second conduction regions of the MOSFET transistor have a second conductivity type; and the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor comprises a gate-insulation region (33B; 133B; 233B; 333B) and a gate electrode (33A; 133A; 233A; 333A), laterally delimited by first and second electrical-insulation regions (30, 31; 130, 131; 230, 231; 330, 331) of insulating material, characterized in that: the first and the second conduction regions (20, 21; 120, 121; 220, 221; 320, 321) of the MOSFET transistor face the dielectric layer, the gate-insulation region (33B; 133B; 233B; 333B) of the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor is formed by a portion of the dielectric layer; the gate electrode (33A; 133A; 233A; 333A) of the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor is formed by a portion of the channel layer; the D-mode HEMT (2; 102; 202; 302) further comprises a second metal region (27; 127; 227; 327) extending through the barrier layer and in direct electrical contact with the channel layer; and the first metal region (25; 125; 225; 325) extends through the barrier layer, the channel layer and the dielectric layer. the heterostructure layer (17; 117; 217; 317) comprises a dielectric layer (12; 112; 212; 312) extending over the base body (16; 116; 216; 316); a channel layer (13; 113; 213; 313), extending over the dielectric layer; and a barrier layer (14; 114; 214; 314), extending over the channel layer; the base body has a first conductivity type and the first and the second conduction regions of the MOSFET transistor have a second conductivity type; and the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor comprises a gate-insulation region (33B; 133B; 233B; 333B) and a gate electrode (33A; 133A; 233A; 333A), laterally delimited by first and second electrical-insulation regions (30, 31; 130, 131; 230, 231; 330, 331) of insulating material, characterized in that: the first and the second conduction regions (20, 21; 120, 121; 220, 221; 320, 321) of the MOSFET transistor face the dielectric layer, the gate-insulation region (33B; 133B; 233B; 333B) of the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor is formed by a portion of the dielectric layer; the gate electrode (33A; 133A; 233A; 333A) of the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor is formed by a portion of the channel layer; the D-mode HEMT (2; 102; 202; 302) further comprises a second metal region (27; 127; 227; 327) extending through the barrier layer and in direct electrical contact with the channel layer; and the first metal region (25; 125; 225; 325) extends through the barrier layer, the channel layer and the dielectric layer. the first and the second conduction regions (20, 21; 120, 121; 220, 221; 320, 321) of the MOSFET transistor face the dielectric layer, the gate-insulation region (33B; 133B; 233B; 333B) of the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor is formed by a portion of the dielectric layer; the gate electrode (33A; 133A; 233A; 333A) of the insulated-gate region (33A, 33B; 133A, 133B; 233A, 233B; 333A, 333B) of the MOSFET transistor is formed by a portion of the channel layer; the D-mode HEMT (2; 102; 202; 302) further comprises a second metal region (27; 127; 227; 327) extending through the barrier layer and in direct electrical contact with the channel layer; and the first metal region (25; 125; 225; 325) extends through the barrier layer, the channel layer and the dielectric layer.