An analog-to-digital conversion circuit (120_1-120_K, 220, 320) for converting an analog signal (VA, VA 1 -VA K) into a digital signal, the analog-to-digital conversion circuit (120_1-120_K, 220, 320) comprising: a first comparator (232, 332), configured to compare the analog signal (VA, VA 1 -VA K) with a ramp signal to generate a first comparison signal; a second comparator (234, 334), configured to compare the analog signal (VA, VA 1 -VA K) with the ramp signal plus a predetermined offset (V OS) to generate a second comparison signal; and a first counter (242, 342), coupled to the first comparator (232, 332), wherein when the first comparison signal indicates that a signal level of the ramp signal is less than a signal level of the analog signal (VA, VA 1 -VA K), the first counter (242, 342) is configured to count a number of clock cycles of a first clock signal to generate a first count value; the first count value serves as a first portion of the digital signal; and a second counter (244, 344), coupled to the second comparator (232, 332), wherein when the second comparison signal indicates that the signal level of the ramp signal plus the predetermined offset (V OS) is greater than the signal level of the analog signal (VA, VA 1 -VA K), the second counter (244, 344) is configured to count a number of clock cycles of a second clock signal to increment a second count value; the second count value serves as a second portion of the digital signal; a frequency of the first clock signal is less than a frequency of the second clock signal; characterized in that: the second counter is configured such that before the first count value is incremented for the first time after the signal level of the ramp signal plus the predetermined offset (V OS) reaches the signal level of the analog signal (VA, VA 1 -VA K), the second counter is disabled from incrementing the second value; when the first count value is incremented for the first time after the signal level of the ramp signal plus the predetermined offset (V OS) reaches the signal level of the analog signal (VA, VA 1 -VA K), the second counter (244, 344) is configured to start counting the number of clock cycles of the second clock signal in response to a change of the first count value, and increment the second count value. a first comparator (232, 332), configured to compare the analog signal (VA, VA 1 -VA K) with a ramp signal to generate a first comparison signal; a second comparator (234, 334), configured to compare the analog signal (VA, VA 1 -VA K) with the ramp signal plus a predetermined offset (V OS) to generate a second comparison signal; and a first counter (242, 342), coupled to the first comparator (232, 332), wherein when the first comparison signal indicates that a signal level of the ramp signal is less than a signal level of the analog signal (VA, VA 1 -VA K), the first counter (242, 342) is configured to count a number of clock cycles of a first clock signal to generate a first count value; the first count value serves as a first portion of the digital signal; and a second counter (244, 344), coupled to the second comparator (232, 332), wherein when the second comparison signal indicates that the signal level of the ramp signal plus the predetermined offset (V OS) is greater than the signal level of the analog signal (VA, VA 1 -VA K), the second counter (244, 344) is configured to count a number of clock cycles of a second clock signal to increment a second count value; the second count value serves as a second portion of the digital signal; a frequency of the first clock signal is less than a frequency of the second clock signal; characterized in that: the second counter is configured such that before the first count value is incremented for the first time after the signal level of the ramp signal plus the predetermined offset (V OS) reaches the signal level of the analog signal (VA, VA 1 -VA K), the second counter is disabled from incrementing the second value; when the first count value is incremented for the first time after the signal level of the ramp signal plus the predetermined offset (V OS) reaches the signal level of the analog signal (VA, VA 1 -VA K), the second counter (244, 344) is configured to start counting the number of clock cycles of the second clock signal in response to a change of the first count value, and increment the second count value.