A method of forming sidewall spacers (56, 75A) on a memory device comprised of a memory array and at least one peripheral circuit, comprising: forming a first sidewall spacer (34, 56) adjacent a word line structure in said memory array, said first sidewall spacer (34, 56) being tapered in cross-section and having a first thickness of from 15-27 nm; and forming a second sidewall spacer adjacent a transistor structure in said at least one peripheral circuit, said second sidewall spacer (22, 66, 75, 75A) having a second thickness that is greater than said first thickness, and having an L-shape in the cross-section, wherein said first and second sidewall spacers (56, 75A) consist of material from a single layer of spacer material; wherein forming said first and second sidewall spacers (56, 75A) comprises: forming said layer of spacer material on an upper surface of a semiconducting substrate, above said word line structure in said memory array and above said transistor structure in said at least one peripheral circuit, the layer of spacer material contacting a LDD region of the substrate in the peripheral circuit; forming a masking layer above said layer of spacer material in said at least one peripheral circuit; performing an anisotropic etching process on said layer of spacer material formed above said word line structure to thereby define said first sidewall spacer (34, 56) having said first thickness; wherein the forming of the second sidewall spacer is performed by: removing said masking layer; forming a layer of material above said layer of spacer material adjacent said transistor structure and above said word line structure in said memory array, said layer of material being selectively etchable with respect to said layer of spacer material; and performing an anisotropic etching process on said layer of material to define a masking spacer adjacent said layer of spacer material that is adjacent said transistor structure in said peripheral circuit. forming a first sidewall spacer (34, 56) adjacent a word line structure in said memory array, said first sidewall spacer (34, 56) being tapered in cross-section and having a first thickness of from 15-27 nm; and forming a second sidewall spacer adjacent a transistor structure in said at least one peripheral circuit, said second sidewall spacer (22, 66, 75, 75A) having a second thickness that is greater than said first thickness, and having an L-shape in the cross-section, wherein said first and second sidewall spacers (56, 75A) consist of material from a single layer of spacer material; wherein forming said first and second sidewall spacers (56, 75A) comprises: forming said layer of spacer material on an upper surface of a semiconducting substrate, above said word line structure in said memory array and above said transistor structure in said at least one peripheral circuit, the layer of spacer material contacting a LDD region of the substrate in the peripheral circuit; forming a masking layer above said layer of spacer material in said at least one peripheral circuit; performing an anisotropic etching process on said layer of spacer material formed above said word line structure to thereby define said first sidewall spacer (34, 56) having said first thickness; wherein the forming of the second sidewall spacer is performed by: removing said masking layer; forming a layer of material above said layer of spacer material adjacent said transistor structure and above said word line structure in said memory array, said layer of material being selectively etchable with respect to said layer of spacer material; and performing an anisotropic etching process on said layer of material to define a masking spacer adjacent said layer of spacer material that is adjacent said transistor structure in said peripheral circuit. forming said layer of spacer material on an upper surface of a semiconducting substrate, above said word line structure in said memory array and above said transistor structure in said at least one peripheral circuit, the layer of spacer material contacting a LDD region of the substrate in the peripheral circuit; forming a masking layer above said layer of spacer material in said at least one peripheral circuit; performing an anisotropic etching process on said layer of spacer material formed above said word line structure to thereby define said first sidewall spacer (34, 56) having said first thickness; wherein the forming of the second sidewall spacer is performed by: removing said masking layer; forming a layer of material above said layer of spacer material adjacent said transistor structure and above said word line structure in said memory array, said layer of material being selectively etchable with respect to said layer of spacer material; and performing an anisotropic etching process on said layer of material to define a masking spacer adjacent said layer of spacer material that is adjacent said transistor structure in said peripheral circuit. removing said masking layer; forming a layer of material above said layer of spacer material adjacent said transistor structure and above said word line structure in said memory array, said layer of material being selectively etchable with respect to said layer of spacer material; and performing an anisotropic etching process on said layer of material to define a masking spacer adjacent said layer of spacer material that is adjacent said transistor structure in said peripheral circuit.