A memory controller that is connected to a memory module which is compliant with a DDR3 memory interface, the memory controller comprising: DQS control means for outputting a data strobe signal DQS to a memory element, the DQS control means being provided for each of the memory elements included in the memory module; DQ control means for signal DQS, outputting write data, and receiving read data in synchronization with the date strobe signal DQS, the DQ control means being provided for each of the memory element included in the memory module, and the data strobe signal DQS being output to the memory element; and write leveling control means for controlling write levelling, the write leveling being performed at the time of initialization, wherein the DQS control means comprises a DQS delay means (2422, 2424) for delaying an output timing of the data strobe signal DQS by a delay amount that is set by the write leveling control means, the DQ control means comprises a DQ delay means (2442, 2444) for delaying an output timing of the write data and a reception timing of the read data by the delay amount that is set by the write leveling control means, at the time of the write leveling, after adjustment of a delay amount of less than one clock cycle is performed on the DQS delay means and the DQ delay means, the write leveling control means compares a read data sequence, which is obtained by reading the read data sequence after writing an expected value data sequence and, with the expected value data sequence for each of the memory elements and adjusts the delay amount by a unit of a clock cycle in accordance with a result of a comparison for each of the DQS delay means and the DQ delay means, said memory controller being characterised in that at the time of the writing, the write leveling control means controls the DQS control means to output the data strobe signal DQS that is longer than a burst length, which is defined in a standard, by 2*M clock cycle, wherein M is an integer of one or greater clock cycle, and controls the DQ control means to add M pieces of data to a beginning and an end of the expected value data sequence, in which the number of data included in the expected value data sequence matches the burst length, and to output the expected value data sequence with the added data. DQS control means for outputting a data strobe signal DQS to a memory element, the DQS control means being provided for each of the memory elements included in the memory module; DQ control means for signal DQS, outputting write data, and receiving read data in synchronization with the date strobe signal DQS, the DQ control means being provided for each of the memory element included in the memory module, and the data strobe signal DQS being output to the memory element; and write leveling control means for controlling write levelling, the write leveling being performed at the time of initialization, wherein the DQS control means comprises a DQS delay means (2422, 2424) for delaying an output timing of the data strobe signal DQS by a delay amount that is set by the write leveling control means, the DQ control means comprises a DQ delay means (2442, 2444) for delaying an output timing of the write data and a reception timing of the read data by the delay amount that is set by the write leveling control means, at the time of the write leveling, after adjustment of a delay amount of less than one clock cycle is performed on the DQS delay means and the DQ delay means, the write leveling control means compares a read data sequence, which is obtained by reading the read data sequence after writing an expected value data sequence and, with the expected value data sequence for each of the memory elements and adjusts the delay amount by a unit of a clock cycle in accordance with a result of a comparison for each of the DQS delay means and the DQ delay means, said memory controller being characterised in that at the time of the writing, the write leveling control means controls the DQS control means to output the data strobe signal DQS that is longer than a burst length, which is defined in a standard, by 2*M clock cycle, wherein M is an integer of one or greater clock cycle, and controls the DQ control means to add M pieces of data to a beginning and an end of the expected value data sequence, in which the number of data included in the expected value data sequence matches the burst length, and to output the expected value data sequence with the added data.