An apparatus comprising: a gate drive circuit for producing a first gate drive signal on a gate drive output wherein said first gate drive signal comprises an ON state and an OFF state; a first semiconductor switching device having a first gate, a first drain, and a first source; a second semiconductor switching device having a second gate, a second drain, and a second source, said second semiconductor switching device having a first turn-on time that is less than a second turn-on time associated with said first semiconductor switching device; said first and second semiconductor switching devices (234, 226) being connected in a parallel arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected, wherein said first gate of said first semiconductor switching device is connected to said first gate drive output of said gate drive circuit to receive said first gate drive signal; and a pulse former coupled between said gate drive output and said second gate of said second semiconductor switching device for producing a second gate drive signal comprising an ON state and an OFF state, said pulse former being configured to generate: (i) said second gate drive signal as a first pulse when said first gate drive signal transitions from said OFF state to said ON state, (ii) said second gate drive signal as a second pulse when said first gate drive signal transitions from said ON state to said OFF state, and (iii) said second gate drive signal in said OFF state between said first and second pulses (254, 256). a gate drive circuit for producing a first gate drive signal on a gate drive output wherein said first gate drive signal comprises an ON state and an OFF state; a first semiconductor switching device having a first gate, a first drain, and a first source; a second semiconductor switching device having a second gate, a second drain, and a second source, said second semiconductor switching device having a first turn-on time that is less than a second turn-on time associated with said first semiconductor switching device; said first and second semiconductor switching devices (234, 226) being connected in a parallel arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected, wherein said first gate of said first semiconductor switching device is connected to said first gate drive output of said gate drive circuit to receive said first gate drive signal; and a pulse former coupled between said gate drive output and said second gate of said second semiconductor switching device for producing a second gate drive signal comprising an ON state and an OFF state, said pulse former being configured to generate: (i) said second gate drive signal as a first pulse when said first gate drive signal transitions from said OFF state to said ON state, (ii) said second gate drive signal as a second pulse when said first gate drive signal transitions from said ON state to said OFF state, and (iii) said second gate drive signal in said OFF state between said first and second pulses (254, 256). (i) said second gate drive signal as a first pulse when said first gate drive signal transitions from said OFF state to said ON state, (ii) said second gate drive signal as a second pulse when said first gate drive signal transitions from said ON state to said OFF state, and (iii) said second gate drive signal in said OFF state between said first and second pulses (254, 256).