A data processor of Reduced Instruction Set Computer type, comprising: an instruction-execution unit; and an instruction set having a first instruction arranged to cause the instruction-execution unit to execute a process involving flag generation, and a second instruction arranged to cause the instruction-execution unit to execute a process involving use of a flag (GT32, GU32, Z32, V32, C32, GT64, GU64, Z64, V64, C64), wherein the instruction-execution unit has an operation circuit operable to perform a process according to a result of decoding of an instruction, a flag latch circuit (U,T), and a flag select circuit (FMUX), the operation circuit (ALU,SFT) is arranged to execute an operation process on operand (EXA,EXB) in a first data size and a second data size larger than the first data size according to a result of decode of the first instruction, wherein the operation circuit (ALU, SFT) is arranged to perform a first process on the operand of the first data size, generate a first flag group (GT32, GU32, Z32, V32, C32) and a second flag group (GT64, GU64, Z64, V64, C64), and select a first flag out of the first flag group and a second flag out of the second flag group according to a result of decode of the first instruction, wherein the operation circuit is arranged to perform a second process on the operand of the second data size, generate the first flag group (GB32, GU32, Z32, V32, C32) and the second flag group (GT64, GU64, Z64, V64, C64), and select a first flag out of the first flag group (GT32, GU32, Z32, V32, C32) and a second flag out of the second flag group (GT64, GU64, Z64, V64, C64) according to a result of the decoding of the first instruction, wherein the operation of the first process on the first data size operand is identical with the operation of the second process on the low-order bits of the second data size operand, wherein the first flag group (GT32, GU32, Z32, V32, C32) and the second flag group (GT64, GU64, Z64, V64, C64) generated by the operation on the operand of the first data size and the first flag group (GT32, GU32, Z32, V32, C32) and the second flag group (GT64, GU64, Z64, V64, C64) generated by the operation on the operand of the second data size are the same, the flag latch circuit (U,T) latches the first flag and the second flag (new U, new T) generated by the operation circuit (ALU,SFT) according to a result of decode of the first instruction, and the flag select circuit (FMUX) selects one of the first flag and the second flag(new U, new T) latched by the flag latch circuit (U,T), according to a result of decode of the second instruction. an instruction-execution unit; and an instruction set having a first instruction arranged to cause the instruction-execution unit to execute a process involving flag generation, and a second instruction arranged to cause the instruction-execution unit to execute a process involving use of a flag (GT32, GU32, Z32, V32, C32, GT64, GU64, Z64, V64, C64), wherein the instruction-execution unit has an operation circuit operable to perform a process according to a result of decoding of an instruction, a flag latch circuit (U,T), and a flag select circuit (FMUX), the operation circuit (ALU,SFT) is arranged to execute an operation process on operand (EXA,EXB) in a first data size and a second data size larger than the first data size according to a result of decode of the first instruction, wherein the operation circuit (ALU, SFT) is arranged to perform a first process on the operand of the first data size, generate a first flag group (GT32, GU32, Z32, V32, C32) and a second flag group (GT64, GU64, Z64, V64, C64), and select a first flag out of the first flag group and a second flag out of the second flag group according to a result of decode of the first instruction, wherein the operation circuit is arranged to perform a second process on the operand of the second data size, generate the first flag group (GB32, GU32, Z32, V32, C32) and the second flag group (GT64, GU64, Z64, V64, C64), and select a first flag out of the first flag group (GT32, GU32, Z32, V32, C32) and a second flag out of the second flag group (GT64, GU64, Z64, V64, C64) according to a result of the decoding of the first instruction, wherein the operation of the first process on the first data size operand is identical with the operation of the second process on the low-order bits of the second data size operand, wherein the first flag group (GT32, GU32, Z32, V32, C32) and the second flag group (GT64, GU64, Z64, V64, C64) generated by the operation on the operand of the first data size and the first flag group (GT32, GU32, Z32, V32, C32) and the second flag group (GT64, GU64, Z64, V64, C64) generated by the operation on the operand of the second data size are the same, the flag latch circuit (U,T) latches the first flag and the second flag (new U, new T) generated by the operation circuit (ALU,SFT) according to a result of decode of the first instruction, and the flag select circuit (FMUX) selects one of the first flag and the second flag(new U, new T) latched by the flag latch circuit (U,T), according to a result of decode of the second instruction.