An electronic circuit for driving an N-type transistor, the N-type transistor having a control node, an output node, and a power supply node coupled to a high voltage supply, the electronic circuit comprising: a bootstrap voltage node capacitively coupled to the output node of the N-type transistor; a first input transistor having a control node, a current input node, and a current output node, wherein the control node is coupled to receive a first input signal (ResetL, SetL); a second input transistor having a control node, a current input node, and a current output node, wherein the control node is coupled to receive a second input signal (SetL, ResetL); a first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) having a control node, a current input node, and a current output node, wherein the control node of the first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) is coupled to the current input node of the first input transistor, and wherein the current input node of the first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) is coupled to the bootstrap voltage node; a second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) having a control node, a current input node, and a current output node, wherein the control node of the second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) is coupled to the current input node of the second input transistor, and wherein the current input node of the second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) is coupled to the bootstrap voltage node; wherein the first and second composite current mirrors comprise respective series couplings of two or more respective current mirrors; a first comparator having a first input node coupled to the current output node of the second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) and having a second input node coupled to receive a first reference voltage (SetRef), wherein the first reference voltage (SetRef) is related to a voltage at the output node of the N-type transistor, wherein the first comparator also has an output node; and a second comparator having a first input node coupled to the output node of the first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) and having a second input node coupled to receive a second reference voltage (RstRef), wherein the second reference voltage (RstRef) is related to the voltage at the output node of the N-type transistor, wherein the second comparator also has an output node. a bootstrap voltage node capacitively coupled to the output node of the N-type transistor; a first input transistor having a control node, a current input node, and a current output node, wherein the control node is coupled to receive a first input signal (ResetL, SetL); a second input transistor having a control node, a current input node, and a current output node, wherein the control node is coupled to receive a second input signal (SetL, ResetL); a first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) having a control node, a current input node, and a current output node, wherein the control node of the first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) is coupled to the current input node of the first input transistor, and wherein the current input node of the first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) is coupled to the bootstrap voltage node; a second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) having a control node, a current input node, and a current output node, wherein the control node of the second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) is coupled to the current input node of the second input transistor, and wherein the current input node of the second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) is coupled to the bootstrap voltage node; wherein the first and second composite current mirrors comprise respective series couplings of two or more respective current mirrors; a first comparator having a first input node coupled to the current output node of the second composite current mirror circuit (M14/M15, M3/M4/M5, M10/M11) and having a second input node coupled to receive a first reference voltage (SetRef), wherein the first reference voltage (SetRef) is related to a voltage at the output node of the N-type transistor, wherein the first comparator also has an output node; and a second comparator having a first input node coupled to the output node of the first composite current mirror circuit (M12/M13, M0/M1/M2, M6/M7) and having a second input node coupled to receive a second reference voltage (RstRef), wherein the second reference voltage (RstRef) is related to the voltage at the output node of the N-type transistor, wherein the second comparator also has an output node.