A DC-DC converter (10, 20) comprising: first and second ports; first, second, third and fourth transistors (T1-T4) coupled in series between a first terminal of the first port and a second terminal of the first port; first, second, third and fourth diodes (D1-D4) coupled antiparallel to respective ones of the first, second, third and fourth transistors (T1-T4); a first inductor coupled between a first terminal of the second port and first node at which the first and second transistors (T1; T2) are connected; a second inductor coupled between a second terminal of the second port and a second node at which the third and fourth transistors (T3; T4) are connected; a first capacitor coupled between the first terminal of the first port and a third node at which the second and third transistors (T2; T3) are connected; and a second capacitor coupled between the second terminal of the first port and the third node; and a controller configured to operate the first, second, third and fourth transistors (T1-T4) to provide a first mode of operation in which the first and second capacitors (C1; C2) are alternately charged when a voltage at the second port is in a first range and a second mode of operation in which the first and second capacitors (C1; C2) are simultaneously charged when a voltage at the second port is in a second range; characterized in that the first mode of operation comprises alternately performing the following operations: pulse width modulating the second transistor while the first and fourth transistors (T1; T4) are off to charge the first capacitor; pulse width modulating the third transistor while the first and fourth transistors (T1; T4) are off to charge the second capacitor; and further characterized in that the second mode of operation comprise pulse width modulating the second and third transistor (T2; T3) while the first and fourth transistors (T1; T4) are off to simultaneously charge the first and second capacitors (C1; C2). first and second ports; first, second, third and fourth transistors (T1-T4) coupled in series between a first terminal of the first port and a second terminal of the first port; first, second, third and fourth diodes (D1-D4) coupled antiparallel to respective ones of the first, second, third and fourth transistors (T1-T4); a first inductor coupled between a first terminal of the second port and first node at which the first and second transistors (T1; T2) are connected; a second inductor coupled between a second terminal of the second port and a second node at which the third and fourth transistors (T3; T4) are connected; a first capacitor coupled between the first terminal of the first port and a third node at which the second and third transistors (T2; T3) are connected; and a second capacitor coupled between the second terminal of the first port and the third node; and a controller configured to operate the first, second, third and fourth transistors (T1-T4) to provide a first mode of operation in which the first and second capacitors (C1; C2) are alternately charged when a voltage at the second port is in a first range and a second mode of operation in which the first and second capacitors (C1; C2) are simultaneously charged when a voltage at the second port is in a second range; characterized in that the first mode of operation comprises alternately performing the following operations: pulse width modulating the second transistor while the first and fourth transistors (T1; T4) are off to charge the first capacitor; pulse width modulating the third transistor while the first and fourth transistors (T1; T4) are off to charge the second capacitor; and further characterized in that the second mode of operation comprise pulse width modulating the second and third transistor (T2; T3) while the first and fourth transistors (T1; T4) are off to simultaneously charge the first and second capacitors (C1; C2). pulse width modulating the second transistor while the first and fourth transistors (T1; T4) are off to charge the first capacitor; pulse width modulating the third transistor while the first and fourth transistors (T1; T4) are off to charge the second capacitor; and further characterized in that the second mode of operation comprise pulse width modulating the second and third transistor (T2; T3) while the first and fourth transistors (T1; T4) are off to simultaneously charge the first and second capacitors (C1; C2).