An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transaction memory support circuitry comprising conflict detection circuitry to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; in which: in response to a load-exclusive instruction specifying a given address, the processing circuitry is configured to set an exclusive monitor indication for the given address; in response to a store-exclusive instruction specifying the given address, the processing circuitry is configured to return a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set; in response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, the processing circuitry is configured to trigger clearing of any exclusive monitor indication previously set for the load target address by a thread other than the thread comprising the predetermined type of load instruction; and in response to said load-exclusive instruction, at least one of the processing circuitry and the transactional memory support circuitry is configured to trigger an abort of a transaction for which the given address is specified as one of the working set of addresses, where the transaction to be aborted is a transaction of a thread other than the thread comprising the load-exclusive instruction. processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transaction memory support circuitry comprising conflict detection circuitry to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; in which: in response to a load-exclusive instruction specifying a given address, the processing circuitry is configured to set an exclusive monitor indication for the given address; in response to a store-exclusive instruction specifying the given address, the processing circuitry is configured to return a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set; in response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, the processing circuitry is configured to trigger clearing of any exclusive monitor indication previously set for the load target address by a thread other than the thread comprising the predetermined type of load instruction; and in response to said load-exclusive instruction, at least one of the processing circuitry and the transactional memory support circuitry is configured to trigger an abort of a transaction for which the given address is specified as one of the working set of addresses, where the transaction to be aborted is a transaction of a thread other than the thread comprising the load-exclusive instruction. in response to a load-exclusive instruction specifying a given address, the processing circuitry is configured to set an exclusive monitor indication for the given address; in response to a store-exclusive instruction specifying the given address, the processing circuitry is configured to return a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set; in response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, the processing circuitry is configured to trigger clearing of any exclusive monitor indication previously set for the load target address by a thread other than the thread comprising the predetermined type of load instruction; and in response to said load-exclusive instruction, at least one of the processing circuitry and the transactional memory support circuitry is configured to trigger an abort of a transaction for which the given address is specified as one of the working set of addresses, where the transaction to be aborted is a transaction of a thread other than the thread comprising the load-exclusive instruction.