A circuit for correction of a signal which is susceptible to baseline wander, the circuit comprising: a front-end signal processing circuit (102; 210), including a digital processing logic circuit, configured and arranged to process an input signal by mitigating signal artifacts; a slicer circuit (106; 212) configured and arranged to sample the processed input signal and, therefrom, generate a symbol output derived from the sampled processed input signal; and a summing cross-over filter circuit configured and arranged between the front-end signal processing circuit (102; 210) and the slicer circuit (106; 212) to mitigate baseline wander in the symbol output, wherein the summing cross-over filter circuit comprises: a first circuit configured and arranged to perform a high-pass filtering process including receiving the processed input signal from the front-end signal processing circuit (102; 210) and providing a high-pass output that includes portions of the processed input signal having frequency content above a first threshold; a second circuit configured and arranged to perform a low-pass filtering process including receiving the symbol output from the slicer circuit (106; 212) and, therefrom, providing a low-pass output that includes portions of the symbol output having frequency content below a second threshold; and a summing circuit configured and arranged to output a sum of the high-pass output and the low-pass output to the slicer circuit; and a decision feedback equalization circuit configured and arranged to provide feedback to the summing circuit derived from the symbol output, and a gain compensation circuit configured and arranged in a pathway of the second circuit. a front-end signal processing circuit (102; 210), including a digital processing logic circuit, configured and arranged to process an input signal by mitigating signal artifacts; a slicer circuit (106; 212) configured and arranged to sample the processed input signal and, therefrom, generate a symbol output derived from the sampled processed input signal; and a summing cross-over filter circuit configured and arranged between the front-end signal processing circuit (102; 210) and the slicer circuit (106; 212) to mitigate baseline wander in the symbol output, wherein the summing cross-over filter circuit comprises: a first circuit configured and arranged to perform a high-pass filtering process including receiving the processed input signal from the front-end signal processing circuit (102; 210) and providing a high-pass output that includes portions of the processed input signal having frequency content above a first threshold; a second circuit configured and arranged to perform a low-pass filtering process including receiving the symbol output from the slicer circuit (106; 212) and, therefrom, providing a low-pass output that includes portions of the symbol output having frequency content below a second threshold; and a summing circuit configured and arranged to output a sum of the high-pass output and the low-pass output to the slicer circuit; and a first circuit configured and arranged to perform a high-pass filtering process including receiving the processed input signal from the front-end signal processing circuit (102; 210) and providing a high-pass output that includes portions of the processed input signal having frequency content above a first threshold; a second circuit configured and arranged to perform a low-pass filtering process including receiving the symbol output from the slicer circuit (106; 212) and, therefrom, providing a low-pass output that includes portions of the symbol output having frequency content below a second threshold; and a summing circuit configured and arranged to output a sum of the high-pass output and the low-pass output to the slicer circuit; and a decision feedback equalization circuit configured and arranged to provide feedback to the summing circuit derived from the symbol output, and a gain compensation circuit configured and arranged in a pathway of the second circuit.