A 3D-NAND memory device, comprising: a first substrate having a first side on which a memory stack is formed and a second side that is opposite to the first side; a doped region formed in the first side of the first substrate and electrically coupled to at least a source terminal of a memory transistor formed on the first side of the first substrate; a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA (32, 33), the first VIA (32, 33) extending from the second side of the first substrate to the doped region; a common source structure formed over and coupled to the doped region, wherein the common source structure comprises a top portion that is made of tungsten and a bottom portion (28") that is made of polysilicon; a bit line formed over the common source structure that is coupled to the common source structure through a second VIA; a second connection structure positioned over the bit line that is coupled to the bit line through a third VIA, the first connection structure and the second connection structure being coupled to each other a plurality of channel structures (38, 84) extending from the first side of the first substrate; and a plurality of word lines positioned over the first side of the first substrate in a staircase configuration, wherein: the plurality of the word lines are spaced apart from each other by a plurality of insulating layers, the plurality of channel structures (38, 84) extend through the plurality of word lines and the plurality of the insulation layers, the plurality of channel structures (38, 84) are disposed below the bit line, and the common source structure extends through the plurality of word lines and the plurality of insulating layers and separates the plurality of the channel structures (38, 84). a first substrate having a first side on which a memory stack is formed and a second side that is opposite to the first side; a doped region formed in the first side of the first substrate and electrically coupled to at least a source terminal of a memory transistor formed on the first side of the first substrate; a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA (32, 33), the first VIA (32, 33) extending from the second side of the first substrate to the doped region; a common source structure formed over and coupled to the doped region, wherein the common source structure comprises a top portion that is made of tungsten and a bottom portion (28") that is made of polysilicon; a bit line formed over the common source structure that is coupled to the common source structure through a second VIA; a second connection structure positioned over the bit line that is coupled to the bit line through a third VIA, the first connection structure and the second connection structure being coupled to each other a plurality of channel structures (38, 84) extending from the first side of the first substrate; and a plurality of word lines positioned over the first side of the first substrate in a staircase configuration, wherein: the plurality of the word lines are spaced apart from each other by a plurality of insulating layers, the plurality of channel structures (38, 84) extend through the plurality of word lines and the plurality of the insulation layers, the plurality of channel structures (38, 84) are disposed below the bit line, and the common source structure extends through the plurality of word lines and the plurality of insulating layers and separates the plurality of the channel structures (38, 84). the plurality of channel structures (38, 84) extend through the plurality of word lines and the plurality of the insulation layers, the plurality of channel structures (38, 84) are disposed below the bit line, and the common source structure extends through the plurality of word lines and the plurality of insulating layers and separates the plurality of the channel structures (38, 84).