A method for encoding a sequence of control information bits comprising: generating a first sequence of J cyclic redundancy check, CRC, bits based on the sequence of control information bits using a first CRC polynomial; generating a second sequence of J' CRC bits based on the sequence of control information bits using a second CRC polynomial; distributing the first sequence of J CRC bits and the second sequence of J' CRC bits between the sequence of control information bits to form a first combined sequence of bits, such that, in the bit order of the first combined sequence of bits following the distribution, each of the J+J' CRC bits of the first and the second sequences follows said control information bits, which are used to generate said each CRC bit, and a CRC bit from the first sequence of J CRC bits is located before the first CRC bit from the second sequence of J' CRC bits to enable an error detection check based on said CRC bit from the first sequence of J CRC bits to be performed before a first check based on said first CRC bit from the second sequence of J' CRC bits, wherein the distributing further comprises: determining a first distribution pattern to form a second combined sequence of bits comprising the first sequence of J CRC bits and the sequence of control information bits; applying the first distribution pattern to the first sequence of J CRC bits and the sequence of control information bits to generate the second combined sequence of bits; determining a second distribution pattern to form the first combined sequence of bits comprising the first sequence of J CRC bits, the second sequence of J' CRC bits and the sequence of control information bits; and applying the second distribution pattern to the second combined sequence of bits and the second sequence of J' CRC bits to generate the first combined sequence of bits; and polar encoding the first combined sequence of bits. generating a first sequence of J cyclic redundancy check, CRC, bits based on the sequence of control information bits using a first CRC polynomial; generating a second sequence of J' CRC bits based on the sequence of control information bits using a second CRC polynomial; distributing the first sequence of J CRC bits and the second sequence of J' CRC bits between the sequence of control information bits to form a first combined sequence of bits, such that, in the bit order of the first combined sequence of bits following the distribution, each of the J+J' CRC bits of the first and the second sequences follows said control information bits, which are used to generate said each CRC bit, and a CRC bit from the first sequence of J CRC bits is located before the first CRC bit from the second sequence of J' CRC bits to enable an error detection check based on said CRC bit from the first sequence of J CRC bits to be performed before a first check based on said first CRC bit from the second sequence of J' CRC bits, wherein the distributing further comprises: determining a first distribution pattern to form a second combined sequence of bits comprising the first sequence of J CRC bits and the sequence of control information bits; applying the first distribution pattern to the first sequence of J CRC bits and the sequence of control information bits to generate the second combined sequence of bits; determining a second distribution pattern to form the first combined sequence of bits comprising the first sequence of J CRC bits, the second sequence of J' CRC bits and the sequence of control information bits; and applying the second distribution pattern to the second combined sequence of bits and the second sequence of J' CRC bits to generate the first combined sequence of bits; and polar encoding the first combined sequence of bits. determining a first distribution pattern to form a second combined sequence of bits comprising the first sequence of J CRC bits and the sequence of control information bits; applying the first distribution pattern to the first sequence of J CRC bits and the sequence of control information bits to generate the second combined sequence of bits; determining a second distribution pattern to form the first combined sequence of bits comprising the first sequence of J CRC bits, the second sequence of J' CRC bits and the sequence of control information bits; and applying the second distribution pattern to the second combined sequence of bits and the second sequence of J' CRC bits to generate the first combined sequence of bits; and polar encoding the first combined sequence of bits.