Interconnection network (110,200) for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages; wherein N is a non-prime positive integer, and wherein M is a positive integer equal to, or higher than, two; wherein the M stages include a first stage and a last stage and wherein each stage includes switching elements (111,112,113) having, each, respective input pins and respective output pins; wherein the input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals; wherein, the input and output pins of the switching elements (111,112,113) of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing, each, respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage; whereby the interconnection network (110,200) is operable to route, on the basis of routing commands applied to the switching elements (111,112,113), N input values received at the N input terminals through the M stages and the interconnection sub-networks to provide, at the N output terminals, N output values corresponding to, or circularly shifted with respect to, said N input values received at the N input terminals; characterized in that M denotes a number of given submultiples of N whose product is equal to N; wherein each stage is associated with a respective submultiple of said M given submultiples of N, and includes S i switching elements (111,112,113), each having sm i respective input pins and sm i respective output pins, wherein S i =Nlsm i, wherein sm i denotes said respective submultiple associated with said stage, and wherein i denotes said stage and is a positive integer comprised between one and M; wherein each switching element (111,112,113) is configured to: • receive, at the sm i respective input pins, sm i respective input values; and • provide at the sm i respective output pins, on the basis of a respective routing command applied to said switching element (111,112,113), sm i respective output values corresponding to, or circularly shifted with respect to, said sm i respective input values received at the sm i respective input pins; wherein the interconnection sub-networks are not connected to each other; and wherein the interconnection network includes sm 1 interconnection sub-networks for routing, each, N / sm 1 respective input values from N / sm 1 respective output pins of the switching elements of the first stage to N / sm 1 respective input pins of the switching elements of the last stage; wherein sm 1 denotes the submultiple, among said M given submultiples of N, which is associated with the first stage. • receive, at the sm i respective input pins, sm i respective input values; and • provide at the sm i respective output pins, on the basis of a respective routing command applied to said switching element (111,112,113), sm i respective output values corresponding to, or circularly shifted with respect to, said sm i respective input values received at the sm i respective input pins;