A pixel sensor array formed on a substrate, the pixel sensor array comprising: a plurality of surface pixel sensors formed at a surface of the substrate; a layer of dielectric material formed over the surface of the substrate; a plurality of apertures formed in the dielectric layer, each aperture aligned with one of the surface pixel sensors, each aperture having an inner side wall; a reflective lining layer formed on the inner side wall of each aperture, the lining layer being substantially fully reflective to visible light, an inner wall of each reflective lining layer spaced apart from the surface of the substrate and having a smaller cross-sectional area than a cross-sectional area of each surface pixel sensor, the inner wall of each reflective lining layer lying in a plane with a top surface of the layer of dielectric material; a filler material disposed in each aperture inside of the reflective lining layer and having a top surface lying in the plane with the top surface of the layer of dielectric material, the filler material being substantially transparent to visible light; and a microlens disposed over the top surface of each aperture; characterized by a vertical structure disposed between each adjacent pair of the pixel sensors and forming entrance apertures for light to pass into the pixel sensors, each vertical structure including: segments of a first metal interconnect layer positioned below a top surface of the reflective lining layers of the adjacent ones of the pixel sensors; segments of a second metal interconnect layer positioned above a top surface of the reflective lining layers of the adjacent ones of the pixel sensors; segments of a third metal interconnect layer positioned above the segments of the second metal interconnect layer; a plurality of first metal interconnect vias disposed between segments of the first metal interconnect layer and the second metal interconnect layer; a plurality of second metal interconnect vias disposed between segments of the second metal interconnect layer and the third metal interconnect layer; the plurality of first and second metal interconnect vias (70, 72) laterally positioned with respect to one another to block flare light from passing through any of the vertical structures. a plurality of surface pixel sensors formed at a surface of the substrate; a layer of dielectric material formed over the surface of the substrate; a plurality of apertures formed in the dielectric layer, each aperture aligned with one of the surface pixel sensors, each aperture having an inner side wall; a reflective lining layer formed on the inner side wall of each aperture, the lining layer being substantially fully reflective to visible light, an inner wall of each reflective lining layer spaced apart from the surface of the substrate and having a smaller cross-sectional area than a cross-sectional area of each surface pixel sensor, the inner wall of each reflective lining layer lying in a plane with a top surface of the layer of dielectric material; a filler material disposed in each aperture inside of the reflective lining layer and having a top surface lying in the plane with the top surface of the layer of dielectric material, the filler material being substantially transparent to visible light; and a microlens disposed over the top surface of each aperture; characterized by a vertical structure disposed between each adjacent pair of the pixel sensors and forming entrance apertures for light to pass into the pixel sensors, each vertical structure including: segments of a first metal interconnect layer positioned below a top surface of the reflective lining layers of the adjacent ones of the pixel sensors; segments of a second metal interconnect layer positioned above a top surface of the reflective lining layers of the adjacent ones of the pixel sensors; segments of a third metal interconnect layer positioned above the segments of the second metal interconnect layer; a plurality of first metal interconnect vias disposed between segments of the first metal interconnect layer and the second metal interconnect layer; a plurality of second metal interconnect vias disposed between segments of the second metal interconnect layer and the third metal interconnect layer; the plurality of first and second metal interconnect vias (70, 72) laterally positioned with respect to one another to block flare light from passing through any of the vertical structures. segments of a first metal interconnect layer positioned below a top surface of the reflective lining layers of the adjacent ones of the pixel sensors; segments of a second metal interconnect layer positioned above a top surface of the reflective lining layers of the adjacent ones of the pixel sensors; segments of a third metal interconnect layer positioned above the segments of the second metal interconnect layer; a plurality of first metal interconnect vias disposed between segments of the first metal interconnect layer and the second metal interconnect layer; a plurality of second metal interconnect vias disposed between segments of the second metal interconnect layer and the third metal interconnect layer; the plurality of first and second metal interconnect vias (70, 72) laterally positioned with respect to one another to block flare light from passing through any of the vertical structures.