A multimode data synchronization system comprising: a first data synchronizer; a second data synchronizer; a first phase locked loop, PLL, coupled to the first data synchronizer, the first PLL being adapted to selectively receive a first clock signal in an idle mode of operation and a data signal in a read mode of operation; a second PLL coupled to the second data synchronizer, the second PLL being adapted to selectively receive a reference clock signal and to generate the first clock signal from the reference clock signal in the idle mode of operation and a delayed data signal in the read mode of operation, the second PLL comprising: a phase detector; a first loop filter (loop filter 2); a second loop filter (loop filter 3); a first charge pump for driving the first loop filter (loop filter 2); a second charge pump for driving the second loop filter (loop filter 3); the phase detector being adapted to selectively drive the first charge pump in the read mode of operation and the second charge pump in the idle mode of operation; a voltage controlled oscillator being selectively controlled by the first loop filter in the read mode of operation and the second loop filter in the idle mode of operation; and a comparator adapted to compare the voltages of the first and second loop filters and to selectively control the first charge pump in the idle mode of operation and the second charge pump in the read mode of operation such that the voltage of the first loop filter is maintained substantially the same as the voltage of the second loop filter. a first data synchronizer; a second data synchronizer; a first phase locked loop, PLL, coupled to the first data synchronizer, the first PLL being adapted to selectively receive a first clock signal in an idle mode of operation and a data signal in a read mode of operation; a second PLL coupled to the second data synchronizer, the second PLL being adapted to selectively receive a reference clock signal and to generate the first clock signal from the reference clock signal in the idle mode of operation and a delayed data signal in the read mode of operation, the second PLL comprising: a phase detector; a first loop filter (loop filter 2); a second loop filter (loop filter 3); a first charge pump for driving the first loop filter (loop filter 2); a second charge pump for driving the second loop filter (loop filter 3); the phase detector being adapted to selectively drive the first charge pump in the read mode of operation and the second charge pump in the idle mode of operation; a voltage controlled oscillator being selectively controlled by the first loop filter in the read mode of operation and the second loop filter in the idle mode of operation; and a comparator adapted to compare the voltages of the first and second loop filters and to selectively control the first charge pump in the idle mode of operation and the second charge pump in the read mode of operation such that the voltage of the first loop filter is maintained substantially the same as the voltage of the second loop filter. a phase detector; a first loop filter (loop filter 2); a second loop filter (loop filter 3); a first charge pump for driving the first loop filter (loop filter 2); a second charge pump for driving the second loop filter (loop filter 3); the phase detector being adapted to selectively drive the first charge pump in the read mode of operation and the second charge pump in the idle mode of operation; a voltage controlled oscillator being selectively controlled by the first loop filter in the read mode of operation and the second loop filter in the idle mode of operation; and a comparator adapted to compare the voltages of the first and second loop filters and to selectively control the first charge pump in the idle mode of operation and the second charge pump in the read mode of operation such that the voltage of the first loop filter is maintained substantially the same as the voltage of the second loop filter.