A method of operation within an integrated circuit memory device (105, 155, 205, 305), the method comprising: storing a plurality of digital values that specify respective termination impedances (161a, 161b); switchably coupling sets of load elements to a data input/output, I/O, to apply termination impedances (161a, 161b) specified by the digital values, wherein switchably coupling the sets of load elements to the data I/O includes: applying a first one of two termination impedances to the data I/O during an idle state of the memory device (105, 155, 205, 305) effecting a first termination (Hard_T), applying (355, 359) a second one of the two termination impedances (161a, 161b) to the data I/O, effecting a second termination (Soft_T) to the data I/O while the memory device (105, 155, 205, 305) receives write data in a memory write operation and applying the first one of the termination impedances (161a, 161b) to the data I/O during a time period that follows directly after the memory write operation, wherein the first termination impedance and the second termination impedance (161a, 161b) have different impedance values; outputting read data via the data I/O in a memory read operation, wherein all termination impedances are decoupled from the data I/O effecting no termination (No_T). storing a plurality of digital values that specify respective termination impedances (161a, 161b); switchably coupling sets of load elements to a data input/output, I/O, to apply termination impedances (161a, 161b) specified by the digital values, wherein switchably coupling the sets of load elements to the data I/O includes: applying a first one of two termination impedances to the data I/O during an idle state of the memory device (105, 155, 205, 305) effecting a first termination (Hard_T), applying (355, 359) a second one of the two termination impedances (161a, 161b) to the data I/O, effecting a second termination (Soft_T) to the data I/O while the memory device (105, 155, 205, 305) receives write data in a memory write operation and applying the first one of the termination impedances (161a, 161b) to the data I/O during a time period that follows directly after the memory write operation, wherein the first termination impedance and the second termination impedance (161a, 161b) have different impedance values; outputting read data via the data I/O in a memory read operation, wherein all termination impedances are decoupled from the data I/O effecting no termination (No_T). applying a first one of two termination impedances to the data I/O during an idle state of the memory device (105, 155, 205, 305) effecting a first termination (Hard_T), applying (355, 359) a second one of the two termination impedances (161a, 161b) to the data I/O, effecting a second termination (Soft_T) to the data I/O while the memory device (105, 155, 205, 305) receives write data in a memory write operation and applying the first one of the termination impedances (161a, 161b) to the data I/O during a time period that follows directly after the memory write operation, wherein the first termination impedance and the second termination impedance (161a, 161b) have different impedance values; outputting read data via the data I/O in a memory read operation, wherein all termination impedances are decoupled from the data I/O effecting no termination (No_T).