A method for forming a three-dimensional, 3D, memory device, comprising: forming an initial channel hole in a stack structure of a plurality of first layers and a plurality of second layers alternatingly arranged over a substrate; forming an offset between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole; filling the channel hole with a channel-forming structure to form a semiconductor channel (22, 106), forming the channel-forming structure comprising forming a blocking layer (102, 221, 251, 261) over a sidewall of the channel hole; forming a memory layer (103, 222) over the blocking layer (102, 221, 251, 261), the memory layer (103, 222) extending along a vertical direction; forming a tunneling layer (104, 223, 263) over the memory layer (103, 222); forming a semiconductor layer over the tunneling layer (104, 223, 263); forming a dielectric core over the semiconductor layer to fill up the channel hole; replacing the plurality of second layers with a plurality of gate electrodes (101, 242); and removing a portion of the channel-forming structure to divide the memory layer (103, 222) into a plurality of sub-memory portions, each sub-memory portion partially surrounding a respective gate electrode (101, 242), removing the plurality of first layers and a portion of the blocking layer to expose the memory layer and form a third initial gate-line slit; removing a portion of the memory layer to expose the tunneling layer, characterized by the steps of removing a portion of the tunneling layer (104, 223, 263) to form a plurality of recessed areas in the tunneling layer (104, 223, 263) to form gate-line slits, the plurality of recessed areas dividing the memory layer (103, 222) into the plurality of sub-memory portions. forming an initial channel hole in a stack structure of a plurality of first layers and a plurality of second layers alternatingly arranged over a substrate; forming an offset between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole; filling the channel hole with a channel-forming structure to form a semiconductor channel (22, 106), forming the channel-forming structure comprising forming a blocking layer (102, 221, 251, 261) over a sidewall of the channel hole; forming a memory layer (103, 222) over the blocking layer (102, 221, 251, 261), the memory layer (103, 222) extending along a vertical direction; forming a tunneling layer (104, 223, 263) over the memory layer (103, 222); forming a semiconductor layer over the tunneling layer (104, 223, 263); forming a dielectric core over the semiconductor layer to fill up the channel hole; replacing the plurality of second layers with a plurality of gate electrodes (101, 242); and removing a portion of the channel-forming structure to divide the memory layer (103, 222) into a plurality of sub-memory portions, each sub-memory portion partially surrounding a respective gate electrode (101, 242), removing the plurality of first layers and a portion of the blocking layer to expose the memory layer and form a third initial gate-line slit; removing a portion of the memory layer to expose the tunneling layer, characterized by the steps of removing a portion of the tunneling layer (104, 223, 263) to form a plurality of recessed areas in the tunneling layer (104, 223, 263) to form gate-line slits, the plurality of recessed areas dividing the memory layer (103, 222) into the plurality of sub-memory portions.