A method for analyzing the behavior of an integrated circuit comprising paths and physical components, implemented by computer, - said physical components being either not represented in a first level of abstraction at least equal to or higher than the RTL level, or represented in said first level of abstraction; - said integrated circuit comprising a set of modules (A, B) consisting of physical component(s); - each module defining a function between an input signal and an output signal, - the physical components, the paths and the modules each being identified by a name, said method being characterized in that it further comprises the following steps: - a first step, generating a first array, of extracting a first set of names corresponding to the physical components represented and to the modules; - a second step, generating two associative arrays (TAB2, TAB2'), comprising the extraction of the names of the paths and those of the physical components for each of said paths and the assignment of a membership module name to said physical components; - a third step, generating a third associative array, allotting a label to the set of physical components, said label being: ∘ their name for the components represented by a name in the first and two associative arrays (TAB2, TAB2'); ∘ the name of the membership module for the components not represented by a name in the first and two associative arrays (TAB2, TAB2'); - a fourth step, generating fourth and fifth associative arrays (TAB4, TAB5), of determining at least one physical parameter for each of the components represented and for each of the modules, and of associating the names of the components represented with the physical parameters determined, and of associating the names of the components represented and of associating the names of the modules with the physical parameters determined, and where said at least one physical parameter being able to be the switching frequency of a signal or the holding time of a signal or the activity corresponding to the ratio between a (total) number of change of value or a number of cycles of holding at 1 or a number of cycles of holding at 0 of a signal and the number of cycles of the clock signal or the propagation lag of a logic cell; and - a fifth step of assigning the physical parameters contained in the fourth and fifth associative arrays (TAB4, TAB5) to the physical components contained in the third associative array, the fifth step generating a sixth associative array whose content allows the calculation of the total activity of the path or of the degradation of the propagation time of the path. - said physical components being either not represented in a first level of abstraction at least equal to or higher than the RTL level, or represented in said first level of abstraction; - said integrated circuit comprising a set of modules (A, B) consisting of physical component(s); - each module defining a function between an input signal and an output signal, - the physical components, the paths and the modules each being identified by a name, said method being characterized in that it further comprises the following steps: - a first step, generating a first array, of extracting a first set of names corresponding to the physical components represented and to the modules; - a second step, generating two associative arrays (TAB2, TAB2'), comprising the extraction of the names of the paths and those of the physical components for each of said paths and the assignment of a membership module name to said physical components; - a third step, generating a third associative array, allotting a label to the set of physical components, said label being: ∘ their name for the components represented by a name in the first and two associative arrays (TAB2, TAB2'); ∘ the name of the membership module for the components not represented by a name in the first and two associative arrays (TAB2, TAB2'); ∘ their name for the components represented by a name in the first and two associative arrays (TAB2, TAB2'); ∘ the name of the membership module for the components not represented by a name in the first and two associative arrays (TAB2, TAB2'); - a fourth step, generating fourth and fifth associative arrays (TAB4, TAB5), of determining at least one physical parameter for each of the components represented and for each of the modules, and of associating the names of the components represented with the physical parameters determined, and of associating the names of the components represented and of associating the names of the modules with the physical parameters determined, and where said at least one physical parameter being able to be the switching frequency of a signal or the holding time of a signal or the activity corresponding to the ratio between a (total) number of change of value or a number of cycles of holding at 1 or a number of cycles of holding at 0 of a signal and the number of cycles of the clock signal or the propagation lag of a logic cell; and - a fifth step of assigning the physical parameters contained in the fourth and fifth associative arrays (TAB4, TAB5) to the physical components contained in the third associative array, the fifth step generating a sixth associative array whose content allows the calculation of the total activity of the path or of the degradation of the propagation time of the path.