A sensing amplifier for performing read operations on a non-volatile flash memory cell, comprising: a current mirror comprising a first resistor and a second resistor, the first resistor comprising a first terminal and second terminal and the second resistor comprising a first terminal and a second terminal; a voltage source (V DD) coupled to the first terminal of the first resistor and coupled to the first terminal of the second resistor; a reference circuit coupled to the second terminal of the first resistor; a transistor comprising a first terminal and a second terminal, wherein the first terminal of the transistor is coupled to the second terminal of the second resistor; a selected flash memory cell coupled to the second terminal of the transistor; wherein the second terminal of the transistor provides a voltage indicative of the value stored in the selected memory cell, a first value indicated when a current drawn by the reference circuit is greater than a current drawn by the selected memory cell and a second value indicated when a current drawn by the reference circuit is less than a current drawn by the selected memory cell; and further comprising: an operational amplifier, wherein a positive input terminal of the operational amplifier is coupled to the second terminal of the first resistor and a negative input terminal of the operational amplifier is coupled to the second terminal of the second resistor; and wherein the transistor is a PMOS transistor, the PMOS transistor further comprising a third terminal coupled to an output of the operational amplifier. a current mirror comprising a first resistor and a second resistor, the first resistor comprising a first terminal and second terminal and the second resistor comprising a first terminal and a second terminal; a voltage source (V DD) coupled to the first terminal of the first resistor and coupled to the first terminal of the second resistor; a reference circuit coupled to the second terminal of the first resistor; a transistor comprising a first terminal and a second terminal, wherein the first terminal of the transistor is coupled to the second terminal of the second resistor; a selected flash memory cell coupled to the second terminal of the transistor; wherein the second terminal of the transistor provides a voltage indicative of the value stored in the selected memory cell, a first value indicated when a current drawn by the reference circuit is greater than a current drawn by the selected memory cell and a second value indicated when a current drawn by the reference circuit is less than a current drawn by the selected memory cell; and further comprising: an operational amplifier, wherein a positive input terminal of the operational amplifier is coupled to the second terminal of the first resistor and a negative input terminal of the operational amplifier is coupled to the second terminal of the second resistor; and wherein the transistor is a PMOS transistor, the PMOS transistor further comprising a third terminal coupled to an output of the operational amplifier. an operational amplifier, wherein a positive input terminal of the operational amplifier is coupled to the second terminal of the first resistor and a negative input terminal of the operational amplifier is coupled to the second terminal of the second resistor; and wherein the transistor is a PMOS transistor, the PMOS transistor further comprising a third terminal coupled to an output of the operational amplifier.