A circuit for implementing an artificial neuron, said circuit comprising: - an integrator (401, 700, 1000) configured to integrate an input current pulse of the neuron (400, 710, 1010) so as to output a Vmem voltage signal; - a signal generator (402, 701, 1001) linked to the output of the integrator, having a first and a second output and configured to produce, when the voltage Vmem is higher than or equal to a predetermined voltage Vth (707, 1007), a first signal on its first output, corresponding to an output current pulse of the neuron (711, 1011), and a second signal on its second output, corresponding to a control voltage pulse Vout; - a resistive memory (708, 1008) comprising two terminals and able to switch from a high resistance state to a low resistance state in a non-deterministic period of time Tset, following a statistical distribution specific to said memory, a first terminal being linked to the output of the integrator (401, 700, 1000); - a transistor (Q1, Q'1) having a first terminal linked to a branch at zero potential, a second terminal linked to a second terminal of the resistive memory (708, 1008) and a control terminal linked to the second output of the signal generator, said transistor being further configured to be controlled by the second output signal (720, 1020) of the signal generator (701, 1001) such that in the presence of the control voltage pulse Vout, the second terminal of the resistive memory is linked, through said transistor, to the branch at zero potential, such that the resistive memory switches from its high resistance state to its low resistance state, this switch having the effect of lowering the voltage Vmem; - a delay generator linked to the first output of the signal generator and adapted to produce a delayed voltage pulse when the resistive memory switches from its high resistance state to its low resistance state; - a second transistor having a first terminal linked to a branch at zero potential, a second terminal linked to the first terminal of the resistive memory and a control terminal linked to said delay generator such that the first terminal of the resistive memory is linked to the branch at zero potential when the resistive memory switches from its high resistance state to its low resistance state; - a connection linking the second terminal of the resistive memory to said delay generator such that said delayed voltage pulse is applied to the second terminal of the resistive memory in such a manner as to make the resistive memory switch from its low resistance state to its high resistance state, after said switch from the high resistance state to the low resistance state. - an integrator (401, 700, 1000) configured to integrate an input current pulse of the neuron (400, 710, 1010) so as to output a Vmem voltage signal; - a signal generator (402, 701, 1001) linked to the output of the integrator, having a first and a second output and configured to produce, when the voltage Vmem is higher than or equal to a predetermined voltage Vth (707, 1007), a first signal on its first output, corresponding to an output current pulse of the neuron (711, 1011), and a second signal on its second output, corresponding to a control voltage pulse Vout; - a resistive memory (708, 1008) comprising two terminals and able to switch from a high resistance state to a low resistance state in a non-deterministic period of time Tset, following a statistical distribution specific to said memory, a first terminal being linked to the output of the integrator (401, 700, 1000); - a transistor (Q1, Q'1) having a first terminal linked to a branch at zero potential, a second terminal linked to a second terminal of the resistive memory (708, 1008) and a control terminal linked to the second output of the signal generator, said transistor being further configured to be controlled by the second output signal (720, 1020) of the signal generator (701, 1001) such that in the presence of the control voltage pulse Vout, the second terminal of the resistive memory is linked, through said transistor, to the branch at zero potential, such that the resistive memory switches from its high resistance state to its low resistance state, this switch having the effect of lowering the voltage Vmem; - a delay generator linked to the first output of the signal generator and adapted to produce a delayed voltage pulse when the resistive memory switches from its high resistance state to its low resistance state; - a second transistor having a first terminal linked to a branch at zero potential, a second terminal linked to the first terminal of the resistive memory and a control terminal linked to said delay generator such that the first terminal of the resistive memory is linked to the branch at zero potential when the resistive memory switches from its high resistance state to its low resistance state; - a connection linking the second terminal of the resistive memory to said delay generator such that said delayed voltage pulse is applied to the second terminal of the resistive memory in such a manner as to make the resistive memory switch from its low resistance state to its high resistance state, after said switch from the high resistance state to the low resistance state.