A circuit for filtering inter-symbol interference in an integrated circuit, the circuit comprising: a first stage having a first feed forward equalizer coupled to receive digital samples of an input signal, wherein an output of the first feed forward equalizer has reduced pre-cursor inter-symbol interference and is coupled to a decision feedback equalizer of the first stage that generates first decision outputs based upon the digital samples; a second stage coupled to receive the digital samples of the input signal; wherein the second stage comprises a pre-filter coupled to an output of a delay element for receiving delayed digital samples, and a second feed forward equalizer for receiving the first decision outputs and generating filtered decisions, the delay element aligning an output of the pre-filter with the filtered decisions; and wherein the filtered decisions generated by the second feed forward equalizer comprise detected inter-symbol interference associated with the first decision outputs; a first subtractor circuit coupled to receive the output of the pre-filter and the detected inter-symbol interference of the second feed forward equalizer, wherein the detected inter-symbol interference is subtracted from the output of the pre-filter; and an adaptation stage comprising a pre-filter adaptation circuit coupled to the pre-filter and a feed forward equalizer adaptation circuit coupled to the second feed forward equalizer; wherein the second stage generates second decision outputs based upon an output of the first subtractor circuit; wherein a second subtractor circuit generates an error signal based upon the output of the first subtractor circuit and the second decision outputs; and wherein the pre-filter adaptation circuit provides adapted pre-filter coefficients to the pre-filter and the feed forward equalizer adaptation circuit provides adapted coefficients to the second feed forward equalizer based upon the error signal generated by the second subtractor circuit. a first stage having a first feed forward equalizer coupled to receive digital samples of an input signal, wherein an output of the first feed forward equalizer has reduced pre-cursor inter-symbol interference and is coupled to a decision feedback equalizer of the first stage that generates first decision outputs based upon the digital samples; a second stage coupled to receive the digital samples of the input signal; wherein the second stage comprises a pre-filter coupled to an output of a delay element for receiving delayed digital samples, and a second feed forward equalizer for receiving the first decision outputs and generating filtered decisions, the delay element aligning an output of the pre-filter with the filtered decisions; and wherein the filtered decisions generated by the second feed forward equalizer comprise detected inter-symbol interference associated with the first decision outputs; a first subtractor circuit coupled to receive the output of the pre-filter and the detected inter-symbol interference of the second feed forward equalizer, wherein the detected inter-symbol interference is subtracted from the output of the pre-filter; and an adaptation stage comprising a pre-filter adaptation circuit coupled to the pre-filter and a feed forward equalizer adaptation circuit coupled to the second feed forward equalizer; wherein the second stage generates second decision outputs based upon an output of the first subtractor circuit; wherein a second subtractor circuit generates an error signal based upon the output of the first subtractor circuit and the second decision outputs; and wherein the pre-filter adaptation circuit provides adapted pre-filter coefficients to the pre-filter and the feed forward equalizer adaptation circuit provides adapted coefficients to the second feed forward equalizer based upon the error signal generated by the second subtractor circuit.