A computer-implemented method comprising: compiling a hardware description language description of an electronic system into a plurality of programs, each of the plurality of programs comprising a plurality of instructions that are processor-executable to realize at least a portion of the operation of the electronic system, wherein the compiling comprises: parsing the HDL description; traversing busses in the HDL description to identify dataflow operations and traversing control signals to identify control operations associated with the dataflow operations; creating a data structure of a network of logic function blocks representing the electronic system from the HDL description, the network comprising dataflow elements corresponding to the dataflow operations and control logic corresponding to the control operations; partitioning the network into a plurality of program partitions based on reducing communication between partitions, each partition comprising dataflow operations corresponding to dataflow elements that are connected together, and control operations corresponding to control logic that controls those dataflow elements; compiling the plurality of program partitions to generate arithmetic/logic instructions corresponding to the dataflow operations and control flow instructions based on the corresponding control logic for a plurality of general purpose processors based on efficient communication between processors; assigning the plurality of programs to a plurality of processors based on efficient communication between processors, wherein efficiency is measured in terms of shorter latency and/or higher bandwidth; and downloading each of the plurality of programs to an instruction memory of one of a plurality of processors. compiling a hardware description language description of an electronic system into a plurality of programs, each of the plurality of programs comprising a plurality of instructions that are processor-executable to realize at least a portion of the operation of the electronic system, wherein the compiling comprises: parsing the HDL description; traversing busses in the HDL description to identify dataflow operations and traversing control signals to identify control operations associated with the dataflow operations; creating a data structure of a network of logic function blocks representing the electronic system from the HDL description, the network comprising dataflow elements corresponding to the dataflow operations and control logic corresponding to the control operations; partitioning the network into a plurality of program partitions based on reducing communication between partitions, each partition comprising dataflow operations corresponding to dataflow elements that are connected together, and control operations corresponding to control logic that controls those dataflow elements; compiling the plurality of program partitions to generate arithmetic/logic instructions corresponding to the dataflow operations and control flow instructions based on the corresponding control logic for a plurality of general purpose processors based on efficient communication between processors; parsing the HDL description; traversing busses in the HDL description to identify dataflow operations and traversing control signals to identify control operations associated with the dataflow operations; creating a data structure of a network of logic function blocks representing the electronic system from the HDL description, the network comprising dataflow elements corresponding to the dataflow operations and control logic corresponding to the control operations; partitioning the network into a plurality of program partitions based on reducing communication between partitions, each partition comprising dataflow operations corresponding to dataflow elements that are connected together, and control operations corresponding to control logic that controls those dataflow elements; compiling the plurality of program partitions to generate arithmetic/logic instructions corresponding to the dataflow operations and control flow instructions based on the corresponding control logic for a plurality of general purpose processors based on efficient communication between processors; assigning the plurality of programs to a plurality of processors based on efficient communication between processors, wherein efficiency is measured in terms of shorter latency and/or higher bandwidth; and downloading each of the plurality of programs to an instruction memory of one of a plurality of processors.