A computer-implemented method of rescaling a design of an integrated circuit to retain the functionality, latency, bandwidth and interface of an original circuit (105; 209; 309), wherein the integrated circuit comprises the original circuit (105; 209; 309) to be rescaled and designed to operate at a frequency F o, the original circuit (105; 209; 309) including a set of sequential nodes (111, 112; 213-218; 311, 312), a set of combinational nodes (A, B, C,...) and a set of interconnections, wherein each sequential node (111, 112; 213-218; 311, 312) in the original circuit (105; 209; 309) is associated with a phase φ of a clock, the method comprising: generating a rescaled circuit of said original circuit, said rescaled circuit designed to operate at a fractional frequency F o /k and comprising a plurality of k replica circuits (125, 126; 251, 252; 301-304), wherein k is an integer greater than 1, wherein each of said k replica circuits (125,126; 251, 252; 301-304) includes a replica set of sequential nodes (121, 122, 123, 124; 233-237, 243-237), a replica set of combinational nodes (A, B, C,...; A', B', C',...), and a replica set of interconnects that are identical to the set of sequential nodes (111, 112; 213-218; 311, 312), the set of combinational nodes (A, B, C,...) and the set of interconnections in the original circuit (105; 209; 309), wherein each of the sequential nodes (121, 122, 123, 124; 233-237, 243-237) of the k replica circuits is associated with a phase φ' of a clock that is at a fraction of the phase φ of its corresponding sequential node on the original circuit, where: φ ′ = φ + 360 ° × i / k wherein i ∈ {0,1,..., k - 1} is the index of replica circuits; wherein the replica set of sequential nodes (121, 122, 123, 124; 233-237, 243-237) has inputs that are logically equivalent to inputs of the set of sequential nodes (111, 112; 213-218; 311, 312) in the original circuit (105; 209; 309); and wherein generating the rescaled circuit of said original circuit comprises establishing connections between the plurality of k replica circuits according to their logical equivalency with the sequential nodes (111, 112; 213-218; 311, 312) of the original circuit and clock phase φ' of the k replica circuits; replacing the original circuit (105; 209; 309) in the design of the integrated circuit with the rescaled circuit. generating a rescaled circuit of said original circuit, said rescaled circuit designed to operate at a fractional frequency F o /k and comprising a plurality of k replica circuits (125, 126; 251, 252; 301-304), wherein k is an integer greater than 1, wherein each of said k replica circuits (125,126; 251, 252; 301-304) includes a replica set of sequential nodes (121, 122, 123, 124; 233-237, 243-237), a replica set of combinational nodes (A, B, C,...; A', B', C',...), and a replica set of interconnects that are identical to the set of sequential nodes (111, 112; 213-218; 311, 312), the set of combinational nodes (A, B, C,...) and the set of interconnections in the original circuit (105; 209; 309), wherein each of the sequential nodes (121, 122, 123, 124; 233-237, 243-237) of the k replica circuits is associated with a phase φ' of a clock that is at a fraction of the phase φ of its corresponding sequential node on the original circuit, where: φ ′ = φ + 360 ° × i / k wherein i ∈ {0,1,..., k - 1} is the index of replica circuits; wherein the replica set of sequential nodes (121, 122, 123, 124; 233-237, 243-237) has inputs that are logically equivalent to inputs of the set of sequential nodes (111, 112; 213-218; 311, 312) in the original circuit (105; 209; 309); and wherein generating the rescaled circuit of said original circuit comprises establishing connections between the plurality of k replica circuits according to their logical equivalency with the sequential nodes (111, 112; 213-218; 311, 312) of the original circuit and clock phase φ' of the k replica circuits; replacing the original circuit (105; 209; 309) in the design of the integrated circuit with the rescaled circuit. wherein i ∈ {0,1,..., k - 1} is the index of replica circuits; wherein the replica set of sequential nodes (121, 122, 123, 124; 233-237, 243-237) has inputs that are logically equivalent to inputs of the set of sequential nodes (111, 112; 213-218; 311, 312) in the original circuit (105; 209; 309); and wherein generating the rescaled circuit of said original circuit comprises establishing connections between the plurality of k replica circuits according to their logical equivalency with the sequential nodes (111, 112; 213-218; 311, 312) of the original circuit and clock phase φ' of the k replica circuits; replacing the original circuit (105; 209; 309) in the design of the integrated circuit with the rescaled circuit.