A multi-mode terminal configured to work in a multi-mode dual active mode or in a multi-mode single standby mode, comprising: a power management chip, a digital baseband chip, a first radio frequency chip, a second radio frequency chip, a first card socket, a second card socket, a first clock source and a second clock source, wherein: the power management chip is connected to the digital baseband chip, the first card socket and the second card socket to supply power to the digital baseband chip, the first card socket and the second card socket; the digital baseband chip is further connected to the first card socket and the second card socket, and is respectively connected to the first radio frequency chip and the second radio frequency chip through an in-phase/quadrature (I/Q) data line and a control line to transmit, receive and process I/Q signals with supported modes, as well as control transmission paths and reception paths with the supported modes; the first clock source is connected to the first radio frequency chip, the second clock source is connected to the second radio frequency chip; when the multi-mode terminal switches to a multi-mode dual active mode, the first clock source is configured to provide the reference clock for the first radio frequency chip and the second clock source is configured to provide the reference clock for the second radio frequency chip; and a clock path is further connected between the first radio frequency chip and the second radio frequency chip, and the first radio frequency chip is configured to provide an output clock for the second radio frequency chip through the clock path to serve as the reference clock of the second radio frequency chip when the multi-mode terminal switches to a multi-mode single standby mode. the power management chip is connected to the digital baseband chip, the first card socket and the second card socket to supply power to the digital baseband chip, the first card socket and the second card socket; the digital baseband chip is further connected to the first card socket and the second card socket, and is respectively connected to the first radio frequency chip and the second radio frequency chip through an in-phase/quadrature (I/Q) data line and a control line to transmit, receive and process I/Q signals with supported modes, as well as control transmission paths and reception paths with the supported modes; the first clock source is connected to the first radio frequency chip, the second clock source is connected to the second radio frequency chip; when the multi-mode terminal switches to a multi-mode dual active mode, the first clock source is configured to provide the reference clock for the first radio frequency chip and the second clock source is configured to provide the reference clock for the second radio frequency chip; and a clock path is further connected between the first radio frequency chip and the second radio frequency chip, and the first radio frequency chip is configured to provide an output clock for the second radio frequency chip through the clock path to serve as the reference clock of the second radio frequency chip when the multi-mode terminal switches to a multi-mode single standby mode.