A circuit, comprising: a resistor (RCON), a normal capacitor (130A, 210A) and a ferroelectric capacitor (160A, 250A) that are connected in series; an input terminal to provide an input voltage across the circuit; and an output terminal to deliver an output voltage taken across the normal capacitor (130A, 210A), wherein the circuit is an integrated circuit formed on a substrate (185A, 285A), the circuit comprises: a ferroelectric layer (170A, 265A) sandwiched between a first buffer layer (175A, 270A) and a second buffer layer (165A, 260A), wherein the first buffer layer (175A, 270A) contacts a portion of a surface of a first metal layer (180A, 280A) and the first metal layer (180A, 280A) extends beyond the first buffer layer, wherein the first metal layer (180A, 280A) is arranged on the substrate (185A, 285A); and a dielectric layer (140A, 230A) sandwiched between a second metal layer (162A, 255A) and a third metal layer (135A, 225A), such that the second metal layer (162A, 255A) extends beyond the dielectric layer (140A, 230A) and in contact with the second buffer layer (165A, 260A), wherein the ferroelectric capacitor (160A, 250A) is formed by the first metal (185A, 285A) layer, the ferroelectric layer (170A, 265A) sandwiched between the first buffer layer (175A, 270A) and the second buffer layer (165A, 260A), and the second metal layer (162A, 255A), and wherein the normal capacitor (130A, 210A) is formed by the dielectric layer (140A, 230A) and the third metal layer (135A, 225A); wherein the first metal layer (180A, 280A) and the third metal layer (135A, 225A) serve as the input terminal, and the second metal layer (162A, 255A) and the third metal layer (135A, 225A) serve as the output terminal. a resistor (RCON), a normal capacitor (130A, 210A) and a ferroelectric capacitor (160A, 250A) that are connected in series; an input terminal to provide an input voltage across the circuit; and an output terminal to deliver an output voltage taken across the normal capacitor (130A, 210A), wherein the circuit is an integrated circuit formed on a substrate (185A, 285A), the circuit comprises: a ferroelectric layer (170A, 265A) sandwiched between a first buffer layer (175A, 270A) and a second buffer layer (165A, 260A), wherein the first buffer layer (175A, 270A) contacts a portion of a surface of a first metal layer (180A, 280A) and the first metal layer (180A, 280A) extends beyond the first buffer layer, wherein the first metal layer (180A, 280A) is arranged on the substrate (185A, 285A); and a dielectric layer (140A, 230A) sandwiched between a second metal layer (162A, 255A) and a third metal layer (135A, 225A), such that the second metal layer (162A, 255A) extends beyond the dielectric layer (140A, 230A) and in contact with the second buffer layer (165A, 260A), wherein the ferroelectric capacitor (160A, 250A) is formed by the first metal (185A, 285A) layer, the ferroelectric layer (170A, 265A) sandwiched between the first buffer layer (175A, 270A) and the second buffer layer (165A, 260A), and the second metal layer (162A, 255A), and wherein the normal capacitor (130A, 210A) is formed by the dielectric layer (140A, 230A) and the third metal layer (135A, 225A); wherein the first metal layer (180A, 280A) and the third metal layer (135A, 225A) serve as the input terminal, and the second metal layer (162A, 255A) and the third metal layer (135A, 225A) serve as the output terminal. a ferroelectric layer (170A, 265A) sandwiched between a first buffer layer (175A, 270A) and a second buffer layer (165A, 260A), wherein the first buffer layer (175A, 270A) contacts a portion of a surface of a first metal layer (180A, 280A) and the first metal layer (180A, 280A) extends beyond the first buffer layer, wherein the first metal layer (180A, 280A) is arranged on the substrate (185A, 285A); and a dielectric layer (140A, 230A) sandwiched between a second metal layer (162A, 255A) and a third metal layer (135A, 225A), such that the second metal layer (162A, 255A) extends beyond the dielectric layer (140A, 230A) and in contact with the second buffer layer (165A, 260A), wherein the ferroelectric capacitor (160A, 250A) is formed by the first metal (185A, 285A) layer, the ferroelectric layer (170A, 265A) sandwiched between the first buffer layer (175A, 270A) and the second buffer layer (165A, 260A), and the second metal layer (162A, 255A), and wherein the normal capacitor (130A, 210A) is formed by the dielectric layer (140A, 230A) and the third metal layer (135A, 225A); wherein the first metal layer (180A, 280A) and the third metal layer (135A, 225A) serve as the input terminal, and the second metal layer (162A, 255A) and the third metal layer (135A, 225A) serve as the output terminal.