A gate driver (11, 12) for outputting gate signals to gate lines of a display, the gate driver comprising a plurality of stages (STA1,... STA4, STB1,..., STB4), wherein a stage (STAq) of the plurality of stages includes: a pull-up transistor configured to output a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor configured to output a first source voltage input to a first source voltage terminal (VSST) to the output terminal depending on a voltage of a pull-down node; a boosting capacitor connected between the output terminal and the pull-up node and configured to maintain a difference voltage between the output terminal and the pull-up node; and a first noise removing unit configured to supply a gate-off voltage to the pull-up node to remove noise of the pull-up node, characterized by the first noise removing unit comprising: a first transistor configured to be turned on in response to a gate-on voltage of a first node and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the pull-up node; a second transistor configured to be turned on in response to a gate-on voltage of the clock signal input to the first clock terminal and to thereby supply the gate-on voltage of the clock signal to the first node; and a third transistor configured to be turned on in response to a gate-on voltage of the pull-up node and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the first node; and the stage (STAq) further including a second noise removing unit including a fifth transistor configured to be turned on in response to a gate-on voltage of another clock signal input to a second clock terminal and to thereby connect the pull-up node to an input terminal configured to receive the output signal of a previous stage (STAq-1). a pull-up transistor configured to output a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor configured to output a first source voltage input to a first source voltage terminal (VSST) to the output terminal depending on a voltage of a pull-down node; a boosting capacitor connected between the output terminal and the pull-up node and configured to maintain a difference voltage between the output terminal and the pull-up node; and a first noise removing unit configured to supply a gate-off voltage to the pull-up node to remove noise of the pull-up node, a first transistor configured to be turned on in response to a gate-on voltage of a first node and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the pull-up node; a second transistor configured to be turned on in response to a gate-on voltage of the clock signal input to the first clock terminal and to thereby supply the gate-on voltage of the clock signal to the first node; and a third transistor configured to be turned on in response to a gate-on voltage of the pull-up node and to thereby supply the first source voltage of the first source voltage terminal (VSST) to the first node; and the stage (STAq) further including a second noise removing unit including a fifth transistor configured to be turned on in response to a gate-on voltage of another clock signal input to a second clock terminal and to thereby connect the pull-up node to an input terminal configured to receive the output signal of a previous stage (STAq-1).