A liquid crystal display device comprising a plurality of pixel areas defined by intersections of a plurality of gate lines and a plurality of data lines, each of the plurality of pixel areas comprising: a gate line and a gate disposed on a substrate the gate line including the gate; a gate insulator disposed to cover the gate line and the gate; a semiconductor layer disposed on the gate insulator, a portion of the semiconductor layer being an active layer disposed on only the gate with the gate insulator therebetween; a thin film transistor comprising the active layer, the gate, the gate insulator, a source which is a first side portion of the semiconductor layer at a first side of the active layer, a drain which is a second side portion of the semiconductor layer at a second side of the active layer, and a lightly doped drain (LDD 144) which is a portion of the semiconductor layer disposed between the active layer and the source and between the active layer and the drain; a pixel electrode connected to the drain of the thin film transistor and configured to supply a data voltage to the pixel area; a common electrode configured to supply a common voltage to the pixel area; wherein at least a portion of the lightly doped drain (LDD 144) is disposed on the gate, characterized in that the semiconductor layer comprises a first part comprising the source and extending along and overlapping one of two data lines defining the pixel area, a second part comprising the drain and extending parallel to and between the two data lines defining the pixel area, and a connecting part connecting the first part to the second part of the semiconductor layer, the connecting part comprising the active layer, and wherein the connecting part of the semiconductor layer extends along and overlaps the gate line of the pixel area. a gate line and a gate disposed on a substrate the gate line including the gate; a gate insulator disposed to cover the gate line and the gate; a semiconductor layer disposed on the gate insulator, a portion of the semiconductor layer being an active layer disposed on only the gate with the gate insulator therebetween; a thin film transistor comprising the active layer, the gate, the gate insulator, a source which is a first side portion of the semiconductor layer at a first side of the active layer, a drain which is a second side portion of the semiconductor layer at a second side of the active layer, and a lightly doped drain (LDD 144) which is a portion of the semiconductor layer disposed between the active layer and the source and between the active layer and the drain; a pixel electrode connected to the drain of the thin film transistor and configured to supply a data voltage to the pixel area; a common electrode configured to supply a common voltage to the pixel area; wherein at least a portion of the lightly doped drain (LDD 144) is disposed on the gate, characterized in that the semiconductor layer comprises a first part comprising the source and extending along and overlapping one of two data lines defining the pixel area, a second part comprising the drain and extending parallel to and between the two data lines defining the pixel area, and a connecting part connecting the first part to the second part of the semiconductor layer, the connecting part comprising the active layer, and wherein the connecting part of the semiconductor layer extends along and overlaps the gate line of the pixel area.