A device adapted to implement a state machine which defines a plurality of predetermined states and a plurality of predetermined events, for decoding USB data communicated over a universal serial bus, the device comprising: a pair of data input terminals for receiving the USB data, and a clock input terminal for receiving a system clock; a clock processor coupled to the pair of data input terminals and the clock input terminal, and configured to output, based on the system clock, synchronized data and a device clock; an event generator coupled to the clock processor to receive the synchronized data and the device clock; state logic circuitry coupled to an output of the event generator; output terminals, coupled to the event generator and comprising a decoded-data output terminal and a clock output terminal; and control circuity coupled to the event generator and for providing control information to the event generator; wherein the state logic circuitry is configured to store a present state, being one of the predetermined states; wherein the event generator is configured to trigger respective ones of the predetermined events, in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state; wherein: a one of the predetermined events comprises identifying a stuffed-bit in the synchronized data, another of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data, a combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data, and a further of the predetermined events comprises outputting, at the output terminals, the decoded stuffed-bit stripped synchronized data and toggling the output clock. a pair of data input terminals for receiving the USB data, and a clock input terminal for receiving a system clock; a clock processor coupled to the pair of data input terminals and the clock input terminal, and configured to output, based on the system clock, synchronized data and a device clock; an event generator coupled to the clock processor to receive the synchronized data and the device clock; state logic circuitry coupled to an output of the event generator; output terminals, coupled to the event generator and comprising a decoded-data output terminal and a clock output terminal; and control circuity coupled to the event generator and for providing control information to the event generator; wherein the state logic circuitry is configured to store a present state, being one of the predetermined states; wherein the event generator is configured to trigger respective ones of the predetermined events, in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state; wherein: a one of the predetermined events comprises identifying a stuffed-bit in the synchronized data, another of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data, a combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data, and a further of the predetermined events comprises outputting, at the output terminals, the decoded stuffed-bit stripped synchronized data and toggling the output clock. a one of the predetermined events comprises identifying a stuffed-bit in the synchronized data, another of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data, a combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data, and a further of the predetermined events comprises outputting, at the output terminals, the decoded stuffed-bit stripped synchronized data and toggling the output clock.