A method for preparing a target quantum state of a quantum system register comprising multiple target qubits on a quantum computer, the method performed by one or more classical processors and quantum hardware of the quantum computer, the quantum hardware comprising one or more control devices and a quantum circuit, which comprises the quantum system register and a unary register comprising multiple control qubits, wherein the target quantum state comprises a superposition of L computational basis states, the method comprising, sequentially for each index l = 1 to l = L: preparing the quantum system register and the unary register in a quantum state, wherein preparing the quantum system register and a unary register in a quantum state comprises preparing the quantum system register and unary register in a quantum state | ψ l 〉 = β l | D l 〉 | 1 〉 + ∑ l ′ = 1 l − 1 α l ′ | D l ′ 〉 | 0 〉, wherein l represents the index, | D l 〉 represents the 1-th computational basis state, α represents a computational basis state amplitude, and β l is a normalization term, wherein: the state of the quantum system register is entangled with the unary register, at an initial time step the state of the quantum system register equals the target quantum state up to the first (l-1) computational basis states if the state of the unary register is |0〉, and the state of the quantum system register equals the 1-th computational basis state if the unary register is in state 11); selecting a target qubit from the quantum system register whose occupation number is different in the 1-th computational basis state and the l+1-th computational basis state; applying a rotation to the selected qubit, wherein the rotation is controlled by the state of a unary register; erasing the unary register state for the 1-th computational basis state; and implementing a NOT logic gate on the remaining target qubits in the quantum system register whose occupation numbers are different in the l-th computational basis state and the l+1-th computational basis state, wherein implementation of the NOT logic gate is controlled by the state of the unary register. preparing the quantum system register and the unary register in a quantum state, wherein preparing the quantum system register and a unary register in a quantum state comprises preparing the quantum system register and unary register in a quantum state | ψ l 〉 = β l | D l 〉 | 1 〉 + ∑ l ′ = 1 l − 1 α l ′ | D l ′ 〉 | 0 〉, wherein l represents the index, | D l 〉 represents the 1-th computational basis state, α represents a computational basis state amplitude, and β l is a normalization term, wherein: the state of the quantum system register is entangled with the unary register, at an initial time step the state of the quantum system register equals the target quantum state up to the first (l-1) computational basis states if the state of the unary register is |0〉, and the state of the quantum system register equals the 1-th computational basis state if the unary register is in state 11); the state of the quantum system register is entangled with the unary register, at an initial time step the state of the quantum system register equals the target quantum state up to the first (l-1) computational basis states if the state of the unary register is |0〉, and the state of the quantum system register equals the 1-th computational basis state if the unary register is in state 11); selecting a target qubit from the quantum system register whose occupation number is different in the 1-th computational basis state and the l+1-th computational basis state; applying a rotation to the selected qubit, wherein the rotation is controlled by the state of a unary register; erasing the unary register state for the 1-th computational basis state; and implementing a NOT logic gate on the remaining target qubits in the quantum system register whose occupation numbers are different in the l-th computational basis state and the l+1-th computational basis state, wherein implementation of the NOT logic gate is controlled by the state of the unary register.