A switching regulator circuit comprising: a first switching transistor having an input terminal to receive an input voltage and an output terminal coupled to an output node; a ramp generator to produce a ramp signal having a period; and a comparator to receive the ramp signal and an error signal, the output of the comparator is coupled to a flip flop, and in accordance therewith, produce a modulation signal, wherein, in a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of the first switching transistor during each period of the ramp signal, and in a second mode of operation, the error signal increase above a maximum value of the ramp signal, and in accordance therewith, the first switching transistor is turned on for one or more full periods of the ramp signal; and the ramp generator further comprising: a current feedback circuit to sense a current in the switching regulator and produce an offset in the ramp signal, wherein said maximum value of the ramp signal is less than a maximum value of the error signal; a current source; a capacitor having a terminal coupled to the current source; a switch; and an OR gate having a first input coupled to receive a reset signal and a second input coupled to receive the modulation signal, wherein the ramp signal has a constant value when the reset signal is in a first state, and wherein the ramp signal increases to said maximum value when the reset signal is in a second state; wherein the magnitude of the current source and the offset are configured to set said maximum value to be less than a maximum value of the error signal. a first switching transistor having an input terminal to receive an input voltage and an output terminal coupled to an output node; a ramp generator to produce a ramp signal having a period; and a comparator to receive the ramp signal and an error signal, the output of the comparator is coupled to a flip flop, and in accordance therewith, produce a modulation signal, wherein, in a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of the first switching transistor during each period of the ramp signal, and in a second mode of operation, the error signal increase above a maximum value of the ramp signal, and in accordance therewith, the first switching transistor is turned on for one or more full periods of the ramp signal; and the ramp generator further comprising: a current feedback circuit to sense a current in the switching regulator and produce an offset in the ramp signal, wherein said maximum value of the ramp signal is less than a maximum value of the error signal; a current source; a capacitor having a terminal coupled to the current source; a switch; and an OR gate having a first input coupled to receive a reset signal and a second input coupled to receive the modulation signal, wherein the ramp signal has a constant value when the reset signal is in a first state, and wherein the ramp signal increases to said maximum value when the reset signal is in a second state; wherein the magnitude of the current source and the offset are configured to set said maximum value to be less than a maximum value of the error signal. a current feedback circuit to sense a current in the switching regulator and produce an offset in the ramp signal, wherein said maximum value of the ramp signal is less than a maximum value of the error signal; a current source; a capacitor having a terminal coupled to the current source; a switch; and an OR gate having a first input coupled to receive a reset signal and a second input coupled to receive the modulation signal, wherein the ramp signal has a constant value when the reset signal is in a first state, and wherein the ramp signal increases to said maximum value when the reset signal is in a second state; wherein the magnitude of the current source and the offset are configured to set said maximum value to be less than a maximum value of the error signal.