An organic light emitting diode (OLED) display, comprising: a data driver for applying a plurality of data signals to a plurality of data lines (D1-Dn); a scan driver for applying a plurality of scan signals to a plurality of scan lines (S1-Sn); a driving transistor for generating a current corresponding to a voltage supplied from a first electrode and a control electrode; a switching transistor for applying the data signal to the driving transistor; an OLED electrically connected to the driving transistor; and an inspection circuit for inspecting the scan signal including: a first signal input section for generating and outputting to the scan driver a frame pulse, a first shiftclock signal (SFTCLK), and a second shiftclock signal (SFTCLKB); a second signal input section for generating and outputting to the scan driver a first clock signal (SCLK1) and a second clock signal (SCLK2); and a signal receiving unit for receiving a scan signal output from at least one of the plurality of scan lines (S1-Sn), and generating and outputting an output signal corresponding to the received scan signal; wherein the first signal input section includes: a first transistor; and a first tri-state inverter circuit having an input terminal and an output terminal, wherein the first transistor is arranged to supply a second power voltage to the output terminal of the first tri-state inverter circuit when an output signal of the first tri-state inverter circuit is determined regardless of a signal input to the input terminal of the first tri-state inverter circuit; and wherein the second signal input section includes: a second transistor; and a second tri-state inverter circuit having an input terminal and an output terminal, wherein the second transistor supplies a first power voltage (VVDD) to the output terminal of the second tri-state inverter circuit when an output signal of the second tri-state inverter circuit is determined regardless of a signal input to the input terminal of the second tri-state inverter circuit. a data driver for applying a plurality of data signals to a plurality of data lines (D1-Dn); a scan driver for applying a plurality of scan signals to a plurality of scan lines (S1-Sn); a driving transistor for generating a current corresponding to a voltage supplied from a first electrode and a control electrode; a switching transistor for applying the data signal to the driving transistor; an OLED electrically connected to the driving transistor; and an inspection circuit for inspecting the scan signal including: a first signal input section for generating and outputting to the scan driver a frame pulse, a first shiftclock signal (SFTCLK), and a second shiftclock signal (SFTCLKB); a second signal input section for generating and outputting to the scan driver a first clock signal (SCLK1) and a second clock signal (SCLK2); and a signal receiving unit for receiving a scan signal output from at least one of the plurality of scan lines (S1-Sn), and generating and outputting an output signal corresponding to the received scan signal; a first signal input section for generating and outputting to the scan driver a frame pulse, a first shiftclock signal (SFTCLK), and a second shiftclock signal (SFTCLKB); a second signal input section for generating and outputting to the scan driver a first clock signal (SCLK1) and a second clock signal (SCLK2); and a signal receiving unit for receiving a scan signal output from at least one of the plurality of scan lines (S1-Sn), and generating and outputting an output signal corresponding to the received scan signal; a first transistor; and a first tri-state inverter circuit having an input terminal and an output terminal, wherein the first transistor is arranged to supply a second power voltage to the output terminal of the first tri-state inverter circuit when an output signal of the first tri-state inverter circuit is determined regardless of a signal input to the input terminal of the first tri-state inverter circuit; and a second transistor; and a second tri-state inverter circuit having an input terminal and an output terminal, wherein the second transistor supplies a first power voltage (VVDD) to the output terminal of the second tri-state inverter circuit when an output signal of the second tri-state inverter circuit is determined regardless of a signal input to the input terminal of the second tri-state inverter circuit.