A sending arrangement, being providable: - with data signals transportable on at least one data line (CH0+, CH0-, CH1+, CH1-, CH2+, CH2-, CH3+, CH3-) wherein each of the data lines (CH0+, CH0-, CH1+, CH1-, CH2+, CH2-, CH3+, CH3-) is provided with -- single-ended logic-level-based data signals (HSD0, HSD1, HSD2, HSD3) as well as -- differential common-mode-based data signals (DD0+, DD0-, DD1+, DD1-, DD2+, DD2-, DD3+, DD3-), and - with clock signals transportable on at least one clock line (CLK+, CLK-) wherein each of the clock lines (CLK+, CLK-) is provided with -- single-ended logic-level-based clock signals as well as -- differential common-mode-based clock signals, - wherein the sending arrangement serializes the single-ended logic-level-based data signals and clock signals and the differential common-mode-based data signals and clock signals in the form of a common signal stream and - wherein the sending arrangement comprises: -- at least one clock generator for generating at least one reference clock on at least one clock line, -- at least one serializer connected downstream of the clock generator, the serializer being provided with a stop state recognizable on the clock line and inserting at least one stop sequence assigned to the stop state into the common signal stream, due to which stop sequence it is recognizable for at least one receiving arrangement that the transmission of the common signal stream is switched off upon expiry of at least one defined time interval, and -- at least one detection/control means connected upstream of the clock generator for recognizing the stop state on the clock line and for time-delayed passing on of at least one switch-off signal assigned to the stop state to the clock generator by means of which switch-off signal the clock generator and the serializer are switched to idle state. - with data signals transportable on at least one data line (CH0+, CH0-, CH1+, CH1-, CH2+, CH2-, CH3+, CH3-) wherein each of the data lines (CH0+, CH0-, CH1+, CH1-, CH2+, CH2-, CH3+, CH3-) is provided with -- single-ended logic-level-based data signals (HSD0, HSD1, HSD2, HSD3) as well as -- differential common-mode-based data signals (DD0+, DD0-, DD1+, DD1-, DD2+, DD2-, DD3+, DD3-), and -- single-ended logic-level-based data signals (HSD0, HSD1, HSD2, HSD3) as well as -- differential common-mode-based data signals (DD0+, DD0-, DD1+, DD1-, DD2+, DD2-, DD3+, DD3-), and - with clock signals transportable on at least one clock line (CLK+, CLK-) wherein each of the clock lines (CLK+, CLK-) is provided with -- single-ended logic-level-based clock signals as well as -- differential common-mode-based clock signals, -- single-ended logic-level-based clock signals as well as -- differential common-mode-based clock signals, - wherein the sending arrangement serializes the single-ended logic-level-based data signals and clock signals and the differential common-mode-based data signals and clock signals in the form of a common signal stream and - wherein the sending arrangement comprises: -- at least one clock generator for generating at least one reference clock on at least one clock line, -- at least one serializer connected downstream of the clock generator, the serializer being provided with a stop state recognizable on the clock line and inserting at least one stop sequence assigned to the stop state into the common signal stream, due to which stop sequence it is recognizable for at least one receiving arrangement that the transmission of the common signal stream is switched off upon expiry of at least one defined time interval, and -- at least one detection/control means connected upstream of the clock generator for recognizing the stop state on the clock line and for time-delayed passing on of at least one switch-off signal assigned to the stop state to the clock generator by means of which switch-off signal the clock generator and the serializer are switched to idle state. -- at least one clock generator for generating at least one reference clock on at least one clock line, -- at least one serializer connected downstream of the clock generator, the serializer being provided with a stop state recognizable on the clock line and inserting at least one stop sequence assigned to the stop state into the common signal stream, due to which stop sequence it is recognizable for at least one receiving arrangement that the transmission of the common signal stream is switched off upon expiry of at least one defined time interval, and -- at least one detection/control means connected upstream of the clock generator for recognizing the stop state on the clock line and for time-delayed passing on of at least one switch-off signal assigned to the stop state to the clock generator by means of which switch-off signal the clock generator and the serializer are switched to idle state.