A multi-core processor (100, 900, 1100, 1200, 1400, 1500, 1600, 1800, 1900, 2000, 2100, 2200) comprising a plurality of physical processing cores, characterized in that: the processor includes a domain (102, 104, 1202, 1502, 1504) comprising at least two of the microprocessor's cores; the processor provides a resource to the domain, which resource is shared by the cores of the domain; the resource is configurable to accommodate a plurality of operating states restricting, to relatively different degrees, the power, speed, or efficiency with which the cores sharing the resource are able to operate; each enabled core in the domain has a target operating state; each core comprises inter-core state discovery microcode enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores; the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; each instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the instance; and the synchronization logic is configured to: coordinate with other enabled cores in the domain to discover whether a more restrictive target operating state than a currently implemented operating state can be implemented; recursively invoke, unless it detects a termination condition, instances of synchronization logic on other cores until synchronized instances of the synchronization logic have been invoked on all of the cores of the domain; and detect a termination condition defined by a discovery, from a synchronized instance of the synchronization logic, that another core in the domain has a target operating state that is not more restrictive than the currently implemented operating state; and enable implementation of the more restrictive target operating state if and only if the core is authorized to configure the resource and each of the enabled cores in the domain sharing the resource has a target operating state at least as restrictive as the more restrictive operating state. the processor includes a domain (102, 104, 1202, 1502, 1504) comprising at least two of the microprocessor's cores; the processor provides a resource to the domain, which resource is shared by the cores of the domain; the resource is configurable to accommodate a plurality of operating states restricting, to relatively different degrees, the power, speed, or efficiency with which the cores sharing the resource are able to operate; each enabled core in the domain has a target operating state; each core comprises inter-core state discovery microcode enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores; the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; each instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the instance; and the synchronization logic is configured to: coordinate with other enabled cores in the domain to discover whether a more restrictive target operating state than a currently implemented operating state can be implemented; recursively invoke, unless it detects a termination condition, instances of synchronization logic on other cores until synchronized instances of the synchronization logic have been invoked on all of the cores of the domain; and detect a termination condition defined by a discovery, from a synchronized instance of the synchronization logic, that another core in the domain has a target operating state that is not more restrictive than the currently implemented operating state; and enable implementation of the more restrictive target operating state if and only if the core is authorized to configure the resource and each of the enabled cores in the domain sharing the resource has a target operating state at least as restrictive as the more restrictive operating state. coordinate with other enabled cores in the domain to discover whether a more restrictive target operating state than a currently implemented operating state can be implemented; recursively invoke, unless it detects a termination condition, instances of synchronization logic on other cores until synchronized instances of the synchronization logic have been invoked on all of the cores of the domain; and detect a termination condition defined by a discovery, from a synchronized instance of the synchronization logic, that another core in the domain has a target operating state that is not more restrictive than the currently implemented operating state; and enable implementation of the more restrictive target operating state if and only if the core is authorized to configure the resource and each of the enabled cores in the domain sharing the resource has a target operating state at least as restrictive as the more restrictive operating state.