An electrostatic discharge structure, comprising: a substrate; a positive power supply, negative power supply, and input formed on the substrate; an ESD active circuit formed on the substrate and connected to the substrate, positive power supply, the negative power supply and the input; a through wafer via structure electrically connected to the negative power supply and the substrate to provide a low series resistance path between the negative power supply and the substrate; and a ground plane formed on a bottom of the substrate and in contact with the through wafer via structure, the ESD structure further comprising further through wafer vias (510, 705, 1105) in contact with the ground plane and not directly connected with the negative power supply, wherein the through wafer via structure and the further through wafer vias (510, 705, 1105) collectively form a guard ring substantially surrounding the ESD active circuit to prevent minority carrier migration to or from the ESD active circuit, wherein the further through wafer vias of the guard ring comprise a first set of through wafer vias on one side of the ESD active circuit, and a second set of through wafer vias on an opposite side of the ESD active circuit, the first and second sets each comprising a plurality of through wafer vias each in contact with the ground plane and the through wafer vias of each set each extending laterally across the substrate parallel to one another and spaced apart from one another in a direction perpendicular to their lateral extent across the substrate, so as to lower the resistance of the ESD structure laterally and vertically. a substrate; a positive power supply, negative power supply, and input formed on the substrate; an ESD active circuit formed on the substrate and connected to the substrate, positive power supply, the negative power supply and the input; a through wafer via structure electrically connected to the negative power supply and the substrate to provide a low series resistance path between the negative power supply and the substrate; and a ground plane formed on a bottom of the substrate and in contact with the through wafer via structure, the ESD structure further comprising further through wafer vias (510, 705, 1105) in contact with the ground plane and not directly connected with the negative power supply, wherein the through wafer via structure and the further through wafer vias (510, 705, 1105) collectively form a guard ring substantially surrounding the ESD active circuit to prevent minority carrier migration to or from the ESD active circuit, wherein the further through wafer vias of the guard ring comprise a first set of through wafer vias on one side of the ESD active circuit, and a second set of through wafer vias on an opposite side of the ESD active circuit, the first and second sets each comprising a plurality of through wafer vias each in contact with the ground plane and the through wafer vias of each set each extending laterally across the substrate parallel to one another and spaced apart from one another in a direction perpendicular to their lateral extent across the substrate, so as to lower the resistance of the ESD structure laterally and vertically.