An apparatus comprising: a processing circuitry, the processing circuitry configured to, demodulate a message, wherein the message is to indicate switching to 256-quadradture amplitude modulation, QAM, scheme from an existing non-256-QAM scheme; a memory (205, 305) configured to store soft channel bits such that the number of the soft channel bits for using the 256-QAM scheme is within 20% above or below the number of the soft channel bits stored while a user equipment, UE, is using the existing non-256-QAM scheme, wherein the existing non-256-QAM scheme is to support a maximum number of 2 or 4 layers for spatial multiplexing in downlink; and logic that: processes a transport block associated with the 256-QAM scheme, wherein the transport block has a size larger than a transport block size of the existing non-256-QAM scheme; discards a first number of parity bits (502; 602) for a modulation and coding scheme, MCS, when the UE is configured to apply the 256-QAM scheme; and discards a second number of parity bits for the MCS when the UE is configured to apply the existing non-256-QAM scheme, the first number of parity bits being greater than the second number of parity bits, wherein the logic discards the first number of parity bits according to a rate matching pattern rate, which remains the same after switching to the 256-QAM scheme. a processing circuitry, the processing circuitry configured to, demodulate a message, wherein the message is to indicate switching to 256-quadradture amplitude modulation, QAM, scheme from an existing non-256-QAM scheme; a memory (205, 305) configured to store soft channel bits such that the number of the soft channel bits for using the 256-QAM scheme is within 20% above or below the number of the soft channel bits stored while a user equipment, UE, is using the existing non-256-QAM scheme, wherein the existing non-256-QAM scheme is to support a maximum number of 2 or 4 layers for spatial multiplexing in downlink; and logic that: processes a transport block associated with the 256-QAM scheme, wherein the transport block has a size larger than a transport block size of the existing non-256-QAM scheme; discards a first number of parity bits (502; 602) for a modulation and coding scheme, MCS, when the UE is configured to apply the 256-QAM scheme; and discards a second number of parity bits for the MCS when the UE is configured to apply the existing non-256-QAM scheme, the first number of parity bits being greater than the second number of parity bits, wherein the logic discards the first number of parity bits according to a rate matching pattern rate, which remains the same after switching to the 256-QAM scheme. processes a transport block associated with the 256-QAM scheme, wherein the transport block has a size larger than a transport block size of the existing non-256-QAM scheme; discards a first number of parity bits (502; 602) for a modulation and coding scheme, MCS, when the UE is configured to apply the 256-QAM scheme; and discards a second number of parity bits for the MCS when the UE is configured to apply the existing non-256-QAM scheme, the first number of parity bits being greater than the second number of parity bits, wherein the logic discards the first number of parity bits according to a rate matching pattern rate, which remains the same after switching to the 256-QAM scheme.