An electronic device (100, 400), comprising: a plurality of combinatorial logic modules (108,109); a random number generator; a plurality of signal generators (415,416), each one of the plurality of signal generators comprising a corresponding output (411,412) at which a corresponding clock signal of a plurality of clock signals is to be provided, wherein each of the corresponding clock signals having a clock transition of a first type and a clock transition of a second type during each period of a reference clock period (206,207), an order of the clock transitions of the first type provided by the plurality of signal generators is based upon information from the random number generator, and during each period of the reference clock period (206,207) a latest clock transition of the first type of the plurality of clock signals (202,203) precedes an earliest clock transition of the second type of the plurality of clock signals (202,203); and a plurality of storage elements (104,105), each storage element of the plurality of storage elements comprising: a data input (115, 116) coupled to a corresponding combinatorial logic module (108, 109) of the plurality of combinatorial logic modules, a clock input (111, 112) coupled to the output of a corresponding signal generator of the plurality of signal generators, and a data output (118, 119) and a a first latch coupled to the data input of the storage element and to the clock input of the storage element, wherein the first latch stores a value at the data input in response to a clock transition of the first type; and a second latch coupled to the first latch to receive the value stored at the first latch, wherein the second latch stores the received value in response to a clock transition of the second type and provides the stored value at its latch output coupled to the data output (118, 119). a plurality of combinatorial logic modules (108,109); a random number generator; a plurality of signal generators (415,416), each one of the plurality of signal generators comprising a corresponding output (411,412) at which a corresponding clock signal of a plurality of clock signals is to be provided, wherein each of the corresponding clock signals having a clock transition of a first type and a clock transition of a second type during each period of a reference clock period (206,207), an order of the clock transitions of the first type provided by the plurality of signal generators is based upon information from the random number generator, and during each period of the reference clock period (206,207) a latest clock transition of the first type of the plurality of clock signals (202,203) precedes an earliest clock transition of the second type of the plurality of clock signals (202,203); and each of the corresponding clock signals having a clock transition of a first type and a clock transition of a second type during each period of a reference clock period (206,207), an order of the clock transitions of the first type provided by the plurality of signal generators is based upon information from the random number generator, and during each period of the reference clock period (206,207) a latest clock transition of the first type of the plurality of clock signals (202,203) precedes an earliest clock transition of the second type of the plurality of clock signals (202,203); and a plurality of storage elements (104,105), each storage element of the plurality of storage elements comprising: a data input (115, 116) coupled to a corresponding combinatorial logic module (108, 109) of the plurality of combinatorial logic modules, a clock input (111, 112) coupled to the output of a corresponding signal generator of the plurality of signal generators, and a data output (118, 119) and a a first latch coupled to the data input of the storage element and to the clock input of the storage element, wherein the first latch stores a value at the data input in response to a clock transition of the first type; and a second latch coupled to the first latch to receive the value stored at the first latch, wherein the second latch stores the received value in response to a clock transition of the second type and provides the stored value at its latch output coupled to the data output (118, 119). a data input (115, 116) coupled to a corresponding combinatorial logic module (108, 109) of the plurality of combinatorial logic modules, a clock input (111, 112) coupled to the output of a corresponding signal generator of the plurality of signal generators, and a data output (118, 119) and a a first latch coupled to the data input of the storage element and to the clock input of the storage element, wherein the first latch stores a value at the data input in response to a clock transition of the first type; and a second latch coupled to the first latch to receive the value stored at the first latch, wherein the second latch stores the received value in response to a clock transition of the second type and provides the stored value at its latch output coupled to the data output (118, 119).