A device equipped for attack detection through signal delay monitoring, comprising: a signal processing component within the device; a physical interface for providing a signal to the signal processing component; at least one signal delay monitor (112',120') included in, or at least coupled to, the physical interface, wherein the at least one signal delay monitor (112',120') is to determine whether a signal originating outside of the device to be processed by the signal processing component is received as expected at the physical interface and indicate a potential attack when the signal is determined to not be received as expected, wherein in determining whether the signal is received as expected the signal delay monitor is to determine whether the signal is received within an expected reception window defining a time period in which receipt of the signal is expected, said signal representing data input, wherein the at least one signal delay monitor (112',120') comprises at least: a new data reception monitoring module including logic enabled by a system clock to compare a state of a data input in the physical interface to a previous state of the data input to determine if new data has been received at the physical interface, the said state of the data input being either a logical high or a logical low; and an expected reception window monitoring module including logic enabled by a window clock to determine if the state of the data input changes during the expected reception window, wherein in indicating a potential attack the signal delay monitor (112',120') is to set a fault bit based on logic that performs a logical AND on an output of the new data reception monitoring module and on an output of the expected reception window monitoring module. a signal processing component within the device; a physical interface for providing a signal to the signal processing component; at least one signal delay monitor (112',120') included in, or at least coupled to, the physical interface, wherein the at least one signal delay monitor (112',120') is to determine whether a signal originating outside of the device to be processed by the signal processing component is received as expected at the physical interface and indicate a potential attack when the signal is determined to not be received as expected, wherein in determining whether the signal is received as expected the signal delay monitor is to determine whether the signal is received within an expected reception window defining a time period in which receipt of the signal is expected, said signal representing data input, wherein the at least one signal delay monitor (112',120') comprises at least: a new data reception monitoring module including logic enabled by a system clock to compare a state of a data input in the physical interface to a previous state of the data input to determine if new data has been received at the physical interface, the said state of the data input being either a logical high or a logical low; and an expected reception window monitoring module including logic enabled by a window clock to determine if the state of the data input changes during the expected reception window, a new data reception monitoring module including logic enabled by a system clock to compare a state of a data input in the physical interface to a previous state of the data input to determine if new data has been received at the physical interface, the said state of the data input being either a logical high or a logical low; and an expected reception window monitoring module including logic enabled by a window clock to determine if the state of the data input changes during the expected reception window, wherein in indicating a potential attack the signal delay monitor (112',120') is to set a fault bit based on logic that performs a logical AND on an output of the new data reception monitoring module and on an output of the expected reception window monitoring module.