A semiconductor device, comprising: a first CMOS inverter including a first n-channel MOS transistor and a first p-channel MOS transistor connected in series at a first node; a second CMOS inverter including a second n-channel MOS transistor and a second p-channel MOS transistor connected in series at a second node, said second CMOS inverter forming a flip-flop circuit together with said first CMOS inverter; a first transfer transistor provided between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line, said first transfer transistor being activated by a selection signal on said word line; and a second transfer transistor provided between a second bit line (/BL) and said second node, said second transfer transistor having a second gate electrode connected to said word line, said second transfer transistor being activated by a selection signal on said word line, said first transfer transistor and said second transfer transistor being formed respectively in first (40B1) and second device regions (40B2) defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, said first transfer transistor contacting with said first bit line at a first bit contact region on said first device region, said second transfer transistor contacting with said second bit line at a second bit contact region on said second device region, characterized in that: said device isolation region is an STI type device isolation region, there is further provided a non-volatile memory on said semiconductor substrate, said first (40B1) and second (40B2) device regions have rounded corners when viewed in respective cross-sections, said first bit contact region is formed in said first device region (40B1) such that a center of said first bit contact region is offset toward said second device region (40B2), and wherein said second bit contact region is formed in said second device region and such that a center of said second bit contact region is offset toward said first device region (40B1). a first CMOS inverter including a first n-channel MOS transistor and a first p-channel MOS transistor connected in series at a first node; a second CMOS inverter including a second n-channel MOS transistor and a second p-channel MOS transistor connected in series at a second node, said second CMOS inverter forming a flip-flop circuit together with said first CMOS inverter; a first transfer transistor provided between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line, said first transfer transistor being activated by a selection signal on said word line; and a second transfer transistor provided between a second bit line (/BL) and said second node, said second transfer transistor having a second gate electrode connected to said word line, said second transfer transistor being activated by a selection signal on said word line, said first transfer transistor and said second transfer transistor being formed respectively in first (40B1) and second device regions (40B2) defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, said first transfer transistor contacting with said first bit line at a first bit contact region on said first device region, said second transfer transistor contacting with said second bit line at a second bit contact region on said second device region, said device isolation region is an STI type device isolation region, there is further provided a non-volatile memory on said semiconductor substrate, said first (40B1) and second (40B2) device regions have rounded corners when viewed in respective cross-sections, said first bit contact region is formed in said first device region (40B1) such that a center of said first bit contact region is offset toward said second device region (40B2), and wherein said second bit contact region is formed in said second device region and such that a center of said second bit contact region is offset toward said first device region (40B1).