An apparatus, comprising: a first pair of switching devices configured to selectively couple an application processor to Universal Serial Bus, USB, differential data transmission lines (DN/DP); a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer (316, 400) including differential terminals coupled to the USB differential data transmission lines, respectively, characterized in that the equalizer comprises: a first current source (410-N); a first field effect transistor, FET, coupled in series with the first current source between a first voltage rail and a negative one of the USB differential data transmission lines, wherein the first FET includes a first gate coupled to a positive one of the USB differential data transmission lines; a second current source (410-P); a second FET coupled in series with the second current source between the first voltage rail and the positive one of the USB differential data transmission lines, wherein the second FET includes a second gate coupled to the negative one of the USB differential data transmission lines; and a capacitor (Ceq) coupled between a first node between the first current source and the first FET, and a second node between the second current source and the second FET. a first pair of switching devices configured to selectively couple an application processor to Universal Serial Bus, USB, differential data transmission lines (DN/DP); a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer (316, 400) including differential terminals coupled to the USB differential data transmission lines, respectively, characterized in that the equalizer comprises: a first current source (410-N); a first field effect transistor, FET, coupled in series with the first current source between a first voltage rail and a negative one of the USB differential data transmission lines, wherein the first FET includes a first gate coupled to a positive one of the USB differential data transmission lines; a second current source (410-P); a second FET coupled in series with the second current source between the first voltage rail and the positive one of the USB differential data transmission lines, wherein the second FET includes a second gate coupled to the negative one of the USB differential data transmission lines; and a capacitor (Ceq) coupled between a first node between the first current source and the first FET, and a second node between the second current source and the second FET. a first current source (410-N); a first field effect transistor, FET, coupled in series with the first current source between a first voltage rail and a negative one of the USB differential data transmission lines, wherein the first FET includes a first gate coupled to a positive one of the USB differential data transmission lines; a second current source (410-P); a second FET coupled in series with the second current source between the first voltage rail and the positive one of the USB differential data transmission lines, wherein the second FET includes a second gate coupled to the negative one of the USB differential data transmission lines; and a capacitor (Ceq) coupled between a first node between the first current source and the first FET, and a second node between the second current source and the second FET.