An avalanche photodetector comprising: a silicon layer comprising a central region doped such that a first portion of the central region is in a n+ doping state and a second portion of the central region comprises a p-type-intrinsic-n-type, PIN, junction, the PIN junction embedded in the central region and comprising a p doping region, at least a portion of the first portion of the central region as an n+ doping region, and an intrinsic region disposed between the p doping region and the n+ doping region, the intrinsic region located from a first depth down to a second depth below a top surface of the silicon layer and the p doping region embedded from the top surface of the silicon layer down to the first depth, and the PIN junction functioning as a carrier multiplication region when under an avalanche effect induced by a reverse bias voltage; a germanium layer configured to absorb light and disposed on an opposite side of the p doping region as the intrinsic region such that the p doping region is disposed between the germanium layer and the intrinsic region, the germanium layer in an intrinsic state or doped such that the germanium layer is in a p doping state; and a plurality of electrode regions (104, 105, 201) configured to apply the reverse bias voltage across the PIN junction causing a photoelectric effect to convert light energy to electrical energy, the plurality of electrode regions (104, 105, 201) comprising a first electrode region disposed in the silicon layer and doped such that the first electrode region is in a n++ doping state, and a second electrode region disposed in the silicon layer and doped such that the second electrode region is in a n++ doping state, and a third electrode region disposed in the germanium layer and doped such that the third electrode region is in a p++ doping state, wherein the central region is between the first electrode region and the second electrode region, characterized in that the first and second electrode regions (104, 105) extend from the top surface of the silicon layer down to a depth less than the thickness of the silicon layer. a silicon layer comprising a central region doped such that a first portion of the central region is in a n+ doping state and a second portion of the central region comprises a p-type-intrinsic-n-type, PIN, junction, the PIN junction embedded in the central region and comprising a p doping region, at least a portion of the first portion of the central region as an n+ doping region, and an intrinsic region disposed between the p doping region and the n+ doping region, the intrinsic region located from a first depth down to a second depth below a top surface of the silicon layer and the p doping region embedded from the top surface of the silicon layer down to the first depth, and the PIN junction functioning as a carrier multiplication region when under an avalanche effect induced by a reverse bias voltage; a germanium layer configured to absorb light and disposed on an opposite side of the p doping region as the intrinsic region such that the p doping region is disposed between the germanium layer and the intrinsic region, the germanium layer in an intrinsic state or doped such that the germanium layer is in a p doping state; and a plurality of electrode regions (104, 105, 201) configured to apply the reverse bias voltage across the PIN junction causing a photoelectric effect to convert light energy to electrical energy, the plurality of electrode regions (104, 105, 201) comprising a first electrode region disposed in the silicon layer and doped such that the first electrode region is in a n++ doping state, and a second electrode region disposed in the silicon layer and doped such that the second electrode region is in a n++ doping state, and a third electrode region disposed in the germanium layer and doped such that the third electrode region is in a p++ doping state, wherein the central region is between the first electrode region and the second electrode region, characterized in that the first and second electrode regions (104, 105) extend from the top surface of the silicon layer down to a depth less than the thickness of the silicon layer.