An apparatus comprising: a first count stage (81, 101) comprising: a ferroelectric capacitor (21, 42) having first and second polarization states; a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal, said ferroelectric capacitor being connected between said control terminal and said first switch terminal; a reset port configured to connect a reset signal to said control terminal, said reset signal causing said ferroelectric capacitor to be polarized in said first polarization state; a count port configured to receive pulses to be counted, said count port being connected to said first switch terminal by a conductive load; and a detector that generates a count complete signal if a potential on said first switch terminal exceeds a threshold value while said count port is receiving one of said pulses, characterised in that: said first count stage comprises a delay circuit that couples said count complete signal of said first count stage to said reset port of said first count stage after a predetermined time delay, and wherein said apparatus further comprises a second count stage (82, 102), said second count stage comprising: a ferroelectric capacitor (21, 41) having first and second polarization states; a variable impedance element having an impedance between third and fourth switch terminals that is determined by a signal on a further control terminal, said ferroelectric capacitor of the second count stage being connected between said further control terminal and said third switch terminal; a reset port configured to connect a reset signal to said further control terminal, said reset signal causing said ferroelectric capacitor of the second count stage to be polarized in said first polarization state; a count port configured to receive pulses to be counted, said count port being connected to said third switch terminal by a further conductive load; a detector that generates a count complete signal if a potential on said third switch terminal exceeds a threshold value while said count port of the second count stage is receiving one of said pulses, wherein said count complete signal of said first count stage is coupled to said count port of said second count stage. a ferroelectric capacitor (21, 42) having first and second polarization states; a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal, said ferroelectric capacitor being connected between said control terminal and said first switch terminal; a reset port configured to connect a reset signal to said control terminal, said reset signal causing said ferroelectric capacitor to be polarized in said first polarization state; a count port configured to receive pulses to be counted, said count port being connected to said first switch terminal by a conductive load; and a detector that generates a count complete signal if a potential on said first switch terminal exceeds a threshold value while said count port is receiving one of said pulses, characterised in that: said first count stage comprises a delay circuit that couples said count complete signal of said first count stage to said reset port of said first count stage after a predetermined time delay, and wherein said apparatus further comprises a second count stage (82, 102), said second count stage comprising: a ferroelectric capacitor (21, 41) having first and second polarization states; a variable impedance element having an impedance between third and fourth switch terminals that is determined by a signal on a further control terminal, said ferroelectric capacitor of the second count stage being connected between said further control terminal and said third switch terminal; a reset port configured to connect a reset signal to said further control terminal, said reset signal causing said ferroelectric capacitor of the second count stage to be polarized in said first polarization state; a count port configured to receive pulses to be counted, said count port being connected to said third switch terminal by a further conductive load; a detector that generates a count complete signal if a potential on said third switch terminal exceeds a threshold value while said count port of the second count stage is receiving one of said pulses, wherein said count complete signal of said first count stage is coupled to said count port of said second count stage. a ferroelectric capacitor (21, 41) having first and second polarization states; a variable impedance element having an impedance between third and fourth switch terminals that is determined by a signal on a further control terminal, said ferroelectric capacitor of the second count stage being connected between said further control terminal and said third switch terminal; a reset port configured to connect a reset signal to said further control terminal, said reset signal causing said ferroelectric capacitor of the second count stage to be polarized in said first polarization state; a count port configured to receive pulses to be counted, said count port being connected to said third switch terminal by a further conductive load; a detector that generates a count complete signal if a potential on said third switch terminal exceeds a threshold value while said count port of the second count stage is receiving one of said pulses, wherein said count complete signal of said first count stage is coupled to said count port of said second count stage.