An apparatus, comprising: a memory array; a first cache; a second cache; and a controller coupled with the memory array and configured to cause the apparatus to: receive a read command comprising a logical address of the memory array of data requested by the read command; determine whether the logical address is absent from the first cache, the first cache comprising mappings between a first set of logical addresses and of a first set of physical addresses of the memory array; identify a descriptor associated with the logical address and that is stored in the second cache based at least in part on determining that the logical address is absent from the first cache, the second cache comprising one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array, wherein each descriptor includes a starting logical address of the second set of logical addresses, a starting physical address of the second set of physical addresses, and a length indicating a quantity of logical addresses associated with the descriptor; and retrieve the data from the memory array based at least in part on the descriptor stored in the second cache. a memory array; a first cache; a second cache; and a controller coupled with the memory array and configured to cause the apparatus to: receive a read command comprising a logical address of the memory array of data requested by the read command; determine whether the logical address is absent from the first cache, the first cache comprising mappings between a first set of logical addresses and of a first set of physical addresses of the memory array; identify a descriptor associated with the logical address and that is stored in the second cache based at least in part on determining that the logical address is absent from the first cache, the second cache comprising one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array, wherein each descriptor includes a starting logical address of the second set of logical addresses, a starting physical address of the second set of physical addresses, and a length indicating a quantity of logical addresses associated with the descriptor; and retrieve the data from the memory array based at least in part on the descriptor stored in the second cache. receive a read command comprising a logical address of the memory array of data requested by the read command; determine whether the logical address is absent from the first cache, the first cache comprising mappings between a first set of logical addresses and of a first set of physical addresses of the memory array; identify a descriptor associated with the logical address and that is stored in the second cache based at least in part on determining that the logical address is absent from the first cache, the second cache comprising one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array, wherein each descriptor includes a starting logical address of the second set of logical addresses, a starting physical address of the second set of physical addresses, and a length indicating a quantity of logical addresses associated with the descriptor; and retrieve the data from the memory array based at least in part on the descriptor stored in the second cache.