A semiconductor device having a voltage generation circuit, wherein the voltage generation circuit comprises: a reference voltage generation circuit which outputs a first reference voltage (VBGR); and a plurality of correction circuits (20-1, 20-2, 20-n) which generate correction current (Icomp) and feed back the correction current (Icomp) to the reference voltage generation circuit, wherein each of the correction circuits (20-1, 20-2, 20-n) generates a sub correction current (Icompi) on the basis of a respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) that is also output by the reference voltage generation circuit, wherein the sub correction current (Icompi) monotonously increases with increasing temperature from a predetermined temperature (T2a, T2b, T2c), wherein the predetermined temperature (T2a, T2b, T2c) varies among the correction circuits (20-1, 20-2, 20-n), wherein the correction current (Icomp) is sum of a plurality of the sub correction currents (Icompi) generated by the correction circuits (20-1, 20-2, 20-n), wherein each of the correction circuits (20-1, 20-2, 20-n) generates the sub correction current (Icompi) on the basis of the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) and a forward voltage of a P-N junction or a current corresponding to the forward voltage, wherein each of the correction circuits (20-1, 20-2, 20-n) comprises: a first PMOS transistor whose source is coupled to a first power supply and whose drain is coupled to its gate; a second PMOS transistor whose source is coupled to the first power supply and whose gate is coupled to the gate of the first PMOS transistor; a bipolar transistor whose collector is coupled to the drain of the first PMOS transistor and having a base to which the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) is coupled; and a resistor whose one end is coupled to an emitter of the bipolar transistor and whose other end is coupled to a second power supply, wherein the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) is obtained by dividing the first reference voltage (VBGR) by a resistor and varies among the correction circuits (20-1, 20-2, 20-n), and wherein the second PMOS transistor outputs the sub correction current (Icompi) from the drain. a reference voltage generation circuit which outputs a first reference voltage (VBGR); and a plurality of correction circuits (20-1, 20-2, 20-n) which generate correction current (Icomp) and feed back the correction current (Icomp) to the reference voltage generation circuit, wherein each of the correction circuits (20-1, 20-2, 20-n) generates a sub correction current (Icompi) on the basis of a respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) that is also output by the reference voltage generation circuit, wherein the sub correction current (Icompi) monotonously increases with increasing temperature from a predetermined temperature (T2a, T2b, T2c), wherein the predetermined temperature (T2a, T2b, T2c) varies among the correction circuits (20-1, 20-2, 20-n), wherein the correction current (Icomp) is sum of a plurality of the sub correction currents (Icompi) generated by the correction circuits (20-1, 20-2, 20-n), wherein each of the correction circuits (20-1, 20-2, 20-n) generates the sub correction current (Icompi) on the basis of the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) and a forward voltage of a P-N junction or a current corresponding to the forward voltage, wherein each of the correction circuits (20-1, 20-2, 20-n) comprises: a first PMOS transistor whose source is coupled to a first power supply and whose drain is coupled to its gate; a second PMOS transistor whose source is coupled to the first power supply and whose gate is coupled to the gate of the first PMOS transistor; a bipolar transistor whose collector is coupled to the drain of the first PMOS transistor and having a base to which the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) is coupled; and a resistor whose one end is coupled to an emitter of the bipolar transistor and whose other end is coupled to a second power supply, wherein the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) is obtained by dividing the first reference voltage (VBGR) by a resistor and varies among the correction circuits (20-1, 20-2, 20-n), and wherein the second PMOS transistor outputs the sub correction current (Icompi) from the drain. a first PMOS transistor whose source is coupled to a first power supply and whose drain is coupled to its gate; a second PMOS transistor whose source is coupled to the first power supply and whose gate is coupled to the gate of the first PMOS transistor; a bipolar transistor whose collector is coupled to the drain of the first PMOS transistor and having a base to which the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) is coupled; and a resistor whose one end is coupled to an emitter of the bipolar transistor and whose other end is coupled to a second power supply, wherein the respective voltage (VBGRC1 - VBGRCn) proportional to the first reference voltage (VBGR) is obtained by dividing the first reference voltage (VBGR) by a resistor and varies among the correction circuits (20-1, 20-2, 20-n), and wherein the second PMOS transistor outputs the sub correction current (Icompi) from the drain.