An insulating gate field effect transistor (TGFET) device comprising: a silicon carbide containing semiconductor body conductively coupled with a source contact and a drain contact, the semiconductor body including a first well region comprising a first volume of the semiconductor body that is disposed at a first side of the semiconductor body and that is doped with a first type of dopant, the semiconductor body including a second well region comprising a second volume of the semiconductor body that is disposed at the first side of the semiconductor body and that is doped with an oppositely charged second type of dopant, the second well region disposed within the first well region; and a gate oxide coupled with the semiconductor body and with a gate contact, the gate oxide including an outer section (244,248) and an interior section having different thickness dimensions, the outer section disposed over the first well region, the second well region, and a doped surface region of the semiconductor body, the interior section disposed over, and confined to an area over, a junction gate field effect transistor region of the semiconductor body, wherein the semiconductor body is configured to form a conductive channel from the source contact to the drain contact through the second well region and the junction gate field effect transistor region when a gate signal is applied to the gate contact; wherein the outer section (244,248) of the gate oxide has a smaller thickness dimension than the interior section of the gate oxide, characterized in that the interior section of the gate oxide has a thickness that is at least five times greater than a thickness of the outer section (244, 248) of the gate oxide, wherein the outer section (244, 248) of the gate oxide extends from first and second ends (236, 238) of the gate oxide to the interior section of the gate oxide. a silicon carbide containing semiconductor body conductively coupled with a source contact and a drain contact, the semiconductor body including a first well region comprising a first volume of the semiconductor body that is disposed at a first side of the semiconductor body and that is doped with a first type of dopant, the semiconductor body including a second well region comprising a second volume of the semiconductor body that is disposed at the first side of the semiconductor body and that is doped with an oppositely charged second type of dopant, the second well region disposed within the first well region; and a gate oxide coupled with the semiconductor body and with a gate contact, the gate oxide including an outer section (244,248) and an interior section having different thickness dimensions, the outer section disposed over the first well region, the second well region, and a doped surface region of the semiconductor body, the interior section disposed over, and confined to an area over, a junction gate field effect transistor region of the semiconductor body, wherein the semiconductor body is configured to form a conductive channel from the source contact to the drain contact through the second well region and the junction gate field effect transistor region when a gate signal is applied to the gate contact; wherein the outer section (244,248) of the gate oxide has a smaller thickness dimension than the interior section of the gate oxide, characterized in that the interior section of the gate oxide has a thickness that is at least five times greater than a thickness of the outer section (244, 248) of the gate oxide, wherein the outer section (244, 248) of the gate oxide extends from first and second ends (236, 238) of the gate oxide to the interior section of the gate oxide.