A charge pump circuit comprising: a first transistor including a first terminal, a second terminal connected to an output terminal, and a control terminal; a second transistor including a first terminal, a second terminal to which a constant current is supplied, and a control terminal connected to the second terminal; a third transistor including a first terminal connected to the first terminal of the first transistor, a second terminal connected to a voltage source that supplies an arbitrary voltage, and a control terminal; a fourth transistor group (Tr14-1, Tr14-2, Tr14-N) including N transistors (Tr14-1, Tr14-2, Tr14-N) arranged in a cascade on a first terminal side of the first transistor, where N is an integer greater than or equal to 1, the N transistors (Tr14-1, Tr14-2, Tr14-N) all including control terminals connected to the control terminal of the second transistor; a fifth transistor group (Tr15-1, Tr15-2, Tr15-N) including N transistors (Tr15-1, Tr15-2, Tr15-N) arranged in a cascade on a first terminal side of the second transistor, the N transistors (Tr15-1, Tr15-2, Tr15-N) all including control terminals connected to the control terminal of the second transistor; a first switch element that electrically connects the control terminal of the first transistor to the control terminal of the second transistor; a second switch element that connects the control terminal of the first transistor to a ground node; a third switch element that electrically connects the control terminal of the third transistor to the control terminals of the fourth transistor group (Tr14-1, Tr14-2, Tr14-N) and the fifth transistor group (Tr15-1, Tr15-2, Tr15-N); and a fourth switch element that connects the control terminal of the third transistor to the ground node, wherein the first transistor has a channel width and a channel length identical to those of the second transistor, the third transistor has the channel width and the channel length identical to those of the first transistor and the second transistor, in the fourth transistor group (Tr14-1, Tr14-2, Tr14-N), each of the transistors (Tr14-1, Tr14-2, Tr14-N) has the channel width and the channel length identical to those of the second transistor, and a first terminal of one of the transistors (Tr14-1, Tr14-2, Tr14-N) is connected to the ground node, and in the fifth transistor group (Tr15-1, Tr15-2, Tr15-N), each of the transistors (Tr15-1, Tr15-2, Tr15-N) has the channel width and the channel length identical to those of the second transistor, and a first terminal of one of the transistors (Tr15-1, Tr15-2, Tr15-N) is connected to the ground node. a first transistor including a first terminal, a second terminal connected to an output terminal, and a control terminal; a second transistor including a first terminal, a second terminal to which a constant current is supplied, and a control terminal connected to the second terminal; a third transistor including a first terminal connected to the first terminal of the first transistor, a second terminal connected to a voltage source that supplies an arbitrary voltage, and a control terminal; a fourth transistor group (Tr14-1, Tr14-2, Tr14-N) including N transistors (Tr14-1, Tr14-2, Tr14-N) arranged in a cascade on a first terminal side of the first transistor, where N is an integer greater than or equal to 1, the N transistors (Tr14-1, Tr14-2, Tr14-N) all including control terminals connected to the control terminal of the second transistor; a fifth transistor group (Tr15-1, Tr15-2, Tr15-N) including N transistors (Tr15-1, Tr15-2, Tr15-N) arranged in a cascade on a first terminal side of the second transistor, the N transistors (Tr15-1, Tr15-2, Tr15-N) all including control terminals connected to the control terminal of the second transistor; a first switch element that electrically connects the control terminal of the first transistor to the control terminal of the second transistor; a second switch element that connects the control terminal of the first transistor to a ground node; a third switch element that electrically connects the control terminal of the third transistor to the control terminals of the fourth transistor group (Tr14-1, Tr14-2, Tr14-N) and the fifth transistor group (Tr15-1, Tr15-2, Tr15-N); and a fourth switch element that connects the control terminal of the third transistor to the ground node, wherein the first transistor has a channel width and a channel length identical to those of the second transistor, the third transistor has the channel width and the channel length identical to those of the first transistor and the second transistor, in the fourth transistor group (Tr14-1, Tr14-2, Tr14-N), each of the transistors (Tr14-1, Tr14-2, Tr14-N) has the channel width and the channel length identical to those of the second transistor, and a first terminal of one of the transistors (Tr14-1, Tr14-2, Tr14-N) is connected to the ground node, and in the fifth transistor group (Tr15-1, Tr15-2, Tr15-N), each of the transistors (Tr15-1, Tr15-2, Tr15-N) has the channel width and the channel length identical to those of the second transistor, and a first terminal of one of the transistors (Tr15-1, Tr15-2, Tr15-N) is connected to the ground node.