A level shift circuit that transmits an input signal from a primary side voltage system to a system operating on a secondary side voltage system (2, 2-1, 2-2) differing from the primary side voltage system, the level shift circuit (2, 2-1, 2-2) being characterized by comprising: a series circuit of a first resistor (LSR1, LSR1a) and first switching element connected between a high voltage side power source voltage of the secondary side voltage system (2, 2-1, 2-2) and a low voltage side power source voltage of the primary side voltage system; a series circuit of a second resistor (LSR2, LSR2a) and second switching element connected between the high voltage side power source voltage of the secondary side voltage system (2, 2-1, 2-2) and the low voltage side power source voltage of the primary side voltage system; a latch malfunction protection circuit, operating on the secondary side voltage system (2, 2-1, 2-2), into which is input the voltage of a first connection point, which is a connection point of the first resistor (LSR1, LSR1a) and first switching element, and into which is input the voltage of a second connection point, which is a connection point of the second resistor (LSR2, LSR2a) and second switching element; a latch circuit, operating on the secondary side voltage system (2, 2-1, 2-2), into which is input the output of the latch malfunction protection circuit; a third switching element (PM1a) connected in parallel to the first resistor (LSR1, LSR1a); a fourth switching element (PM2a) connected in parallel to the second resistor (LSR2, LSR2a); and a logic gate circuit, operating on the secondary side voltage system (2, 2-1, 2-2), into which are input the voltages of the first and second connection points (P1, P2), wherein a signal of the primary side voltage system that controls the turning on and off of the first switching element is input into the first switching element, and a signal of the primary side voltage system that controls the turning on and off of the second switching element is input into the second switching element, the latch malfunction protection circuit is configured so as to transmit a signal determined based on the voltages of the first and second connection points (P1, P2) to the latch circuit when either one of the first and second switching elements (HVN1, HVN2) is turned on, and so as not to transmit a signal determined based on the voltages of the first and second connection points (P1, P2) to the latch circuit when the first and second switching elements (HVN1, HVN2) are turned on simultaneously, and the logic gate circuit causes the third and fourth switching elements (PM1a, PM2a) to be turned on when the voltages of the first and second connection points (P1, P2) are both lower than the threshold value of the logic gate circuit. a series circuit of a first resistor (LSR1, LSR1a) and first switching element connected between a high voltage side power source voltage of the secondary side voltage system (2, 2-1, 2-2) and a low voltage side power source voltage of the primary side voltage system; a series circuit of a second resistor (LSR2, LSR2a) and second switching element connected between the high voltage side power source voltage of the secondary side voltage system (2, 2-1, 2-2) and the low voltage side power source voltage of the primary side voltage system; a latch malfunction protection circuit, operating on the secondary side voltage system (2, 2-1, 2-2), into which is input the voltage of a first connection point, which is a connection point of the first resistor (LSR1, LSR1a) and first switching element, and into which is input the voltage of a second connection point, which is a connection point of the second resistor (LSR2, LSR2a) and second switching element; a latch circuit, operating on the secondary side voltage system (2, 2-1, 2-2), into which is input the output of the latch malfunction protection circuit; a third switching element (PM1a) connected in parallel to the first resistor (LSR1, LSR1a); a fourth switching element (PM2a) connected in parallel to the second resistor (LSR2, LSR2a); and a logic gate circuit, operating on the secondary side voltage system (2, 2-1, 2-2), into which are input the voltages of the first and second connection points (P1, P2), wherein a signal of the primary side voltage system that controls the turning on and off of the first switching element is input into the first switching element, and a signal of the primary side voltage system that controls the turning on and off of the second switching element is input into the second switching element, the latch malfunction protection circuit is configured so as to transmit a signal determined based on the voltages of the first and second connection points (P1, P2) to the latch circuit when either one of the first and second switching elements (HVN1, HVN2) is turned on, and so as not to transmit a signal determined based on the voltages of the first and second connection points (P1, P2) to the latch circuit when the first and second switching elements (HVN1, HVN2) are turned on simultaneously, and the logic gate circuit causes the third and fourth switching elements (PM1a, PM2a) to be turned on when the voltages of the first and second connection points (P1, P2) are both lower than the threshold value of the logic gate circuit.