An apparatus comprising: a processor (10A, 10B); and a timer unit (12, 12A, 12B), wherein the timer unit (12, 12A, 12B) is coupled to the processor (10A, 10B) and is configured to time a selected time interval and, in response to the expiration of the current selected time interval, pulse a signal and begin timing a next iteration of the selected time interval, wherein the timer unit (12, 12A, 12B) is programmable with the selected time interval and wherein the timer unit (12, 12A, 12B) is initialized to the selected time interval during an initialization of the apparatus, wherein the processor (10, 10A, 10B) is coupled to receive the signal from the timer unit (12, 12A, 12B) and is configured to execute code that attempts to acquire a lock, the code including a first instruction that is defined in an instruction set architecture implemented by the processor (10A, 10B), wherein the first instruction is defined to cause the processor (10A, 10B) to enter a low power state, in which less power is consumed than in a normal operating state of the processor (10A, 10B), for a thread that includes the first instruction, wherein the processor (10A, 10B) is executing the thread when the first instruction is executed, and wherein the processor (10A, 10B) is configured to exit the low power state for the thread responsive to the pulse on the signal from the timer unit (12, 12A, 12B) and to continue execution with an instruction that follows the first instruction in the code, and wherein the thread causes the processor (10A, 10B) to iteratively: attempt to acquire the lock and, responsive to failing to acquire the lock, execute the first instruction to enter the low power state until the next pulse is received on the signal from the timer unit (12, 12A, 12B), wherein the typical time for which it is expected that a thread will hold the lock once the lock has been acquired by the thread is approximately the selected time interval multiplied by a maximum number of iterations of attempting to acquire the lock, failing, and executing the first instructions prior to blocking the thread; and the processor is further configured to: determine that an additional iteration is not permitted because the maximum number of iterations has been reached; and responsive to determining that the additional iteration is not permitted, block the thread. a processor (10A, 10B); and a timer unit (12, 12A, 12B), wherein the timer unit (12, 12A, 12B) is coupled to the processor (10A, 10B) and is configured to time a selected time interval and, in response to the expiration of the current selected time interval, pulse a signal and begin timing a next iteration of the selected time interval, wherein the timer unit (12, 12A, 12B) is programmable with the selected time interval and wherein the timer unit (12, 12A, 12B) is initialized to the selected time interval during an initialization of the apparatus, wherein the processor (10, 10A, 10B) is coupled to receive the signal from the timer unit (12, 12A, 12B) and is configured to execute code that attempts to acquire a lock, the code including a first instruction that is defined in an instruction set architecture implemented by the processor (10A, 10B), wherein the first instruction is defined to cause the processor (10A, 10B) to enter a low power state, in which less power is consumed than in a normal operating state of the processor (10A, 10B), for a thread that includes the first instruction, wherein the processor (10A, 10B) is executing the thread when the first instruction is executed, and wherein the processor (10A, 10B) is configured to exit the low power state for the thread responsive to the pulse on the signal from the timer unit (12, 12A, 12B) and to continue execution with an instruction that follows the first instruction in the code, and wherein the thread causes the processor (10A, 10B) to iteratively: attempt to acquire the lock and, responsive to failing to acquire the lock, execute the first instruction to enter the low power state until the next pulse is received on the signal from the timer unit (12, 12A, 12B), wherein the typical time for which it is expected that a thread will hold the lock once the lock has been acquired by the thread is approximately the selected time interval multiplied by a maximum number of iterations of attempting to acquire the lock, failing, and executing the first instructions prior to blocking the thread; and the processor is further configured to: determine that an additional iteration is not permitted because the maximum number of iterations has been reached; and responsive to determining that the additional iteration is not permitted, block the thread. determine that an additional iteration is not permitted because the maximum number of iterations has been reached; and responsive to determining that the additional iteration is not permitted, block the thread.