A memory device comprising: a plurality of rows of memory cells (112, 114), wherein a first row of the plurality of rows comprises a first segment and a second segment, the first segment comprises a first subset of the memory cells of the first row and the second segment comprises a second subset of the memory cells of the first row, wherein the first row is configured to store a numeric sequence, wherein the memory cells of the first subset are configured to store a first portion of the numeric sequence and the memory cells of the second subset are configured to store a second portion of the numeric sequence; a first match line coupled to the memory cells of the first subset and a second match line coupled to the memory cells of the second subset; a first pre-charge circuit configured to pre-charge the first match line to a first pre-charge voltage and a second pre-charge circuit configured to pre-charge the second match line to a second pre-charge voltage different from the first pre-charge voltage; a first input circuit configured to provide the first portion of the input numeric sequence to the first segment of the first row; and a second input circuit configured to provide the second portion of the input numeric sequence to the second segment of the first row, wherein: the memory device is a content addressable memory, CAM, and each of the plurality of rows further comprises a plurality of comparators, each comparator being coupled to a corresponding memory cell, and the second segment of the first row is configured to compare the second portion of the input numeric sequence to the second portion of the numeric sequence if the first portion of the input numeric sequence matches the first portion of the numeric sequence, and the second segment of the first row is configured not to compare the second portion of the input numeric sequence to the second portion of the numeric sequence if the first portion of the input numeric sequence does not match the first portion of the numeric sequence. a plurality of rows of memory cells (112, 114), wherein a first row of the plurality of rows comprises a first segment and a second segment, the first segment comprises a first subset of the memory cells of the first row and the second segment comprises a second subset of the memory cells of the first row, wherein the first row is configured to store a numeric sequence, wherein the memory cells of the first subset are configured to store a first portion of the numeric sequence and the memory cells of the second subset are configured to store a second portion of the numeric sequence; a first match line coupled to the memory cells of the first subset and a second match line coupled to the memory cells of the second subset; a first pre-charge circuit configured to pre-charge the first match line to a first pre-charge voltage and a second pre-charge circuit configured to pre-charge the second match line to a second pre-charge voltage different from the first pre-charge voltage; a first input circuit configured to provide the first portion of the input numeric sequence to the first segment of the first row; and a second input circuit configured to provide the second portion of the input numeric sequence to the second segment of the first row, wherein: the memory device is a content addressable memory, CAM, and each of the plurality of rows further comprises a plurality of comparators, each comparator being coupled to a corresponding memory cell, and the second segment of the first row is configured to compare the second portion of the input numeric sequence to the second portion of the numeric sequence if the first portion of the input numeric sequence matches the first portion of the numeric sequence, and the second segment of the first row is configured not to compare the second portion of the input numeric sequence to the second portion of the numeric sequence if the first portion of the input numeric sequence does not match the first portion of the numeric sequence. the memory device is a content addressable memory, CAM, and each of the plurality of rows further comprises a plurality of comparators, each comparator being coupled to a corresponding memory cell, and the second segment of the first row is configured to compare the second portion of the input numeric sequence to the second portion of the numeric sequence if the first portion of the input numeric sequence matches the first portion of the numeric sequence, and the second segment of the first row is configured not to compare the second portion of the input numeric sequence to the second portion of the numeric sequence if the first portion of the input numeric sequence does not match the first portion of the numeric sequence.