A semiconductor device comprising: a match line; a plurality of TCAM cells coupled to the match line and a pair of search lines (ST, SB); an output circuit coupled to the match line; and a match line drawing amplification circuit coupled to the match line and for drawing the potential of the match line, wherein the plurality of TCAM cells is arranged between the match line drawing amplification circuit and the output circuit, and wherein each of the TCAM cells is made of two SRAM cells, wherein the match line drawing amplification circuit comprises: a first P-channel MOS transistor whose gate is coupled to the match line, whose source is supplied with a first reference potential (Vcc), and whose drain is coupled to a common coupling node; a first N-channel MOS transistor whose gate is coupled to the match line, and whose drain is coupled to the common coupling node; a second N-channel MOS transistor whose source is supplied with a second reference potential (Vss) lower than the first reference potential (Vcc), and whose drain is coupled to the source of the first N-channel MOS transistor; a second P-channel MOS transistor whose gate is coupled to the common coupling node, whose source is supplied with the first reference potential (Vcc), and whose drain is coupled to the match line; a third N-channel MOS transistor whose gate is coupled to the common coupling node, and whose drain is coupled to the match line; and a fourth N-channel MOS transistor whose source is supplied with the second reference potential (Vss), and whose drain is coupled to the source of the third N-channel MOS transistor. a match line; a plurality of TCAM cells coupled to the match line and a pair of search lines (ST, SB); an output circuit coupled to the match line; and a match line drawing amplification circuit coupled to the match line and for drawing the potential of the match line, wherein the plurality of TCAM cells is arranged between the match line drawing amplification circuit and the output circuit, and wherein each of the TCAM cells is made of two SRAM cells, wherein the match line drawing amplification circuit comprises: a first P-channel MOS transistor whose gate is coupled to the match line, whose source is supplied with a first reference potential (Vcc), and whose drain is coupled to a common coupling node; a first N-channel MOS transistor whose gate is coupled to the match line, and whose drain is coupled to the common coupling node; a second N-channel MOS transistor whose source is supplied with a second reference potential (Vss) lower than the first reference potential (Vcc), and whose drain is coupled to the source of the first N-channel MOS transistor; a second P-channel MOS transistor whose gate is coupled to the common coupling node, whose source is supplied with the first reference potential (Vcc), and whose drain is coupled to the match line; a third N-channel MOS transistor whose gate is coupled to the common coupling node, and whose drain is coupled to the match line; and a fourth N-channel MOS transistor whose source is supplied with the second reference potential (Vss), and whose drain is coupled to the source of the third N-channel MOS transistor. a first P-channel MOS transistor whose gate is coupled to the match line, whose source is supplied with a first reference potential (Vcc), and whose drain is coupled to a common coupling node; a first N-channel MOS transistor whose gate is coupled to the match line, and whose drain is coupled to the common coupling node; a second N-channel MOS transistor whose source is supplied with a second reference potential (Vss) lower than the first reference potential (Vcc), and whose drain is coupled to the source of the first N-channel MOS transistor; a second P-channel MOS transistor whose gate is coupled to the common coupling node, whose source is supplied with the first reference potential (Vcc), and whose drain is coupled to the match line; a third N-channel MOS transistor whose gate is coupled to the common coupling node, and whose drain is coupled to the match line; and a fourth N-channel MOS transistor whose source is supplied with the second reference potential (Vss), and whose drain is coupled to the source of the third N-channel MOS transistor.