A method of translating a high-level language code into a HDL code, comprising the steps of: marking a translation-targeted section of a high-level language code using a programming directive; partitioning the high-level language code into a hardware code part and a software code part; compiling the software code part and the hardware code part together by means of a main compiler; characterized in that the hardware code part comprises the marked translation-targeted section as a sub-routine, and the software code part comprises the high-level language code with the marked translation-targeted section replaced by a wrapper for calling the subroutine; the software code part and the hardware code part are compiled together into a low-level intermediate representation code of the main compiler immediately before generation of a target assembly code in order to preserve a standard call linkage convention of a main core; and the method further comprising the steps of: translating the low-level intermediate representation code corresponding to the hardware code part into a HDL code by means of a HDL backend of a HLL-to-HDL (high-level language to hardware description language) translator, translating the low-level intermediate representation code corresponding to the software code part into target executable code; and executing the target executable code corresponding to the software code part in the main core and executing the HDL code in a dedicated hardware which is a FPGA, after synthesizing the HDL code. marking a translation-targeted section of a high-level language code using a programming directive; partitioning the high-level language code into a hardware code part and a software code part; compiling the software code part and the hardware code part together by means of a main compiler; characterized in that the hardware code part comprises the marked translation-targeted section as a sub-routine, and the software code part comprises the high-level language code with the marked translation-targeted section replaced by a wrapper for calling the subroutine; the software code part and the hardware code part are compiled together into a low-level intermediate representation code of the main compiler immediately before generation of a target assembly code in order to preserve a standard call linkage convention of a main core; and the method further comprising the steps of: translating the low-level intermediate representation code corresponding to the hardware code part into a HDL code by means of a HDL backend of a HLL-to-HDL (high-level language to hardware description language) translator, translating the low-level intermediate representation code corresponding to the software code part into target executable code; and translating the low-level intermediate representation code corresponding to the hardware code part into a HDL code by means of a HDL backend of a HLL-to-HDL (high-level language to hardware description language) translator, translating the low-level intermediate representation code corresponding to the software code part into target executable code; and executing the target executable code corresponding to the software code part in the main core and executing the HDL code in a dedicated hardware which is a FPGA, after synthesizing the HDL code.