A microprocessor having a plurality of architectural condition flags and which performs an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the plurality of architectural condition flags satisfy a condition specified in the architectural instruction, the microprocessor comprising: a register, that includes storage for the plurality of architectural condition flags and also contains storage for a non-architectural indicator; a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the operation on the source operands to generate the result; determines whether the plurality of architectural condition flags satisfy the condition; and updates the non-architectural indicator to indicate whether the plurality of architectural condition flags satisfy the condition; wherein in response to the second microinstruction, the execution pipeline: if the non-architectural indicator updated by the first microinstruction indicates the plurality of architectural condition flags satisfy the condition, updates the destination register with the result; and if the non-architectural indicator updated by the first microinstruction indicates the plurality of architectural condition flags do not satisfy the condition, updates the destination register with the current value of the destination register. a register, that includes storage for the plurality of architectural condition flags and also contains storage for a non-architectural indicator; a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the operation on the source operands to generate the result; determines whether the plurality of architectural condition flags satisfy the condition; and updates the non-architectural indicator to indicate whether the plurality of architectural condition flags satisfy the condition; performs the operation on the source operands to generate the result; determines whether the plurality of architectural condition flags satisfy the condition; and updates the non-architectural indicator to indicate whether the plurality of architectural condition flags satisfy the condition; wherein in response to the second microinstruction, the execution pipeline: if the non-architectural indicator updated by the first microinstruction indicates the plurality of architectural condition flags satisfy the condition, updates the destination register with the result; and if the non-architectural indicator updated by the first microinstruction indicates the plurality of architectural condition flags do not satisfy the condition, updates the destination register with the current value of the destination register. if the non-architectural indicator updated by the first microinstruction indicates the plurality of architectural condition flags satisfy the condition, updates the destination register with the result; and if the non-architectural indicator updated by the first microinstruction indicates the plurality of architectural condition flags do not satisfy the condition, updates the destination register with the current value of the destination register.