A method for communicating between a security module, said security module being housed on a chip card, and a host device, said host device comprising a card reader (RDR_SL) for connecting to the security module via at least one communication line operating at a first frequency, said method comprising: operating the host device at a second frequency, said second frequency being lower than the first frequency, said operation generating a plurality of signals toward the card reader (RDR_SL), at least one of which having a third frequency, said third frequency being equal to or lower than the second frequency, the card reader (RDR_SL) receiving said plurality of signals; and converting, by the card reader (RDR_SL), at least one of the received signals, said conversion yielding at least the communication line operating at the first frequency, characterised in that: said received signals comprise two separate, suitably phased sub-clock signals (CK0, CK1) and at least two inputs for said security module (I0, I1); said conversion being: generating a clock signal for the security module by multiplexing said two separate, suitably phased sub-clock signals (CK0, CK1); multiplexing from said at least two inputs (10, I1) an input signal for input into the security module; and de-multiplexing an output signal from said security module to produce at least two separate outputs (00, O1). operating the host device at a second frequency, said second frequency being lower than the first frequency, said operation generating a plurality of signals toward the card reader (RDR_SL), at least one of which having a third frequency, said third frequency being equal to or lower than the second frequency, the card reader (RDR_SL) receiving said plurality of signals; and converting, by the card reader (RDR_SL), at least one of the received signals, said conversion yielding at least the communication line operating at the first frequency, characterised in that: said received signals comprise two separate, suitably phased sub-clock signals (CK0, CK1) and at least two inputs for said security module (I0, I1); said conversion being: generating a clock signal for the security module by multiplexing said two separate, suitably phased sub-clock signals (CK0, CK1); multiplexing from said at least two inputs (10, I1) an input signal for input into the security module; and de-multiplexing an output signal from said security module to produce at least two separate outputs (00, O1). said received signals comprise two separate, suitably phased sub-clock signals (CK0, CK1) and at least two inputs for said security module (I0, I1); said conversion being: generating a clock signal for the security module by multiplexing said two separate, suitably phased sub-clock signals (CK0, CK1); multiplexing from said at least two inputs (10, I1) an input signal for input into the security module; and de-multiplexing an output signal from said security module to produce at least two separate outputs (00, O1). generating a clock signal for the security module by multiplexing said two separate, suitably phased sub-clock signals (CK0, CK1); multiplexing from said at least two inputs (10, I1) an input signal for input into the security module; and de-multiplexing an output signal from said security module to produce at least two separate outputs (00, O1).