A semiconductor device, comprising: gate layers and insulating layers that are stacked alternatingly along a stack direction perpendicular to a substrate of the semiconductor device and form a stack upon the substrate; an array of channel structures being formed in an array region of the stack; a first staircase formed of a first section of the stack in a connection region upon the substrate; a second staircase formed of a second section of the stack in the connection region upon the substrate; and a dummy staircase formed of the first section of the stack and disposed between the first staircase and the second staircase in the connection region, wherein the stack of alternatingly disposed gate layers and the insulating layers is divided into sections, wherein each section of the stack is further divided into groups, wherein each group is then divided into divisions, wherein each division includes a layer pair, wherein the first staircase is formed of first group stair steps (G1 - G9) that go down in a first direction, and the second staircase is formed of second group stair steps (G1 - G9) that go down in the first direction, wherein the dummy staircase is formed of dummy group stair steps (G1 - G9) that go down in a second direction that is opposite to the first direction, wherein each stair step of the first group stair steps (G1 - G9) is formed of multiple first division stair steps (D1 - D6) and each stair step of the second group stair steps (G1 - G9) is formed of multiple second division stair steps (D1 - D6), wherein the multiple division stair steps (D1 - D6) go down in a third direction that is perpendicular to the first direction, wherein the directions that the staircases (270, 280, 290) go upirror go down are projections of the according directions into a plane (xy), which is perpendicular to the stack direction, wherein a sidewall of the dummy staircase to the second staircase has a same height as the first staircase, characterized in that the group stair steps (G1 - G9) have a height of multiple layer pairs and division stair steps (D1 - D6) have a height of one layer pair, wherein the height of a layer pair is a thickness sum of a gate layer and an insulating layer. gate layers and insulating layers that are stacked alternatingly along a stack direction perpendicular to a substrate of the semiconductor device and form a stack upon the substrate; an array of channel structures being formed in an array region of the stack; a first staircase formed of a first section of the stack in a connection region upon the substrate; a second staircase formed of a second section of the stack in the connection region upon the substrate; and a dummy staircase formed of the first section of the stack and disposed between the first staircase and the second staircase in the connection region, wherein the stack of alternatingly disposed gate layers and the insulating layers is divided into sections, wherein each section of the stack is further divided into groups, wherein each group is then divided into divisions, wherein each division includes a layer pair, wherein the first staircase is formed of first group stair steps (G1 - G9) that go down in a first direction, and the second staircase is formed of second group stair steps (G1 - G9) that go down in the first direction, wherein the dummy staircase is formed of dummy group stair steps (G1 - G9) that go down in a second direction that is opposite to the first direction, wherein each stair step of the first group stair steps (G1 - G9) is formed of multiple first division stair steps (D1 - D6) and each stair step of the second group stair steps (G1 - G9) is formed of multiple second division stair steps (D1 - D6), wherein the multiple division stair steps (D1 - D6) go down in a third direction that is perpendicular to the first direction, wherein the directions that the staircases (270, 280, 290) go upirror go down are projections of the according directions into a plane (xy), which is perpendicular to the stack direction, wherein a sidewall of the dummy staircase to the second staircase has a same height as the first staircase, characterized in that the group stair steps (G1 - G9) have a height of multiple layer pairs and division stair steps (D1 - D6) have a height of one layer pair, wherein the height of a layer pair is a thickness sum of a gate layer and an insulating layer.