A partial replay controller for controlling execution replay of an instruction block executed in a processor employing a block-atomic execution model in which instructions are grouped into instruction blocks in which either all instructions in the instruction block are committed or none of the instructions are committed, comprising: a detection circuit configured to set a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification or an occurrence of an exception in the processor during execution of the instruction block by the processor, wherein an instruction is associated with a potential architectural state modification if it modifies an architectural state in the processor and has an observable interaction with functions or processes outside of the instruction block; in response to the record/replay state being an active state for the instruction block, re-executing the instruction block by the processor; and a record/replay circuit configured to, during re-execution of the instruction block by the processor in response to the record/replay state being an active state for the instruction block: inspect an entry state in a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction; record produced data of the executed next load/store instruction in the record/replay log file, in response to the previously produced data not being recorded in the record/replay log file for the next load/store instruction; and execute the next load/store instruction using the previously produced data recorded for the next load/store instruction in the record/replay log file, in response to the previously produced data being recorded in the record/replay log file for the next load/store instruction. a detection circuit configured to set a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification or an occurrence of an exception in the processor during execution of the instruction block by the processor, wherein an instruction is associated with a potential architectural state modification if it modifies an architectural state in the processor and has an observable interaction with functions or processes outside of the instruction block; in response to the record/replay state being an active state for the instruction block, re-executing the instruction block by the processor; and a record/replay circuit configured to, during re-execution of the instruction block by the processor in response to the record/replay state being an active state for the instruction block: inspect an entry state in a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction; record produced data of the executed next load/store instruction in the record/replay log file, in response to the previously produced data not being recorded in the record/replay log file for the next load/store instruction; and execute the next load/store instruction using the previously produced data recorded for the next load/store instruction in the record/replay log file, in response to the previously produced data being recorded in the record/replay log file for the next load/store instruction. inspect an entry state in a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction; record produced data of the executed next load/store instruction in the record/replay log file, in response to the previously produced data not being recorded in the record/replay log file for the next load/store instruction; and execute the next load/store instruction using the previously produced data recorded for the next load/store instruction in the record/replay log file, in response to the previously produced data being recorded in the record/replay log file for the next load/store instruction.