A buffer system (101; 301) having an output (REF+, REF-; LDO) for driving a switched load (103; 303) that changes during periods indicated by a switching signal, wherein the buffer system comprises an electronic circuit, the electronic circuit comprising: an error amplifier (105, 107; 305; 601; 701; 801; 901) configured to generate an error signal output indicative of a difference between a reference voltage (V ref+, V ref-) at a first input to the error amplifier and a monitored voltage at a second input to the error amplifier; a main buffer (109, 111; 309; 603; 703; 803; 903) configured to buffer the error signal output from the error amplifier (105, 107; 305; 601; 701; 801; 901) and to deliver the buffered error signal output to the output (REF+, REF-; LDO) of the buffer system; a replica buffer (113, 115; 313; 605; 705; 805; 905) configured to buffer the error signal output from the error amplifier (105, 107; 305; 601; 701; 801; 901); a capacitance (117; 317; 607) connected between the output of the replica buffer (113, 115; 313; 605; 705; 805; 905) and the second input to the error amplifier (105, 107; 305; 601; 701; 801; 901); and a controllable electronic switch (121, 123; 321; 609) configured to: connect the second input of the error amplifier (105, 107; 305; 601; 701; 801; 901) to the output (REF+, REF-; LDO) of the buffer system when the switching signal indicates that a load change is not taking place, thereby creating a first feedback loop including the main buffer (109, 111; 309; 603; 703; 803; 903), and disconnect the second input of the error amplifier (105, 107; 305; 601; 701; 801; 901) from the output (REF+, REF-; LDO) of the buffer system when the switching signal indicates that a load change is taking place, thereby creating a second feedback loop including the replica buffer (113, 115; 313; 605; 705; 805; 905) and the capacitance (117; 317; 607). an error amplifier (105, 107; 305; 601; 701; 801; 901) configured to generate an error signal output indicative of a difference between a reference voltage (V ref+, V ref-) at a first input to the error amplifier and a monitored voltage at a second input to the error amplifier; a main buffer (109, 111; 309; 603; 703; 803; 903) configured to buffer the error signal output from the error amplifier (105, 107; 305; 601; 701; 801; 901) and to deliver the buffered error signal output to the output (REF+, REF-; LDO) of the buffer system; a replica buffer (113, 115; 313; 605; 705; 805; 905) configured to buffer the error signal output from the error amplifier (105, 107; 305; 601; 701; 801; 901); a capacitance (117; 317; 607) connected between the output of the replica buffer (113, 115; 313; 605; 705; 805; 905) and the second input to the error amplifier (105, 107; 305; 601; 701; 801; 901); and a controllable electronic switch (121, 123; 321; 609) configured to: connect the second input of the error amplifier (105, 107; 305; 601; 701; 801; 901) to the output (REF+, REF-; LDO) of the buffer system when the switching signal indicates that a load change is not taking place, thereby creating a first feedback loop including the main buffer (109, 111; 309; 603; 703; 803; 903), and disconnect the second input of the error amplifier (105, 107; 305; 601; 701; 801; 901) from the output (REF+, REF-; LDO) of the buffer system when the switching signal indicates that a load change is taking place, thereby creating a second feedback loop including the replica buffer (113, 115; 313; 605; 705; 805; 905) and the capacitance (117; 317; 607). connect the second input of the error amplifier (105, 107; 305; 601; 701; 801; 901) to the output (REF+, REF-; LDO) of the buffer system when the switching signal indicates that a load change is not taking place, thereby creating a first feedback loop including the main buffer (109, 111; 309; 603; 703; 803; 903), and disconnect the second input of the error amplifier (105, 107; 305; 601; 701; 801; 901) from the output (REF+, REF-; LDO) of the buffer system when the switching signal indicates that a load change is taking place, thereby creating a second feedback loop including the replica buffer (113, 115; 313; 605; 705; 805; 905) and the capacitance (117; 317; 607).