A signal processing device, comprising: a memory medium comprising program instructions for performing forward error correction, FEC, using an M-width approximated min-sum instruction, MAMINSUM; and a processing element configured to execute the program instructions, wherein the processing element includes an M-width data-processing pathway, wherein the M-width data-processing pathway is configured by the program instructions to execute a MAMINSUM instruction, wherein the MAMINSUM instruction specifies a set of first input operands and a set of second input operands, wherein, in executing the MAMINSUM instruction, the M-width data-processing pathway is configured to: on a first respective clock cycle of a plurality of clock cycles: determine an absolute value of a first respective input operand of the first set of input operands; determine a sign function of the first respective input operand; determine an absolute value of a second respective input operand of the second set of input operands; and determine a sign function of the second respective input operand; on a second respective clock cycle of the plurality of clock cycles: determine a respective minimum magnitude value comprising a minimum of the absolute value of the first respective input operand and the absolute value of the second respective input operand; and determine a respective final sign function comprising a product of the sign function of the first respective input operand and the sign function of the second respective input operand; and on a third respective clock cycle of the plurality of clock cycles: determine a respective output value by applying the respective final sign function to the respective minimum magnitude value; and store the respective output value. a memory medium comprising program instructions for performing forward error correction, FEC, using an M-width approximated min-sum instruction, MAMINSUM; and a processing element configured to execute the program instructions, wherein the processing element includes an M-width data-processing pathway, wherein the M-width data-processing pathway is configured by the program instructions to execute a MAMINSUM instruction, wherein the MAMINSUM instruction specifies a set of first input operands and a set of second input operands, wherein, in executing the MAMINSUM instruction, the M-width data-processing pathway is configured to: on a first respective clock cycle of a plurality of clock cycles: determine an absolute value of a first respective input operand of the first set of input operands; determine a sign function of the first respective input operand; determine an absolute value of a second respective input operand of the second set of input operands; and determine a sign function of the second respective input operand; on a second respective clock cycle of the plurality of clock cycles: determine a respective minimum magnitude value comprising a minimum of the absolute value of the first respective input operand and the absolute value of the second respective input operand; and determine a respective final sign function comprising a product of the sign function of the first respective input operand and the sign function of the second respective input operand; and on a third respective clock cycle of the plurality of clock cycles: determine a respective output value by applying the respective final sign function to the respective minimum magnitude value; and store the respective output value. on a first respective clock cycle of a plurality of clock cycles: determine an absolute value of a first respective input operand of the first set of input operands; determine a sign function of the first respective input operand; determine an absolute value of a second respective input operand of the second set of input operands; and determine a sign function of the second respective input operand; determine an absolute value of a first respective input operand of the first set of input operands; determine a sign function of the first respective input operand; determine an absolute value of a second respective input operand of the second set of input operands; and determine a sign function of the second respective input operand; on a second respective clock cycle of the plurality of clock cycles: determine a respective minimum magnitude value comprising a minimum of the absolute value of the first respective input operand and the absolute value of the second respective input operand; and determine a respective final sign function comprising a product of the sign function of the first respective input operand and the sign function of the second respective input operand; and determine a respective minimum magnitude value comprising a minimum of the absolute value of the first respective input operand and the absolute value of the second respective input operand; and determine a respective final sign function comprising a product of the sign function of the first respective input operand and the sign function of the second respective input operand; and on a third respective clock cycle of the plurality of clock cycles: determine a respective output value by applying the respective final sign function to the respective minimum magnitude value; and store the respective output value. determine a respective output value by applying the respective final sign function to the respective minimum magnitude value; and store the respective output value.