A high-frequency circuit used in a dual-band wireless apparatus for wireless communications selectively using first and second frequency bands, comprising: one or more antenna terminals (ANT1, ANT2) each connected to an antenna capable of transmitting and receiving signals in said first and second frequency bands; a first transmitting terminal (11bg-T), to which a transmitting signal in said first frequency band is input; a second transmitting terminal (11a-T), to which a transmitting signal in said second frequency band is input; a first receiving terminal (11bg-R), from which a received signal in said first frequency band is output; a second receiving terminal (11a-R), from which a received signal in said second frequency band is output; a switch circuit for switching the connection between said antenna terminals (ANT1, ANT2) and said first and second transmitting terminals (11bg-T, 11a-T) or said first and second receiving terminals (11bg-R, 11a-R); a first power amplifier circuit disposed between said switch circuit and said first transmitting terminal (11bg-T); a second power amplifier circuit disposed between said switch circuit and said second transmitting terminal (11a-T); a bandpass filter circuit (4, 5) disposed between said antenna terminals (ANT1, ANT2) and at least one of said first and second transmitting and receiving terminals (11 bg-R, 11a-R, 11bg-T, 11a-T); and a detection circuit having a voltage detection terminal (Vdet) for monitoring the output power of said first and second power amplifier circuits (2, 3); characterised in that a balanced-unbalanced conversion circuit is connected to at least one of said first and second transmitting terminals (11bg-T, 11a-T) and/or at least one of said first and second receiving terminals (11bg-R, 11a-R), and said balanced-unbalanced conversion circuit comprises: a first inductance element (Lla) connected to an unbalanced terminal (In) of the conversion circuit; a second inductance element (L1b) connected to the first inductance element (L1a); a third inductance element connected to one of the balanced terminals of the conversion circuit; a fourth inductance element connected to the other of the balanced terminals of the conversion circuit; a DC feed terminal (Vdd) connected between said third and fourth inductance elements (L2, L3); and a capacitor connected between the DC feed terminal (Vdd) and the ground. one or more antenna terminals (ANT1, ANT2) each connected to an antenna capable of transmitting and receiving signals in said first and second frequency bands; a first transmitting terminal (11bg-T), to which a transmitting signal in said first frequency band is input; a second transmitting terminal (11a-T), to which a transmitting signal in said second frequency band is input; a first receiving terminal (11bg-R), from which a received signal in said first frequency band is output; a second receiving terminal (11a-R), from which a received signal in said second frequency band is output; a switch circuit for switching the connection between said antenna terminals (ANT1, ANT2) and said first and second transmitting terminals (11bg-T, 11a-T) or said first and second receiving terminals (11bg-R, 11a-R); a first power amplifier circuit disposed between said switch circuit and said first transmitting terminal (11bg-T); a second power amplifier circuit disposed between said switch circuit and said second transmitting terminal (11a-T); a bandpass filter circuit (4, 5) disposed between said antenna terminals (ANT1, ANT2) and at least one of said first and second transmitting and receiving terminals (11 bg-R, 11a-R, 11bg-T, 11a-T); and a detection circuit having a voltage detection terminal (Vdet) for monitoring the output power of said first and second power amplifier circuits (2, 3); a balanced-unbalanced conversion circuit is connected to at least one of said first and second transmitting terminals (11bg-T, 11a-T) and/or at least one of said first and second receiving terminals (11bg-R, 11a-R), and said balanced-unbalanced conversion circuit comprises: a first inductance element (Lla) connected to an unbalanced terminal (In) of the conversion circuit; a second inductance element (L1b) connected to the first inductance element (L1a); a third inductance element connected to one of the balanced terminals of the conversion circuit; a fourth inductance element connected to the other of the balanced terminals of the conversion circuit; a DC feed terminal (Vdd) connected between said third and fourth inductance elements (L2, L3); and a capacitor connected between the DC feed terminal (Vdd) and the ground. a first inductance element (Lla) connected to an unbalanced terminal (In) of the conversion circuit; a second inductance element (L1b) connected to the first inductance element (L1a); a third inductance element connected to one of the balanced terminals of the conversion circuit; a fourth inductance element connected to the other of the balanced terminals of the conversion circuit; a DC feed terminal (Vdd) connected between said third and fourth inductance elements (L2, L3); and a capacitor connected between the DC feed terminal (Vdd) and the ground.