A method of fabricating a type III-V semiconductor device, the method comprising: providing an etching tool that comprises an interior chamber; providing a plurality of type III-V semiconductor wafers; perform ing a process cycle for each one of the type III-V semiconductor wafers in the plurality, the process cycle comprising: performing a preliminary contamination control process, wherein the preliminary contamination control process comprises forming a carbon containing protective material that covers exposed surfaces of the interior chamber; after forming the protective material inserting one of the type III-V semiconductor wafers into the interior chamber with the protective material covering the exposed surfaces of the interior chamber; plasma etching type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber while the protective material covers the exposed surfaces of the interior chamber;performing an oxygen based ashing step after the plasma etching of the type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber, wherein the oxygen based ashing step at least partially removes the carbon containing protective material from the exposed surfaces of the interior chamber; and after performing the ashing step, removing the type III-V semiconductor wafer that is present in the interior chamber. providing an etching tool that comprises an interior chamber; providing a plurality of type III-V semiconductor wafers; perform ing a process cycle for each one of the type III-V semiconductor wafers in the plurality, the process cycle comprising: performing a preliminary contamination control process, wherein the preliminary contamination control process comprises forming a carbon containing protective material that covers exposed surfaces of the interior chamber; after forming the protective material inserting one of the type III-V semiconductor wafers into the interior chamber with the protective material covering the exposed surfaces of the interior chamber; plasma etching type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber while the protective material covers the exposed surfaces of the interior chamber;performing an oxygen based ashing step after the plasma etching of the type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber, wherein the oxygen based ashing step at least partially removes the carbon containing protective material from the exposed surfaces of the interior chamber; and after performing the ashing step, removing the type III-V semiconductor wafer that is present in the interior chamber. performing a preliminary contamination control process, wherein the preliminary contamination control process comprises forming a carbon containing protective material that covers exposed surfaces of the interior chamber; after forming the protective material inserting one of the type III-V semiconductor wafers into the interior chamber with the protective material covering the exposed surfaces of the interior chamber; plasma etching type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber while the protective material covers the exposed surfaces of the interior chamber;performing an oxygen based ashing step after the plasma etching of the type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber, wherein the oxygen based ashing step at least partially removes the carbon containing protective material from the exposed surfaces of the interior chamber; and after performing the ashing step, removing the type III-V semiconductor wafer that is present in the interior chamber.