Device comprising a first circuit (CORR), a second circuit, and a third circuit (LOOP), wherein: the first circuit (CORR) is configured to: - receive a first signal (I1(t)), a second signal (Q1(t)), and a third signal (THETA), the third signal being representative of a phase shift; - generate a fourth signal (I2(t)) and a fifth signal (Q2(t)) by application of said phase shift respectively to the first signal and to the second signal; and - deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal (sI2-Q2) corresponding to a sampling over one bit of the difference between the fourth and fifth signals, and a ninth signal (sI2+Q2) corresponding to a sampling over one bit of the sum between the fourth and fifth signals, the second circuit is configured to: - receive the sixth, seventh, eighth, and ninth signals; - determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit (UP/DW) from among a first state and a second state based on the eighth and ninth signals (sI2-Q2, sI2+Q2); - deliver a digital signal (LOOP-IN) corresponding to a multiplication of the first bit (UP/DW) by a gain; and - periodically decrease, during said first phase, said gain down to a unit value, and the third circuit (LOOP) is configured to determine the third signal (THETA) based on said digital signal (LOOP-IN). the first circuit (CORR) is configured to: - receive a first signal (I1(t)), a second signal (Q1(t)), and a third signal (THETA), the third signal being representative of a phase shift; - generate a fourth signal (I2(t)) and a fifth signal (Q2(t)) by application of said phase shift respectively to the first signal and to the second signal; and - deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal (sI2-Q2) corresponding to a sampling over one bit of the difference between the fourth and fifth signals, and a ninth signal (sI2+Q2) corresponding to a sampling over one bit of the sum between the fourth and fifth signals, the second circuit is configured to: - receive the sixth, seventh, eighth, and ninth signals; - determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit (UP/DW) from among a first state and a second state based on the eighth and ninth signals (sI2-Q2, sI2+Q2); - deliver a digital signal (LOOP-IN) corresponding to a multiplication of the first bit (UP/DW) by a gain; and - periodically decrease, during said first phase, said gain down to a unit value, and - receive a first signal (I1(t)), a second signal (Q1(t)), and a third signal (THETA), the third signal being representative of a phase shift; - generate a fourth signal (I2(t)) and a fifth signal (Q2(t)) by application of said phase shift respectively to the first signal and to the second signal; and - deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal (sI2-Q2) corresponding to a sampling over one bit of the difference between the fourth and fifth signals, and a ninth signal (sI2+Q2) corresponding to a sampling over one bit of the sum between the fourth and fifth signals, the second circuit is configured to: - receive the sixth, seventh, eighth, and ninth signals; - determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit (UP/DW) from among a first state and a second state based on the eighth and ninth signals (sI2-Q2, sI2+Q2); - deliver a digital signal (LOOP-IN) corresponding to a multiplication of the first bit (UP/DW) by a gain; and - periodically decrease, during said first phase, said gain down to a unit value, and the third circuit (LOOP) is configured to determine the third signal (THETA) based on said digital signal (LOOP-IN).