A memory comprising a data transmission circuit, a data bus and a plurality of memory regions, wherein the data transmission circuit comprises at least two data transmission structures, characterised in that each of the data transmission structures comprises a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal, the memory transmission terminal is configured to connect to the memory region, the bus transmission terminal is configured to connect to the data bus, and the interactive transmission terminal is configured to connect to another data transmission structure; data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal; data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal; data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal; the data inputted from the interactive transmission terminal is data inputted through the bus transmission terminal or the memory transmission terminal of another data transmission structure; and a control module is connected to the data transmission structure and receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate a delayed input control signal corresponding to the input control signal, wherein the delayed input control signal is used for selectively establishing different data transmission paths of the data transmission structure. each of the data transmission structures comprises a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal, the memory transmission terminal is configured to connect to the memory region, the bus transmission terminal is configured to connect to the data bus, and the interactive transmission terminal is configured to connect to another data transmission structure; data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal; data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal; data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal; the data inputted from the interactive transmission terminal is data inputted through the bus transmission terminal or the memory transmission terminal of another data transmission structure; and a control module is connected to the data transmission structure and receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate a delayed input control signal corresponding to the input control signal, wherein the delayed input control signal is used for selectively establishing different data transmission paths of the data transmission structure.