A non-volatile memory device comprising: an array (501, 511, 521, 531) of four-terminal flash memory cells organized in rows and columns, each four-terminal flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal; and a high voltage row decoder (502, 512, 522, 532, 700) comprising: a latch high voltage level shifter (711, 2000) comprising inverters (2001, 2002) receiving a first voltage from a first voltage source and a second voltage smaller than the first voltage from a second voltage source and transistors receiving an input and an enabling signal, wherein after the latch high voltage level shifter (711, 2000) receives the enabling signal, the latch high voltage level shifter is configured to ramp the first voltage upward from an initial positive voltage and to ramp the second voltage upward from ground, whereby the difference between the first voltage and the second voltage is 9.0 volts or less, wherein the latch high voltage level shifter is further configured to output the first voltage when the input is high and to output the second voltage when the input is low; an erase gate decoder configured for receiving the first voltage from the latch high voltage level shifter (711, 2000) and applying the first voltage to an erase gate line connected to erase gate terminals of a plurality of four-terminal flash memory cells in the array (501, 511, 521, 531) during a program or erase operation; and a source line decoder configured for receiving the first voltage from the latch high voltage level shifter and applying the first voltage to a source line connected to source line terminals of a plurality of four-terminal flash memory cells in the array (501, 511, 521, 531) during a program or erase operation. an array (501, 511, 521, 531) of four-terminal flash memory cells organized in rows and columns, each four-terminal flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal; and a high voltage row decoder (502, 512, 522, 532, 700) comprising: a latch high voltage level shifter (711, 2000) comprising inverters (2001, 2002) receiving a first voltage from a first voltage source and a second voltage smaller than the first voltage from a second voltage source and transistors receiving an input and an enabling signal, wherein after the latch high voltage level shifter (711, 2000) receives the enabling signal, the latch high voltage level shifter is configured to ramp the first voltage upward from an initial positive voltage and to ramp the second voltage upward from ground, whereby the difference between the first voltage and the second voltage is 9.0 volts or less, wherein the latch high voltage level shifter is further configured to output the first voltage when the input is high and to output the second voltage when the input is low; an erase gate decoder configured for receiving the first voltage from the latch high voltage level shifter (711, 2000) and applying the first voltage to an erase gate line connected to erase gate terminals of a plurality of four-terminal flash memory cells in the array (501, 511, 521, 531) during a program or erase operation; and a source line decoder configured for receiving the first voltage from the latch high voltage level shifter and applying the first voltage to a source line connected to source line terminals of a plurality of four-terminal flash memory cells in the array (501, 511, 521, 531) during a program or erase operation. a latch high voltage level shifter (711, 2000) comprising inverters (2001, 2002) receiving a first voltage from a first voltage source and a second voltage smaller than the first voltage from a second voltage source and transistors receiving an input and an enabling signal, wherein after the latch high voltage level shifter (711, 2000) receives the enabling signal, the latch high voltage level shifter is configured to ramp the first voltage upward from an initial positive voltage and to ramp the second voltage upward from ground, whereby the difference between the first voltage and the second voltage is 9.0 volts or less, wherein the latch high voltage level shifter is further configured to output the first voltage when the input is high and to output the second voltage when the input is low; an erase gate decoder configured for receiving the first voltage from the latch high voltage level shifter (711, 2000) and applying the first voltage to an erase gate line connected to erase gate terminals of a plurality of four-terminal flash memory cells in the array (501, 511, 521, 531) during a program or erase operation; and a source line decoder configured for receiving the first voltage from the latch high voltage level shifter and applying the first voltage to a source line connected to source line terminals of a plurality of four-terminal flash memory cells in the array (501, 511, 521, 531) during a program or erase operation.