A communication unit (600, 700) comprising: a plurality of cascaded devices wherein the plurality of cascaded devices comprises at least one master device and at least one slave device (720, 723) configured in a master-slave arrangement; wherein the at least one master device and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a re-created synchronised system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742) wherein the communication unit (600, 700) is characterized in that: the at least one master device comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit, configured to output a system clock signal (782, 784); and a modulator circuit coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal; embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal; and distribute the modulated embedded master-slave clock signal to the at least one master device and at least one slave device; wherein the at least one master device and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed modulated embedded master-slave clock signal and re-create therefrom the system clock signal (788,790), which at this point constitutes a re-created synchronized system clock signal (788,780) and the frame start signal (731, 733) and the demodulator circuit further configured to provide the re-created synchronised system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the master device and at least one slave device. a plurality of cascaded devices wherein the plurality of cascaded devices comprises at least one master device and at least one slave device (720, 723) configured in a master-slave arrangement; wherein the at least one master device and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a re-created synchronised system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742) wherein the communication unit (600, 700) is characterized in that: the at least one master device comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit, configured to output a system clock signal (782, 784); and a modulator circuit coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal; embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal; and distribute the modulated embedded master-slave clock signal to the at least one master device and at least one slave device; an analog-to-digital converter, ADC, (741, 742) configured to use a re-created synchronised system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742) wherein the communication unit (600, 700) is characterized in that: the at least one master device comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit, configured to output a system clock signal (782, 784); and a modulator circuit coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal; embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal; and distribute the modulated embedded master-slave clock signal to the at least one master device and at least one slave device; a clock generation circuit comprising an internally-generated reference phase locked loop circuit, configured to output a system clock signal (782, 784); and a modulator circuit coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal; embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal; and distribute the modulated embedded master-slave clock signal to the at least one master device and at least one slave device; receive the system clock signal and a frame start signal; embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal; and distribute the modulated embedded master-slave clock signal to the at least one master device and at least one slave device; wherein the at least one master device and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed modulated embedded master-slave clock signal and re-create therefrom the system clock signal (788,790), which at this point constitutes a re-created synchronized system clock signal (788,780) and the frame start signal (731, 733) and the demodulator circuit further configured to provide the re-created synchronised system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the master device and at least one slave device.