A display apparatus comprising a reset unit, multiple light-emitting elements and pixel driving circuits (300, 400) for driving the light-emitting elements, the pixel driving circuits (300, 400) comprising: a scanning line (S(n)) configured to provide a scanning signal (Vs(n)); a power line comprising a first power line (ELVDD) configured to provide a voltage at a high level to the pixel driving circuit (300, 400) and a second power line (ELVSS) configured to provide a voltage at a low level to the pixel driving circuit (300, 400); and a data line (DATA) configured to provide a data signal (data_n); a light-emitting control signal line (EMB(n)) configured to provide a light-emitting control signal (Vemb(n)); a driving transistor (DTFT) having a source electrode connected to one end of the light-emitting element, a gate electrode connected to a first intermediate node (p), and a drain electrode connected to a second intermediate node (q), wherein the first power line (ELVDD) is connected to the other end of the light-emitting element; a charging unit having a second transistor having a gate connected to the scanning line (S(n)), a first electrode connected to the data line (DATA), and a second electrode connected to the first intermediate node (p); a storage capacitor having a first end connected to the second intermediate node (q) and a second end connected to a third intermediate node (r); and a light-emitting control unit having a first transistor and a third transistor, in which each of the first transistor and the third transistor has a gate connected to the light-emitting control signal line (EMB(n)), wherein the first transistor has a first electrode connected to the second intermediate node (q) and a second electrode connected to the second power line (ELVSS), and the third transistor has a first electrode connected to the first intermediate node (p) and a second electrode connected to the third intermediate node (r); wherein a row of the pixel driving circuits connected to the same scanning line share the reset unit, the reset unit comprising a switch transistor having a first electrode connected to a reference signal line (Vref), a gate connected to the scanning line (S(n)), and a second electrode connected to the third intermediate node (r) of the row of pixel driving circuits. a scanning line (S(n)) configured to provide a scanning signal (Vs(n)); a power line comprising a first power line (ELVDD) configured to provide a voltage at a high level to the pixel driving circuit (300, 400) and a second power line (ELVSS) configured to provide a voltage at a low level to the pixel driving circuit (300, 400); and a data line (DATA) configured to provide a data signal (data_n); a light-emitting control signal line (EMB(n)) configured to provide a light-emitting control signal (Vemb(n)); a driving transistor (DTFT) having a source electrode connected to one end of the light-emitting element, a gate electrode connected to a first intermediate node (p), and a drain electrode connected to a second intermediate node (q), wherein the first power line (ELVDD) is connected to the other end of the light-emitting element; a charging unit having a second transistor having a gate connected to the scanning line (S(n)), a first electrode connected to the data line (DATA), and a second electrode connected to the first intermediate node (p); a storage capacitor having a first end connected to the second intermediate node (q) and a second end connected to a third intermediate node (r); and a light-emitting control unit having a first transistor and a third transistor, in which each of the first transistor and the third transistor has a gate connected to the light-emitting control signal line (EMB(n)), wherein the first transistor has a first electrode connected to the second intermediate node (q) and a second electrode connected to the second power line (ELVSS), and the third transistor has a first electrode connected to the first intermediate node (p) and a second electrode connected to the third intermediate node (r); wherein a row of the pixel driving circuits connected to the same scanning line share the reset unit, the reset unit comprising a switch transistor having a first electrode connected to a reference signal line (Vref), a gate connected to the scanning line (S(n)), and a second electrode connected to the third intermediate node (r) of the row of pixel driving circuits.