A variable range logic threshold enabled input receiver apparatus, the apparatus comprising: a logic device; a logic threshold configuration (630, 634, 632) coupled in parallel to the logic device and configured to receive a variable logic threshold value (Vref) and to control the logic threshold of the logic device for the variable logic threshold value the input current connections for the logic device and the logic threshold configuration being common as are the output current connections; characterised in that: the logic device comprises an NMOS inverter having a gate adapted to receive an input signal; wherein the variable range logic threshold enabled input receiver apparatus futher comprises: a helper device (642, 644) configured to also receive the variable logic threshold value Vref an configured to provide a bias current path from a power supply Vdd to the logic device distinct from a bias current path provided from Vdd to the logic device by the logic threshold configuration; and wherein the logic threshold configuration comprises: a Vref NMOS FET having a gate configured to receive the variable logic threshold value, and having a source common to a source of the NMOS inverter; a first PMOS pull up FET with a source coupled to Vdd, a drain, a gate common to the drain and coupled to the drain of the NMOS inverter; a second PMOS pull up FET with a source coupled to Vdd, with a gate connection coupled to a drain of the Vref NMOS FET and a drain coupled to the drain of the NMOS inverter; and wherein the helper device comprises one or more PMOS FET positioned in parallel to the first and second PMOS pull up FET (632, 634), has a gate controlled by the Vref value and is adapted to pull up the drain of the NMOS inverter. a logic device; a logic threshold configuration (630, 634, 632) coupled in parallel to the logic device and configured to receive a variable logic threshold value (Vref) and to control the logic threshold of the logic device for the variable logic threshold value the input current connections for the logic device and the logic threshold configuration being common as are the output current connections; characterised in that: the logic device comprises an NMOS inverter having a gate adapted to receive an input signal; wherein the variable range logic threshold enabled input receiver apparatus futher comprises: a helper device (642, 644) configured to also receive the variable logic threshold value Vref an configured to provide a bias current path from a power supply Vdd to the logic device distinct from a bias current path provided from Vdd to the logic device by the logic threshold configuration; and wherein the logic threshold configuration comprises: a Vref NMOS FET having a gate configured to receive the variable logic threshold value, and having a source common to a source of the NMOS inverter; a first PMOS pull up FET with a source coupled to Vdd, a drain, a gate common to the drain and coupled to the drain of the NMOS inverter; a second PMOS pull up FET with a source coupled to Vdd, with a gate connection coupled to a drain of the Vref NMOS FET and a drain coupled to the drain of the NMOS inverter; and wherein the helper device comprises one or more PMOS FET positioned in parallel to the first and second PMOS pull up FET (632, 634), has a gate controlled by the Vref value and is adapted to pull up the drain of the NMOS inverter. a Vref NMOS FET having a gate configured to receive the variable logic threshold value, and having a source common to a source of the NMOS inverter; a first PMOS pull up FET with a source coupled to Vdd, a drain, a gate common to the drain and coupled to the drain of the NMOS inverter; a second PMOS pull up FET with a source coupled to Vdd, with a gate connection coupled to a drain of the Vref NMOS FET and a drain coupled to the drain of the NMOS inverter; and wherein the helper device comprises one or more PMOS FET positioned in parallel to the first and second PMOS pull up FET (632, 634), has a gate controlled by the Vref value and is adapted to pull up the drain of the NMOS inverter.