A manufacturing method of a TFT array substrate, including the following steps: respectively forming a metal oxide semiconductor layer, an etching barrier layer, a source electrode, a data line, a drain electrode, a pixel electrode, a gate insulating layer, a contact hole, a gate electrode and a gate scanning line on a substrate by patterning processes, wherein the metal oxide semiconductor layer and the etching barrier layer are formed by a first patterning process, and the source electrode, the drain electrode, the pixel electrode and the data line are formed by a second patterning process, wherein the manufacturing method includes the following steps: Step S1): forming the metal oxide semiconductor layer and the etching barrier layer on the substrate by the first patterning process with a first gray-tone or half-tone mask; Step S2): forming the source electrode, the drain electrode, the data line and the pixel electrode on the substrate after the step S1) by the second patterning process with a second gray-tone or half-tone mask; Step S3): forming the gate insulating layer on the substrate after the step S2), and forming the contact hole by a third patterning process; and Step S4): forming the gate electrode and the gate scanning line on the substrate after the step S3) by a forth patterning process, wherein the step S1) includes the following steps: S11) depositing a metal oxide semiconductor film and an etching barrier film in this order on the substrate; S12) coating a layer of photoresist on the substrate after the step S11); S13) using the first gray-tone or half-tone mask to perform exposing and developing processes on the photoresist so as to form a photoresist completely retained region, a photoresist partially retained region and photoresist completely removed regions, the photoresist completely retained region corresponding to a region for forming the etching barrier layer, the photoresist partially retained region corresponding to a region for forming the metal oxide semiconductor layer, and regions not covered by the photoresist corresponding to the photoresist completely removed region; S14) performing an etching process after the step S13) so as to form the metal oxide semiconductor layer; S15) performing an ashing treatment after the step S14) so as to remove the photoresist of the photoresist partially retained region; S16) performing an etching process after the step S15) so as to form the etching barrier layer; and S17) peeling off a remaining portion of the photoresist, wherein in the step S11), a modification layer is firstly deposited on the substrate, then, the metal oxide semiconductor film, and the etching barrier film are deposited sequentially on the modification layer,wherein the etching barrier layer is deposited as a dual-layer structure made of a SiO 2 layer contacting the metal oxide semiconductor layer and being formed by a low speed deposition manner, and of a SiN x layer away from the metal oxide semiconductor layer and being formed by a high speed deposition manner; the deposition of the modification layer is performed by a PECVD method; and the modification layer is made of an oxide, a nitride or an oxynitride compound, and a thickness of the modification layer is in a range of 500 - 2000 Å. Step S1): forming the metal oxide semiconductor layer and the etching barrier layer on the substrate by the first patterning process with a first gray-tone or half-tone mask; Step S2): forming the source electrode, the drain electrode, the data line and the pixel electrode on the substrate after the step S1) by the second patterning process with a second gray-tone or half-tone mask; Step S3): forming the gate insulating layer on the substrate after the step S2), and forming the contact hole by a third patterning process; and Step S4): forming the gate electrode and the gate scanning line on the substrate after the step S3) by a forth patterning process, S11) depositing a metal oxide semiconductor film and an etching barrier film in this order on the substrate; S12) coating a layer of photoresist on the substrate after the step S11); S13) using the first gray-tone or half-tone mask to perform exposing and developing processes on the photoresist so as to form a photoresist completely retained region, a photoresist partially retained region and photoresist completely removed regions, the photoresist completely retained region corresponding to a region for forming the etching barrier layer, the photoresist partially retained region corresponding to a region for forming the metal oxide semiconductor layer, and regions not covered by the photoresist corresponding to the photoresist completely removed region; S14) performing an etching process after the step S13) so as to form the metal oxide semiconductor layer; S15) performing an ashing treatment after the step S14) so as to remove the photoresist of the photoresist partially retained region; S16) performing an etching process after the step S15) so as to form the etching barrier layer; and S17) peeling off a remaining portion of the photoresist,