An integrated circuit operating at a nominal operating voltage (V DD) with a signal pad and a control circuit coupled with the signal pad, the control circuit comprising: a first N-channel metal oxide semiconductor (NMOS) transistor having a drain coupled to the integrated circuit signal pad and a gate coupled to the nominal operating voltage (V DD); a second NMOS transistor having a source coupled to a power common and a drain coupled to a source of the first NMOS transistor; a first P-channel metal oxide semiconductor (PMOS) transistor having a drain coupled to the integrated circuit signal pad; a second PMOS transistor having a drain coupled to a source of the first PMOS transistor, and a source of the second PMOS transistor coupled to the nominal operating voltage (V DD); a third PMOS transistor having a drain coupled to the integrated circuit signal pad and a source coupled to a gate of the second PMOS transistor; a fourth PMOS transistor having a drain coupled to the gate of the second PMOS transistor and the source of the third PMOS transistor, the fourth PMOS transistor having a source coupled to a control signal; a third NMOS transistor having a drain coupled to the gate of the second PMOS transistor and the source of the third PMOS transistor, the third NMOS transistor has a gate coupled to the nominal operating voltage and a source coupled to the control signal; a fourth NMOS transistor having a source coupled to the integrated circuit signal pad; a fifth PMOS transistor having a source coupled to the integrated circuit signal pad and a gate coupled to the nominal operating voltage (V DD); drains of the fourth NMOS transistor and the fifth PMOS transistor are coupled to a gate of the fourth PMOS transistor; a gate of the first PMOS transistor is coupled to a data out signal; characterized in that the control signal is a control signal which when set provides for a five volt tolerance of the integrated circuit signal pad; the gate of the fourth NMOS transistor is coupled to the nominal operating voltage (V DD); a gate of the second NMOS transistor is coupled to a data out enable signal; a first parasitic diode is formed between the source and the drain of the first PMOS transistor; and a second parasitic diode is formed between the source and the drain of the second PMOS transistor, wherein when the control signal is at a logic 1, the control circuit is controlled such that current flow through the second parasitic diode can drive the integrated circuit signal pad to substantially the nominal operating voltage (V DD) while the second parasitic diode substantially prevents current flow from the integrated circuit signal pad to the nominal operating voltage (V DD) when the integrated circuit signal pad is at a voltage higher than the nominal operating voltage (V DD). a first N-channel metal oxide semiconductor (NMOS) transistor having a drain coupled to the integrated circuit signal pad and a gate coupled to the nominal operating voltage (V DD); a second NMOS transistor having a source coupled to a power common and a drain coupled to a source of the first NMOS transistor; a first P-channel metal oxide semiconductor (PMOS) transistor having a drain coupled to the integrated circuit signal pad; a second PMOS transistor having a drain coupled to a source of the first PMOS transistor, and a source of the second PMOS transistor coupled to the nominal operating voltage (V DD); a third PMOS transistor having a drain coupled to the integrated circuit signal pad and a source coupled to a gate of the second PMOS transistor; a fourth PMOS transistor having a drain coupled to the gate of the second PMOS transistor and the source of the third PMOS transistor, the fourth PMOS transistor having a source coupled to a control signal; a third NMOS transistor having a drain coupled to the gate of the second PMOS transistor and the source of the third PMOS transistor, the third NMOS transistor has a gate coupled to the nominal operating voltage and a source coupled to the control signal; a fourth NMOS transistor having a source coupled to the integrated circuit signal pad; a fifth PMOS transistor having a source coupled to the integrated circuit signal pad and a gate coupled to the nominal operating voltage (V DD); drains of the fourth NMOS transistor and the fifth PMOS transistor are coupled to a gate of the fourth PMOS transistor; a gate of the first PMOS transistor is coupled to a data out signal; characterized in that the control signal is a control signal which when set provides for a five volt tolerance of the integrated circuit signal pad; the gate of the fourth NMOS transistor is coupled to the nominal operating voltage (V DD); a gate of the second NMOS transistor is coupled to a data out enable signal; a first parasitic diode is formed between the source and the drain of the first PMOS transistor; and a second parasitic diode is formed between the source and the drain of the second PMOS transistor, wherein when the control signal is at a logic 1, the control circuit is controlled such that current flow through the second parasitic diode can drive the integrated circuit signal pad to substantially the nominal operating voltage (V DD) while the second parasitic diode substantially prevents current flow from the integrated circuit signal pad to the nominal operating voltage (V DD) when the integrated circuit signal pad is at a voltage higher than the nominal operating voltage (V DD).