A radio system comprising: a radio unit; and a signal processing unit (4,6), wherein said radio unit comprises: a reception signal converting circuit (42,24-1,24-2,71) configured to generate a reception digital signal from a reception radio signal; a clock generating circuit configured to generate a clock; and a first interface (31, 46) configured to operate in synchronization with said clock, and wherein said signal processing unit (4,6) comprises: a second interface (34, 47) connected with said first interface (31, 46) and configured to operate in synchronization with said clock; and a processing section (26, 48) configured to convert said reception digital signal supplied through said first and second interfaces, wherein said reception signal converting circuit (42, 24-1, 24-2, 71) generates the reception digital signal by carrying out A/D sampling in synchronization with said clock, and said processing section (26, 48) is configured to discriminate a reception data from said reception digital signal in synchronization with said clock, wherein the first interface (31, 46) includes a first converting circuit, wherein the first converting circuit is configured to perform a first signal converting process in synchronization with said clock, wherein the second interface (34, 47) includes a second converting circuit, wherein the second converting circuit is configured to perform a second signal converting process in synchronization with said clock, wherein the first signal converting process and the second signal converting process include at least one of a signal level converting process and a parallel bit converting process, wherein the signal level converting process is a process for converting physical quantities of each input and output, and wherein the parallel bit converting process is a process for combining and separating data when data bit width of the input and output are different. a radio unit; and a signal processing unit (4,6), wherein said radio unit comprises: a reception signal converting circuit (42,24-1,24-2,71) configured to generate a reception digital signal from a reception radio signal; a clock generating circuit configured to generate a clock; and a first interface (31, 46) configured to operate in synchronization with said clock, and a reception signal converting circuit (42,24-1,24-2,71) configured to generate a reception digital signal from a reception radio signal; a clock generating circuit configured to generate a clock; and a first interface (31, 46) configured to operate in synchronization with said clock, and wherein said signal processing unit (4,6) comprises: a second interface (34, 47) connected with said first interface (31, 46) and configured to operate in synchronization with said clock; and a processing section (26, 48) configured to convert said reception digital signal supplied through said first and second interfaces, a second interface (34, 47) connected with said first interface (31, 46) and configured to operate in synchronization with said clock; and a processing section (26, 48) configured to convert said reception digital signal supplied through said first and second interfaces, wherein said reception signal converting circuit (42, 24-1, 24-2, 71) generates the reception digital signal by carrying out A/D sampling in synchronization with said clock, and said processing section (26, 48) is configured to discriminate a reception data from said reception digital signal in synchronization with said clock, wherein the first interface (31, 46) includes a first converting circuit, wherein the first converting circuit is configured to perform a first signal converting process in synchronization with said clock, wherein the second interface (34, 47) includes a second converting circuit, wherein the second converting circuit is configured to perform a second signal converting process in synchronization with said clock, wherein the first signal converting process and the second signal converting process include at least one of a signal level converting process and a parallel bit converting process, wherein the signal level converting process is a process for converting physical quantities of each input and output, and wherein the parallel bit converting process is a process for combining and separating data when data bit width of the input and output are different. said reception signal converting circuit (42, 24-1, 24-2, 71) generates the reception digital signal by carrying out A/D sampling in synchronization with said clock, and said processing section (26, 48) is configured to discriminate a reception data from said reception digital signal in synchronization with said clock, wherein the first interface (31, 46) includes a first converting circuit, wherein the first converting circuit is configured to perform a first signal converting process in synchronization with said clock, wherein the second interface (34, 47) includes a second converting circuit, wherein the second converting circuit is configured to perform a second signal converting process in synchronization with said clock, wherein the first signal converting process and the second signal converting process include at least one of a signal level converting process and a parallel bit converting process, wherein the signal level converting process is a process for converting physical quantities of each input and output, and wherein the parallel bit converting process is a process for combining and separating data when data bit width of the input and output are different.