A power-on reset circuit, comprising: a complementary-to-absolute-temperature, CTAT, circuit that is configured to output a first control voltage; a proportional-to-absolute-temperature, PTAT, circuit that is configured to output a first PTAT current; and a comparator that is coupled with the CTAT circuit, and configured to receive the first control voltage, and a second control voltage that is generated based on the first PTAT current and compare the first and second control voltages to generate a power-on reset signal; characterised in that the PTAT circuit comprises a first resistor that is configured to receive a supply voltage; first and second transistors each having first through third terminals, wherein the first terminal of the first transistor is configured to receive the supply voltage and the first terminal of the second transistor is coupled with the first resistor, wherein the second terminal of the second transistor is coupled with the second and third terminals of the first transistor, and wherein the third terminals of the first and second transistors are configured to output second and third PTAT currents, respectively: third and fourth transistors each having first through third terminals, wherein the first terminals of the third and fourth transistors are coupled with a ground terminal, and the second terminal of the third transistor is coupled with the second and third terminals of the fourth transistor, and wherein the third terminals of the third and fourth transistors are coupled with the third terminals of the first and second transistors, respectively; and fifth and sixth transistors each having first through third terminals, wherein the second terminals of the fifth and sixth transistors are coupled with the second terminals of the first and fourth transistors, respectively, and wherein the first terminal of the fifth transistor is configured to receive the supply voltage, and the first terminal of the sixth transistor is coupled with the ground terminal. a complementary-to-absolute-temperature, CTAT, circuit that is configured to output a first control voltage; a proportional-to-absolute-temperature, PTAT, circuit that is configured to output a first PTAT current; and a comparator that is coupled with the CTAT circuit, and configured to receive the first control voltage, and a second control voltage that is generated based on the first PTAT current and compare the first and second control voltages to generate a power-on reset signal; characterised in that the PTAT circuit comprises a first resistor that is configured to receive a supply voltage; first and second transistors each having first through third terminals, wherein the first terminal of the first transistor is configured to receive the supply voltage and the first terminal of the second transistor is coupled with the first resistor, wherein the second terminal of the second transistor is coupled with the second and third terminals of the first transistor, and wherein the third terminals of the first and second transistors are configured to output second and third PTAT currents, respectively: third and fourth transistors each having first through third terminals, wherein the first terminals of the third and fourth transistors are coupled with a ground terminal, and the second terminal of the third transistor is coupled with the second and third terminals of the fourth transistor, and wherein the third terminals of the third and fourth transistors are coupled with the third terminals of the first and second transistors, respectively; and fifth and sixth transistors each having first through third terminals, wherein the second terminals of the fifth and sixth transistors are coupled with the second terminals of the first and fourth transistors, respectively, and wherein the first terminal of the fifth transistor is configured to receive the supply voltage, and the first terminal of the sixth transistor is coupled with the ground terminal. third and fourth transistors each having first through third terminals, wherein the first terminals of the third and fourth transistors are coupled with a ground terminal, and the second terminal of the third transistor is coupled with the second and third terminals of the fourth transistor, and wherein the third terminals of the third and fourth transistors are coupled with the third terminals of the first and second transistors, respectively; and fifth and sixth transistors each having first through third terminals, wherein the second terminals of the fifth and sixth transistors are coupled with the second terminals of the first and fourth transistors, respectively, and wherein the first terminal of the fifth transistor is configured to receive the supply voltage, and the first terminal of the sixth transistor is coupled with the ground terminal.