A three-dimensional memory device (100, 200), comprising: a first page buffer (111, 211) and a second page buffer (112, 212), respectively configured to temporarily store a first write-in data and a second write-in data; a sense amplifier (130, 230); a first path selector (121, 221), coupled between a first global bit line, the sense amplifier (130, 230), and the first page buffer (111, 211), and coupling the sense amplifier (130, 230) or the first page buffer (111,211) to the first global bit line according to a first control signal; and a second path selector (122, 222), coupled between a second global bit line, the sense amplifier (130, 230), and the second page buffer (112,212), and coupling the sense amplifier (130, 230) or the second page buffer (112, 212) to the second global bit line according to a second control signal wherein the first path selector (121, 221) comprises: a first switch, coupled between the first global bit line (GBL1, GBL(n)) and the first page buffer (111, 211); and a second switch, coupled between the first global bit line (GBL1, GBL(n)) and the sense amplifier (130, 230); and wherein the second path selector (122, 222) comprises: a third switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the second page buffer (112, 212); and a fourth switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the sense amplifier (130, 230). a first page buffer (111, 211) and a second page buffer (112, 212), respectively configured to temporarily store a first write-in data and a second write-in data; a sense amplifier (130, 230); a first path selector (121, 221), coupled between a first global bit line, the sense amplifier (130, 230), and the first page buffer (111, 211), and coupling the sense amplifier (130, 230) or the first page buffer (111,211) to the first global bit line according to a first control signal; and a second path selector (122, 222), coupled between a second global bit line, the sense amplifier (130, 230), and the second page buffer (112,212), and coupling the sense amplifier (130, 230) or the second page buffer (112, 212) to the second global bit line according to a second control signal wherein the first path selector (121, 221) comprises: a first switch, coupled between the first global bit line (GBL1, GBL(n)) and the first page buffer (111, 211); and a second switch, coupled between the first global bit line (GBL1, GBL(n)) and the sense amplifier (130, 230); and wherein the second path selector (122, 222) comprises: a third switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the second page buffer (112, 212); and a fourth switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the sense amplifier (130, 230). a first switch, coupled between the first global bit line (GBL1, GBL(n)) and the first page buffer (111, 211); and a second switch, coupled between the first global bit line (GBL1, GBL(n)) and the sense amplifier (130, 230); and wherein the second path selector (122, 222) comprises: a third switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the second page buffer (112, 212); and a fourth switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the sense amplifier (130, 230). a third switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the second page buffer (112, 212); and a fourth switch, coupled between the second global bit line (GBL2, GBL(n+1)) and the sense amplifier (130, 230).