A logic gate (30, 40) comprising: a first input and a second input; a first memristor (M 1), a second memristor (M 2), a third memristor (M 3), and a fourth memristor (M 4), each memristor having a positive terminal and a negative terminal; and a first output (32, 42) and a second output (34, 44), wherein the negative terminal of the first memristor (M 1) and the positive terminal of the second memristor (M 2) are connected in common to the first input, wherein the negative terminal of the third memristor (M 3) and the positive terminal of the fourth memristor (M 4) are connected in common to the second input, wherein the negative terminal of the second memristor (M 2) and the negative terminal of the fourth memristor (M 4) are connected in common to the first output (32, 42), wherein the positive terminal of the first memristor (M 1) and the positive terminal of the third memristor (M 3) are connected in common to the second output (34, 44), further comprising a transistor (NMOST, PMOST, T), wherein the gate of the transistor is connected to one of the first and second outputs (34, 42), wherein the drain of the transistor is connected to the other of the first and second outputs (32, 44), and wherein the source of the transistor is connected to a positive or negative supply voltage or ground, and wherein, in use, the voltage of the first output (32, 42), corresponds to the result of a first logic operation relative to voltages applied to the first and second inputs (A, B), and the voltage of the second output (34, 44), corresponds to the result of a second logic operation relative to voltages applied to the first and second inputs (A, B), and wherein the first logic operation is different from the second logic operation. a first input and a second input; a first memristor (M 1), a second memristor (M 2), a third memristor (M 3), and a fourth memristor (M 4), each memristor having a positive terminal and a negative terminal; and a first output (32, 42) and a second output (34, 44), wherein the negative terminal of the first memristor (M 1) and the positive terminal of the second memristor (M 2) are connected in common to the first input, wherein the negative terminal of the third memristor (M 3) and the positive terminal of the fourth memristor (M 4) are connected in common to the second input, wherein the negative terminal of the second memristor (M 2) and the negative terminal of the fourth memristor (M 4) are connected in common to the first output (32, 42), wherein the positive terminal of the first memristor (M 1) and the positive terminal of the third memristor (M 3) are connected in common to the second output (34, 44), further comprising a transistor (NMOST, PMOST, T), wherein the gate of the transistor is connected to one of the first and second outputs (34, 42), wherein the drain of the transistor is connected to the other of the first and second outputs (32, 44), and wherein the source of the transistor is connected to a positive or negative supply voltage or ground, and wherein, in use, the voltage of the first output (32, 42), corresponds to the result of a first logic operation relative to voltages applied to the first and second inputs (A, B), and the voltage of the second output (34, 44), corresponds to the result of a second logic operation relative to voltages applied to the first and second inputs (A, B), and wherein the first logic operation is different from the second logic operation.