A memory device, comprising: a silicon substrate having an upper surface, wherein: the upper surface is planar in a memory cell area of the silicon substrate, the upper surface includes an upwardly extending silicon fin in a logic device area of the silicon substrate, and the silicon fin includes a pair of side surfaces extending up and terminating at a top surface; a memory device in the memory cell area, comprising: spaced apart first source and first drain regions formed in the silicon substrate with a first channel region of the silicon substrate extending there between, a conductive floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the first source region, a conductive word line gate disposed over and insulated from a second portion of the first channel region that is adjacent the first drain region, a conductive control gate disposed over and insulated from the floating gate, and a conductive erase gate disposed over and insulated from the first source region; a logic device in the logic device area, comprising: spaced apart second source and second drain regions formed in the silicon substrate with a second channel region of the silicon substrate extending there between, wherein the second channel region extends along the top surface and the pair of side surfaces, and a conductive logic gate disposed over and insulated from the top surface, and disposed laterally adjacent to and insulated from the pair of side surfaces. a silicon substrate having an upper surface, wherein: the upper surface is planar in a memory cell area of the silicon substrate, the upper surface includes an upwardly extending silicon fin in a logic device area of the silicon substrate, and the silicon fin includes a pair of side surfaces extending up and terminating at a top surface; the upper surface is planar in a memory cell area of the silicon substrate, the upper surface includes an upwardly extending silicon fin in a logic device area of the silicon substrate, and the silicon fin includes a pair of side surfaces extending up and terminating at a top surface; a memory device in the memory cell area, comprising: spaced apart first source and first drain regions formed in the silicon substrate with a first channel region of the silicon substrate extending there between, a conductive floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the first source region, a conductive word line gate disposed over and insulated from a second portion of the first channel region that is adjacent the first drain region, a conductive control gate disposed over and insulated from the floating gate, and a conductive erase gate disposed over and insulated from the first source region; spaced apart first source and first drain regions formed in the silicon substrate with a first channel region of the silicon substrate extending there between, a conductive floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the first source region, a conductive word line gate disposed over and insulated from a second portion of the first channel region that is adjacent the first drain region, a conductive control gate disposed over and insulated from the floating gate, and a conductive erase gate disposed over and insulated from the first source region; a logic device in the logic device area, comprising: spaced apart second source and second drain regions formed in the silicon substrate with a second channel region of the silicon substrate extending there between, wherein the second channel region extends along the top surface and the pair of side surfaces, and a conductive logic gate disposed over and insulated from the top surface, and disposed laterally adjacent to and insulated from the pair of side surfaces. spaced apart second source and second drain regions formed in the silicon substrate with a second channel region of the silicon substrate extending there between, wherein the second channel region extends along the top surface and the pair of side surfaces, and a conductive logic gate disposed over and insulated from the top surface, and disposed laterally adjacent to and insulated from the pair of side surfaces.