An electronic device comprising: a plurality of CMOS control elements (1800, 1805, 1810, 1815) arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements (1800, 1805, 1810, 1815) comprising two semiconductor devices, the plurality of CMOS control elements comprising: a first subset of CMOS control elements (1800, 1810), each CMOS control element of the first subset of CMOS control elements comprising a semiconductor device of a first class (1830, 1832) and a semiconductor device of a second class; and a second subset of CMOS control elements (1805, 1815), each CMOS control element of the second subset of CMOS control elements comprising a semiconductor device of the first class (1834, 1836) and a semiconductor device of a third class; wherein the plurality of CMOS control elements (1800, 1805, 1810, 1815) are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class (1830, 1832, 1834, 1836) are only adjacent to other CMOS semiconductor devices of the first class (1830, 1832, 1834, 1836), CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class; wherein the semiconductor devices of the first class comprise low voltage devices, the semiconductor devices of the second class comprise high voltage PMOS devices, and the semiconductor devices of the third class comprise high voltage NMOS devices. a plurality of CMOS control elements (1800, 1805, 1810, 1815) arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements (1800, 1805, 1810, 1815) comprising two semiconductor devices, the plurality of CMOS control elements comprising: a first subset of CMOS control elements (1800, 1810), each CMOS control element of the first subset of CMOS control elements comprising a semiconductor device of a first class (1830, 1832) and a semiconductor device of a second class; and a second subset of CMOS control elements (1805, 1815), each CMOS control element of the second subset of CMOS control elements comprising a semiconductor device of the first class (1834, 1836) and a semiconductor device of a third class; a first subset of CMOS control elements (1800, 1810), each CMOS control element of the first subset of CMOS control elements comprising a semiconductor device of a first class (1830, 1832) and a semiconductor device of a second class; and a second subset of CMOS control elements (1805, 1815), each CMOS control element of the second subset of CMOS control elements comprising a semiconductor device of the first class (1834, 1836) and a semiconductor device of a third class; wherein the plurality of CMOS control elements (1800, 1805, 1810, 1815) are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class (1830, 1832, 1834, 1836) are only adjacent to other CMOS semiconductor devices of the first class (1830, 1832, 1834, 1836), CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class; wherein the semiconductor devices of the first class comprise low voltage devices, the semiconductor devices of the second class comprise high voltage PMOS devices, and the semiconductor devices of the third class comprise high voltage NMOS devices.