A method comprising: generating a buck output voltage using a buck converter, based on a clock signal for controlling switches of said buck converter to set the output voltage of said buck converter to a target buck voltage; generating a target boost voltage using a boost converter comprising a first switch coupled to an inductor; generating a control signal (NCTRL2) for the boost converter from said buck clock signal to selectively close or open the first switch; wherein said generating a control signal (NCTRL2) for the boost converter comprises setting the control signal (NCTRL2) to the buck clock signal when the buck clock signal is within a predetermined range optimized for the target boost voltage defined by a minimum frequency (Fmin) and a maximum Frequency (Fmax), using a first limiting circuit to set the switching frequency of the control signal (NCTRL2) to a frequency no less than said minimum frequency (Fmin) to avoid under-boost, when the frequency of the buck clock signal is less than the minimum frequency and using a second limiting circuit to set the switching frequency of the control signal (NCTRL2) to a frequency no more than said maximum frequency (Fmax) to avoid over-boost, when the frequency of the buck clock signal is greater than the maximum frequency (Fmax); wherein the frequency of the control signal (NCTRL2) is within said predetermined frequency range and wherein the control signal (NCTRL2) for the boost converter is synchronous with the buck clock signal when the frequency of the buck clock signal is within said predetermined frequency range. generating a buck output voltage using a buck converter, based on a clock signal for controlling switches of said buck converter to set the output voltage of said buck converter to a target buck voltage; generating a target boost voltage using a boost converter comprising a first switch coupled to an inductor; generating a control signal (NCTRL2) for the boost converter from said buck clock signal to selectively close or open the first switch; wherein said generating a control signal (NCTRL2) for the boost converter comprises setting the control signal (NCTRL2) to the buck clock signal when the buck clock signal is within a predetermined range optimized for the target boost voltage defined by a minimum frequency (Fmin) and a maximum Frequency (Fmax), using a first limiting circuit to set the switching frequency of the control signal (NCTRL2) to a frequency no less than said minimum frequency (Fmin) to avoid under-boost, when the frequency of the buck clock signal is less than the minimum frequency and using a second limiting circuit to set the switching frequency of the control signal (NCTRL2) to a frequency no more than said maximum frequency (Fmax) to avoid over-boost, when the frequency of the buck clock signal is greater than the maximum frequency (Fmax); setting the control signal (NCTRL2) to the buck clock signal when the buck clock signal is within a predetermined range optimized for the target boost voltage defined by a minimum frequency (Fmin) and a maximum Frequency (Fmax), using a first limiting circuit to set the switching frequency of the control signal (NCTRL2) to a frequency no less than said minimum frequency (Fmin) to avoid under-boost, when the frequency of the buck clock signal is less than the minimum frequency and using a second limiting circuit to set the switching frequency of the control signal (NCTRL2) to a frequency no more than said maximum frequency (Fmax) to avoid over-boost, when the frequency of the buck clock signal is greater than the maximum frequency (Fmax); wherein the frequency of the control signal (NCTRL2) is within said predetermined frequency range and wherein the control signal (NCTRL2) for the boost converter is synchronous with the buck clock signal when the frequency of the buck clock signal is within said predetermined frequency range.