A memory bit cell selection circuit for a memory system comprising single port memory bit cells and configured to separately decode memory read and write addresses into read and write row and column selects, respectively, the memory bit cell selection circuit configured to: in response to a memory write operation: receive a write row select indicating a memory bit cell row (R -R) among a plurality of memory bit cell rows in a memory array corresponding to a memory write address for the memory write operation; receive a write column select indicating a memory bit cell column (C -C) among a plurality of memory bit cell columns in the memory array corresponding to the memory write address for the memory write operation; select the memory bit cell column of memory bit cells in the memory array addressed by the write column select; and generate a read/write row select indicating the memory write operation; and select the memory bit cell row of memory bit cells in the memory array addressed by the write row select in response to the read/write row select indicating the memory write operation; and in response to a memory read operation: receive a read row select indicating a memory bit cell row (R -R) among the plurality of memory bit cell rows in the memory array corresponding to a memory read address for the memory read operation; receive a read column select indicating a memory bit cell column (C -C) among the plurality of memory bit cell columns in the memory array corresponding to the memory read address for the memory read operation; select the memory bit cell column of memory bit cells in the memory array addressed by the read column select; the memory bit cell selection circuit characterised in that it is further configured to: generate a read/write row select indicating the memory read operation in response to the memory write operation not being present for the memory read operation; and select the memory bit cell row of the memory bit cells in the memory array addressed by the read row select in response to the read/write row select indicating the memory read operation. in response to a memory write operation: receive a write row select indicating a memory bit cell row (R -R) among a plurality of memory bit cell rows in a memory array corresponding to a memory write address for the memory write operation; receive a write column select indicating a memory bit cell column (C -C) among a plurality of memory bit cell columns in the memory array corresponding to the memory write address for the memory write operation; select the memory bit cell column of memory bit cells in the memory array addressed by the write column select; and generate a read/write row select indicating the memory write operation; and select the memory bit cell row of memory bit cells in the memory array addressed by the write row select in response to the read/write row select indicating the memory write operation; and receive a write row select indicating a memory bit cell row (R -R) among a plurality of memory bit cell rows in a memory array corresponding to a memory write address for the memory write operation; receive a write column select indicating a memory bit cell column (C -C) among a plurality of memory bit cell columns in the memory array corresponding to the memory write address for the memory write operation; select the memory bit cell column of memory bit cells in the memory array addressed by the write column select; and generate a read/write row select indicating the memory write operation; and select the memory bit cell row of memory bit cells in the memory array addressed by the write row select in response to the read/write row select indicating the memory write operation; and in response to a memory read operation: receive a read row select indicating a memory bit cell row (R -R) among the plurality of memory bit cell rows in the memory array corresponding to a memory read address for the memory read operation; receive a read column select indicating a memory bit cell column (C -C) among the plurality of memory bit cell columns in the memory array corresponding to the memory read address for the memory read operation; select the memory bit cell column of memory bit cells in the memory array addressed by the read column select; the memory bit cell selection circuit characterised in that it is further configured to: receive a read row select indicating a memory bit cell row (R -R) among the plurality of memory bit cell rows in the memory array corresponding to a memory read address for the memory read operation; receive a read column select indicating a memory bit cell column (C -C) among the plurality of memory bit cell columns in the memory array corresponding to the memory read address for the memory read operation; select the memory bit cell column of memory bit cells in the memory array addressed by the read column select; the memory bit cell selection circuit characterised in that it is further configured to: generate a read/write row select indicating the memory read operation in response to the memory write operation not being present for the memory read operation; and select the memory bit cell row of the memory bit cells in the memory array addressed by the read row select in response to the read/write row select indicating the memory read operation. response to the memory write operation not being present for the memory read operation; and select the memory bit cell row of the memory bit cells in the memory array addressed by the read row select in response to the read/write row select indicating the memory read operation.