An endoscope video processor to be used with an endoscope having a CCD or CMOS imaging device, and a light source device (12, 99, 111, 135) for emitting different types of illumination light interchangeably at charge-storage time intervals of said imaging device to illuminate a site of interest, said endoscope video processor comprising: a dynamically reconfigurable processor having a reconfigurable region to be reconfigured between a first image producing circuit for processing said image signal obtained under said first illumination light to produce a first image and a second image producing circuit for processing said image signal obtained under said second illumination light to produce a second image, wherein reconfiguration of said reconfigurable region is performed in synchronization with interchange of said illumination light to process said image signals and produce differently illuminated images and a common region which applies common processing to said image signals regardless of the type of said illumination light; and a reconfiguration controller, adapted for determining the timing of said reconfiguration, wherein said dynamically reconfigurable processor comprises: a plurality of processor elements whose functions and interconnections are dynamically changeable; and a configuration memory storing multiple sets of circuit information which defines different functions and interconnections of said processor elements, wherein said reconfigurable region and the common region are configured by selecting one of said circuit information and determining the function and interconnection of said processor elements, wherein said reconfiguration controller instructs said reconfiguration during vertical blanking intervals when a vertical synchronization signal stays at zero level. a dynamically reconfigurable processor having a reconfigurable region to be reconfigured between a first image producing circuit for processing said image signal obtained under said first illumination light to produce a first image and a second image producing circuit for processing said image signal obtained under said second illumination light to produce a second image, wherein reconfiguration of said reconfigurable region is performed in synchronization with interchange of said illumination light to process said image signals and produce differently illuminated images and a common region which applies common processing to said image signals regardless of the type of said illumination light; and a reconfiguration controller, adapted for determining the timing of said reconfiguration, wherein said dynamically reconfigurable processor comprises: a plurality of processor elements whose functions and interconnections are dynamically changeable; and a configuration memory storing multiple sets of circuit information which defines different functions and interconnections of said processor elements, wherein said reconfigurable region and the common region are configured by selecting one of said circuit information and determining the function and interconnection of said processor elements, wherein said reconfiguration controller instructs said reconfiguration during vertical blanking intervals when a vertical synchronization signal stays at zero level. a plurality of processor elements whose functions and interconnections are dynamically changeable; and a configuration memory storing multiple sets of circuit information which defines different functions and interconnections of said processor elements, wherein said reconfigurable region and the common region are configured by selecting one of said circuit information and determining the function and interconnection of said processor elements, wherein said reconfiguration controller instructs said reconfiguration during vertical blanking intervals when a vertical synchronization signal stays at zero level.