A HVPMOS switched capacitor charge pump, comprising: - a charge stage for charging a first capacitive means (C FLY) and a pump stage for charging a second capacitive means (C CP), said pump stage coupled to said charge stage for transferring a charge of said first capacitive means to said second capacitive means, thereby raising the voltage potential of said second capacitive means to above the voltage potential of said first capacitive means, characterized in that a HVPMOS transistor of said charge stage is coupled between a first input of said charge stage and a first terminal of said first capacitive means (C FLY, 27), and where a HVPMOS transistor of said pump stage is coupled between said first terminal of said first capacitive means and a first terminal of said second capacitive means (C CP, 28); - bulk switch circuits (22a, 22b, 24a, 24b) for synchronously switching the bulk of said HVPMOS transistors of said charge stage and said pump stage to the higher voltage node of said HVPMOS transistors, where said higher voltage node is a source of said HVPMOS transistors when switched on, or a drain of said HVPMOS transistors when switched off, said bulk switch circuit comprising two serially coupled minimum HVPMOS transistors (29a; 29b), each said minimum HVPMOS transistor having their drains coupled together, and where a bulk terminal of each of said minimum HVPMOS transistors is coupled to its respective source, where said minimum HVPMOS transistors are smaller sized transistors than said HVPMOS transistors of said charge and pump stage, where a first of said bulk switch circuits is coupled in parallel to a drain and a bulk terminal of said HVPMOS transistor of said charge stage, where a second of said bulk switch circuits is coupled in parallel to said bulk terminal and a source of said HVPMOS transistor of said charge stage, where a third of said bulk switch circuits is coupled in parallel to a drain and a bulk terminal of said HVPMOS transistor of said pump stage; and where a fourth of said bulk switch circuits is coupled in parallel to said bulk terminal and a source of said HVPMOS transistor of said pump stage. - a charge stage for charging a first capacitive means (C FLY) and a pump stage for charging a second capacitive means (C CP), said pump stage coupled to said charge stage for transferring a charge of said first capacitive means to said second capacitive means, thereby raising the voltage potential of said second capacitive means to above the voltage potential of said first capacitive means, characterized in that a HVPMOS transistor of said charge stage is coupled between a first input of said charge stage and a first terminal of said first capacitive means (C FLY, 27), and where a HVPMOS transistor of said pump stage is coupled between said first terminal of said first capacitive means and a first terminal of said second capacitive means (C CP, 28); - bulk switch circuits (22a, 22b, 24a, 24b) for synchronously switching the bulk of said HVPMOS transistors of said charge stage and said pump stage to the higher voltage node of said HVPMOS transistors, where said higher voltage node is a source of said HVPMOS transistors when switched on, or a drain of said HVPMOS transistors when switched off, said bulk switch circuit comprising two serially coupled minimum HVPMOS transistors (29a; 29b), each said minimum HVPMOS transistor having their drains coupled together, and where a bulk terminal of each of said minimum HVPMOS transistors is coupled to its respective source,