A vertical insulated gate field-effect transistor semiconductor device comprising an array of cells formed in a die of semiconductor material presenting a first face and a second face opposite to said first face, with first and second superposed drain layers (8, 10) of a first conductivity type, said array including edge cells at the edges of said array, the first drain layer extending from said second face, and the second drain layer having a less high dopant density than said first drain layer and extending to said first face, each of said cells comprising: a source region of said first conductivity type extending from said first face; a base region of a second conductivity type, opposite to the first conductivity type surrounding said source region at and below said first face, said base region forming with said source region and drain layers (8, 10) respectively a base-source junction and a base-drain junction both extending to said first face so as to define respective junction perimeters (16, 18) thereat; and a gate electrode insulated from said die by an insulating layer and extending at said first face over at least part of said perimeters (16, 18) of said base-source junction and said base-drain junction at said first face, whereby to form a conductive channel in an on-state of the device in said base region between said source region and said drain layers (8, 10) in response to a gate voltage applied to said gate electrode, said second drain layer including peripheral regions of said first conductivity type extending beside respective perimeters of said base-drain Junctions, said peripheral regions being of higher dopant density than the rest of the second drain layer so as to present to a source-drain current a higher conductivity path extending beside said perimeters of said base-drain junctions; said gate electrodes of said edge cells extending beyond at least part of said perimeters (16, 18) of said base-source junction and said base-drain junction at said first face towards the adjacent edge of the die: said second drain layer in each of said edge cells including a region of said first conductivity type, said region being of lighter dopant density than the rest of the second drain layer, wherein said region extends beyond said gate electrode to the adjacent edge of the die; wherein intermediate regions in said second drain layer present a lighter dopant density than the rest of the second drain layer, said intermediate regions being adjacent said first face, at least in the vicinity of said peripheral region. a source region of said first conductivity type extending from said first face; a base region of a second conductivity type, opposite to the first conductivity type surrounding said source region at and below said first face, said base region forming with said source region and drain layers (8, 10) respectively a base-source junction and a base-drain junction both extending to said first face so as to define respective junction perimeters (16, 18) thereat; and a gate electrode insulated from said die by an insulating layer and extending at said first face over at least part of said perimeters (16, 18) of said base-source junction and said base-drain junction at said first face, whereby to form a conductive channel in an on-state of the device in said base region between said source region and said drain layers (8, 10) in response to a gate voltage applied to said gate electrode,