A thin film transistor array substrate for a display panel comprising: a plurality of fan-out areas located in a non-display area of the thin film transistor array substrate, wherein a display area of the thin film transistor array substrate has a plurality of sub display areas corresponding to the fan-out areas respectively, and the sub display areas and the fan-out areas are arranged opposite each other; a plurality of scanning lines extending along a first direction; a data line combination comprising a plurality of data lines (201, 202, 203, 204, 205) extending along a second direction, wherein the first direction and the second direction are orthogonal to each other; a common line combination comprising a plurality of common lines, each common line crossing with a data line (201, 202, 203, 204, 205), wherein a parasitic capacitor (307, 308, 309) is formed for each data line on each overlapping area of the data line with the common lines which cross the data line; and a connecting line combination comprising a plurality of connecting lines (206, 207, 208, 209, 210) located in one of the fan-out areas and connected to the data lines (201, 202, 203, 204, 205); wherein a resistance of each connecting line is gradually increased from the middle area of the fan-out area to two sides of the fan-out area; wherein the connecting line located in the middle area of the fan-out area connects to the data line located in a middle area of the corresponding sub display area, and the connecting lines located at the two sides of the fan-out area connect to the data lines located at the two sides of the corresponding sub display area; wherein a capacitance value of the parasitic capacitor formed between the data line connected to the connecting line with a larger resistance value and the common lines is less than that of the parasitic capacitor formed between the data line connected to the connecting line with a smaller resistance value and the common lines; wherein a capacitance value of the parasitic capacitors (307, 308, 309) formed from the data line combination and the common line combination is reduced from the middle area of the sub display area to two sides of the sub display area. a plurality of fan-out areas located in a non-display area of the thin film transistor array substrate, wherein a display area of the thin film transistor array substrate has a plurality of sub display areas corresponding to the fan-out areas respectively, and the sub display areas and the fan-out areas are arranged opposite each other; a plurality of scanning lines extending along a first direction; a data line combination comprising a plurality of data lines (201, 202, 203, 204, 205) extending along a second direction, wherein the first direction and the second direction are orthogonal to each other; a common line combination comprising a plurality of common lines, each common line crossing with a data line (201, 202, 203, 204, 205), wherein a parasitic capacitor (307, 308, 309) is formed for each data line on each overlapping area of the data line with the common lines which cross the data line; and a connecting line combination comprising a plurality of connecting lines (206, 207, 208, 209, 210) located in one of the fan-out areas and connected to the data lines (201, 202, 203, 204, 205); wherein a resistance of each connecting line is gradually increased from the middle area of the fan-out area to two sides of the fan-out area; wherein the connecting line located in the middle area of the fan-out area connects to the data line located in a middle area of the corresponding sub display area, and the connecting lines located at the two sides of the fan-out area connect to the data lines located at the two sides of the corresponding sub display area; wherein a capacitance value of the parasitic capacitor formed between the data line connected to the connecting line with a larger resistance value and the common lines is less than that of the parasitic capacitor formed between the data line connected to the connecting line with a smaller resistance value and the common lines; wherein a capacitance value of the parasitic capacitors (307, 308, 309) formed from the data line combination and the common line combination is reduced from the middle area of the sub display area to two sides of the sub display area.