An integrated circuit structure, comprising: a plurality of single crystalline silicon fins (102, 152, 202), the fins having a lower fin portion (102A, 152A, 202A, 214A, 305) that is phosphorous-doped and an upper fin portion (102B, 152B, 202B, 214B, 304) and a shoulder feature at a region between the lower fin portion (102A, 152A, 202A, 214A, 305) and the upper fin portion (102B, 152B, 202B, 214B, 304), wherein the lower fin portion (102A, 152A, 202A, 214A, 305) is narrower than the upper fin portion (102B, 152B, 202B, 214B, 304); a solid state dopant source layer (120, 216, 220, 390) being a phosphosilicate glass, PSG, the layer comprising the PSG directly on sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of a first fin of the plurality of fins (102, 152, 202) and directly on sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of a second fin of the plurality of fins (102, 152, 202), the layer comprising the PSG having a first end portion substantially co-planar with the shoulder feature of the first fin, and the layer comprising the PSG having a second end portion substantially co-planar with the shoulder feature of the second fin, wherein the dopant source layer (120, 216, 220, 390) is used to dope the lower fin portions (102A, 152A, 202A, 214A, 305); an insulating capping layer (122, 218, 222, 392), which is a nitride layer and which is directly on the layer being the PSG (120, 216, 220, 390) directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the first fin and directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the second fin; a dielectric fill material directly laterally adjacent to the insulating layer (122, 218, 222, 392) directly on the layer being the PSG directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the first fin and directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the second fin, the dielectric fill material is recessed to a height approximately the same as the height of the lower fin portions (102A, 152A, 202A, 214A, 305); and a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion (102B, 152B, 202B, 214B, 304) of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion (102B, 152B, 202B, 214B, 304) of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin. a plurality of single crystalline silicon fins (102, 152, 202), the fins having a lower fin portion (102A, 152A, 202A, 214A, 305) that is phosphorous-doped and an upper fin portion (102B, 152B, 202B, 214B, 304) and a shoulder feature at a region between the lower fin portion (102A, 152A, 202A, 214A, 305) and the upper fin portion (102B, 152B, 202B, 214B, 304), wherein the lower fin portion (102A, 152A, 202A, 214A, 305) is narrower than the upper fin portion (102B, 152B, 202B, 214B, 304); a solid state dopant source layer (120, 216, 220, 390) being a phosphosilicate glass, PSG, the layer comprising the PSG directly on sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of a first fin of the plurality of fins (102, 152, 202) and directly on sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of a second fin of the plurality of fins (102, 152, 202), the layer comprising the PSG having a first end portion substantially co-planar with the shoulder feature of the first fin, and the layer comprising the PSG having a second end portion substantially co-planar with the shoulder feature of the second fin, wherein the dopant source layer (120, 216, 220, 390) is used to dope the lower fin portions (102A, 152A, 202A, 214A, 305); an insulating capping layer (122, 218, 222, 392), which is a nitride layer and which is directly on the layer being the PSG (120, 216, 220, 390) directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the first fin and directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the second fin; a dielectric fill material directly laterally adjacent to the insulating layer (122, 218, 222, 392) directly on the layer being the PSG directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the first fin and directly on the sidewalls of the lower fin portion (102A, 152A, 202A, 214A, 305) of the second fin, the dielectric fill material is recessed to a height approximately the same as the height of the lower fin portions (102A, 152A, 202A, 214A, 305); and a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion (102B, 152B, 202B, 214B, 304) of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion (102B, 152B, 202B, 214B, 304) of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin.