Memory device comprising at least one local column of memory cells, each local column comprising: complementary local bit lines (LWBL, LWBLb) between which a plurality of said memory cells are connected, each cell being connected to a word line for addressing the cell; a local write receiver via which said complementary local bit lines are connectable to complementary global bit lines (GWBL, GWBLb); and a timing signal generator provided for generating a pulsed signal as local column write enable signal; the local write receiver comprising: a connection mechanism provided for connecting said complementary local bit lines to said complementary global bit lines and thereby passing on said reduced voltage swing, the connection mechanism comprising access transistors, the gates of the access transistors being connected to a local column write enable line (WL_WR) for receiving a local column write enable signal from said timing signal generator; and a pair of cross-coupled inverters; characterised in that the local write receiver is configured for creating a full voltage swing on said complementary local bit lines from a reduced voltage swing on said complementary global bit lines; and in that the pair of cross-coupled inverters is directly connected to said complementary local bit lines and provided for converting said reduced voltage swing, passed on by said connection mechanism, to said full voltage swing on said complementary local bit lines; wherein said cross-coupled inverters of said local write receiver have connections to left and right ground rails (VSSL, VSSR) for receiving left and right VSS biases; and wherein the memory device further comprises a VSS biasing circuit configured for applying said left and right VSS biases to said left and right ground rails (VSSL, VSSR), wherein the VSS biasing circuit is provided for establishing a predetermined, data dependent voltage difference between the left and right VSS biases. complementary local bit lines (LWBL, LWBLb) between which a plurality of said memory cells are connected, each cell being connected to a word line for addressing the cell; a local write receiver via which said complementary local bit lines are connectable to complementary global bit lines (GWBL, GWBLb); and a timing signal generator provided for generating a pulsed signal as local column write enable signal; a connection mechanism provided for connecting said complementary local bit lines to said complementary global bit lines and thereby passing on said reduced voltage swing, the connection mechanism comprising access transistors, the gates of the access transistors being connected to a local column write enable line (WL_WR) for receiving a local column write enable signal from said timing signal generator; and a pair of cross-coupled inverters; characterised in that the local write receiver is configured for creating a full voltage swing on said complementary local bit lines from a reduced voltage swing on said complementary global bit lines; and in that the pair of cross-coupled inverters is directly connected to said complementary local bit lines and provided for converting said reduced voltage swing, passed on by said connection mechanism, to said full voltage swing on said complementary local bit lines; wherein said cross-coupled inverters of said local write receiver have connections to left and right ground rails (VSSL, VSSR) for receiving left and right VSS biases; and wherein the memory device further comprises a VSS biasing circuit configured for applying said left and right VSS biases to said left and right ground rails (VSSL, VSSR), wherein the VSS biasing circuit is provided for establishing a predetermined, data dependent voltage difference between the left and right VSS biases.