A microprocessor having architectural condition flags, wherein the microprocessor performs a set of ALU architectural instructions that instruct the microprocessor to perform a shift operation on a first source operand to generate a first result, to perform a second operation on the first result and a second operand to generate a second result, and to write the second result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, and wherein a first subset of the architectural instructions require an architectural carry flag to be updated by the ALU operation, and a second subset of the architectural instructions require the architectural carry flag to be updated by the shift operation, the microprocessor comprising: a hardware instruction translator, that receives an instruction from the set of architectural instructions and responsively translates it into at least first and second microinstructions, wherein the second microinstruction is an ALU microinstruction; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the shift operation on the first source operand to generate the first result; and generates a carry value, if the instruction belongs to the second subset; wherein in response to the second microinstruction, the execution pipeline performs the following actions on the basis of the values of the architectural flags existing prior to execution of the first microinstruction: writes the destination register with the second result, if the architectural condition flag values satisfy the condition; and writes the destination register with the current value of the destination register, if the architectural condition flag values do not satisfy the condition; wherein in response to the microinstructions, the execution pipeline also: updates the architectural condition flags with the carry value generated by the first microinstruction, if the instruction belongs to the second subset and the architectural condition flag values satisfy the condition; and updates the architectural condition flags with a value generated by the second microinstruction, if the instruction belongs to the first subset and the architectural condition flag values satisfy the condition. a hardware instruction translator, that receives an instruction from the set of architectural instructions and responsively translates it into at least first and second microinstructions, wherein the second microinstruction is an ALU microinstruction; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the shift operation on the first source operand to generate the first result; and generates a carry value, if the instruction belongs to the second subset; wherein in response to the second microinstruction, the execution pipeline performs the following actions on the basis of the values of the architectural flags existing prior to execution of the first microinstruction: performs the shift operation on the first source operand to generate the first result; and generates a carry value, if the instruction belongs to the second subset; wherein in response to the second microinstruction, the execution pipeline performs the following actions on the basis of the values of the architectural flags existing prior to execution of the first microinstruction: writes the destination register with the second result, if the architectural condition flag values satisfy the condition; and writes the destination register with the current value of the destination register, if the architectural condition flag values do not satisfy the condition; wherein in response to the microinstructions, the execution pipeline also: updates the architectural condition flags with the carry value generated by the first microinstruction, if the instruction belongs to the second subset and the architectural condition flag values satisfy the condition; and updates the architectural condition flags with a value generated by the second microinstruction, if the instruction belongs to the first subset and the architectural condition flag values satisfy the condition. updates the architectural condition flags with the carry value generated by the first microinstruction, if the instruction belongs to the second subset and the architectural condition flag values satisfy the condition; and updates the architectural condition flags with a value generated by the second microinstruction, if the instruction belongs to the first subset and the architectural condition flag values satisfy the condition.