A microprocessor capable of running both x86 instruction set architecture, ISA, machine language programs and Advanced RISC Machines, ARM, ISA machine language programs, the microprocessor comprising: a mode indicator, that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program; a plurality of non-ISA-specific model-specific registers, MSRs,, arranged to configure and control global operational characteristics of the microprocessor that are non-specific to the x86 ISA and to the ARM ISA; a hardware instruction translator; and an execution pipeline; wherein the microprocessor is arranged such that: when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR; and when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR; wherein the hardware instruction translator includes a complex instruction translator arranged to translate the x86 ISA RDMSR/WRMSR instruction into a first sequence of microinstructions to access the addressed MSR, and to translate the ARM ISA MRRC/MCRR instruction into a second sequence of microinstructions to access the addressed MSR, wherein the microinstructions are defined by a microinstruction set of the microprocessor distinct from the x86 ISA and the ARM ISA; and wherein the execution pipeline executes the first sequence of microinstructions to perform the x86 ISA RDMSR/WRMSR instruction, and executes the second sequence of microinstructions to perform the ARM ISA MRRC/MCRR instruction. a mode indicator, that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program; a plurality of non-ISA-specific model-specific registers, MSRs,, arranged to configure and control global operational characteristics of the microprocessor that are non-specific to the x86 ISA and to the ARM ISA; a hardware instruction translator; and an execution pipeline; wherein the microprocessor is arranged such that: when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR; and when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR; wherein the hardware instruction translator includes a complex instruction translator arranged to translate the x86 ISA RDMSR/WRMSR instruction into a first sequence of microinstructions to access the addressed MSR, and to translate the ARM ISA MRRC/MCRR instruction into a second sequence of microinstructions to access the addressed MSR, wherein the microinstructions are defined by a microinstruction set of the microprocessor distinct from the x86 ISA and the ARM ISA; and when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR; and when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR; wherein the hardware instruction translator includes a complex instruction translator arranged to translate the x86 ISA RDMSR/WRMSR instruction into a first sequence of microinstructions to access the addressed MSR, and to translate the ARM ISA MRRC/MCRR instruction into a second sequence of microinstructions to access the addressed MSR, wherein the microinstructions are defined by a microinstruction set of the microprocessor distinct from the x86 ISA and the ARM ISA; and wherein the execution pipeline executes the first sequence of microinstructions to perform the x86 ISA RDMSR/WRMSR instruction, and executes the second sequence of microinstructions to perform the ARM ISA MRRC/MCRR instruction.