A synchronous buck converter device having pulse frequency modulation at low load, wherein when a current load of the synchronous buck converter device is above a predetermined limit, the synchronous buck converter device is arranged to function in continuous current mode with a fixed frequency, wherein the frequency is fixed using a circuit configured to set a minimum off-time, wherein the minimum off-time is proportional to 1-D, wherein D is a duty cycle, wherein the circuit is configured to create a threshold voltage proportional to a difference between a power supply voltage (Vdd) and a reference voltage (Vref), characterized in that said circuit is comprising: - a comparator providing an output signal of the minimum off-time wherein a first input of the comparator receives the threshold voltage (Vdd-Vref) from a first p-channel MOSFET; - a first amplifier, wherein a negative input terminal of the first amplifier receives the reference voltage (VREF) and a positive input of the first amplifier is electrically connected to a second terminal of a first resistor and to a source of said first p-channel MOSFET; - said first p-channel MOSFET, configured to provide the threshold voltage at its drain, wherein the gate of the p-channel MOSFET is connected to an output of said first amplifier, the drain of the p-channel MOSFET is connected to a second terminal of a second resistor and the source voltage of the MOSFET is a replica of the reference voltage (VREF); - said first resistor, wherein a first terminal of the first resistor is connected to the supply voltage and the second terminal of the first resistor is connected to the source of the first p-channel MOSFET; - said second resistor, wherein a first terminal of the second resistor is connected to ground; - a second amplifier, wherein a first input of the second amplifier is connected to a midpoint of a voltage divider comprising a third resistor and a fourth resistor, a second input of the second amplifier is connected to the source of a second p-channel MOSFET, wherein the second amplifier is configured to create a replica of the midpoint voltage of the voltage divider (153, 154) at the source of the second p-channel MOSFET; - said voltage divider (153, 154) connected between the supply voltage voltage and ground, wherein the voltage at the midpoint of the voltage divider is proportional to the supply voltage voltage; - a fifth resistor, wherein a first terminal of the fifth resistor is connected to the supply voltage; - said second p-channel MOSFET, wherein the gate of the second p-channel MOSFET is connected to the output of said second amplifier, the source of the second p-channel MOSFET is connected to a second terminal of the fifth resistor and to a second input of said second amplifier and the drain of the second p-channel MOSFET is connected to a first terminal of a capacitor and to a second input of said comparator, wherein the current through said fifth resistor is proportional to the supply voltage; and - said capacitor. - a comparator providing an output signal of the minimum off-time wherein a first input of the comparator receives the threshold voltage (Vdd-Vref) from a first p-channel MOSFET; - a first amplifier, wherein a negative input terminal of the first amplifier receives the reference voltage (VREF) and a positive input of the first amplifier is electrically connected to a second terminal of a first resistor and to a source of said first p-channel MOSFET; - said first p-channel MOSFET, configured to provide the threshold voltage at its drain, wherein the gate of the p-channel MOSFET is connected to an output of said first amplifier, the drain of the p-channel MOSFET is connected to a second terminal of a second resistor and the source voltage of the MOSFET is a replica of the reference voltage (VREF); - said first resistor, wherein a first terminal of the first resistor is connected to the supply voltage and the second terminal of the first resistor is connected to the source of the first p-channel MOSFET; - said second resistor, wherein a first terminal of the second resistor is connected to ground; - a second amplifier, wherein a first input of the second amplifier is connected to a midpoint of a voltage divider comprising a third resistor and a fourth resistor, a second input of the second amplifier is connected to the source of a second p-channel MOSFET, wherein the second amplifier is configured to create a replica of the midpoint voltage of the voltage divider (153, 154) at the source of the second p-channel MOSFET; - said voltage divider (153, 154) connected between the supply voltage voltage and ground, wherein the voltage at the midpoint of the voltage divider is proportional to the supply voltage voltage; - a fifth resistor, wherein a first terminal of the fifth resistor is connected to the supply voltage; - said second p-channel MOSFET, wherein the gate of the second p-channel MOSFET is connected to the output of said second amplifier, the source of the second p-channel MOSFET is connected to a second terminal of the fifth resistor and to a second input of said second amplifier and the drain of the second p-channel MOSFET is connected to a first terminal of a capacitor and to a second input of said comparator, wherein the current through said fifth resistor is proportional to the supply voltage; and - said capacitor.