A microprocessor for connection to a voltage regulator module adapted to transition from operating at a current frequency to a new frequency in a performance-optimizing manner, comprising: core logic, configured to operate according to a core clock signal in order to execute program instructions; clock generation circuitry, controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, comprising: first and second phase-locked loops, PLLs, (112A, 112B) each controllable to generate a clock signal having one of N different possible frequencies; and a selection circuit controllable to select one of the PLLs (112A, 112B) to provide its clock signal to the core logic as the core clock signal, such that the selected PLL is the online PLL and the non-selected PLL is the offline PLL; and characterised in that it furthermore comprises a control circuit, coupled to the clock generation circuitry, comprising operating point data that specifies voltage/frequency combinations at which the core logic may reliably operate, and configured to control, in response to a request to operate the core logic at the new higher frequency, the voltage regulator module to output one of a plurality of possible voltages, wherein the control circuit is further configured to: (a) request the voltage regulator module to raise the output to the next higher one of the plurality of possible voltages; (b) make a determination whether the next higher one of the plurality of possible frequencies than the current core clock signal frequency is a frequency at which the core logic may reliably operate at the next higher voltage based on the operating point data; (c) if the determination is true: (i) control the offline PLL to lock in to the next higher frequency, and (ii) after the output has reached the next higher voltage and the offline PLL has locked in to the next higher frequency, control the selection circuit to select the offline PLL to become the online PLL; and otherwise, wait for the output to reach the next higher voltage; and wherein the control circuit is arranged to perform actions (a), (b), and (c) between two and N-1 times during the transition to the new frequency, without suspending operation of the core logic. core logic, configured to operate according to a core clock signal in order to execute program instructions; clock generation circuitry, controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, comprising: first and second phase-locked loops, PLLs, (112A, 112B) each controllable to generate a clock signal having one of N different possible frequencies; and a selection circuit controllable to select one of the PLLs (112A, 112B) to provide its clock signal to the core logic as the core clock signal, such that the selected PLL is the online PLL and the non-selected PLL is the offline PLL; and characterised in that it furthermore comprises a control circuit, coupled to the clock generation circuitry, comprising operating point data that specifies voltage/frequency combinations at which the core logic may reliably operate, and configured to control, in response to a request to operate the core logic at the new higher frequency, the voltage regulator module to output one of a plurality of possible voltages, wherein the control circuit is further configured to: (a) request the voltage regulator module to raise the output to the next higher one of the plurality of possible voltages; (b) make a determination whether the next higher one of the plurality of possible frequencies than the current core clock signal frequency is a frequency at which the core logic may reliably operate at the next higher voltage based on the operating point data; (c) if the determination is true: (i) control the offline PLL to lock in to the next higher frequency, and (ii) after the output has reached the next higher voltage and the offline PLL has locked in to the next higher frequency, control the selection circuit to select the offline PLL to become the online PLL; and otherwise, wait for the output to reach the next higher voltage; and first and second phase-locked loops, PLLs, (112A, 112B) each controllable to generate a clock signal having one of N different possible frequencies; and a selection circuit controllable to select one of the PLLs (112A, 112B) to provide its clock signal to the core logic as the core clock signal, such that the selected PLL is the online PLL and the non-selected PLL is the offline PLL; and (a) request the voltage regulator module to raise the output to the next higher one of the plurality of possible voltages; (b) make a determination whether the next higher one of the plurality of possible frequencies than the current core clock signal frequency is a frequency at which the core logic may reliably operate at the next higher voltage based on the operating point data; (c) if the determination is true: (i) control the offline PLL to lock in to the next higher frequency, and (ii) after the output has reached the next higher voltage and the offline PLL has locked in to the next higher frequency, control the selection circuit to select the offline PLL to become the online PLL; and otherwise, wait for the output to reach the next higher voltage; and (i) control the offline PLL to lock in to the next higher frequency, and (ii) after the output has reached the next higher voltage and the offline PLL has locked in to the next higher frequency, control the selection circuit to select the offline PLL to become the online PLL; and