An electronic circuit device (50; 60) comprising: a negative resistance circuit that has a first transistor (10; 10a) having a control terminal (G1; B1) coupled to a resonator, a first terminal (D1, CC1) and a second terminal (S1, E1) and a negative resistance generator which comprises a first capacitor coupled between the second terminal (S1, E1) of the first transistor (10; 10a) and ground, and a first inductor and a first resistor coupled between the second terminal (S1, E1) of the first transistor (10; 10a) and ground in parallel with the first capacitor; a second transistor (20; 20a) that has a control terminal (G2; B2) coupled to the first terminal (D1; CC1) of the first transistor (10; 10a), a first terminal (D2; CC2) coupled to a DC bias terminal and a second terminal (S2, E2) coupled to ground through a further capacitor; and a path that is coupled between the DC bias terminal and the first terminal (D1; CC1) of the first transistor (10; 10a) through the second transistor (20; 20a) and provides a bias to the first transistor (10; 10a), wherein the electronic circuit device (50; 60) further comprises: a node which is coupled between the first terminal (D1, CC1) of the first transistor (10, 10a), the control terminal (G2, B2) of the second transistor (20, 20a) and the second terminal (S2, E2) of the second transistor (20, 20a), a second inductor provided between the first terminal (D1; CC1) of the first transistor (10; 10a) and the node, a third inductor provided between the node and the second terminal (S2; E2) of the second transistor (20; 20a), and a second resistor is provided between the third inductor and the second terminal (S2; E2) of the second transistor (20; 20a). a negative resistance circuit that has a first transistor (10; 10a) having a control terminal (G1; B1) coupled to a resonator, a first terminal (D1, CC1) and a second terminal (S1, E1) and a first transistor (10; 10a) having a control terminal (G1; B1) coupled to a resonator, a first terminal (D1, CC1) and a second terminal (S1, E1) and a negative resistance generator which comprises a first capacitor coupled between the second terminal (S1, E1) of the first transistor (10; 10a) and ground, and a first inductor and a first resistor coupled between the second terminal (S1, E1) of the first transistor (10; 10a) and ground in parallel with the first capacitor; a second transistor (20; 20a) that has a control terminal (G2; B2) coupled to the first terminal (D1; CC1) of the first transistor (10; 10a), a first terminal (D2; CC2) coupled to a DC bias terminal and a second terminal (S2, E2) coupled to ground through a further capacitor; and a path that is coupled between the DC bias terminal and the first terminal (D1; CC1) of the first transistor (10; 10a) through the second transistor (20; 20a) and provides a bias to the first transistor (10; 10a), wherein the electronic circuit device (50; 60) further comprises: a node which is coupled between the first terminal (D1, CC1) of the first transistor (10, 10a), the control terminal (G2, B2) of the second transistor (20, 20a) and the second terminal (S2, E2) of the second transistor (20, 20a), a second inductor provided between the first terminal (D1; CC1) of the first transistor (10; 10a) and the node, a third inductor provided between the node and the second terminal (S2; E2) of the second transistor (20; 20a), and a second resistor is provided between the third inductor and the second terminal (S2; E2) of the second transistor (20; 20a). a node which is coupled between the first terminal (D1, CC1) of the first transistor (10, 10a), the control terminal (G2, B2) of the second transistor (20, 20a) and the second terminal (S2, E2) of the second transistor (20, 20a), a second inductor provided between the first terminal (D1; CC1) of the first transistor (10; 10a) and the node, a third inductor provided between the node and the second terminal (S2; E2) of the second transistor (20; 20a), and a second resistor is provided between the third inductor and the second terminal (S2; E2) of the second transistor (20; 20a).