A method of forming a memory device, comprising: providing a silicon substrate, wherein the substrate has a memory area, an LV area and an HV area which are insulated from each other by insulation material extending into a surface of the substrate, and wherein the substrate has a first conductivity type; forming pairs of spaced apart memory stacks on the substrate and in the memory area, wherein each memory stack includes: a floating gate disposed over and insulated from the substrate, and a control gate disposed over and insulated from the floating gate; forming a first conductive layer over and insulated from the substrate in the memory area, the LV area and the HV area, wherein the first conductive layer extends up and over the pairs of memory stacks; forming a first insulation layer on the first conductive layer in the memory area, the LV area and the HV area; removing the first insulation layer from the memory area and the HV area, while maintaining the first insulation layer in the LV area; performing a conductive material deposition to thicken the first conductive layer in the memory area and the HV area, and to form a second conductive layer on the first insulation layer in the LV area; performing an etch to thin the thickened first conductive layer in the memory area and the HV area, and to remove the second conductive layer in the LV area, wherein a top surface of the first conductive layer in the memory area and the HV area is higher than a bottom surface of the first insulation layer in the LV area; removing the first insulation layer from the LV area; and patterning the first conductive layer to form gate blocks of the first conductive layer in the memory area, the LV area and the HV area, wherein the gate blocks of the first conductive layer in the LV area have a height less than that of the gate blocks of the first conductive layer in the HV area. providing a silicon substrate, wherein the substrate has a memory area, an LV area and an HV area which are insulated from each other by insulation material extending into a surface of the substrate, and wherein the substrate has a first conductivity type; forming pairs of spaced apart memory stacks on the substrate and in the memory area, wherein each memory stack includes: a floating gate disposed over and insulated from the substrate, and a control gate disposed over and insulated from the floating gate; a floating gate disposed over and insulated from the substrate, and a control gate disposed over and insulated from the floating gate; forming a first conductive layer over and insulated from the substrate in the memory area, the LV area and the HV area, wherein the first conductive layer extends up and over the pairs of memory stacks; forming a first insulation layer on the first conductive layer in the memory area, the LV area and the HV area; removing the first insulation layer from the memory area and the HV area, while maintaining the first insulation layer in the LV area; performing a conductive material deposition to thicken the first conductive layer in the memory area and the HV area, and to form a second conductive layer on the first insulation layer in the LV area; performing an etch to thin the thickened first conductive layer in the memory area and the HV area, and to remove the second conductive layer in the LV area, wherein a top surface of the first conductive layer in the memory area and the HV area is higher than a bottom surface of the first insulation layer in the LV area; removing the first insulation layer from the LV area; and patterning the first conductive layer to form gate blocks of the first conductive layer in the memory area, the LV area and the HV area, wherein the gate blocks of the first conductive layer in the LV area have a height less than that of the gate blocks of the first conductive layer in the HV area.