A random code generator, comprising: a control circuit generating a control signal (Ctrl) and an enabling signal (En), wherein during a program cycle, the enabling signal (En) is activated; a high voltage power supply receiving the enabling signal (En), wherein the high voltage power supply generates a program voltage (Vpgm) according to an oscillation signal (Osc), wherein when the enabling signal (En) is activated, the high voltage power supply outputs the program voltage (Vpgm), wherein when the enabling signal (En) is inactivated, the high voltage power supply stops outputting the program voltage (Vpgm); a memory module receiving the control signal (Ctrl), and determining a selected one time programmable memory cell of the memory module according to the control signal (Ctrl), wherein during the program cycle, the selected one time programmable memory cell receives the program voltage (Vpgm); and a counter receiving the oscillation signal (Osc) and the enabling signal (En), wherein during the program cycle, the counter counts a pulse number of the oscillation signal (Osc) to acquire a counting value (Count), and the control circuit determines a random code according to the counting value (Count); wherein the high voltage power supply comprises: a voltage regulator comprising a charge pump, a clock signal selector and a feedback detector, wherein the charge pump generates the program voltage (Vpgm) according to the oscillation signal (Osc), the feedback detector generates a pump control signal (Pump) according to the program voltage (Vpgm), and the clock signal selector generates the oscillation signal (Osc) according to a clock signal and the pump control signal (Pump); and a power switch, wherein a first terminal of the power switch receives the program voltage (Vpgm), a second terminal of the power switch is connected with the selected one time programmable memory cell, and a control terminal of the power switch receives the enabling signal (En), wherein during the program cycle, the power switch is in a close state, and the high voltage power supply outputs the program voltage (Vpgm) to the selected one time programmable memory cell. a control circuit generating a control signal (Ctrl) and an enabling signal (En), wherein during a program cycle, the enabling signal (En) is activated; a high voltage power supply receiving the enabling signal (En), wherein the high voltage power supply generates a program voltage (Vpgm) according to an oscillation signal (Osc), wherein when the enabling signal (En) is activated, the high voltage power supply outputs the program voltage (Vpgm), wherein when the enabling signal (En) is inactivated, the high voltage power supply stops outputting the program voltage (Vpgm); a memory module receiving the control signal (Ctrl), and determining a selected one time programmable memory cell of the memory module according to the control signal (Ctrl), wherein during the program cycle, the selected one time programmable memory cell receives the program voltage (Vpgm); and a counter receiving the oscillation signal (Osc) and the enabling signal (En), wherein during the program cycle, the counter counts a pulse number of the oscillation signal (Osc) to acquire a counting value (Count), and the control circuit determines a random code according to the counting value (Count); wherein the high voltage power supply comprises: a voltage regulator comprising a charge pump, a clock signal selector and a feedback detector, wherein the charge pump generates the program voltage (Vpgm) according to the oscillation signal (Osc), the feedback detector generates a pump control signal (Pump) according to the program voltage (Vpgm), and the clock signal selector generates the oscillation signal (Osc) according to a clock signal and the pump control signal (Pump); and a power switch, wherein a first terminal of the power switch receives the program voltage (Vpgm), a second terminal of the power switch is connected with the selected one time programmable memory cell, and a control terminal of the power switch receives the enabling signal (En), wherein during the program cycle, the power switch is in a close state, and the high voltage power supply outputs the program voltage (Vpgm) to the selected one time programmable memory cell. a voltage regulator comprising a charge pump, a clock signal selector and a feedback detector, wherein the charge pump generates the program voltage (Vpgm) according to the oscillation signal (Osc), the feedback detector generates a pump control signal (Pump) according to the program voltage (Vpgm), and the clock signal selector generates the oscillation signal (Osc) according to a clock signal and the pump control signal (Pump); and a power switch, wherein a first terminal of the power switch receives the program voltage (Vpgm), a second terminal of the power switch is connected with the selected one time programmable memory cell, and a control terminal of the power switch receives the enabling signal (En), wherein during the program cycle, the power switch is in a close state, and the high voltage power supply outputs the program voltage (Vpgm) to the selected one time programmable memory cell.