A semiconductor product, comprising: a semiconductor wafer having a semiconductive substrate and a first surface and a second surface, the first and second surfaces disposed on opposite sides of the substrate, the semiconductor wafer having a thickness between the first surface and the second surface of between 2 to 50 micrometer; a carrier wafer attached to the semiconductor wafer, the first surface of the semiconductor wafer facing the carrier wafer; a laterally diffused MOS transistor having at least one doping region disposed in the semiconductive substrate adjacent to the first surface; at least one dielectric layer disposed on the first surface; at least one wiring embedded in the dielectric layer; at least one via hole formed in the substrate extending from the second surface of the semiconductive substrate and through a portion of the dielectric layer to the at least one wiring; an electrically conductive path coupled to the wiring and extending through the via hole to the second surface of the semiconductor wafer; a CMOS circuit disposed in the semiconductive substrate; at least one deep trench (146a, 146b) filled with dielectric that extends from the second surface of the semiconductor wafer to the bottom of at least one shallow trench, the at least one shallow trench extending from the first surface into the substrate filled with insulating material (101a, 101b), thereby forming a barrier between the at least one doping region of the transistor and the CMOS circuit; wherein the laterally diffused MOS transistor has a source doping region, a drain doping region, a drift region, and a gate electrode that are disposed at the first surface of the semiconductor wafer, wherein said drift region extends to said second surface; a second dielectric layer being disposed on and covering the second surface of the semiconductor wafer and a field plate being disposed on and covering the second dielectric layer, the field plate being electrically coupled to the source doping region via the at least one via hole, or to an external potential via an external connection. a semiconductor wafer having a semiconductive substrate and a first surface and a second surface, the first and second surfaces disposed on opposite sides of the substrate, the semiconductor wafer having a thickness between the first surface and the second surface of between 2 to 50 micrometer; a carrier wafer attached to the semiconductor wafer, the first surface of the semiconductor wafer facing the carrier wafer; a laterally diffused MOS transistor having at least one doping region disposed in the semiconductive substrate adjacent to the first surface; at least one dielectric layer disposed on the first surface; at least one wiring embedded in the dielectric layer; at least one via hole formed in the substrate extending from the second surface of the semiconductive substrate and through a portion of the dielectric layer to the at least one wiring; an electrically conductive path coupled to the wiring and extending through the via hole to the second surface of the semiconductor wafer; a CMOS circuit disposed in the semiconductive substrate; at least one deep trench (146a, 146b) filled with dielectric that extends from the second surface of the semiconductor wafer to the bottom of at least one shallow trench, the at least one shallow trench extending from the first surface into the substrate filled with insulating material (101a, 101b), thereby forming a barrier between the at least one doping region of the transistor and the CMOS circuit; wherein the laterally diffused MOS transistor has a source doping region, a drain doping region, a drift region, and a gate electrode that are disposed at the first surface of the semiconductor wafer, wherein said drift region extends to said second surface; a second dielectric layer being disposed on and covering the second surface of the semiconductor wafer and a field plate being disposed on and covering the second dielectric layer, the field plate being electrically coupled to the source doping region via the at least one via hole, or to an external potential via an external connection.