A method for manufacturing display device, comprising forming a p-type thin film transistor (TFT (pD)) and an n-type thin film transistor (TFT (nD)) on a substrate, wherein the forming of the p-type thin film transistor (TFT (pD)) and the n-type thin film transistor (TFT (nD)) each include: forming a gate electrode (GT, GT'); forming a drain electrode (DT, DT') of any one material selected from a group consisting of aluminium, gallium, indium, and thallium as main material; forming a source electrode (ST, ST') of any one material selected from a group consisting of aluminium, gallium, indium, and thallium as main material; forming an insulating film; and forming a semiconductor layer (SC, SC'; PS; AS) formed on a top surface of the gate electrode (GT, GT') through the insulating film, wherein the drain electrode (DT, DT') and the source electrode (ST, ST') are formed so as to be opposed to each other with a clearance formed therebetween on a top surface of the semiconductor layer (SC, SC'; PS; AS); the drain electrode (DT') and the source electrode (ST') of the n-type thin film transistor (TFT (nD)) are formed in the same layer and are made of the same material as the drain electrode and the source electrode of the p-type thin film transistor (TFT (pD)); wherein the p-type thin film transistor (TFT (pD)) is formed to further include a diffusion layer at an interface between the drain electrode and the semiconductor layer (SC; PS; AS) and at an interface between the source electrode and the semiconductor layer (SC; PS; AS), the diffusion layer containing p-type impurities out of the main material of the drain electrode and the source electrode; wherein the n-type thin film transistor (TFT (nD)) is formed to further include a contact layer made of semiconductor, which is located between the drain electrode (DT') and the semiconductor layer (SC'; AS) as well as between the source electrode (ST') and the semiconductor layer (SC'; AS), wherein the contact layer is doped with n-type impurities; and wherein the diffusion layers of the p-type thin film transistor (TFT (pD)) are formed through annealing, so that said material of the drain electrode and said material of the source electrode of the of the p-type thin film transistor (TFT (pD)) are diffused into the semiconductor layer (SC;PS;AS) to form said diffusion layers at each of the interface between the drain electrode and the semiconductor layer (SC,PS;AS) and the interface between the source electrode and the semiconductor layer (SC;PS;AS). forming a gate electrode (GT, GT'); forming a drain electrode (DT, DT') of any one material selected from a group consisting of aluminium, gallium, indium, and thallium as main material; forming a source electrode (ST, ST') of any one material selected from a group consisting of aluminium, gallium, indium, and thallium as main material; forming an insulating film; and forming a semiconductor layer (SC, SC'; PS; AS) formed on a top surface of the gate electrode (GT, GT') through the insulating film, wherein the drain electrode (DT, DT') and the source electrode (ST, ST') are formed so as to be opposed to each other with a clearance formed therebetween on a top surface of the semiconductor layer (SC, SC'; PS; AS); the drain electrode (DT') and the source electrode (ST') of the n-type thin film transistor (TFT (nD)) are formed in the same layer and are made of the same material as the drain electrode and the source electrode of the p-type thin film transistor (TFT (pD)); wherein the p-type thin film transistor (TFT (pD)) is formed to further include a diffusion layer at an interface between the drain electrode and the semiconductor layer (SC; PS; AS) and at an interface between the source electrode and the semiconductor layer (SC; PS; AS), the diffusion layer containing p-type impurities out of the main material of the drain electrode and the source electrode; wherein the n-type thin film transistor (TFT (nD)) is formed to further include a contact layer made of semiconductor, which is located between the drain electrode (DT') and the semiconductor layer (SC'; AS) as well as between the source electrode (ST') and the semiconductor layer (SC'; AS), wherein the contact layer is doped with n-type impurities; and wherein the diffusion layers of the p-type thin film transistor (TFT (pD)) are formed through annealing, so that said material of the drain electrode and said material of the source electrode of the of the p-type thin film transistor (TFT (pD)) are diffused into the semiconductor layer (SC;PS;AS) to form said diffusion layers at each of the interface between the drain electrode and the semiconductor layer (SC,PS;AS) and the interface between the source electrode and the semiconductor layer (SC;PS;AS).