A display device comprising: a substrate having an insulating surface; a first gate electrode (104; 471 a, b; 401; 451a, b) and a first electrode formed on the insulating surface of the substrate; a gate insulating layer (105a, b; 472a, b; 402a, b; 452a, b) formed over the first gate electrode and over the first electrode; a first crystalline semiconductor layer (405; 903; 473a, b; 423) formed on the gate insulating layer above the first gate electrode; a first semiconductor layer (406a; 408a) having one conductivity type formed on the crystalline semiconductor layer to contact the crystalline semiconductor; a second semiconductor layer (406b; 408b) having one conductivity type formed on the first semiconductor layer to contact the first semiconductor layer; a first source electrode (112, 113, 114, 115; 208a-d; 218a-d; 482a-d; 425a, b; 462a-d) and a first drain electrode (112, 113, 114, 115; 208a-d; 218a-d; 482a-d; 425a, b; 462a-d) formed on the second semiconductor layer; a first insulating layer (116, 140) formed over the first source electrode, the first drain electrode, and the first electrode; a first opening formed in the first insulating layer (116, 140) to reach the first source electrode or the first drain electrode; a second opening formed in the gate insulating layer and the first insulating layer (116, 140) to reach the first electrode; and a wiring layer formed in the first opening and the second opening to electrically connect the first source electrode or the first drain electrode to the first electrode, wherein the first gate electrode (104; 471a, b; 401; 451a, b) and the first electrode are formed of the same material and in the same plane, and wherein the first electrode (120; 304; 304a, 304b) is a pixel electrode. a substrate having an insulating surface; a first gate electrode (104; 471 a, b; 401; 451a, b) and a first electrode formed on the insulating surface of the substrate; a gate insulating layer (105a, b; 472a, b; 402a, b; 452a, b) formed over the first gate electrode and over the first electrode; a first crystalline semiconductor layer (405; 903; 473a, b; 423) formed on the gate insulating layer above the first gate electrode; a first semiconductor layer (406a; 408a) having one conductivity type formed on the crystalline semiconductor layer to contact the crystalline semiconductor; a second semiconductor layer (406b; 408b) having one conductivity type formed on the first semiconductor layer to contact the first semiconductor layer; a first source electrode (112, 113, 114, 115; 208a-d; 218a-d; 482a-d; 425a, b; 462a-d) and a first drain electrode (112, 113, 114, 115; 208a-d; 218a-d; 482a-d; 425a, b; 462a-d) formed on the second semiconductor layer; a first insulating layer (116, 140) formed over the first source electrode, the first drain electrode, and the first electrode; a first opening formed in the first insulating layer (116, 140) to reach the first source electrode or the first drain electrode; a second opening formed in the gate insulating layer and the first insulating layer (116, 140) to reach the first electrode; and a wiring layer formed in the first opening and the second opening to electrically connect the first source electrode or the first drain electrode to the first electrode, wherein the first gate electrode (104; 471a, b; 401; 451a, b) and the first electrode are formed of the same material and in the same plane, and wherein the first electrode (120; 304; 304a, 304b) is a pixel electrode.