A charge pump circuit comprising a plurality of charge pump stages cascaded to one another between an input terminal, designed to receive an input voltage (V DD), and an output terminal, the charge pump stages are configured to jointly perform boosting of the input voltage (V DD)to provide on the output terminal an output voltage (V out) having a boosted value with respect to the input voltage (V DD); the charge pump circuit further comprising: a clock generator, configured to generate a clock signal having a first frequency value (CLK_Freq) provided to the charge pump stages to perform the boosting of the input voltage (V DD); and an output-voltage regulation feedback closed-loop (4, 6), coupled to the clock generator and configured to detect a feedback voltage (V f) as a function of the output voltage (V out) and to generate a control signal (S t) provided to the clock generator to perform a regulation of the output voltage (V out) based on the feedback voltage (V f), the output-voltage regulation feedback closed-loop (4, 6) including a voltage detection stage, coupled to the output terminal and configured to provide the feedback voltage (V f) as a function of the output voltage (V out), and a comparator stage, configured to perform a comparison between the feedback voltage (V f) and a reference voltage (V ref) and to generate the control signal (St) based on the comparison, characterized by comprising a discharge control stage coupled to the output-voltage regulation feedback closed-loop (4, 6) and to the clock generator, configured to control discharge of the charge pump circuit by generation of at least two of: a first discharge control signal (S c2) configured to disable the comparator stage; a second discharge control signal (S c3) configured to reduce the frequency of the clock signal to a second frequency value (CLK_Freq'), lower than the first frequency value (CLK_Freq); and a third discharge control signal (S c1) designed to cause an increase of a current load (Iload) on the output terminal by the voltage detection stage. a clock generator, configured to generate a clock signal having a first frequency value (CLK_Freq) provided to the charge pump stages to perform the boosting of the input voltage (V DD); and an output-voltage regulation feedback closed-loop (4, 6), coupled to the clock generator and configured to detect a feedback voltage (V f) as a function of the output voltage (V out) and to generate a control signal (S t) provided to the clock generator to perform a regulation of the output voltage (V out) based on the feedback voltage (V f), the output-voltage regulation feedback closed-loop (4, 6) including a voltage detection stage, coupled to the output terminal and configured to provide the feedback voltage (V f) as a function of the output voltage (V out), and a comparator stage, configured to perform a comparison between the feedback voltage (V f) and a reference voltage (V ref) and to generate the control signal (St) based on the comparison, characterized by comprising a discharge control stage coupled to the output-voltage regulation feedback closed-loop (4, 6) and to the clock generator, configured to control discharge of the charge pump circuit by generation of at least two of: a first discharge control signal (S c2) configured to disable the comparator stage; a second discharge control signal (S c3) configured to reduce the frequency of the clock signal to a second frequency value (CLK_Freq'), lower than the first frequency value (CLK_Freq); and a third discharge control signal (S c1) designed to cause an increase of a current load (Iload) on the output terminal by the voltage detection stage.