A power supply voltage selection circuit, comprising: first and second nodes capable of respectively receiving a first input power supply voltage and a second input power supply voltage smaller than the first voltage; a third node capable of supplying an output power supply voltage (VCORE); a first MOS power transistor coupling the first node to the third node; a second MOS power transistor coupling the second node to the third node; and a control circuit capable, in a first configuration, of keeping the first and second transistors respectively on and off to apply the first input power supply voltage to the third node and, in a second configuration, of keeping the first and second transistors respectively off and on to apply the second input power supply voltage to the third node, the control circuit comprising a feedback loop from the third node to the gate of the first transistor, and being capable, during a phase of transition from the first to the second configuration or from the second to the first configuration, of controlling the first transistor in linear operating region to apply a DC voltage ramp to the third node, wherein the control circuit comprises: a voltage ramp generator; and a first linear regulation circuit forming the feedback loop, and having a first input node connected to the third node, having a second input node connected to an output node (s) of the ramp generator, and having an output node (s) connected to the gate of the first transistor, and wherein the first linear regulation circuit is capable of adjusting a control signal applied, via its output node (s), to the gate of the first transistor, to control the output voltage (VCORE) to a target voltage applied to its second input node. first and second nodes capable of respectively receiving a first input power supply voltage and a second input power supply voltage smaller than the first voltage; a third node capable of supplying an output power supply voltage (VCORE); a first MOS power transistor coupling the first node to the third node; a second MOS power transistor coupling the second node to the third node; and a control circuit capable, in a first configuration, of keeping the first and second transistors respectively on and off to apply the first input power supply voltage to the third node and, in a second configuration, of keeping the first and second transistors respectively off and on to apply the second input power supply voltage to the third node, the control circuit comprising a feedback loop from the third node to the gate of the first transistor, and being capable, during a phase of transition from the first to the second configuration or from the second to the first configuration, of controlling the first transistor in linear operating region to apply a DC voltage ramp to the third node, wherein the control circuit comprises: a voltage ramp generator; and a first linear regulation circuit forming the feedback loop, and having a first input node connected to the third node, having a second input node connected to an output node (s) of the ramp generator, and having an output node (s) connected to the gate of the first transistor, a voltage ramp generator; and a first linear regulation circuit forming the feedback loop, and having a first input node connected to the third node, having a second input node connected to an output node (s) of the ramp generator, and having an output node (s) connected to the gate of the first transistor, and wherein the first linear regulation circuit is capable of adjusting a control signal applied, via its output node (s), to the gate of the first transistor, to control the output voltage (VCORE) to a target voltage applied to its second input node.