An integrated circuit comprising: core logic; a plurality of interface blocks physically disposed about a periphery of the core logic; and a plurality of input or output (I/O) circuits assigned to one of the plurality of interface blocks, wherein the I/O circuits comprise external I/O circuits adapted to be coupled to a device other than the integrated circuit and internal I/O circuits adapted to be coupled to the integrated circuit; wherein each interface block includes: a first plurality of I/O circuits physically disposed on a first side of the interface block and a second plurality of I/O circuits spaced apart from the first plurality of I/O circuits and physically disposed on a second side of the interface block opposite the first side of the interface block, the first plurality of I/O circuits and the second plurality of I/O circuits defining an exterior of the interface block; interface logic for the interface block, the interface logic comprising a region physically located between the first plurality of I/O circuits and the second plurality of I/O circuits, said region defining an interior of the interface block; and a logic hub of the interface logic physically located at the interior of the interface block, the logic hub including a clock distribution of minimal length that distributes clock signals from the interior of the interface block toward the first plurality of I/O circuits and the second plurality of I/O circuits at the exterior of the interface block, the clock signals to drive launch logic and capture logic to and from the I/O circuits of the interface block. core logic; a plurality of interface blocks physically disposed about a periphery of the core logic; and a plurality of input or output (I/O) circuits assigned to one of the plurality of interface blocks, wherein the I/O circuits comprise external I/O circuits adapted to be coupled to a device other than the integrated circuit and internal I/O circuits adapted to be coupled to the integrated circuit; wherein each interface block includes: a first plurality of I/O circuits physically disposed on a first side of the interface block and a second plurality of I/O circuits spaced apart from the first plurality of I/O circuits and physically disposed on a second side of the interface block opposite the first side of the interface block, the first plurality of I/O circuits and the second plurality of I/O circuits defining an exterior of the interface block; interface logic for the interface block, the interface logic comprising a region physically located between the first plurality of I/O circuits and the second plurality of I/O circuits, said region defining an interior of the interface block; and a logic hub of the interface logic physically located at the interior of the interface block, the logic hub including a clock distribution of minimal length that distributes clock signals from the interior of the interface block toward the first plurality of I/O circuits and the second plurality of I/O circuits at the exterior of the interface block, the clock signals to drive launch logic and capture logic to and from the I/O circuits of the interface block. a first plurality of I/O circuits physically disposed on a first side of the interface block and a second plurality of I/O circuits spaced apart from the first plurality of I/O circuits and physically disposed on a second side of the interface block opposite the first side of the interface block, the first plurality of I/O circuits and the second plurality of I/O circuits defining an exterior of the interface block; interface logic for the interface block, the interface logic comprising a region physically located between the first plurality of I/O circuits and the second plurality of I/O circuits, said region defining an interior of the interface block; and a logic hub of the interface logic physically located at the interior of the interface block, the logic hub including a clock distribution of minimal length that distributes clock signals from the interior of the interface block toward the first plurality of I/O circuits and the second plurality of I/O circuits at the exterior of the interface block, the clock signals to drive launch logic and capture logic to and from the I/O circuits of the interface block.