An apparatus comprising: a receiver to receive data via an interconnect, the receiver including a voltage margining circuit to receive non-deterministic data communicated via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels, wherein the voltage margining circuit comprises: a parallel sampler circuit to receive a plurality of signals from the interconnect and to receive a plurality of reference voltage levels from a reference level generator, at least two of the plurality of signals received at opposite polarity levels and a third of the plurality of signals received at a midpoint value between the opposite polarity levels, the parallel sampler circuit to indicate when a bit error occurs for a sample of the plurality of signals; wherein the parallel sampler circuit comprises: a plurality of data samplers each to receive a selected pair of a first signal, a second signal, and a third signal, and to output a corresponding value based on a comparison of the selected pair; and a plurality of margin samplers each to receive a selected one of the first, second and third signals and a selected one of a first reference voltage level, second reference voltage level, and a third reference voltage level, and to output a corresponding margining value based on a comparison of the selected first, second or third signal, and the selected first, second or third reference voltage level; and an error collection circuit coupled to the parallel sampler circuit and including one or more error counters to maintain a count of samples having a bit error and to communicate a report of the count of samples maintained for a voltage margining process performed on non-deterministic data. a receiver to receive data via an interconnect, the receiver including a voltage margining circuit to receive non-deterministic data communicated via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels, wherein the voltage margining circuit comprises: a parallel sampler circuit to receive a plurality of signals from the interconnect and to receive a plurality of reference voltage levels from a reference level generator, at least two of the plurality of signals received at opposite polarity levels and a third of the plurality of signals received at a midpoint value between the opposite polarity levels, the parallel sampler circuit to indicate when a bit error occurs for a sample of the plurality of signals; wherein the parallel sampler circuit comprises: a plurality of data samplers each to receive a selected pair of a first signal, a second signal, and a third signal, and to output a corresponding value based on a comparison of the selected pair; and a plurality of margin samplers each to receive a selected one of the first, second and third signals and a selected one of a first reference voltage level, second reference voltage level, and a third reference voltage level, and to output a corresponding margining value based on a comparison of the selected first, second or third signal, and the selected first, second or third reference voltage level; and an error collection circuit coupled to the parallel sampler circuit and including one or more error counters to maintain a count of samples having a bit error and to communicate a report of the count of samples maintained for a voltage margining process performed on non-deterministic data. a parallel sampler circuit to receive a plurality of signals from the interconnect and to receive a plurality of reference voltage levels from a reference level generator, at least two of the plurality of signals received at opposite polarity levels and a third of the plurality of signals received at a midpoint value between the opposite polarity levels, the parallel sampler circuit to indicate when a bit error occurs for a sample of the plurality of signals; wherein the parallel sampler circuit comprises: a plurality of data samplers each to receive a selected pair of a first signal, a second signal, and a third signal, and to output a corresponding value based on a comparison of the selected pair; and a plurality of margin samplers each to receive a selected one of the first, second and third signals and a selected one of a first reference voltage level, second reference voltage level, and a third reference voltage level, and to output a corresponding margining value based on a comparison of the selected first, second or third signal, and the selected first, second or third reference voltage level; and a plurality of data samplers each to receive a selected pair of a first signal, a second signal, and a third signal, and to output a corresponding value based on a comparison of the selected pair; and a plurality of margin samplers each to receive a selected one of the first, second and third signals and a selected one of a first reference voltage level, second reference voltage level, and a third reference voltage level, and to output a corresponding margining value based on a comparison of the selected first, second or third signal, and the selected first, second or third reference voltage level; and an error collection circuit coupled to the parallel sampler circuit and including one or more error counters to maintain a count of samples having a bit error and to communicate a report of the count of samples maintained for a voltage margining process performed on non-deterministic data.