A thin film transistor, comprising: a substrate; a semiconductor layer disposed on the substrate, comprising a channel region, source and drain regions, a first body contact region formed at a first edge of the semiconductor layer and a second body contact region formed at a second edge of the semiconductor layer, the second edge of the semiconductor layer being opposite the first edge of the semiconductor layer; a gate insulating layer disposed on the channel region of the semiconductor layer exposing the first and second body contact regions; a silicon layer disposed on the gate insulating layer and the first and second body contact regions, the silicon layer contacting the first and second body contact regions; a metal gate electrode disposed on the silicon layer; an interlayer insulating layer disposed on the metal gate electrode and the gate insulating layer; and source and drain electrodes (112a, 112b) disposed on the interlayer insulating layer and electrically connected with the source and drain regions (102s, 102d), respectively, wherein the source region,, the drain region, the channel region, and the first and second body contact regions each have a rectangular shape respectively having a source region width, a drain region width, a channel region width, a first body contact region width and a second body contact region width, characterized in that a sum of the channel region width, of the first body contact region width and of the second body contact region width is equal to the source region width and to the drain region width and in that the first and second body contact regions have a same length as the channel region of the semiconductor layer. a substrate; a semiconductor layer disposed on the substrate, comprising a channel region, source and drain regions, a first body contact region formed at a first edge of the semiconductor layer and a second body contact region formed at a second edge of the semiconductor layer, the second edge of the semiconductor layer being opposite the first edge of the semiconductor layer; a gate insulating layer disposed on the channel region of the semiconductor layer exposing the first and second body contact regions; a silicon layer disposed on the gate insulating layer and the first and second body contact regions, the silicon layer contacting the first and second body contact regions; a metal gate electrode disposed on the silicon layer; an interlayer insulating layer disposed on the metal gate electrode and the gate insulating layer; and source and drain electrodes (112a, 112b) disposed on the interlayer insulating layer and electrically connected with the source and drain regions (102s, 102d), respectively, wherein the source region,, the drain region, the channel region, and the first and second body contact regions each have a rectangular shape respectively having a source region width, a drain region width, a channel region width, a first body contact region width and a second body contact region width, characterized in that a sum of the channel region width, of the first body contact region width and of the second body contact region width is equal to the source region width and to the drain region width and in that the first and second body contact regions have a same length as the channel region of the semiconductor layer.