A method of forming a NAND unit cell construction, comprising: forming a cavity extending into a semiconductor substrate; epitaxially growing alternating layers of n-type doped semiconductor material (20, 22, 24, 26) and p-type doped semiconductor material (21, 23, 25) within the cavity; patterning the epitaxially-grown alternating layers into a plurality of vertical columns (40, 42, 44, 46, 48, 50); adjacent columns being spaced from one another by openings (58, 60); lining at least portions of the openings (58, 60) with tunnel dielectric, charge-storage material and blocking dielectric to narrow said portions of the openings (58, 60); forming alternating layers of electrically insulative material (84, 86, 88, 90) and electrically conductive material (78, 80, 82) within the narrowed portions of the openings (58, 60), the layers of the electrically conductive material (78, 80, 82) forming a plurality of horizontally-spaced control gate structures, said horizontally-spaced control gate structures (78, 80, 82), said blocking dielectric, said charge-storage material, said tunnel dielectric and said vertical columns (40, 42, 44, 46, 48, 50) forming string devices of the NAND unit cell construction; and the plurality of horizontally-spaced control gate structures are horizontally aligned with the layers of p-type doped semiconductor material and have the same vertical thickness than the layers of p-type doped semiconductor material or the plurality of horizontally-spaced control gate structures are horizontally aligned with the layers of n-type doped semiconductor material have the same vertical thickness than the layers of n-type doped semiconductor material. forming a cavity extending into a semiconductor substrate; epitaxially growing alternating layers of n-type doped semiconductor material (20, 22, 24, 26) and p-type doped semiconductor material (21, 23, 25) within the cavity; patterning the epitaxially-grown alternating layers into a plurality of vertical columns (40, 42, 44, 46, 48, 50); adjacent columns being spaced from one another by openings (58, 60); lining at least portions of the openings (58, 60) with tunnel dielectric, charge-storage material and blocking dielectric to narrow said portions of the openings (58, 60); forming alternating layers of electrically insulative material (84, 86, 88, 90) and electrically conductive material (78, 80, 82) within the narrowed portions of the openings (58, 60), the layers of the electrically conductive material (78, 80, 82) forming a plurality of horizontally-spaced control gate structures, said horizontally-spaced control gate structures (78, 80, 82), said blocking dielectric, said charge-storage material, said tunnel dielectric and said vertical columns (40, 42, 44, 46, 48, 50) forming string devices of the NAND unit cell construction; and the plurality of horizontally-spaced control gate structures are horizontally aligned with the layers of p-type doped semiconductor material and have the same vertical thickness than the layers of p-type doped semiconductor material or the plurality of horizontally-spaced control gate structures are horizontally aligned with the layers of n-type doped semiconductor material have the same vertical thickness than the layers of n-type doped semiconductor material.