A Gas Chromatograph detector, comprising: a) a first circuit (302) including a first counter circuitry (305) having a first N-bit counter (307) configured to receive a first count up signal (310) and a first count down signal (312) in response to a first amplifier output (315) and provide a first counter output (317), wherein the first circuit (302) comprises a first digital pulse width modulator, PWM, (347) configured to provide first PWM output (350); b) a second circuit (302) including a second counter circuitry (305) having a second N-bit counter (307) configured to receive a second count up signal (310) and a second count down signal (312) in response to a second amplifier output (315) and provide a second counter output (317), wherein the second circuit (302) comprises a second digital pulse width modulator, PWM, (347) configured to provide a second PWM output (350); c) a digital subtractor of an A/D converter configured to subtract the first counter output (317) from the second counter output (317) and provide a digital subtractor output, wherein the A/D converter is a sigma-delta A/D converter; and d) a digital logic shared between one to many detector channels to implement at least a portion of the first counter circuitry (305) and the second counter circuitry (305), the digital logic configured to receive the digital subtractor output and provide a GC measurement in a digital form, e) wherein the first circuit (302) comprises a reference amplifier that includes a first Thermal Conductivity Detector, TCD, (335) configured to provide the first amplifier output (315), and the second circuit 302 comprises an amplifier that includes a second Thermal Conductivity Detector, TCD, (335) configured to provide the second amplifier output (315), and f) wherein the GC detector does not have an analog difference amplifier that removes a large common mode range and provides a highly resolved difference signal to a sigma-delta A/D converter and does not have an internal sigma block internal to the sigma-delta A/D converter, and g) wherein by the first and second Thermal Conductivity Detectors, TCD, (335, 335) an integrator of a Sigma-Delta (Σ-Δ) A/D converter is eliminated and the Σ factor of the Sigma-Delta (Σ-Δ) A/D converter is accomplished in a digital form. a) a first circuit (302) including a first counter circuitry (305) having a first N-bit counter (307) configured to receive a first count up signal (310) and a first count down signal (312) in response to a first amplifier output (315) and provide a first counter output (317), wherein the first circuit (302) comprises a first digital pulse width modulator, PWM, (347) configured to provide first PWM output (350); b) a second circuit (302) including a second counter circuitry (305) having a second N-bit counter (307) configured to receive a second count up signal (310) and a second count down signal (312) in response to a second amplifier output (315) and provide a second counter output (317), wherein the second circuit (302) comprises a second digital pulse width modulator, PWM, (347) configured to provide a second PWM output (350); c) a digital subtractor of an A/D converter configured to subtract the first counter output (317) from the second counter output (317) and provide a digital subtractor output, wherein the A/D converter is a sigma-delta A/D converter; and d) a digital logic shared between one to many detector channels to implement at least a portion of the first counter circuitry (305) and the second counter circuitry (305), the digital logic configured to receive the digital subtractor output and provide a GC measurement in a digital form, e) wherein the first circuit (302) comprises a reference amplifier that includes a first Thermal Conductivity Detector, TCD, (335) configured to provide the first amplifier output (315), and the second circuit 302 comprises an amplifier that includes a second Thermal Conductivity Detector, TCD, (335) configured to provide the second amplifier output (315), and f) wherein the GC detector does not have an analog difference amplifier that removes a large common mode range and provides a highly resolved difference signal to a sigma-delta A/D converter and does not have an internal sigma block internal to the sigma-delta A/D converter, and g) wherein by the first and second Thermal Conductivity Detectors, TCD, (335, 335) an integrator of a Sigma-Delta (Σ-Δ) A/D converter is eliminated and the Σ factor of the Sigma-Delta (Σ-Δ) A/D converter is accomplished in a digital form.