A memory cell comprising: A microelectronic component comprising: a semiconductor layer resting on an insulating layer resting on a silicon substrate and comprising a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region comprising first and second portions respectively extending from the drain region and from the source region; the first conductivity type and the second conductivity type being opposite; an insulated front gate electrode resting on said first portion; a first back gate electrode arranged under the insulating layer, opposite the first portion and comprising a doped silicone region of the first conductivity type; a second back gate electrode arranged under the insulating layer, opposite the second portion, and comprising a doped silicon region of the second conductivity type; and control means adapted to supply a first bias voltage to the first back gate electrode, a second bias voltage, different from the first bias voltage, to the second back gate electrode, a reference voltage to the source region, a first control signal (V D) to the drain region, and a second control signal (V G) to the front gate electrode. A microelectronic component comprising: a semiconductor layer resting on an insulating layer resting on a silicon substrate and comprising a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region comprising first and second portions respectively extending from the drain region and from the source region; the first conductivity type and the second conductivity type being opposite; an insulated front gate electrode resting on said first portion; a first back gate electrode arranged under the insulating layer, opposite the first portion and comprising a doped silicone region of the first conductivity type; a second back gate electrode arranged under the insulating layer, opposite the second portion, and comprising a doped silicon region of the second conductivity type; and a semiconductor layer resting on an insulating layer resting on a silicon substrate and comprising a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region comprising first and second portions respectively extending from the drain region and from the source region; the first conductivity type and the second conductivity type being opposite; an insulated front gate electrode resting on said first portion; a first back gate electrode arranged under the insulating layer, opposite the first portion and comprising a doped silicone region of the first conductivity type; a second back gate electrode arranged under the insulating layer, opposite the second portion, and comprising a doped silicon region of the second conductivity type; and control means adapted to supply a first bias voltage to the first back gate electrode, a second bias voltage, different from the first bias voltage, to the second back gate electrode, a reference voltage to the source region, a first control signal (V D) to the drain region, and a second control signal (V G) to the front gate electrode.