An integrated circuit, comprising: a first floating-point multiplier that is configured to receive a first set of floating-point numbers and that is configured to output a first floating-point number; a second floating-point multiplier that is configured to receive a second set of floating-point numbers and that is configured to output a second floating-point number; and a floating-point adder circuit that is configured to receive the first floating-point number and the second floating-point number and that is configured to output a corresponding third floating-point number, wherein: the first floating-point number and the second floating-point number have a first format, and the third floating-point number has a second format that is different than the first format; the first floating-point number and the second floating-point number have a first dynamic range, and the third floating-point number has a second dynamic range that is less than the first dynamic range; and wherein the circuit is configured such that a normal-range result of first floating-point number and the second floating-point number is converted to a subnormal range of the third floating-point number, characterized in that the circuit is configured such that a subnormal-range result of the first set of floating-point numbers is converted to a normal range of the first floating-point number, and wherein a subnormal-range result of the second set of floating-point numbers is converted to a normal range of the second floating-point number; a normal-range result of the first and second floating-point numbers is converted to an exception-condition range of the third floating-point number; and an exception result of the first floating-point number and the second floating-point number is converted to a normal range of the third floating-point number. a first floating-point multiplier that is configured to receive a first set of floating-point numbers and that is configured to output a first floating-point number; a second floating-point multiplier that is configured to receive a second set of floating-point numbers and that is configured to output a second floating-point number; and a floating-point adder circuit that is configured to receive the first floating-point number and the second floating-point number and that is configured to output a corresponding third floating-point number, wherein: the first floating-point number and the second floating-point number have a first format, and the third floating-point number has a second format that is different than the first format; the first floating-point number and the second floating-point number have a first dynamic range, and the third floating-point number has a second dynamic range that is less than the first dynamic range; and wherein the circuit is configured such that a normal-range result of first floating-point number and the second floating-point number is converted to a subnormal range of the third floating-point number, characterized in that the circuit is configured such that a subnormal-range result of the first set of floating-point numbers is converted to a normal range of the first floating-point number, and wherein a subnormal-range result of the second set of floating-point numbers is converted to a normal range of the second floating-point number; a normal-range result of the first and second floating-point numbers is converted to an exception-condition range of the third floating-point number; and an exception result of the first floating-point number and the second floating-point number is converted to a normal range of the third floating-point number. the first floating-point number and the second floating-point number have a first format, and the third floating-point number has a second format that is different than the first format; the first floating-point number and the second floating-point number have a first dynamic range, and the third floating-point number has a second dynamic range that is less than the first dynamic range; and wherein the circuit is configured such that a normal-range result of first floating-point number and the second floating-point number is converted to a subnormal range of the third floating-point number, characterized in that the circuit is configured such that a subnormal-range result of the first set of floating-point numbers is converted to a normal range of the first floating-point number, and wherein a subnormal-range result of the second set of floating-point numbers is converted to a normal range of the second floating-point number; a normal-range result of the first and second floating-point numbers is converted to an exception-condition range of the third floating-point number; and an exception result of the first floating-point number and the second floating-point number is converted to a normal range of the third floating-point number.