A clock gating circuit (100, 200, 300) for selectively passing an input clock signal (CLK_IN) as an output clock signal (CLK_OUT) in response to a clock enable signal (CLK_EN), the clock gating circuit (100, 200, 300) comprising: a latch control circuit having input terminals to receive the input clock signal (CLK_IN), the clock enable signal (CLK_EN), and a clock gating control signal (CLK_GC), and having an output terminal to generate a latch enable signal (LAT_EN); a storage latch (110, 210) for latching the clock enable signal (CLK EN), the storage latch (110, 210) having a data terminal responsive to the clock enable signal (CLK_EN), a latch enable terminal responsive to the latch enable signal (LAT_EN), and having an output terminal to generate the clock gating control signal (CLK_GC); and a logic gate having input terminals to receive the input clock signal (CLK_IN) and the clock gating control signal (CLK_GC), and having an output terminal to generate the output clock signal (CLK_OUT), wherein the latch control circuit (100, 200, 300) comprises: an AND gate having a first input responsive to the clock enable signal (CLK_EN), a second input responsive to the clock gating control signal (CLK_GC), and an output; and a NOR gate having a first input responsive to the input clock signal (CLK_IN), a second input coupled to the output of the AND gate, and an output to generate the latch enable signal (LAT_EN) or wherein the latch control circuit (100, 200, 300) comprises: an inverter having an input responsive to the clock enable signal (CLK_EN), and an output; an AND gate having a first input coupled to the output of the inverter, a second input responsive to the clock gating control signal (CLK_GC), and an output; and a NOR gate having a first input responsive to the input clock signal (CLK_IN), a second input coupled to the output of the AND gate, and an output to generate the latch enable signal (LAT_EN). a latch control circuit having input terminals to receive the input clock signal (CLK_IN), the clock enable signal (CLK_EN), and a clock gating control signal (CLK_GC), and having an output terminal to generate a latch enable signal (LAT_EN); a storage latch (110, 210) for latching the clock enable signal (CLK EN), the storage latch (110, 210) having a data terminal responsive to the clock enable signal (CLK_EN), a latch enable terminal responsive to the latch enable signal (LAT_EN), and having an output terminal to generate the clock gating control signal (CLK_GC); and a logic gate having input terminals to receive the input clock signal (CLK_IN) and the clock gating control signal (CLK_GC), and having an output terminal to generate the output clock signal (CLK_OUT), wherein the latch control circuit (100, 200, 300) comprises: an AND gate having a first input responsive to the clock enable signal (CLK_EN), a second input responsive to the clock gating control signal (CLK_GC), and an output; and a NOR gate having a first input responsive to the input clock signal (CLK_IN), a second input coupled to the output of the AND gate, and an output to generate the latch enable signal (LAT_EN) or an AND gate having a first input responsive to the clock enable signal (CLK_EN), a second input responsive to the clock gating control signal (CLK_GC), and an output; and a NOR gate having a first input responsive to the input clock signal (CLK_IN), a second input coupled to the output of the AND gate, and an output to generate the latch enable signal (LAT_EN) or wherein the latch control circuit (100, 200, 300) comprises: an inverter having an input responsive to the clock enable signal (CLK_EN), and an output; an AND gate having a first input coupled to the output of the inverter, a second input responsive to the clock gating control signal (CLK_GC), and an output; and a NOR gate having a first input responsive to the input clock signal (CLK_IN), a second input coupled to the output of the AND gate, and an output to generate the latch enable signal (LAT_EN). an inverter having an input responsive to the clock enable signal (CLK_EN), and an output; an AND gate having a first input coupled to the output of the inverter, a second input responsive to the clock gating control signal (CLK_GC), and an output; and a NOR gate having a first input responsive to the input clock signal (CLK_IN), a second input coupled to the output of the AND gate, and an output to generate the latch enable signal (LAT_EN).