A memory module comprising: a circuit board; a first plurality of components (116, 117) disposed on the circuit board, each of the components (116, 117) having an address/control input, a clock input, a data output and a strobe output; a first termination component and a second termination component disposed on the circuit board; a common address/control signal path coupled at one end to said first termination component and coupled to the address/control input of each of the components (116, 117) in succession such that control signals propagating toward the first termination component on the address/control signal path arrive at the address/control inputs of respective components (116, 117) at progressively later times corresponding to relative positions of the components (116, 117); a plurality of bidirectional data signal paths, each of the data signal paths extending from the data output of a respective one of the components (116, 117) along the length of the circuit board and including a plurality of data signal conductors to convey a respective read data value; and a plurality of strobe signal paths, each of the strobe signal paths routed from the strobe output of a respective one of the components (116, 117) to convey a strobe signal that indicates that the read data value is present on the data signal path extending from the data output of the one of the components (116, 117). characterized in that the memory module further comprises: a clock signal path coupled at one end to said second termination component and coupled to the clock input of each of the components (116, 117) such that a clock signal propagating toward the second termination component on the clock signal path arrives at the clock inputs of respective components (116, 117) at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the components (116, 117), the clock signal indicating to the components (116, 117) respective times at which to sample the control signals arriving at their address/control inputs, and wherein the clock signal path is coupled along its length to the clock input of each of the components (116, 117). a circuit board; a first plurality of components (116, 117) disposed on the circuit board, each of the components (116, 117) having an address/control input, a clock input, a data output and a strobe output; a first termination component and a second termination component disposed on the circuit board; a common address/control signal path coupled at one end to said first termination component and coupled to the address/control input of each of the components (116, 117) in succession such that control signals propagating toward the first termination component on the address/control signal path arrive at the address/control inputs of respective components (116, 117) at progressively later times corresponding to relative positions of the components (116, 117); a plurality of bidirectional data signal paths, each of the data signal paths extending from the data output of a respective one of the components (116, 117) along the length of the circuit board and including a plurality of data signal conductors to convey a respective read data value; and a plurality of strobe signal paths, each of the strobe signal paths routed from the strobe output of a respective one of the components (116, 117) to convey a strobe signal that indicates that the read data value is present on the data signal path extending from the data output of the one of the components (116, 117). a clock signal path coupled at one end to said second termination component and coupled to the clock input of each of the components (116, 117) such that a clock signal propagating toward the second termination component on the clock signal path arrives at the clock inputs of respective components (116, 117) at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the components (116, 117), the clock signal indicating to the components (116, 117) respective times at which to sample the control signals arriving at their address/control inputs, and wherein the clock signal path is coupled along its length to the clock input of each of the components (116, 117).