A method of performing a programming process to a three dimensional NAND memory device, comprising: during a pre-charging phase of the programming process, applying a first voltage to a plurality of word lines of the 3D NAND memory device, wherein the plurality of word lines is located vertically above a plurality of dummy word lines; during the pre-charging phase, applying a second voltage to a second neighboring word line (WL_x+2) of the 3D NAND memory device, wherein the second neighboring word line (WL_x+2) is one of the plurality of word lines and located vertically above a selected word line of the plurality of word lines; and during a boosting phase of the programming process, applying the second voltage to the second neighboring word line (WL_x+2) and a plurality of first word lines of the plurality of word lines, and applying a third voltage to a first neighboring word line (WL_x+1) of the 3D NAND memory device, wherein the first neighboring word line (WL_x+1) is one of the plurality of word lines but excluded from the plurality of first word lines and located vertically below the second neighboring word line (WL_x+2) and above the selected word line; wherein applying the first voltage to the plurality of wordlines of the 3D NAND memory device comprises: increasing voltages of the plurality of word lines from zero volt when the pre-charging phase begins; applying the first voltage to the plurality of word lines from a first time to a second time; and decreasing voltages of a first portion of the plurality of word lines excluding the second neighboring word line (WL_x+2) from the first voltage at the second time to zero volt at a third time until the pre-charging phase ends, and wherein applying the second voltage to the second neighboring wordline of the 3D NAND memory device comprises: increasing a voltage of the second neighboring word line (WL_x+2) from zero volt at a fourth time to the second voltage at a fifth time; and applying the second voltage to the second neighboring word line (WL_x+2) from the fifth time to a seventh time; wherein the pre-charging phase ends and the boosting phase begins at the seventh time, wherein during the precharge phase the second voltage is different from the first voltage. during a pre-charging phase of the programming process, applying a first voltage to a plurality of word lines of the 3D NAND memory device, wherein the plurality of word lines is located vertically above a plurality of dummy word lines; during the pre-charging phase, applying a second voltage to a second neighboring word line (WL_x+2) of the 3D NAND memory device, wherein the second neighboring word line (WL_x+2) is one of the plurality of word lines and located vertically above a selected word line of the plurality of word lines; and during a boosting phase of the programming process, applying the second voltage to the second neighboring word line (WL_x+2) and a plurality of first word lines of the plurality of word lines, and applying a third voltage to a first neighboring word line (WL_x+1) of the 3D NAND memory device, wherein the first neighboring word line (WL_x+1) is one of the plurality of word lines but excluded from the plurality of first word lines and located vertically below the second neighboring word line (WL_x+2) and above the selected word line; wherein applying the first voltage to the plurality of wordlines of the 3D NAND memory device comprises: increasing voltages of the plurality of word lines from zero volt when the pre-charging phase begins; applying the first voltage to the plurality of word lines from a first time to a second time; and decreasing voltages of a first portion of the plurality of word lines excluding the second neighboring word line (WL_x+2) from the first voltage at the second time to zero volt at a third time until the pre-charging phase ends, and wherein applying the second voltage to the second neighboring wordline of the 3D NAND memory device comprises: increasing a voltage of the second neighboring word line (WL_x+2) from zero volt at a fourth time to the second voltage at a fifth time; and applying the second voltage to the second neighboring word line (WL_x+2) from the fifth time to a seventh time; wherein the pre-charging phase ends and the boosting phase begins at the seventh time, wherein during the precharge phase the second voltage is different from the first voltage. increasing voltages of the plurality of word lines from zero volt when the pre-charging phase begins; applying the first voltage to the plurality of word lines from a first time to a second time; and decreasing voltages of a first portion of the plurality of word lines excluding the second neighboring word line (WL_x+2) from the first voltage at the second time to zero volt at a third time until the pre-charging phase ends, and wherein applying the second voltage to the second neighboring wordline of the 3D NAND memory device comprises: increasing a voltage of the second neighboring word line (WL_x+2) from zero volt at a fourth time to the second voltage at a fifth time; and applying the second voltage to the second neighboring word line (WL_x+2) from the fifth time to a seventh time; wherein the pre-charging phase ends and the boosting phase begins at the seventh time, wherein during the precharge phase the second voltage is different from the first voltage.