A storage device comprising: an interface circuit configured to exchange data with a host device, the interface circuit including, a first input terminal (DIN_t) configured to receive a first signal from the host device, a second input terminal (DIN_c) configured to receive a second signal from the host device, the second signal being complementary to the first signal, a squelch circuit configured to detect levels of the first signal and the second signal, and a reference clock detector configured to detect a receipt of a reference clock (REF_CLK) from the host device; and a power manager configured to supply a power to the interface circuit such that the power manager selectively supplies the power to the squelch circuit based on whether the reference clock detector detects the receipt of the reference clock (REF_CLK) from the host device, wherein the reference clock detector is configured to, detect interruption of the receipt of the reference clock (REF_CLK) while the storage device is in an active mode, and generate a first trigger signal, in response to detecting the interruption of the receipt of the reference clock (REF_CLK), wherein the power manager is configured to block supply of the power to the squelch circuit in response to the first trigger signal, wherein the reference clock detector is further configured to, detect resumption of the receipt of the reference clock (REF_CLK) while the storage device is in an idle mode, and generate a second trigger signal, in response to detecting the resumption of the receipt of the reference clock (REF_CLK), and wherein the power manager is further configured to supply the power to the squelch circuit in response to the second trigger signal. an interface circuit configured to exchange data with a host device, the interface circuit including, a first input terminal (DIN_t) configured to receive a first signal from the host device, a second input terminal (DIN_c) configured to receive a second signal from the host device, the second signal being complementary to the first signal, a squelch circuit configured to detect levels of the first signal and the second signal, and a reference clock detector configured to detect a receipt of a reference clock (REF_CLK) from the host device; and a first input terminal (DIN_t) configured to receive a first signal from the host device, a second input terminal (DIN_c) configured to receive a second signal from the host device, the second signal being complementary to the first signal, a squelch circuit configured to detect levels of the first signal and the second signal, and a reference clock detector configured to detect a receipt of a reference clock (REF_CLK) from the host device; and a power manager configured to supply a power to the interface circuit such that the power manager selectively supplies the power to the squelch circuit based on whether the reference clock detector detects the receipt of the reference clock (REF_CLK) from the host device, wherein the reference clock detector is configured to, detect interruption of the receipt of the reference clock (REF_CLK) while the storage device is in an active mode, and generate a first trigger signal, in response to detecting the interruption of the receipt of the reference clock (REF_CLK), detect interruption of the receipt of the reference clock (REF_CLK) while the storage device is in an active mode, and generate a first trigger signal, in response to detecting the interruption of the receipt of the reference clock (REF_CLK), wherein the power manager is configured to block supply of the power to the squelch circuit in response to the first trigger signal, wherein the reference clock detector is further configured to, detect resumption of the receipt of the reference clock (REF_CLK) while the storage device is in an idle mode, and generate a second trigger signal, in response to detecting the resumption of the receipt of the reference clock (REF_CLK), and detect resumption of the receipt of the reference clock (REF_CLK) while the storage device is in an idle mode, and generate a second trigger signal, in response to detecting the resumption of the receipt of the reference clock (REF_CLK), and wherein the power manager is further configured to supply the power to the squelch circuit in response to the second trigger signal.