An array substrate, comprising a base; a pixel electrode and a thin film transistor, disposed on the base; a passivation layer, covering the thin film transistor and the pixel electrode, the passivation layer being provided with a transferring through hole (K1,K2) exposing the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously; a connection electrode, disposed on the passivation layer and at the transferring through hole (K1,K2), wherein the connection electrode is connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole (K1,K2), wherein the array substrate further comprises a gate line and a data line, wherein the thin film transistor comprises a gate electrode, an active layer, the source electrode and the drain electrode, the pixel electrode, the gate line and the gate electrode are disposed on the base, the pixel electrode, the gate line and the gate electrode are covered with a gate insulation layer, the active layer, the source electrode, the drain electrode and the data line are disposed on the gate insulation layer, and a conductive channel is formed between the source electrode and the drain electrode, characterized in that: the connection electrode comprises a first compensation block which is a portion of the connection electrode disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base overlaps at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base, and a second compensation block which is another portion of the connection electrode disposed at a side of the connection electrode away from the gate line, an orthographic projection of the second compensation block on the base overlaps at least a portion of an orthographic projection of an edge of the source electrode or the drain electrode at a side away from the gate line on the base, wherein the first compensation block extends from a main body of the connection electrode towards the gate line, the second compensation block extends from the main body of the connection electrode to a direction away from the gate line, and in a plane which is parallel to the substrate, sizes of the first compensation block and the second compensation block are smaller than a size of the main body in a direction parallel to a direction of the gate line. a base; a pixel electrode and a thin film transistor, disposed on the base; a passivation layer, covering the thin film transistor and the pixel electrode, the passivation layer being provided with a transferring through hole (K1,K2) exposing the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously; a connection electrode, disposed on the passivation layer and at the transferring through hole (K1,K2), wherein the connection electrode is connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole (K1,K2), wherein the array substrate further comprises a gate line and a data line, wherein the thin film transistor comprises a gate electrode, an active layer, the source electrode and the drain electrode, the pixel electrode, the gate line and the gate electrode are disposed on the base, the pixel electrode, the gate line and the gate electrode are covered with a gate insulation layer, the active layer, the source electrode, the drain electrode and the data line are disposed on the gate insulation layer, and a conductive channel is formed between the source electrode and the drain electrode, characterized in that: the connection electrode comprises a first compensation block which is a portion of the connection electrode disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base overlaps at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base, and a second compensation block which is another portion of the connection electrode disposed at a side of the connection electrode away from the gate line, an orthographic projection of the second compensation block on the base overlaps at least a portion of an orthographic projection of an edge of the source electrode or the drain electrode at a side away from the gate line on the base, wherein the first compensation block extends from a main body of the connection electrode towards the gate line, the second compensation block extends from the main body of the connection electrode to a direction away from the gate line, and in a plane which is parallel to the substrate, sizes of the first compensation block and the second compensation block are smaller than a size of the main body in a direction parallel to a direction of the gate line.