An integrated circuit, comprising: a floating-point adder configured to receive first and second numbers, each having a mantissa and an exponent, wherein the floating-point adder comprises: a subtraction circuit; a normalization circuit; a mantissa alignment circuit; an addition circuit; wherein the subtraction circuit, the normalization circuit, the mantissa alignment circuit and the addition circuit are operable in a first mode that supports a first mantissa size and in a second mode that supports a second mantissa size that is different than the first mantissa size; and a multiplexer configured to receive far path signals from the addition circuit and to receive near path signals from the normalization circuit in the first and second modes; wherein the mantissa alignment circuit comprises a right shifter configured to shift a mantissa by a shift value to generate a shifted mantissa; characterized in that the mantissa alignment circuit further comprises: a gating circuit configured to selectively pass through the shifted mantissa and to selectively output only zero bits; and a comparison circuit configured to compare the shift value to a maximum shift value and to control the gating circuit, and wherein the comparison circuit is configured to selectively direct the gating circuit to output only zero bits, if the shift value exceeds the maximum shift value and to pass through the shifted mantissa if the shift value is equal or less than the maximum shift value. a floating-point adder configured to receive first and second numbers, each having a mantissa and an exponent, wherein the floating-point adder comprises: a subtraction circuit; a normalization circuit; a mantissa alignment circuit; an addition circuit; wherein the subtraction circuit, the normalization circuit, the mantissa alignment circuit and the addition circuit are operable in a first mode that supports a first mantissa size and in a second mode that supports a second mantissa size that is different than the first mantissa size; and a multiplexer configured to receive far path signals from the addition circuit and to receive near path signals from the normalization circuit in the first and second modes; a subtraction circuit; a normalization circuit; a mantissa alignment circuit; an addition circuit; wherein the subtraction circuit, the normalization circuit, the mantissa alignment circuit and the addition circuit are operable in a first mode that supports a first mantissa size and in a second mode that supports a second mantissa size that is different than the first mantissa size; and a multiplexer configured to receive far path signals from the addition circuit and to receive near path signals from the normalization circuit in the first and second modes; wherein the mantissa alignment circuit comprises a right shifter configured to shift a mantissa by a shift value to generate a shifted mantissa; characterized in that the mantissa alignment circuit further comprises: a gating circuit configured to selectively pass through the shifted mantissa and to selectively output only zero bits; and a comparison circuit configured to compare the shift value to a maximum shift value and to control the gating circuit, and wherein the comparison circuit is configured to selectively direct the gating circuit to output only zero bits, if the shift value exceeds the maximum shift value and to pass through the shifted mantissa if the shift value is equal or less than the maximum shift value. a gating circuit configured to selectively pass through the shifted mantissa and to selectively output only zero bits; and a comparison circuit configured to compare the shift value to a maximum shift value and to control the gating circuit, and wherein the comparison circuit is configured to selectively direct the gating circuit to output only zero bits, if the shift value exceeds the maximum shift value and to pass through the shifted mantissa if the shift value is equal or less than the maximum shift value.