A differential signal conditioner circuit with common mode voltage compensation, the differential signal conditioner circuit comprising: a signal multiplexer configured to receive a differential input signal that comprises a high signal and a low signal and a reference CMV signal; a differential amplifier coupled to the signal multiplexer configured to: receive the reference CMV signal from the signal multiplexer and output a CMV error value during a first cycle, and receive the differential input signal from the signal multiplexer and output an amplified difference signal during a second cycle; a CMV measurement circuit configured to: receive the reference CMV signal from the signal multiplexer and output a confirmation value during the first cycle; and receive the differential input signal from the signal multiplexer and output a CMV compensation value during the second cycle; a processing element configured to receive the CMV error value, the amplified difference signal, the CMV compensation value, and a differential amplifier gain value and generate a CMV compensated output based on the CMV error value, the amplified difference signal, the CMV compensation value, and the differential amplifier gain value; and wherein the processing element is configured to generate the CMV compensated output by: dividing the CMV error value by the differential amplifier gain value to produce a scaled CMV error value; multiplying the CMV compensation value with the scaled CMV error value to produce a compensation factor; and adding the compensation factor to the amplified difference signal to produce the CMV compensated output. a signal multiplexer configured to receive a differential input signal that comprises a high signal and a low signal and a reference CMV signal; a differential amplifier coupled to the signal multiplexer configured to: receive the reference CMV signal from the signal multiplexer and output a CMV error value during a first cycle, and receive the differential input signal from the signal multiplexer and output an amplified difference signal during a second cycle; receive the reference CMV signal from the signal multiplexer and output a CMV error value during a first cycle, and receive the differential input signal from the signal multiplexer and output an amplified difference signal during a second cycle; a CMV measurement circuit configured to: receive the reference CMV signal from the signal multiplexer and output a confirmation value during the first cycle; and receive the differential input signal from the signal multiplexer and output a CMV compensation value during the second cycle; receive the reference CMV signal from the signal multiplexer and output a confirmation value during the first cycle; and receive the differential input signal from the signal multiplexer and output a CMV compensation value during the second cycle; a processing element configured to receive the CMV error value, the amplified difference signal, the CMV compensation value, and a differential amplifier gain value and generate a CMV compensated output based on the CMV error value, the amplified difference signal, the CMV compensation value, and the differential amplifier gain value; and wherein the processing element is configured to generate the CMV compensated output by: dividing the CMV error value by the differential amplifier gain value to produce a scaled CMV error value; multiplying the CMV compensation value with the scaled CMV error value to produce a compensation factor; and adding the compensation factor to the amplified difference signal to produce the CMV compensated output. dividing the CMV error value by the differential amplifier gain value to produce a scaled CMV error value; multiplying the CMV compensation value with the scaled CMV error value to produce a compensation factor; and adding the compensation factor to the amplified difference signal to produce the CMV compensated output.