An apparatus, comprising: an output buffer that holds N words arranged as N/J mutually exclusive output buffer word groups of J words each of the N words, J is greater than 3 and N is at least sixteen times J; an array of N processing units, PU, arranged as N/J mutually exclusive PU groups of J PUs each of the N PUs, each PU group of the N/J PU groups has an associated output buffer word group of the N/J output buffer word groups, each PU of the N PUs includes an accumulator having an output and an arithmetic unit that performs operations on inputs, which include the accumulator output, to generate a first result for accumulation into the accumulator; a plurality of activation function units that selectively perform an activation function on the outputs of the accumulators to generate results for provision to the N output buffer words; and for each PU group of the N/J PU groups of J PUs: first, second, third and fourth of the J PUs of the PU group and at least one of the plurality of activation function units compute an input gate, a forget gate, an output gate and a candidate state of a Long Short Term Memory, LSTM, cell, respectively, for writing to respective first, second, third and fourth words of the associated output buffer word group; and wherein each PU comprises: first and second multiplexed registers (208, 705) each having: at least J+1 inputs and an output, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input that controls selection of the J+1 inputs for provision on the output; and the arithmetic unit has first and second inputs to receive the output of the first and second multiplexed registers (208, 705), respectively, and a third input that receives the accumulator output. an output buffer that holds N words arranged as N/J mutually exclusive output buffer word groups of J words each of the N words, J is greater than 3 and N is at least sixteen times J; an array of N processing units, PU, arranged as N/J mutually exclusive PU groups of J PUs each of the N PUs, each PU group of the N/J PU groups has an associated output buffer word group of the N/J output buffer word groups, each PU of the N PUs includes an accumulator having an output and an arithmetic unit that performs operations on inputs, which include the accumulator output, to generate a first result for accumulation into the accumulator; a plurality of activation function units that selectively perform an activation function on the outputs of the accumulators to generate results for provision to the N output buffer words; and for each PU group of the N/J PU groups of J PUs: first, second, third and fourth of the J PUs of the PU group and at least one of the plurality of activation function units compute an input gate, a forget gate, an output gate and a candidate state of a Long Short Term Memory, LSTM, cell, respectively, for writing to respective first, second, third and fourth words of the associated output buffer word group; and wherein each PU comprises: first and second multiplexed registers (208, 705) each having: at least J+1 inputs and an output, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input that controls selection of the J+1 inputs for provision on the output; and the arithmetic unit has first and second inputs to receive the output of the first and second multiplexed registers (208, 705), respectively, and a third input that receives the accumulator output. first and second multiplexed registers (208, 705) each having: at least J+1 inputs and an output, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input that controls selection of the J+1 inputs for provision on the output; and at least J+1 inputs and an output, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input that controls selection of the J+1 inputs for provision on the output; and the arithmetic unit has first and second inputs to receive the output of the first and second multiplexed registers (208, 705), respectively, and a third input that receives the accumulator output.