An apparatus, comprising: an address decoder configured to receive address signals and provide decoded addresses; a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations; and a command/address input circuit configured to receive multilevel command and address signals and provide output signals representing values of the multilevel command and address signals to the address decoder and the command decoder, wherein a plurality of the command and address signals represent a greater plurality of bits, wherein the command/address input circuit comprises: a multilevel input buffer (310, 700, 1110) configured to receive the multilevel command and address signals and provide respective output signals for each of the multilevel command and address signals having logic levels based on the respective multilevel command and address signal; a command and address input decoder circuit (320, 1120) configured to receive the output signals from the multilevel input buffer and configured to provide decoded signals representing the bits of the multilevel command and address signals to the address decoder; and a signal latch configured to latch the output signals from the multilevel input buffer and provide the latched signals to the command decoder. an address decoder configured to receive address signals and provide decoded addresses; a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations; and a command/address input circuit configured to receive multilevel command and address signals and provide output signals representing values of the multilevel command and address signals to the address decoder and the command decoder, wherein a plurality of the command and address signals represent a greater plurality of bits, wherein the command/address input circuit comprises: a multilevel input buffer (310, 700, 1110) configured to receive the multilevel command and address signals and provide respective output signals for each of the multilevel command and address signals having logic levels based on the respective multilevel command and address signal; a command and address input decoder circuit (320, 1120) configured to receive the output signals from the multilevel input buffer and configured to provide decoded signals representing the bits of the multilevel command and address signals to the address decoder; and a signal latch configured to latch the output signals from the multilevel input buffer and provide the latched signals to the command decoder. a multilevel input buffer (310, 700, 1110) configured to receive the multilevel command and address signals and provide respective output signals for each of the multilevel command and address signals having logic levels based on the respective multilevel command and address signal; a command and address input decoder circuit (320, 1120) configured to receive the output signals from the multilevel input buffer and configured to provide decoded signals representing the bits of the multilevel command and address signals to the address decoder; and a signal latch configured to latch the output signals from the multilevel input buffer and provide the latched signals to the command decoder.