An apparatus, comprising: a first transistor having a control gate coupled to a first signal line, wherein when the first transistor is configured to a low impedance state the first transistor couples a portion of a memory array to sense circuitry (330, 430); and a second transistor having a control gate coupled to a logic gate combining a signal of the first signal line and a signal of a second signal line, wherein when the second transistor is configured to a low impedance state the second transistor couples a portion of the memory array to program circuitry (332, 432); wherein the first transistor and the second transistor comprise different types of transistors; wherein the sense circuitry (330, 430) comprises a third transistor coupled in series with the first transistor; characterised in that: the logic gate is configured such that the second transistor is configured to be in a high impedance state when the first transistor is configured to be in a high impedance state, the second transistor is configured to be in the high impedance state when the first transistor is configured to be in the low impedance state and the signal of the second signal line has a first logic level, and the second transistor is configured to be in the low impedance state when the first transistor is configured to be in the low impedance state and the signal of the second signal line has a second logic level different than the first logic level; and the third transistor is configured to be in the low impedance state when the first transistor is configured to be in the low impedance state and the second transistor is configured to be in the high impedance state, and the third transistor is further configured to be in the high impedance state when the first transistor is configured to be in the low impedance state and the second transistor is configured to be in the low impedance state. a first transistor having a control gate coupled to a first signal line, wherein when the first transistor is configured to a low impedance state the first transistor couples a portion of a memory array to sense circuitry (330, 430); and a second transistor having a control gate coupled to a logic gate combining a signal of the first signal line and a signal of a second signal line, wherein when the second transistor is configured to a low impedance state the second transistor couples a portion of the memory array to program circuitry (332, 432); wherein the first transistor and the second transistor comprise different types of transistors; wherein the sense circuitry (330, 430) comprises a third transistor coupled in series with the first transistor; characterised in that: the logic gate is configured such that the second transistor is configured to be in a high impedance state when the first transistor is configured to be in a high impedance state, the second transistor is configured to be in the high impedance state when the first transistor is configured to be in the low impedance state and the signal of the second signal line has a first logic level, and the second transistor is configured to be in the low impedance state when the first transistor is configured to be in the low impedance state and the signal of the second signal line has a second logic level different than the first logic level; and the third transistor is configured to be in the low impedance state when the first transistor is configured to be in the low impedance state and the second transistor is configured to be in the high impedance state, and the third transistor is further configured to be in the high impedance state when the first transistor is configured to be in the low impedance state and the second transistor is configured to be in the low impedance state. the logic gate is configured such that the second transistor is configured to be in a high impedance state when the first transistor is configured to be in a high impedance state, the second transistor is configured to be in the high impedance state when the first transistor is configured to be in the low impedance state and the signal of the second signal line has a first logic level, and the second transistor is configured to be in the low impedance state when the first transistor is configured to be in the low impedance state and the signal of the second signal line has a second logic level different than the first logic level; and the third transistor is configured to be in the low impedance state when the first transistor is configured to be in the low impedance state and the second transistor is configured to be in the high impedance state, and the third transistor is further configured to be in the high impedance state when the first transistor is configured to be in the low impedance state and the second transistor is configured to be in the low impedance state.