A thin film transistor array panel comprising: a substrate; a gate line elongated in a first direction and comprising a gate electrode and a dummy gate electrode extended therefrom and disposed on the substrate; a gate insulating layer on the gate electrode and the dummy gate electrode; a semiconductor on the gate insulating layer; and a source electrode and a drain electrode (175a, 175b) disposed on the semiconductor, the drain electrode (175a, 175b) comprising a first drain electrode portion at a first end of the drain electrode (175a, 175b) and a second drain electrode portion at an opposing second end of the drain electrode (175a, 175b), wherein the first drain electrode portion faces the source electrode with respect to the gate electrode to form a thin film transistor together with the semiconductor, the first drain electrode portion comprises a plurality of first regions (R1, R2, R3) each having a predetermined width in the first direction, respectively, wherein at least one of the plurality of first regions (R1, R2, R3) overlaps the gate electrode in a first overlapping region, the second drain electrode portion comprises a plurality of second regions (R4, R5, R6) each having a predetermined width in the first direction, respectively, wherein at least one of the plurality of second regions (R4, R5, R6) overlaps the dummy gate electrode in a second overlapping region, at least one region of the plurality of first regions (R1, R2, R3) of the drain electrode comprises an edge which forms an angle from 0 degrees to 90 degrees with the first direction, at least one of the plurality of second regions (R4, R5, R6) comprises an edge which forms an angle from 0 degrees to 90 degrees with the first direction, planar areas of the plurality of first regions (R1, R2, R3) and planar areas of the plurality of second regions (R4, R5, R6) one of increase or decrease in the first direction away from the source electrode, and a planar area of the at least one of the plurality of first regions (R1, R2, R3) overlapping the gate electrode in a first overlapping region is the same as a planar area of the at least one of the plurality of second regions (R4, R5, R6) overlapping the dummy gate electrode in a second overlapping region. a substrate; a gate line elongated in a first direction and comprising a gate electrode and a dummy gate electrode extended therefrom and disposed on the substrate; a gate insulating layer on the gate electrode and the dummy gate electrode; a semiconductor on the gate insulating layer; and a source electrode and a drain electrode (175a, 175b) disposed on the semiconductor, the drain electrode (175a, 175b) comprising a first drain electrode portion at a first end of the drain electrode (175a, 175b) and a second drain electrode portion at an opposing second end of the drain electrode (175a, 175b), wherein the first drain electrode portion faces the source electrode with respect to the gate electrode to form a thin film transistor together with the semiconductor, the first drain electrode portion comprises a plurality of first regions (R1, R2, R3) each having a predetermined width in the first direction, respectively, wherein at least one of the plurality of first regions (R1, R2, R3) overlaps the gate electrode in a first overlapping region, the second drain electrode portion comprises a plurality of second regions (R4, R5, R6) each having a predetermined width in the first direction, respectively, wherein at least one of the plurality of second regions (R4, R5, R6) overlaps the dummy gate electrode in a second overlapping region, at least one region of the plurality of first regions (R1, R2, R3) of the drain electrode comprises an edge which forms an angle from 0 degrees to 90 degrees with the first direction, at least one of the plurality of second regions (R4, R5, R6) comprises an edge which forms an angle from 0 degrees to 90 degrees with the first direction, planar areas of the plurality of first regions (R1, R2, R3) and planar areas of the plurality of second regions (R4, R5, R6) one of increase or decrease in the first direction away from the source electrode, and a planar area of the at least one of the plurality of first regions (R1, R2, R3) overlapping the gate electrode in a first overlapping region is the same as a planar area of the at least one of the plurality of second regions (R4, R5, R6) overlapping the dummy gate electrode in a second overlapping region.