A circuit arrangement comprising: one or more input buffers (312, 314,..., 316) disposed on a system-on-chip (SoC) and configured to receive and store a plurality of streaming debug packets; one or more response buffers (328, 330,..., 332) disposed on the SoC; a transaction control circuit disposed on the SoC and coupled to the one or more input buffers and to the one or more response buffers, wherein the transaction control circuit is configured to process each debug packet in the one or more input buffers by: in a first mode, determine, in response to an input debug packet, if space is available in the one or more input buffers for the input debug packet, and store, in response to determining that space is available, the input debug packet in one of the one or more input buffers; decoding an operation code in the debug packet, determining from an address in the debug packet, an interface circuit of a plurality of interface circuits to access a storage circuit in a subsystem of a plurality of sub-systems on the SoC, issue a request via the interface circuit to access the storage circuit according to the operation code, in a second mode, repeat, for a debug packet in the input buffer, the decoding of the operation code in the debug packet, determining the interface circuit, and issuing the request a plurality of times, and store responses and data received from the plurality of interface circuits in the one or more response buffers. one or more input buffers (312, 314,..., 316) disposed on a system-on-chip (SoC) and configured to receive and store a plurality of streaming debug packets; one or more response buffers (328, 330,..., 332) disposed on the SoC; a transaction control circuit disposed on the SoC and coupled to the one or more input buffers and to the one or more response buffers, wherein the transaction control circuit is configured to process each debug packet in the one or more input buffers by: in a first mode, determine, in response to an input debug packet, if space is available in the one or more input buffers for the input debug packet, and store, in response to determining that space is available, the input debug packet in one of the one or more input buffers; decoding an operation code in the debug packet, determining from an address in the debug packet, an interface circuit of a plurality of interface circuits to access a storage circuit in a subsystem of a plurality of sub-systems on the SoC, issue a request via the interface circuit to access the storage circuit according to the operation code, in a second mode, repeat, for a debug packet in the input buffer, the decoding of the operation code in the debug packet, determining the interface circuit, and issuing the request a plurality of times, and store responses and data received from the plurality of interface circuits in the one or more response buffers. in a first mode, determine, in response to an input debug packet, if space is available in the one or more input buffers for the input debug packet, and store, in response to determining that space is available, the input debug packet in one of the one or more input buffers; determine, in response to an input debug packet, if space is available in the one or more input buffers for the input debug packet, and store, in response to determining that space is available, the input debug packet in one of the one or more input buffers; decoding an operation code in the debug packet, determining from an address in the debug packet, an interface circuit of a plurality of interface circuits to access a storage circuit in a subsystem of a plurality of sub-systems on the SoC, issue a request via the interface circuit to access the storage circuit according to the operation code, in a second mode, repeat, for a debug packet in the input buffer, the decoding of the operation code in the debug packet, determining the interface circuit, and issuing the request a plurality of times, and store responses and data received from the plurality of interface circuits in the one or more response buffers.