A processor, comprising: at least one processing complex comprising at least one processing core and at least one cache memory; and a neural network unit, NNU,, comprising: an array of neural processing units, NPU,; cache control logic; and a memory array selectively coupled to the array of NPUs and to the cache control logic; characterised in that to transition from a first mode in which the memory array operates to hold neural network weights to be read by the array of NPUs to a second mode in which the memory array and cache control logic operate as a victim cache for the processing complex: the cache control logic is configured to begin to cache evicted cache lines into the memory array in response to eviction requests received from the processing complex; and the cache control logic is configured to begin to provide to the processing complex cache lines that hit in the memory array in response to load requests from the processing complex; and wherein to transition from the second mode to the first mode: the cache control logic is configured to invalidate all cache lines of the memory array; the cache control logic is configured to cease to cache evicted cache lines into the memory array in response to eviction requests received from the processing complex; and the cache control logic is configured to cease to provide to the processing complex cache lines in response to load requests received from the processing complex. at least one processing complex comprising at least one processing core and at least one cache memory; and a neural network unit, NNU,, comprising: an array of neural processing units, NPU,; cache control logic; and a memory array selectively coupled to the array of NPUs and to the cache control logic; characterised in that to transition from a first mode in which the memory array operates to hold neural network weights to be read by the array of NPUs to a second mode in which the memory array and cache control logic operate as a victim cache for the processing complex: the cache control logic is configured to begin to cache evicted cache lines into the memory array in response to eviction requests received from the processing complex; and the cache control logic is configured to begin to provide to the processing complex cache lines that hit in the memory array in response to load requests from the processing complex; and an array of neural processing units, NPU,; cache control logic; and a memory array selectively coupled to the array of NPUs and to the cache control logic; characterised in that to transition from a first mode in which the memory array operates to hold neural network weights to be read by the array of NPUs to a second mode in which the memory array and cache control logic operate as a victim cache for the processing complex: the cache control logic is configured to begin to cache evicted cache lines into the memory array in response to eviction requests received from the processing complex; and the cache control logic is configured to begin to provide to the processing complex cache lines that hit in the memory array in response to load requests from the processing complex; and wherein to transition from the second mode to the first mode: the cache control logic is configured to invalidate all cache lines of the memory array; the cache control logic is configured to cease to cache evicted cache lines into the memory array in response to eviction requests received from the processing complex; and the cache control logic is configured to cease to provide to the processing complex cache lines in response to load requests received from the processing complex. the cache control logic is configured to invalidate all cache lines of the memory array; the cache control logic is configured to cease to cache evicted cache lines into the memory array in response to eviction requests received from the processing complex; and the cache control logic is configured to cease to provide to the processing complex cache lines in response to load requests received from the processing complex.