A sigma-delta modulator comprising: - a plurality of capacitor pairs; - a plurality of switches (220..250) configured to couple any pair of capacitors from said plurality of capacitor pairs selectively to a differential input signal or a differential reference signal, wherein the differential reference signal is provided by at least one digital-to-analog converter; and - control means operable to control sampling through said switches (220..250) to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the differential input signal or the differential reference signal, - wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the differential input signal, and has also been assigned a second predetermined number of times to the differential reference signal, and - wherein the digital-to-analog converter is a single-bit or a multi-bit digital-to-analog converter, wherein a rotation sequence of said differential input signal and said differential reference signal to respective pairs of capacitors is controlled at every sample such that for the same DAC input values for sequential samples the differential input signal is sequentially assigned to different pairs of the plurality of capacitor pairs and the differential reference signal is sequentially assigned to respective other pairs of the plurality of capacitor pairs according to a predefined rotation cycle sequence. - a plurality of capacitor pairs; - a plurality of switches (220..250) configured to couple any pair of capacitors from said plurality of capacitor pairs selectively to a differential input signal or a differential reference signal, wherein the differential reference signal is provided by at least one digital-to-analog converter; and - control means operable to control sampling through said switches (220..250) to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the differential input signal or the differential reference signal, - wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the differential input signal, and has also been assigned a second predetermined number of times to the differential reference signal, and - wherein the digital-to-analog converter is a single-bit or a multi-bit digital-to-analog converter, wherein a rotation sequence of said differential input signal and said differential reference signal to respective pairs of capacitors is controlled at every sample such that for the same DAC input values for sequential samples the differential input signal is sequentially assigned to different pairs of the plurality of capacitor pairs and the differential reference signal is sequentially assigned to respective other pairs of the plurality of capacitor pairs according to a predefined rotation cycle sequence.