A spiking neuron-based working memory device, comprising: an input interface configured to convert input spike signals into respective burst signals having predetermined forms, and output a sequence of the burst signals, the burst signals corresponding to the input spike signals in a burst structure; and two or more memory elements, MEs (120,...,140), configured to sequentially store burst signals respectively corresponding to the outputted sequence of the burst signals, each j of the MEs continuously outputting spike signals respectively corresponding to the stored burst signals, wherein, when one of the burst signals respectively corresponding to one of the burst signals is stored in one of the MEs, the one of the MEs is deactivated and activates a subsequent one of the MEs, and wherein each of the MEs comprises gate neurons (821, 822, 823), a continuity unit, and a control neuron, the gate neurons (821, 822, 823) being configured, when activated, to transfer the burst signals received from the input interface to the continuity unit, the continuity unit being configured, when a reset signal is input, to output an idle signal to the next ME, the continuity unit being further configured, when the transferred burst signals are input, to activate one or more neurons corresponding to the input values respectively corresponding to the transferred burst signals, the continuity unit being further configured to continuously output the spike signals respectively corresponding to the input values until a reset signal is input, the continuity unit being further configured, when the burst signals are stored, to interrupt outputting the idle signal to the next ME the control neuron being configured, when a previous ME interrupts outputting an idle signal to the control neuron to activate the gate neurons (821, 822, 823), the control neuron being further configured, when the continuity unit outputs the spike signals, to suppress the gate neurons (821, 822, 823). an input interface configured to convert input spike signals into respective burst signals having predetermined forms, and output a sequence of the burst signals, the burst signals corresponding to the input spike signals in a burst structure; and two or more memory elements, MEs (120,...,140), configured to sequentially store burst signals respectively corresponding to the outputted sequence of the burst signals, each j of the MEs continuously outputting spike signals respectively corresponding to the stored burst signals, wherein, when one of the burst signals respectively corresponding to one of the burst signals is stored in one of the MEs, the one of the MEs is deactivated and activates a subsequent one of the MEs, and wherein each of the MEs comprises gate neurons (821, 822, 823), a continuity unit, and a control neuron, the gate neurons (821, 822, 823) being configured, when activated, to transfer the burst signals received from the input interface to the continuity unit, the continuity unit being configured, when a reset signal is input, to output an idle signal to the next ME, the continuity unit being further configured, when the transferred burst signals are input, to activate one or more neurons corresponding to the input values respectively corresponding to the transferred burst signals, the continuity unit being further configured to continuously output the spike signals respectively corresponding to the input values until a reset signal is input, the continuity unit being further configured, when the burst signals are stored, to interrupt outputting the idle signal to the next ME the control neuron being configured, when a previous ME interrupts outputting an idle signal to the control neuron to activate the gate neurons (821, 822, 823), the control neuron being further configured, when the continuity unit outputs the spike signals, to suppress the gate neurons (821, 822, 823).