A bias circuit for an RF bipolar amplifier, the bias circuit comprising: a first bias circuit terminal configured to be coupled to a base of a common-base transistor of the RF bipolar amplifier; a second bias circuit terminal configured to be coupled to a base of a common-emitter transistor of the RF bipolar amplifier; a current source coupled between a bias supply voltage rail and a collector of a first bias transistor; a bias network coupled to the current source, the first bias circuit terminal, and the second bias circuit terminal; and a buffer amplifier having an input coupled to the collector of the first bias transistor and an output coupled to the first bias circuit terminal; wherein the buffer amplifier is configured to at least partially source current provided to the first bias circuit terminal and to sink current from the first bias circuit terminal; and wherein the bias network is configured to provide a current to the first bias circuit terminal and the second bias circuit terminal, and wherein the bias network comprises: the first bias transistor, a second bias transistor, a third bias transistor, a second bias resistor, and a third bias resistor, wherein the first bias transistor and third bias transistor are arranged in a cascode stack between the current source and a common supply rail, the first bias transistor having a base coupled to the first bias circuit terminal and the third bias transistor having a base coupled to the second bias circuit terminal; and the second bias transistor having a base coupled to the first bias transistor base, a collector coupled to the bias supply voltage rail, and an emitter coupled to the common supply rail through a series arrangement of the second bias resistor and the third bias resistor, wherein the third bias transistor base is coupled to a common node between the second bias resistor and the third bias resistor. a first bias circuit terminal configured to be coupled to a base of a common-base transistor of the RF bipolar amplifier; a second bias circuit terminal configured to be coupled to a base of a common-emitter transistor of the RF bipolar amplifier; a current source coupled between a bias supply voltage rail and a collector of a first bias transistor; a bias network coupled to the current source, the first bias circuit terminal, and the second bias circuit terminal; and a buffer amplifier having an input coupled to the collector of the first bias transistor and an output coupled to the first bias circuit terminal; wherein the buffer amplifier is configured to at least partially source current provided to the first bias circuit terminal and to sink current from the first bias circuit terminal; and wherein the bias network is configured to provide a current to the first bias circuit terminal and the second bias circuit terminal, and wherein the bias network comprises: the first bias transistor, a second bias transistor, a third bias transistor, a second bias resistor, and a third bias resistor, wherein the first bias transistor and third bias transistor are arranged in a cascode stack between the current source and a common supply rail, the first bias transistor having a base coupled to the first bias circuit terminal and the third bias transistor having a base coupled to the second bias circuit terminal; and the second bias transistor having a base coupled to the first bias transistor base, a collector coupled to the bias supply voltage rail, and an emitter coupled to the common supply rail through a series arrangement of the second bias resistor and the third bias resistor, wherein the third bias transistor base is coupled to a common node between the second bias resistor and the third bias resistor. the first bias transistor, a second bias transistor, a third bias transistor, a second bias resistor, and a third bias resistor, wherein the first bias transistor and third bias transistor are arranged in a cascode stack between the current source and a common supply rail, the first bias transistor having a base coupled to the first bias circuit terminal and the third bias transistor having a base coupled to the second bias circuit terminal; and the second bias transistor having a base coupled to the first bias transistor base, a collector coupled to the bias supply voltage rail, and an emitter coupled to the common supply rail through a series arrangement of the second bias resistor and the third bias resistor, wherein the third bias transistor base is coupled to a common node between the second bias resistor and the third bias resistor.