A hardware accelerator system for signature matching in a distributed network system comprising one or more hardware accelerator circuits (160a-d; 180a-d), wherein each of the hardware accelerator circuit utilizes a compressed deterministic finite automata, DFA, comprising a state table defined by a plurality of states and a plurality of characters, the state table representing a database of digital signatures, wherein the plurality of states are divided into groups (Group 0, Group 1), each group comprising a leader state (252, 254) having a plurality of leader state transitions (252a-f, 254n; 254a-f; 254g) and one or more member states (255, 253), each having a plurality of member state transitions, the one or more hardware accelerators (160a-d; 180a-d) comprising: a memory circuit characterized in that the memory circuit is configured to store, leader state transitions that are unique for each leader state within each group of the compressed DFA, for each leader state in each group, a single occurrence of a most repeated leader state transition from the plurality of leader state transitions, wherein the unique leader state transitions comprises the leader state transitions that are different from the most repeated leader state transition within the respective group; and leader transition bitmasks associated respectively with the leader states (252, 254) within each group (Group 0, Group 1), wherein each of the leader transition bitmasks comprises a plurality of leader bitmasks that identify the unique leader state transitions from the plurality of leader state transitions with each group, wherein the memory circuit is further configured to store, member state transitions that are unique for each member state within each group of the compressed DFA, wherein the unique member state transitions comprise the member state transitions that are different from the leader state transitions for a respective character within the respective group; and member transition bitmasks associated respectively with the one or more member states, wherein each of the member transition bitmasks comprises a plurality of member bitmasks that identify the unique member state transitions for each member state within each group of the compressed DFA. a memory circuit characterized in that the memory circuit is configured to store, leader state transitions that are unique for each leader state within each group of the compressed DFA, for each leader state in each group, a single occurrence of a most repeated leader state transition from the plurality of leader state transitions, wherein the unique leader state transitions comprises the leader state transitions that are different from the most repeated leader state transition within the respective group; and leader transition bitmasks associated respectively with the leader states (252, 254) within each group (Group 0, Group 1), wherein each of the leader transition bitmasks comprises a plurality of leader bitmasks that identify the unique leader state transitions from the plurality of leader state transitions with each group, wherein the memory circuit is further configured to store, member state transitions that are unique for each member state within each group of the compressed DFA, wherein the unique member state transitions comprise the member state transitions that are different from the leader state transitions for a respective character within the respective group; and member transition bitmasks associated respectively with the one or more member states, wherein each of the member transition bitmasks comprises a plurality of member bitmasks that identify the unique member state transitions for each member state within each group of the compressed DFA.