An organic electroluminescent device (OELD) comprising: a first substrate including a pixel region that includes an element region and a light emission region; a storage capacitor (StgC) disposed outside of the light emission region and all over the element region and disposed on the first substrate, and including a first storage electrode, a first buffer layer on the first storage electrode, and a second storage electrode on the first buffer layer; a second buffer layer on the storage capacitor (StgC); a plurality of TFTs (STr, DTr) including a driving TFT (DTr) and a switching TFT (STr) on the second buffer layer within the element region; wherein each TFT of the plurality of TFTs (STr, DTr) includes: a semiconductor layer (113, 115); a gate insulating layer on the semiconductor layer (113, 115); a gate electrode (120a, 120b) on the gate insulating layer; an inter-layer insulating layer on the gate electrode (120a, 120b), and including semiconductor contact holes exposing the semiconductor layer (113, 115); and a source electrode and a drain electrode (136a, 136b) on the inter-layer insulating layer, and contacting the semiconductor layer (113, 115) through the corresponding semiconductor contact holes, a passivation layer on the plurality of TFTs (STr, DTr); and a first auxiliary pattern, which is on the inter-layer insulating layer, connected to the second storage electrode through a storage contact hole (sch) that is formed between the switching TFT (STr) and the driving TFT (DTr) in the inter-layer insulating layer, the gate insulating layer and the second buffer layer to expose the second storage electrode, wherein the first auxiliary pattern is connected to a gate electrode of the driving TFT (DTr) and a drain electrode of the switching TFT (STr), and wherein the storage capacitor (StgC) overlaps the driving TFT (DTr) and the switching TFT (STr). a first substrate including a pixel region that includes an element region and a light emission region; a storage capacitor (StgC) disposed outside of the light emission region and all over the element region and disposed on the first substrate, and including a first storage electrode, a first buffer layer on the first storage electrode, and a second storage electrode on the first buffer layer; a second buffer layer on the storage capacitor (StgC); a plurality of TFTs (STr, DTr) including a driving TFT (DTr) and a switching TFT (STr) on the second buffer layer within the element region; wherein each TFT of the plurality of TFTs (STr, DTr) includes: a semiconductor layer (113, 115); a gate insulating layer on the semiconductor layer (113, 115); a gate electrode (120a, 120b) on the gate insulating layer; an inter-layer insulating layer on the gate electrode (120a, 120b), and including semiconductor contact holes exposing the semiconductor layer (113, 115); and a source electrode and a drain electrode (136a, 136b) on the inter-layer insulating layer, and contacting the semiconductor layer (113, 115) through the corresponding semiconductor contact holes, a plurality of TFTs (STr, DTr) including a driving TFT (DTr) and a switching TFT (STr) on the second buffer layer within the element region; wherein each TFT of the plurality of TFTs (STr, DTr) includes: a semiconductor layer (113, 115); a gate insulating layer on the semiconductor layer (113, 115); a gate electrode (120a, 120b) on the gate insulating layer; an inter-layer insulating layer on the gate electrode (120a, 120b), and including semiconductor contact holes exposing the semiconductor layer (113, 115); and a source electrode and a drain electrode (136a, 136b) on the inter-layer insulating layer, and contacting the semiconductor layer (113, 115) through the corresponding semiconductor contact holes, a semiconductor layer (113, 115); a gate insulating layer on the semiconductor layer (113, 115); a gate electrode (120a, 120b) on the gate insulating layer; an inter-layer insulating layer on the gate electrode (120a, 120b), and including semiconductor contact holes exposing the semiconductor layer (113, 115); and a source electrode and a drain electrode (136a, 136b) on the inter-layer insulating layer, and contacting the semiconductor layer (113, 115) through the corresponding semiconductor contact holes, a passivation layer on the plurality of TFTs (STr, DTr); and a first auxiliary pattern, which is on the inter-layer insulating layer, connected to the second storage electrode through a storage contact hole (sch) that is formed between the switching TFT (STr) and the driving TFT (DTr) in the inter-layer insulating layer, the gate insulating layer and the second buffer layer to expose the second storage electrode, wherein the first auxiliary pattern is connected to a gate electrode of the driving TFT (DTr) and a drain electrode of the switching TFT (STr), and wherein the storage capacitor (StgC) overlaps the driving TFT (DTr) and the switching TFT (STr).