A non-volatile memory cell (010, 100, 300, 500, 700, 800, 910) comprising: a coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921) formed on a first well (110, 310, 510, 710, 810, 920) and is coupled to a source line; a read device (012, D12, P12, D32, N32, D52, P52, D72, N72, D82, 922) electrically connected to a first bit line (BLr), a first word line (WLr), and the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921); characterized by a program module coupled to a second bit line (BLp) and a second word line (WLp), the program module comprising: a floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932) formed on a second well (120, 320, 520, 720, 820, 930) and is coupled to the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921); and a program device (D14, N11, D34, N33, D54, N51, D74, N74, D84, 931) electrically connected to the floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932) and formed on the second well (120, 320, 520, 720, 820, 930); and an erase device (014, D15, P13, D35, P31, D55, P54, D75, P71, D85, 941) formed on a third well (130, 330, 530, 730, 830, 940) and is coupled to an erase line; wherein the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921), the floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932)and the erase device (014, D15, P13, D35, P31, D55, P54, D75, P71, D85, 941) are coupled by a common floating gate (114, 314, 514, 714, 814); wherein a gate of the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, 921) is a first part of the common floating gate (114, 314, 514, 714) formed on the first well (110, 310, 510, 710, 920), a gate (115, 315, 515, 715) of the read device (012, D12, P12, D32, N32, D52, P52, D72, N72, 922) is formed on the first well (110, 310, 510, 710, 920), and a second terminal (112, 312, 512, 712) of the read device (012, D12, P12, D32, N32, D52, P52, D72, N72, 922) is electrically coupled to a first terminal (112, 312, 512, 712) of the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, 921). a coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921) formed on a first well (110, 310, 510, 710, 810, 920) and is coupled to a source line; a read device (012, D12, P12, D32, N32, D52, P52, D72, N72, D82, 922) electrically connected to a first bit line (BLr), a first word line (WLr), and the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921); characterized by a program module coupled to a second bit line (BLp) and a second word line (WLp), the program module comprising: a floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932) formed on a second well (120, 320, 520, 720, 820, 930) and is coupled to the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921); and a program device (D14, N11, D34, N33, D54, N51, D74, N74, D84, 931) electrically connected to the floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932) and formed on the second well (120, 320, 520, 720, 820, 930); and a floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932) formed on a second well (120, 320, 520, 720, 820, 930) and is coupled to the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921); and a program device (D14, N11, D34, N33, D54, N51, D74, N74, D84, 931) electrically connected to the floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932) and formed on the second well (120, 320, 520, 720, 820, 930); and an erase device (014, D15, P13, D35, P31, D55, P54, D75, P71, D85, 941) formed on a third well (130, 330, 530, 730, 830, 940) and is coupled to an erase line; wherein the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, D81, 921), the floating gate device (D13, N12, D33, N34, D53, N52, D73, N75, D83, 932)and the erase device (014, D15, P13, D35, P31, D55, P54, D75, P71, D85, 941) are coupled by a common floating gate (114, 314, 514, 714, 814); wherein a gate of the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, 921) is a first part of the common floating gate (114, 314, 514, 714) formed on the first well (110, 310, 510, 710, 920), a gate (115, 315, 515, 715) of the read device (012, D12, P12, D32, N32, D52, P52, D72, N72, 922) is formed on the first well (110, 310, 510, 710, 920), and a second terminal (112, 312, 512, 712) of the read device (012, D12, P12, D32, N32, D52, P52, D72, N72, 922) is electrically coupled to a first terminal (112, 312, 512, 712) of the coupling device (011, D11, P11, D31, N31, D51, P51, D71, N71, 921).