A method for forming a 3D memory device, comprising: forming an alternating layer stack (102, 104, 106, 108, 110, 112) comprising a plurality of dielectric layer pairs (SC1A, SC2A) disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region (480 A, 490 A) comprising a number of N sub-staircase regions (481, 482, 483, 484, 485, 486) over the alternating layer stack wherein N is greater than 1; forming a first staircase structure (580A, 580B) over the staircase region (480 A, 490 A), the first staircase structure (580A, 580B) having a number of M steps at each of the sub-staircase regions (481, 482, 483, 484, 485, 486) wherein M is greater than 1, so that in each sub-staircase region, each dielectric layer pair of the topmost M dielectric layers pairs is exposed; and forming a second staircase structure (680A, 680B) starting from the first staircase structure (580A, 580B), wherein forming the second staircase structure comprises: applying a repetitive etch-trim process using a second mask stack formed and patterned over a top surface of the first staircase structure, the second mask stack exposing a first portion (S1A, S1B) of the staircase region (580A, 580B) so that M steps of the first sub-staircase of the staircase region (580A, 580B) are exposed, and removing M levels of the dielectric layer pairs (SC1A, SC2A) in the exposed first portion, trimming the second mask to further expose a second portion (S2A, S2B) of each of the staircase regions (580A, 580B), and removing further M levels of the dielectric layer pairs (SC1A, SC2A) in the exposed first and second portions, repeating the removing-trimming process for each respective first portion (S1A, S1B) and each respective second portion (S2A, S2B) of each subsequent sub-staircase region of the staircase region (580A, 580B) in a first direction until the top surface of each of the dielectric layer pairs (SC1A, SC2A) is exposed for electrical connection, so that after forming the second staircase structure, a number of 2 *N *M steps are present at the staircase region, each of the N sub-staircase regions comprises 2 *M steps and each step is at a different level. forming an alternating layer stack (102, 104, 106, 108, 110, 112) comprising a plurality of dielectric layer pairs (SC1A, SC2A) disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region (480 A, 490 A) comprising a number of N sub-staircase regions (481, 482, 483, 484, 485, 486) over the alternating layer stack wherein N is greater than 1; forming a first staircase structure (580A, 580B) over the staircase region (480 A, 490 A), the first staircase structure (580A, 580B) having a number of M steps at each of the sub-staircase regions (481, 482, 483, 484, 485, 486) wherein M is greater than 1, so that in each sub-staircase region, each dielectric layer pair of the topmost M dielectric layers pairs is exposed; and forming a second staircase structure (680A, 680B) starting from the first staircase structure (580A, 580B), wherein forming the second staircase structure comprises: applying a repetitive etch-trim process using a second mask stack formed and patterned over a top surface of the first staircase structure, the second mask stack exposing a first portion (S1A, S1B) of the staircase region (580A, 580B) so that M steps of the first sub-staircase of the staircase region (580A, 580B) are exposed, and removing M levels of the dielectric layer pairs (SC1A, SC2A) in the exposed first portion, trimming the second mask to further expose a second portion (S2A, S2B) of each of the staircase regions (580A, 580B), and removing further M levels of the dielectric layer pairs (SC1A, SC2A) in the exposed first and second portions, repeating the removing-trimming process for each respective first portion (S1A, S1B) and each respective second portion (S2A, S2B) of each subsequent sub-staircase region of the staircase region (580A, 580B) in a first direction until the top surface of each of the dielectric layer pairs (SC1A, SC2A) is exposed for electrical connection, so that after forming the second staircase structure, a number of 2 *N *M steps are present at the staircase region, each of the N sub-staircase regions comprises 2 *M steps and each step is at a different level. applying a repetitive etch-trim process using a second mask stack formed and patterned over a top surface of the first staircase structure, the second mask stack exposing a first portion (S1A, S1B) of the staircase region (580A, 580B) so that M steps of the first sub-staircase of the staircase region (580A, 580B) are exposed, and removing M levels of the dielectric layer pairs (SC1A, SC2A) in the exposed first portion, trimming the second mask to further expose a second portion (S2A, S2B) of each of the staircase regions (580A, 580B), and removing further M levels of the dielectric layer pairs (SC1A, SC2A) in the exposed first and second portions, repeating the removing-trimming process for each respective first portion (S1A, S1B) and each respective second portion (S2A, S2B) of each subsequent sub-staircase region of the staircase region (580A, 580B) in a first direction until the top surface of each of the dielectric layer pairs (SC1A, SC2A) is exposed for electrical connection, so that after forming the second staircase structure, a number of 2 *N *M steps are present at the staircase region, each of the N sub-staircase regions comprises 2 *M steps and each step is at a different level.