A superconductive gate system comprising: a Josephson D-gate circuit comprising a plurality of Josephson junctions and a bi-stable loop, the Josephson D-gate circuit being configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum, SFQ, pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input, the digital state being provided at an output, wherein the plurality of Josephson junctions of the Josephson D-gate circuit comprises a first Josephson junction (JJ 1) associated with the enable input, a second Josephson junction (JJ 2) associated with the data input, a third Josephson junction (JJ 3) interconnecting the enable input and the first Josephson junction (JJ 1), and a fourth Josephson junction (JJ 4) interconnecting the data input and the second Josephson junction (JJ 2), wherein the output is coupled to a node interconnecting the first Josephson junction (JJ 1) and the third Josephson junction (JJ 3), and wherein the digital state corresponds to a superconducting phase associated with the first Josephson junction (JJ 1); a first bias transformer interconnecting the first Josephson junction (JJ 1) and the second Josephson junction (JJ 2) and being configured to induce a bias in the bi-stable loop in response to a bias current (I BIAS); a second bias transformer coupled to a node interconnecting the second Josephson junction (JJ 2) and the fourth Josephson junction (JJ 4) and being configured to induce a bias in the fourth Josephson junction (JJ 4) in response to the bias current (I BIAS); and a readout circuit coupled to the output and being configured to reproduce the digital state as an output signal. a Josephson D-gate circuit comprising a plurality of Josephson junctions and a bi-stable loop, the Josephson D-gate circuit being configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum, SFQ, pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input, the digital state being provided at an output, wherein the plurality of Josephson junctions of the Josephson D-gate circuit comprises a first Josephson junction (JJ 1) associated with the enable input, a second Josephson junction (JJ 2) associated with the data input, a third Josephson junction (JJ 3) interconnecting the enable input and the first Josephson junction (JJ 1), and a fourth Josephson junction (JJ 4) interconnecting the data input and the second Josephson junction (JJ 2), wherein the output is coupled to a node interconnecting the first Josephson junction (JJ 1) and the third Josephson junction (JJ 3), and wherein the digital state corresponds to a superconducting phase associated with the first Josephson junction (JJ 1); a first Josephson junction (JJ 1) associated with the enable input, a second Josephson junction (JJ 2) associated with the data input, a third Josephson junction (JJ 3) interconnecting the enable input and the first Josephson junction (JJ 1), and a fourth Josephson junction (JJ 4) interconnecting the data input and the second Josephson junction (JJ 2), wherein the output is coupled to a node interconnecting the first Josephson junction (JJ 1) and the third Josephson junction (JJ 3), and wherein the digital state corresponds to a superconducting phase associated with the first Josephson junction (JJ 1); a first bias transformer interconnecting the first Josephson junction (JJ 1) and the second Josephson junction (JJ 2) and being configured to induce a bias in the bi-stable loop in response to a bias current (I BIAS); a second bias transformer coupled to a node interconnecting the second Josephson junction (JJ 2) and the fourth Josephson junction (JJ 4) and being configured to induce a bias in the fourth Josephson junction (JJ 4) in response to the bias current (I BIAS); and a readout circuit coupled to the output and being configured to reproduce the digital state as an output signal.