A peak-buck peak-boost control circuit (501, 601, 700) adapted to be placed in a voltage regulator (500, 600), the peak-buck peak-boost control circuit being adapted to select in which one of a peak-buck buck mode, a peak-buck buck-boost mode, a peak-boost buck-boost mode and a peak-boost boost mode of operation the voltage regulator should operate, the voltage regulator being adapted to receive an input voltage (V IN) and being adapted to provide an output voltage (V OUT), the peak-buck peak-boost control circuit comprising: a mode selection circuit adapted to generate control signals (ON_BST, PK_BUK, PK_BST, ON_BUK) representing (a) a first control state in which the input voltage is greater than the output voltage by at least a first predetermined value; (b) a second control state in which the input voltage is greater than the output voltage and less than or equal to the first predetermined value; (c) a third control state in which the output voltage is greater than the input voltage and less than or equal to a second predetermined value; (d) a fourth control state in which the output voltage is greater than the input voltage by at least the second predetermined value; and a switch control signal generation circuit for generating control signals (A, B, C, D) for operating switches (S A, S B, S C, S D) in the voltage regulator, wherein the voltage regulator is configured to be operated in (a) the peak-buck buck mode by the first control state, (b) the peak-buck buck-boost mode by the second control state, (c) the peak-boost buck-boost mode by the third control state and (d) the peak-boost boost mode by the fourth control state; characterised in that the peak-buck peak-boost control circuit is adapted to receive a first clock signal (CLK_A), a second clock signal (CLK_B) and a third clock signal (CLK_C), wherein the first clock signal marks the beginning of a switching period and the second and third clock signal mark respective predetermined switching period delays, and wherein the peak-buck peak-boost control circuit is adapted to implement a peak current-mode control scheme for generating the control signals (A, B, C, D) for operating the switches (S A, S B, S C, S D) based on a configuration to (i) detect a peak in a current (I L) of an inductor in the voltage regulator when a voltage difference, representing the current of the inductor, reaches a variable voltage threshold; and to (ii) apply the timing of the first, second and third clock signals. a mode selection circuit adapted to generate control signals (ON_BST, PK_BUK, PK_BST, ON_BUK) representing (a) a first control state in which the input voltage is greater than the output voltage by at least a first predetermined value; (b) a second control state in which the input voltage is greater than the output voltage and less than or equal to the first predetermined value; (c) a third control state in which the output voltage is greater than the input voltage and less than or equal to a second predetermined value; (d) a fourth control state in which the output voltage is greater than the input voltage by at least the second predetermined value; and a switch control signal generation circuit for generating control signals (A, B, C, D) for operating switches (S A, S B, S C, S D) in the voltage regulator, wherein the voltage regulator is configured to be operated in (a) the peak-buck buck mode by the first control state, (b) the peak-buck buck-boost mode by the second control state, (c) the peak-boost buck-boost mode by the third control state and (d) the peak-boost boost mode by the fourth control state; characterised in that the peak-buck peak-boost control circuit is adapted to receive a first clock signal (CLK_A), a second clock signal (CLK_B) and a third clock signal (CLK_C), wherein the first clock signal marks the beginning of a switching period and the second and third clock signal mark respective predetermined switching period delays, and wherein the peak-buck peak-boost control circuit is adapted to implement a peak current-mode control scheme for generating the control signals (A, B, C, D) for operating the switches (S A, S B, S C, S D) based on a configuration to (i) detect a peak in a current (I L) of an inductor in the voltage regulator when a voltage difference, representing the current of the inductor, reaches a variable voltage threshold; and to (ii) apply the timing of the first, second and third clock signals. (i) detect a peak in a current (I L) of an inductor in the voltage regulator when a voltage difference, representing the current of the inductor, reaches a variable voltage threshold; and to (ii) apply the timing of the first, second and third clock signals.