Apparatus for clock synchronisation comprising: a first phase locked loop configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency, the first phase locked loop comprising a frequency divider that is configured to control the multiple in response to a control signal; and a second phase locked loop configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop; wherein the second phase locked loop comprises a phase detector, a loop filter and a sigma-delta modulator, the phase detector configured to provide a phase error signal that indicates a phase difference between the input signal (Fantenna) and the output signal (Fout); the loop filter configured to receive the phase error signal, and to provide at an output an output value to an input of the sigma-delta modulator, wherein the loop filter is configured to receive a freeze signal to fix the output value at the output of the loop filter and wherein the sigma delta modulator is configured to provide the control signal, so as to provide the multiple that is fractional, wherein the second phase locked loop comprises phase adjustment means, operable to adjust a phase difference between the input signal (Fantenna) and output signal (Fout) by receiving a phase control signal (phase_control) to add an offset value to the input or the output of the sigma-delta modulator for a number of cycles of the output frequency, resulting in a phase change of the output signal (Fout), during which the freeze signal is applied to the loop filter. a first phase locked loop configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency, the first phase locked loop comprising a frequency divider that is configured to control the multiple in response to a control signal; and a second phase locked loop configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop; wherein the second phase locked loop comprises a phase detector, a loop filter and a sigma-delta modulator, the phase detector configured to provide a phase error signal that indicates a phase difference between the input signal (Fantenna) and the output signal (Fout); the loop filter configured to receive the phase error signal, and to provide at an output an output value to an input of the sigma-delta modulator, wherein the loop filter is configured to receive a freeze signal to fix the output value at the output of the loop filter and wherein the sigma delta modulator is configured to provide the control signal, so as to provide the multiple that is fractional, wherein the second phase locked loop comprises phase adjustment means, operable to adjust a phase difference between the input signal (Fantenna) and output signal (Fout) by receiving a phase control signal (phase_control) to add an offset value to the input or the output of the sigma-delta modulator for a number of cycles of the output frequency, resulting in a phase change of the output signal (Fout), during which the freeze signal is applied to the loop filter.