A data distribution method, comprising: receiving a first packet stream; dividing the first packet stream to obtain a first data block stream; sending the first data block stream to a first circuit; processing, by the first circuit, the first data block stream to obtain a first data stream; distributing, by the first circuit, the first data stream to N1 second circuits of M second circuits in a physical layer circuit, PHY, wherein the M is greater than the N1, the N1 is a positive integer, and the M is a positive integer; and processing, by the N1 second circuits, the received first data stream to obtain N1 first code streams, wherein the N1 second circuits are in a one-to-one correspondence with the N1 first code streams; wherein: the first circuit comprises a receiving circuit, the first data stream is the first data block stream, and each second circuit of the M second circuits comprises a physical layer encoding circuit, a scrambling circuit, and an alignment marker insertion circuit; or, the first circuit comprises a physical layer encoding circuit, the first data stream is a data stream that is obtained after physical layer encoding is performed on the first data block stream, each second circuit of the M second circuits comprises a scrambling circuit and an alignment marker insertion circuit, and the first circuit is a circuit in the PHY; or, the first circuit comprises a physical layer encoding circuit, a scrambling circuit, and an alignment marker insertion circuit, the first data stream is a data stream that is obtained after physical layer encoding, scrambling, and alignment marker insertion are performed on the first data block stream, each second circuit of the M second circuits comprises a receiving circuit, and the first circuit is a circuit in the PHY. receiving a first packet stream; dividing the first packet stream to obtain a first data block stream; sending the first data block stream to a first circuit; processing, by the first circuit, the first data block stream to obtain a first data stream; distributing, by the first circuit, the first data stream to N1 second circuits of M second circuits in a physical layer circuit, PHY, wherein the M is greater than the N1, the N1 is a positive integer, and the M is a positive integer; and processing, by the N1 second circuits, the received first data stream to obtain N1 first code streams, wherein the N1 second circuits are in a one-to-one correspondence with the N1 first code streams; wherein: the first circuit comprises a receiving circuit, the first data stream is the first data block stream, and each second circuit of the M second circuits comprises a physical layer encoding circuit, a scrambling circuit, and an alignment marker insertion circuit; or, the first circuit comprises a physical layer encoding circuit, the first data stream is a data stream that is obtained after physical layer encoding is performed on the first data block stream, each second circuit of the M second circuits comprises a scrambling circuit and an alignment marker insertion circuit, and the first circuit is a circuit in the PHY; or, the first circuit comprises a physical layer encoding circuit, a scrambling circuit, and an alignment marker insertion circuit, the first data stream is a data stream that is obtained after physical layer encoding, scrambling, and alignment marker insertion are performed on the first data block stream, each second circuit of the M second circuits comprises a receiving circuit, and the first circuit is a circuit in the PHY. the first circuit comprises a receiving circuit, the first data stream is the first data block stream, and each second circuit of the M second circuits comprises a physical layer encoding circuit, a scrambling circuit, and an alignment marker insertion circuit; or, the first circuit comprises a physical layer encoding circuit, the first data stream is a data stream that is obtained after physical layer encoding is performed on the first data block stream, each second circuit of the M second circuits comprises a scrambling circuit and an alignment marker insertion circuit, and the first circuit is a circuit in the PHY; or, the first circuit comprises a physical layer encoding circuit, a scrambling circuit, and an alignment marker insertion circuit, the first data stream is a data stream that is obtained after physical layer encoding, scrambling, and alignment marker insertion are performed on the first data block stream, each second circuit of the M second circuits comprises a receiving circuit, and the first circuit is a circuit in the PHY.