A circuit for parallel perforation in rate matching, the circuit comprising multiple selector arrays and corresponding multiple register groups; characterized in that: the multiple selector arrays comprise a first selector array (sx), a second selector array (sy) and a third selector array (sz); and the multiple register groups comprise a first register group (x), a second register group (y) and a third register group (z); wherein the input data are connected to a data input end of the first selector array (sx); the first selector array (sx) is configured to remove the null bits" in the input data and output of the first selector array (sx) is registered into the first register group (x); the first register group (x) is connected to both a data input end of the second selector array (sy) and a data input end of the third selector array (sz); the third selector array (sz) is configured to output remaining valid data in the first register group (x) to the third register group (y) if the valid data in the first register group (x) are not used while combining the valid data in the first register group (x) and the third register group (z) by the second selector array (sy) and output of the third selector array (sz) is registered into the third register group (z); the third register group (z) and the first register group (x), after combined with each other, serve as the data input end of the second selector array (sy); the second selector array (sy) is configured to combine valid data in the first register group (x) and valid data in the third register group (z) respectively and output of the second selector array (sy) is registered into the second register group (y); and the data in the second register group (y) serve as output data. the multiple selector arrays comprise a first selector array (sx), a second selector array (sy) and a third selector array (sz); and the multiple register groups comprise a first register group (x), a second register group (y) and a third register group (z); wherein the input data are connected to a data input end of the first selector array (sx); the first selector array (sx) is configured to remove the null bits" in the input data and output of the first selector array (sx) is registered into the first register group (x); the first register group (x) is connected to both a data input end of the second selector array (sy) and a data input end of the third selector array (sz); the third selector array (sz) is configured to output remaining valid data in the first register group (x) to the third register group (y) if the valid data in the first register group (x) are not used while combining the valid data in the first register group (x) and the third register group (z) by the second selector array (sy) and output of the third selector array (sz) is registered into the third register group (z); the third register group (z) and the first register group (x), after combined with each other, serve as the data input end of the second selector array (sy); the second selector array (sy) is configured to combine valid data in the first register group (x) and valid data in the third register group (z) respectively and output of the second selector array (sy) is registered into the second register group (y); and the data in the second register group (y) serve as output data.