A clock delay circuit configured to generate a delayed clock signal based on an input clock signal (CKIN), the delayed clock signal delayed by a delay time T DEL, the circuit comprising: an input module configured to receive the input clock signal (CKIN); a reference current source providing a reference current; a capacitor configured to charge or discharge based on the input clock signal (CKIN) and an output clock signal, the capacitor having a capacitance C and connected to a top node; a current mirror configured to generate one or more starved currents based on the reference current and having a current scaling factor and configured to provide a scaled version of the reference current at the top node, scaled by a current scaling factor N TOP; a switching module configured to provide current from the current source to charge the capacitor when the input clock signal (CKIN) is high and discharge the capacitor when the input clock signal (CKIN) is low; a Schmitt trigger configured to generate a Schmitt trigger output signal in response to the input clock signal (CKIN), wherein the Schmitt trigger output signal increases from a low signal to a high signal over a charging period of time T CHARGE correlated with T DEL, in response to a high signal input from the input clock signal (CKIN), via the switching module, the high signal based on an upper threshold voltage V ST, High of the Schmitt Trigger, wherein the Schmitt trigger output signal reverts to a low signal in response to a low signal from the input clock signal (CKIN), and wherein the Schmitt trigger is configured to be current starved by a first starved current of the one or more starved currents when the input clock signal (CKIN) is high and the Schmitt trigger is configured to be shorted to ground and the reference current when the input clock signal (CKIN) is low; a plurality of inverters configured to generate the delayed clock signal based on the Schmitt trigger output signal, wherein one or more of the plurality inverters are configured to be current starved by a second starved current of the one or more starved currents when the input clock signal (CKIN) is high and configured to be shorted to ground and the reference current when the input clock signal (CKIN) is low; and wherein T DEL is based on T CHARGE and T CHARGE is based on C, N TOP, V ST, High, and a supply voltage V SUPL. an input module configured to receive the input clock signal (CKIN); a reference current source providing a reference current; a capacitor configured to charge or discharge based on the input clock signal (CKIN) and an output clock signal, the capacitor having a capacitance C and connected to a top node; a current mirror configured to generate one or more starved currents based on the reference current and having a current scaling factor and configured to provide a scaled version of the reference current at the top node, scaled by a current scaling factor N TOP; a switching module configured to provide current from the current source to charge the capacitor when the input clock signal (CKIN) is high and discharge the capacitor when the input clock signal (CKIN) is low; a Schmitt trigger configured to generate a Schmitt trigger output signal in response to the input clock signal (CKIN), wherein the Schmitt trigger output signal increases from a low signal to a high signal over a charging period of time T CHARGE correlated with T DEL, in response to a high signal input from the input clock signal (CKIN), via the switching module, the high signal based on an upper threshold voltage V ST, High of the Schmitt Trigger, wherein the Schmitt trigger output signal reverts to a low signal in response to a low signal from the input clock signal (CKIN), and wherein the Schmitt trigger is configured to be current starved by a first starved current of the one or more starved currents when the input clock signal (CKIN) is high and the Schmitt trigger is configured to be shorted to ground and the reference current when the input clock signal (CKIN) is low; a plurality of inverters configured to generate the delayed clock signal based on the Schmitt trigger output signal, wherein one or more of the plurality inverters are configured to be current starved by a second starved current of the one or more starved currents when the input clock signal (CKIN) is high and configured to be shorted to ground and the reference current when the input clock signal (CKIN) is low; and wherein T DEL is based on T CHARGE and T CHARGE is based on C, N TOP, V ST, High, and a supply voltage V SUPL.