A gate driving circuit comprising N cascaded shift register circuits divided into groups, wherein continuous multiple stages of shift register circuits are included in each group and wherein each group of shift register circuits comprises K stages of shift register circuits, where K and N are positive integers, wherein each of the K shift register circuits comprises a reset circuit, wherein for the reset circuit of each of the K shift register circuits, a reset signal input terminal receives a reset signal from a K th stage of shift register circuit subsequent to the current shift register circuit; wherein the reset circuit comprises: a first adjustment control circuit having an input terminal, an output terminal and a control terminal, wherein the input terminal of the first adjustment control circuit is configured to receive a ground line signal via a ground input terminal, and the control terminal of the first adjustment control circuit is configured to receive a first control signal; a second adjustment control circuit having an input terminal, an output terminal and a control terminal, wherein the input terminal of the second adjustment control circuit is configured to receive an adjustment signal via an adjustment signal input terminal, the control terminal of the second adjustment control circuit is configured to receive a second control signal, and the output terminal of the second adjustment control circuit is coupled to the output terminal of the first adjustment control circuit; the preset signal input terminal (RESET input) for receiving the reset signal; and a storage circuit having a first terminal and a second terminal, wherein the first terminal of the storage circuit is coupled to the output terminal of the first adjustment control circuit and the output terminal of the second adjustment control circuit, and the second terminal of the storage circuit is coupled to the reset signal input terminal and a transistor of the shift register circuit for receiving a reset input signal for resetting the shift register circuit; wherein the first adjustment control circuit and the second adjustment control circuit each comprise thin film transistors and the storage circuit comprises a capacitor; wherein in the first adjustment control circuit, the input terminal comprises one of a source and a drain, the output terminal comprises the other of the source and the drain, and the control terminal comprises a gate; and in the second adjustment control circuit, the input terminal comprises one of a source and a drain, the output terminal comprises the other of the source and the drain, and the control terminal comprises a gate; and wherein the first control signal is in phase with a gate driving input signal of the shift register circuit, and the second control signal is in phase with the reset signal. a first adjustment control circuit having an input terminal, an output terminal and a control terminal, wherein the input terminal of the first adjustment control circuit is configured to receive a ground line signal via a ground input terminal, and the control terminal of the first adjustment control circuit is configured to receive a first control signal; a second adjustment control circuit having an input terminal, an output terminal and a control terminal, wherein the input terminal of the second adjustment control circuit is configured to receive an adjustment signal via an adjustment signal input terminal, the control terminal of the second adjustment control circuit is configured to receive a second control signal, and the output terminal of the second adjustment control circuit is coupled to the output terminal of the first adjustment control circuit; the preset signal input terminal (RESET input) for receiving the reset signal; and a storage circuit having a first terminal and a second terminal, wherein the first terminal of the storage circuit is coupled to the output terminal of the first adjustment control circuit and the output terminal of the second adjustment control circuit, and the second terminal of the storage circuit is coupled to the reset signal input terminal and a transistor of the shift register circuit for receiving a reset input signal for resetting the shift register circuit; wherein the first adjustment control circuit and the second adjustment control circuit each comprise thin film transistors and the storage circuit comprises a capacitor; wherein in the first adjustment control circuit, the input terminal comprises one of a source and a drain, the output terminal comprises the other of the source and the drain, and the control terminal comprises a gate; and in the second adjustment control circuit, the input terminal comprises one of a source and a drain, the output terminal comprises the other of the source and the drain, and the control terminal comprises a gate; and wherein the first control signal is in phase with a gate driving input signal of the shift register circuit, and the second control signal is in phase with the reset signal.