An apparatus comprising: a memory to store a plurality of data values corresponding to an SIMD (Single Instruction, Multiple Data) instruction; and a processor having a plurality of SIMD lanes, wherein each of the plurality of the SIMD lanes is to process one of the plurality of data stored in the memory in accordance with the SIMD instruction, characterized in that the processor is configured to invert a plurality of floating point values using at least one SIMD instruction by: receiving a plurality of data values x i, with 1≤i≤n, each representing a floating point value having a fraction portion f i and an exponent portion n i; scaling the plurality of fraction portions f i of the plurality of data values to generate a plurality of scaled arguments z i, such that z i ∈[1,2); multiplying the plurality of scaled arguments z i to generate a first value M; inverting the first value M to generate a second value R; calculating an inverted version of each scaled argument z i by multiplying the second value R with all scaled arguments z j, where 1≤j≤n and j≠i; negating for each x i to be inverted the exponent portion n i by changing a sign of the exponent portion n i of the respective argument x i to generate a negated exponent m i; and multiplying 2 m i with the inverted version of the scaled argument z i to generate an inverse version of x i. a memory to store a plurality of data values corresponding to an SIMD (Single Instruction, Multiple Data) instruction; and a processor having a plurality of SIMD lanes, wherein each of the plurality of the SIMD lanes is to process one of the plurality of data stored in the memory in accordance with the SIMD instruction, characterized in that the processor is configured to invert a plurality of floating point values using at least one SIMD instruction by: receiving a plurality of data values x i, with 1≤i≤n, each representing a floating point value having a fraction portion f i and an exponent portion n i; scaling the plurality of fraction portions f i of the plurality of data values to generate a plurality of scaled arguments z i, such that z i ∈[1,2); multiplying the plurality of scaled arguments z i to generate a first value M; inverting the first value M to generate a second value R; calculating an inverted version of each scaled argument z i by multiplying the second value R with all scaled arguments z j, where 1≤j≤n and j≠i; negating for each x i to be inverted the exponent portion n i by changing a sign of the exponent portion n i of the respective argument x i to generate a negated exponent m i; and multiplying 2 m i with the inverted version of the scaled argument z i to generate an inverse version of x i. receiving a plurality of data values x i, with 1≤i≤n, each representing a floating point value having a fraction portion f i and an exponent portion n i; scaling the plurality of fraction portions f i of the plurality of data values to generate a plurality of scaled arguments z i, such that z i ∈[1,2); multiplying the plurality of scaled arguments z i to generate a first value M; inverting the first value M to generate a second value R; calculating an inverted version of each scaled argument z i by multiplying the second value R with all scaled arguments z j, where 1≤j≤n and j≠i; negating for each x i to be inverted the exponent portion n i by changing a sign of the exponent portion n i of the respective argument x i to generate a negated exponent m i; and multiplying 2 m i with the inverted version of the scaled argument z i to generate an inverse version of x i.