A semiconductor storage device comprising: a ternary content addressable memory, TCAM, cell array comprising a plurality of TCAM cells, a first word line; a second word line; a first match line; a second match line; a pair of search lines (SLO, /SLO); a first TCAM cell (MC0#0) included in the plurality of TCAM cells and joined to the first word line, the second word line, and the first match line; and a second TCAM cell (MCO#1) included in the plurality of TCAM cells and joined to the first word line, the second word line, and the second match line, wherein the first TCAM cell (MC0#0) and the second TCAM cell (MCO#1) are arranged adjacent to each other in a first direction in a planar view, wherein the pair of search lines (SLO, /SLO) is shared by being joined to the first TCAM cell (MC0#0) and the second TCAM cell (MCO#1), wherein the pair of search lines (SLO, /SLO) is arranged between the first TCAM cell (MC0#0) and the second TCAM cell (MCO#1), wherein the first word line and the second word line are formed using wirings of a first wiring layer and extended in the first direction, wherein the first match line and the second match line are formed using wirings of a second wiring layer provided adjacent to and above the first wiring layer and extended in the first direction, wherein the first word line and the second word line are provided in parallel with each other and disposed between two first wirings to which a first reference potential is supplied, the two first wirings, the first word line, and the second word line extending parallel to each other in the first direction, the two first wirings, the first word line, the second word line having a same length in the first direction, wherein the first wirings are formed using wirings of the first wiring layer, wherein the first match line and the second match line are provided in parallel with each other and disposed between two second wirings to which the first reference potential is supplied, the two second wirings, the first match line, the second match line extending parallel to each other in the first direction, wherein the second wirings are formed using wirings of the second wiring layer, the second wirings are arranged above the first wirings, and wherein the first wirings and the second wirings are coupled to each other through a plurality of via electrodes formed between the first wiring layer and the second wiring layer. a ternary content addressable memory, TCAM, cell array comprising a plurality of TCAM cells, a first word line; a second word line; a first match line; a second match line; a pair of search lines (SLO, /SLO); a first TCAM cell (MC0#0) included in the plurality of TCAM cells and joined to the first word line, the second word line, and the first match line; and a second TCAM cell (MCO#1) included in the plurality of TCAM cells and joined to the first word line, the second word line, and the second match line, wherein the first TCAM cell (MC0#0) and the second TCAM cell (MCO#1) are arranged adjacent to each other in a first direction in a planar view, wherein the pair of search lines (SLO, /SLO) is shared by being joined to the first TCAM cell (MC0#0) and the second TCAM cell (MCO#1), wherein the pair of search lines (SLO, /SLO) is arranged between the first TCAM cell (MC0#0) and the second TCAM cell (MCO#1), wherein the first word line and the second word line are formed using wirings of a first wiring layer and extended in the first direction, wherein the first match line and the second match line are formed using wirings of a second wiring layer provided adjacent to and above the first wiring layer and extended in the first direction, wherein the first word line and the second word line are provided in parallel with each other and disposed between two first wirings to which a first reference potential is supplied, the two first wirings, the first word line, and the second word line extending parallel to each other in the first direction, the two first wirings, the first word line, the second word line having a same length in the first direction, wherein the first wirings are formed using wirings of the first wiring layer, wherein the first match line and the second match line are provided in parallel with each other and disposed between two second wirings to which the first reference potential is supplied, the two second wirings, the first match line, the second match line extending parallel to each other in the first direction, wherein the second wirings are formed using wirings of the second wiring layer, the second wirings are arranged above the first wirings, and wherein the first wirings and the second wirings are coupled to each other through a plurality of via electrodes formed between the first wiring layer and the second wiring layer.