A semiconductor device comprising: a bit line; a source line; a potential change circuit comprising a first multiplexer that is connected to the bit line, an input signal line (BL_OS), a write and read control signal line (WREN), and a read circuit input signal line, and a second multiplexer connected to the source line, the input signal line (BL_OS), the write and read control signal line (WREN), and a second source line; and a memory cell, the memory cell comprising: a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor material; a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor material, wherein the second semiconductor material is an oxide semiconductor; and a capacitor, wherein the first semiconductor material is different from the second semiconductor material, wherein the first gate electrode, the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other to form a node which holds charge, wherein the source line, one of terminals of the second multiplexer, and the first source electrode are electrically connected to each other, wherein the bit line, the second source electrode, and the first drain electrode are electrically connected to each other, wherein the potential change circuit is configured to selectively apply a first potential to the source line or a second potential to the source line, and wherein the first potential is equal to a potential of the bit line and the second potential is different from the potential of the bit line, wherein the potential change circuit is configured to apply the first potential to the source line, when a potential which turns the first transistor on is applied to the node. a bit line; a source line; a potential change circuit comprising a first multiplexer that is connected to the bit line, an input signal line (BL_OS), a write and read control signal line (WREN), and a read circuit input signal line, and a second multiplexer connected to the source line, the input signal line (BL_OS), the write and read control signal line (WREN), and a second source line; and a first multiplexer that is connected to the bit line, an input signal line (BL_OS), a write and read control signal line (WREN), and a read circuit input signal line, and a second multiplexer connected to the source line, the input signal line (BL_OS), the write and read control signal line (WREN), and a second source line; and a memory cell, the memory cell comprising: a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor material; a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor material, wherein the second semiconductor material is an oxide semiconductor; and a capacitor, a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor material; a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor material, wherein the second semiconductor material is an oxide semiconductor; and a capacitor, wherein the first semiconductor material is different from the second semiconductor material, wherein the first gate electrode, the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other to form a node which holds charge, wherein the source line, one of terminals of the second multiplexer, and the first source electrode are electrically connected to each other, wherein the bit line, the second source electrode, and the first drain electrode are electrically connected to each other, wherein the potential change circuit is configured to selectively apply a first potential to the source line or a second potential to the source line, and wherein the first potential is equal to a potential of the bit line and the second potential is different from the potential of the bit line, wherein the potential change circuit is configured to apply the first potential to the source line, when a potential which turns the first transistor on is applied to the node.