A processor comprising: a plurality of parallel execution lanes within a single instruction multiple data micro-architecture; a plurality of program counter registers (466a-466g), wherein each program counter register is configured to store a program counter of a next instruction of a dynamic variable length instruction word to fetch from memory and store, in an instruction cache as a dynamic variable length instruction word, said dynamic variable length instruction word including an instruction from each of one or more basic blocks to be simultaneously executed; a size register configured to store a number of instructions in a dynamic variable length instruction word; a vector register configured to store identifiers in particular fields, wherein each field is associated with a corresponding lane of the plurality of execution lanes, wherein a given identifier identifies a given one of the plurality of program counter registers; and control logic configured to: execute compiler generated program code to update the size register to indicate a number of instructions that are included in a next dynamic variable length instruction word to be fetched for simultaneous execution, said compiler being configured to identify divergence points and insert program code to support simultaneous execution of multiple paths; execute program code to update one or more of the program counter registers, each of the updated program counter registers identifying a different instruction of the next dynamic variable length instruction word; fetch a number of instructions indicated by the size register, wherein a separate program counter register of the plurality of program counter registers is used to identify which instructions are fetched; and wherein the plurality of execution lanes are configured to simultaneously execute the fetched instructions within said next dynamic variable length instruction word. a plurality of parallel execution lanes within a single instruction multiple data micro-architecture; a plurality of program counter registers (466a-466g), wherein each program counter register is configured to store a program counter of a next instruction of a dynamic variable length instruction word to fetch from memory and store, in an instruction cache as a dynamic variable length instruction word, said dynamic variable length instruction word including an instruction from each of one or more basic blocks to be simultaneously executed; a size register configured to store a number of instructions in a dynamic variable length instruction word; a vector register configured to store identifiers in particular fields, wherein each field is associated with a corresponding lane of the plurality of execution lanes, wherein a given identifier identifies a given one of the plurality of program counter registers; and control logic configured to: execute compiler generated program code to update the size register to indicate a number of instructions that are included in a next dynamic variable length instruction word to be fetched for simultaneous execution, said compiler being configured to identify divergence points and insert program code to support simultaneous execution of multiple paths; execute program code to update one or more of the program counter registers, each of the updated program counter registers identifying a different instruction of the next dynamic variable length instruction word; fetch a number of instructions indicated by the size register, wherein a separate program counter register of the plurality of program counter registers is used to identify which instructions are fetched; and wherein the plurality of execution lanes are configured to simultaneously execute the fetched instructions within said next dynamic variable length instruction word. execute compiler generated program code to update the size register to indicate a number of instructions that are included in a next dynamic variable length instruction word to be fetched for simultaneous execution, said compiler being configured to identify divergence points and insert program code to support simultaneous execution of multiple paths; execute program code to update one or more of the program counter registers, each of the updated program counter registers identifying a different instruction of the next dynamic variable length instruction word; fetch a number of instructions indicated by the size register, wherein a separate program counter register of the plurality of program counter registers is used to identify which instructions are fetched; and wherein the plurality of execution lanes are configured to simultaneously execute the fetched instructions within said next dynamic variable length instruction word.