A semiconductor device, comprising: two vertical arrangements (NMOS, PMOS) of pluralities of nanowires (604, 608, 606, 610) disposed above a substrate, each nanowire (604, 608, 606, 610) comprising a channel region and source and drain regions disposed on either side of the channel region, each plurality of nanowires in said two vertical arrangements comprising a gate stack (630, 632) disposed on and completely surrounding the channel region of each of the plurality of nanowires, a pair of contacts over the source and drain regions, and a pair of spacers on the plurality of nanowires between said pair of contacts and said gate stack (630, 632) wherein each channel region comprises an inner region (202, 204, 506A) having a first band gap and an outer cladding layer (205, 506B) surrounding the inner region (202, 204, 506A) the cladding layer having a second, lower band gap, the cladding layer not being present around the source and drain regions of the nanowires and under the spacers (516, 622) wherein the gate stack (630, 632) comprises a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer; wherein the plurality of nanowires (604, 608) in a first of said two vertical arrangements (NMOS) are of a group IlI-V material and have in the source and drain regions and under the spacers an intervening semiconductor material (606, 610) there between consisting of germanium, and the plurality of nanowires (606, 610) in the other of said two vertical arrangements (PMOS) are of germanium and have in the source and drain regions and under the spacerst an intervening semiconductor material (604, 608) there between consisting of a group IlI-V material. two vertical arrangements (NMOS, PMOS) of pluralities of nanowires (604, 608, 606, 610) disposed above a substrate, each nanowire (604, 608, 606, 610) comprising a channel region and source and drain regions disposed on either side of the channel region, each plurality of nanowires in said two vertical arrangements comprising a gate stack (630, 632) disposed on and completely surrounding the channel region of each of the plurality of nanowires, a pair of contacts over the source and drain regions, and a pair of spacers on the plurality of nanowires between said pair of contacts and said gate stack (630, 632) wherein each channel region comprises an inner region (202, 204, 506A) having a first band gap and an outer cladding layer (205, 506B) surrounding the inner region (202, 204, 506A) the cladding layer having a second, lower band gap, the cladding layer not being present around the source and drain regions of the nanowires and under the spacers (516, 622) wherein the gate stack (630, 632) comprises a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer; wherein the plurality of nanowires (604, 608) in a first of said two vertical arrangements (NMOS) are of a group IlI-V material and have in the source and drain regions and under the spacers an intervening semiconductor material (606, 610) there between consisting of germanium, and the plurality of nanowires (606, 610) in the other of said two vertical arrangements (PMOS) are of germanium and have in the source and drain regions and under the spacerst an intervening semiconductor material (604, 608) there between consisting of a group IlI-V material.