An apparatus comprising: an integrator circuit (202, 204) comprising two integrator inputs and two integrator outputs; a first switch circuit (206, 208, 210, 212) configured to selectively couple one of a first apparatus input signal (V INP) and a second apparatus input signal (V INM) with one of a first integrator input and a second integrator input, the first switch circuit comprising: a first switch configured to couple the first integrator input with the first apparatus input signal (V INP); a second switch configured to couple the second integrator input with the first apparatus input signal (V INP); a third switch configured to couple the first integrator input with the second apparatus input signal (V INM); and a fourth switch configured to couple the second integrator input with the second apparatus input signal (V INM); a first comparator configured to: receive a first output (V INP_COMP) of the integrator circuit (202, 204) and a first reference signal (V TH); and generate a first comparator output signal; and a second comparator configured to: receive a second output (V INM _ COMP) of the integrator circuit (202, 204) and the first reference signal (V TH); and generate a second comparator output signal, and a switch control generation circuit configured to receive the first and second comparator output signals (INC, DEC) and to generate control signals for the first switch circuit (206, 208, 210, 212). an integrator circuit (202, 204) comprising two integrator inputs and two integrator outputs; a first switch circuit (206, 208, 210, 212) configured to selectively couple one of a first apparatus input signal (V INP) and a second apparatus input signal (V INM) with one of a first integrator input and a second integrator input, the first switch circuit comprising: a first switch configured to couple the first integrator input with the first apparatus input signal (V INP); a second switch configured to couple the second integrator input with the first apparatus input signal (V INP); a third switch configured to couple the first integrator input with the second apparatus input signal (V INM); and a fourth switch configured to couple the second integrator input with the second apparatus input signal (V INM); a first switch configured to couple the first integrator input with the first apparatus input signal (V INP); a second switch configured to couple the second integrator input with the first apparatus input signal (V INP); a third switch configured to couple the first integrator input with the second apparatus input signal (V INM); and a fourth switch configured to couple the second integrator input with the second apparatus input signal (V INM); a first comparator configured to: receive a first output (V INP_COMP) of the integrator circuit (202, 204) and a first reference signal (V TH); and generate a first comparator output signal; and receive a first output (V INP_COMP) of the integrator circuit (202, 204) and a first reference signal (V TH); and generate a first comparator output signal; and a second comparator configured to: receive a second output (V INM _ COMP) of the integrator circuit (202, 204) and the first reference signal (V TH); and generate a second comparator output signal, and receive a second output (V INM _ COMP) of the integrator circuit (202, 204) and the first reference signal (V TH); and generate a second comparator output signal, and a switch control generation circuit configured to receive the first and second comparator output signals (INC, DEC) and to generate control signals for the first switch circuit (206, 208, 210, 212).