An interfacing device to a bidirectional bus line of the I2C type, the bus being adapted to take a first high logic level (V_Bus High) and a first low logic level (V_Bus Low), the device including: - a first input adapted to be operationally connected to a first reference potential, - a second input adapted to be operationally connected to a second supply potential, and - a third input adapted to be operationally connected to a third supply potential, the second and third supply potentials (V12, VCC) having a greater absolute value than said first reference potential, - a first pin (uP) adapted to be operationally connected to a port of a device adapted to communicate through said I2C bus, and normally kept at a second high logic level (V_uP High) defined by said third reference potential, - a second pin (Bus) adapted to be operationally connected to said I2C bus, and normally kept at said first high logic level (V_Bus High) defined by said second supply potential, characterised by - switching means comprising an output connection (Q30-OUT) to said second pin (Bus), a first control connection (Q30-R), and a reference connection (Q30-rif) to said first reference potential, and adapted to force the second pin (Bus) to said first reference potential when said first pin (uP) is forced to a low logic level, - a first diode having an anode connected to the first pin (uP) and a cathode connected to the second pin (Bus), and adapted to generate a low logic level in reception on the first pin (uP) in the presence of the low logic level on the bus, - drive means for driving said switching means, comprising an output connection (Q29-OUT) operationally connected to said third supply potential and to said control connection (Q30-R), a second control connection (Q29-R) operationally connected to said third supply potential and to said first pin (uP), and a reference connection (Q29-RIF) to said first reference potential, - said second control connection (Q29-R) of the drive means being operationally connected to said first pin (uP) through a second diode, the second diode having an anode connected to the second control connection (Q29-R) and a cathode connected to the first pin (uP). - a first input adapted to be operationally connected to a first reference potential, - a second input adapted to be operationally connected to a second supply potential, and - a third input adapted to be operationally connected to a third supply potential, the second and third supply potentials (V12, VCC) having a greater absolute value than said first reference potential, - a first pin (uP) adapted to be operationally connected to a port of a device adapted to communicate through said I2C bus, and normally kept at a second high logic level (V_uP High) defined by said third reference potential, - a second pin (Bus) adapted to be operationally connected to said I2C bus, and normally kept at said first high logic level (V_Bus High) defined by said second supply potential, - switching means comprising an output connection (Q30-OUT) to said second pin (Bus), a first control connection (Q30-R), and a reference connection (Q30-rif) to said first reference potential, and adapted to force the second pin (Bus) to said first reference potential when said first pin (uP) is forced to a low logic level, - a first diode having an anode connected to the first pin (uP) and a cathode connected to the second pin (Bus), and adapted to generate a low logic level in reception on the first pin (uP) in the presence of the low logic level on the bus, - drive means for driving said switching means, comprising an output connection (Q29-OUT) operationally connected to said third supply potential and to said control connection (Q30-R), a second control connection (Q29-R) operationally connected to said third supply potential and to said first pin (uP), and a reference connection (Q29-RIF) to said first reference potential, - said second control connection (Q29-R) of the drive means being operationally connected to said first pin (uP) through a second diode, the second diode having an anode connected to the second control connection (Q29-R) and a cathode connected to the first pin (uP).