A vertical memory device, comprising: gate electrodes (485, 700, 710, 720) on a substrate, the gate electrodes (485, 700, 710, 720) being stacked in a first direction substantially vertical to an upper surface of the substrate, the gate electrodes (485, 700, 710, 720) being stepped in a second direction with an extension length between adjacent ones of the gate electrodes (485, 700, 710, 720) gradually decreasing from a lowermost level toward an uppermost level, the second direction being substantially parallel to the upper surface of the substrate, the gate electrodes (485, 700, 710, 720) including a pad at an end portion thereof in the second direction; a channel extending through the gate electrodes (485, 700, 710, 720) in the first direction; and a conductive contact plug contacting the pad of a first and uppermost gate electrode among the gate electrodes (485, 700, 710, 720) such that the pad is electrically connected to said contact plug wherein the conductive contact plug extends through the gate electrodes (485, 700, 710, 720) in the first direction, and is electrically insulated from second gate electrodes among the gate electrodes (485, 700, 710, 720), the pad has a thickness greater than those of other portions of a respective one of the gate electrodes (485, 700, 710, 720), and the vertical memory device further comprises: a circuit pattern on the substrate; an insulating interlayer on the substrate, the insulating interlayer covering the circuit pattern, the conductive contact plug at least partially extending through the insulating interlayer to electrically connect to the circuit pattern; and a base pattern on the insulating interlayer, the base pattern having the gate electrodes (485, 700, 710, 720) and the channel formed thereon. gate electrodes (485, 700, 710, 720) on a substrate, the gate electrodes (485, 700, 710, 720) being stacked in a first direction substantially vertical to an upper surface of the substrate, the gate electrodes (485, 700, 710, 720) being stepped in a second direction with an extension length between adjacent ones of the gate electrodes (485, 700, 710, 720) gradually decreasing from a lowermost level toward an uppermost level, the second direction being substantially parallel to the upper surface of the substrate, the gate electrodes (485, 700, 710, 720) including a pad at an end portion thereof in the second direction; a channel extending through the gate electrodes (485, 700, 710, 720) in the first direction; and a conductive contact plug contacting the pad of a first and uppermost gate electrode among the gate electrodes (485, 700, 710, 720) such that the pad is electrically connected to said contact plug wherein the conductive contact plug extends through the gate electrodes (485, 700, 710, 720) in the first direction, and is electrically insulated from second gate electrodes among the gate electrodes (485, 700, 710, 720), the pad has a thickness greater than those of other portions of a respective one of the gate electrodes (485, 700, 710, 720), and the vertical memory device further comprises: a circuit pattern on the substrate; an insulating interlayer on the substrate, the insulating interlayer covering the circuit pattern, the conductive contact plug at least partially extending through the insulating interlayer to electrically connect to the circuit pattern; and a base pattern on the insulating interlayer, the base pattern having the gate electrodes (485, 700, 710, 720) and the channel formed thereon. a circuit pattern on the substrate; an insulating interlayer on the substrate, the insulating interlayer covering the circuit pattern, the conductive contact plug at least partially extending through the insulating interlayer to electrically connect to the circuit pattern; and a base pattern on the insulating interlayer, the base pattern having the gate electrodes (485, 700, 710, 720) and the channel formed thereon.