A power supply shut-off device comprising: a pair of field effect transistors (10A, 10B) that are connected to each other at source terminals thereof, and have a P-type channel polarity; an input terminal that is connected to a drain terminal of one of the pair of field effect transistors, and supplied with a power from a battery; an output terminal that is connected to a drain terminal of the other of the pair of field effect transistors, and supplies the power to a load, a pair of temperature detection elements that are installed adjacent to the drain terminals of the pair of field effect transistors, respectively, wherein the power supply shut-off device further comprises: a pair of parasitic diodes (11A, 11B) formed within the pair of field effect transistor and having anodes connected to the drain terminals of the pair of field effect transistors (10A, 10B), respectively, and cathodes connected to the source terminals of the pair of field effect transistors (10A, 10B), respectively, and a diagnosis unit that performs failure diagnosis of the pair of field effect transistors based on a detection result by the pair of temperature detection elements, the failure diagnosis being performed when the pair of field effect transistors become the ON state, and the pair of temperature detection elements being connected to the drain terminals of the pair of field effect transistors (10A, 10B), respectively. a pair of field effect transistors (10A, 10B) that are connected to each other at source terminals thereof, and have a P-type channel polarity; an input terminal that is connected to a drain terminal of one of the pair of field effect transistors, and supplied with a power from a battery; an output terminal that is connected to a drain terminal of the other of the pair of field effect transistors, and supplies the power to a load, a pair of temperature detection elements that are installed adjacent to the drain terminals of the pair of field effect transistors, respectively, wherein the power supply shut-off device further comprises: a pair of parasitic diodes (11A, 11B) formed within the pair of field effect transistor and having anodes connected to the drain terminals of the pair of field effect transistors (10A, 10B), respectively, and cathodes connected to the source terminals of the pair of field effect transistors (10A, 10B), respectively, and a diagnosis unit that performs failure diagnosis of the pair of field effect transistors based on a detection result by the pair of temperature detection elements, the failure diagnosis being performed when the pair of field effect transistors become the ON state, and the pair of temperature detection elements being connected to the drain terminals of the pair of field effect transistors (10A, 10B), respectively. a pair of parasitic diodes (11A, 11B) formed within the pair of field effect transistor and having anodes connected to the drain terminals of the pair of field effect transistors (10A, 10B), respectively, and cathodes connected to the source terminals of the pair of field effect transistors (10A, 10B), respectively, and a diagnosis unit that performs failure diagnosis of the pair of field effect transistors based on a detection result by the pair of temperature detection elements, the failure diagnosis being performed when the pair of field effect transistors become the ON state, and the pair of temperature detection elements being connected to the drain terminals of the pair of field effect transistors (10A, 10B), respectively.