A phase-locked loop, PLL comprising: a phase comparison module; a loop filter; a voltage controller oscillator, VCO; a feedback divider; and a jitter evaluation module, wherein the phase comparison module is configured to receive an application clock signal and a feedback clock signal, the loop filter is configured to receive an output signal from the phase comparison module, the VCO is configured to receive an output signal from the loop filter and provide the output clock signal, and the feedback divider is configured to receive the output clock signal and provide the feedback clock signal to the phase comparison module, wherein the phase comparison module comprises a phase comparator and a measurement module, wherein the phase comparator is a flip-flop configured to receive the application and feedback clock signals (105, 106), the phase comparison module comprising a synchronizer configured to receive an output signal from the flip-flop and provide the output signal from the phase comparison module to the loop filter, the measurement module being configured to: detect a metastable output in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106) by detecting oscillations in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106) and counting a number of oscillations in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106); and provide an output signal to the jitter evaluation module indicating a metastability resolution time for the phase comparator, the jitter evaluation module being configured to provide an output indicative of jitter based on the metastability resolution time, the metastability resolution time being defined as a time taken for the output of the phase comparator to settle on a definite value after a change in the application clock signal and feedback clock signal. a phase comparison module; a loop filter; a voltage controller oscillator, VCO; a feedback divider; and a jitter evaluation module, wherein the phase comparison module is configured to receive an application clock signal and a feedback clock signal, the loop filter is configured to receive an output signal from the phase comparison module, the VCO is configured to receive an output signal from the loop filter and provide the output clock signal, and the feedback divider is configured to receive the output clock signal and provide the feedback clock signal to the phase comparison module, wherein the phase comparison module comprises a phase comparator and a measurement module, wherein the phase comparator is a flip-flop configured to receive the application and feedback clock signals (105, 106), the phase comparison module comprising a synchronizer configured to receive an output signal from the flip-flop and provide the output signal from the phase comparison module to the loop filter, the measurement module being configured to: detect a metastable output in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106) by detecting oscillations in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106) and counting a number of oscillations in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106); and provide an output signal to the jitter evaluation module indicating a metastability resolution time for the phase comparator, the jitter evaluation module being configured to provide an output indicative of jitter based on the metastability resolution time, the metastability resolution time being defined as a time taken for the output of the phase comparator to settle on a definite value after a change in the application clock signal and feedback clock signal. detect a metastable output in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106) by detecting oscillations in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106) and counting a number of oscillations in the output signal from the phase comparator over active clock cycles of the application and feedback clock signals (105, 106); and provide an output signal to the jitter evaluation module indicating a metastability resolution time for the phase comparator, the jitter evaluation module being configured to provide an output indicative of jitter based on the metastability resolution time, the metastability resolution time being defined as a time taken for the output of the phase comparator to settle on a definite value after a change in the application clock signal and feedback clock signal.