A multi-processor two-level memory, 2LM, system for hybrid directory and snoopy-based coherency, comprising: system memory comprising near memory and far memory, and a processor (110A, 110B, 110C,..., 110N) coupled to the system memory, the processor (110A, 110B, 110C,..., 110N) comprising: one or more cores, each comprising a cache; a cache home agent, CHA, coupled to the cache comprised in the one or more cores; a far memory controller coupled to the far memory; and a near memory controller coupled to the CHA, to the near memory, and to the far memory controller, wherein the near memory controller is to: receive a first memory read operation from the CHA directed at a first memory address; detect a miss for the first memory address at the near memory; issue, in response to detection of the miss, a second memory read operation to the far memory controller to retrieve a cache line, comprising first data, from the first memory address of far memory; receive the cache line from the far memory controller in response to completion of the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote processors (110A, 110B, 110C,..., 110N) to maintain data coherence for the cache line in an absence of directory state in the far memory; wherein the near memory controller is to: write the cache line to the near memory; and update directory bits in the cache line to a directory state consistent with a read opcode of the first memory read operation. system memory comprising near memory and far memory, and a processor (110A, 110B, 110C,..., 110N) coupled to the system memory, the processor (110A, 110B, 110C,..., 110N) comprising: one or more cores, each comprising a cache; a cache home agent, CHA, coupled to the cache comprised in the one or more cores; a far memory controller coupled to the far memory; and a near memory controller coupled to the CHA, to the near memory, and to the far memory controller, wherein the near memory controller is to: receive a first memory read operation from the CHA directed at a first memory address; detect a miss for the first memory address at the near memory; issue, in response to detection of the miss, a second memory read operation to the far memory controller to retrieve a cache line, comprising first data, from the first memory address of far memory; receive the cache line from the far memory controller in response to completion of the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote processors (110A, 110B, 110C,..., 110N) to maintain data coherence for the cache line in an absence of directory state in the far memory; wherein the near memory controller is to: write the cache line to the near memory; and update directory bits in the cache line to a directory state consistent with a read opcode of the first memory read operation. one or more cores, each comprising a cache; a cache home agent, CHA, coupled to the cache comprised in the one or more cores; a far memory controller coupled to the far memory; and a near memory controller coupled to the CHA, to the near memory, and to the far memory controller, wherein the near memory controller is to: receive a first memory read operation from the CHA directed at a first memory address; detect a miss for the first memory address at the near memory; issue, in response to detection of the miss, a second memory read operation to the far memory controller to retrieve a cache line, comprising first data, from the first memory address of far memory; receive the cache line from the far memory controller in response to completion of the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote processors (110A, 110B, 110C,..., 110N) to maintain data coherence for the cache line in an absence of directory state in the far memory; wherein the near memory controller is to: write the cache line to the near memory; and update directory bits in the cache line to a directory state consistent with a read opcode of the first memory read operation. receive a first memory read operation from the CHA directed at a first memory address; detect a miss for the first memory address at the near memory; issue, in response to detection of the miss, a second memory read operation to the far memory controller to retrieve a cache line, comprising first data, from the first memory address of far memory; receive the cache line from the far memory controller in response to completion of the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote processors (110A, 110B, 110C,..., 110N) to maintain data coherence for the cache line in an absence of directory state in the far memory; wherein the near memory controller is to: write the cache line to the near memory; and update directory bits in the cache line to a directory state consistent with a read opcode of the first memory read operation. write the cache line to the near memory; and update directory bits in the cache line to a directory state consistent with a read opcode of the first memory read operation.