A vertical topology light emitting diode, comprising: a conductive substrate comprising metal or metal containing material; a p-type electrode on the conductive substrate; a semiconductor structure on the p-type electrode, wherein the p-type electrode is arranged between the conductive substrate and the semiconductor structure, wherein the semiconductor structure comprises a p-type GaN-based semiconductor layer, an active layer on the p-type GaN-based semiconductor layer, and an n-type GaN-based semiconductor layer on the active layer; an n-type electrode on a main light emitting surface of the semiconductor structure; a passivation layer on a side surface of the semiconductor structure, wherein the passivation layer covers side portions of the p-type GaN-based semiconductor layer, the active layer, and the n-type GaN-based semiconductor layer, wherein the passivation layer is partially arranged between the semiconductor structure and the conductive substrate, wherein said conductive substrate is electrically and thermally conductive, wherein the portion of the passivation layer on the side surface of the semiconductor structure is further arranged on the main light emitting surface of the semiconductor structure where it is patterned to form an open space to expose a top surface portion of the n-type electrode, wherein the passivation layer arranged partially between the conductive substrate and the semiconductor structure extends to the portion of the passivation layer arranged on the main light emitting surface of the semiconductor structure, and wherein a metal pad is arranged on the n-type electrode, wherein the metal pad comprises at least one of Cr and Au, wherein the metal pad extends over a portion of the passivation layer, wherein the metal pad is in contact with the patterned portion of the passivation layer, wherein the patterned portion comprises the open space. a conductive substrate comprising metal or metal containing material; a p-type electrode on the conductive substrate; a semiconductor structure on the p-type electrode, wherein the p-type electrode is arranged between the conductive substrate and the semiconductor structure, wherein the semiconductor structure comprises a p-type GaN-based semiconductor layer, an active layer on the p-type GaN-based semiconductor layer, and an n-type GaN-based semiconductor layer on the active layer; an n-type electrode on a main light emitting surface of the semiconductor structure; a passivation layer on a side surface of the semiconductor structure, wherein the passivation layer covers side portions of the p-type GaN-based semiconductor layer, the active layer, and the n-type GaN-based semiconductor layer, wherein the passivation layer is partially arranged between the semiconductor structure and the conductive substrate, wherein said conductive substrate is electrically and thermally conductive, wherein the portion of the passivation layer on the side surface of the semiconductor structure is further arranged on the main light emitting surface of the semiconductor structure where it is patterned to form an open space to expose a top surface portion of the n-type electrode, wherein the passivation layer arranged partially between the conductive substrate and the semiconductor structure extends to the portion of the passivation layer arranged on the main light emitting surface of the semiconductor structure, and wherein a metal pad is arranged on the n-type electrode, wherein the metal pad comprises at least one of Cr and Au, wherein the metal pad extends over a portion of the passivation layer, wherein the metal pad is in contact with the patterned portion of the passivation layer, wherein the patterned portion comprises the open space.