A three-dimensional memory device, comprising: a substrate; insulation layers disposed on the substrate; gate material layers disposed on the substrate, wherein the insulation layers and the gate material layers are alternately stacked in a vertical direction; a vertical structure penetrating the gate material layers in the vertical direction, wherein the vertical structure comprises: a semiconductor layer elongated in the vertical direction; and a trapping layer surrounding the semiconductor layer in a horizontal direction, wherein the trapping layer comprises trapping sections (24A, 24B) aligned in the vertical direction and separated from one another, wherein a length of each of the trapping sections (24A, 24B) in the vertical direction is less than a length of each of the gate material layers in the vertical direction; and a tunneling layer disposed between the semiconductor layer and the trapping layer, and a filling layer surrounded by the semiconductor layer, the tunneling layer, the trapping layer, and a blocking layer in the horizontal direction; characterized in that the trapping sections (24A, 24B) comprises first trapping sections and a second trapping section, the first trapping sections are disposed above the second trapping section in the vertical direction, and the semiconductor layer penetrates through the second trapping section in the vertical direction, wherein the second trapping section is disposed under the tunneling layer in the vertical direction, and the second trapping section is separated from each of the first trapping sections, wherein one of the insulation layers is directly connected with the second trapping section and one of the first trapping sections. a substrate; insulation layers disposed on the substrate; gate material layers disposed on the substrate, wherein the insulation layers and the gate material layers are alternately stacked in a vertical direction; a vertical structure penetrating the gate material layers in the vertical direction, wherein the vertical structure comprises: a semiconductor layer elongated in the vertical direction; and a trapping layer surrounding the semiconductor layer in a horizontal direction, wherein the trapping layer comprises trapping sections (24A, 24B) aligned in the vertical direction and separated from one another, wherein a length of each of the trapping sections (24A, 24B) in the vertical direction is less than a length of each of the gate material layers in the vertical direction; and a tunneling layer disposed between the semiconductor layer and the trapping layer, and a filling layer surrounded by the semiconductor layer, the tunneling layer, the trapping layer, and a blocking layer in the horizontal direction; characterized in that the trapping sections (24A, 24B) comprises first trapping sections and a second trapping section, the first trapping sections are disposed above the second trapping section in the vertical direction, and the semiconductor layer penetrates through the second trapping section in the vertical direction, a semiconductor layer elongated in the vertical direction; and a trapping layer surrounding the semiconductor layer in a horizontal direction, wherein the trapping layer comprises trapping sections (24A, 24B) aligned in the vertical direction and separated from one another, wherein a length of each of the trapping sections (24A, 24B) in the vertical direction is less than a length of each of the gate material layers in the vertical direction; and a tunneling layer disposed between the semiconductor layer and the trapping layer, and a filling layer surrounded by the semiconductor layer, the tunneling layer, the trapping layer, and a blocking layer in the horizontal direction; characterized in that the trapping sections (24A, 24B) comprises first trapping sections and a second trapping section, the first trapping sections are disposed above the second trapping section in the vertical direction, and the semiconductor layer penetrates through the second trapping section in the vertical direction, wherein the second trapping section is disposed under the tunneling layer in the vertical direction, and the second trapping section is separated from each of the first trapping sections, wherein one of the insulation layers is directly connected with the second trapping section and one of the first trapping sections.