A DC-DC buck converter comprising: a high-side power FET having a current path coupled in series between an input terminal (Vin) and an inductor, the inductor being connected to an output terminal (Vout) for supplying an output current to a load; a low-side power FET having a current path coupled between a reference voltage terminal and an interconnection node of the high-side power FET with the inductor; a pulse width modulation controller (PWM Controller) arranged to receive a feedback signal from the output terminal (Vout), and to provide pulse width modulated signals; a gate driver circuit (DRIVER) arranged to receive the pulse width modulated signals from the pulse width modulation controller (PWM Controller) and, responsive thereto, to apply pulse width modulated drive signals to the gates of the high-side and low-side power FETs; characterised in that it comprises a gate drive voltage controller (GATE DRIVE VOLTAGE CONTROLLER) that is coupled to receive signals that are representative of an input voltage (Vin) at the input terminal, an output voltage (Vout) at the output terminal, an input current (Iin) at the input terminal, and the output current (lout), wherein the gate drive voltage controller (GATE DRIVE VOLTAGE CONTROLLER) is arranged to generate an adjustment signal (Adjust) in response to at least some of the signals that are representative of the input voltage, the output voltage, the input current, and the output current; and a voltage regulator (REGULATOR) coupled to the gate drive voltage controller and to the gate driver circuit (DRIVER), the voltage regulator being arranged to receive the adjustment signal and to provide an adjusted gate drive voltage to the gate driver circuit (DRIVER) based on the adjustment signal. a high-side power FET having a current path coupled in series between an input terminal (Vin) and an inductor, the inductor being connected to an output terminal (Vout) for supplying an output current to a load; a low-side power FET having a current path coupled between a reference voltage terminal and an interconnection node of the high-side power FET with the inductor; a pulse width modulation controller (PWM Controller) arranged to receive a feedback signal from the output terminal (Vout), and to provide pulse width modulated signals; a gate driver circuit (DRIVER) arranged to receive the pulse width modulated signals from the pulse width modulation controller (PWM Controller) and, responsive thereto, to apply pulse width modulated drive signals to the gates of the high-side and low-side power FETs; characterised in that it comprises a gate drive voltage controller (GATE DRIVE VOLTAGE CONTROLLER) that is coupled to receive signals that are representative of an input voltage (Vin) at the input terminal, an output voltage (Vout) at the output terminal, an input current (Iin) at the input terminal, and the output current (lout), wherein the gate drive voltage controller (GATE DRIVE VOLTAGE CONTROLLER) is arranged to generate an adjustment signal (Adjust) in response to at least some of the signals that are representative of the input voltage, the output voltage, the input current, and the output current; and a voltage regulator (REGULATOR) coupled to the gate drive voltage controller and to the gate driver circuit (DRIVER), the voltage regulator being arranged to receive the adjustment signal and to provide an adjusted gate drive voltage to the gate driver circuit (DRIVER) based on the adjustment signal.