A processor-based device comprising a plurality of processing elements, PEs, (102 -102) communicatively coupled to each other via an interconnect bus, each PE comprising a hardware table walker, HTW, and: an execution pipeline (120 -120) comprising a decode stage (124 -124) and an execute stage (126 -126); a system memory comprising a page table; and a local cache (128 -128); a first PE (102) of the plurality of PEs configured to: decode, using the decode stage of the execution pipeline, a special page table entry, SP-PTE, field store instruction; and execute, using the execute stage of the execution pipeline, the SP-PTE field store instruction to modify SP-PTE fields (114 -114) of a PTE (112 -112) cached in a cache line (130) corresponding to the PTE in the local cache (128) of the first PE; and a second PE (102) of the plurality of PEs configured to: receive, via the interconnect bus, a bus request (138, 142) from the first PE for the cache line; and update a coherence state of a copy (130') of the cache line in the local cache of the second PE to a coherence state of walker-readable, W, to indicate that the copy of the cache line can only be read by a hardware table walker, HTW, (116) of the second PE to perform virtual to physical address translation, and wherein the modification of the SP-PTE fields is not visible to hardware table walkers. an execution pipeline (120 -120) comprising a decode stage (124 -124) and an execute stage (126 -126); a system memory comprising a page table; and a local cache (128 -128); a first PE (102) of the plurality of PEs configured to: decode, using the decode stage of the execution pipeline, a special page table entry, SP-PTE, field store instruction; and execute, using the execute stage of the execution pipeline, the SP-PTE field store instruction to modify SP-PTE fields (114 -114) of a PTE (112 -112) cached in a cache line (130) corresponding to the PTE in the local cache (128) of the first PE; and decode, using the decode stage of the execution pipeline, a special page table entry, SP-PTE, field store instruction; and execute, using the execute stage of the execution pipeline, the SP-PTE field store instruction to modify SP-PTE fields (114 -114) of a PTE (112 -112) cached in a cache line (130) corresponding to the PTE in the local cache (128) of the first PE; and a second PE (102) of the plurality of PEs configured to: receive, via the interconnect bus, a bus request (138, 142) from the first PE for the cache line; and update a coherence state of a copy (130') of the cache line in the local cache of the second PE to a coherence state of walker-readable, W, to indicate that the copy of the cache line can only be read by a hardware table walker, HTW, (116) of the second PE to perform virtual to physical address translation, and wherein the modification of the SP-PTE fields is not visible to hardware table walkers. receive, via the interconnect bus, a bus request (138, 142) from the first PE for the cache line; and update a coherence state of a copy (130') of the cache line in the local cache of the second PE to a coherence state of walker-readable, W, to indicate that the copy of the cache line can only be read by a hardware table walker, HTW, (116) of the second PE to perform virtual to physical address translation, and wherein the modification of the SP-PTE fields is not visible to hardware table walkers.