A field effect transistor comprising: a first piezoelectric layer supporting a channel; a second piezoelectric layer over the first piezoelectric layer; a dielectric layer (116, 116a) having a plurality of dielectric segments (116, 116a) separated by a plurality of gaps, the dielectric layer (116, 116a) over the second piezoelectric layer; a gate having a main body and a plurality of tines, the main body of the gate covering at least one dielectric segment of the plurality of dielectric segments (116, 116a) and covering at least two gaps of the plurality of gaps, the plurality of tines having proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer; a source electrically coupled to the second piezoelectric layer; and a drain electrically coupled to the second piezoelectric layer, characterized in that each tine has a width, measured parallel to a direction of current flow in the channel, of less than 200 nm, the dielectric layer (116, 116a) exerts compressive stress onto the first and second piezoelectric layers, the exerted compressive stress having an absolute value greater than 100 megapascals, and in the first piezoelectric layer adjacent to the second piezoelectric layer, stress exerted by the dielectric layer (116, 116a) creates a piezoelectric charge of at least 1×10 11 per cm 2 of electronic charge beneath the tines, so that the channel is non-conducting when there is a voltage difference between the source and the drain and there is no voltage applied between the gate and the source or the gate and the drain. a first piezoelectric layer supporting a channel; a second piezoelectric layer over the first piezoelectric layer; a dielectric layer (116, 116a) having a plurality of dielectric segments (116, 116a) separated by a plurality of gaps, the dielectric layer (116, 116a) over the second piezoelectric layer; a gate having a main body and a plurality of tines, the main body of the gate covering at least one dielectric segment of the plurality of dielectric segments (116, 116a) and covering at least two gaps of the plurality of gaps, the plurality of tines having proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer; a source electrically coupled to the second piezoelectric layer; and a drain electrically coupled to the second piezoelectric layer, characterized in that each tine has a width, measured parallel to a direction of current flow in the channel, of less than 200 nm, the dielectric layer (116, 116a) exerts compressive stress onto the first and second piezoelectric layers, the exerted compressive stress having an absolute value greater than 100 megapascals, and in the first piezoelectric layer adjacent to the second piezoelectric layer, stress exerted by the dielectric layer (116, 116a) creates a piezoelectric charge of at least 1×10 11 per cm 2 of electronic charge beneath the tines, so that the channel is non-conducting when there is a voltage difference between the source and the drain and there is no voltage applied between the gate and the source or the gate and the drain.