A time-to-digital converter comprising: - an edge detector responsive to first and second signals (12, 10), said second signal comprising a plurality of edges during each period of the first signal, said edge detector being adapted to detect, during each period of the first signal, an edge of the second signal that is closest to an edge of the first signal; - a time-to-voltage converter (200; 225) adapted to generate a voltage proportional to a difference in time between the detected edge of the second signal and the edge of the first signal, wherein the time-to-voltage converter (200; 225) has first and second differential outputs adapted to be charged to a predefined voltage level (VDD; Vref) in response to a reset signal, wherein a first conductive path is formed between the first differential output and a first supply voltage (GND; Vchg) in response to the edge of the first signal during a first time period, and wherein a second conductive path is formed between the second differential output and the first supply voltage (GND; Vchg) in response to the detected edge of the second signal during a second time period, wherein said first and second time periods do not overlap; and - an analog-to-digital converter adapted to digitize a difference in voltages (V1, V2) of the first and second differential outputs; and wherein said time-to-voltage converter (200; 225) further comprises: - first (206; 260) and second (214; 238) transistors adapted to provide the first conductive path between the first differential output and the first supply voltage (GND; Vchg); - third (204; 240) and fourth (216; 258) transistors adapted to provide the second conductive path between the second differential output and the first supply voltage (GND; Vchg); - a fifth (212; 242) transistor adapted to charge the first differential output to the predefined voltage level (VDD; Vref); and - a sixth (202; 262) transistor adapted to charge the second differential output to the predefined voltage level (VDD; Vref), wherein the predefined voltage level (VDD; Vref) is a second supply voltage different from the first supply voltage (GND; Vchg). - an edge detector responsive to first and second signals (12, 10), said second signal comprising a plurality of edges during each period of the first signal, said edge detector being adapted to detect, during each period of the first signal, an edge of the second signal that is closest to an edge of the first signal; - a time-to-voltage converter (200; 225) adapted to generate a voltage proportional to a difference in time between the detected edge of the second signal and the edge of the first signal, wherein the time-to-voltage converter (200; 225) has first and second differential outputs adapted to be charged to a predefined voltage level (VDD; Vref) in response to a reset signal, wherein a first conductive path is formed between the first differential output and a first supply voltage (GND; Vchg) in response to the edge of the first signal during a first time period, and wherein a second conductive path is formed between the second differential output and the first supply voltage (GND; Vchg) in response to the detected edge of the second signal during a second time period, wherein said first and second time periods do not overlap; and - an analog-to-digital converter adapted to digitize a difference in voltages (V1, V2) of the first and second differential outputs; and - first (206; 260) and second (214; 238) transistors adapted to provide the first conductive path between the first differential output and the first supply voltage (GND; Vchg); - third (204; 240) and fourth (216; 258) transistors adapted to provide the second conductive path between the second differential output and the first supply voltage (GND; Vchg); - a fifth (212; 242) transistor adapted to charge the first differential output to the predefined voltage level (VDD; Vref); and - a sixth (202; 262) transistor adapted to charge the second differential output to the predefined voltage level (VDD; Vref),