A structure, comprising: a SiGe virtual substrate with a relaxed graded SiGe buffer layer, a relaxed SiGe layer located on the relaxed graded SiGe buffer layer and a strained SiGe layer located on the relaxed SiGe layer; a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and a first trench (55a, 55b) defined in the relaxed SiGe layer and the strained SiGe layer, wherein a bottom portion of the first trench is located in the relaxed SiGe layer, the first trench having a liner oxide formed by a first dielectric layer, and a secondary protective liner comprising a dielectric material located conformally over the liner oxide and a fill material, wherein the liner oxide includes Ge and is an oxide in the form of Si 1-x Ge x O 2, wherein the Ge in the liner oxide comprises Ge incorporated into the liner oxide from the SiGe virtual substrate during a thermal oxidation step in which the liner oxide is formed, wherein the secondary protective liner does not include Ge, and wherein the trench is proximate at least one side of one of the first source region and the first drain region for inducing a portion of the first type of strain in the first channel region by expansion or contraction of the fill material. a SiGe virtual substrate with a relaxed graded SiGe buffer layer, a relaxed SiGe layer located on the relaxed graded SiGe buffer layer and a strained SiGe layer located on the relaxed SiGe layer; a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and a first trench (55a, 55b) defined in the relaxed SiGe layer and the strained SiGe layer, wherein a bottom portion of the first trench is located in the relaxed SiGe layer, the first trench having a liner oxide formed by a first dielectric layer, and a secondary protective liner comprising a dielectric material located conformally over the liner oxide and a fill material, wherein the liner oxide includes Ge and is an oxide in the form of Si 1-x Ge x O 2, wherein the Ge in the liner oxide comprises Ge incorporated into the liner oxide from the SiGe virtual substrate during a thermal oxidation step in which the liner oxide is formed, wherein the secondary protective liner does not include Ge, and wherein the trench is proximate at least one side of one of the first source region and the first drain region for inducing a portion of the first type of strain in the first channel region by expansion or contraction of the fill material. a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and a first trench (55a, 55b) defined in the relaxed SiGe layer and the strained SiGe layer, wherein a bottom portion of the first trench is located in the relaxed SiGe layer, the first trench having a liner oxide formed by a first dielectric layer, and a secondary protective liner comprising a dielectric material located conformally over the liner oxide and a fill material, wherein the liner oxide includes Ge and is an oxide in the form of Si 1-x Ge x O 2, wherein the Ge in the liner oxide comprises Ge incorporated into the liner oxide from the SiGe virtual substrate during a thermal oxidation step in which the liner oxide is formed, wherein the secondary protective liner does not include Ge, and wherein the trench is proximate at least one side of one of the first source region and the first drain region for inducing a portion of the first type of strain in the first channel region by expansion or contraction of the fill material.