A differential folded-cascode amplifier for amplifying a differential input signal comprising a first input signal (vin) and a second input signal (vip) and for outputting a differential output signal comprising a first output signal (voutp) and a second output signal (voutn), the amplifier comprising: a first input transistor connected to a first input (105; 205) and a second input transistor connected to a second input (110; 210), said first and second input forming a differential input pair, a current-bias transistor configured to provide a bias current to the first and second input transistors (M3 and M8); a first gain stage (115; 215) coupled to the first input transistor, wherein the first gain stage is coupled between two power supply buses (Vdd and Vss), said first gain stage comprising: a p-channel cascode transistor and an n-channel cascode.transistor connected to each other in cascode configuration, an n-channel current-gain transistor and a p-channel current-gain transistor, wherein the gates of said p-channel and n-channel cascode and current-gain transistors (M11, M15, M16 and M17) are biased by DC voltages; wherein the n-channel current-gain transistor is biased by a first DC bias voltage (vbiasn1) and the p-channel current-gain transistor is biased by a second DC bias voltage (vbiasp1); characterized by first and second gain boosting capacitors (C2 and C4), wherein the first and second capacitors (C2 and C4) pass the first input signal (vin) to the gates of the n-channel current-gain transistor and the p-channel current-gain transistor, respectively, while blocking said DC bias voltages (vbiasn1 and vbiasp1), respectively, from the first input (105, 205), first and second gain boosting resistors (R1 and R3), wherein the first gain boosting resistor and the second gain boosting resistor pass said first and second DC bias voltages (vbiasp1 and vbiasn1) to the gates of the n-channel and p-channel current-gain transistors (M16 and M11), respectively. a first input transistor connected to a first input (105; 205) and a second input transistor connected to a second input (110; 210), said first and second input forming a differential input pair, a current-bias transistor configured to provide a bias current to the first and second input transistors (M3 and M8); a first gain stage (115; 215) coupled to the first input transistor, wherein the first gain stage is coupled between two power supply buses (Vdd and Vss), said first gain stage comprising: a p-channel cascode transistor and an n-channel cascode.transistor connected to each other in cascode configuration, an n-channel current-gain transistor and a p-channel current-gain transistor, wherein the gates of said p-channel and n-channel cascode and current-gain transistors (M11, M15, M16 and M17) are biased by DC voltages; wherein the n-channel current-gain transistor is biased by a first DC bias voltage (vbiasn1) and the p-channel current-gain transistor is biased by a second DC bias voltage (vbiasp1); characterized by first and second gain boosting capacitors (C2 and C4), wherein the first and second capacitors (C2 and C4) pass the first input signal (vin) to the gates of the n-channel current-gain transistor and the p-channel current-gain transistor, respectively, while blocking said DC bias voltages (vbiasn1 and vbiasp1), respectively, from the first input (105, 205), first and second gain boosting resistors (R1 and R3), wherein the first gain boosting resistor and the second gain boosting resistor pass said first and second DC bias voltages (vbiasp1 and vbiasn1) to the gates of the n-channel and p-channel current-gain transistors (M16 and M11), respectively. a p-channel cascode transistor and an n-channel cascode.transistor connected to each other in cascode configuration, an n-channel current-gain transistor and a p-channel current-gain transistor, wherein the gates of said p-channel and n-channel cascode and current-gain transistors (M11, M15, M16 and M17) are biased by DC voltages; wherein the n-channel current-gain transistor is biased by a first DC bias voltage (vbiasn1) and the p-channel current-gain transistor is biased by a second DC bias voltage (vbiasp1); characterized by first and second gain boosting capacitors (C2 and C4), wherein the first and second capacitors (C2 and C4) pass the first input signal (vin) to the gates of the n-channel current-gain transistor and the p-channel current-gain transistor, respectively, while blocking said DC bias voltages (vbiasn1 and vbiasp1), respectively, from the first input (105, 205), first and second gain boosting resistors (R1 and R3), wherein the first gain boosting resistor and the second gain boosting resistor pass said first and second DC bias voltages (vbiasp1 and vbiasn1) to the gates of the n-channel and p-channel current-gain transistors (M16 and M11), respectively.