A display device comprising within one pixel: a gate line including at least one line portion (21a, 21b) and extending in a first direction; a data line (171a, 171b) extending in a second direction crossing the first direction; a transistor (Qa, Qb) including a gate electrode (124a, 124b) connected to the gate line, a source electrode (173a, 173b) connected to the data line (171a, 171b), and a drain electrode (175a, 175b); a connecting portion; and a connecting member (73a, 73b) disposed between the data line (171a, 171b) and the source electrode (173a, 173b), the connecting member (73a, 73b) extends from the data line (171a, 171b) in the first direction such that the connecting member (73a, 73b) begins to overlap with the gate electrode (124a, 124b) when crossing the gate electrode edge and the connecting member (73a, 73b) further extends until it connects to the the source electrode (173a, 173b), wherein the data line (171a, 171b) includes a main portion crossing the at least one line portion (21a, 21b) of the gate line and a thinner portion (71, 71b) that extends from the main portion and does not overlap the at least one line portion (21a, 21b) of the gate line in the plan view, wherein the connecting portion, where the thinner portion (71, 71b) of the data line (171a, 171b) and the connecting member (73, 73b) are connected to each other, does not overlap the gate line and the gate electrode (124a, 124b) in plan view, and wherein the width of the main portion is greater than the width (W1, W1a, W1b) of the thinner portion (71, 71b), such that an edge of the data line (171a, 171b) where the main portion and the thinner portion (71, 71b) are connected to each other forms a curved edge, and the curved edge faces the transistor and does not overlap the gate line. a gate line including at least one line portion (21a, 21b) and extending in a first direction; a data line (171a, 171b) extending in a second direction crossing the first direction; a transistor (Qa, Qb) including a gate electrode (124a, 124b) connected to the gate line, a source electrode (173a, 173b) connected to the data line (171a, 171b), and a drain electrode (175a, 175b); a connecting portion; and a connecting member (73a, 73b) disposed between the data line (171a, 171b) and the source electrode (173a, 173b), the connecting member (73a, 73b) extends from the data line (171a, 171b) in the first direction such that the connecting member (73a, 73b) begins to overlap with the gate electrode (124a, 124b) when crossing the gate electrode edge and the connecting member (73a, 73b) further extends until it connects to the the source electrode (173a, 173b), wherein the data line (171a, 171b) includes a main portion crossing the at least one line portion (21a, 21b) of the gate line and a thinner portion (71, 71b) that extends from the main portion and does not overlap the at least one line portion (21a, 21b) of the gate line in the plan view, wherein the connecting portion, where the thinner portion (71, 71b) of the data line (171a, 171b) and the connecting member (73, 73b) are connected to each other, does not overlap the gate line and the gate electrode (124a, 124b) in plan view, and wherein the width of the main portion is greater than the width (W1, W1a, W1b) of the thinner portion (71, 71b), such that an edge of the data line (171a, 171b) where the main portion and the thinner portion (71, 71b) are connected to each other forms a curved edge, and the curved edge faces the transistor and does not overlap the gate line.