A data prefetcher in a microprocessor having a cache memory, wherein the data prefetcher is configured to receive a plurality of memory accesses each to an address within a memory block, wherein the plurality of memory access addresses are non-monotonically increasing or decreasing as a function of time, the data prefetcher comprising: a storage element; and control logic, coupled to the storage element, wherein as the plurality of memory accesses are received, the control logic is configured to: maintain within the storage element a largest address and a smallest address of the plurality of accesses and counts of changes to the largest and smallest addresses within the memory block; maintain a history of recently accessed cache lines implicated by the access addresses within the memory block; determine a predominant access direction based on the counts, wherein the predominant access direction corresponds to a clear direction trend among the plurality of memory accesses; determine a predominant access pattern based on the history, wherein the predominant access pattern corresponds to a clear pattern among the plurality of memory accesses; and prefetch into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block that are not indicated by the history as being recently accessed. a storage element; and control logic, coupled to the storage element, wherein as the plurality of memory accesses are received, the control logic is configured to: maintain within the storage element a largest address and a smallest address of the plurality of accesses and counts of changes to the largest and smallest addresses within the memory block; maintain a history of recently accessed cache lines implicated by the access addresses within the memory block; determine a predominant access direction based on the counts, wherein the predominant access direction corresponds to a clear direction trend among the plurality of memory accesses; determine a predominant access pattern based on the history, wherein the predominant access pattern corresponds to a clear pattern among the plurality of memory accesses; and prefetch into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block that are not indicated by the history as being recently accessed. maintain within the storage element a largest address and a smallest address of the plurality of accesses and counts of changes to the largest and smallest addresses within the memory block; maintain a history of recently accessed cache lines implicated by the access addresses within the memory block; determine a predominant access direction based on the counts, wherein the predominant access direction corresponds to a clear direction trend among the plurality of memory accesses; determine a predominant access pattern based on the history, wherein the predominant access pattern corresponds to a clear pattern among the plurality of memory accesses; and prefetch into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block that are not indicated by the history as being recently accessed.