A monolithic three-dimensional memory device comprising: at least one alternating stack of insulating layers (132, 232) and electrically conductive layers (146, 246) located over a semiconductor substrate (9, 10); memory openings extending through the at least one alternating stack (132, 146, 232, 246), wherein each of the memory openings is filled with an epitaxial channel portion contacting a portion of the semiconductor substrate (9, 10) and a memory stack structure; and support openings extending through the at least one alternating stack (132, 146, 232, 246), wherein each of the support openings is filled with a support pillar structure, characterised in that: each of the memory stack structures and the support pillar structures comprise an instance of a layer stack including charge storage material portions, a tunneling dielectric layer, and at least one vertical semiconductor channel layer (601, 602); each instance of the layer stack in the memory stack structures is vertically spaced from the semiconductor substrate (9, 10) by the respective epitaxial channel portion; and each instance of the layer stack in the support pillar structures is in physical contact with an impurity-doped semiconductor material portion of the semiconductor substrate (9, 10), wherein the impurity-doped semiconductor material portion has a greater concentration of an impurity species than the portions of the semiconductor substrate (9, 10) that contact the epitaxial channel portions. at least one alternating stack of insulating layers (132, 232) and electrically conductive layers (146, 246) located over a semiconductor substrate (9, 10); memory openings extending through the at least one alternating stack (132, 146, 232, 246), wherein each of the memory openings is filled with an epitaxial channel portion contacting a portion of the semiconductor substrate (9, 10) and a memory stack structure; and support openings extending through the at least one alternating stack (132, 146, 232, 246), wherein each of the support openings is filled with a support pillar structure, characterised in that: each of the memory stack structures and the support pillar structures comprise an instance of a layer stack including charge storage material portions, a tunneling dielectric layer, and at least one vertical semiconductor channel layer (601, 602); each instance of the layer stack in the memory stack structures is vertically spaced from the semiconductor substrate (9, 10) by the respective epitaxial channel portion; and each instance of the layer stack in the support pillar structures is in physical contact with an impurity-doped semiconductor material portion of the semiconductor substrate (9, 10), wherein the impurity-doped semiconductor material portion has a greater concentration of an impurity species than the portions of the semiconductor substrate (9, 10) that contact the epitaxial channel portions. each of the memory stack structures and the support pillar structures comprise an instance of a layer stack including charge storage material portions, a tunneling dielectric layer, and at least one vertical semiconductor channel layer (601, 602); each instance of the layer stack in the memory stack structures is vertically spaced from the semiconductor substrate (9, 10) by the respective epitaxial channel portion; and each instance of the layer stack in the support pillar structures is in physical contact with an impurity-doped semiconductor material portion of the semiconductor substrate (9, 10), wherein the impurity-doped semiconductor material portion has a greater concentration of an impurity species than the portions of the semiconductor substrate (9, 10) that contact the epitaxial channel portions.