An electronic device comprising: a substrate; a circuit layer on said substrate; at least one circuit component; a first dielectric layer stack comprising a first plurality of dielectric layers (21, 22, 34); at least one electrically conductive via in the first plurality of dielectric layers (21, 22, 34); a first liquid crystal polymer outer sealing layer on said first dielectric layer stack; characterized in the circuit layer comprising at least one solder pad; the electronic device further comprising: a LCP solder mask on said substrate and having at least one aperture aligned with said at least one solder pad; a fused seam between said substrate and said LCP solder mask; solder in the at least one aperture; a second dielectric layer stack comprising a second plurality of dielectric layers (21, 22, 34) on said substrate on a side thereof opposite said LCP solder mask; at least one electrically conductive via in the second plurality of dielectric layers (21, 22, 34); and a second LCP outer sealing layer on said second dielectric layer stack; wherein the at least one circuit component being electrically coupled to said at least one solder pad via said solder; wherein the first dielectric layer stack being on said LCP solder mask and having at least one aperture aligned with said at least one solder pad, and wherein the substrate is formed from LCP. a substrate; a circuit layer on said substrate; at least one circuit component; a first dielectric layer stack comprising a first plurality of dielectric layers (21, 22, 34); at least one electrically conductive via in the first plurality of dielectric layers (21, 22, 34); a first liquid crystal polymer outer sealing layer on said first dielectric layer stack; characterized in the circuit layer comprising at least one solder pad; the electronic device further comprising: a LCP solder mask on said substrate and having at least one aperture aligned with said at least one solder pad; a fused seam between said substrate and said LCP solder mask; solder in the at least one aperture; a second dielectric layer stack comprising a second plurality of dielectric layers (21, 22, 34) on said substrate on a side thereof opposite said LCP solder mask; at least one electrically conductive via in the second plurality of dielectric layers (21, 22, 34); and a second LCP outer sealing layer on said second dielectric layer stack; wherein the at least one circuit component being electrically coupled to said at least one solder pad via said solder; wherein the first dielectric layer stack being on said LCP solder mask and having at least one aperture aligned with said at least one solder pad, and wherein the substrate is formed from LCP. a LCP solder mask on said substrate and having at least one aperture aligned with said at least one solder pad; a fused seam between said substrate and said LCP solder mask; solder in the at least one aperture; a second dielectric layer stack comprising a second plurality of dielectric layers (21, 22, 34) on said substrate on a side thereof opposite said LCP solder mask; at least one electrically conductive via in the second plurality of dielectric layers (21, 22, 34); and a second LCP outer sealing layer on said second dielectric layer stack; wherein the at least one circuit component being electrically coupled to said at least one solder pad via said solder; wherein the first dielectric layer stack being on said LCP solder mask and having at least one aperture aligned with said at least one solder pad, and wherein the substrate is formed from LCP.