An apparatus comprising: a voltage regulator circuit configured to regulate the voltage on an output node that provides power to a load circuit having varying current draw, the voltage regulator circuit including: a gate-control node, wherein there is no direct current path between the output node and the gate-control node; an output transistor including a gate connected to the gate-control node and having a gate-source capacitance, the output transistor configured to: integrate the current applied to the gate-control node by storing the applied current in the gate-source capacitance to produce a voltage on the gate-control node; and adjust the amount of an output current provided to the output node in response to the voltage on the gate-control node; and comparator circuitry configured to: compare the output voltage on the output node to a first reference voltage and a second reference voltage and a third reference voltage, wherein the third reference voltage is lower than the first reference voltage and the first reference voltage is lower than the second reference voltage; decrease the voltage on the gate-control node by applying, in response to the feedback voltage being lower than the first reference voltage, a first pull-down circuit to the gate-control node; decrease the voltage on the gate-control node by applying a second pull-down circuit in response to the output voltage being lower than the third reference voltage; increase the voltage on the gate-control node by applying, in response to the output voltage being higher than the second reference voltage, a pull-up circuit to the gate-control node; and maintain the voltage on the gate-control node by disabling, in response to the output voltage being between the first and second reference voltages, the pull-up and pull-down circuits at the gate-control node. a gate-control node, wherein there is no direct current path between the output node and the gate-control node; an output transistor including a gate connected to the gate-control node and having a gate-source capacitance, the output transistor configured to: integrate the current applied to the gate-control node by storing the applied current in the gate-source capacitance to produce a voltage on the gate-control node; and adjust the amount of an output current provided to the output node in response to the voltage on the gate-control node; and integrate the current applied to the gate-control node by storing the applied current in the gate-source capacitance to produce a voltage on the gate-control node; and adjust the amount of an output current provided to the output node in response to the voltage on the gate-control node; and comparator circuitry configured to: compare the output voltage on the output node to a first reference voltage and a second reference voltage and a third reference voltage, wherein the third reference voltage is lower than the first reference voltage and the first reference voltage is lower than the second reference voltage; decrease the voltage on the gate-control node by applying, in response to the feedback voltage being lower than the first reference voltage, a first pull-down circuit to the gate-control node; decrease the voltage on the gate-control node by applying a second pull-down circuit in response to the output voltage being lower than the third reference voltage; increase the voltage on the gate-control node by applying, in response to the output voltage being higher than the second reference voltage, a pull-up circuit to the gate-control node; and maintain the voltage on the gate-control node by disabling, in response to the output voltage being between the first and second reference voltages, the pull-up and pull-down circuits at the gate-control node. compare the output voltage on the output node to a first reference voltage and a second reference voltage and a third reference voltage, wherein the third reference voltage is lower than the first reference voltage and the first reference voltage is lower than the second reference voltage; decrease the voltage on the gate-control node by applying, in response to the feedback voltage being lower than the first reference voltage, a first pull-down circuit to the gate-control node; decrease the voltage on the gate-control node by applying a second pull-down circuit in response to the output voltage being lower than the third reference voltage; increase the voltage on the gate-control node by applying, in response to the output voltage being higher than the second reference voltage, a pull-up circuit to the gate-control node; and maintain the voltage on the gate-control node by disabling, in response to the output voltage being between the first and second reference voltages, the pull-up and pull-down circuits at the gate-control node.