A semiconductor device, comprising: a semiconductor substrate; a bottom barrier layer above the semiconductor substrate; a three-dimensional group Ill - V material body with a channel region above the bottom barrier layer; a source region disposed above the three-dimensional III-V material body and on a first side of the channel region; a drain region disposed above the three-dimensional III-V material body and on a second side of the channel region, the second side of the channel region being opposite the first side; a top barrier layer provided between the three-dimensional group III - V material body and source/drain regions (214, 216), the top barrier layer, the bottom barrier layer and the three-dimensional group Ill - V material body forming a heterostructure; a trench separating the source region from the drain region, said trench being disposed in the top barrier layer and partially disposed in the bottom barrier layer and exposing the channel region; a gate stack disposed in the trench and on the exposed portion of the channel region, the gate stack comprising: a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region; a second gate dielectric layer conformal with and disposed on the first dielectric layer around the channel region, the second gate dielectric layer being on the first gate dielectric layer and separated from the channel region by the first gate dielectric layer, the second gate dielectric layer having a higher dielectric constant than the first gate dielectric layer; a gate electrode disposed on the second dielectric layer around the channel region, the gate electrode being separated from the channel region by both the first gate dielectric layer and the second gate dielectric layer, wherein the gate stack completely surrounds the channel region. a semiconductor substrate; a bottom barrier layer above the semiconductor substrate; a three-dimensional group Ill - V material body with a channel region above the bottom barrier layer; a source region disposed above the three-dimensional III-V material body and on a first side of the channel region; a drain region disposed above the three-dimensional III-V material body and on a second side of the channel region, the second side of the channel region being opposite the first side; a top barrier layer provided between the three-dimensional group III - V material body and source/drain regions (214, 216), the top barrier layer, the bottom barrier layer and the three-dimensional group Ill - V material body forming a heterostructure; a trench separating the source region from the drain region, said trench being disposed in the top barrier layer and partially disposed in the bottom barrier layer and exposing the channel region; a gate stack disposed in the trench and on the exposed portion of the channel region, the gate stack comprising: a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region; a second gate dielectric layer conformal with and disposed on the first dielectric layer around the channel region, the second gate dielectric layer being on the first gate dielectric layer and separated from the channel region by the first gate dielectric layer, the second gate dielectric layer having a higher dielectric constant than the first gate dielectric layer; a gate electrode disposed on the second dielectric layer around the channel region, the gate electrode being separated from the channel region by both the first gate dielectric layer and the second gate dielectric layer, wherein the gate stack completely surrounds the channel region. a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region; a second gate dielectric layer conformal with and disposed on the first dielectric layer around the channel region, the second gate dielectric layer being on the first gate dielectric layer and separated from the channel region by the first gate dielectric layer, the second gate dielectric layer having a higher dielectric constant than the first gate dielectric layer; a gate electrode disposed on the second dielectric layer around the channel region, the gate electrode being separated from the channel region by both the first gate dielectric layer and the second gate dielectric layer, wherein the gate stack completely surrounds the channel region.