A stacked arrangement of active dies having a composite drain (104, 404, 504), a composite source, and a composite gate (106, 406, 506), said stacked arrangement of active dies comprising: a group IV vertical transistor die; a group III-V transistor die stacked over said group IV vertical transistor die, said group III-V transistor die having a drain electrode (414, 514) on a front side of said group III-V transistor die coupled to a drain pad on a back side of said group III-V transistor die by a through-substrate via (218, 418, 518); a drain electrode (124, 324, 424) of said group IV vertical transistor die on a top side of said group IV vertical transistor die being in direct contact with a source electrode (112, 212) of said group III-V transistor die on said back side of said group III-V transistor die, said source electrode of said group III-V transistor die situated on said drain electrode of said group IV vertical transistor die; a gate electrode (116, 216) of said group III-V transistor die on said back side of said group III-V transistor die being situated on a gate receiving pad on a top side of said group IV vertical transistor die such that a source electrode (122, 322) of said group IV vertical transistor die on a bottom side of said group IV vertical transistor die is coupled to said gate electrode of said group III-V transistor die to provide said composite source on a bottom side of said stacked arrangement of active dies; said drain electrode (114, 214, 414, 514) of said group III-V transistor die providing said composite drain on a top side of said stacked arrangement of active dies; a gate (126, 326, 426, 526) of said group IV vertical transistor die providing said composite gate (106, 406, 506) on said top side of said stacked arrangement of active dies. a group IV vertical transistor die; a group III-V transistor die stacked over said group IV vertical transistor die, said group III-V transistor die having a drain electrode (414, 514) on a front side of said group III-V transistor die coupled to a drain pad on a back side of said group III-V transistor die by a through-substrate via (218, 418, 518); a drain electrode (124, 324, 424) of said group IV vertical transistor die on a top side of said group IV vertical transistor die being in direct contact with a source electrode (112, 212) of said group III-V transistor die on said back side of said group III-V transistor die, said source electrode of said group III-V transistor die situated on said drain electrode of said group IV vertical transistor die; a gate electrode (116, 216) of said group III-V transistor die on said back side of said group III-V transistor die being situated on a gate receiving pad on a top side of said group IV vertical transistor die such that a source electrode (122, 322) of said group IV vertical transistor die on a bottom side of said group IV vertical transistor die is coupled to said gate electrode of said group III-V transistor die to provide said composite source on a bottom side of said stacked arrangement of active dies; said drain electrode (114, 214, 414, 514) of said group III-V transistor die providing said composite drain on a top side of said stacked arrangement of active dies; a gate (126, 326, 426, 526) of said group IV vertical transistor die providing said composite gate (106, 406, 506) on said top side of said stacked arrangement of active dies.