A frame rate conversion circuit comprising: a first selection circuitry configured to receive a plurality of video signals (1252, 1254, 1256) and to select a video signal of the plurality of video signals; a first scaler positioning module comprising: a first scaler slot positioned within a first video signal path of at least two video signal paths and configured to receive the selected video signal from the selection circuitry, wherein the first scaler positioning module includes a connection to a memory interface connecting an output of the first scaler slot to the memory interface, a second scaler slot positioned within a second video signal path of the at least two video signal paths and configured to receive a stored video signal from the memory interface, wherein the connection to the memory interface is connecting an output of the memory interface to the second scaler slot, a second selection circuitry comprising a first input and a second input, a first scaler placed in the first scaler slot, wherein the first scaler is configured to: scale the selected video signal, write the scaled video signal to a memory via the memory interface, and output the scaled video signal to the first input of the second selection circuitry, and a second scaler placed in the second scaler slot, wherein the second scaler is configured to: read the scaled video signal from the memory via the memory interface; further scale the read scaled video signal; and output the further scaled video signal to the second input of the second selection circuitry; and wherein the second selection circuitry is connected to the output of the first scaler slot and to the output of the second scaler slot, wherein the second selection circuitry is configured to select the output of the first scaler slot or the output of the second scaler slot. a first selection circuitry configured to receive a plurality of video signals (1252, 1254, 1256) and to select a video signal of the plurality of video signals; a first scaler positioning module comprising: a first scaler slot positioned within a first video signal path of at least two video signal paths and configured to receive the selected video signal from the selection circuitry, wherein the first scaler positioning module includes a connection to a memory interface connecting an output of the first scaler slot to the memory interface, a second scaler slot positioned within a second video signal path of the at least two video signal paths and configured to receive a stored video signal from the memory interface, wherein the connection to the memory interface is connecting an output of the memory interface to the second scaler slot, a second selection circuitry comprising a first input and a second input, a first scaler placed in the first scaler slot, wherein the first scaler is configured to: scale the selected video signal, write the scaled video signal to a memory via the memory interface, and output the scaled video signal to the first input of the second selection circuitry, and a second scaler placed in the second scaler slot, wherein the second scaler is configured to: read the scaled video signal from the memory via the memory interface; further scale the read scaled video signal; and output the further scaled video signal to the second input of the second selection circuitry; and wherein the second selection circuitry is connected to the output of the first scaler slot and to the output of the second scaler slot, wherein the second selection circuitry is configured to select the output of the first scaler slot or the output of the second scaler slot. a first scaler slot positioned within a first video signal path of at least two video signal paths and configured to receive the selected video signal from the selection circuitry, wherein the first scaler positioning module includes a connection to a memory interface connecting an output of the first scaler slot to the memory interface, a second scaler slot positioned within a second video signal path of the at least two video signal paths and configured to receive a stored video signal from the memory interface, wherein the connection to the memory interface is connecting an output of the memory interface to the second scaler slot, a second selection circuitry comprising a first input and a second input, a first scaler placed in the first scaler slot, wherein the first scaler is configured to: scale the selected video signal, write the scaled video signal to a memory via the memory interface, and output the scaled video signal to the first input of the second selection circuitry, and scale the selected video signal, write the scaled video signal to a memory via the memory interface, and output the scaled video signal to the first input of the second selection circuitry, and a second scaler placed in the second scaler slot, wherein the second scaler is configured to: read the scaled video signal from the memory via the memory interface; further scale the read scaled video signal; and output the further scaled video signal to the second input of the second selection circuitry; and wherein the second selection circuitry is connected to the output of the first scaler slot and to the output of the second scaler slot, wherein the second selection circuitry is configured to select the output of the first scaler slot or the output of the second scaler slot. read the scaled video signal from the memory via the memory interface; further scale the read scaled video signal; and output the further scaled video signal to the second input of the second selection circuitry; and