A processor for performing deep learning, the processor comprising: a controller; a processing element array including a plurality of processing elements, wherein: i) the plurality of processing elements comprise first processing elements, ii) the plurality of processing elements are arranged in a matrix of a number of rows and a number of columns, iii) a first row of the processing element array includes the first processing elements, iv) a second row of the processing element array includes second processing elements; a first data input interface connected to each processing element of the first processing elements, wherein the first data input interface is configured to input filter data to the first processing elements; a second data input interface connected to each processing element of the processing element array, wherein the second data input interface is configured to input target data to the processing element array; and a shifter including a plurality of registers, wherein: i) a first register of the plurality of registers is connected to the first row, ii) a second register of the plurality of registers is connected to the second row, and iii) the shifter is configured to input a plurality of processing instructions to the processing element array, wherein the plurality of processing instructions includes a first processing instruction, wherein the processor is configured to, in a first cycle, control the first data input interface to input a first element from among a plurality of elements included in the filter data to the first processing elements, control the second data input interface to input first data from among the target data to each of the first processing elements, and control the processing element array to process the first element and the first data based on the first processing instruction which is input through the shifter, and wherein the processor is configured to, in a second cycle following the first cycle, control the processing element array to shift the first element to the second processing elements, control the second data input interface to input second data from among the target data to each of the second processing elements, and control the processing element array to process the first element shifted from the first row and the second data based on the first processing instruction inputted through the shifter. a controller; a processing element array including a plurality of processing elements, wherein: i) the plurality of processing elements comprise first processing elements, ii) the plurality of processing elements are arranged in a matrix of a number of rows and a number of columns, iii) a first row of the processing element array includes the first processing elements, iv) a second row of the processing element array includes second processing elements; a first data input interface connected to each processing element of the first processing elements, wherein the first data input interface is configured to input filter data to the first processing elements; a second data input interface connected to each processing element of the processing element array, wherein the second data input interface is configured to input target data to the processing element array; and a shifter including a plurality of registers, wherein: i) a first register of the plurality of registers is connected to the first row, ii) a second register of the plurality of registers is connected to the second row, and iii) the shifter is configured to input a plurality of processing instructions to the processing element array, wherein the plurality of processing instructions includes a first processing instruction, wherein the processor is configured to, in a first cycle, control the first data input interface to input a first element from among a plurality of elements included in the filter data to the first processing elements, control the second data input interface to input first data from among the target data to each of the first processing elements, and control the processing element array to process the first element and the first data based on the first processing instruction which is input through the shifter, and wherein the processor is configured to, in a second cycle following the first cycle, control the processing element array to shift the first element to the second processing elements, control the second data input interface to input second data from among the target data to each of the second processing elements, and control the processing element array to process the first element shifted from the first row and the second data based on the first processing instruction inputted through the shifter.