A method for operating an ST-MRAM array, comprising: calculating a plurality of Error Correction Code, ECC, bits (306, 422) associated with an ECC word of a ST-MRAM array, the ECC word associated with a plurality of data bits (308, 421) and each ECC bit of the plurality of ECC bits (306, 422) is calculated using an even number of data bits of the plurality of data bits associated with the ECC word; storing the plurality of ECC bits (306, 422) in the ST-MRAM array; determining the majority state associated with the plurality of data bits (308, 421); inverting the plurality of data bits (308, 421) to provide a plurality of inverted data bits (308, 421) based at least in part on the majority state of the plurality of data bits; storing the plurality of inverted data bits in the ST-MRAM array; storing at least one inversion status bit (304, 423) in the ST-MRAM array; reading the stored plurality of inverted data bits (308, 421), the stored plurality of ECC bits (306, 422), and the stored at least one inversion status bit (304, 423) from the ST-MRAM array; calculating each parity bit of a plurality of parity bits using an even number of the data bits (308, 421) of the stored plurality of inverted data bits read from the ST-MRAM array; detecting at least one error in the plurality of inverted data bits (308, 421) based at least in part on a comparison of the plurality of parity bits and the plurality of ECC bits (306, 422); generating a plurality of corrected ECC bits using the plurality of parity bits and the stored plurality of ECC bits (306, 422) read from the ST-MRAM array; generating a plurality of corrected data bits; inverting the plurality of corrected data bits based at least in part on the state of the at least one inversion status bit (304, 423). calculating a plurality of Error Correction Code, ECC, bits (306, 422) associated with an ECC word of a ST-MRAM array, the ECC word associated with a plurality of data bits (308, 421) and each ECC bit of the plurality of ECC bits (306, 422) is calculated using an even number of data bits of the plurality of data bits associated with the ECC word; storing the plurality of ECC bits (306, 422) in the ST-MRAM array; determining the majority state associated with the plurality of data bits (308, 421); inverting the plurality of data bits (308, 421) to provide a plurality of inverted data bits (308, 421) based at least in part on the majority state of the plurality of data bits; storing the plurality of inverted data bits in the ST-MRAM array; storing at least one inversion status bit (304, 423) in the ST-MRAM array; reading the stored plurality of inverted data bits (308, 421), the stored plurality of ECC bits (306, 422), and the stored at least one inversion status bit (304, 423) from the ST-MRAM array; calculating each parity bit of a plurality of parity bits using an even number of the data bits (308, 421) of the stored plurality of inverted data bits read from the ST-MRAM array; detecting at least one error in the plurality of inverted data bits (308, 421) based at least in part on a comparison of the plurality of parity bits and the plurality of ECC bits (306, 422); generating a plurality of corrected ECC bits using the plurality of parity bits and the stored plurality of ECC bits (306, 422) read from the ST-MRAM array; generating a plurality of corrected data bits; inverting the plurality of corrected data bits based at least in part on the state of the at least one inversion status bit (304, 423).