A system for clock recovery in digital video communication comprising: - a delay measurement block for generating Program Clock Reference input signals and for continuously determining time interval between successive Program Clock Reference input signals, - a first storage device connected to an output of said delay measurement block for introducing temporal delay and outputting a first Program Clock Reference signal corresponding to said time interval between arrival of successive Program Clock Reference input signals, - a Program Clock Reference inter-arrival time computation filtering device which comprises an Infinite Impulse Response filter coupled to a timer and is connected at its first input to an output of said first storage device and receiving a second Program Clock Reference signal from said delay measurement block for determining an average time of arrival difference between successive Program Clock Reference packets by applying filtering on Program Clock Reference packets, - an error correction device connected to an output of said Program Clock Reference inter-arrival time computation filtering device for minimizing the error in the average Program Clock Reference difference between successive Program Clock Reference packets by converting the average difference between successive system clock signals to frequency error, - a controlled system clock generator which comprises a Phase Locked Loop device and is connected to the output of said error correction device to generate system clock, - a second storage device connected at the output of said controlled system clock generator for generating a first system clock output signal, - a controlled clock period difference computation element which comprises a voltage-to-frequency conversion device and has a first input connected to a first clock system output of said second storage element and a second input connected to a second system clock output of said controlled system clock generator, for computing the clock period difference between first and second system clock signals at said first and second system clock outputs said controlled clock period difference computation element being coupled at its output to said error correction device to form a feedback loop for minimizing the error between said system clock signals and successive Program Clock Reference differences observed by correcting a frequency of said system clock signals at regular interval. - a delay measurement block for generating Program Clock Reference input signals and for continuously determining time interval between successive Program Clock Reference input signals, - a first storage device connected to an output of said delay measurement block for introducing temporal delay and outputting a first Program Clock Reference signal corresponding to said time interval between arrival of successive Program Clock Reference input signals, - a Program Clock Reference inter-arrival time computation filtering device which comprises an Infinite Impulse Response filter coupled to a timer and is connected at its first input to an output of said first storage device and receiving a second Program Clock Reference signal from said delay measurement block for determining an average time of arrival difference between successive Program Clock Reference packets by applying filtering on Program Clock Reference packets, - an error correction device connected to an output of said Program Clock Reference inter-arrival time computation filtering device for minimizing the error in the average Program Clock Reference difference between successive Program Clock Reference packets by converting the average difference between successive system clock signals to frequency error, - a controlled system clock generator which comprises a Phase Locked Loop device and is connected to the output of said error correction device to generate system clock, - a second storage device connected at the output of said controlled system clock generator for generating a first system clock output signal, - a controlled clock period difference computation element which comprises a voltage-to-frequency conversion device and has a first input connected to a first clock system output of said second storage element and a second input connected to a second system clock output of said controlled system clock generator, for computing the clock period difference between first and second system clock signals at said first and second system clock outputs