A computer-implemented method of assessing the performance of a hardware design for an integrated circuit to complete a symbolic task, wherein the symbolic task represents a set or group of tasks using one or more symbolic variables, the method comprising: (a) receiving the hardware design (102, 502); (b) receiving a hardware monitor (106, 500) comprising: monitoring and counting logic (108, 514) configured to: monitor one or more control signals and/or data signals of the hardware design (102, 502) to identify start and completion of the symbolic task; and count a number of cycles between the start and the completion of the symbolic task; and property evaluation logic (110, 516) configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design (102, 502) in completing the symbolic task; (c) formally verifying, using a formal verification tool, that the one or more formal properties hold for the hardware design for each task of the set or group of tasks which the symbolic task represents by verifying that the one or more formal properties hold for all valid values of the one or more symbolic variables; and (d) outputting an indication of whether each of the one or more formal properties was successfully verified, the indication providing an exhaustive assessment of the performance of the hardware design in completing the task. (a) receiving the hardware design (102, 502); (b) receiving a hardware monitor (106, 500) comprising: monitoring and counting logic (108, 514) configured to: monitor one or more control signals and/or data signals of the hardware design (102, 502) to identify start and completion of the symbolic task; and count a number of cycles between the start and the completion of the symbolic task; and property evaluation logic (110, 516) configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design (102, 502) in completing the symbolic task; monitoring and counting logic (108, 514) configured to: monitor one or more control signals and/or data signals of the hardware design (102, 502) to identify start and completion of the symbolic task; and count a number of cycles between the start and the completion of the symbolic task; and monitor one or more control signals and/or data signals of the hardware design (102, 502) to identify start and completion of the symbolic task; and count a number of cycles between the start and the completion of the symbolic task; and property evaluation logic (110, 516) configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design (102, 502) in completing the symbolic task; (c) formally verifying, using a formal verification tool, that the one or more formal properties hold for the hardware design for each task of the set or group of tasks which the symbolic task represents by verifying that the one or more formal properties hold for all valid values of the one or more symbolic variables; and (d) outputting an indication of whether each of the one or more formal properties was successfully verified, the indication providing an exhaustive assessment of the performance of the hardware design in completing the task.