A matched filtering circuit apparatus in a baseband processing system of a terminal device, wherein n working clocks is taken as a processing period, and the n is a number of code channels that matched filtering circuit apparatus must deal with, the matched filtering circuit apparatus is located in a joint detection circuit in said baseband processing system, joint detection technology fully uses all users' signals which cause the multiple access interference as well as prior information of correlated multipath and takes user signal separation as a uniform correlated joint detection process, and said matched filtering circuit apparatus comprising a control unit, a vector buffer unit, a shift integral selection unit, a correlator unit, as well as a coherent integral unit, being characterized in that, said control unit is configured to control processes of de-scrambling, de-spreading, de-rotating and maximum ratio combining data; an output port of said control unit connects to said vector buffer unit, said shift integral selection unit and said coherent integral unit simultaneously; said vector buffer unit is configured to perform data buffer, so that the matched filtering circuit apparatus performs matched filtering operation and data buffer simultaneously; said control unit comprises a control signal generation logic unit and a counter, wherein, said control signal generation logic unit is located at the output port of said control unit; said counter connects to said control signal generation logic unit and is configured to count under the control of a matched filtering start indication signal, and send the counted result to the control signal generation logic as a time coordinate of a matched filter; said control signal generation logic unit is located behind said counter and is configured to generate and output a vector buffer unit control signal, a shift buffer enabling and selection control signal, and an integral unit control signal; wherein said shift integral selection unit comprises two shift buffer register groups and one selector group, wherein, said selector group is located between the two shift buffer register groups and configured to sample and output antenna data buffered in real time in said shift integral selection unit under the control of said shift buffer enabling and selection control signal; wherein said correlator unit comprises a plurality of correlators and an adder group, wherein, each of said plurality of correlators is configured to multiply said vector elements with said antenna data, and an output port of said correlator directly connects to an input port of said adder group; said adder group is configured to accumulate the multiplication result of a single correlator; wherein, said coherent integral unit comprises a selector, a coherent integral adder and a coherent integral buffer, wherein, an input port of said coherent integral adder connects to output ports of said selector and said correlator unit; said coherent integral adder is configured to implement integral operation on all chip sample data of all symbols in code channels under the control of said integral unit control signal, and an output port of the coherent integral accumulator connects to an input port of the coherent integral buffer, wherein the integral operation is an operation to accumulate a summation result output by said correlator unit and a summation result of a same symbol in a previous period.