A transmitter configured to be coupled to a serial link having a plurality of video channels and at least one video clock channel, said transmitter including: at least one input coupled to receive video data and at least one input coupled to receive audio data; at least two outputs each configured to be coupled to a respective video channel of the serial link, including a clock output configured to be coupled to the video clock channel; and circuitry, coupled between the outputs and each said input, characterized in that the circuitry is configured to generate encoded video data and encoded audio data by encoding the video data and audio data, to assert code words indicative of the encoded video data to each of the outputs in response to a pixel clock during active video periods, to assert packets including encoded auxiliary data to at least one of the outputs during data islands, and to assert the pixel clock to a receiver over the serial link, wherein each of the data islands is a time interval that neither coincides with nor overlaps any of the active video periods, the circuitry is configured to include time code data in an audio clock regeneration packet transmitted during a data island that occurs within a vertical blanking interval, the time code data comprising a numerator value and a denominator value that together define a fractional relationship between the pixel clock and an MCLK frequency, which is an integer multiple of 128 multiplied by the audio sample rate; and include audio sample packets, which are separate from the audio clock regeneration packets, and which contain one or more audio samples, and wherein each of the audio clock regeneration packet and the audio sample packet comprises a respective header containing a packet type identifier distinguishing the audio clock regeneration packet from the audio sample packet, and the time code data together with the pixel click are indicative of an audio clock. at least one input coupled to receive video data and at least one input coupled to receive audio data; at least two outputs each configured to be coupled to a respective video channel of the serial link, including a clock output configured to be coupled to the video clock channel; and circuitry, coupled between the outputs and each said input, characterized in that the circuitry is configured to generate encoded video data and encoded audio data by encoding the video data and audio data, to assert code words indicative of the encoded video data to each of the outputs in response to a pixel clock during active video periods, to assert packets including encoded auxiliary data to at least one of the outputs during data islands, and to assert the pixel clock to a receiver over the serial link, wherein each of the data islands is a time interval that neither coincides with nor overlaps any of the active video periods, the circuitry is configured to include time code data in an audio clock regeneration packet transmitted during a data island that occurs within a vertical blanking interval, the time code data comprising a numerator value and a denominator value that together define a fractional relationship between the pixel clock and an MCLK frequency, which is an integer multiple of 128 multiplied by the audio sample rate; and include audio sample packets, which are separate from the audio clock regeneration packets, and which contain one or more audio samples, and wherein each of the audio clock regeneration packet and the audio sample packet comprises a respective header containing a packet type identifier distinguishing the audio clock regeneration packet from the audio sample packet, and the time code data together with the pixel click are indicative of an audio clock.