A hardware implementation of a temporal memory system, comprising at least one array (360, 361, 362) of memory cells logically organized in rows and columns, each memory cell being adapted for storing a scalar value and adapted for changing the stored scalar value, each array being linked to a block of the temporal memory system, an input system adapted for receiving an input frame as input and creating a bundle of current block-level one-hot encoded binary strings of bit length M, by partitioning the input frame and quantizing the information contained in each partition, at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address, each addressing unit comprising - a column addressing unit adapted for receiving one of the current block-level one-hot encoded binary strings of bit length M as input and for concatenating replicas of the received current one-hot encoded binary string into a column address vector, or for receiving such column address vector, and for applying the column address vector as column addresses to the array of cells, and - a row addressing unit for receiving as input a row address vector and applying the row address vector as a row address to the array of cells, a shifting unit for enqueuing a row address vector, for dequeuing the enqueued row address vector delayed by at least one input frame, and for sending the delayed dequeued row address vector as input to the row addressing unit, and a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied and on the column addresses applied, each read out scalar value corresponding to a likelihood of temporal coincidence between the applied row address vector for a previously received input frame and the applied column address vector for a subsequently received input frame, this likelihood being adjustable through the scalar value stored in the memory cell, the reading unit being further adapted to generate a row address vector to be applied to the shifting unit, by identifying those memory cell or cells in the selected row of memory cells that satisfy a selection criterion, if such cell is available, or choosing an arbitrary addressed memory cell if none of the addressed cells satisfies the selection criterion, and sparsifying the column address vector based on the result of the reading step for obtaining a column address vector comprising only one logically high bit or only one logically low bit, and making this sparsified column address vector a row address vector. an input system adapted for receiving an input frame as input and creating a bundle of current block-level one-hot encoded binary strings of bit length M, by partitioning the input frame and quantizing the information contained in each partition, at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address, each addressing unit comprising - a column addressing unit adapted for receiving one of the current block-level one-hot encoded binary strings of bit length M as input and for concatenating replicas of the received current one-hot encoded binary string into a column address vector, or for receiving such column address vector, and for applying the column address vector as column addresses to the array of cells, and - a row addressing unit for receiving as input a row address vector and applying the row address vector as a row address to the array of cells, - a column addressing unit adapted for receiving one of the current block-level one-hot encoded binary strings of bit length M as input and for concatenating replicas of the received current one-hot encoded binary string into a column address vector, or for receiving such column address vector, and for applying the column address vector as column addresses to the array of cells, and - a row addressing unit for receiving as input a row address vector and applying the row address vector as a row address to the array of cells, a shifting unit for enqueuing a row address vector, for dequeuing the enqueued row address vector delayed by at least one input frame, and for sending the delayed dequeued row address vector as input to the row addressing unit, and a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied and on the column addresses applied, each read out scalar value corresponding to a likelihood of temporal coincidence between the applied row address vector for a previously received input frame and the applied column address vector for a subsequently received input frame, this likelihood being adjustable through the scalar value stored in the memory cell, the reading unit being further adapted to generate a row address vector to be applied to the shifting unit, by identifying those memory cell or cells in the selected row of memory cells that satisfy a selection criterion, if such cell is available, or choosing an arbitrary addressed memory cell if none of the addressed cells satisfies the selection criterion, and sparsifying the column address vector based on the result of the reading step for obtaining a column address vector comprising only one logically high bit or only one logically low bit, and making this sparsified column address vector a row address vector.