A chip carrier socket for an electronic-photonic integrated-circuit assembly, the chip carrier socket comprising: a carrier bottom comprising one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each of the conductive vias being configured to provide electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom; and a carrier top configured to mate to the carrier bottom while enclosing the electronic-photonic integrated-circuit assembly within an enclosed cavity formed by the mating of the carrier top and carrier bottom; wherein the carrier bottom comprises a fluid inlet port and a fluid outlet port and/or the carrier top comprises a fluid inlet port and a fluid outlet port, the fluid inlet port and fluid outlet port each being configured to allow passage of cooling fluid between the interior and exterior of the enclosed cavity formed by the mating of the carrier top and carrier bottom, and characterised in that the carrier top comprises an optical via passing from a first surface of the carrier top to a second surface of the carrier top and arranged to couple to an optical port on the electronic-photonic integrated-circuit assembly, when the electronic-photonic integrated-circuit assembly is enclosed within the enclosed cavity formed by the mating of the carrier top and bottom, and/or characterised in that the carrier bottom comprises an optical via passing from one surface of the carrier bottom to a surface other than the one surface of the carrier bottom. a carrier bottom comprising one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each of the conductive vias being configured to provide electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom; and a carrier top configured to mate to the carrier bottom while enclosing the electronic-photonic integrated-circuit assembly within an enclosed cavity formed by the mating of the carrier top and carrier bottom; wherein the carrier bottom comprises a fluid inlet port and a fluid outlet port and/or the carrier top comprises a fluid inlet port and a fluid outlet port, the fluid inlet port and fluid outlet port each being configured to allow passage of cooling fluid between the interior and exterior of the enclosed cavity formed by the mating of the carrier top and carrier bottom, and characterised in that the carrier top comprises an optical via passing from a first surface of the carrier top to a second surface of the carrier top and arranged to couple to an optical port on the electronic-photonic integrated-circuit assembly, when the electronic-photonic integrated-circuit assembly is enclosed within the enclosed cavity formed by the mating of the carrier top and bottom, and/or characterised in that the carrier bottom comprises an optical via passing from one surface of the carrier bottom to a surface other than the one surface of the carrier bottom. the carrier top comprises an optical via passing from a first surface of the carrier top to a second surface of the carrier top and arranged to couple to an optical port on the electronic-photonic integrated-circuit assembly, when the electronic-photonic integrated-circuit assembly is enclosed within the enclosed cavity formed by the mating of the carrier top and bottom, and/or characterised in that the carrier bottom comprises an optical via passing from one surface of the carrier bottom to a surface other than the one surface of the carrier bottom.