A print fluid cartridge comprising: a fluid reservoir to store fluid; a fluid ejection die coupled to the fluid reservoir, the fluid ejection die comprising: a plurality of nozzles (102, 206, 256) to eject drops of fluid; a memory arrangement comprising: a plurality of memory banks (208, 308, 404, 510) arranged on a substrate to form a group of memory banks, each memory bank having memory units (110, 210), wherein one of the memory banks (208-n) is arranged at a top end, one of the memory banks is arranged at a bottom end, and the remaining memory banks are disposed serially between the memory banks at the top and bottom ends; at least one select register on the substrate, wherein the at least one select register is to generate a select signal to access the memory units (110, 210) in the plurality of memory banks (208, 308, 404, 510), wherein the at least one select register is disposed at the top end or the bottom end of the group of memory banks (208, 308, 404, 510); wherein the at least one select register comprises: a row select register (302, 406, 504) to generate a row select signal; a column select register (304, 408, 506) to generate a column select signal; and a bank select register (306, 410, 508) to generate a bank select signal, wherein the row select signal, the column select signal, and the bank select signal are routed to the plurality of memory banks (208, 308, 404, 510) from the same side of the group of memory banks. a fluid reservoir to store fluid; a fluid ejection die coupled to the fluid reservoir, the fluid ejection die comprising: a plurality of nozzles (102, 206, 256) to eject drops of fluid; a memory arrangement comprising: a plurality of memory banks (208, 308, 404, 510) arranged on a substrate to form a group of memory banks, each memory bank having memory units (110, 210), wherein one of the memory banks (208-n) is arranged at a top end, one of the memory banks is arranged at a bottom end, and the remaining memory banks are disposed serially between the memory banks at the top and bottom ends; at least one select register on the substrate, wherein the at least one select register is to generate a select signal to access the memory units (110, 210) in the plurality of memory banks (208, 308, 404, 510), wherein the at least one select register is disposed at the top end or the bottom end of the group of memory banks (208, 308, 404, 510); wherein the at least one select register comprises: a row select register (302, 406, 504) to generate a row select signal; a column select register (304, 408, 506) to generate a column select signal; and a bank select register (306, 410, 508) to generate a bank select signal, wherein the row select signal, the column select signal, and the bank select signal are routed to the plurality of memory banks (208, 308, 404, 510) from the same side of the group of memory banks. a plurality of nozzles (102, 206, 256) to eject drops of fluid; a memory arrangement comprising: a plurality of memory banks (208, 308, 404, 510) arranged on a substrate to form a group of memory banks, each memory bank having memory units (110, 210), wherein one of the memory banks (208-n) is arranged at a top end, one of the memory banks is arranged at a bottom end, and the remaining memory banks are disposed serially between the memory banks at the top and bottom ends; at least one select register on the substrate, wherein the at least one select register is to generate a select signal to access the memory units (110, 210) in the plurality of memory banks (208, 308, 404, 510), a plurality of memory banks (208, 308, 404, 510) arranged on a substrate to form a group of memory banks, each memory bank having memory units (110, 210), wherein one of the memory banks (208-n) is arranged at a top end, one of the memory banks is arranged at a bottom end, and the remaining memory banks are disposed serially between the memory banks at the top and bottom ends; at least one select register on the substrate, wherein the at least one select register is to generate a select signal to access the memory units (110, 210) in the plurality of memory banks (208, 308, 404, 510), wherein the at least one select register is disposed at the top end or the bottom end of the group of memory banks (208, 308, 404, 510); wherein the at least one select register comprises: a row select register (302, 406, 504) to generate a row select signal; a column select register (304, 408, 506) to generate a column select signal; and a bank select register (306, 410, 508) to generate a bank select signal, wherein the row select signal, the column select signal, and the bank select signal are routed to the plurality of memory banks (208, 308, 404, 510) from the same side of the group of memory banks. a row select register (302, 406, 504) to generate a row select signal; a column select register (304, 408, 506) to generate a column select signal; and a bank select register (306, 410, 508) to generate a bank select signal, wherein the row select signal, the column select signal, and the bank select signal are routed to the plurality of memory banks (208, 308, 404, 510) from the same side of the group of memory banks.