A liquid crystal display panel, comprising: a plurality of pixels arranged in a plurality of rows and columns; a plurality of data lines (D1, D2), each for providing date signals to the pixels in a column, and a plurality of gate-lines (G1, G2, G3), each for proving gate-line signals to the pixels in a row, wherein each of some or all of the pixels comprises: a first sub-pixel area comprising a first sub-pixel electrode ( 32 1) associated to a first capacitor (C lcA, CstA), the first sub-pixel electrode (32 1) arranged to receive the data signal from one of the data lines (Dl) via a first switching element (132 1); and a second sub-pixel area comprising a second sub-pixel electrode (34 1) associated to a second capacitor (ClcB), the second sub-pixel electrode being arranged to receive said data signal from said one of the data lines via a second switching element (134 1), wherein each of the first and second switching elements (132 1, 134 1) comprises a control end arranged to receive a first gate-line signal for charging the first capacitor (ClcA, CstA) and the second capacitor (ClcB), characterised in that: the second sub-pixel electrode (34 1) is connected to a first end of a third capacitor (CstB), and a second end of the third capacitor (CstB) is connectable to said one of the data lines via a third switching element, and the third switching element (136 1) comprises a control end also arranged to receive the first gate-line signal, and the second end of the third capacitor (CstB) is connected to a circuit element arranged to cause part of the electrical charge on the second capacitor to transfer to the third capacitor (CstB) when the first gate-line signal has at least partially passed. a plurality of pixels arranged in a plurality of rows and columns; a plurality of data lines (D1, D2), each for providing date signals to the pixels in a column, and a plurality of gate-lines (G1, G2, G3), each for proving gate-line signals to the pixels in a row, wherein each of some or all of the pixels comprises: a first sub-pixel area comprising a first sub-pixel electrode ( 32 1) associated to a first capacitor (C lcA, CstA), the first sub-pixel electrode (32 1) arranged to receive the data signal from one of the data lines (Dl) via a first switching element (132 1); and a second sub-pixel area comprising a second sub-pixel electrode (34 1) associated to a second capacitor (ClcB), the second sub-pixel electrode being arranged to receive said data signal from said one of the data lines via a second switching element (134 1), wherein each of the first and second switching elements (132 1, 134 1) comprises a control end arranged to receive a first gate-line signal for charging the first capacitor (ClcA, CstA) and the second capacitor (ClcB), characterised in that: the second sub-pixel electrode (34 1) is connected to a first end of a third capacitor (CstB), and a second end of the third capacitor (CstB) is connectable to said one of the data lines via a third switching element, and the third switching element (136 1) comprises a control end also arranged to receive the first gate-line signal, and the second end of the third capacitor (CstB) is connected to a circuit element arranged to cause part of the electrical charge on the second capacitor to transfer to the third capacitor (CstB) when the first gate-line signal has at least partially passed.