A phase detector of a phase-locked loop PLL, the phase detector comprising: a reference edge detector configured to assert a first phase tracking signal responsive to detecting a start edge of a received clock reference signal; a feedback edge detector configured to assert a second phase tracking signal responsive to detecting start edge of a received feedback signal corresponding to an output clock signal generated by the PLL; feedback pause controller FPC block configured to assert a feedback-pause-control FPC signal responsive to detecting an end edge of the feedback signal subsequent to detecting assertion of a pause signal; and a reset network configured to assert a reset signal to reset the reference edge detector and the feedback edge detector responsive to detecting either assertion of both the first phase tracking signal and the second phase tracking signal, or assertion of the FPC signal; wherein the pause signal is generated by a controller external to the phase detector responsive to the controller detecting a loss of reliability of the clock reference signal; wherein the phase detector further comprises: a time-limiter comprising: an absolute phase detection block configured to detect whether the first phase tracking signal or the second phase tracking signal is presently asserted; a delay timer block, coupled with the absolute phase detection block to detect whether a signal duration of the presently asserted first phase tracking signal or second phase tracking signal exceeds a threshold duration; and a pulse gating block, coupled with the delay timer block to de-assert the first phase tracking signal and the second phase tracking signal automatically responsive to the delay timer block determining that the signal duration exceeds the threshold duration at least until a next asserting of the reset signal. a reference edge detector configured to assert a first phase tracking signal responsive to detecting a start edge of a received clock reference signal; a feedback edge detector configured to assert a second phase tracking signal responsive to detecting start edge of a received feedback signal corresponding to an output clock signal generated by the PLL; feedback pause controller FPC block configured to assert a feedback-pause-control FPC signal responsive to detecting an end edge of the feedback signal subsequent to detecting assertion of a pause signal; and a reset network configured to assert a reset signal to reset the reference edge detector and the feedback edge detector responsive to detecting either assertion of both the first phase tracking signal and the second phase tracking signal, or assertion of the FPC signal; wherein the pause signal is generated by a controller external to the phase detector responsive to the controller detecting a loss of reliability of the clock reference signal; wherein the phase detector further comprises: a time-limiter comprising: an absolute phase detection block configured to detect whether the first phase tracking signal or the second phase tracking signal is presently asserted; a delay timer block, coupled with the absolute phase detection block to detect whether a signal duration of the presently asserted first phase tracking signal or second phase tracking signal exceeds a threshold duration; and a pulse gating block, coupled with the delay timer block to de-assert the first phase tracking signal and the second phase tracking signal automatically responsive to the delay timer block determining that the signal duration exceeds the threshold duration at least until a next asserting of the reset signal. an absolute phase detection block configured to detect whether the first phase tracking signal or the second phase tracking signal is presently asserted; a delay timer block, coupled with the absolute phase detection block to detect whether a signal duration of the presently asserted first phase tracking signal or second phase tracking signal exceeds a threshold duration; and a pulse gating block, coupled with the delay timer block to de-assert the first phase tracking signal and the second phase tracking signal automatically responsive to the delay timer block determining that the signal duration exceeds the threshold duration at least until a next asserting of the reset signal.