A convolutional accelerator, comprising: a feature line buffer; a kernel buffer separate from the feature line buffer; a Multiply-Accumulate, MAC cluster; a configuration register, and mode control circuitry coupled to the feature line buffer, the kernel buffer, and the MAC cluster. wherein the mode control circuitry: in a first mode of operation (2408, 2410, 2412, 2414) of the convolutional accelerator: stores feature data in the feature line buffer; stores kernel data in the kernel buffer; transfers feature data from the feature line buffer to the MAC cluster; and transfers kernel data from the kernel buffer to the MAC cluster; and in a second mode of operation (2420, 2422, 2424, 2426) of the convolutional accelerator: stores feature data in the kernel buffer; stores kernel data in the feature line buffer; transfers feature data from the kernel buffer to the MAC cluster; and transfers kernel data from the feature line buffer to the MAC cluster, wherein: the feature line buffer is a single port memory; the kernel buffer comprises a plurality of dual-port buffers, and the mode control circuitry, in operation, determines whether to operate in the first mode of operation (2408, 2410, 2412, 2414) or the second mode of operation (2420, 2422, 2424, 2426) based on a configuration parameter stored in the configuration register. a feature line buffer; a kernel buffer separate from the feature line buffer; a Multiply-Accumulate, MAC cluster; a configuration register, and mode control circuitry coupled to the feature line buffer, the kernel buffer, and the MAC cluster. wherein the mode control circuitry: in a first mode of operation (2408, 2410, 2412, 2414) of the convolutional accelerator: stores feature data in the feature line buffer; stores kernel data in the kernel buffer; transfers feature data from the feature line buffer to the MAC cluster; and transfers kernel data from the kernel buffer to the MAC cluster; and in a second mode of operation (2420, 2422, 2424, 2426) of the convolutional accelerator: stores feature data in the kernel buffer; stores kernel data in the feature line buffer; transfers feature data from the kernel buffer to the MAC cluster; and transfers kernel data from the feature line buffer to the MAC cluster, in a first mode of operation (2408, 2410, 2412, 2414) of the convolutional accelerator: stores feature data in the feature line buffer; stores kernel data in the kernel buffer; transfers feature data from the feature line buffer to the MAC cluster; and transfers kernel data from the kernel buffer to the MAC cluster; and stores feature data in the feature line buffer; stores kernel data in the kernel buffer; transfers feature data from the feature line buffer to the MAC cluster; and transfers kernel data from the kernel buffer to the MAC cluster; and in a second mode of operation (2420, 2422, 2424, 2426) of the convolutional accelerator: stores feature data in the kernel buffer; stores kernel data in the feature line buffer; transfers feature data from the kernel buffer to the MAC cluster; and transfers kernel data from the feature line buffer to the MAC cluster, stores feature data in the kernel buffer; stores kernel data in the feature line buffer; transfers feature data from the kernel buffer to the MAC cluster; and transfers kernel data from the feature line buffer to the MAC cluster, wherein: the feature line buffer is a single port memory; the kernel buffer comprises a plurality of dual-port buffers, and the mode control circuitry, in operation, determines whether to operate in the first mode of operation (2408, 2410, 2412, 2414) or the second mode of operation (2420, 2422, 2424, 2426) based on a configuration parameter stored in the configuration register. the feature line buffer is a single port memory; the kernel buffer comprises a plurality of dual-port buffers, and the mode control circuitry, in operation, determines whether to operate in the first mode of operation (2408, 2410, 2412, 2414) or the second mode of operation (2420, 2422, 2424, 2426) based on a configuration parameter stored in the configuration register.