An integrated circuit for handling voltage droop, the integrated circuit comprising: a delay chain system configured to monitor power supply voltage on the integrated circuit, the delay chain system comprising: a plurality of delay chains, wherein each of the plurality of delay chains comprises a delay chain path and each delay chain path comprises a different length; a controlled set of capture flops configured to sample each delay chain path every clock cycle to determine if the logic in the delay chain path completed during each clock cycle; and an adder configured to sum the number of delay chain paths determined to have completed during each clock cycle; a filter configured to detect a voltage droop by filtering the sum of the number of delay chain paths determined to have completed during each clock cycle; a clock phase generator and validator, configured to generate a plurality of independent clock phases and configured to determine a plurality of valid clock phases, wherein valid clock phases are phases that can be selected next to stretch the clock cycle; and a clock phase multiplexer configured to shift from a current clock phase to a next clock phase selected from the plurality of valid clock phases, such that the current clock cycle is stretched, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before the next clock cycle. a delay chain system configured to monitor power supply voltage on the integrated circuit, the delay chain system comprising: a plurality of delay chains, wherein each of the plurality of delay chains comprises a delay chain path and each delay chain path comprises a different length; a controlled set of capture flops configured to sample each delay chain path every clock cycle to determine if the logic in the delay chain path completed during each clock cycle; and an adder configured to sum the number of delay chain paths determined to have completed during each clock cycle; a plurality of delay chains, wherein each of the plurality of delay chains comprises a delay chain path and each delay chain path comprises a different length; a controlled set of capture flops configured to sample each delay chain path every clock cycle to determine if the logic in the delay chain path completed during each clock cycle; and an adder configured to sum the number of delay chain paths determined to have completed during each clock cycle; a filter configured to detect a voltage droop by filtering the sum of the number of delay chain paths determined to have completed during each clock cycle; a clock phase generator and validator, configured to generate a plurality of independent clock phases and configured to determine a plurality of valid clock phases, wherein valid clock phases are phases that can be selected next to stretch the clock cycle; and a clock phase multiplexer configured to shift from a current clock phase to a next clock phase selected from the plurality of valid clock phases, such that the current clock cycle is stretched, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before the next clock cycle.