A memory system, comprising: - a memory controller, for selectively generating at least a clock signal (CLK, WCK) and an inverted clock signal (CLKB, WCKB); and - a memory module which is coupled to the memory controller, wherein - the memory module is configured to receive at least the clock signal (CLK, WCK) and the inverted clock (CLKB, WCKB) signal from the memory controller, and - the memory module comprises: - a first termination resistor, wherein a first node of the first termination resistor is to configured receive the clock signal (CLK, WCK); - a second termination resistor, wherein a first node of the second termination resistor is to configured receive the inverted clock signal (CLKB, WCKB); - a switch module, coupled between the first termination resistor and the second termination resistor, for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor; - the memory controller is configured to selectively generate the clock signal (CLK, WCK) and the inverted clock signal (CLKB, WCKB) to the memory module via a first channel (210_1) and a second channel (210_2), respectively; and - when the memory controller does not generate the clock signal (CLK, WCK) and the inverted clock signal (CLKB, WCKB), the memory controller is configured to keep the first channel (210_1) and the second channel (210_2) at fixed differential voltage levels. - a memory controller, for selectively generating at least a clock signal (CLK, WCK) and an inverted clock signal (CLKB, WCKB); and - a memory module which is coupled to the memory controller, wherein - the memory module is configured to receive at least the clock signal (CLK, WCK) and the inverted clock (CLKB, WCKB) signal from the memory controller, and - the memory module comprises: - a first termination resistor, wherein a first node of the first termination resistor is to configured receive the clock signal (CLK, WCK); - a second termination resistor, wherein a first node of the second termination resistor is to configured receive the inverted clock signal (CLKB, WCKB); - a switch module, coupled between the first termination resistor and the second termination resistor, for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor; - a first termination resistor, wherein a first node of the first termination resistor is to configured receive the clock signal (CLK, WCK); - a second termination resistor, wherein a first node of the second termination resistor is to configured receive the inverted clock signal (CLKB, WCKB); - a switch module, coupled between the first termination resistor and the second termination resistor, for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor; - the memory controller is configured to selectively generate the clock signal (CLK, WCK) and the inverted clock signal (CLKB, WCKB) to the memory module via a first channel (210_1) and a second channel (210_2), respectively; and - when the memory controller does not generate the clock signal (CLK, WCK) and the inverted clock signal (CLKB, WCKB), the memory controller is configured to keep the first channel (210_1) and the second channel (210_2) at fixed differential voltage levels.