A digital-to-time converter "DTC" comprising: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input (F ref) to receive a first clock signal and a second input (F DCO) to receive a second clock signal, the first clock signal traversing a first path through the delay chain circuit, the second clock signal traversing a second path through the delay chain circuit, each of the delay cells having either a first state that adds a fast delay to the first path and a slow delay to the second path, or a second state that adds a slow delay to the first path and a fast delay to the second path; a dynamic element matching "DEM" controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively, to set each of the plurality of delay cells to either the first state or the second state, the DEM controller, responsive to a control signal, setting states of the plurality of delay cells such that n of the delay cells are in the first state and the remaining delay cells are in the second state; a phase detector coupled to outputs of the first path and the second path of the delay chain circuit, the phase detector configured to perform bang-bang phase detection on the outputs; an accumulator coupled to an output of the phase detector, the accumulator configured to accumulate the output of the phase detector; and a calibration circuit coupled to an output of the accumulator and an input of the DEM controller, the calibration circuit including an input to receive the control signal, the calibration circuit configured to adjust the control signal before the control signal is supplied to the DEM controller to compensate for power supply noise and mismatches in the delay chain by monitoring the output of the accumulator. a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input (F ref) to receive a first clock signal and a second input (F DCO) to receive a second clock signal, the first clock signal traversing a first path through the delay chain circuit, the second clock signal traversing a second path through the delay chain circuit, each of the delay cells having either a first state that adds a fast delay to the first path and a slow delay to the second path, or a second state that adds a slow delay to the first path and a fast delay to the second path; a dynamic element matching "DEM" controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively, to set each of the plurality of delay cells to either the first state or the second state, the DEM controller, responsive to a control signal, setting states of the plurality of delay cells such that n of the delay cells are in the first state and the remaining delay cells are in the second state; a phase detector coupled to outputs of the first path and the second path of the delay chain circuit, the phase detector configured to perform bang-bang phase detection on the outputs; an accumulator coupled to an output of the phase detector, the accumulator configured to accumulate the output of the phase detector; and a calibration circuit coupled to an output of the accumulator and an input of the DEM controller, the calibration circuit including an input to receive the control signal, the calibration circuit configured to adjust the control signal before the control signal is supplied to the DEM controller to compensate for power supply noise and mismatches in the delay chain by monitoring the output of the accumulator.