A current buffer used in a receiver arrangement characterized by: a first and a second transistors (M1, M2) connected in series with a first and a second current sources (I1, 12) such that the drain of the first transistor is directly connected to the source of the second transistor, wherein the source of the first transistor is directly connected to the first current source and the drain of the second transistor is directly connected to the second current source, wherein the input node (I n) of the current buffer is the source of the first transistor and the output node is the drain of the second transistor; a third transistor connected in series with a current mirror in between the drain of the first transistor and the output node, the current mirror comprising a fourth and a fifth transistor (M4, M5), wherein a source of the third transistor is directly connected to the drain of the first transistor; and a third current source connected to the output node;wherein in a direct path mode, the first and the second transistor (M1, M2) and the first and the second current source (II, 12) are turned on, while the third, the fourth and the fifth transistors (M3, M4, M5) and the third current source (I 3) are turned off, during the direct path mode a signal current at the input node (I n) directly appears at an output node (Out); and wherein in a mirror path mode, the second transistor and the second current source (I 2) are being turned off while the first, the third, the fourth and the fifth transistors (M1, M3, M4, M5) and the first and the third current sources (I 1, I 3) are turned on; wherein the current signal at the input node (I n) goes through the current mirror (M4, M5) and appears at the output node (Out) with a gain that is controlled by slicing the fifth transistor of the current mirror pair (M4, M5) and the third current source (I 3) allowing more than one gain in the mirror path mode. a first and a second transistors (M1, M2) connected in series with a first and a second current sources (I1, 12) such that the drain of the first transistor is directly connected to the source of the second transistor, wherein the source of the first transistor is directly connected to the first current source and the drain of the second transistor is directly connected to the second current source, wherein the input node (I n) of the current buffer is the source of the first transistor and the output node is the drain of the second transistor; a third transistor connected in series with a current mirror in between the drain of the first transistor and the output node, the current mirror comprising a fourth and a fifth transistor (M4, M5), wherein a source of the third transistor is directly connected to the drain of the first transistor; and a third current source connected to the output node;wherein in a direct path mode, the first and the second transistor (M1, M2) and the first and the second current source (II, 12) are turned on, while the third, the fourth and the fifth transistors (M3, M4, M5) and the third current source (I 3) are turned off, during the direct path mode a signal current at the input node (I n) directly appears at an output node (Out); and wherein in a mirror path mode, the second transistor and the second current source (I 2) are being turned off while the first, the third, the fourth and the fifth transistors (M1, M3, M4, M5) and the first and the third current sources (I 1, I 3) are turned on; wherein the current signal at the input node (I n) goes through the current mirror (M4, M5) and appears at the output node (Out) with a gain that is controlled by slicing the fifth transistor of the current mirror pair (M4, M5) and the third current source (I 3) allowing more than one gain in the mirror path mode.