A circuit for reading a sensor including a pixel matrix array, said circuit comprising: a plurality of voltage-to-delay converting circuits configured to receive, on an input, a voltage value representative of the voltage of a read conductor (LC, LC1 - LC3) of a respective column (C1 - C3) of pixels of said matrix array and to deliver as output a binary signal called a comparative signal, this signal being switched at a time dependent on the input voltage value; characterized in that it also comprises: - a plurality of frequency-multiplying circuits (CMF1 - CMF3), each associated with a group of at least one said voltage-to-delay converting circuit, having respective inputs connected to a common clock transmission line that is intended to propagate a clock signal called a primary clock signal, and respective outputs for clock signals (HS, HS1 - HS3), called secondary clock signals, of the primary clock signal, that are of a frequency that is a multiple of said primary clock signal, these circuits being configured to multiply the frequency of the primary clock signal present on their input by the same multiplicative factor; and a plurality of binary counters (CBN, CBN1 - CBN3), one for each of said voltage-to-delay converting circuits, having a same number of counting bits and configured to receive, on a first input, a said secondary clock signal, and, on a second input, the binary comparative signal delivered by the corresponding voltage-to-delay converting circuit, each of said counters being configured to count at a rate dictated by said secondary clock signal until said binary comparative signal switches. a plurality of voltage-to-delay converting circuits configured to receive, on an input, a voltage value representative of the voltage of a read conductor (LC, LC1 - LC3) of a respective column (C1 - C3) of pixels of said matrix array and to deliver as output a binary signal called a comparative signal, this signal being switched at a time dependent on the input voltage value; characterized in that it also comprises: - a plurality of frequency-multiplying circuits (CMF1 - CMF3), each associated with a group of at least one said voltage-to-delay converting circuit, having respective inputs connected to a common clock transmission line that is intended to propagate a clock signal called a primary clock signal, and respective outputs for clock signals (HS, HS1 - HS3), called secondary clock signals, of the primary clock signal, that are of a frequency that is a multiple of said primary clock signal, these circuits being configured to multiply the frequency of the primary clock signal present on their input by the same multiplicative factor; and - a plurality of frequency-multiplying circuits (CMF1 - CMF3), each associated with a group of at least one said voltage-to-delay converting circuit, having respective inputs connected to a common clock transmission line that is intended to propagate a clock signal called a primary clock signal, and respective outputs for clock signals (HS, HS1 - HS3), called secondary clock signals, of the primary clock signal, that are of a frequency that is a multiple of said primary clock signal, these circuits being configured to multiply the frequency of the primary clock signal present on their input by the same multiplicative factor; and a plurality of binary counters (CBN, CBN1 - CBN3), one for each of said voltage-to-delay converting circuits, having a same number of counting bits and configured to receive, on a first input, a said secondary clock signal, and, on a second input, the binary comparative signal delivered by the corresponding voltage-to-delay converting circuit, each of said counters being configured to count at a rate dictated by said secondary clock signal until said binary comparative signal switches.