A three-dimensional memory device, comprising: a substrate (202, 302); a memory stack ( 210, 334) comprising interleaved conductive layers (206, 332) and dielectric layers (208, 308, 348) above the substrate (202, 302); a channel structure (204, 310) extending vertically through the memory stack ( 210, 334); a channel local contact ( 224, 340) above and in contact with the channel structure ( 204, 310); a slit structure (226, 344) extending vertically through the memory stack ( 210, 334); and a peripheral local contact extending vertically to the substrate (202, 302) outside of the memory stack (210, 334), wherein upper ends of the channel local contact (224, 340), the slit structure ( 226, 344), and the peripheral local contact are flush with one another, the memory device further comprising: a channel contact above and in contact with the upper end of the channel local contact; a slit contact above and in contact with the upper end of the slit structure; and a peripheral contact above and in contact with the upper end of the peripheral local contact, wherein upper ends of the channel contact, the slit contact, and the peripheral contact are flush with one another; wherein the slit structure comprises: a source contact comprising a first source contact portion and a second source contact portion above the first source contact portion, the second source contact portion has a different material than the first source contact portion; and a spacer laterally between the source contact of the slit structure and the conductive layers of the memory stack; the memory device further comprising a staircase local contact (242, 343) above and in contact with one of the conductive layers (206, 332) at a staircase structure on an edge of the memory stack (210, 334), wherein an upper end of the staircase local contact (242, 343) is flush with the upper ends of the channel local contact (224, 340), the slit structure (226, 344), and the peripheral local contact, wherein the memory device further comprises a barrier structure (246, 307) which comprises interleaved first dielectric layers and second dielectric layers, wherein the peripheral local contact (244, 345) extends vertically through the barrier structure (246, 307). a substrate (202, 302); a memory stack ( 210, 334) comprising interleaved conductive layers (206, 332) and dielectric layers (208, 308, 348) above the substrate (202, 302); a channel structure (204, 310) extending vertically through the memory stack ( 210, 334); a channel local contact ( 224, 340) above and in contact with the channel structure ( 204, 310); a slit structure (226, 344) extending vertically through the memory stack ( 210, 334); and a peripheral local contact extending vertically to the substrate (202, 302) outside of the memory stack (210, 334), wherein upper ends of the channel local contact (224, 340), the slit structure ( 226, 344), and the peripheral local contact are flush with one another, a channel contact above and in contact with the upper end of the channel local contact; a slit contact above and in contact with the upper end of the slit structure; and a peripheral contact above and in contact with the upper end of the peripheral local contact, wherein upper ends of the channel contact, the slit contact, and the peripheral contact are flush with one another; wherein the slit structure comprises: a source contact comprising a first source contact portion and a second source contact portion above the first source contact portion, the second source contact portion has a different material than the first source contact portion; and a spacer laterally between the source contact of the slit structure and the conductive layers of the memory stack; the memory device further comprising a staircase local contact (242, 343) above and in contact with one of the conductive layers (206, 332) at a staircase structure on an edge of the memory stack (210, 334), wherein an upper end of the staircase local contact (242, 343) is flush with the upper ends of the channel local contact (224, 340), the slit structure (226, 344), and the peripheral local contact, wherein the memory device further comprises a barrier structure (246, 307) which comprises interleaved first dielectric layers and second dielectric layers, wherein the peripheral local contact (244, 345) extends vertically through the barrier structure (246, 307). a source contact comprising a first source contact portion and a second source contact portion above the first source contact portion, the second source contact portion has a different material than the first source contact portion; and a spacer laterally between the source contact of the slit structure and the conductive layers of the memory stack; the memory device further comprising a staircase local contact (242, 343) above and in contact with one of the conductive layers (206, 332) at a staircase structure on an edge of the memory stack (210, 334), wherein an upper end of the staircase local contact (242, 343) is flush with the upper ends of the channel local contact (224, 340), the slit structure (226, 344), and the peripheral local contact, wherein the memory device further comprises a barrier structure (246, 307) which comprises interleaved first dielectric layers and second dielectric layers, wherein the peripheral local contact (244, 345) extends vertically through the barrier structure (246, 307).