An integrated current reference circuit, comprising a first voltage source (Vcc); a voltage offset circuit having a first end and a second end; a reference current (Iref) having one end coupled to the second end of the voltage offset circuit and another end coupled to a ground potential; a first p-channel transistor having a source coupled to the first voltage source (Vcc), a gate coupled to the first end of the voltage offset circuit, and a drain coupled to the reference current (Iref); a second p-channel transistor having a source coupled to the first voltage source (Vcc), a gate coupled to the first end of the voltage offset circuit, and a drain configured to provide an output current (lout); characterised in that the voltage offset circuit comprises: a second voltage source (Vd); an n-channel transistor having a drain coupled to the second voltage source (Vd), a gate coupled to the drain of the first p-channel transistor, and a source coupled to the gate of the first p-channel transistor; and a first resistor coupled between the source of the n-channel transistor and the ground potential; wherein the first voltage source (Vcc) is about 0.9V to 1.0V, and the second voltage source (Vd) is about 0.6V; wherein the gate of the n-channel transistor has a voltage about 0.4V, and the gate of the first p-channel transistor has a voltage about 0.1V. a first voltage source (Vcc); a voltage offset circuit having a first end and a second end; a reference current (Iref) having one end coupled to the second end of the voltage offset circuit and another end coupled to a ground potential; a first p-channel transistor having a source coupled to the first voltage source (Vcc), a gate coupled to the first end of the voltage offset circuit, and a drain coupled to the reference current (Iref); a second p-channel transistor having a source coupled to the first voltage source (Vcc), a gate coupled to the first end of the voltage offset circuit, and a drain configured to provide an output current (lout); characterised in that the voltage offset circuit comprises: a second voltage source (Vd); an n-channel transistor having a drain coupled to the second voltage source (Vd), a gate coupled to the drain of the first p-channel transistor, and a source coupled to the gate of the first p-channel transistor; and a first resistor coupled between the source of the n-channel transistor and the ground potential; wherein the first voltage source (Vcc) is about 0.9V to 1.0V, and the second voltage source (Vd) is about 0.6V; wherein the gate of the n-channel transistor has a voltage about 0.4V, and the gate of the first p-channel transistor has a voltage about 0.1V. a second voltage source (Vd); an n-channel transistor having a drain coupled to the second voltage source (Vd), a gate coupled to the drain of the first p-channel transistor, and a source coupled to the gate of the first p-channel transistor; and a first resistor coupled between the source of the n-channel transistor and the ground potential; wherein the first voltage source (Vcc) is about 0.9V to 1.0V, and the second voltage source (Vd) is about 0.6V; wherein the gate of the n-channel transistor has a voltage about 0.4V, and the gate of the first p-channel transistor has a voltage about 0.1V.