An apparatus comprising: means for delaying (310, 410) an input signal by a first delay of an integer number of time units; and means for delaying (320, 330; 500; 600) the input signal further by a second delay of a fraction of one time unit based on extra loading provided by at least one dummy logic gate (518; 618), wherein the means for delaying the input signal further by the second delay comprises: means for passing (510, 512, 516; 610, 612, 616) the input signal via a first path without the extra loading if the second delay is not selected, means for passing (510, 514, 516; 610, 614, 616) the input signal via a second path with the extra loading coupled to the second path if the second delay is selected; and a second delay circuit comprising the first path providing a shorter delay when the first path is selected, the second path providing a longer delay when the second path is selected, and the at least one dummy logic gate being coupled to the second path and providing extra loading to obtain the longer delay for the second path; wherein the first path comprises first and second logic gates, the second path comprises the second logic gate and a third logic gate, and the at least one dummy logic gate is coupled to the third logic gate; characterized in that the at least one dummy logic gate is same type of logic gate as the first, second and third logic gates. means for delaying (310, 410) an input signal by a first delay of an integer number of time units; and means for delaying (320, 330; 500; 600) the input signal further by a second delay of a fraction of one time unit based on extra loading provided by at least one dummy logic gate (518; 618), wherein the means for delaying the input signal further by the second delay comprises: means for passing (510, 512, 516; 610, 612, 616) the input signal via a first path without the extra loading if the second delay is not selected, means for passing (510, 514, 516; 610, 614, 616) the input signal via a second path with the extra loading coupled to the second path if the second delay is selected; and a second delay circuit comprising the first path providing a shorter delay when the first path is selected, the second path providing a longer delay when the second path is selected, and the at least one dummy logic gate being coupled to the second path and providing extra loading to obtain the longer delay for the second path; wherein the first path comprises first and second logic gates, the second path comprises the second logic gate and a third logic gate, and the at least one dummy logic gate is coupled to the third logic gate; characterized in that the at least one dummy logic gate is same type of logic gate as the first, second and third logic gates. means for passing (510, 512, 516; 610, 612, 616) the input signal via a first path without the extra loading if the second delay is not selected, means for passing (510, 514, 516; 610, 614, 616) the input signal via a second path with the extra loading coupled to the second path if the second delay is selected; and a second delay circuit comprising the first path providing a shorter delay when the first path is selected, the second path providing a longer delay when the second path is selected, and the at least one dummy logic gate being coupled to the second path and providing extra loading to obtain the longer delay for the second path; wherein the first path comprises first and second logic gates, the second path comprises the second logic gate and a third logic gate, and the at least one dummy logic gate is coupled to the third logic gate; characterized in that the at least one dummy logic gate is same type of logic gate as the first, second and third logic gates.