An apparatus to measure time delay between clocks, comprising: a digital delay measurement circuit to detect edge events of a reference clock in relation to first and second clocks (102, 104) during a measurement period, count detected edge events during the measurement period, determine a delay between the first and second clocks (102, 104) based on the count, and generate a digital output value proportional to the delay between the first and second clocks (102, 104); characterised in that the delay measurement circuit includes: a digital phase detector to detect the edge events of the reference clock in relation to the first and second clocks (102, 104) during the measurement period, wherein the digital phase detector is configured to detect an edge event of the reference clock when an edge of the reference clock occurs between an edge of the first clock and a subsequent edge of the second clock; and a counter circuit to count the detected edge events during the measurement period; wherein the delay measurement circuit is configured to determine the delay between the first and second clocks (102, 104) based on the count; wherein the counter circuit is configured to count detected edge events of the reference clock and edges of the reference clock during the measurement period; and the delay measurement circuit is further configured to determine the delay between the first and second clocks (102, 104) based on a ratio of a number of detected edge events to a number of reference clock edges counted during the measurement period. a digital delay measurement circuit to detect edge events of a reference clock in relation to first and second clocks (102, 104) during a measurement period, count detected edge events during the measurement period, determine a delay between the first and second clocks (102, 104) based on the count, and generate a digital output value proportional to the delay between the first and second clocks (102, 104); characterised in that the delay measurement circuit includes: a digital phase detector to detect the edge events of the reference clock in relation to the first and second clocks (102, 104) during the measurement period, wherein the digital phase detector is configured to detect an edge event of the reference clock when an edge of the reference clock occurs between an edge of the first clock and a subsequent edge of the second clock; and a counter circuit to count the detected edge events during the measurement period; a digital phase detector to detect the edge events of the reference clock in relation to the first and second clocks (102, 104) during the measurement period, wherein the digital phase detector is configured to detect an edge event of the reference clock when an edge of the reference clock occurs between an edge of the first clock and a subsequent edge of the second clock; and a counter circuit to count the detected edge events during the measurement period; wherein the delay measurement circuit is configured to determine the delay between the first and second clocks (102, 104) based on the count; wherein the counter circuit is configured to count detected edge events of the reference clock and edges of the reference clock during the measurement period; and the delay measurement circuit is further configured to determine the delay between the first and second clocks (102, 104) based on a ratio of a number of detected edge events to a number of reference clock edges counted during the measurement period.