A device structure for a nitride semiconductor transistor comprising: a substrate (312, 512, 712) having a nitride semiconductor layer formed on a device area of the substrate and defining a plurality of active regions for an array of islands of a multi-island transistor, each island having a source electrode (320, 520), a drain electrode (322, 522) and a gate electrode (326, 526) formed on a respective active region of the island, each source electrode having a plurality of source peninsulas, each drain electrode having a plurality of drain peninsulas, the source and drain peninsulas being interleaved and spaced apart over the active region of the island to define a channel region therebetween, and the gate electrode (326, 526) being formed on the nitride semiconductor layer over the channel region, and running between the source and drain peninsulas across the island, and characterized in that: the array of islands extending in first and second directions over the device area, the active region of each island comprising a two dimensional electron gas region, and the active region of each island being isolated in the first and second directions from active regions of adjacent islands by an intervening inactive region (370, 570) of the device area; the source, drain and gate electrodes of each island each having, respectively, a source contact area (340, 540), a drain contact area (342, 542) and gate contact area (346, 546); and the source, drain and gate electrodes of each island of the array of islands having an arrangement wherein: the source, drain and gate electrodes of each island are electrically isolated by said intervening inactive regions (370, 570) from the source, drain and gate electrodes of neighbouring islands in said first and second directions, and an overlying interconnect structure comprising at least one dielectric layer and at least one overlying metallization layer providing: a source interconnection (690, 790) interconnecting in parallel the source electrodes of sets of multiple islands; a drain interconnection (692, 792) interconnecting in parallel the drain electrodes of sets of multiple islands; and a gate interconnection interconnecting the gate electrodes of multiple islands to form a common gate; wherein said source, drain and gate interconnections are provided selectively through said at least one dielectric layer to respective said contact areas of source, drain and gate electrodes of non-defective islands, excluding defective islands, to provide electrical isolation of each defective island failing to meet electrical sp ecifications. the array of islands extending in first and second directions over the device area, the active region of each island comprising a two dimensional electron gas region, and the active region of each island being isolated in the first and second directions from active regions of adjacent islands by an intervening inactive region (370, 570) of the device area; the source, drain and gate electrodes of each island each having, respectively, a source contact area (340, 540), a drain contact area (342, 542) and gate contact area (346, 546); and the source, drain and gate electrodes of each island of the array of islands having an arrangement wherein: the source, drain and gate electrodes of each island are electrically isolated by said intervening inactive regions (370, 570) from the source, drain and gate electrodes of neighbouring islands in said first and second directions, and an overlying interconnect structure comprising at least one dielectric layer and at least one overlying metallization layer providing: a source interconnection (690, 790) interconnecting in parallel the source electrodes of sets of multiple islands; a drain interconnection (692, 792) interconnecting in parallel the drain electrodes of sets of multiple islands; and a source interconnection (690, 790) interconnecting in parallel the source electrodes of sets of multiple islands; a drain interconnection (692, 792) interconnecting in parallel the drain electrodes of sets of multiple islands; and