A method of improving stability of a memory device that includes a plurality of non-volatile memory cells and a controller configured to program each of the non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state, wherein each of the non-volatile memory cells comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between, a floating gate disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region, and a control gate disposed vertically over and insulated from the floating gate, the method comprising: testing the non-volatile memory cells to confirm the memory cells are operational: after the testing, programming each of the operational non-volatile memory cells to a mid-program state; and after the programming, baking the memory device at a high temperature while the operational non-volatile memory cells are programmed to the mid-program state; wherein a high bake temperature is an elevated temperature which exceeds the highest operating temperature endured by the memory device during normal use; wherein, for each of the non-volatile memory cells a non-volatile memory cell has a first threshold voltage when programmed in the minimum program state, the non-volatile memory cell has a second threshold voltage when programmed in the maximum program state, and the non-volatile memory cell has a third threshold voltage when programmed in the mid-program state, wherein the third threshold voltage is substantially at a mid-point between the first and second threshold voltages. spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between, a floating gate disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region, and a control gate disposed vertically over and insulated from the floating gate, the method comprising: testing the non-volatile memory cells to confirm the memory cells are operational: after the testing, programming each of the operational non-volatile memory cells to a mid-program state; and after the programming, baking the memory device at a high temperature while the operational non-volatile memory cells are programmed to the mid-program state; wherein a high bake temperature is an elevated temperature which exceeds the highest operating temperature endured by the memory device during normal use; wherein, for each of the non-volatile memory cells a non-volatile memory cell has a first threshold voltage when programmed in the minimum program state, the non-volatile memory cell has a second threshold voltage when programmed in the maximum program state, and the non-volatile memory cell has a third threshold voltage when programmed in the mid-program state, wherein the third threshold voltage is substantially at a mid-point between the first and second threshold voltages. testing the non-volatile memory cells to confirm the memory cells are operational: after the testing, programming each of the operational non-volatile memory cells to a mid-program state; and after the programming, baking the memory device at a high temperature while the operational non-volatile memory cells are programmed to the mid-program state; wherein a high bake temperature is an elevated temperature which exceeds the highest operating temperature endured by the memory device during normal use; wherein, for each of the non-volatile memory cells a non-volatile memory cell has a first threshold voltage when programmed in the minimum program state, the non-volatile memory cell has a second threshold voltage when programmed in the maximum program state, and the non-volatile memory cell has a third threshold voltage when programmed in the mid-program state, wherein the third threshold voltage is substantially at a mid-point between the first and second threshold voltages.