Phase locked loop, PLL, circuit (700,1000,1100) comprising a reference signal source (701, 704) and a voltage controlled oscillator for generating a phase and/or frequency controlled output signal, wherein a multi-modulus divider divides the output signal of the voltage controlled oscillator to generate a divider signal that is compared with a reference signal in a phase and/or frequency detector outputting an error signal that controls the voltage controlled oscillator, wherein the phase locked loop circuit comprises - a delay locked loop, DLL, as the reference signal source that provides n reference signals ( ref 1 -ref n) that have the same frequency and are shifted among each other by a fixed phase difference, wherein n is a natural number, - generator means (711 1 -711 n,712) for generating one associated divider signal for each reference signal ( ref 1 -ref n), - n phase frequency detectors and charge pumps (PFDs&CPs) (406 1 -406 n) configured such that each one of the reference signals ( ref 1 -ref n) and its associated divider signal ( div 1 -div n) are connected as a pair of input signals to one phase frequency detector and charge pump (PFD&CP) outputting an error signal if a frequency and/or phase difference is detected between the input signals; and - a node (∑) where all error signals generated by the phase frequency detectors and charge pumps (PFDs & CPs) are summed up to generate a control voltage signal for controlling the voltage controlled oscillator, characterized in that - the multi-modulus divider is operatively connected with an associated delta sigma modulator to form a fractional-N divider, wherein the generator means comprise a plurality of multi-modulus dividers and associated delta sigma modulators to form parallel fractional-N dividers (711 1 711 n) outputting the respective associated divider signals (div i -div n), wherein a multiphase splitter receives the output signal of the voltage controlled oscillator or of the pre-scaler receiving the output of the voltage controlled oscillator and outputs a plurality of phase shifted output signals to each one of the plurality of fractional-N dividers (711 1 -711 n). - a delay locked loop, DLL, as the reference signal source that provides n reference signals ( ref 1 -ref n) that have the same frequency and are shifted among each other by a fixed phase difference, wherein n is a natural number, - generator means (711 1 -711 n,712) for generating one associated divider signal for each reference signal ( ref 1 -ref n), - n phase frequency detectors and charge pumps (PFDs&CPs) (406 1 -406 n) configured such that each one of the reference signals ( ref 1 -ref n) and its associated divider signal ( div 1 -div n) are connected as a pair of input signals to one phase frequency detector and charge pump (PFD&CP) outputting an error signal if a frequency and/or phase difference is detected between the input signals; and - a node (∑) where all error signals generated by the phase frequency detectors and charge pumps (PFDs & CPs) are summed up to generate a control voltage signal for controlling the voltage controlled oscillator, characterized in that - the multi-modulus divider is operatively connected with an associated delta sigma modulator to form a fractional-N divider, wherein the generator means comprise a plurality of multi-modulus dividers and associated delta sigma modulators to form parallel fractional-N dividers (711 1 711 n) outputting the respective associated divider signals (div i -div n), wherein a multiphase splitter receives the output signal of the voltage controlled oscillator or of the pre-scaler receiving the output of the voltage controlled oscillator and outputs a plurality of phase shifted output signals to each one of the plurality of fractional-N dividers (711 1 -711 n). wherein the generator means comprise a plurality of multi-modulus dividers and associated delta sigma modulators to form parallel fractional-N dividers (711 1 711 n) outputting the respective associated divider signals (div i -div n), wherein a multiphase splitter receives the output signal of the voltage controlled oscillator or of the pre-scaler receiving the output of the voltage controlled oscillator and outputs a plurality of phase shifted output signals to each one of the plurality of fractional-N dividers (711 1 -711 n).