A low dropout voltage regulator apparatus comprising: a first node having a supply voltage; a second node providing the output voltage; a circuit ground node; a third node coupled to the circuit ground node through a resistive path comprising two resistances R3 and R4; a fourth node being between the two resistances on the resistive path; a multiple collector PNP transistor having the emitter connected to the supply voltage; a start-up current source connected between the first collector of the multiple collector PNP transistor and the ground note; a p-channel field effect transistor, FET, having the source coupled to the first node the drain coupled to the second node and the gate coupled to the first collector of the multiple collector PNP transistor; a voltage divider circuit comprising a first resistor, R1, a fifth node, and a second resistor R2, connected in series between the second node and the ground node, the fifth node being between the first resistor R1 and the second resistor R2; a first NPN bipolar isolation transistor; a second NPN bipolar isolation transistor having its base connected to the base of the first NPN bipolar transistor and to the fifth node; a load resistor connected between the second node and the ground node; a load capacitor in parallel with the load resistor and sharing the second node with the load resistor; the emitter of the first NPN bipolar isolation transistor being connected to the third node and the collector of the first NPN bipolar isolation transistor being connected to the first collector of the multiple collector PNP transistor; the emitter of the second NPN bipolar isolation transistor being connected to the fourth node and the collector of the second NPN bipolar transistor being connected to the second collector and the base of the multiple collector PNP transistor; characterized in that a feedback compensation capacitor is connected between the second node and the third node. a first node having a supply voltage; a second node providing the output voltage; a circuit ground node; a third node coupled to the circuit ground node through a resistive path comprising two resistances R3 and R4; a fourth node being between the two resistances on the resistive path; a multiple collector PNP transistor having the emitter connected to the supply voltage; a start-up current source connected between the first collector of the multiple collector PNP transistor and the ground note; a p-channel field effect transistor, FET, having the source coupled to the first node the drain coupled to the second node and the gate coupled to the first collector of the multiple collector PNP transistor; a voltage divider circuit comprising a first resistor, R1, a fifth node, and a second resistor R2, connected in series between the second node and the ground node, the fifth node being between the first resistor R1 and the second resistor R2; a first NPN bipolar isolation transistor; a second NPN bipolar isolation transistor having its base connected to the base of the first NPN bipolar transistor and to the fifth node; a load resistor connected between the second node and the ground node; a load capacitor in parallel with the load resistor and sharing the second node with the load resistor; the emitter of the first NPN bipolar isolation transistor being connected to the third node and the collector of the first NPN bipolar isolation transistor being connected to the first collector of the multiple collector PNP transistor; the emitter of the second NPN bipolar isolation transistor being connected to the fourth node and the collector of the second NPN bipolar transistor being connected to the second collector and the base of the multiple collector PNP transistor; characterized in that a feedback compensation capacitor is connected between the second node and the third node.