A printed circuit board comprising: an external layer that includes multiple integrated circuit installation regions (410A-410D) that are each configured to receive an IC (110A-110D); a first trace routing layer comprising a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region; a second trace routing layer comprising a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, wherein the first path crosses the second path at a point between the first IC installation region and the second IC installation region; a first via region comprising one or more first vias that extend from the first trace routing layer to the second trace routing layer, the first via region being within a first perimeter defined by a first portion of the first path, a first portion of the second path, the point at which the first path crosses the second path, and a portion of a perimeter of the first IC installation region; and a second via region comprising one or more second vias that extend from the first trace routing layer to the second trace routing layer, the second via region being within a second perimeter defined by a second portion of the first path, a second portion of the second path, the point at which the first path crosses the second path, and a portion of a perimeter of the second IC installation region, wherein: each first via electrically couples a respective third conductive trace on the first trace routing layer to a respective fourth conductive trace on the second trace routing layer, wherein the respective third conductive trace, the respective fourth conductive trace, and the first via provides a first conductive path between a third IC installation region and a fourth IC installation region; each second via electrically couples a respective fifth conductive trace on the first trace routing layer to a respective sixth conductive trace on the second trace routing layer, wherein the respective fifth conductive trace, the respective sixth conductive trace, and the second via provides a second conductive path between the third IC installation region and the fourth IC installation region. an external layer that includes multiple integrated circuit installation regions (410A-410D) that are each configured to receive an IC (110A-110D); a first trace routing layer comprising a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region; a second trace routing layer comprising a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, wherein the first path crosses the second path at a point between the first IC installation region and the second IC installation region; a first via region comprising one or more first vias that extend from the first trace routing layer to the second trace routing layer, the first via region being within a first perimeter defined by a first portion of the first path, a first portion of the second path, the point at which the first path crosses the second path, and a portion of a perimeter of the first IC installation region; and a second via region comprising one or more second vias that extend from the first trace routing layer to the second trace routing layer, the second via region being within a second perimeter defined by a second portion of the first path, a second portion of the second path, the point at which the first path crosses the second path, and a portion of a perimeter of the second IC installation region, wherein: each first via electrically couples a respective third conductive trace on the first trace routing layer to a respective fourth conductive trace on the second trace routing layer, wherein the respective third conductive trace, the respective fourth conductive trace, and the first via provides a first conductive path between a third IC installation region and a fourth IC installation region; each second via electrically couples a respective fifth conductive trace on the first trace routing layer to a respective sixth conductive trace on the second trace routing layer, wherein the respective fifth conductive trace, the respective sixth conductive trace, and the second via provides a second conductive path between the third IC installation region and the fourth IC installation region. each first via electrically couples a respective third conductive trace on the first trace routing layer to a respective fourth conductive trace on the second trace routing layer, wherein the respective third conductive trace, the respective fourth conductive trace, and the first via provides a first conductive path between a third IC installation region and a fourth IC installation region; each second via electrically couples a respective fifth conductive trace on the first trace routing layer to a respective sixth conductive trace on the second trace routing layer, wherein the respective fifth conductive trace, the respective sixth conductive trace, and the second via provides a second conductive path between the third IC installation region and the fourth IC installation region.