Arrangement for phase synchronisation of a plurality of devices, wherein one device is the main device (master) and the other devices are subordinate devices (slaves), having in each case a phase synchronisation unit for each device, which unit in each case comprises: a first controlled oscillator for generating a main reference signal, a first phase detector which to control the first oscillator compares the phase of a first comparison signal derived from the main reference signal with the phase of a second comparison signal derived from an auxiliary reference signal (REF_IN) when the device itself is the main device (master), and a second phase detector which to control the first oscillator compares the phase of a third comparison signal derived from the main reference signal with the phase of a reference signal (CASC_REF) which comes from the phase synchronisation unit of the main device (master) when the device itself is not the main device (master) but a subordinate device (slave), characterised in that each phase synchronisation unit also comprises: a second controlled oscillator for generating a clock pulse signal (AD_CLOCK), a third phase detector which to control the second oscillator compares the phase of a fourth comparison signal derived from the main reference signal with the phase of a fifth comparison signal derived from the clock pulse signal (AD_CLOCK) when the device itself is the main device (master), and a fourth phase detector which to control the second oscillator compares the phase of a sixth comparison signal derived from the clock pulse signal (AD_CLOCK) with the phase of a reference clock pulse signal (CASC_CLOCK) which is transmitted by the phase synchronisation unit of the main device (master) when the device itself is not the main device (master) but a subordinate device (slave). a first controlled oscillator for generating a main reference signal, a first phase detector which to control the first oscillator compares the phase of a first comparison signal derived from the main reference signal with the phase of a second comparison signal derived from an auxiliary reference signal (REF_IN) when the device itself is the main device (master), and a second phase detector which to control the first oscillator compares the phase of a third comparison signal derived from the main reference signal with the phase of a reference signal (CASC_REF) which comes from the phase synchronisation unit of the main device (master) when the device itself is not the main device (master) but a subordinate device (slave), characterised in that each phase synchronisation unit also comprises: a second controlled oscillator for generating a clock pulse signal (AD_CLOCK), a third phase detector which to control the second oscillator compares the phase of a fourth comparison signal derived from the main reference signal with the phase of a fifth comparison signal derived from the clock pulse signal (AD_CLOCK) when the device itself is the main device (master), and a fourth phase detector which to control the second oscillator compares the phase of a sixth comparison signal derived from the clock pulse signal (AD_CLOCK) with the phase of a reference clock pulse signal (CASC_CLOCK) which is transmitted by the phase synchronisation unit of the main device (master) when the device itself is not the main device (master) but a subordinate device (slave). a second controlled oscillator for generating a clock pulse signal (AD_CLOCK), a third phase detector which to control the second oscillator compares the phase of a fourth comparison signal derived from the main reference signal with the phase of a fifth comparison signal derived from the clock pulse signal (AD_CLOCK) when the device itself is the main device (master), and a fourth phase detector which to control the second oscillator compares the phase of a sixth comparison signal derived from the clock pulse signal (AD_CLOCK) with the phase of a reference clock pulse signal (CASC_CLOCK) which is transmitted by the phase synchronisation unit of the main device (master) when the device itself is not the main device (master) but a subordinate device (slave).