A circuit comprising: a first signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal; a second signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal, wherein the second terminal of the second signal transistor is coupled to the control terminal of the first signal transistor, and wherein the first terminal of the second signal transistor is coupled to the second terminal of the first signal transistor; a third signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal, wherein the second terminal of the third signal transistor is coupled to the first terminal of the second signal transistor; a fourth signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal, wherein the second terminal of the fourth signal transistor is coupled to the second terminal of the second signal transistor, and wherein the first terminal of the fourth signal transistor is coupled to the first terminal of the first signal transistor; a first buffer input; a first bias circuit that AC couples the first buffer input to the control terminal of the second signal transistor; a second bias circuit; a third bias circuit; and a buffer output that is coupled to the first terminal of the second signal transistor; characterized by: a second buffer input; wherein the second bias circuit is configured to AC couple the second buffer input to the control terminal of the third signal transistor; and wherein the third bias circuit is configured to AC couple the first buffer input to the control terminal of the fourth signal transistor. a first signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal; a second signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal, wherein the second terminal of the second signal transistor is coupled to the control terminal of the first signal transistor, and wherein the first terminal of the second signal transistor is coupled to the second terminal of the first signal transistor; a third signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal, wherein the second terminal of the third signal transistor is coupled to the first terminal of the second signal transistor; a fourth signal transistor having a source representing a first terminal, a gate representing a control terminal, and a drain representing a second terminal, wherein the second terminal of the fourth signal transistor is coupled to the second terminal of the second signal transistor, and wherein the first terminal of the fourth signal transistor is coupled to the first terminal of the first signal transistor; a first buffer input; a first bias circuit that AC couples the first buffer input to the control terminal of the second signal transistor; a second bias circuit; a third bias circuit; and a buffer output that is coupled to the first terminal of the second signal transistor; characterized by: a second buffer input; wherein the second bias circuit is configured to AC couple the second buffer input to the control terminal of the third signal transistor; and wherein the third bias circuit is configured to AC couple the first buffer input to the control terminal of the fourth signal transistor. a second buffer input; wherein the second bias circuit is configured to AC couple the second buffer input to the control terminal of the third signal transistor; and wherein the third bias circuit is configured to AC couple the first buffer input to the control terminal of the fourth signal transistor.