A multi-processor processing system, characterized by comprising: a voltage regulator and bypass circuit configured to receive a first supply voltage and generate a second supply voltage (VDDb), wherein the second supply voltage has a voltage value less than the first supply voltage; a first processor configured to receive and operate in accordance with a first clock signal having a first predetermined frequency and the first supply voltage; a second processor configured to receive and operate in accordance with either the first clock signal or a second clock signal having a second predetermined frequency different from the first predetermined frequency and receive and operate in accordance with the first supply voltage or the second supply voltage; a controller coupled to the voltage regulator and bypass circuit and configured to generate a bypass signal to be outputted to said voltage regulator and bypass circuit for selectively inputting the first supply voltage or the second supply voltage to the second processor; and wherein the first processor is further configured to receive and operate in accordance with the first clock signal and the first supply voltage during both a first mode and a second mode of operation; wherein said controller comprises a finite state machine (FSM); and if a LDD_MODE_SELECT signal input into said controller is high, then if a switch command SMP/ASMP_SELECT that indicates operation in the ASMP mode, is received at the controller, the controller, will output a low BYPASS signal and a high EN signal to said voltage regulator and bypass circuit, and based on these values for the EN and BYPASS signals, the FSM transitions to the ASMP mode state, wherein prior to entering said ASMP mode state 320, a Delay2 state is entered by the FSM which provides a predetermined amount of time for delay before the FSM outputs the low BYPASS signal and enter the ASMP mode state, wherein Delay2 may be any suitable time period range, depending on the physical operating characteristics of the type of voltage regulator utilized to generate the second voltage (VDDb), and if the switch command indicates operation in the SMP mode, the controller will output a high BYPASS signal and a high EN signal to said voltage regulator and bypass circuit and based on these values for the EN and BYPASS signals, the FSM transitions to the SMP mode state wherein, prior to entering the SMP mode state, a Delay1 state is entered which provides a predetermined amount of time for delay before the FSM outputs the high BYPASS signal and enters the SMP mode state wherein, the Delay1 may be any suitable time period range, e.g., sub-microseconds to tens of microseconds, depending on the physical operating characteristics of the type of voltage regulator utilized to generate the first supply voltage. a voltage regulator and bypass circuit configured to receive a first supply voltage and generate a second supply voltage (VDDb), wherein the second supply voltage has a voltage value less than the first supply voltage; a first processor configured to receive and operate in accordance with a first clock signal having a first predetermined frequency and the first supply voltage; a second processor configured to receive and operate in accordance with either the first clock signal or a second clock signal having a second predetermined frequency different from the first predetermined frequency and receive and operate in accordance with the first supply voltage or the second supply voltage; a controller coupled to the voltage regulator and bypass circuit and configured to generate a bypass signal to be outputted to said voltage regulator and bypass circuit for selectively inputting the first supply voltage or the second supply voltage to the second processor; and wherein the first processor is further configured to receive and operate in accordance with the first clock signal and the first supply voltage during both a first mode and a second mode of operation; wherein said controller comprises a finite state machine (FSM); and if a LDD_MODE_SELECT signal input into said controller is high, then if a switch command SMP/ASMP_SELECT that indicates operation in the ASMP mode, is received at the controller, the controller, will output a low BYPASS signal and a high EN signal to said voltage regulator and bypass circuit, and based on these values for the EN and BYPASS signals, the FSM transitions to the ASMP mode state, wherein prior to entering said ASMP mode state 320, a Delay2 state is entered by the FSM which provides a predetermined amount of time for delay before the FSM outputs the low BYPASS signal and enter the ASMP mode state, wherein Delay2 may be any suitable time period range, depending on the physical operating characteristics of the type of voltage regulator utilized to generate the second voltage (VDDb), and if the switch command indicates operation in the SMP mode, the controller will output a high BYPASS signal and a high EN signal to said voltage regulator and bypass circuit and based on these values for the EN and BYPASS signals, the FSM transitions to the SMP mode state wherein, prior to entering the SMP mode state, a Delay1 state is entered which provides a predetermined amount of time for delay before the FSM outputs the high BYPASS signal and enters the SMP mode state wherein, the Delay1 may be any suitable time period range, e.g., sub-microseconds to tens of microseconds, depending on the physical operating characteristics of the type of voltage regulator utilized to generate the first supply voltage.