A method of producing a quantum computer chip comprising a qubit chip and a device interposer chip, the method comprising: Bonding the qubit chip to a test interposer chip having a readout circuit, the qubit chip comprising a plurality of metallic pads and a plurality of metallic studs each formed on a different metallic pad, the test interposer chip comprising a plurality of metallic pads and a plurality of test solder bumps each formed on a different metallic pad, the number of test solder bumps in the plurality of test solder bumps being less than the number of metallic studs in the plurality of metallic studs, the bonding of the qubit chip to the test interposer chip comprising bonding a subset of the plurality of metallic studs to the plurality of test solder bumps; Cooling the bonded qubit chip and test interposer chip to an operating temperature of the qubit chip; thereafter performing, via the readout circuit, a frequency measurement on the qubit chip bonded to the test interposer chip for qubits on the qubit chip at the operating temperature of the qubit chip, the qubits being fixed frequency qubits each having one or more Josephson junctions; pulling the qubit chip apart from the test interposer chip after performing the frequency measurement; modifying a frequency of a subset of qubits after pulling the qubit chip apart from the test interposer chip; and bonding the qubit chip to the device interposer chip after modifying the frequency of the subset of qubits, the device interposer chip comprising a plurality of metallic pads and a plurality of device solder bumps each formed on a different metallic pad, the number of test solder bumps in the plurality of test solder bumps being less than the number of device solder bumps in the plurality of device solder bumps, the bonding of the qubit chip to the device interposer chip comprising bonding the plurality of metallic studs to the plurality of device solder bumps, the size of each device solder bump being larger than that of each test solder bump; wherein the device interposer chip is the test interposer chip reused and the method further comprises removing the test solder bumps from the test interposer chip after the pulling and forming the plurality of device solder bumps on the test interposer chip. Bonding the qubit chip to a test interposer chip having a readout circuit, the qubit chip comprising a plurality of metallic pads and a plurality of metallic studs each formed on a different metallic pad, the test interposer chip comprising a plurality of metallic pads and a plurality of test solder bumps each formed on a different metallic pad, the number of test solder bumps in the plurality of test solder bumps being less than the number of metallic studs in the plurality of metallic studs, the bonding of the qubit chip to the test interposer chip comprising bonding a subset of the plurality of metallic studs to the plurality of test solder bumps; Cooling the bonded qubit chip and test interposer chip to an operating temperature of the qubit chip; thereafter performing, via the readout circuit, a frequency measurement on the qubit chip bonded to the test interposer chip for qubits on the qubit chip at the operating temperature of the qubit chip, the qubits being fixed frequency qubits each having one or more Josephson junctions; pulling the qubit chip apart from the test interposer chip after performing the frequency measurement; modifying a frequency of a subset of qubits after pulling the qubit chip apart from the test interposer chip; and bonding the qubit chip to the device interposer chip after modifying the frequency of the subset of qubits, the device interposer chip comprising a plurality of metallic pads and a plurality of device solder bumps each formed on a different metallic pad, the number of test solder bumps in the plurality of test solder bumps being less than the number of device solder bumps in the plurality of device solder bumps, the bonding of the qubit chip to the device interposer chip comprising bonding the plurality of metallic studs to the plurality of device solder bumps, the size of each device solder bump being larger than that of each test solder bump; wherein the device interposer chip is the test interposer chip reused and the method further comprises removing the test solder bumps from the test interposer chip after the pulling and forming the plurality of device solder bumps on the test interposer chip.