A system, comprising: at least one memory (110, 326); and a processing device, operatively coupled with the at least one memory (110, 326), configured to: schedule, by a command scheduler of the system, a first write command on a command bus, wherein the command bus transmits commands from the system to a controller of a memory system, the command scheduler schedules commands on the command bus, the first write command requires use of one data bus at a first time period after scheduling the first write command, and the data bus is used to transfer first data associated with the first write command from the system to the memory system; schedule an address command immediately following the first write command, wherein the address command specifies an address for the first data; prior to the first time period, identify, by the command scheduler, a second write command according to a scheduling policy that favors scheduling of write commands over read commands, wherein the data bus is used to transfer second data associated with the second write command from the system to the memory system; determine, by the command scheduler, whether scheduling the second write command on the command bus immediately following the address command will cause a conflict in usage of the data bus for transferring the first data and the second data on the data bus; in response to determining that scheduling the second write command will cause the conflict in usage of the data bus, identify, by the command scheduler, a read command for which scheduling on the command bus will not cause the conflict in usage of the data bus; and schedule, by the command scheduler, the read command on the command bus immediately following the address command and prior to scheduling the second write command. at least one memory (110, 326); and a processing device, operatively coupled with the at least one memory (110, 326), configured to: schedule, by a command scheduler of the system, a first write command on a command bus, wherein the command bus transmits commands from the system to a controller of a memory system, the command scheduler schedules commands on the command bus, the first write command requires use of one data bus at a first time period after scheduling the first write command, and the data bus is used to transfer first data associated with the first write command from the system to the memory system; schedule an address command immediately following the first write command, wherein the address command specifies an address for the first data; prior to the first time period, identify, by the command scheduler, a second write command according to a scheduling policy that favors scheduling of write commands over read commands, wherein the data bus is used to transfer second data associated with the second write command from the system to the memory system; determine, by the command scheduler, whether scheduling the second write command on the command bus immediately following the address command will cause a conflict in usage of the data bus for transferring the first data and the second data on the data bus; in response to determining that scheduling the second write command will cause the conflict in usage of the data bus, identify, by the command scheduler, a read command for which scheduling on the command bus will not cause the conflict in usage of the data bus; and schedule, by the command scheduler, the read command on the command bus immediately following the address command and prior to scheduling the second write command. schedule, by a command scheduler of the system, a first write command on a command bus, wherein the command bus transmits commands from the system to a controller of a memory system, the command scheduler schedules commands on the command bus, the first write command requires use of one data bus at a first time period after scheduling the first write command, and the data bus is used to transfer first data associated with the first write command from the system to the memory system; schedule an address command immediately following the first write command, wherein the address command specifies an address for the first data; prior to the first time period, identify, by the command scheduler, a second write command according to a scheduling policy that favors scheduling of write commands over read commands, wherein the data bus is used to transfer second data associated with the second write command from the system to the memory system; determine, by the command scheduler, whether scheduling the second write command on the command bus immediately following the address command will cause a conflict in usage of the data bus for transferring the first data and the second data on the data bus; in response to determining that scheduling the second write command will cause the conflict in usage of the data bus, identify, by the command scheduler, a read command for which scheduling on the command bus will not cause the conflict in usage of the data bus; and schedule, by the command scheduler, the read command on the command bus immediately following the address command and prior to scheduling the second write command.