A wireless communication device (100, 200, 300, 500) configured to calibrate one transceiver chain that is transmitting a first output signal (Tx_A) while another transceiver chain is concurrently transmitting a second output signal (Tx_B), comprising: a first transceiver chain including a first transmit circuit and a first receive circuit coupled in parallel between a core logic (210, 530) and a first antenna, the first transceiver chain further including a loopback path configured to route the first output signal (Tx_A) as a loopback calibration signal (LB_A) from the first transmit circuit directly to the first receive circuit, wherein the first receive circuit further comprises an low noise amplifier, LNA, that amplifies the loopback calibration signal (LB_A), and provides a resulting signal (LB_A'), wherein the first receive circuit further comprises a summing node that subtracts a compensation signal (CMP_B) from the amplified loopback calibration signal (LB_A') to generate a first calibration signal (CAL_A), and wherein the first calibration signal (CAL_A) comprises a pre-distortion signal that pre-distorts signals provided by the core logic (210, 530) to the first transceiver chain to pre-compensate for non-linearities of a power amplifier within the first transmit circuit; a second transceiver chain including a second transmit circuit and a second receive circuit coupled in parallel between the core logic (210, 530) and a second antenna, wherein the second transceiver chain transmits the second output signal (Tx_B) via the second antenna while the first transceiver chain transmits the first output signal (Tx_A) via the first antenna; and an interference processor connected between the second transmit circuit and the first receive circuit, wherein the interference processor is configured to process the second output signal (Tx_B) comprising an output signal (OUT_B) of a power amplifier within the second transmit chain to generate the compensation signal (CMP_B) that eliminates, from the loopback calibration signal (LB_A), unwanted components of the second output signal (Tx_B) received by the first antenna. a first transceiver chain including a first transmit circuit and a first receive circuit coupled in parallel between a core logic (210, 530) and a first antenna, the first transceiver chain further including a loopback path configured to route the first output signal (Tx_A) as a loopback calibration signal (LB_A) from the first transmit circuit directly to the first receive circuit, wherein the first receive circuit further comprises an low noise amplifier, LNA, that amplifies the loopback calibration signal (LB_A), and provides a resulting signal (LB_A'), wherein the first receive circuit further comprises a summing node that subtracts a compensation signal (CMP_B) from the amplified loopback calibration signal (LB_A') to generate a first calibration signal (CAL_A), and wherein the first calibration signal (CAL_A) comprises a pre-distortion signal that pre-distorts signals provided by the core logic (210, 530) to the first transceiver chain to pre-compensate for non-linearities of a power amplifier within the first transmit circuit; a second transceiver chain including a second transmit circuit and a second receive circuit coupled in parallel between the core logic (210, 530) and a second antenna, wherein the second transceiver chain transmits the second output signal (Tx_B) via the second antenna while the first transceiver chain transmits the first output signal (Tx_A) via the first antenna; and an interference processor connected between the second transmit circuit and the first receive circuit, wherein the interference processor is configured to process the second output signal (Tx_B) comprising an output signal (OUT_B) of a power amplifier within the second transmit chain to generate the compensation signal (CMP_B) that eliminates, from the loopback calibration signal (LB_A), unwanted components of the second output signal (Tx_B) received by the first antenna.