A semiconductor device (200A, 200B), comprising: a first wafer (1; 302) having an array transistor (14, 214) formed therein; a second wafer (2; 304) having a capacitor structure (61, 216) formed therein; and a bonding interface (76, 303) formed between the first wafer and the second wafer that includes a plurality of bonding structures that are configured to couple the array transistor (14, 214) to the capacitor structure (61, 216) to form a memory cell, wherein the first wafer comprises a first substrate (10, 210) and the second wafer comprises a second substrate (60, 212), the first substrate (10, 210) having a first side (10a, 210a) and an opposing second side (10b, 210b), the second substrate (60, 212) having a first side (60a, 212a) and an opposing second side (60b, 212b), the array transistor (14, 214) being positioned in the first side (10a, 210a) of the first substrate (10, 210); the semiconductor device (200A, 200B) further comprising: a first dielectric stack (7, 248) formed over the array transistor (14, 214) on the first side (10a, 210a) of the first substrate (10, 210); a plurality of first contact structures (11a-11f, 220a-220f) formed in and extending through the first dielectric stack (7, 248), a first terminal contact (11a, 220a) of the first contact structures (11a-11f, 220a-220f) being coupled to a first doped region (24, 242) of the array transistor (14, 214); a second dielectric stack (8, 250) formed on the first side (60a, 212a) of the second substrate (60, 212) so that the capacitor structure (61, 216) is positioned in the second dielectric stack (8, 250); a plurality of second contact structures (68a-68e, 222a-222g) formed in and extending through the second dielectric stack (8, 250); wherein the capacitor structure (61; 216) is coupled to at least one of the second contact structures; wherein the first contact structures (11a-11f, 220a-220f) and the second contact structures (68a-68e, 222a-222g) are bonded to each other through the bonding structures; a third dielectric stack (9, 240) formed on the second side (60b, 212b) of the second substrate (60, 212); and a through silicon contact (73; 226) formed in the third dielectric stack (9, 240) and extending from the second side (60b, 212b) of the second substrate (60, 212) through the second substrate (60, 212) to connect to a second terminal contact of the second contact structures (68a-68e, 222a-222g). a first wafer (1; 302) having an array transistor (14, 214) formed therein; a second wafer (2; 304) having a capacitor structure (61, 216) formed therein; and a bonding interface (76, 303) formed between the first wafer and the second wafer that includes a plurality of bonding structures that are configured to couple the array transistor (14, 214) to the capacitor structure (61, 216) to form a memory cell, wherein the first wafer comprises a first substrate (10, 210) and the second wafer comprises a second substrate (60, 212), the first substrate (10, 210) having a first side (10a, 210a) and an opposing second side (10b, 210b), the second substrate (60, 212) having a first side (60a, 212a) and an opposing second side (60b, 212b), the array transistor (14, 214) being positioned in the first side (10a, 210a) of the first substrate (10, 210); the semiconductor device (200A, 200B) further comprising: a first dielectric stack (7, 248) formed over the array transistor (14, 214) on the first side (10a, 210a) of the first substrate (10, 210); a plurality of first contact structures (11a-11f, 220a-220f) formed in and extending through the first dielectric stack (7, 248), a first terminal contact (11a, 220a) of the first contact structures (11a-11f, 220a-220f) being coupled to a first doped region (24, 242) of the array transistor (14, 214); a second dielectric stack (8, 250) formed on the first side (60a, 212a) of the second substrate (60, 212) so that the capacitor structure (61, 216) is positioned in the second dielectric stack (8, 250); a plurality of second contact structures (68a-68e, 222a-222g) formed in and extending through the second dielectric stack (8, 250); wherein the capacitor structure (61; 216) is coupled to at least one of the second contact structures; wherein the first contact structures (11a-11f, 220a-220f) and the second contact structures (68a-68e, 222a-222g) are bonded to each other through the bonding structures; a third dielectric stack (9, 240) formed on the second side (60b, 212b) of the second substrate (60, 212); and a through silicon contact (73; 226) formed in the third dielectric stack (9, 240) and extending from the second side (60b, 212b) of the second substrate (60, 212) through the second substrate (60, 212) to connect to a second terminal contact of the second contact structures (68a-68e, 222a-222g).