A summing tracking quantizer within an analog-to-digital converter comprising: an additive combining circuit configured for summing multiple feed forward signals from cascaded integrator stages (11a, 116b, 116c) of the analog-to-digital converter, a scaled sampled analog cancellation signal, and a loop delay compensation feedback signal to form a quantization noise signal; a reference voltage generation circuit configured for selectively generating tracking reference voltages (207a, 207b, 207c, 207d) determined by a retained previous digital output code (235, 735) wherein at least one of the tracking reference voltages (207a, 207b, 207c and 207d) is the loop delay compensation feedback signal based on the retained previous digital output code (235, 735); a plurality of comparator circuits (215a, 215b, 215c, 215d, 715a, 715b, 715c and 715d) in communication with the additive combining circuit to receive the quantization noise signal and configured for creating a difference quantization code from the comparison of the selectively generated tracking reference voltages (207a, 207b, 207c, and 207d) the multiple feed forward signals, the scaled sampled analog cancellation signal, and the loop delay compensation feedback signal; a difference quantization summation circuit (225, 725) connected to receive the difference quantization code from the plurality of comparator circuits (215a, 215b, 215c, 215d, 715a, 715b, 715c and 715d) and configured for adding the difference quantization code with the retained previous digital output code (235, 735) to generate a present digital output code; and a delay compensation circuit configured for receiving the present digital output code from the difference quantization summation circuit and configured for generating the loop delay compensation feedback signal and transferring the loop delay compensation feedback signal to the additive combining circuit to compensate for loop delay. an additive combining circuit configured for summing multiple feed forward signals from cascaded integrator stages (11a, 116b, 116c) of the analog-to-digital converter, a scaled sampled analog cancellation signal, and a loop delay compensation feedback signal to form a quantization noise signal; a reference voltage generation circuit configured for selectively generating tracking reference voltages (207a, 207b, 207c, 207d) determined by a retained previous digital output code (235, 735) wherein at least one of the tracking reference voltages (207a, 207b, 207c and 207d) is the loop delay compensation feedback signal based on the retained previous digital output code (235, 735); a plurality of comparator circuits (215a, 215b, 215c, 215d, 715a, 715b, 715c and 715d) in communication with the additive combining circuit to receive the quantization noise signal and configured for creating a difference quantization code from the comparison of the selectively generated tracking reference voltages (207a, 207b, 207c, and 207d) the multiple feed forward signals, the scaled sampled analog cancellation signal, and the loop delay compensation feedback signal; a difference quantization summation circuit (225, 725) connected to receive the difference quantization code from the plurality of comparator circuits (215a, 215b, 215c, 215d, 715a, 715b, 715c and 715d) and configured for adding the difference quantization code with the retained previous digital output code (235, 735) to generate a present digital output code; and a delay compensation circuit configured for receiving the present digital output code from the difference quantization summation circuit and configured for generating the loop delay compensation feedback signal and transferring the loop delay compensation feedback signal to the additive combining circuit to compensate for loop delay.