An apparatus comprising: a plurality of arithmetic logic units (301, 302, 303) wherein each arithmetic logic unit (301, 302, 303) is arranged to carry out an operation on at least one operand, said operation determined by an operation code received by that arithmetic logic unit (301, 302, 303), wherein said operation codes (310, 320, 330) and said operands are received on a first clock cycle; and wherein: a first one of the of arithmetic logic units is configured to carry out a first operation defined by a first operation code on at least one operand to output a first result; a second one of the arithmetic logic units is configured to carry out a second operation defined by a second operation code on at least one operand to output a second result; and a third one of the arithmetic logic units is configured to carry out a third operation defined by a third operation code on at least one operand to output a third result, characterized in that the plurality of arithmetic logic units are selectable between a tree configuration and a cascade configuration, based upon an algorithm to be executed, wherein the third one of the arithmetic logic units receives the first and second results as operand inputs when the plurality of arithmetic logic units are in the tree configuration, and the third one of the arithmetic logic units receives the second result as an operand input and the second one of the arithmetic logic units receives the first result as an operand input when the plurality of arithmetic logic units are in the cascade configuration. a plurality of arithmetic logic units (301, 302, 303) wherein each arithmetic logic unit (301, 302, 303) is arranged to carry out an operation on at least one operand, said operation determined by an operation code received by that arithmetic logic unit (301, 302, 303), wherein said operation codes (310, 320, 330) and said operands are received on a first clock cycle; and wherein: a first one of the of arithmetic logic units is configured to carry out a first operation defined by a first operation code on at least one operand to output a first result; a second one of the arithmetic logic units is configured to carry out a second operation defined by a second operation code on at least one operand to output a second result; and a third one of the arithmetic logic units is configured to carry out a third operation defined by a third operation code on at least one operand to output a third result, a first one of the of arithmetic logic units is configured to carry out a first operation defined by a first operation code on at least one operand to output a first result; a second one of the arithmetic logic units is configured to carry out a second operation defined by a second operation code on at least one operand to output a second result; and a third one of the arithmetic logic units is configured to carry out a third operation defined by a third operation code on at least one operand to output a third result, characterized in that the plurality of arithmetic logic units are selectable between a tree configuration and a cascade configuration, based upon an algorithm to be executed, wherein the third one of the arithmetic logic units receives the first and second results as operand inputs when the plurality of arithmetic logic units are in the tree configuration, and the third one of the arithmetic logic units receives the second result as an operand input and the second one of the arithmetic logic units receives the first result as an operand input when the plurality of arithmetic logic units are in the cascade configuration.