An integrated circuit structure, comprising: a substrate; a first gate structure (308A; 308B; 308C; 308D; 308E) over the substrate, wherein the first gate structure (308A; 308B; 308C; 308D; 308E) comprises a gate cap dielectric layer on a top surface of a first gate electrode, the gate cap dielectric layer of the first gate structure being composed of any of the following or a combination including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitrides, carbon doped silicon oxides, amorphous silicon, zirconium oxide, hafnium oxide, lanthanum oxide; a second gate structure (308A; 308B; 308C; 308D; 308E) over the substrate, wherein the second gate structure (308A; 308B; 308C; 308D; 308E) comprises a gate cap dielectric layer on a top surface of a second gate electrode, the gate cap dielectric layer of the second gate structure having the same composition as the gate cap dielectric layer of the first gate structure; a trench contact structure over the substrate, wherein the trench contact structure is between the first gate structure (308A; 308B; 308C; 308D; 308E) and the second gate structure (308A; 308B; 308C; 308D; 308E), wherein the trench contact structure comprises a trench cap dielectric layer on a top surface of a trench contact, the trench cap dielectric layer having a different composition and having a different etch rate than the gate cap dielectric layer and being composed of any of the following or a combination including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitrides, carbon doped silicon oxides, amorphous silicon, zirconium oxide, hafnium oxide, lanthanum oxide; a gate contact via (342A; 342B) in an opening of the gate cap dielectric layer of the first gate structure (308A; 308B; 308C; 308D; 308E), the gate contact via (342A; 342B) on a portion of the first gate structure (308A; 308B; 308C; 308D; 308E), wherein the portion of the first gate structure (308A; 308B; 308C; 308D; 308E) is over the substrate, wherein the gate contact via (342A; 342B) is further on a portion of the trench cap dielectric layer of the trench contact structure and wherein the gate contact via comprises cobalt, a first dielectric spacer (320; 520) between the first gate structure (308A; 308B;308C; 308D; 308E) and the trench contact structure and having a top surface; and a second dielectric spacer between the second gate structure (308A; 308B;308C; 308D; 308E) and the trench contact structure and having a top surface, wherein the top surfaces of the gate cap dielectric layers, the trench cap dielectric layer and the first and second dielectric spacers are co-planar. a substrate; a first gate structure (308A; 308B; 308C; 308D; 308E) over the substrate, wherein the first gate structure (308A; 308B; 308C; 308D; 308E) comprises a gate cap dielectric layer on a top surface of a first gate electrode, the gate cap dielectric layer of the first gate structure being composed of any of the following or a combination including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitrides, carbon doped silicon oxides, amorphous silicon, zirconium oxide, hafnium oxide, lanthanum oxide; a second gate structure (308A; 308B; 308C; 308D; 308E) over the substrate, wherein the second gate structure (308A; 308B; 308C; 308D; 308E) comprises a gate cap dielectric layer on a top surface of a second gate electrode, the gate cap dielectric layer of the second gate structure having the same composition as the gate cap dielectric layer of the first gate structure; a trench contact structure over the substrate, wherein the trench contact structure is between the first gate structure (308A; 308B; 308C; 308D; 308E) and the second gate structure (308A; 308B; 308C; 308D; 308E), wherein the trench contact structure comprises a trench cap dielectric layer on a top surface of a trench contact, the trench cap dielectric layer having a different composition and having a different etch rate than the gate cap dielectric layer and being composed of any of the following or a combination including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitrides, carbon doped silicon oxides, amorphous silicon, zirconium oxide, hafnium oxide, lanthanum oxide; a gate contact via (342A; 342B) in an opening of the gate cap dielectric layer of the first gate structure (308A; 308B; 308C; 308D; 308E), the gate contact via (342A; 342B) on a portion of the first gate structure (308A; 308B; 308C; 308D; 308E), wherein the portion of the first gate structure (308A; 308B; 308C; 308D; 308E) is over the substrate, wherein the gate contact via (342A; 342B) is further on a portion of the trench cap dielectric layer of the trench contact structure and wherein the gate contact via comprises cobalt, a first dielectric spacer (320; 520) between the first gate structure (308A; 308B;308C; 308D; 308E) and the trench contact structure and having a top surface; and a second dielectric spacer between the second gate structure (308A; 308B;308C; 308D; 308E) and the trench contact structure and having a top surface,