An array substrate comprising a plurality of pixel units, with a pixel structure of each pixel unit comprising: a first electrode layer (21, 31) and a second electrode layer (22, 32) which overlap with each other, wherein an insulating layer (23, 33) is disposed between the second electrode layer (22, 32) and the first electrode layer (21, 31), and the second electrode layer (22, 32) in cooperation with the first electrode layer (21, 31) are configured to generate a fringe electric field, the second electrode layer (22, 32) comprises a plurality of second electrode groups (221, 321), each comprising a first common electrode (2211, 3211) and a second pixel electrode (2212, 3212), with a first gap (2213, 3213) disposed between the first common electrode (2211, 3211) and the second pixel electrode (2212, 3212), wherein the array substrate is suitable for applying the first common electrode (2211, 3211) with a constant voltage and the second pixel electrode (2212, 3212) with a first control voltage; and the first electrode layer (21, 31) comprises a plurality of first electrode groups (211, 311), and each first electrode group (211, 311) comprises a first pixel electrode group (2111, 3111) and a second common electrode group (2112, 3112), with a second gap (2113, 3113) disposed between the first pixel electrode group (2111, 3111) and the second common electrode group (2112, 3112); wherein each first pixel electrode group (2111, 3111) is composed of at least two sub-electrodes, and each second common electrode group (2112, 3112) is composed of at least two sub-electrodes, wherein the array substrate is suitable for applying to each of the first pixel electrode groups (2111, 3111) a second control voltage and to each of the second common electrode groups (2112, 3112) a constant voltage, characterized in that the outermost edges of the electrodes of each of the first pixel electrode groups (2111, 3111) and the outermost edges of the first common electrode (2211, 3211) of each of the second electrode groups are aligned in the vertical direction, and the outermost edges of the electrodes of each of the second common electrode groups (2112, 3112) and the outermost edges of the second pixel electrode (2212, 3212) of each of the second electrode groups are aligned in the vertical direction. a first electrode layer (21, 31) and a second electrode layer (22, 32) which overlap with each other, wherein an insulating layer (23, 33) is disposed between the second electrode layer (22, 32) and the first electrode layer (21, 31), and the second electrode layer (22, 32) in cooperation with the first electrode layer (21, 31) are configured to generate a fringe electric field, the second electrode layer (22, 32) comprises a plurality of second electrode groups (221, 321), each comprising a first common electrode (2211, 3211) and a second pixel electrode (2212, 3212), with a first gap (2213, 3213) disposed between the first common electrode (2211, 3211) and the second pixel electrode (2212, 3212), wherein the array substrate is suitable for applying the first common electrode (2211, 3211) with a constant voltage and the second pixel electrode (2212, 3212) with a first control voltage; and the first electrode layer (21, 31) comprises a plurality of first electrode groups (211, 311), and each first electrode group (211, 311) comprises a first pixel electrode group (2111, 3111) and a second common electrode group (2112, 3112), with a second gap (2113, 3113) disposed between the first pixel electrode group (2111, 3111) and the second common electrode group (2112, 3112); wherein each first pixel electrode group (2111, 3111) is composed of at least two sub-electrodes, and each second common electrode group (2112, 3112) is composed of at least two sub-electrodes, wherein the array substrate is suitable for applying to each of the first pixel electrode groups (2111, 3111) a second control voltage and to each of the second common electrode groups (2112, 3112) a constant voltage, characterized in that the outermost edges of the electrodes of each of the first pixel electrode groups (2111, 3111) and the outermost edges of the first common electrode (2211, 3211) of each of the second electrode groups are aligned in the vertical direction, and the outermost edges of the electrodes of each of the second common electrode groups (2112, 3112) and the outermost edges of the second pixel electrode (2212, 3212) of each of the second electrode groups are aligned in the vertical direction.