An apparatus comprising: a pseudo-random noise generator circuit (212, 224, 562) arranged to generate a pseudo-random noise; signal control circuitry (102, 564) configured and arranged to receive the pseudo-random noise and an input clock signal derived from an application clock signal and to provide a reference clock signal carrying pseudo-random phase noise; a phase-locked loop, PLL (104, 332, 568) including a phase detector being configured and arranged to, responsive to the reference clock signal, provide an output phase error signal that is indicative of a phase difference between the reference clock signal and a feedback signal generated by the PLL; and a correlation circuit (106, 1090, 1091) configured and arranged to self-test the PLL (104, 332, 568) by cross-correlating a signal corresponding to the output phase error signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of at least one of a phase margin limit and a previously calculated phase margin of the PLL (104, 332, 568), wherein the correlation circuit (106, 980, 1090, 1091) further includes a summing circuit and a low-pass filter circuit configured and arranged to derive a PLL impulse response from a difference between the cross-correlation result between the phase error signal and the pseudo-random noise and an auto-correlation of the pseudo-random noise, the summing circuit being configured to receive the cross-correlation result and the auto-correlation, subtract the auto-correlation result from the cross-correlation result and output the PLL impulse response filtered by the low-pass filter circuit. a pseudo-random noise generator circuit (212, 224, 562) arranged to generate a pseudo-random noise; signal control circuitry (102, 564) configured and arranged to receive the pseudo-random noise and an input clock signal derived from an application clock signal and to provide a reference clock signal carrying pseudo-random phase noise; a phase-locked loop, PLL (104, 332, 568) including a phase detector being configured and arranged to, responsive to the reference clock signal, provide an output phase error signal that is indicative of a phase difference between the reference clock signal and a feedback signal generated by the PLL; and a correlation circuit (106, 1090, 1091) configured and arranged to self-test the PLL (104, 332, 568) by cross-correlating a signal corresponding to the output phase error signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of at least one of a phase margin limit and a previously calculated phase margin of the PLL (104, 332, 568), wherein the correlation circuit (106, 980, 1090, 1091) further includes a summing circuit and a low-pass filter circuit configured and arranged to derive a PLL impulse response from a difference between the cross-correlation result between the phase error signal and the pseudo-random noise and an auto-correlation of the pseudo-random noise, the summing circuit being configured to receive the cross-correlation result and the auto-correlation, subtract the auto-correlation result from the cross-correlation result and output the PLL impulse response filtered by the low-pass filter circuit.