A flip-flop circuit (FF 10) for retaining input data, comprising: a first master latch circuit (LAT 11) for latching the input data; a second master latch circuit (LAT 12) for latching the input data; a first C-element circuit (CE 11) for receiving an inverted output of the first master latch circuit (LAT 11) and an inverted output of the second master latch circuit (LAT 12); a second C-element circuit (CE 12) for receiving a non-inverted output of the first master latch circuit (LAT 11) and a non-inverted output of the second master latch circuit (LAT 12); a first slave latch circuit (LAT 13) for latching an output of the first C-element circuit (CE 11); a second slave latch circuit (LAT 14) for latching an output of the second C-element circuit (CE 12); a third C-element circuit (CE 13) for receiving an inverted output of the first slave latch circuit (LAT 13) and an inverted output of the second slave latch circuit (LAT 14); a fourth C-element circuit (CE 14) for receiving a non-inverted output of the first slave latch circuit (LAT 13) and a non-inverted output of the second slave latch circuit (LAT 14); a first inverter circuit (INV 11); a second inverter circuit (INV 12) being interconnected to the first inverter circuit (INV 11); a third inverter circuit (INV 13); and a fourth inverter circuit (INV 14) being interconnected to the third inverter circuit (INV 13), an input terminal of the first inverter circuit (INV 11) and an output terminal of the second inverter circuit (INV 12) being connected to a connection point between an output terminal of the first C-element circuit (CE 11) and a data input terminal of the first slave latch circuit (LAT 13), an output terminal of the first inverter circuit (INV 11) and an input terminal of the second inverter circuit (INV 12) being connected to a connection point between an output terminal of the second C-element circuit (CE 12) and a data input terminal of the second slave latch circuit (LAT 14), an input terminal of the third inverter circuit (INV 13) and an output terminal of the fourth inverter circuit (INV 14) being connected to an output terminal of the third C-element circuit (CE 13), an output terminal of the third inverter circuit (INV 13) and an input terminal of the fourth inverter circuit (INV 14) being connected to an output terminal of the fourth C-element circuit (CE 14). a first master latch circuit (LAT 11) for latching the input data; a second master latch circuit (LAT 12) for latching the input data; a first C-element circuit (CE 11) for receiving an inverted output of the first master latch circuit (LAT 11) and an inverted output of the second master latch circuit (LAT 12); a second C-element circuit (CE 12) for receiving a non-inverted output of the first master latch circuit (LAT 11) and a non-inverted output of the second master latch circuit (LAT 12); a first slave latch circuit (LAT 13) for latching an output of the first C-element circuit (CE 11); a second slave latch circuit (LAT 14) for latching an output of the second C-element circuit (CE 12); a third C-element circuit (CE 13) for receiving an inverted output of the first slave latch circuit (LAT 13) and an inverted output of the second slave latch circuit (LAT 14); a fourth C-element circuit (CE 14) for receiving a non-inverted output of the first slave latch circuit (LAT 13) and a non-inverted output of the second slave latch circuit (LAT 14); a first inverter circuit (INV 11); a second inverter circuit (INV 12) being interconnected to the first inverter circuit (INV 11); a third inverter circuit (INV 13); and a fourth inverter circuit (INV 14) being interconnected to the third inverter circuit (INV 13), an input terminal of the first inverter circuit (INV 11) and an output terminal of the second inverter circuit (INV 12) being connected to a connection point between an output terminal of the first C-element circuit (CE 11) and a data input terminal of the first slave latch circuit (LAT 13), an output terminal of the first inverter circuit (INV 11) and an input terminal of the second inverter circuit (INV 12) being connected to a connection point between an output terminal of the second C-element circuit (CE 12) and a data input terminal of the second slave latch circuit (LAT 14), an input terminal of the third inverter circuit (INV 13) and an output terminal of the fourth inverter circuit (INV 14) being connected to an output terminal of the third C-element circuit (CE 13), an output terminal of the third inverter circuit (INV 13) and an input terminal of the fourth inverter circuit (INV 14) being connected to an output terminal of the fourth C-element circuit (CE 14).