A method for producing a semiconductor integrated circuit device comprising a memory circuit region and a peripheral circuit region, the memory circuit region including a memory cell (3a, 3b, 3c, 3d, 3e, 3f) in which a memory gate structure (4a, 4b), a first select gate structure (5a, 5b) and a second select gate structure (6a, 6b) are disposed between a source region (D1, D3) and a drain region, the memory gate structure being disposed between the first select gate structure and the second gate structure through a sidewall spacer, the first select gate structure including a first select gate electrode (G2a, G2b), the second select gate structure including a second select gate electrode (G3a, G3b), the peripheral circuit region including a logic gate structure (7a, 7b) of a peripheral circuit, the method comprising: a sidewall spacer formation step of forming the memory gate structure in the memory circuit region and then forming the sidewall spacer covering the memory gate structure, the memory gate structure including a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode (G1a, G1b) stacked in this order; a conductive layer formation step of stacking a gate insulating film (25a, 25b) and a conductive layer in this order in the memory circuit region formed with the memory gate structure and in the peripheral circuit region; a conductive layer patterning step of etching back the conductive layer in the memory circuit region while leaving intact the conductive layer covering an entire surface of the peripheral circuit region, so as to form a sidewall-shaped surrounding conductive layer (Ga, Gb) around the memory gate electrode and along the sidewall spacer; and a gate electrode formation step of patterning the conductive layer in the peripheral circuit region by using a resist (Rr1a, Rr1b) patterned by using a photomask, the resist (Rr1a) covering portions of the peripheral circuit region where the logic gate structures (7a, 7b) are to be formed later, and the resist (Rr1b) covering an entire surface of the memory circuit region but including openings (H1, H2, H3, H4) in accordance with select gate electrode cutout portions, exposing a part of the sidewall shaped surrounding conductive layer, so as to form a logic gate electrode (G5, G6) of the logic gate structure on the gate insulating film, and removing at least a part of the sidewall shaped surrounding conductive layer corresponding to the select gate electrode cutout portions in the memory circuit region by using the resist, so as to divide the sidewall shaped surrounding conductive layer into the first select gate electrode and the second select gate electrode, the second select gate electrode being electrically separated from the first select gate electrode. a sidewall spacer formation step of forming the memory gate structure in the memory circuit region and then forming the sidewall spacer covering the memory gate structure, the memory gate structure including a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode (G1a, G1b) stacked in this order; a conductive layer formation step of stacking a gate insulating film (25a, 25b) and a conductive layer in this order in the memory circuit region formed with the memory gate structure and in the peripheral circuit region; a conductive layer patterning step of etching back the conductive layer in the memory circuit region while leaving intact the conductive layer covering an entire surface of the peripheral circuit region, so as to form a sidewall-shaped surrounding conductive layer (Ga, Gb) around the memory gate electrode and along the sidewall spacer; and a gate electrode formation step of patterning the conductive layer in the peripheral circuit region by using a resist (Rr1a, Rr1b) patterned by using a photomask, the resist (Rr1a) covering portions of the peripheral circuit region where the logic gate structures (7a, 7b) are to be formed later, and the resist (Rr1b) covering an entire surface of the memory circuit region but including openings (H1, H2, H3, H4) in accordance with select gate electrode cutout portions, exposing a part of the sidewall shaped surrounding conductive layer, so as to form a logic gate electrode (G5, G6) of the logic gate structure on the gate insulating film, and removing at least a part of the sidewall shaped surrounding conductive layer corresponding to the select gate electrode cutout portions in the memory circuit region by using the resist, so as to divide the sidewall shaped surrounding conductive layer into the first select gate electrode and the second select gate electrode, the second select gate electrode being electrically separated from the first select gate electrode.