A memory cell (200, 400A-400C) comprising: a programming selection transistor (210, 210A-210C, 410A-410C) having a first terminal, a second terminal configured to receive a bit line program signal (BLP, BLP1, BLP2), and a control terminal configured to receive a word line program signal (WLP, WLP1, WLP2); a following gate transistor (220, 220A-220C, 420A-420C) having a first terminal, a second terminal coupled to the first terminal of the programming selection transistor (210, 210A-210C, 410A-410C), and a control terminal configured to receive a following control signal (FL, FL1, FL2); an antifuse element (230, 230A-230C, 430A-430C) having a first terminal configured to receive an antifuse control signal (AF, AF1, AF2), and a second terminal coupled to the first terminal of the following gate transistor (220, 220A-220C, 420A-420C); and a reading circuit (240, 440A-440C) coupled to the second terminal of the following gate transistor (220, 220A-220C, 420A-420C) and configured to form a read current according to a bit line read signal (BLR, BLR1, BLR2) and a selection signal (SL, SL1, SL2) during a reading operation of the memory cell (200, 400A-400C), the reading circuit (240, 440A-440C) comprising a reading transistor (242, 442A-442C) having a first terminal configured to receive the bit line read signal (BLR, BLR1, BLR2), a second terminal configured to receive the selection signal (SL, SL1, SL2), and a control terminal coupled to the second terminal of the following gate transistor (220, 220A-220C, 420A-420C); wherein during the reading operation of the memory cell (200, 400A-400C), the bit line program signal (BLP, BLP1, BLP2) is at a first voltage, the word line program signal (WLP, WLP1, WLP2) changes from a second voltage to the first voltage, the following control signal (FL, FL1, FL2) is at the second voltage, the antifuse control signal (AFL, AFL1, AFL2) is at the second voltage, the bit line read signal (BLR, BLR1, BLR2) is at the second voltage, the selection signal (SL, SL1, SL2) is at the first voltage, and the second voltage is higher than the first voltage; and the antifuse element (230, 230A-230C, 430A-430C) is a varactor formed by a metal oxide semiconductor transistor having a source/drain extension area formed between a source of the metal oxide semiconductor transistor and a drain of metal oxide semiconductor transistor for shorting the source and the drain of the metal oxide semiconductor transistor. a programming selection transistor (210, 210A-210C, 410A-410C) having a first terminal, a second terminal configured to receive a bit line program signal (BLP, BLP1, BLP2), and a control terminal configured to receive a word line program signal (WLP, WLP1, WLP2); a following gate transistor (220, 220A-220C, 420A-420C) having a first terminal, a second terminal coupled to the first terminal of the programming selection transistor (210, 210A-210C, 410A-410C), and a control terminal configured to receive a following control signal (FL, FL1, FL2); an antifuse element (230, 230A-230C, 430A-430C) having a first terminal configured to receive an antifuse control signal (AF, AF1, AF2), and a second terminal coupled to the first terminal of the following gate transistor (220, 220A-220C, 420A-420C); and a reading circuit (240, 440A-440C) coupled to the second terminal of the following gate transistor (220, 220A-220C, 420A-420C) and configured to form a read current according to a bit line read signal (BLR, BLR1, BLR2) and a selection signal (SL, SL1, SL2) during a reading operation of the memory cell (200, 400A-400C), the reading circuit (240, 440A-440C) comprising a reading transistor (242, 442A-442C) having a first terminal configured to receive the bit line read signal (BLR, BLR1, BLR2), a second terminal configured to receive the selection signal (SL, SL1, SL2), and a control terminal coupled to the second terminal of the following gate transistor (220, 220A-220C, 420A-420C); wherein during the reading operation of the memory cell (200, 400A-400C), the bit line program signal (BLP, BLP1, BLP2) is at a first voltage, the word line program signal (WLP, WLP1, WLP2) changes from a second voltage to the first voltage, the following control signal (FL, FL1, FL2) is at the second voltage, the antifuse control signal (AFL, AFL1, AFL2) is at the second voltage, the bit line read signal (BLR, BLR1, BLR2) is at the second voltage, the selection signal (SL, SL1, SL2) is at the first voltage, and the second voltage is higher than the first voltage; and the antifuse element (230, 230A-230C, 430A-430C) is a varactor formed by a metal oxide semiconductor transistor having a source/drain extension area formed between a source of the metal oxide semiconductor transistor and a drain of metal oxide semiconductor transistor for shorting the source and the drain of the metal oxide semiconductor transistor.