A circuit arrangement for detecting unwanted signals on a clock signal (fosc), the circuit arrangement comprising an input for receiving the clock signal (fosc), the circuit arrangement being characterised by: a locked loop circuit configured to apply frequency multiplication, the loop circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal (fosc) and an output for providing a loop output signal (fpll), a frequency of the loop output signal (fpll) being a multiple of a frequency of the clock signal (fosc), a detector coupled to the output of the loop circuit and to the input of the circuit arrangement, the detector being arranged to: a) identify correct transitions in the clock signal, using the loop output signal (fpll); and b) remove incorrect transitions, due to unwanted signals from the clock signal; so as to provide a filtered clock signal (fout) at an output of the circuit arrangement, wherein the filtered clock signal (fout) at the output of the circuit arrangement corresponds to: c) the clock signal (fosc), when there are no unwanted signals on the clock signal (fosc); and d) the clock signal (fosc) with the incorrect transitions due to unwanted signals removed, when there are unwanted signals on the clock signal (fosc), and wherein the loop circuit and the detector of the circuit arrangement are configured to act as an adaptive narrow bandwidth filter, to provide a filtered clock signal for use as a time base for a processing unit of a system. a locked loop circuit configured to apply frequency multiplication, the loop circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal (fosc) and an output for providing a loop output signal (fpll), a frequency of the loop output signal (fpll) being a multiple of a frequency of the clock signal (fosc), a detector coupled to the output of the loop circuit and to the input of the circuit arrangement, the detector being arranged to: a) identify correct transitions in the clock signal, using the loop output signal (fpll); and b) remove incorrect transitions, due to unwanted signals from the clock signal; so as to provide a filtered clock signal (fout) at an output of the circuit arrangement, a) identify correct transitions in the clock signal, using the loop output signal (fpll); and b) remove incorrect transitions, due to unwanted signals from the clock signal; wherein the filtered clock signal (fout) at the output of the circuit arrangement corresponds to: c) the clock signal (fosc), when there are no unwanted signals on the clock signal (fosc); and d) the clock signal (fosc) with the incorrect transitions due to unwanted signals removed, when there are unwanted signals on the clock signal (fosc), and wherein the loop circuit and the detector of the circuit arrangement are configured to act as an adaptive narrow bandwidth filter, to provide a filtered clock signal for use as a time base for a processing unit of a system. c) the clock signal (fosc), when there are no unwanted signals on the clock signal (fosc); and d) the clock signal (fosc) with the incorrect transitions due to unwanted signals removed, when there are unwanted signals on the clock signal (fosc), and