A method of manufacturing a memory cell, comprising: providing a substrate including a channel region situated between a drain region and a source region; disposing a first dielectric layer over the channel region; disposing a floating gate over the first dielectric layer to capacitively couple the floating gate to the channel region through the first dielectric layer, wherein disposing the floating gate comprises disposing a polysilicon layer on the first dielectric layer and connecting a metal layer to the polysilicon layer; disposing a dielectric nitride layer on the floating gate, wherein disposing the dielectric nitride layer comprises disposing the dielectric nitride layer on the metal layer and between the metal layer; disposing a second dielectric layer on the dielectric nitride layer; and disposing a control gate over the second dielectric layer to capacitively couple the control gate to the floating gate through the second dielectric layer and the dielectric nitride layer, characterized in that the second dielectric layer is obtained from tetraethylorthosilicate, TEOS, and disposing the dielectric nitride layer comprises disposing the dielectric nitride layer on the metal layer and between the metal layer and the second dielectric layer, and further characterized by disposing, between the polysilicon layer (406, 724) and the metal layer (410, 736), a third dielectric layer (408, 726) situated between the polysilicon layer (406, 724) and the metal layer (410, 736), wherein the third dielectric layer (408, 726) includes an un-doped silicon glass, USG, layer (436, 728) and a boron phosphor silicon glass, BPSG, layer (438, 730) disposed on the USG layer. providing a substrate including a channel region situated between a drain region and a source region; disposing a first dielectric layer over the channel region; disposing a floating gate over the first dielectric layer to capacitively couple the floating gate to the channel region through the first dielectric layer, wherein disposing the floating gate comprises disposing a polysilicon layer on the first dielectric layer and connecting a metal layer to the polysilicon layer; disposing a dielectric nitride layer on the floating gate, wherein disposing the dielectric nitride layer comprises disposing the dielectric nitride layer on the metal layer and between the metal layer; disposing a second dielectric layer on the dielectric nitride layer; and disposing a control gate over the second dielectric layer to capacitively couple the control gate to the floating gate through the second dielectric layer and the dielectric nitride layer, characterized in that the second dielectric layer is obtained from tetraethylorthosilicate, TEOS, and disposing the dielectric nitride layer comprises disposing the dielectric nitride layer on the metal layer and between the metal layer and the second dielectric layer, and further characterized by disposing, between the polysilicon layer (406, 724) and the metal layer (410, 736), a third dielectric layer (408, 726) situated between the polysilicon layer (406, 724) and the metal layer (410, 736), wherein the third dielectric layer (408, 726) includes an un-doped silicon glass, USG, layer (436, 728) and a boron phosphor silicon glass, BPSG, layer (438, 730) disposed on the USG layer.