A bistable circuit having a first state and a second state, the bistable circuit comprising: a first switching element having a source electrode supplied with a first clock signal, and a drain electrode connected to an output-node for outputting a state signal indicating one of the first state and the second state, a second switching element having a source electrode connected to a first-node (netA) connected to a gate electrode of the first switching element, and a drain electrode supplied with a predetermined low potential, a fifth switching element having a gate electrode and a drain electrode each supplied with a predetermined set signal, and a source electrode connected to the first-node (netA), a sixth switching element having a gate electrode connected to the first-node (netA), a source electrode connected to a second-node (netB), and a drain electrode supplied with a predetermined low potential, a seventh switching element having a gate electrode supplied with a predetermined reset signal, a source electrode connected to the first-node (netA), and a drain electrode supplied with a predetermined low potential, a ninth switching element having a gate electrode supplied with a second clock signal, a source electrode connected to the output-node, and a drain electrode supplied with a predetermined low potential, and a capacitor (Cap) being connected between the first node (netA) and the output node, characterized in that the bistable circuit further comprises: a capacitor, having one end connected to the second-node (netB), and the other end supplied with a third clock signal, or a third switching element having a gate electrode and a source electrode each supplied with the third clock signal, and a drain electrode connected to the second-node (netB) connected to a gate electrode of the second switching element, a fourth switching element having a gate electrode supplied with a fourth clock signal, a source electrode connected to the second-node (netB), and a drain electrode supplied with a predetermined low potential, an eighth switching element having a gate electrode supplied with the reset signal, a source electrode connected to the output-node, and a drain electrode supplied with a predetermined low potential, wherein the bistable circuit is adapted to operate based on four-phase clock signals including the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, the four-phase clock signals each repeating a potential at a High level and a potential at a Low level cyclically. a first switching element having a source electrode supplied with a first clock signal, and a drain electrode connected to an output-node for outputting a state signal indicating one of the first state and the second state, a second switching element having a source electrode connected to a first-node (netA) connected to a gate electrode of the first switching element, and a drain electrode supplied with a predetermined low potential, a fifth switching element having a gate electrode and a drain electrode each supplied with a predetermined set signal, and a source electrode connected to the first-node (netA), a sixth switching element having a gate electrode connected to the first-node (netA), a source electrode connected to a second-node (netB), and a drain electrode supplied with a predetermined low potential, a seventh switching element having a gate electrode supplied with a predetermined reset signal, a source electrode connected to the first-node (netA), and a drain electrode supplied with a predetermined low potential, a ninth switching element having a gate electrode supplied with a second clock signal, a source electrode connected to the output-node, and a drain electrode supplied with a predetermined low potential, and a capacitor (Cap) being connected between the first node (netA) and the output node, a capacitor, having one end connected to the second-node (netB), and the other end supplied with a third clock signal, or a third switching element having a gate electrode and a source electrode each supplied with the third clock signal, and a drain electrode connected to the second-node (netB) connected to a gate electrode of the second switching element, a fourth switching element having a gate electrode supplied with a fourth clock signal, a source electrode connected to the second-node (netB), and a drain electrode supplied with a predetermined low potential, an eighth switching element having a gate electrode supplied with the reset signal, a source electrode connected to the output-node, and a drain electrode supplied with a predetermined low potential, wherein the bistable circuit is adapted to operate based on four-phase clock signals including the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, the four-phase clock signals each repeating a potential at a High level and a potential at a Low level cyclically.