A differential sampling circuit, comprising: a pair of input stages (2,3) comprising a first and a second input stage, each having a sampling switch (14,15) coupled to a differential input signal and a sampling capacitor (12,13) having an input coupled in series with the sampling switch and an output; a pass-through network (120,220) shunting the input stages between the outputs of the sampling capacitors, the pass-through network comprising a plurality of field effect transistors (121,122,123,221,222,223) operating in a linear region; and a cancellation network (140,240) coupled in parallel with the pass-through network, the cancellation network comprising a plurality of field effect transistors (142,143,242,243,244,245) operating in a saturation region, and wherein the pass-through network comprises: a first current source (131,133,231,233) coupled to a first voltage source; a first field effect transistor (121,123,231,233) having a drain coupled to the first current source and a source coupled to the output of the capacitor from the first input stage; a second current source (131,133,231,233) coupled to the first voltage source; a second field effect transistor (121,123,221,223) having a drain coupled to the second current source and a source coupled to the output of the capacitor from the the second input stage; and a third field effect transistor (122,222) coupled between the outputs of the capacitors from both input stages; wherein the cancellation network comprises: a fourth field effect transistor (142, 143, 242, 243) having a gate coupled to the output of the capacitor from the first input stage, a source coupled to ground, and a drain; a fifth field effect transistor (142, 143, 242, 243) having a gate coupled to the output of the capacitor from the second the input stage, a source coupled to ground, and a drain; and wherein each of the fourth and fifth field effect transistors are formed to have the same channel width and length as the third field effect transistor. a pair of input stages (2,3) comprising a first and a second input stage, each having a sampling switch (14,15) coupled to a differential input signal and a sampling capacitor (12,13) having an input coupled in series with the sampling switch and an output; a pass-through network (120,220) shunting the input stages between the outputs of the sampling capacitors, the pass-through network comprising a plurality of field effect transistors (121,122,123,221,222,223) operating in a linear region; and a cancellation network (140,240) coupled in parallel with the pass-through network, the cancellation network comprising a plurality of field effect transistors (142,143,242,243,244,245) operating in a saturation region, and wherein the pass-through network comprises: a first current source (131,133,231,233) coupled to a first voltage source; a first field effect transistor (121,123,231,233) having a drain coupled to the first current source and a source coupled to the output of the capacitor from the first input stage; a second current source (131,133,231,233) coupled to the first voltage source; a second field effect transistor (121,123,221,223) having a drain coupled to the second current source and a source coupled to the output of the capacitor from the the second input stage; and a third field effect transistor (122,222) coupled between the outputs of the capacitors from both input stages; wherein the cancellation network comprises: a fourth field effect transistor (142, 143, 242, 243) having a gate coupled to the output of the capacitor from the first input stage, a source coupled to ground, and a drain; a fifth field effect transistor (142, 143, 242, 243) having a gate coupled to the output of the capacitor from the second the input stage, a source coupled to ground, and a drain; and wherein each of the fourth and fifth field effect transistors are formed to have the same channel width and length as the third field effect transistor. a first current source (131,133,231,233) coupled to a first voltage source; a first field effect transistor (121,123,231,233) having a drain coupled to the first current source and a source coupled to the output of the capacitor from the first input stage; a second current source (131,133,231,233) coupled to the first voltage source; a second field effect transistor (121,123,221,223) having a drain coupled to the second current source and a source coupled to the output of the capacitor from the the second input stage; and a third field effect transistor (122,222) coupled between the outputs of the capacitors from both input stages; a fourth field effect transistor (142, 143, 242, 243) having a gate coupled to the output of the capacitor from the first input stage, a source coupled to ground, and a drain; a fifth field effect transistor (142, 143, 242, 243) having a gate coupled to the output of the capacitor from the second the input stage, a source coupled to ground, and a drain; and wherein each of the fourth and fifth field effect transistors are formed to have the same channel width and length as the third field effect transistor.