A processor apparatus having a plurality of cores, the processor further comprising: a first circuit configured to receive one or more requests (206-1, 206-2) from the plurality of cores, each of the one or more requests being to enter one of a plurality of power-down modes from a full-power operation, wherein each power-down mode of the plurality of power-down modes has a priority, the power-down mode having the longest entry time from a full-power operation having the lowest priority; assign a priority to each of the plurality of cores based on the priority of the power-down mode the core has requested to enter, wherein the cores requesting to enter the power-down modes of highest priorities are highest priority cores; compare the inrush current caused by entering the power-down mode for each request against an inrush current budget; and grant the maximum number of requests from the highest priority cores of the plurality of cores without the sum of the inrush currents exceeding the inrush current budget, and utilising a remainder of the inrush current budget by selecting cores of lower priorities requiring inrush currents within the remaining inrush current budget; and a second circuit configured to effect entering the respective requested power-down mode in each of the cores having the respective requested power-down mode in each of the cores having the respective request granted and further configured to effect entering the respective requested power-down mode in each of the selected cores of lower priority. a first circuit configured to receive one or more requests (206-1, 206-2) from the plurality of cores, each of the one or more requests being to enter one of a plurality of power-down modes from a full-power operation, wherein each power-down mode of the plurality of power-down modes has a priority, the power-down mode having the longest entry time from a full-power operation having the lowest priority; assign a priority to each of the plurality of cores based on the priority of the power-down mode the core has requested to enter, wherein the cores requesting to enter the power-down modes of highest priorities are highest priority cores; compare the inrush current caused by entering the power-down mode for each request against an inrush current budget; and grant the maximum number of requests from the highest priority cores of the plurality of cores without the sum of the inrush currents exceeding the inrush current budget, and utilising a remainder of the inrush current budget by selecting cores of lower priorities requiring inrush currents within the remaining inrush current budget; and receive one or more requests (206-1, 206-2) from the plurality of cores, each of the one or more requests being to enter one of a plurality of power-down modes from a full-power operation, wherein each power-down mode of the plurality of power-down modes has a priority, the power-down mode having the longest entry time from a full-power operation having the lowest priority; assign a priority to each of the plurality of cores based on the priority of the power-down mode the core has requested to enter, wherein the cores requesting to enter the power-down modes of highest priorities are highest priority cores; compare the inrush current caused by entering the power-down mode for each request against an inrush current budget; and grant the maximum number of requests from the highest priority cores of the plurality of cores without the sum of the inrush currents exceeding the inrush current budget, and utilising a remainder of the inrush current budget by selecting cores of lower priorities requiring inrush currents within the remaining inrush current budget; and a second circuit configured to effect entering the respective requested power-down mode in each of the cores having the respective requested power-down mode in each of the cores having the respective request granted and further configured to effect entering the respective requested power-down mode in each of the selected cores of lower priority.