A synchronous memory device to sequentially receive commands over an external request link from a memory controller, the sequential-received commands including respective row activate commands and column access commands, the synchronous memory device comprising: a first and second bank group (Q0, Q1), each comprising at least two storage arrays organized in plural banks (B0-A, B2-A; B1-A; B3-A), wherein storage arrays within each bank group (Q0, Q1) share a common row decoder (113 0, 113 1) and a common column decoder (103 0, 103 1), respectively, wherein said common column decoder (103 0, 103 1) associated with the first bank group and said column decoder associated with the second bank group are concurrently operable, and a request interface to sequentially-receive the commands from the external request link, the request interface having row control circuitry (301, 305, 307, 113) to activate two rows following two row activate commands (Ry, Rz) sequentially-received from the external request link and addressed to respective storage arrays (B0-A, B1-A) in different ones of the bank groups (Q0, Q1) within a shorter interval (t RRp) than a minimum time interval (t RR) in which the row control circuitry (301, 305B, 307A) can activate two rows following two row activate commands (Ry, Rz) sequentially-received from the external request link and addressed to respective storage arrays (BOA; B1-A) in a same one of the bank (Q0; Q1) groups, wherein as a result of the two row activate commands, respective rows in each of the addressed storage arrays are concurrently open after being latched into respective page buffers, the request interface having column control circuitry (301, 309, 311, 103) to access two columns following two column access commands (Ca, Ce) sequentially-received from the request link and directed to respective, active rows (Ry, Rz) in respective storage arrays (B0-A; B1-A) in different ones of the bank groups (Q0, Q1) within a shorter interval (t CCp) than a minimum time interval (t CC) the column control circuitry can access two columns following two column access commands (Ca, Cb; Ce, Cf) directed to one or more active rows (Rz; Ry) in a same one of the bank groups (Q0; Q1), wherein as a result of the two column access commands, respective data is transferred via a common set of external data connections. a first and second bank group (Q0, Q1), each comprising at least two storage arrays organized in plural banks (B0-A, B2-A; B1-A; B3-A), wherein storage arrays within each bank group (Q0, Q1) share a common row decoder (113 0, 113 1) and a common column decoder (103 0, 103 1), respectively, wherein said common column decoder (103 0, 103 1) associated with the first bank group and said column decoder associated with the second bank group are concurrently operable, and a request interface to sequentially-receive the commands from the external request link, the request interface having row control circuitry (301, 305, 307, 113) to activate two rows following two row activate commands (Ry, Rz) sequentially-received from the external request link and addressed to respective storage arrays (B0-A, B1-A) in different ones of the bank groups (Q0, Q1) within a shorter interval (t RRp) than a minimum time interval (t RR) in which the row control circuitry (301, 305B, 307A) can activate two rows following two row activate commands (Ry, Rz) sequentially-received from the external request link and addressed to respective storage arrays (BOA; B1-A) in a same one of the bank (Q0; Q1) groups, wherein as a result of the two row activate commands, respective rows in each of the addressed storage arrays are concurrently open after being latched into respective page buffers, the request interface having column control circuitry (301, 309, 311, 103) to access two columns following two column access commands (Ca, Ce) sequentially-received from the request link and directed to respective, active rows (Ry, Rz) in respective storage arrays (B0-A; B1-A) in different ones of the bank groups (Q0, Q1) within a shorter interval (t CCp) than a minimum time interval (t CC) the column control circuitry can access two columns following two column access commands (Ca, Cb; Ce, Cf) directed to one or more active rows (Rz; Ry) in a same one of the bank groups (Q0; Q1), wherein as a result of the two column access commands, respective data is transferred via a common set of external data connections.