Transmission/reception device (12; 120; 1200) for a bus system, having a reception comparator for receiving a signal that is transmitted by a bus of the bus system, which bus system exhibits at least intermittently ensured exclusive collision-free access by a subscriber station (10, 20, 30) to the bus of the bus system, and an oscillation reduction unit (15; 150), the input of which is connected in parallel with the input of the reception comparator, wherein the oscillation reduction unit (15; 150) is configured to respond to detection of a change of state of the received signal from a dominant bus state to a recessive bus state by connecting at least one bus wire (41; 42) of the bus to a bus bias voltage potential, wherein the oscillation reduction unit (15; 150) comprises: a detection block (151; 151, 152) that is configured to detect a change of state of the received signal from the dominant bus state to the recessive bus state; transistors (155, 156; 159, 160) that are connected up in such a way as to respond to detection of a change of state of the received signal from the dominant bus state to the recessive bus state by connecting the at least one bus wire (41; 42) of the bus to a bus bias voltage unit; a phase angle detection block for detecting the temporal position of the signals on the bus wires (41, 42) of the bus in relation to one another; and at least one RS timing block (153; 153, 154) that is respectively configured to control the signal on a bus wire (41; 42) on the basis of the detection result of the phase angle detection block in order to adjust the phase angle of the signal on the bus wire (41; 42), characterized in that the RS timing blocks (153; 153, 154) are configured in such a way that the time of actuation of the transistors (155, 156; 159, 160) is adjustable in fractions of the bit time. a reception comparator for receiving a signal that is transmitted by a bus of the bus system, which bus system exhibits at least intermittently ensured exclusive collision-free access by a subscriber station (10, 20, 30) to the bus of the bus system, and an oscillation reduction unit (15; 150), the input of which is connected in parallel with the input of the reception comparator, wherein the oscillation reduction unit (15; 150) is configured to respond to detection of a change of state of the received signal from a dominant bus state to a recessive bus state by connecting at least one bus wire (41; 42) of the bus to a bus bias voltage potential, wherein the oscillation reduction unit (15; 150) comprises: a detection block (151; 151, 152) that is configured to detect a change of state of the received signal from the dominant bus state to the recessive bus state; transistors (155, 156; 159, 160) that are connected up in such a way as to respond to detection of a change of state of the received signal from the dominant bus state to the recessive bus state by connecting the at least one bus wire (41; 42) of the bus to a bus bias voltage unit; a phase angle detection block for detecting the temporal position of the signals on the bus wires (41, 42) of the bus in relation to one another; and at least one RS timing block (153; 153, 154) that is respectively configured to control the signal on a bus wire (41; 42) on the basis of the detection result of the phase angle detection block in order to adjust the phase angle of the signal on the bus wire (41; 42), characterized in that the RS timing blocks (153; 153, 154) are configured in such a way that the time of actuation of the transistors (155, 156; 159, 160) is adjustable in fractions of the bit time. a detection block (151; 151, 152) that is configured to detect a change of state of the received signal from the dominant bus state to the recessive bus state; transistors (155, 156; 159, 160) that are connected up in such a way as to respond to detection of a change of state of the received signal from the dominant bus state to the recessive bus state by connecting the at least one bus wire (41; 42) of the bus to a bus bias voltage unit; a phase angle detection block for detecting the temporal position of the signals on the bus wires (41, 42) of the bus in relation to one another; and at least one RS timing block (153; 153, 154) that is respectively configured to control the signal on a bus wire (41; 42) on the basis of the detection result of the phase angle detection block in order to adjust the phase angle of the signal on the bus wire (41; 42), characterized in that the RS timing blocks (153; 153, 154) are configured in such a way that the time of actuation of the transistors (155, 156; 159, 160) is adjustable in fractions of the bit time.