An array substrate, comprising: a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line; wherein every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group (100, 200), each pixel unit group (100, 200) comprises a plurality of columns of pixel units; each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer (21, 22) on the base substrate, a first insulating layer on a side of the conductive semiconductor layer (21, 22) distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer (21, 22), a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer (21, 22) comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode; the metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode; the metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group (100, 200) through two corresponding drain vias; and the source electrode is electrically connected to the first semiconductor electrode through the source via. a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line; wherein every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group (100, 200), each pixel unit group (100, 200) comprises a plurality of columns of pixel units; each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer (21, 22) on the base substrate, a first insulating layer on a side of the conductive semiconductor layer (21, 22) distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer (21, 22), a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer (21, 22) comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode; the metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode; the metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group (100, 200) through two corresponding drain vias; and the source electrode is electrically connected to the first semiconductor electrode through the source via.