An output circuit comprising: a first transistor including a drain terminal coupled to an external terminal and a gate terminal that receives a first drive signal, wherein the first transistor drives a potential at the external terminal in accordance with the first drive signal; a first capacitor including a first end coupled to the gate terminal of the first transistor and a second end coupled to the drain terminal of the first transistor and the external terminal; and a circuit portion (T12,C11) coupled to the first transistor, wherein the circuit portion (T12,C11) maintains the first transistor in an inactivated state when the gate terminal of the first transistor is in a floating state, wherein the circuit portion (T12, C11) includes: a second transistor including a gate terminal that receives a second drive signal, the second transistor coupled in series with the first transistor between the external terminal and a reference potential, wherein the first drive signal provided to the gate terminal of the first transistor and the second drive signal provided to the gate of the second transistor are in phase with respect to each other; and a second capacitor including a first end coupled to the gate terminal of the second transistor and a second end coupled to the reference potential, the output circuit further comprising: a first gate circuit that generates the first drive signal; and a second gate circuit that generates the second drive signal. a first transistor including a drain terminal coupled to an external terminal and a gate terminal that receives a first drive signal, wherein the first transistor drives a potential at the external terminal in accordance with the first drive signal; a first capacitor including a first end coupled to the gate terminal of the first transistor and a second end coupled to the drain terminal of the first transistor and the external terminal; and a circuit portion (T12,C11) coupled to the first transistor, wherein the circuit portion (T12,C11) maintains the first transistor in an inactivated state when the gate terminal of the first transistor is in a floating state, wherein the circuit portion (T12, C11) includes: a second transistor including a gate terminal that receives a second drive signal, the second transistor coupled in series with the first transistor between the external terminal and a reference potential, wherein the first drive signal provided to the gate terminal of the first transistor and the second drive signal provided to the gate of the second transistor are in phase with respect to each other; and a second capacitor including a first end coupled to the gate terminal of the second transistor and a second end coupled to the reference potential, a second transistor including a gate terminal that receives a second drive signal, the second transistor coupled in series with the first transistor between the external terminal and a reference potential, wherein the first drive signal provided to the gate terminal of the first transistor and the second drive signal provided to the gate of the second transistor are in phase with respect to each other; and a second capacitor including a first end coupled to the gate terminal of the second transistor and a second end coupled to the reference potential, the output circuit further comprising: a first gate circuit that generates the first drive signal; and a second gate circuit that generates the second drive signal. a first gate circuit that generates the first drive signal; and a second gate circuit that generates the second drive signal.