An amplifier module, comprising: a substrate with a mounting surface; a first power transistor die (132, 232, 332; 152, 525, 352) coupled to the mounting surface, wherein the first power transistor die (132, 232, 332; 152, 525, 352) includes a first transistor (335; 355) integrated within the first power transistor die (132, 232, 332; 152, 525, 352), and wherein the first transistor (335; 355) includes a first drain terminal (138, 338; 158, 358) and a first intrinsic drain node (230; 250) corresponding to the first drain terminal (138, 338; 158, 358); a second power transistor die (152, 525, 352; 132, 232, 332) coupled to the mounting surface, wherein the second power transistor die (152, 525, 352; 132, 232, 332) includes a second transistor (355; 335) integrated within the second power transistor die (152, 525, 352; 132, 232, 332), wherein the second transistor (355; 335) includes a second drain terminal (158, 358; 138, 338) and a second intrinsic drain node (250; 230) corresponding to the second drain terminal (158, 358; 138, 338) and wherein the first and second power transistor die are coupled to the mounting surface such that a first and second signal path through the first and second power transistor die, respectively, extend in non-parallel directions having an angular separation of at least +/- 45 degrees from each other; a phase shift and impedance inversion element (172, 272, 372) connected between the first drain terminal (138, 338; 158, 358) and the second drain terminal (158, 358; 138, 338), wherein a total electrical length between the first and second intrinsic drain nodes (230, 250) is ninety degrees, and the phase shift and impedance inversion element (172, 272, 372) has a first electrical length that is less than ninety degrees; and a first shunt inductance circuit (240, 340, 540; 241, 341) coupled to the first drain terminal (138, 338; 158, 358), wherein the first shunt inductance circuit (240, 340, 540; 241, 341) includes a first shunt inductance (142, 242, 342, 542; 146, 246, 346, 546) that has a first inductance value that at least partially resonates out a drain-source capacitance (234, 254) of the first transistor (335; 355) to affect the first electrical length of the phase shift and impedance inversion element (172, 272, 372). a substrate with a mounting surface; a first power transistor die (132, 232, 332; 152, 525, 352) coupled to the mounting surface, wherein the first power transistor die (132, 232, 332; 152, 525, 352) includes a first transistor (335; 355) integrated within the first power transistor die (132, 232, 332; 152, 525, 352), and wherein the first transistor (335; 355) includes a first drain terminal (138, 338; 158, 358) and a first intrinsic drain node (230; 250) corresponding to the first drain terminal (138, 338; 158, 358); a second power transistor die (152, 525, 352; 132, 232, 332) coupled to the mounting surface, wherein the second power transistor die (152, 525, 352; 132, 232, 332) includes a second transistor (355; 335) integrated within the second power transistor die (152, 525, 352; 132, 232, 332), wherein the second transistor (355; 335) includes a second drain terminal (158, 358; 138, 338) and a second intrinsic drain node (250; 230) corresponding to the second drain terminal (158, 358; 138, 338) and wherein the first and second power transistor die are coupled to the mounting surface such that a first and second signal path through the first and second power transistor die, respectively, extend in non-parallel directions having an angular separation of at least +/- 45 degrees from each other; a phase shift and impedance inversion element (172, 272, 372) connected between the first drain terminal (138, 338; 158, 358) and the second drain terminal (158, 358; 138, 338), wherein a total electrical length between the first and second intrinsic drain nodes (230, 250) is ninety degrees, and the phase shift and impedance inversion element (172, 272, 372) has a first electrical length that is less than ninety degrees; and a first shunt inductance circuit (240, 340, 540; 241, 341) coupled to the first drain terminal (138, 338; 158, 358), wherein the first shunt inductance circuit (240, 340, 540; 241, 341) includes a first shunt inductance (142, 242, 342, 542; 146, 246, 346, 546) that has a first inductance value that at least partially resonates out a drain-source capacitance (234, 254) of the first transistor (335; 355) to affect the first electrical length of the phase shift and impedance inversion element (172, 272, 372).