A memory device, comprising: a first semiconductor structure comprising a Flash memory controller, a peripheral circuit, and a first bonding layer comprising a plurality of first bonding contacts; a second semiconductor structure comprising an array of NAND memory cells (337, 416) and a second bonding layer comprising a plurality of second bonding contacts; wherein the peripheral circuit comprises one or more page buffers and word line drivers of the array of NAND memory cells, and wherein the Flash memory controller comprises a host interface operatively coupled to a host processor, a NAND memory interface operatively coupled to the array of NAND memory cells, a management module, and an error correction code, ECC, module; wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the Flash memory controller, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of NAND memory cells; and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface, and wherein the bonding interface between the first bonding layer and the second bonding layer is as a result of hybrid bonding that obtains metal-metal bonding and dielectric-dielectric bonding simultaneously; wherein the peripheral circuit is electrically connected to the Flash memory controller through the first interconnect layer; and wherein the peripheral circuit is electrically connected to the array of NAND memory cells through the first and second interconnect layers and the first and second bonding contacts, characterised in that the Flash memory controller and the peripheral circuit are stacked one over another. a first semiconductor structure comprising a Flash memory controller, a peripheral circuit, and a first bonding layer comprising a plurality of first bonding contacts; a second semiconductor structure comprising an array of NAND memory cells (337, 416) and a second bonding layer comprising a plurality of second bonding contacts; wherein the peripheral circuit comprises one or more page buffers and word line drivers of the array of NAND memory cells, and wherein the Flash memory controller comprises a host interface operatively coupled to a host processor, a NAND memory interface operatively coupled to the array of NAND memory cells, a management module, and an error correction code, ECC, module; wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the Flash memory controller, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of NAND memory cells; and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface, and wherein the bonding interface between the first bonding layer and the second bonding layer is as a result of hybrid bonding that obtains metal-metal bonding and dielectric-dielectric bonding simultaneously; wherein the peripheral circuit is electrically connected to the Flash memory controller through the first interconnect layer; and wherein the peripheral circuit is electrically connected to the array of NAND memory cells through the first and second interconnect layers and the first and second bonding contacts, characterised in that the Flash memory controller and the peripheral circuit are stacked one over another.