A method comprising: receiving sets of digital samples associated with received wireless signals, wherein each of the sets of digital samples corresponds to a particular radio-frequency path; providing the sets of digital samples to a plurality of pipelines, wherein each of the plurality of pipelines includes a plurality of stages, and wherein each of the plurality of stages includes one or more digital logic circuits; receiving, from a receiver processor, control data for the plurality of pipelines; providing the control data to a first pipeline of the plurality of pipelines; generating, by one or more of the plurality of pipelines, sets of interconnect data based on the sets of digital samples, wherein the sets of interconnect data include at least one accumulating value; passing the sets of interconnect data between adjacent pipelines of the plurality of pipelines along a direction; and generating, by a last pipeline of the plurality of pipelines, a result based on the at least one accumulating value; characterized in that generating the sets of interconnect data based on the sets of digital samples includes: generating, by the first pipeline, a first set of interconnect data based on a first set of digital samples of the sets of digital samples and the control data; generating, by a second pipeline of the plurality of pipelines, a second set of interconnect data based on a second set of digital samples of the sets of digital samples and the first set of interconnect data; and generating, by a third pipeline of the plurality of pipelines, a third set of interconnect data based on a third set of digital samples of the sets of digital samples and the second set of interconnect data. receiving sets of digital samples associated with received wireless signals, wherein each of the sets of digital samples corresponds to a particular radio-frequency path; providing the sets of digital samples to a plurality of pipelines, wherein each of the plurality of pipelines includes a plurality of stages, and wherein each of the plurality of stages includes one or more digital logic circuits; receiving, from a receiver processor, control data for the plurality of pipelines; providing the control data to a first pipeline of the plurality of pipelines; generating, by one or more of the plurality of pipelines, sets of interconnect data based on the sets of digital samples, wherein the sets of interconnect data include at least one accumulating value; passing the sets of interconnect data between adjacent pipelines of the plurality of pipelines along a direction; and generating, by a last pipeline of the plurality of pipelines, a result based on the at least one accumulating value; characterized in that generating the sets of interconnect data based on the sets of digital samples includes: generating, by the first pipeline, a first set of interconnect data based on a first set of digital samples of the sets of digital samples and the control data; generating, by a second pipeline of the plurality of pipelines, a second set of interconnect data based on a second set of digital samples of the sets of digital samples and the first set of interconnect data; and generating, by a third pipeline of the plurality of pipelines, a third set of interconnect data based on a third set of digital samples of the sets of digital samples and the second set of interconnect data. generating, by the first pipeline, a first set of interconnect data based on a first set of digital samples of the sets of digital samples and the control data; generating, by a second pipeline of the plurality of pipelines, a second set of interconnect data based on a second set of digital samples of the sets of digital samples and the first set of interconnect data; and generating, by a third pipeline of the plurality of pipelines, a third set of interconnect data based on a third set of digital samples of the sets of digital samples and the second set of interconnect data.