A turbo encoder apparatus for receiving an input bitstream of input data to generate and output encoded bitstreams, the turbo encoder apparatus comprising: a first element encoder for receiving the input bitstream of input data which has a size K of a designated code block and in which a padding has been implemented, encoding the input bitstream of input data, and generating two first output bitstreams, wherein said receiving, said encoding and said generating by the first element encoder are performed in a unit of 8 bits per clock cycle, respectively; an internal interleaver for generating an interleaved input bitstream from the input bitstream of input data; a second element encoder for receiving the interleaved input bitstream, encoding the interleaved input bitstream, and generating a second output bitstream, wherein said receiving, said encoding and said generating by the second element encoder are performed in a unit of 8 bits per clock cycle, respectively; and a trellis termination encoder for generating bits for trellis terminations of the first element encoder and the second element encoder, characterized in that the turbo encoder apparatus further comprises a bitstream assembler for receiving the first output bitstreams, the second output bitstream, and 12 bits for the trellis terminations, dividing the 12 bits for the trellis terminations into three 4-bit parts, connecting the three 4-bit parts to the first and the second output bitstreams, respectively, and inserting null bits into a front portion of each of the first and the second output bitstreams such that each of the first and second output bitstreams has the unit of 4 bytes, wherein the bitstream assembler is configured to add and insert said null bits by changing positions of upper 4 bits and lower 4 bits in a 8 bit unit of the first output bitstreams and the second output bitstream, delaying the lower 4 bits by one cycle using a 4-bit register, and making the lower 4 bits pass through a cycle delay circuit according to the number of null bits to be added, thereby adding and inserting 32-(K+4) mod 32 null bits before the upper 4 bits. a first element encoder for receiving the input bitstream of input data which has a size K of a designated code block and in which a padding has been implemented, encoding the input bitstream of input data, and generating two first output bitstreams, wherein said receiving, said encoding and said generating by the first element encoder are performed in a unit of 8 bits per clock cycle, respectively; an internal interleaver for generating an interleaved input bitstream from the input bitstream of input data; a second element encoder for receiving the interleaved input bitstream, encoding the interleaved input bitstream, and generating a second output bitstream, wherein said receiving, said encoding and said generating by the second element encoder are performed in a unit of 8 bits per clock cycle, respectively; and a trellis termination encoder for generating bits for trellis terminations of the first element encoder and the second element encoder, characterized in that the turbo encoder apparatus further comprises a bitstream assembler for receiving the first output bitstreams, the second output bitstream, and 12 bits for the trellis terminations, dividing the 12 bits for the trellis terminations into three 4-bit parts, connecting the three 4-bit parts to the first and the second output bitstreams, respectively, and inserting null bits into a front portion of each of the first and the second output bitstreams such that each of the first and second output bitstreams has the unit of 4 bytes, wherein the bitstream assembler is configured to add and insert said null bits by changing positions of upper 4 bits and lower 4 bits in a 8 bit unit of the first output bitstreams and the second output bitstream, delaying the lower 4 bits by one cycle using a 4-bit register, and making the lower 4 bits pass through a cycle delay circuit according to the number of null bits to be added, thereby adding and inserting 32-(K+4) mod 32 null bits before the upper 4 bits.