A phased array antenna system, comprising: a beam steering computer; a plurality M, where M is an integer, of antenna elements each one being coupled to a corresponding one of a plurality of M antenna ports; a plurality of M frequency conversion/variable time delay circuits, an input port (16 1, 16 m) of each one of the M frequency conversion/variable time delay circuits being coupled to a corresponding one of the M antenna ports, each one of the M frequency conversion/variable time delay circuits comprising a frequency conversion circuit, wherein the frequency conversion /variable time delay circuit comprises: a plurality of N signal channels, wherein N is an integer, each being fed an input signal (RF Input) of the corresponding input port (16 1, 16 m) and a train of pulses having a period T and a duty cycle T/N, each signal channel comprising: a sampler coupled to the input signal and being responsive to a train of sampling signals; and a controllable time delay(30a-d) for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed by the beam steering computer to the time delay; wherein the train of sampling signals of each signal channel is produced by the time delay in the channel with the period T and the duty cycle T/N, with the train of the sampling signals being delayed with respect to the train of sampling signals in another one of the signal channels by a time T/N. a beam steering computer; a plurality M, where M is an integer, of antenna elements each one being coupled to a corresponding one of a plurality of M antenna ports; a plurality of M frequency conversion/variable time delay circuits, an input port (16 1, 16 m) of each one of the M frequency conversion/variable time delay circuits being coupled to a corresponding one of the M antenna ports, each one of the M frequency conversion/variable time delay circuits comprising a frequency conversion circuit, wherein the frequency conversion /variable time delay circuit comprises: a plurality of N signal channels, wherein N is an integer, each being fed an input signal (RF Input) of the corresponding input port (16 1, 16 m) and a train of pulses having a period T and a duty cycle T/N, each signal channel comprising: a sampler coupled to the input signal and being responsive to a train of sampling signals; and a controllable time delay(30a-d) for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed by the beam steering computer to the time delay; a sampler coupled to the input signal and being responsive to a train of sampling signals; and a controllable time delay(30a-d) for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed by the beam steering computer to the time delay; wherein the train of sampling signals of each signal channel is produced by the time delay in the channel with the period T and the duty cycle T/N, with the train of the sampling signals being delayed with respect to the train of sampling signals in another one of the signal channels by a time T/N.