A circuit to generate a local clock signal from a forwarded clock signal, the circuit comprising: a plurality of substantially similar delay multiplexers connected in a ring to generate the local clock signal, and propagation delay control circuit, configured to adjust a propagation delay of each of the plurality of delay multiplexers; wherein each delay multiplexer of the plurality of delay multiplexers comprises a feedback clock input, a feed-in clock input, and an enable input, wherein a first delay multiplexer is adapted to output, according to a value received at the enable input, either: an inverse of a feedback clock signal (CK FB) received, at the feedback clock input, from a last delay multiplexer of the plurality of delay multiplexers; or an inverse of a feed-in clock signal (CK FI), received at the feed-in clock input, and wherein a second delay multiplexer of the plurality of delay multiplexers comprises a feedback clock input and is configured to output the inverse of a feedback clock signal received, at the feedback clock input of the second delay multiplexer, from another delay multiplexer of the plurality of delay multiplexers; characterized by a pulse generator comprising a first pulse generator output and a second pulse generator output, the pulse generator being configured to generate, at the first pulse generator output, after each rising edge of the forwarded clock signal, the feed-in clock signal (CK FI) having a first triggering edge following a rising edge of the forwarded clock signal by a substantially fixed delay and having a second triggering edge following a falling edge of the forwarded clock signal by a substantially fixed delay, wherein the pulse generator is adapted to generate, at the second pulse generator output, an enable signal, the enable signal having an enabling level during a time interval overlapping the triggering edge of the feed-in clock, and wherein the first pulse generator output is connected to the feed-in clock input, and the second pulse generator output is connected to the enable input. a plurality of substantially similar delay multiplexers connected in a ring to generate the local clock signal, and propagation delay control circuit, configured to adjust a propagation delay of each of the plurality of delay multiplexers; wherein each delay multiplexer of the plurality of delay multiplexers comprises a feedback clock input, a feed-in clock input, and an enable input, wherein a first delay multiplexer is adapted to output, according to a value received at the enable input, either: an inverse of a feedback clock signal (CK FB) received, at the feedback clock input, from a last delay multiplexer of the plurality of delay multiplexers; or an inverse of a feed-in clock signal (CK FI), received at the feed-in clock input, and wherein a second delay multiplexer of the plurality of delay multiplexers comprises a feedback clock input and is configured to output the inverse of a feedback clock signal received, at the feedback clock input of the second delay multiplexer, from another delay multiplexer of the plurality of delay multiplexers; characterized by a pulse generator comprising a first pulse generator output and a second pulse generator output, the pulse generator being configured to generate, at the first pulse generator output, after each rising edge of the forwarded clock signal, the feed-in clock signal (CK FI) having a first triggering edge following a rising edge of the forwarded clock signal by a substantially fixed delay and having a second triggering edge following a falling edge of the forwarded clock signal by a substantially fixed delay, wherein the pulse generator is adapted to generate, at the second pulse generator output, an enable signal, the enable signal having an enabling level during a time interval overlapping the triggering edge of the feed-in clock, and wherein the first pulse generator output is connected to the feed-in clock input, and the second pulse generator output is connected to the enable input. an inverse of a feedback clock signal (CK FB) received, at the feedback clock input, from a last delay multiplexer of the plurality of delay multiplexers; or an inverse of a feed-in clock signal (CK FI), received at the feed-in clock input, and wherein a second delay multiplexer of the plurality of delay multiplexers comprises a feedback clock input and is configured to output the inverse of a feedback clock signal received, at the feedback clock input of the second delay multiplexer, from another delay multiplexer of the plurality of delay multiplexers; characterized by a pulse generator comprising a first pulse generator output and a second pulse generator output, the pulse generator being configured to generate, at the first pulse generator output, after each rising edge of the forwarded clock signal, the feed-in clock signal (CK FI) having a first triggering edge following a rising edge of the forwarded clock signal by a substantially fixed delay and having a second triggering edge following a falling edge of the forwarded clock signal by a substantially fixed delay, wherein the pulse generator is adapted to generate, at the second pulse generator output, an enable signal, the enable signal having an enabling level during a time interval overlapping the triggering edge of the feed-in clock, and wherein the first pulse generator output is connected to the feed-in clock input, and the second pulse generator output is connected to the enable input.