A system configured to verify that an integrated circuit defined by a first hardware design meets a power requirement, the system comprising: a first hardware monitor for the first hardware design; a second hardware monitor for a second hardware design; wherein each of the first and second hardware monitors (1108, 1110) comprises: one or more transition detection logic units (502, 504, 702, 704), the one or more transition detection logic units (502, 504, 702, 704) configured to detect whether a power consuming transition has occurred with one or more flip-flops (1114, 1116) of the respective hardware design (1102, 1104); and one or more counter update logic units (508, 708) in communication with the one or more transition detection logic units (502, 504, 702, 704), the one or more counter update logic units (508, 708) configured to count a number of power consuming transitions detected by the one or more transition detection logic units (502, 504, 702, 704); wherein the first hardware monitor further comprises a property verification logic unit (510, 710, 910) configured to determine whether the power requirement is met at a particular point in time by evaluating one or more properties based on the number of power consuming transitions counted by each of the one or more counter update logic units (508, 708), wherein each of the one or more properties is written in an assertion language so that the property can be formally verified by a formal verification tool, the one or more properties comprising a property that compares the count of power consuming transitions for the first hardware design to the count of power consuming transitions for the second hardware design; a scenario defined in a formal verification language; and the formal verification tool configured to formally verify whether the integrated circuit defined by the first hardware design meets the power requirement for the scenario using the first and second hardware monitors (1108, 1110) and the one or more properties. a first hardware monitor for the first hardware design; a second hardware monitor for a second hardware design; wherein each of the first and second hardware monitors (1108, 1110) comprises: one or more transition detection logic units (502, 504, 702, 704), the one or more transition detection logic units (502, 504, 702, 704) configured to detect whether a power consuming transition has occurred with one or more flip-flops (1114, 1116) of the respective hardware design (1102, 1104); and one or more counter update logic units (508, 708) in communication with the one or more transition detection logic units (502, 504, 702, 704), the one or more counter update logic units (508, 708) configured to count a number of power consuming transitions detected by the one or more transition detection logic units (502, 504, 702, 704); one or more transition detection logic units (502, 504, 702, 704), the one or more transition detection logic units (502, 504, 702, 704) configured to detect whether a power consuming transition has occurred with one or more flip-flops (1114, 1116) of the respective hardware design (1102, 1104); and one or more counter update logic units (508, 708) in communication with the one or more transition detection logic units (502, 504, 702, 704), the one or more counter update logic units (508, 708) configured to count a number of power consuming transitions detected by the one or more transition detection logic units (502, 504, 702, 704); wherein the first hardware monitor further comprises a property verification logic unit (510, 710, 910) configured to determine whether the power requirement is met at a particular point in time by evaluating one or more properties based on the number of power consuming transitions counted by each of the one or more counter update logic units (508, 708), wherein each of the one or more properties is written in an assertion language so that the property can be formally verified by a formal verification tool, the one or more properties comprising a property that compares the count of power consuming transitions for the first hardware design to the count of power consuming transitions for the second hardware design; a scenario defined in a formal verification language; and the formal verification tool configured to formally verify whether the integrated circuit defined by the first hardware design meets the power requirement for the scenario using the first and second hardware monitors (1108, 1110) and the one or more properties.