A circuit comprising: a voltage generator adapted to generate a variable supply voltage (V_CORE) for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal (CLK_CORE) of the processing core, wherein the frequency generator comprises a frequency locked loop comprising: a digitally controlled oscillator configured to generate the variable frequency clock signal (CLK_CORE); and a controller configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the product of a frequency error signal (F_ERR) and a gain, wherein the controller is configured to implement a frequency transition of the variable frequency clock signal (CLK_CORE) from a first frequency (F_H) to a second frequency (F_T) lower than the first frequency by generating: a first value of the digital control signal (C_FREQ) based on a first value of the gain applied to a first value of the frequency error signal (F_ERR) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency (F_L) lower than the second frequency (F_T); and characterized in that: the voltage generator is configured to implement a voltage transition from a first level of the variable supply voltage (V_CORE) to a second level lower than the first level following said first frequency reduction; and the controller is configured to implement the frequency transition by further generating further values of the digital control signal (C_FREQ) based on one or more further gain values different to and lower than the first value of the gain, wherein the controller is configured to apply said further gain values selected such that the second frequency (F_T) is not exceeded by the variable frequency clock signal. a voltage generator adapted to generate a variable supply voltage (V_CORE) for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal (CLK_CORE) of the processing core, wherein the frequency generator comprises a frequency locked loop comprising: a digitally controlled oscillator configured to generate the variable frequency clock signal (CLK_CORE); and a controller configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the product of a frequency error signal (F_ERR) and a gain, wherein the controller is configured to implement a frequency transition of the variable frequency clock signal (CLK_CORE) from a first frequency (F_H) to a second frequency (F_T) lower than the first frequency by generating: a first value of the digital control signal (C_FREQ) based on a first value of the gain applied to a first value of the frequency error signal (F_ERR) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency (F_L) lower than the second frequency (F_T); and characterized in that: the voltage generator is configured to implement a voltage transition from a first level of the variable supply voltage (V_CORE) to a second level lower than the first level following said first frequency reduction; and the controller is configured to implement the frequency transition by further generating further values of the digital control signal (C_FREQ) based on one or more further gain values different to and lower than the first value of the gain, wherein the controller is configured to apply said further gain values selected such that the second frequency (F_T) is not exceeded by the variable frequency clock signal. a digitally controlled oscillator configured to generate the variable frequency clock signal (CLK_CORE); and a controller configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the product of a frequency error signal (F_ERR) and a gain, wherein the controller is configured to implement a frequency transition of the variable frequency clock signal (CLK_CORE) from a first frequency (F_H) to a second frequency (F_T) lower than the first frequency by generating: a first value of the digital control signal (C_FREQ) based on a first value of the gain applied to a first value of the frequency error signal (F_ERR) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency (F_L) lower than the second frequency (F_T); and characterized in that: the voltage generator is configured to implement a voltage transition from a first level of the variable supply voltage (V_CORE) to a second level lower than the first level following said first frequency reduction; and the controller is configured to implement the frequency transition by further generating further values of the digital control signal (C_FREQ) based on one or more further gain values different to and lower than the first value of the gain, wherein the controller is configured to apply said further gain values selected such that the second frequency (F_T) is not exceeded by the variable frequency clock signal. the voltage generator is configured to implement a voltage transition from a first level of the variable supply voltage (V_CORE) to a second level lower than the first level following said first frequency reduction; and the controller is configured to implement the frequency transition by further generating further values of the digital control signal (C_FREQ) based on one or more further gain values different to and lower than the first value of the gain, wherein the controller is configured to apply said further gain values selected such that the second frequency (F_T) is not exceeded by the variable frequency clock signal.