A three-dimensional memory device (700, 701), comprising: a first semiconductor structure (702, 703) comprising an array of NAND memory cells and a first bonding layer (725, 744, 922) comprising a plurality of first bonding contacts (727, 746, 924): a second semiconductor structure (704, 705) comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer (726, 743, 1016) comprising a plurality of second bonding contacts (728, 745, 1018); a third semiconductor structure (706, 707) comprising an array of static random-access memory (SRAM) cells, a third bonding layer (729, 740, 816) comprising a plurality of third bonding contacts (731, 742, 818), and a fourth bonding layer (730, 739, 1106) comprising a plurality of fourth bonding contacts (732, 741, 1108); wherein the third bonding layer and the fourth bonding layer are on both sides of the array of SRAM cells; a first bonding interface (708, 709, 1102) between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with the third bonding contacts at the first bonding interface, wherein said third semiconductor structure is bonded with one of the first and second semiconductor structures in a face-to-face manner; and a second bonding interface (710, 711, 1202) between the second bonding layer and the fourth bonding layer, the second bonding contacts being in contact with the fourth bonding contacts at the second bonding interface, wherein said first bonding interface and said second bonding interface comprise a plurality of interconnects formed through first and second bonding, wherein the third semiconductor structure comprises all the peripheral circuits for controlling and sensing the NAND memory cells and all the peripheral circuits for controlling and sensing the array of DRAM. a first semiconductor structure (702, 703) comprising an array of NAND memory cells and a first bonding layer (725, 744, 922) comprising a plurality of first bonding contacts (727, 746, 924): a second semiconductor structure (704, 705) comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer (726, 743, 1016) comprising a plurality of second bonding contacts (728, 745, 1018); a third semiconductor structure (706, 707) comprising an array of static random-access memory (SRAM) cells, a third bonding layer (729, 740, 816) comprising a plurality of third bonding contacts (731, 742, 818), and a fourth bonding layer (730, 739, 1106) comprising a plurality of fourth bonding contacts (732, 741, 1108); wherein the third bonding layer and the fourth bonding layer are on both sides of the array of SRAM cells; a first bonding interface (708, 709, 1102) between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with the third bonding contacts at the first bonding interface, wherein said third semiconductor structure is bonded with one of the first and second semiconductor structures in a face-to-face manner; and a second bonding interface (710, 711, 1202) between the second bonding layer and the fourth bonding layer, the second bonding contacts being in contact with the fourth bonding contacts at the second bonding interface, wherein said first bonding interface and said second bonding interface comprise a plurality of interconnects formed through first and second bonding, wherein the third semiconductor structure comprises all the peripheral circuits for controlling and sensing the NAND memory cells and all the peripheral circuits for controlling and sensing the array of DRAM.