A vector network analyzer for obtaining at least one wave frequency ratio with respect to a frequency-converting device under test, the vector network analyzer comprising: a transmitter side comprising a transmitter side synthesizer (20, 41a, 41b) and configured to be controlled by at least one transmitter side clock signal, a receiver side comprising a receiver side synthesizer (12, 42a, 42b) and configured to be controlled by at least one receiver side clock signal, and a central clock (14, 43) configured to generate a central clock signal, wherein the at least one transmitter side clock signal and the at least one receiver side clock signal are based on the central clock signal, and a controller configured to provide a common start pulse for the transmitter side and the receiver side, wherein the transmitter side synthesizer (20, 41a, 41b) is configured to generate a first output signal and the receiver side synthesizer (120, 42a, 42b) is configured to generate a second output signal, wherein the first and the second output signal are generated based on the common start pulse with a fixed phase relation to each other, wherein each of the synthesizers (20, 120) comprises: a direct digital source (21, 121) configured to generate a reference signal, a voltage controlled oscillator (24, 124) configured to receive a voltage from a phase detector (22, 122) in order to generate an oscillator signal, the phase detector (22, 122) configured to compare the reference signal with an input signal, and an integer divider (25, 125), configured to divide the oscillator signal by an integer and even value in order to provide a divided signal as an output signal of the transmitter side or the receiver side, and wherein the phase detector (22, 122) is configured to compare the reference signal with the divided signal as the input signal, and wherein at least one of the synthesizers (20, 120) of the vector network analyzer further comprises an additional integer divider (26, 126) configured to divide the divided signal by an integer value in order to generate a further divided signal as the input signal for the respective phase detector (22, 122). a transmitter side comprising a transmitter side synthesizer (20, 41a, 41b) and configured to be controlled by at least one transmitter side clock signal, a receiver side comprising a receiver side synthesizer (12, 42a, 42b) and configured to be controlled by at least one receiver side clock signal, and a central clock (14, 43) configured to generate a central clock signal, wherein the at least one transmitter side clock signal and the at least one receiver side clock signal are based on the central clock signal, and a controller configured to provide a common start pulse for the transmitter side and the receiver side, wherein the transmitter side synthesizer (20, 41a, 41b) is configured to generate a first output signal and the receiver side synthesizer (120, 42a, 42b) is configured to generate a second output signal, wherein the first and the second output signal are generated based on the common start pulse with a fixed phase relation to each other, a direct digital source (21, 121) configured to generate a reference signal, a voltage controlled oscillator (24, 124) configured to receive a voltage from a phase detector (22, 122) in order to generate an oscillator signal, the phase detector (22, 122) configured to compare the reference signal with an input signal, and an integer divider (25, 125), configured to divide the oscillator signal by an integer and even value in order to provide a divided signal as an output signal of the transmitter side or the receiver side, and wherein the phase detector (22, 122) is configured to compare the reference signal with the divided signal as the input signal, and wherein at least one of the synthesizers (20, 120) of the vector network analyzer further comprises an additional integer divider (26, 126) configured to divide the divided signal by an integer value in order to generate a further divided signal as the input signal for the respective phase detector (22, 122).