A system comprising: a register arranged for storing an address for each of one or more rows of a DRAM that do not meet a data retention criteria at a low power refresh rate; wherein the one or more rows of the DRAM do meet a data retention criteria at a standard refresh rate, which is greater than the low power refresh rate; a counter arranged for counting received refresh requests for the DRAM; refresh control circuitry coupled to the register and the counter, wherein the refresh control circuitry, in response to a refresh request for the DRAM and based on a count value of the counter, is arranged for: (i) performing a refresh of the DRAM; or (ii) accessing the register, to perform a refresh of the one or more rows of the DRAM identified in the register; and built-in self test (BIST) circuitry, which performs data retention testing on the DRAM to identify the one or more rows of the DRAM that meet the data retention criteria at the standard refresh rate, but that do not meet the data retention criteria at the low power refresh rate; wherein the data retention testing is in response to start-up of the DRAM, wherein a counter threshold value is determined such that it corresponds to the low power refresh rate, and wherein: (iii) when a count value of the counter does not equal the threshold value, the refresh control circuitry accesses the register to perform the refresh of the one or more rows of the DRAM identified in the register; and (iv) when the count value of the counter equals the threshold value, the refresh control circuitry performs the refresh of the DRAM, wherein the refresh of the DRAM includes refreshing the one or more rows of the DRAM identified in the register, as well as additional rows of the DRAM. a register arranged for storing an address for each of one or more rows of a DRAM that do not meet a data retention criteria at a low power refresh rate; wherein the one or more rows of the DRAM do meet a data retention criteria at a standard refresh rate, which is greater than the low power refresh rate; a counter arranged for counting received refresh requests for the DRAM; refresh control circuitry coupled to the register and the counter, wherein the refresh control circuitry, in response to a refresh request for the DRAM and based on a count value of the counter, is arranged for: (i) performing a refresh of the DRAM; or (ii) accessing the register, to perform a refresh of the one or more rows of the DRAM identified in the register; and (i) performing a refresh of the DRAM; or (ii) accessing the register, to perform a refresh of the one or more rows of the DRAM identified in the register; and built-in self test (BIST) circuitry, which performs data retention testing on the DRAM to identify the one or more rows of the DRAM that meet the data retention criteria at the standard refresh rate, but that do not meet the data retention criteria at the low power refresh rate; wherein the data retention testing is in response to start-up of the DRAM, wherein a counter threshold value is determined such that it corresponds to the low power refresh rate, and wherein: (iii) when a count value of the counter does not equal the threshold value, the refresh control circuitry accesses the register to perform the refresh of the one or more rows of the DRAM identified in the register; and (iv) when the count value of the counter equals the threshold value, the refresh control circuitry performs the refresh of the DRAM, wherein the refresh of the DRAM includes refreshing the one or more rows of the DRAM identified in the register, as well as additional rows of the DRAM. (iii) when a count value of the counter does not equal the threshold value, the refresh control circuitry accesses the register to perform the refresh of the one or more rows of the DRAM identified in the register; and (iv) when the count value of the counter equals the threshold value, the refresh control circuitry performs the refresh of the DRAM, wherein the refresh of the DRAM includes refreshing the one or more rows of the DRAM identified in the register, as well as additional rows of the DRAM.