An apparatus comprising: a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (106, 306) and a feedback clock signal and to output a frequency control signal based on a phase difference between the reference clock signal (106, 306) and the feedback clock signal; a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316, 318) for generating said feedback clock signal by frequency-dividing said oscillator signal; and second divider circuitry for generating an output clock signal (258, 322) by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry and said second divider circuitry is adjustable to delay or advance said output clock signal relative to said feedback clock signal; and an inverter for inverting said oscillator signal to generate an inverted oscillator signal; wherein: one of said first divider circuitry (316, 318) and said second divider circuitry comprises a first master divider (316a, 320a) arranged to receive said oscillator signal; the other one of said first divider circuitry (316, 318) and said second divider circuitry comprises a first slave divider (316a, 320a) arranged to selectively receive said oscillator signal or said inverted oscillator signal; and said first slave divider is configured to re-clock a selected output of said first master divider based on said selected one of said oscillator signal and said inverted oscillator signal. a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (106, 306) and a feedback clock signal and to output a frequency control signal based on a phase difference between the reference clock signal (106, 306) and the feedback clock signal; a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316, 318) for generating said feedback clock signal by frequency-dividing said oscillator signal; and second divider circuitry for generating an output clock signal (258, 322) by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry and said second divider circuitry is adjustable to delay or advance said output clock signal relative to said feedback clock signal; and a phase detector (302, 304), arranged to receive a reference clock signal (106, 306) and a feedback clock signal and to output a frequency control signal based on a phase difference between the reference clock signal (106, 306) and the feedback clock signal; a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316, 318) for generating said feedback clock signal by frequency-dividing said oscillator signal; and second divider circuitry for generating an output clock signal (258, 322) by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry and said second divider circuitry is adjustable to delay or advance said output clock signal relative to said feedback clock signal; and an inverter for inverting said oscillator signal to generate an inverted oscillator signal; wherein: one of said first divider circuitry (316, 318) and said second divider circuitry comprises a first master divider (316a, 320a) arranged to receive said oscillator signal; the other one of said first divider circuitry (316, 318) and said second divider circuitry comprises a first slave divider (316a, 320a) arranged to selectively receive said oscillator signal or said inverted oscillator signal; and said first slave divider is configured to re-clock a selected output of said first master divider based on said selected one of said oscillator signal and said inverted oscillator signal. one of said first divider circuitry (316, 318) and said second divider circuitry comprises a first master divider (316a, 320a) arranged to receive said oscillator signal; the other one of said first divider circuitry (316, 318) and said second divider circuitry comprises a first slave divider (316a, 320a) arranged to selectively receive said oscillator signal or said inverted oscillator signal; and said first slave divider is configured to re-clock a selected output of said first master divider based on said selected one of said oscillator signal and said inverted oscillator signal.