A method performed by one or more data processing apparatus, the method comprising: receiving data representing code of a program to be executed by a processing unit comprising multiple hardware processors; for one or more of the multiple hardware processors: identifying, in the data representing the code of the program, an order of multiple independent groups of first-in-first-out (FIFO) instructions for execution by the hardware processor; determining that an independent group of FIFO instructions of a further hardware processor in the plurality of hardware processors is an instruction to receive data output by one of the multiple independent groups of FIFO instructions of the hardware processor; determining, for each independent group of FIFO instructions for execution by the hardware processor, a path length metric that represents how long it will take to reach an end of the program from the independent group of FIFO instructions; and generating, based at least on the path length metric for each independent group of FIFO instructions for execution by the hardware processor, a new order of the independent groups of FIFO instructions for execution by the hardware processor such that the latency of execution of the program is reduced, the generating comprising moving the one independent group of FIFO instructions of the hardware processor to execute before one or more other independent groups of FIFO instructions of the hardware processor in response to determining that an independent group of FIFO instructions of the further hardware processor is an instruction to receive data output by the one independent group of FIFO instructions of the hardware processor; generating updated code for the program based at least on each new order of independent groups of FIFO instructions for the multiple hardware processors; generating, based on the updated code for the program, output code for execution by the multiple hardware processors; and providing the output code to the multiple hardware processors. receiving data representing code of a program to be executed by a processing unit comprising multiple hardware processors; for one or more of the multiple hardware processors: identifying, in the data representing the code of the program, an order of multiple independent groups of first-in-first-out (FIFO) instructions for execution by the hardware processor; determining that an independent group of FIFO instructions of a further hardware processor in the plurality of hardware processors is an instruction to receive data output by one of the multiple independent groups of FIFO instructions of the hardware processor; determining, for each independent group of FIFO instructions for execution by the hardware processor, a path length metric that represents how long it will take to reach an end of the program from the independent group of FIFO instructions; and generating, based at least on the path length metric for each independent group of FIFO instructions for execution by the hardware processor, a new order of the independent groups of FIFO instructions for execution by the hardware processor such that the latency of execution of the program is reduced, the generating comprising moving the one independent group of FIFO instructions of the hardware processor to execute before one or more other independent groups of FIFO instructions of the hardware processor in response to determining that an independent group of FIFO instructions of the further hardware processor is an instruction to receive data output by the one independent group of FIFO instructions of the hardware processor; identifying, in the data representing the code of the program, an order of multiple independent groups of first-in-first-out (FIFO) instructions for execution by the hardware processor; determining that an independent group of FIFO instructions of a further hardware processor in the plurality of hardware processors is an instruction to receive data output by one of the multiple independent groups of FIFO instructions of the hardware processor; determining, for each independent group of FIFO instructions for execution by the hardware processor, a path length metric that represents how long it will take to reach an end of the program from the independent group of FIFO instructions; and generating, based at least on the path length metric for each independent group of FIFO instructions for execution by the hardware processor, a new order of the independent groups of FIFO instructions for execution by the hardware processor such that the latency of execution of the program is reduced, the generating comprising moving the one independent group of FIFO instructions of the hardware processor to execute before one or more other independent groups of FIFO instructions of the hardware processor in response to determining that an independent group of FIFO instructions of the further hardware processor is an instruction to receive data output by the one independent group of FIFO instructions of the hardware processor; generating updated code for the program based at least on each new order of independent groups of FIFO instructions for the multiple hardware processors; generating, based on the updated code for the program, output code for execution by the multiple hardware processors; and providing the output code to the multiple hardware processors.