A mask read-only memory, comprising: a substrate; a first gate structure (621, 613-1) formed on a surface of the substrate for receiving a word line voltage during a read cycle; a second gate structure (620, 613-2) formed on the surface of the substrate; a third gate structure (622, 613-3) formed on the surface of the substrate; a first diffusion region formed in the surface of the substrate and located adjacent to a first side of the first gate structure (621, 613-1) for generating a first bit line voltage during the read cycle; a second diffusion region formed in the surface of the substrate, and located adjacent to a second side of the first gate structure (621, 613-1) and extended to a first side of the second gate structure (620, 613-2) and a first side of the third gate structure (622, 613-3); a third diffusion region formed in the surface of the substrate for receiving a select line voltage during the read cycle; a fourth gate structure (671, 663-1) formed on the surface of the substrate for receiving the word line voltage during the read cycle; a fifth gate structure (670, 663-2) formed on the surface of the substrate; a sixth gate structure (672, 663-3) formed on the surface of the substrate; a fourth diffusion region formed in the surface of the substrate and located adjacent to a first side of the fourth gate structure (671, 663-1) for generating a second bit line voltage during the read cycle; a fifth diffusion region formed in the surface of the substrate, and located adjacent to a second side of the fourth gate structure (671, 663-1) and extended to a first side of the fifth gate structure (670, 663-2) and a first side of the sixth gate structure (672, 663-3); and a sixth diffusion region formed in the surface of the substrate and contacted with the fifth diffusion region for receiving the select line voltage during the read cycle, wherein the first bit line voltage is different from the second bit line voltage. a substrate; a first gate structure (621, 613-1) formed on a surface of the substrate for receiving a word line voltage during a read cycle; a second gate structure (620, 613-2) formed on the surface of the substrate; a third gate structure (622, 613-3) formed on the surface of the substrate; a first diffusion region formed in the surface of the substrate and located adjacent to a first side of the first gate structure (621, 613-1) for generating a first bit line voltage during the read cycle; a second diffusion region formed in the surface of the substrate, and located adjacent to a second side of the first gate structure (621, 613-1) and extended to a first side of the second gate structure (620, 613-2) and a first side of the third gate structure (622, 613-3); a third diffusion region formed in the surface of the substrate for receiving a select line voltage during the read cycle; a fourth gate structure (671, 663-1) formed on the surface of the substrate for receiving the word line voltage during the read cycle; a fifth gate structure (670, 663-2) formed on the surface of the substrate; a sixth gate structure (672, 663-3) formed on the surface of the substrate; a fourth diffusion region formed in the surface of the substrate and located adjacent to a first side of the fourth gate structure (671, 663-1) for generating a second bit line voltage during the read cycle; a fifth diffusion region formed in the surface of the substrate, and located adjacent to a second side of the fourth gate structure (671, 663-1) and extended to a first side of the fifth gate structure (670, 663-2) and a first side of the sixth gate structure (672, 663-3); and a sixth diffusion region formed in the surface of the substrate and contacted with the fifth diffusion region for receiving the select line voltage during the read cycle, wherein the first bit line voltage is different from the second bit line voltage.