: An apparatus comprising: a processor comprising a first processing domain (510, 810) including a first plurality of cores, the first processing domain being a core domain, and a second processing domain (520, 820, 825, 850, 855) including a graphics engine, the second processing domain being a graphics domain; and a power controller (555, 840) to control power consumption of the first processing domain and the second processing domain, the power controller (555, 840) including: a first logic to receive a performance scale value corresponding to a desired performance state for each of the first and second processing domains (510, 810) from system software, to access a table to map the performance scale value corresponding to the desired performance state for the first processing domain to a target operating frequency for the first processing domain (510, 810) based at least in part on the respective performance scale value, to access a table to map the performance scale value corresponding to the desired performance state for the second processing domain to a target operating frequency for the second processing domain (520, 820, 825, 850, 855) based at least in part on the respective performance scale value, to adjust the target operating frequency for the first processing domain based at least in part on at least one first processing domain constraint; to adjust the target operating frequency for the second processing domain based at least in part on at least one second processing domain constraint; and a frequency control logic to cause the first processing domain (510, 810) to operate at the adjusted target operating frequency for the first processing domain (510, 810) and to cause the second processing domain (520, 820, 825, 850, 855) to operate at the adjusted target operating frequency for the second processing domain (520, 820, 825, 850, 855). a processor comprising a first processing domain (510, 810) including a first plurality of cores, the first processing domain being a core domain, and a second processing domain (520, 820, 825, 850, 855) including a graphics engine, the second processing domain being a graphics domain; and a power controller (555, 840) to control power consumption of the first processing domain and the second processing domain, the power controller (555, 840) including: a first logic to receive a performance scale value corresponding to a desired performance state for each of the first and second processing domains (510, 810) from system software, to access a table to map the performance scale value corresponding to the desired performance state for the first processing domain to a target operating frequency for the first processing domain (510, 810) based at least in part on the respective performance scale value, to access a table to map the performance scale value corresponding to the desired performance state for the second processing domain to a target operating frequency for the second processing domain (520, 820, 825, 850, 855) based at least in part on the respective performance scale value, to adjust the target operating frequency for the first processing domain based at least in part on at least one first processing domain constraint; to adjust the target operating frequency for the second processing domain based at least in part on at least one second processing domain constraint; and to receive a performance scale value corresponding to a desired performance state for each of the first and second processing domains (510, 810) from system software, to access a table to map the performance scale value corresponding to the desired performance state for the first processing domain to a target operating frequency for the first processing domain (510, 810) based at least in part on the respective performance scale value, to access a table to map the performance scale value corresponding to the desired performance state for the second processing domain to a target operating frequency for the second processing domain (520, 820, 825, 850, 855) based at least in part on the respective performance scale value, to adjust the target operating frequency for the first processing domain based at least in part on at least one first processing domain constraint; to adjust the target operating frequency for the second processing domain based at least in part on at least one second processing domain constraint; and a frequency control logic to cause the first processing domain (510, 810) to operate at the adjusted target operating frequency for the first processing domain (510, 810) and to cause the second processing domain (520, 820, 825, 850, 855) to operate at the adjusted target operating frequency for the second processing domain (520, 820, 825, 850, 855).