A display device including a display panel, the display panel comprising a pulse signal combination circuit for combining N input pulse signals into an output pulse signal being a multiple-pulse gate driving signal for driving the display panel, the N input pulse signals being sequentially effective in a temporal order from the first to the N th signal within each display period, N being an integer greater than 1, the pulse signal combination circuit comprising N output control units and a pulse signal output end, wherein a first control end of the n th output control unit is configured to receive the n th input pulse signal, a second control end of the n th output control unit is configured to receive the (n+1) th input pulse signal, and an output end of nth output control unit is connected to the pulse signal output end; the n th output control unit is configured to, within a time duration of each display period after the nth input pulse signal is effective for the first time and before the (n+1) th input pulse signal is effective for the first time, output the nth input pulse signal to the pulse signal output end, where n is a positive integer less than N; wherein a first control end of the N th output control unit is configured to receive the N th input pulse signal, a second control end of the N th output control unit is configured receive the first input pulse signal, and an output end of the N th output control unit is connected to the pulse signal output end; and the N th output control unit is configured to, within a time duration after the N th input pulse signal is effective for the first time within each display period and before the first input pulse signal is effective for the first time within a next display period, output the N th input pulse signal to the pulse signal output end; the circuit characterized in that each output control unit comprises: a first output control transistor, a gate electrode and a first electrode of which are connected to the first control end of the output control unit; a second output control transistor, a gate electrode of which is connected to the second control end of the output control unit, a first electrode of which is connected to a second electrode of the first output control transistor, and a second electrode of which is configured to receive a first level; and a third output control transistor, a gate electrode of which is connected to the second electrode of the first output control transistor, a first electrode of which is connected to the first control end, and a second electrode of which is connected to the pulse signal output end, wherein when the second output control transistor is turned on and the gate electrode of the third output control transistor is configured to receive the first level, the third output control transistor is turned off. a first output control transistor, a gate electrode and a first electrode of which are connected to the first control end of the output control unit; a second output control transistor, a gate electrode of which is connected to the second control end of the output control unit, a first electrode of which is connected to a second electrode of the first output control transistor, and a second electrode of which is configured to receive a first level; and a third output control transistor, a gate electrode of which is connected to the second electrode of the first output control transistor, a first electrode of which is connected to the first control end, and a second electrode of which is connected to the pulse signal output end, wherein when the second output control transistor is turned on and the gate electrode of the third output control transistor is configured to receive the first level, the third output control transistor is turned off.