An apparatus comprising: means configured to decode a single instruction having an opcode, a destination field representing a destination operand, and fields for a first packed data source operand, a second packed data source operand, and a third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data source operand and the destination operand, and wherein the first size is half of the second size; a register file having a plurality of packed data registers including registers for the source and destination operands; and means configured to execute the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a pair of half-sized packed data elements from the first and second packed data source operands that correspond to a packed data element position of the third packed data source operand, add of results from these multiplications to a full-sized packed data element of the packed data element position of the third packed data source operand, wherein, for each packed data element position [i] of the third packed data source operand, a multiplication of a packed data element from a packed data element position from the first packed data source to a packed data element from a packed data element position from the second packed data source to generate a first result, a multiplication of a packed data element from a packed data element position [2i+1] from the first packed data source to a packed data element from a packed data element position [2i+1] from the second packed data source to generate a second result, and an addition of the first and second results to the packed data element of the packed data element position [i] of the third packed data source operand, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source operand, wherein the opcode of the single instruction is configured to define the first size of the packed data elements of the first and second packed data source operand, and the second size of the packed data elements of the third packed data source operand. means configured to decode a single instruction having an opcode, a destination field representing a destination operand, and fields for a first packed data source operand, a second packed data source operand, and a third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data source operand and the destination operand, and wherein the first size is half of the second size; a register file having a plurality of packed data registers including registers for the source and destination operands; and means configured to execute the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a pair of half-sized packed data elements from the first and second packed data source operands that correspond to a packed data element position of the third packed data source operand, add of results from these multiplications to a full-sized packed data element of the packed data element position of the third packed data source operand, wherein, for each packed data element position [i] of the third packed data source operand, a multiplication of a packed data element from a packed data element position from the first packed data source to a packed data element from a packed data element position from the second packed data source to generate a first result, a multiplication of a packed data element from a packed data element position [2i+1] from the first packed data source to a packed data element from a packed data element position [2i+1] from the second packed data source to generate a second result, and an addition of the first and second results to the packed data element of the packed data element position [i] of the third packed data source operand, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source operand, wherein the opcode of the single instruction is configured to define the first size of the packed data elements of the first and second packed data source operand, and the second size of the packed data elements of the third packed data source operand.