A flash memory cell which is writable and erasable by application of programming and erase voltages and is readable by application of a read voltage comprising - a semiconductor substrate comprising a top side, - mutually spaced drain and source connection areas (24,26) formed in the top side of the semiconductor substrate, - a gate insulation layer (30,41) arranged on the top side of the semiconductor substrate between the drain and source connection areas (24,26), - a memory element projecting from the gate insulation layer and made of a storage material for electric charge, the memory element being chargeable and dischargeable by generating a tunnel current through the area of the gate insulation layer arranged below the memory element, - a control transistor gate electrode covering the gate insulation layer and surrounding the memory element on all sides and being electrically insulated therefrom by a dielectric (44,48), the control transistor gate electrode being provided for generating a selectively electrically conducting or blocking channel below the control transistor gate electrode, characterized in - that the memory element is positioned in a decentralized manner between the drain and source connection areas (24,26) and with respective lateral distance to both areas, and - that the top side of the semiconductor substrate comprises, below the gate insulation layer in a region between the drain and source connection areas (24,26), a lateral dopant profile which, in the region below the memory element, comprises a dopant of a first conductance type for setting a first threshold voltage, and, in the region below the control transistor gate electrode, comprises the first dopant and a second compensation dopant of a second conductance type opposed to the first conductance type, for setting a second threshold voltage which is lower than the first threshold voltage. - a semiconductor substrate comprising a top side, - mutually spaced drain and source connection areas (24,26) formed in the top side of the semiconductor substrate, - a gate insulation layer (30,41) arranged on the top side of the semiconductor substrate between the drain and source connection areas (24,26), - a memory element projecting from the gate insulation layer and made of a storage material for electric charge, the memory element being chargeable and dischargeable by generating a tunnel current through the area of the gate insulation layer arranged below the memory element, - a control transistor gate electrode covering the gate insulation layer and surrounding the memory element on all sides and being electrically insulated therefrom by a dielectric (44,48), the control transistor gate electrode being provided for generating a selectively electrically conducting or blocking channel below the control transistor gate electrode, characterized in - that the memory element is positioned in a decentralized manner between the drain and source connection areas (24,26) and with respective lateral distance to both areas, and - that the top side of the semiconductor substrate comprises, below the gate insulation layer in a region between the drain and source connection areas (24,26), a lateral dopant profile which, in the region below the memory element, comprises a dopant of a first conductance type for setting a first threshold voltage, and, in the region below the control transistor gate electrode, comprises the first dopant and a second compensation dopant of a second conductance type opposed to the first conductance type, for setting a second threshold voltage which is lower than the first threshold voltage.