A shift register comprising a plurality of stages (ST1,..., STn) respectively connected to a plurality of gate lines (GL1,..., GLn) of a display panel to output respective scan signals, wherein each stage (STi) includes: a transmission line unit including a plurality of clock lines to supply a plurality of clock signals and a plurality of power lines to supply a plurality of power voltages; and a transistor unit including a plurality of transistors, wherein the transistor unit of each stage (STi) includes: an output unit configured to output any one of the clock signals as the scan signal in response to control of a first node and to output gate off voltage as the scan signal in response to control of a second node; a first node controller including a plurality of transistors (T1, T2, T3) for controlling charge and discharge of the first node; and a second node controller including a plurality of transistors (T4, T5, T6) for controlling charge and discharge of the second node, characterised in that: each stage (STi) further includes a plurality of light-shielding layers (SL1, SL2) overlapping the transistor unit so as to block light, the plurality of light-shielding layers (SL1, SL2) includes a first light-shielding layer and a second light-shielding layer each overlapping different transistors and in that different voltages are applied to the first and second light-shielding layers (SL1, SL2). a transmission line unit including a plurality of clock lines to supply a plurality of clock signals and a plurality of power lines to supply a plurality of power voltages; and a transistor unit including a plurality of transistors, wherein the transistor unit of each stage (STi) includes: an output unit configured to output any one of the clock signals as the scan signal in response to control of a first node and to output gate off voltage as the scan signal in response to control of a second node; a first node controller including a plurality of transistors (T1, T2, T3) for controlling charge and discharge of the first node; and a second node controller including a plurality of transistors (T4, T5, T6) for controlling charge and discharge of the second node, characterised in that: each stage (STi) further includes a plurality of light-shielding layers (SL1, SL2) overlapping the transistor unit so as to block light, the plurality of light-shielding layers (SL1, SL2) includes a first light-shielding layer and a second light-shielding layer each overlapping different transistors and in that different voltages are applied to the first and second light-shielding layers (SL1, SL2). an output unit configured to output any one of the clock signals as the scan signal in response to control of a first node and to output gate off voltage as the scan signal in response to control of a second node; a first node controller including a plurality of transistors (T1, T2, T3) for controlling charge and discharge of the first node; and a second node controller including a plurality of transistors (T4, T5, T6) for controlling charge and discharge of the second node, characterised in that: each stage (STi) further includes a plurality of light-shielding layers (SL1, SL2) overlapping the transistor unit so as to block light, the plurality of light-shielding layers (SL1, SL2) includes a first light-shielding layer and a second light-shielding layer each overlapping different transistors and in that different voltages are applied to the first and second light-shielding layers (SL1, SL2). each stage (STi) further includes a plurality of light-shielding layers (SL1, SL2) overlapping the transistor unit so as to block light, the plurality of light-shielding layers (SL1, SL2) includes a first light-shielding layer and a second light-shielding layer each overlapping different transistors and in that different voltages are applied to the first and second light-shielding layers (SL1, SL2).