A method comprising: providing an electronic device with a first surface and a second surface opposite the first surface; providing a first solder pad at a first distance above the first surface and a second solder pad at second distance above the first surface, the first distance being different from the second distance; providing a dielectric layer between the first solder pad and the second solder pad; blanket-depositing a metal seed layer over the first solder pad, the second solder pad and the dielectric layer; forming a patterned resist layer over portions of the seed layer that are not to be plated so that the seed layer is exposed over the first solder pad and the second solder pad and around edges of the dielectric layer; plating a first metal layer portion over the first solder pad above a height of the dielectric layer and of the patterned resist layer; and concurrently with plating the first metal layer portion, plating a second metal layer portion over the second solder pad above the height of the dielectric layer and of the patterned resist layer so that the first metal layer portion extends over a portion of the dielectric layer and a portion of the patterned resist layer and the second metal layer portion extends over a portion of the dielectric layer and a portion of the patterned resist layer; planarizing the first metal layer portion and the second metal layer portion so that the step of planarizing planarizes only the material forming the first metal layer portion and the second metal layer portion, resulting in the first metal layer portion and the second metal layer portion having a third and a fourth surface respectively, wherein the third surface and the fourth surface are in the same plane and the planarized first metal layer portion and the planarized second metal layer portion still extend above portions of the patterned resist layer and of the dielectric layer; after the planarizing of the first and second metal layer portions, depositing a first solder layer over the first metal layer portion and depositing a second solder layer over the second metal layer portion, such that a top surface of the first solder layer is in the same plane as a top surface of the second solder layer; and etching away the patterned resist layer and portions of the metal seed layer exposed after etching away the patterned resist layer to electrically isolate the solder layers over each plated metal layer portion. providing an electronic device with a first surface and a second surface opposite the first surface; providing a first solder pad at a first distance above the first surface and a second solder pad at second distance above the first surface, the first distance being different from the second distance; providing a dielectric layer between the first solder pad and the second solder pad; blanket-depositing a metal seed layer over the first solder pad, the second solder pad and the dielectric layer; forming a patterned resist layer over portions of the seed layer that are not to be plated so that the seed layer is exposed over the first solder pad and the second solder pad and around edges of the dielectric layer; plating a first metal layer portion over the first solder pad above a height of the dielectric layer and of the patterned resist layer; and concurrently with plating the first metal layer portion, plating a second metal layer portion over the second solder pad above the height of the dielectric layer and of the patterned resist layer so that the first metal layer portion extends over a portion of the dielectric layer and a portion of the patterned resist layer and the second metal layer portion extends over a portion of the dielectric layer and a portion of the patterned resist layer; planarizing the first metal layer portion and the second metal layer portion so that the step of planarizing planarizes only the material forming the first metal layer portion and the second metal layer portion, resulting in the first metal layer portion and the second metal layer portion having a third and a fourth surface respectively, wherein the third surface and the fourth surface are in the same plane and the planarized first metal layer portion and the planarized second metal layer portion still extend above portions of the patterned resist layer and of the dielectric layer; after the planarizing of the first and second metal layer portions, depositing a first solder layer over the first metal layer portion and depositing a second solder layer over the second metal layer portion, such that a top surface of the first solder layer is in the same plane as a top surface of the second solder layer; and etching away the patterned resist layer and portions of the metal seed layer exposed after etching away the patterned resist layer to electrically isolate the solder layers over each plated metal layer portion.