A digital phase shifter (100, 200) comprising: a plurality of digital phase shift circuit groups (30, 80) in which a plurality of digital phase shift circuits (10, 60) are connected in cascade; one or more relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) provided between two digital phase shift circuit groups (30, 80); and two or more bend-type connection units (20, 70) configured to connect one of the two digital phase shift circuit groups (30, 80) to the relay digital phase shift circuit (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) and connect the other of the two digital phase shift circuit groups to the relay digital phase shift circuit (10-11, 10-22, 10-33, 60-17, 60-27, 60-37), wherein each of the digital phase shift circuits (10, 60) and the relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) includes at least a signal line, a pair of inner lines provided at both sides of the signal line, a pair of outer lines provided outside of the inner lines, a first ground conductor connected to one end of each of the inner lines and the outer lines, a second ground conductor connected to the other end of each of the outer lines, and a pair of electronic switches (7a, 7b) provided between the other ends of the inner lines and the second ground conductor, wherein each of the digital phase shift circuits (10, 60) and the relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) is a circuit set in a low-delay mode in which a return current flows through the inner line or a high-delay mode in which a return current flows through the outer line, and wherein at least one of the digital phase shift circuits (10, 60) constituting at least one digital phase shift circuit group (30, 80) and the relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) is a mitigation circuit, characterized in that the mitigation circuit is configured to mitigate differences of phase shift amounts of the plurality of digital phase shift circuits (10, 60) and the one or more relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) caused by reflections at the two or more bend-type connection units (20, 70). a plurality of digital phase shift circuit groups (30, 80) in which a plurality of digital phase shift circuits (10, 60) are connected in cascade; one or more relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) provided between two digital phase shift circuit groups (30, 80); and two or more bend-type connection units (20, 70) configured to connect one of the two digital phase shift circuit groups (30, 80) to the relay digital phase shift circuit (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) and connect the other of the two digital phase shift circuit groups to the relay digital phase shift circuit (10-11, 10-22, 10-33, 60-17, 60-27, 60-37), wherein each of the digital phase shift circuits (10, 60) and the relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) includes at least a signal line, a pair of inner lines provided at both sides of the signal line, a pair of outer lines provided outside of the inner lines, a first ground conductor connected to one end of each of the inner lines and the outer lines, a second ground conductor connected to the other end of each of the outer lines, and a pair of electronic switches (7a, 7b) provided between the other ends of the inner lines and the second ground conductor, wherein each of the digital phase shift circuits (10, 60) and the relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) is a circuit set in a low-delay mode in which a return current flows through the inner line or a high-delay mode in which a return current flows through the outer line, and wherein at least one of the digital phase shift circuits (10, 60) constituting at least one digital phase shift circuit group (30, 80) and the relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) is a mitigation circuit, characterized in that the mitigation circuit is configured to mitigate differences of phase shift amounts of the plurality of digital phase shift circuits (10, 60) and the one or more relay digital phase shift circuits (10-11, 10-22, 10-33, 60-17, 60-27, 60-37) caused by reflections at the two or more bend-type connection units (20, 70).