A current sampling and holding circuit, comprising: a first P-type MOS transistor, wherein a source of the first P-type MOS transistor is connected to a VDD terminal, and a drain of the first P-type MOS transistor is connected to an output terminal of a current-type sensor via a second switch; a first capacitor, connected between a gate and the source of the first P-type MOS transistor; a first switch, connected between the gate and the drain of the first P-type MOS transistor; and a mirroring circuit, wherein an input node of the mirroring circuit is connected to the output terminal of the current-type sensor via a third switch, and an output node of the mirroring circuit is connected to the drain of the first P-type MOS transistor, wherein the mirroring circuit comprises: a current source (Ib), a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, and a fourth current mirror circuit; wherein an input terminal of the first current mirror circuit is connected to a first terminal of the current source (Ib), an input terminal of the second current mirror circuit is connected to a second terminal of the current source (Ib), an input terminal of the third current mirror circuit and an output terminal of the first current mirror circuit are connected to the input node of the mirroring circuit; an input terminal of the fourth current mirror circuit is connected to an output terminal of the third current mirror circuit, and an output terminal of the fourth current mirror circuit and an output terminal of the second current mirror circuit are connected to the output node of the mirroring circuit, the first current mirror circuit is connected between the first terminal of the current source (Ib) and the VDD terminal, the second current mirror circuit is connected between the second terminal of the current source (Ib) and a ground voltage, the third current mirror circuit is connected between the output terminal of the first current mirror circuit and the ground voltage, and the fourth current mirror circuit is connected between the VDD terminal and the third current mirror circuit, wherein in a sampling stage, the first switch and the third switch are turned on and the second switch is turned off, the mirroring circuit receives an output current of the current-type sensor, and a current flowing through the P-type MOS transistor is a mirror current of the output current of the current-type sensor; and in a holding stage, the first switch and the third switch are turned off and the second switch is turned on, and the P-type MOS transistor holds the mirror current of the output current of the current-type sensor. a first P-type MOS transistor, wherein a source of the first P-type MOS transistor is connected to a VDD terminal, and a drain of the first P-type MOS transistor is connected to an output terminal of a current-type sensor via a second switch; a first capacitor, connected between a gate and the source of the first P-type MOS transistor; a first switch, connected between the gate and the drain of the first P-type MOS transistor; and a mirroring circuit, wherein an input node of the mirroring circuit is connected to the output terminal of the current-type sensor via a third switch, and an output node of the mirroring circuit is connected to the drain of the first P-type MOS transistor, wherein the mirroring circuit comprises: a current source (Ib), a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, and a fourth current mirror circuit; wherein an input terminal of the first current mirror circuit is connected to a first terminal of the current source (Ib), an input terminal of the second current mirror circuit is connected to a second terminal of the current source (Ib), an input terminal of the third current mirror circuit and an output terminal of the first current mirror circuit are connected to the input node of the mirroring circuit; an input terminal of the fourth current mirror circuit is connected to an output terminal of the third current mirror circuit, and an output terminal of the fourth current mirror circuit and an output terminal of the second current mirror circuit are connected to the output node of the mirroring circuit, the first current mirror circuit is connected between the first terminal of the current source (Ib) and the VDD terminal, the second current mirror circuit is connected between the second terminal of the current source (Ib) and a ground voltage, the third current mirror circuit is connected between the output terminal of the first current mirror circuit and the ground voltage, and the fourth current mirror circuit is connected between the VDD terminal and the third current mirror circuit, wherein in a sampling stage, the first switch and the third switch are turned on and the second switch is turned off, the mirroring circuit receives an output current of the current-type sensor, and a current flowing through the P-type MOS transistor is a mirror current of the output current of the current-type sensor; and in a holding stage, the first switch and the third switch are turned off and the second switch is turned on, and the P-type MOS transistor holds the mirror current of the output current of the current-type sensor.