A power supply switching circuit, comprising: a comparator (102, 140) connected to receive and compare first (V sup1) and second (V sup2) power supplies, where the comparator (102, 140) is configured to generate a comparator activation signal (CP_OK_V DD) when the comparator is ready to operate, and is configured to generate a first selection signal (OUT_P) identifying which of the first and second power supplies is higher; and an active voltage switching circuit connected to receive the first and second power supplies and configured to generate therefrom a maximum bias voltage (Vmax) which is the higher of the first and second power supplies ( V SUP1, V SUP2); a gate driver circuit connected to receive the first and second power supplies and configured to generate first and second power supply selection signals only in response to the comparator activation signal by using the first selection signal to generate first and second overlapping phase signals ( PHI_1, PHI_2) which control timing of the first and second power supply selection signals so that a ground voltage is not supplied as the first power supply selection signal at the same time as the second power supply selection signal; first and second PMOS power transistors (MP1, MP2) for connecting the first and second power supplies, respectively, to a power supply output (V OUT) in response to the first or second power supply selection signals provided, respectively, to gate terminals of the first and second PMOS power transistors; and a bias switching circuit (SW2, SW4) connected to bias an n-well of each of the first and second PMOS power transistors (MP1, MP2) to avoid forward biased junction diodes by connecting the n-well (NW1, NW2) of each of the first and second PMOS power transistors to either the maximum bias voltage (V MAX) or one of the first and second power supplies ( V SUP1, V SUP2) in response to the comparator activation signal (CP_OK_V MAX). a comparator (102, 140) connected to receive and compare first (V sup1) and second (V sup2) power supplies, where the comparator (102, 140) is configured to generate a comparator activation signal (CP_OK_V DD) when the comparator is ready to operate, and is configured to generate a first selection signal (OUT_P) identifying which of the first and second power supplies is higher; and an active voltage switching circuit connected to receive the first and second power supplies and configured to generate therefrom a maximum bias voltage (Vmax) which is the higher of the first and second power supplies ( V SUP1, V SUP2); a gate driver circuit connected to receive the first and second power supplies and configured to generate first and second power supply selection signals only in response to the comparator activation signal by using the first selection signal to generate first and second overlapping phase signals ( PHI_1, PHI_2) which control timing of the first and second power supply selection signals so that a ground voltage is not supplied as the first power supply selection signal at the same time as the second power supply selection signal; first and second PMOS power transistors (MP1, MP2) for connecting the first and second power supplies, respectively, to a power supply output (V OUT) in response to the first or second power supply selection signals provided, respectively, to gate terminals of the first and second PMOS power transistors; and a bias switching circuit (SW2, SW4) connected to bias an n-well of each of the first and second PMOS power transistors (MP1, MP2) to avoid forward biased junction diodes by connecting the n-well (NW1, NW2) of each of the first and second PMOS power transistors to either the maximum bias voltage (V MAX) or one of the first and second power supplies ( V SUP1, V SUP2) in response to the comparator activation signal (CP_OK_V MAX).