A semiconductor device comprising: a source region placed on a semiconductor substrate and having both ends (161, 162) made smaller in width than a central part in a plan view; a first channel region and a second channel region placed adjacent to corresponding outer peripheral parts of the source region divided, in the plan view, by the both ends on the semiconductor substrate; a first drain region and a second drain region placed, in the plan view, adjacent to the first channel region and the second channel region, respectively, on the semiconductor substrate; gate electrodes placed on respective surfaces of the first channel region and the second channel region through an insulating film and joined to each other near a first source end that is one of the ends of the source region; a gate wire for transmitting an input signal to the gate electrodes connected to a portion where the gate electrodes are joined; drain electrodes placed on respective surfaces of the first drain region and the second drain region and joined to each other near a second source end that is another of the ends of the source region different from the first source end; and a drain wire for transmitting an output signal from the drain electrodes connected to a portion where the drain electrodes are joined, wherein, in the plan view, at least one of the gate wire or the drain wire is made smaller in width than the central part of the source region; wherein the semiconductor device further comprises: a third channel region placed, in the plan view, adjacent to the first drain region; a second source region placed, in the plan view, adjacent to the third channel region; a second gate electrode placed on a surface of the third channel region through an insulating film and connected to the gate wire; a fourth channel region placed, in the plan view, adjacent to the second drain region; a third source region placed, in the plan view, adjacent to the fourth channel region; and a third gate electrode placed on a surface of the fourth channel region through an insulating film and connected to the gate wire. a source region placed on a semiconductor substrate and having both ends (161, 162) made smaller in width than a central part in a plan view; a first channel region and a second channel region placed adjacent to corresponding outer peripheral parts of the source region divided, in the plan view, by the both ends on the semiconductor substrate; a first drain region and a second drain region placed, in the plan view, adjacent to the first channel region and the second channel region, respectively, on the semiconductor substrate; gate electrodes placed on respective surfaces of the first channel region and the second channel region through an insulating film and joined to each other near a first source end that is one of the ends of the source region; a gate wire for transmitting an input signal to the gate electrodes connected to a portion where the gate electrodes are joined; drain electrodes placed on respective surfaces of the first drain region and the second drain region and joined to each other near a second source end that is another of the ends of the source region different from the first source end; and a drain wire for transmitting an output signal from the drain electrodes connected to a portion where the drain electrodes are joined, wherein, in the plan view, at least one of the gate wire or the drain wire is made smaller in width than the central part of the source region; wherein the semiconductor device further comprises: a third channel region placed, in the plan view, adjacent to the first drain region; a second source region placed, in the plan view, adjacent to the third channel region; a second gate electrode placed on a surface of the third channel region through an insulating film and connected to the gate wire; a fourth channel region placed, in the plan view, adjacent to the second drain region; a third source region placed, in the plan view, adjacent to the fourth channel region; and a third gate electrode placed on a surface of the fourth channel region through an insulating film and connected to the gate wire. a third channel region placed, in the plan view, adjacent to the first drain region; a second source region placed, in the plan view, adjacent to the third channel region; a second gate electrode placed on a surface of the third channel region through an insulating film and connected to the gate wire; a fourth channel region placed, in the plan view, adjacent to the second drain region; a third source region placed, in the plan view, adjacent to the fourth channel region; and a third gate electrode placed on a surface of the fourth channel region through an insulating film and connected to the gate wire.