A semiconductor device, comprising: a transimpedance amplifier, TIA, formed in a semiconductor die, wherein a pair of openings is formed through a top insulating layer of the TIA to expose a contact pad; an avalanche photodiode, APD, disposed on the TIA over the contact pad; a build-up interconnect structure including an integrated high voltage capacitor (40; 40a-40f) formed over the semiconductor die, wherein the integrated high voltage capacitor includes: a first bus bar (90b, 68a), a first plurality of fingers (92b, 68a) extending from the first bus bar, a second bus bar (90a, 68a), a second plurality of fingers (92a, 68a) extending from the second bus bar, wherein the second plurality of fingers is interleaved with the first plurality of fingers within a first conductive layer of the build-up interconnect structure, a third bus bar (90b, 68b) formed over the first bus bar, a third plurality of fingers (92b, 68a) extending from the third bus bar, wherein each finger of the third plurality of fingers is aligned directly over a respective finger of the first plurality of fingers, a fourth bus bar (90a, 68b) formed over the second bus bar, a fourth plurality of fingers (92a, 68b) extending from the fourth bus bar, wherein each finger of the fourth plurality of fingers is aligned directly over a respective finger of the second plurality of fingers, a first conductive via extending from the first bus bar to the third bus bar, and a second conductive via extending from the second bus bar to the fourth bus bar; wherein the contact pad is a direct extension from a top bus bar of the integrated high voltage capacitor; and a high voltage input coupled to the integrated high voltage capacitor. a transimpedance amplifier, TIA, formed in a semiconductor die, wherein a pair of openings is formed through a top insulating layer of the TIA to expose a contact pad; an avalanche photodiode, APD, disposed on the TIA over the contact pad; a build-up interconnect structure including an integrated high voltage capacitor (40; 40a-40f) formed over the semiconductor die, wherein the integrated high voltage capacitor includes: a first bus bar (90b, 68a), a first plurality of fingers (92b, 68a) extending from the first bus bar, a second bus bar (90a, 68a), a second plurality of fingers (92a, 68a) extending from the second bus bar, wherein the second plurality of fingers is interleaved with the first plurality of fingers within a first conductive layer of the build-up interconnect structure, a third bus bar (90b, 68b) formed over the first bus bar, a third plurality of fingers (92b, 68a) extending from the third bus bar, wherein each finger of the third plurality of fingers is aligned directly over a respective finger of the first plurality of fingers, a fourth bus bar (90a, 68b) formed over the second bus bar, a fourth plurality of fingers (92a, 68b) extending from the fourth bus bar, wherein each finger of the fourth plurality of fingers is aligned directly over a respective finger of the second plurality of fingers, a first conductive via extending from the first bus bar to the third bus bar, and a second conductive via extending from the second bus bar to the fourth bus bar; wherein the contact pad is a direct extension from a top bus bar of the integrated high voltage capacitor; and a first bus bar (90b, 68a), a first plurality of fingers (92b, 68a) extending from the first bus bar, a second bus bar (90a, 68a), a second plurality of fingers (92a, 68a) extending from the second bus bar, wherein the second plurality of fingers is interleaved with the first plurality of fingers within a first conductive layer of the build-up interconnect structure, a third bus bar (90b, 68b) formed over the first bus bar, a third plurality of fingers (92b, 68a) extending from the third bus bar, wherein each finger of the third plurality of fingers is aligned directly over a respective finger of the first plurality of fingers, a fourth bus bar (90a, 68b) formed over the second bus bar, a fourth plurality of fingers (92a, 68b) extending from the fourth bus bar, wherein each finger of the fourth plurality of fingers is aligned directly over a respective finger of the second plurality of fingers, a first conductive via extending from the first bus bar to the third bus bar, and a second conductive via extending from the second bus bar to the fourth bus bar; wherein the contact pad is a direct extension from a top bus bar of the integrated high voltage capacitor; and a high voltage input coupled to the integrated high voltage capacitor.