A phase change memory, PCM, the PCM comprising: - a PCM array, wherein the PCM array comprises a plurality of rows of PCM cells (E(x,y)), wherein each of the rows of PCM cells comprises a plurality of PCM cells (C(1,1), C(1,2)..., C(3,3)), and wherein each PCM cell (C(1,1)) comprises: - a PCM element (E(1,1)) configured to store a value; and - a selection transistor (SD(1,1)) connected to the PCM element and used to select the PCM element, the gate of the selection transistor being connected to a corresponding word line (WORD LINE #1) of a plurality of word lines; - a plurality of word line driver circuits (104-1, 104-2, 104-3) connected to the rows of PCM cells, wherein each of the word line driver circuits is used to access one of the rows of PCM cells by driving the corresponding word line; - a plurality of bit line driver circuits (106-1, 106-2, 106-3) connected to the rows of PCM cells and an electrical ground, wherein each of the bit line driver circuits is connected to a PCM cell in each of the rows of PCM cells through a bit line, and wherein each of the bit line driver circuits comprises: - a p-channel metal oxide semiconductor, PMOS, transistor connected to a voltage supply circuit and a corresponding bit line for pre-charging the corresponding bit line; and - an n-channel metal oxide semiconductor, NMOS, transistor connected to the electrical ground and the corresponding bit line for control of the corresponding bit line current; - a source driver circuit (108, 808-1, 808-2, 808-3) connected to source lines, wherein in each of the PCM cells, the corresponding PCM element and the corresponding selection transistor are connected in series between a corresponding bit line and a corresponding source line; and - the voltage supply circuit being connected to the word line driver circuits, the bit line driver circuits and the source driver circuit, characterized in that the PCM includes further a write control circuit configured to, during a RESET write operation changing a selected PCM memory element from a low to a high resistance state and during a SET write operation changing a selected PCM memory element from a high to a low resistance state, put the selected corresponding word line and the selected corresponding source line at a same write voltage (Vreset), this write voltage being supplied by the voltage supply circuit and to pre-charge the selected corresponding bit line to said write voltage (Vreset) before pulling it down toward the electrical ground in order to perform the write operation during which the current flowing through said selected corresponding bit line is controlled by the corresponding bit line driver circuit. - a PCM array, wherein the PCM array comprises a plurality of rows of PCM cells (E(x,y)), wherein each of the rows of PCM cells comprises a plurality of PCM cells (C(1,1), C(1,2)..., C(3,3)), and wherein each PCM cell (C(1,1)) comprises: - a PCM element (E(1,1)) configured to store a value; and - a selection transistor (SD(1,1)) connected to the PCM element and used to select the PCM element, the gate of the selection transistor being connected to a corresponding word line (WORD LINE #1) of a plurality of word lines; - a PCM element (E(1,1)) configured to store a value; and - a selection transistor (SD(1,1)) connected to the PCM element and used to select the PCM element, the gate of the selection transistor being connected to a corresponding word line (WORD LINE #1) of a plurality of word lines; - a plurality of word line driver circuits (104-1, 104-2, 104-3) connected to the rows of PCM cells, wherein each of the word line driver circuits is used to access one of the rows of PCM cells by driving the corresponding word line; - a plurality of bit line driver circuits (106-1, 106-2, 106-3) connected to the rows of PCM cells and an electrical ground, wherein each of the bit line driver circuits is connected to a PCM cell in each of the rows of PCM cells through a bit line, and wherein each of the bit line driver circuits comprises: - a p-channel metal oxide semiconductor, PMOS, transistor connected to a voltage supply circuit and a corresponding bit line for pre-charging the corresponding bit line; and - an n-channel metal oxide semiconductor, NMOS, transistor connected to the electrical ground and the corresponding bit line for control of the corresponding bit line current; - a p-channel metal oxide semiconductor, PMOS, transistor connected to a voltage supply circuit and a corresponding bit line for pre-charging the corresponding bit line; and - an n-channel metal oxide semiconductor, NMOS, transistor connected to the electrical ground and the corresponding bit line for control of the corresponding bit line current; - a source driver circuit (108, 808-1, 808-2, 808-3) connected to source lines, wherein in each of the PCM cells, the corresponding PCM element and the corresponding selection transistor are connected in series between a corresponding bit line and a corresponding source line; and - the voltage supply circuit being connected to the word line driver circuits, the bit line driver circuits and the source driver circuit,