A processor implemented method, comprising: accessing, via one or more hardware processors, a field programmable gate arrays (FPGA) pipeline comprising a PCI express-AXI bridge, a control block, a trained Model, a tree architecture auto generation model, wherein the trained model is trained on a first set of features, and wherein the first set of features are identified based on a plurality of features extracted from an original training dataset and a second set of features unused during a previous training; receiving the first set of features from a host server to the FPGA via the PCIe express to AXI bridge, via the one or more hardware processors; autogenerating, by the tree architecture auto generation model, one of a single XGboost models and multi-parallel XGB models based on a user input, wherein each XGB model comprises a plurality of XGB trees for processing the first set of features in parallel, and each XGB tree outputs an inference value based on the processing, wherein the each XGB tree receives a first input from the trained model and a second input from the host server via the PCI express-AXI bridge, and wherein the trained model comprises a plurality of values associated with the training data to be consumed by the plurality of XGB trees, and wherein the trained model comprises a hard-coded model wherein the plurality of values are generated by connecting a wire with one of V CC terminal and a ground terminal; determining, by the control block, a number of XGB models required for processing the first set of features based on a count of a set of PCIe connections associated with width of the PCI express-AXI bridge and a count of a set of XGB input connections available with each of the XGB models, via the one or more hardware processors; selectively activating, in each clock cycle from amongst a plurality of clock cycles, one or more XGB input connections from amongst a set of XGB input connections available at the determined number of XGB models based on a number of current clock cycle from amongst the plurality of clock cycles, via the one or more hardware processors, wherein selectively activating the one or more XGB input connections at the determined number of XGB models in each clock cycle results in one or more unused XGB input connections from one or more previous clock cycles; and utilizing, via the one or more hardware processors, the one or more unused XGB input connections for the processing in one or more subsequent clock cycles. accessing, via one or more hardware processors, a field programmable gate arrays (FPGA) pipeline comprising a PCI express-AXI bridge, a control block, a trained Model, a tree architecture auto generation model, wherein the trained model is trained on a first set of features, and wherein the first set of features are identified based on a plurality of features extracted from an original training dataset and a second set of features unused during a previous training; receiving the first set of features from a host server to the FPGA via the PCIe express to AXI bridge, via the one or more hardware processors; autogenerating, by the tree architecture auto generation model, one of a single XGboost models and multi-parallel XGB models based on a user input, wherein each XGB model comprises a plurality of XGB trees for processing the first set of features in parallel, and each XGB tree outputs an inference value based on the processing, wherein the each XGB tree receives a first input from the trained model and a second input from the host server via the PCI express-AXI bridge, and wherein the trained model comprises a plurality of values associated with the training data to be consumed by the plurality of XGB trees, and wherein the trained model comprises a hard-coded model wherein the plurality of values are generated by connecting a wire with one of V CC terminal and a ground terminal; determining, by the control block, a number of XGB models required for processing the first set of features based on a count of a set of PCIe connections associated with width of the PCI express-AXI bridge and a count of a set of XGB input connections available with each of the XGB models, via the one or more hardware processors; selectively activating, in each clock cycle from amongst a plurality of clock cycles, one or more XGB input connections from amongst a set of XGB input connections available at the determined number of XGB models based on a number of current clock cycle from amongst the plurality of clock cycles, via the one or more hardware processors, wherein selectively activating the one or more XGB input connections at the determined number of XGB models in each clock cycle results in one or more unused XGB input connections from one or more previous clock cycles; and utilizing, via the one or more hardware processors, the one or more unused XGB input connections for the processing in one or more subsequent clock cycles.