A printed circuit board for a semiconductor package, comprising: a first substrate having a first mounting area for mounting a package substrate and a second mounting area for mounting a semiconductor element, said first substrate comprising an external insulating layer and an outer circuit layer; a single layer or multi-layered circuit pattern of the first substrate; and a post bump (30; 301) connected to the circuit pattern and having an upper surface with a concave portion in a circular arc shape for receiving a solder bump having an ellipsoidal shape, and having a lower surface connected to the outer circuit layer provided on the external insulating layer of the first mounting area, wherein the printed circuit board further comprises a solder resist provided on the external insulating layer and on the outer circuit layer, wherein the solder resist comprises an opening through which is provided the lower surface of the post bump (30, 301), wherein a part of the solder resist is partially inserted into a space between the outer circuit layer and the post bump (30, 301), wherein the post bump (30, 301) is characterised by: a first portion on the outer circuit layer and filled in the opening of the solder resist; and a second portion on the first portion and protruding from an upper surface of the solder resist, the second portion having said upper surface of the post bump in a circular arc shape, wherein the second portion of the post bump has a height of 50 to 400 μm, and the upper surface of the second portion has a maximum depth of 20 μm, wherein a radius of the upper surface of the second portion is 20 to 100 μm, wherein the upper surface of the second portion has a curvature of 1 to 0.01 μm -1 and wherein a width of the second portion of the post bump is narrower than a diameter of the solder bump. a first substrate having a first mounting area for mounting a package substrate and a second mounting area for mounting a semiconductor element, said first substrate comprising an external insulating layer and an outer circuit layer; a single layer or multi-layered circuit pattern of the first substrate; and a post bump (30; 301) connected to the circuit pattern and having an upper surface with a concave portion in a circular arc shape for receiving a solder bump having an ellipsoidal shape, and having a lower surface connected to the outer circuit layer provided on the external insulating layer of the first mounting area, wherein the printed circuit board further comprises a solder resist provided on the external insulating layer and on the outer circuit layer, wherein the solder resist comprises an opening through which is provided the lower surface of the post bump (30, 301), wherein a part of the solder resist is partially inserted into a space between the outer circuit layer and the post bump (30, 301), wherein the post bump (30, 301) is characterised by: a first portion on the outer circuit layer and filled in the opening of the solder resist; and a second portion on the first portion and protruding from an upper surface of the solder resist, the second portion having said upper surface of the post bump in a circular arc shape, wherein the second portion of the post bump has a height of 50 to 400 μm, and the upper surface of the second portion has a maximum depth of 20 μm, wherein a radius of the upper surface of the second portion is 20 to 100 μm, wherein the upper surface of the second portion has a curvature of 1 to 0.01 μm -1 and wherein a width of the second portion of the post bump is narrower than a diameter of the solder bump. a first portion on the outer circuit layer and filled in the opening of the solder resist; and a second portion on the first portion and protruding from an upper surface of the solder resist, the second portion having said upper surface of the post bump in a circular arc shape, wherein the second portion of the post bump has a height of 50 to 400 μm, and the upper surface of the second portion has a maximum depth of 20 μm, wherein a radius of the upper surface of the second portion is 20 to 100 μm, wherein the upper surface of the second portion has a curvature of 1 to 0.01 μm -1 and wherein a width of the second portion of the post bump is narrower than a diameter of the solder bump.