A programmable logic device, comprising: a plurality of logic elements (LE's) arranged in an array; a plurality of signal routing lines to route signals among the logic elements; a first hole (302; 402) formed in the array of logic elements such that at least some of the plurality of logic elements are provided around the hole (302; 402), wherein at least one of the plurality of signal routing lines is interrupted at the first hole (302; 402); and the programmable logic device further comprises: interface circuitry (304; 408; 504; 604; 1008) at a location within the first hole (302; 402) adjacent to at least one of the plurality of logic elements which surround the first hole (302; 402), configurable to couple circuitry within the first hole (302; 402) to at least one of the plurality of signal routing lines, wherein the interface circuitry (304; 408; 504; 604; 1008) is configurable to maintain signal routing continuity even though at least some of the signal routing lines are interrupted at the first hole (302; 402) and wherein the first hole (302; 402) is surrounded by the plurality of signal routing lines on at least two sides; and an IP function block partially within the first hole (302; 402), the IP function block being electrically coupled to the interface circuitry (304; 408; 504; 604; 1008), wherein a portion of the logic elements and a portion of the signal routing lines are replaced by the interface circuitry (304; 408; 504; 604; 1008) and the IP function block, characterized by a plurality of I/O pads, wherein a portion of the I/O pads is displaced by at least a portion of the IP function block. a plurality of logic elements (LE's) arranged in an array; a plurality of signal routing lines to route signals among the logic elements; a first hole (302; 402) formed in the array of logic elements such that at least some of the plurality of logic elements are provided around the hole (302; 402), wherein at least one of the plurality of signal routing lines is interrupted at the first hole (302; 402); and the programmable logic device further comprises: interface circuitry (304; 408; 504; 604; 1008) at a location within the first hole (302; 402) adjacent to at least one of the plurality of logic elements which surround the first hole (302; 402), configurable to couple circuitry within the first hole (302; 402) to at least one of the plurality of signal routing lines, wherein the interface circuitry (304; 408; 504; 604; 1008) is configurable to maintain signal routing continuity even though at least some of the signal routing lines are interrupted at the first hole (302; 402) and wherein the first hole (302; 402) is surrounded by the plurality of signal routing lines on at least two sides; and an IP function block partially within the first hole (302; 402), the IP function block being electrically coupled to the interface circuitry (304; 408; 504; 604; 1008), wherein a portion of the logic elements and a portion of the signal routing lines are replaced by the interface circuitry (304; 408; 504; 604; 1008) and the IP function block, characterized by interface circuitry (304; 408; 504; 604; 1008) at a location within the first hole (302; 402) adjacent to at least one of the plurality of logic elements which surround the first hole (302; 402), configurable to couple circuitry within the first hole (302; 402) to at least one of the plurality of signal routing lines, wherein the interface circuitry (304; 408; 504; 604; 1008) is configurable to maintain signal routing continuity even though at least some of the signal routing lines are interrupted at the first hole (302; 402) and wherein the first hole (302; 402) is surrounded by the plurality of signal routing lines on at least two sides; and an IP function block partially within the first hole (302; 402), the IP function block being electrically coupled to the interface circuitry (304; 408; 504; 604; 1008), wherein a portion of the logic elements and a portion of the signal routing lines are replaced by the interface circuitry (304; 408; 504; 604; 1008) and the IP function block, a plurality of I/O pads, wherein a portion of the I/O pads is displaced by at least a portion of the IP function block.