An apparatus for coding video information, the apparatus comprising: a memory configured to store video information associated with an enhancement layer and a corresponding reference layer; and a processor operationally coupled to the memory and configured to: code an EL picture in a current access unit, the EL coded using H.265/HEVC video coding standard and the RL coded using H.264/ AVC video coding standard, wherein the coding of the EL picture is based on information associated with a RL picture in the current access unit; and receive the information associated with the RL picture from an entity external to the processor configured to code the EL picture in the current AU, the information consisting of: decoded sample values of the RL picture; a representation format of the RL picture; and an indication of whether the RL picture is an instantaneous decoding refresh picture, wherein: the processor is further configured to not output the decoded sample values of the RL picture; the memory includes a decoded picture buffer and the processor is further configured to store the decoded sample values of the RL picture in a decoded picture store that is not a part of the decoded picture buffer used for storing the EL; the processor is further configured to obtain from the external entity information relating to an access unit to which the RL picture belongs: the processor is further configured to set a layer identifier of the RL picture equal to a layer identifier of the EL picture or to 0. the processor is further configured to set a picture order count of the RL picture equal to a POC of the EL picture; the processor is further configured to mark the RL picture as a long-term reference picture; the memory includes a coded picture buffer and the processor is further configured to set the RL to have 0 bits in CPB operations; and. the processor is further configured to not refer to the decoded sample values of the RL picture in DPB operations for the EL. a memory configured to store video information associated with an enhancement layer and a corresponding reference layer; and a processor operationally coupled to the memory and configured to: code an EL picture in a current access unit, the EL coded using H.265/HEVC video coding standard and the RL coded using H.264/ AVC video coding standard, wherein the coding of the EL picture is based on information associated with a RL picture in the current access unit; and receive the information associated with the RL picture from an entity external to the processor configured to code the EL picture in the current AU, the information consisting of: decoded sample values of the RL picture; a representation format of the RL picture; and an indication of whether the RL picture is an instantaneous decoding refresh picture, code an EL picture in a current access unit, the EL coded using H.265/HEVC video coding standard and the RL coded using H.264/ AVC video coding standard, wherein the coding of the EL picture is based on information associated with a RL picture in the current access unit; and receive the information associated with the RL picture from an entity external to the processor configured to code the EL picture in the current AU, the information consisting of: decoded sample values of the RL picture; a representation format of the RL picture; and an indication of whether the RL picture is an instantaneous decoding refresh picture, decoded sample values of the RL picture; a representation format of the RL picture; and an indication of whether the RL picture is an instantaneous decoding refresh picture, the processor is further configured to not output the decoded sample values of the RL picture; the memory includes a decoded picture buffer and the processor is further configured to store the decoded sample values of the RL picture in a decoded picture store that is not a part of the decoded picture buffer used for storing the EL; the processor is further configured to obtain from the external entity information relating to an access unit to which the RL picture belongs: the processor is further configured to set a layer identifier of the RL picture equal to a layer identifier of the EL picture or to 0. the processor is further configured to set a picture order count of the RL picture equal to a POC of the EL picture; the processor is further configured to mark the RL picture as a long-term reference picture; the memory includes a coded picture buffer and the processor is further configured to set the RL to have 0 bits in CPB operations; and. the processor is further configured to not refer to the decoded sample values of the RL picture in DPB operations for the EL. the processor is further configured to set a layer identifier of the RL picture equal to a layer identifier of the EL picture or to 0. the processor is further configured to set a picture order count of the RL picture equal to a POC of the EL picture; the processor is further configured to mark the RL picture as a long-term reference picture; the memory includes a coded picture buffer and the processor is further configured to set the RL to have 0 bits in CPB operations; and. the processor is further configured to not refer to the decoded sample values of the RL picture in DPB operations for the EL.