A flip-flop circuit comprising: a first single-input tri-state inverter for receiving an input D; a first dual-input inverter; first and second single-event transient, SET, filters (24, 25); a first dual-input tri-state inverter including a first input that receives output signals from said first dual-input inverter, a second input that receives output signals from first said dual-input inverter via said first SET filter, and an output that sends output signals to a first input of said first dual-input inverter and to a second input of said first dual-input inverter via said second SET filter; a second single-input tri-state inverter that receives an output from said first dual-input inverter; a second dual-input inverter; third and fourth SET filters (29, 30); and a second dual-input tri-state inverter including a first input that receives output signals from said second dual-input inverter, a second input that receives output signals from said second dual-input inverter via said third SET filter, and an output that sends output signals to a first input of said second dual-input inverter and to a second input of said second dual-input inverter via said fourth SET filter, wherein said second dual-input inverter provides an output Q for said flip-flop circuit wherein: the dual-input inverters each have an output that only changes state when signals at both inputs of the inverter are the same; the first single-input tri-state inverter sends output signals directly to the first input of said first dual-input inverter and to the second input of said first dual-input inverter via said second SET filter; and the second single-input tri-state inverter sends output signals directly to the first input of said second dual-input inverter and to the second input of said second dual-input inverter via said fourth SET filter. a first single-input tri-state inverter for receiving an input D; a first dual-input inverter; first and second single-event transient, SET, filters (24, 25); a first dual-input tri-state inverter including a first input that receives output signals from said first dual-input inverter, a second input that receives output signals from first said dual-input inverter via said first SET filter, and an output that sends output signals to a first input of said first dual-input inverter and to a second input of said first dual-input inverter via said second SET filter; a second single-input tri-state inverter that receives an output from said first dual-input inverter; a second dual-input inverter; third and fourth SET filters (29, 30); and a second dual-input tri-state inverter including a first input that receives output signals from said second dual-input inverter, a second input that receives output signals from said second dual-input inverter via said third SET filter, and an output that sends output signals to a first input of said second dual-input inverter and to a second input of said second dual-input inverter via said fourth SET filter, wherein said second dual-input inverter provides an output Q for said flip-flop circuit wherein: the dual-input inverters each have an output that only changes state when signals at both inputs of the inverter are the same; the first single-input tri-state inverter sends output signals directly to the first input of said first dual-input inverter and to the second input of said first dual-input inverter via said second SET filter; and the second single-input tri-state inverter sends output signals directly to the first input of said second dual-input inverter and to the second input of said second dual-input inverter via said fourth SET filter. the dual-input inverters each have an output that only changes state when signals at both inputs of the inverter are the same; the first single-input tri-state inverter sends output signals directly to the first input of said first dual-input inverter and to the second input of said first dual-input inverter via said second SET filter; and the second single-input tri-state inverter sends output signals directly to the first input of said second dual-input inverter and to the second input of said second dual-input inverter via said fourth SET filter.