A wireless receiving apparatus, comprising: a wireless receiver (402, 602) adapted for demodulating a received wireless signal to an analog signal; a sync detector (406, 606) adapted for extracting a sync signal from the analog signal; a clock generating section (408, 608) including a PLL section (410, 610) and the PLL section (410, 610) being adapted for generating a reference clock based on the sync signal; an analog to digital, AD, converter (416, 616) adapted for converting the analog signal to a digital data and for outputting the digital data as a data segment based on the reference clock, the data segment including a data symbol and a sync symbol, and a level of the sync symbol and a level of the data symbol being designated to be different from each other; a buffer (420, 620); and an inverse symbol mapper (422, 622); characterized in that the clock generating section (408, 608) further comprises a clock divider (412, 612) adapted for generating the write clock and the read clock by dividing the reference clock, and for providing the read clock to the buffer (420, 620); and a clock gate section (414, 614) adapted for providing the write clock to the buffer (420, 620) when an output level of the Analog to Digital converter (416, 616) corresponds to the level of the data symbol, and for not providing the write clock to the buffer (420, 620) when the output level of the Analog to Digital converter (416, 616) corresponds to the level of the sync symbol; the buffer (420, 620) is adapted for having written therein the data symbol in accordance with the write clock, and for having read therefrom the written data symbol in accordance with the read clock; and the inverse symbol mapper (422, 622) is adapted for inverse-symbol-mapping the read data symbol onto multibit digital data in accordance with a predetermined mapping table, when the read clock is provided; wherein a clock rate of the read clock is lower than a clock rate of the write clock. a wireless receiver (402, 602) adapted for demodulating a received wireless signal to an analog signal; a sync detector (406, 606) adapted for extracting a sync signal from the analog signal; a clock generating section (408, 608) including a PLL section (410, 610) and the PLL section (410, 610) being adapted for generating a reference clock based on the sync signal; an analog to digital, AD, converter (416, 616) adapted for converting the analog signal to a digital data and for outputting the digital data as a data segment based on the reference clock, the data segment including a data symbol and a sync symbol, and a level of the sync symbol and a level of the data symbol being designated to be different from each other; a buffer (420, 620); and an inverse symbol mapper (422, 622); characterized in that the clock generating section (408, 608) further comprises a clock divider (412, 612) adapted for generating the write clock and the read clock by dividing the reference clock, and for providing the read clock to the buffer (420, 620); and a clock gate section (414, 614) adapted for providing the write clock to the buffer (420, 620) when an output level of the Analog to Digital converter (416, 616) corresponds to the level of the data symbol, and for not providing the write clock to the buffer (420, 620) when the output level of the Analog to Digital converter (416, 616) corresponds to the level of the sync symbol; the buffer (420, 620) is adapted for having written therein the data symbol in accordance with the write clock, and for having read therefrom the written data symbol in accordance with the read clock; and the inverse symbol mapper (422, 622) is adapted for inverse-symbol-mapping the read data symbol onto multibit digital data in accordance with a predetermined mapping table, when the read clock is provided; wherein a clock rate of the read clock is lower than a clock rate of the write clock.