An electronic device configured for coupling to a communication bus to receive therefrom digital signals arranged in frames comprising frames encoded according to a certain communication protocol, the electronic device being configured to receive a number j of frames during a monitoring time interval, the electronic device comprising: a check circuit sensitive to said digital signals arranged in frames, the check circuit configured to perform a check (203, 204, 205) as to whether a received frame is encoded according to said communication protocol and is addressed to the electronic device, a frame counter circuit configured to produce a frame count value which is a function of a number of frames received during said monitoring time interval, the frame counter circuit coupled to said check circuit and configured to increase said frame count value as a result of a positive outcome of said check (203, 204, 205), a comparator circuit configured to: compare said frame count value against a first frame count threshold value and, as a result of said frame count value being equal to said first frame count threshold value, set a frame counter status bit to a first value indicative of a normal operating status of the electronic device, and compare said frame count value against a second frame count threshold value different from said first frame count threshold value and, as a result of said frame count value being equal to said second frame count threshold value, set said frame counter status bit to a second value indicative of an abnormal operating status of the electronic device, a controller circuit configured to transmit over the communication bus a frame comprising said frame counter status bit and to reset said frame count value at the end of said monitoring time interval, wherein the frame counter circuit comprises a modular arithmetic counter circuit having a non-zero bit depth equal to or lower than the integer part of log 2 ( j), and wherein said frame count value is constrained to a modulus value of said modular arithmetic counter circuit. a check circuit sensitive to said digital signals arranged in frames, the check circuit configured to perform a check (203, 204, 205) as to whether a received frame is encoded according to said communication protocol and is addressed to the electronic device, a frame counter circuit configured to produce a frame count value which is a function of a number of frames received during said monitoring time interval, the frame counter circuit coupled to said check circuit and configured to increase said frame count value as a result of a positive outcome of said check (203, 204, 205), a comparator circuit configured to: compare said frame count value against a first frame count threshold value and, as a result of said frame count value being equal to said first frame count threshold value, set a frame counter status bit to a first value indicative of a normal operating status of the electronic device, and compare said frame count value against a second frame count threshold value different from said first frame count threshold value and, as a result of said frame count value being equal to said second frame count threshold value, set said frame counter status bit to a second value indicative of an abnormal operating status of the electronic device, compare said frame count value against a first frame count threshold value and, as a result of said frame count value being equal to said first frame count threshold value, set a frame counter status bit to a first value indicative of a normal operating status of the electronic device, and compare said frame count value against a second frame count threshold value different from said first frame count threshold value and, as a result of said frame count value being equal to said second frame count threshold value, set said frame counter status bit to a second value indicative of an abnormal operating status of the electronic device, a controller circuit configured to transmit over the communication bus a frame comprising said frame counter status bit and to reset said frame count value at the end of said monitoring time interval, wherein the frame counter circuit comprises a modular arithmetic counter circuit having a non-zero bit depth equal to or lower than the integer part of log 2 ( j), and wherein said frame count value is constrained to a modulus value of said modular arithmetic counter circuit.