A hold-time optimization circuit, comprising: a delay control circuit, delaying a clock signal for a delay time so as to generate a delay clock signal, wherein the delay time is adjusted according to a correction pulse signal; and a correction circuit, generating the correction pulse signal according to transition edges of a data signal and transition edges of the delay clock signal, wherein the data signal is sampled by a flip-flop according to the delay clock signal, the data signal comprises a bit, and the correction circuit comprises a glitch generation circuit, and the glitch generation circuit comprises: a rising-edge detector, generating a first detection signal according to rising edges of the bit; a falling-edge detector, generating a second detection signal according to falling edges of the bit; a first AND gate, wherein the first AND gate has a first input terminal for receiving the first detection signal, a second input terminal for receiving the delay clock signal, and an output terminal; a second AND gate, wherein the second AND gate has a first input terminal for receiving the second detection signal, a second input terminal for receiving the delay clock signal, and an output terminal; and a first OR gate, wherein the first OR gate has a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, and an output terminal for outputting the correction pulse signal. a delay control circuit, delaying a clock signal for a delay time so as to generate a delay clock signal, wherein the delay time is adjusted according to a correction pulse signal; and a correction circuit, generating the correction pulse signal according to transition edges of a data signal and transition edges of the delay clock signal, wherein the data signal is sampled by a flip-flop according to the delay clock signal, the data signal comprises a bit, and the correction circuit comprises a glitch generation circuit, and the glitch generation circuit comprises: a rising-edge detector, generating a first detection signal according to rising edges of the bit; a falling-edge detector, generating a second detection signal according to falling edges of the bit; a first AND gate, wherein the first AND gate has a first input terminal for receiving the first detection signal, a second input terminal for receiving the delay clock signal, and an output terminal; a second AND gate, wherein the second AND gate has a first input terminal for receiving the second detection signal, a second input terminal for receiving the delay clock signal, and an output terminal; and a first OR gate, wherein the first OR gate has a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, and an output terminal for outputting the correction pulse signal. a rising-edge detector, generating a first detection signal according to rising edges of the bit; a falling-edge detector, generating a second detection signal according to falling edges of the bit; a first AND gate, wherein the first AND gate has a first input terminal for receiving the first detection signal, a second input terminal for receiving the delay clock signal, and an output terminal; a second AND gate, wherein the second AND gate has a first input terminal for receiving the second detection signal, a second input terminal for receiving the delay clock signal, and an output terminal; and a first OR gate, wherein the first OR gate has a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, and an output terminal for outputting the correction pulse signal.