A semiconductor device, comprising: a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, the semiconductor structure further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, the trench also disposed in the bottom barrier layer and completely surrounding the channel region; and a gate stack disposed in the trench and on the channel region, the gate stack comprising a stack of a first dielectric layer, a second dielectric layer and a gate electrode; wherein the first dielectric layer is conformal with the trench, disposed on outer portions, but not an inner portion, of the channel region and completely surrounds said outer portions of the channel region, the outer portions and the inner portion of the channel region being defined as taken along a channel length from the source region to the drain region; wherein the first and second dielectric layers are different and the second dielectric layer is conformal with the first dielectric layer, disposed on the first dielectric layer and on the inner portion of the channel region, and completely surrounds the inner portion of the channel region; and wherein the gate electrode is disposed on the second dielectric layer, partly overlaps the first dielectric material on said outer portions of the channel region, and completely surrounds said inner portion of the channel region. a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, the semiconductor structure further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body; a source and drain material region disposed above the three-dimensional group III-V material body; a trench disposed in the source and drain material region separating a source region from a drain region, the trench also disposed in the bottom barrier layer and completely surrounding the channel region; and a gate stack disposed in the trench and on the channel region, the gate stack comprising a stack of a first dielectric layer, a second dielectric layer and a gate electrode; wherein the first dielectric layer is conformal with the trench, disposed on outer portions, but not an inner portion, of the channel region and completely surrounds said outer portions of the channel region, the outer portions and the inner portion of the channel region being defined as taken along a channel length from the source region to the drain region; wherein the first and second dielectric layers are different and the second dielectric layer is conformal with the first dielectric layer, disposed on the first dielectric layer and on the inner portion of the channel region, and completely surrounds the inner portion of the channel region; and wherein the gate electrode is disposed on the second dielectric layer, partly overlaps the first dielectric material on said outer portions of the channel region, and completely surrounds said inner portion of the channel region.