A processing system comprising: - a digital processing unit programmable as a function of a firmware stored to a non-volatile memory; - a first resource (106; ADC) and a second resource (106; IF1) connected to said digital processing unit via a communication system, wherein said first resource (106; ADC) comprises a first register and said second resource (106; IF1) comprises a second register; - a time reference circuit comprising a first digital counter circuit configured to generate, in response to a clock signal, a system time signal comprising a plurality of bits indicative of a time tick-count; characterized in that said processing system comprises a first and a second time base distribution circuit configured to generate a first time base signal and a second time base signal by selecting a respective subset of the bits of said system time signal, wherein said first time base signal is provided to said first resource (106; ADC) and said second time base signal is provided to said second resource (106; IF1), wherein said first and said second time base distribution circuit are configured to generate said first time base signal and said second time base signal, respectively, by selecting: - a respective first subset of a respective given number of bits of said system time signal when a respective selection signal (CSEL) has a first value; and - a respective second subset of the respective given number of bits of said system time signal when the respective selection signal (CSEL) has a second value, whereby a time resolution of the respective time base signal varies as a function of the respective selection signal ( CSEL); wherein each of said first resource (106; ADC) and said second resource (106; IF1) is configured to: - detect a respective given event, - store the respective time base signal ( TBI1, TBI2) to the respective register (REG1, REG2) in response to the respective event, and - signal the respective event to said digital processing unit; and wherein said digital processing unit is adapted to read via said communication system: - in response to an event having been signaled by said first resource (106; ADC), said first time base signal from said first register, and - in response to an event having been signaled by said second resource (106; IF1), said second time base signal from said second register. - a digital processing unit programmable as a function of a firmware stored to a non-volatile memory; - a first resource (106; ADC) and a second resource (106; IF1) connected to said digital processing unit via a communication system, wherein said first resource (106; ADC) comprises a first register and said second resource (106; IF1) comprises a second register; - a time reference circuit comprising a first digital counter circuit configured to generate, in response to a clock signal, a system time signal comprising a plurality of bits indicative of a time tick-count; - a respective first subset of a respective given number of bits of said system time signal when a respective selection signal (CSEL) has a first value; and - a respective second subset of the respective given number of bits of said system time signal when the respective selection signal (CSEL) has a second value, whereby a time resolution of the respective time base signal varies as a function of the respective selection signal ( CSEL); - detect a respective given event, - store the respective time base signal ( TBI1, TBI2) to the respective register (REG1, REG2) in response to the respective event, and - signal the respective event to said digital processing unit; and - in response to an event having been signaled by said first resource (106; ADC), said first time base signal from said first register, and - in response to an event having been signaled by said second resource (106; IF1), said second time base signal from said second register.