A memory device comprising: a logic die, the logic die including logic to support an input/output interface and packet processing operations; and a plurality of memory dies stacked on the logic die, at least one memory die including one or more memory die portions, a memory die portion including a memory array and IO logic; wherein the memory device provides a first level of memory and the logic die of the memory device is coupled to a second level of memory external to the memory device having a plurality of memory blocks, and wherein the logic die further includes: a tag cache to store an address tag for at least a subset of the plurality of memory blocks,built-in self test (BIST) logic to provide testing of the memory arrays of the memory dies, and dynamic error workaround logic to provide capabilities to handle soft errors and hard errors appearing in the memory arrays of the one or more memory die portions of the plurality of memory dies; characterized in that each address tag includes a disable bit to disable a memory block, and the dynamic error workaround logic of the logic die includes an error checking and correction logic to check for errors appearing in memory and to attempt to correct detected soft errors, a redundancy control logic to provide resources to address hard errors for at least some of the one or more memory die portions, and a cache line disable logic to use the tag cache to disable memory blocks from further use that exhibit hard errors. a logic die, the logic die including logic to support an input/output interface and packet processing operations; and a plurality of memory dies stacked on the logic die, at least one memory die including one or more memory die portions, a memory die portion including a memory array and IO logic; wherein the memory device provides a first level of memory and the logic die of the memory device is coupled to a second level of memory external to the memory device having a plurality of memory blocks, and wherein the logic die further includes: a tag cache to store an address tag for at least a subset of the plurality of memory blocks,built-in self test (BIST) logic to provide testing of the memory arrays of the memory dies, and dynamic error workaround logic to provide capabilities to handle soft errors and hard errors appearing in the memory arrays of the one or more memory die portions of the plurality of memory dies; characterized in that a tag cache to store an address tag for at least a subset of the plurality of memory blocks,built-in self test (BIST) logic to provide testing of the memory arrays of the memory dies, and each address tag includes a disable bit to disable a memory block, and the dynamic error workaround logic of the logic die includes an error checking and correction logic to check for errors appearing in memory and to attempt to correct detected soft errors, a redundancy control logic to provide resources to address hard errors for at least some of the one or more memory die portions, and a cache line disable logic to use the tag cache to disable memory blocks from further use that exhibit hard errors. an error checking and correction logic to check for errors appearing in memory and to attempt to correct detected soft errors, a redundancy control logic to provide resources to address hard errors for at least some of the one or more memory die portions, and a cache line disable logic to use the tag cache to disable memory blocks from further use that exhibit hard errors.