A memory device comprising: a memory cell array comprising a plurality of memory cells; a voltage generator (200; 301) configured to generate voltages used for a program operation and a verify operation for the memory cells; and a control logic (230; 300) configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th program loops comprising a program operation and a verify operation are performed and at least two program loops are performed in which the verify operation is skipped when a pass/fail determination of the program operation of the N-th program loop indicates a pass, wherein N is an integer equal to or greater than 1, wherein the at least two program loops comprise: an (N +1)-th program loop comprising a normal program operation on first memory cells among the memory cells, using a normal program voltage (VP_N) and a forcing program operation on second memory cells among the memory cells, using a forcing program voltage (VP_F); and an (N+2)-th program loop comprising a forcing program operation on the first memory cells using the forcing program voltage (VP_F), wherein the verify operation comprises an operation for determining coarse on cells and coarse off cells based on a first threshold voltage and an operation for determining fine on cells and fine off cells based on a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage, and wherein the memory cells having threshold voltage levels lower than the first threshold voltage correspond to the first memory cells, and the memory cells having threshold voltage levels greater than the first threshold voltage and less than the second threshold voltage correspond to the second memory cells. a memory cell array comprising a plurality of memory cells; a voltage generator (200; 301) configured to generate voltages used for a program operation and a verify operation for the memory cells; and a control logic (230; 300) configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th program loops comprising a program operation and a verify operation are performed and at least two program loops are performed in which the verify operation is skipped when a pass/fail determination of the program operation of the N-th program loop indicates a pass, wherein N is an integer equal to or greater than 1, wherein the at least two program loops comprise: an (N +1)-th program loop comprising a normal program operation on first memory cells among the memory cells, using a normal program voltage (VP_N) and a forcing program operation on second memory cells among the memory cells, using a forcing program voltage (VP_F); and an (N+2)-th program loop comprising a forcing program operation on the first memory cells using the forcing program voltage (VP_F), wherein the verify operation comprises an operation for determining coarse on cells and coarse off cells based on a first threshold voltage and an operation for determining fine on cells and fine off cells based on a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage, and wherein the memory cells having threshold voltage levels lower than the first threshold voltage correspond to the first memory cells, and the memory cells having threshold voltage levels greater than the first threshold voltage and less than the second threshold voltage correspond to the second memory cells. an (N +1)-th program loop comprising a normal program operation on first memory cells among the memory cells, using a normal program voltage (VP_N) and a forcing program operation on second memory cells among the memory cells, using a forcing program voltage (VP_F); and an (N+2)-th program loop comprising a forcing program operation on the first memory cells using the forcing program voltage (VP_F), wherein the verify operation comprises an operation for determining coarse on cells and coarse off cells based on a first threshold voltage and an operation for determining fine on cells and fine off cells based on a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage, and wherein the memory cells having threshold voltage levels lower than the first threshold voltage correspond to the first memory cells, and the memory cells having threshold voltage levels greater than the first threshold voltage and less than the second threshold voltage correspond to the second memory cells.