An apparatus comprising: a first device (310; 410; 510) configured to generate control flow instructions and a control flow based on an evaluation of a plurality of conditions of executable instructions, wherein the control flow defines an order in which the control flow instructions are executed, wherein the control flow comprises a first portion and a second portion, with the first portion comprising a first number of control flow instructions and the second portion comprising a second number of control flow instructions; and a second device (320-1; 420-1, 420-2,..., 420-N; 520) including: an array of memory cells (330; 430-1, 430-2,..., 430-N; 630); a controller (340; 440-1, 440-2,..., 440-N) configured to control an execution of the control flow instructions on data stored in the array; an execution unit (350; 450-1, 450-2,..., 450-N) to execute the control flow instructions of the first portion of the control flow while the control flow instructions of the second portion of the control flow are generated on the first device, the execution unit being sensing circuitry (350; 450-1, 450-2,..., 450-N) comprising a plurality of sense amplifiers (606; 706) and a plurality of compute components (631; 731) wherein: the plurality of compute components (631; 731) comprise transistors; the plurality of compute components (631; 731) are formed on pitch with the memory cells of the respective memory array; and the execution unit (350; 450-1, 450-2,..., 450-N) is operated by the controller (340; 440-1, 440-2,..., 440-N) to execute the control flow instructions, wherein executing the control flow instructions includes performing at least one logical operation. a first device (310; 410; 510) configured to generate control flow instructions and a control flow based on an evaluation of a plurality of conditions of executable instructions, wherein the control flow defines an order in which the control flow instructions are executed, wherein the control flow comprises a first portion and a second portion, with the first portion comprising a first number of control flow instructions and the second portion comprising a second number of control flow instructions; and a second device (320-1; 420-1, 420-2,..., 420-N; 520) including: an array of memory cells (330; 430-1, 430-2,..., 430-N; 630); a controller (340; 440-1, 440-2,..., 440-N) configured to control an execution of the control flow instructions on data stored in the array; an execution unit (350; 450-1, 450-2,..., 450-N) to execute the control flow instructions of the first portion of the control flow while the control flow instructions of the second portion of the control flow are generated on the first device, the execution unit being sensing circuitry (350; 450-1, 450-2,..., 450-N) comprising a plurality of sense amplifiers (606; 706) and a plurality of compute components (631; 731) wherein: the plurality of compute components (631; 731) comprise transistors; the plurality of compute components (631; 731) are formed on pitch with the memory cells of the respective memory array; and the execution unit (350; 450-1, 450-2,..., 450-N) is operated by the controller (340; 440-1, 440-2,..., 440-N) to execute the control flow instructions, wherein executing the control flow instructions includes performing at least one logical operation. an array of memory cells (330; 430-1, 430-2,..., 430-N; 630); a controller (340; 440-1, 440-2,..., 440-N) configured to control an execution of the control flow instructions on data stored in the array; an execution unit (350; 450-1, 450-2,..., 450-N) to execute the control flow instructions of the first portion of the control flow while the control flow instructions of the second portion of the control flow are generated on the first device, the execution unit being sensing circuitry (350; 450-1, 450-2,..., 450-N) comprising a plurality of sense amplifiers (606; 706) and a plurality of compute components (631; 731) wherein: the plurality of compute components (631; 731) comprise transistors; the plurality of compute components (631; 731) are formed on pitch with the memory cells of the respective memory array; and the execution unit (350; 450-1, 450-2,..., 450-N) is operated by the controller (340; 440-1, 440-2,..., 440-N) to execute the control flow instructions, wherein executing the control flow instructions includes performing at least one logical operation. the plurality of compute components (631; 731) comprise transistors; the plurality of compute components (631; 731) are formed on pitch with the memory cells of the respective memory array; and the execution unit (350; 450-1, 450-2,..., 450-N) is operated by the controller (340; 440-1, 440-2,..., 440-N) to execute the control flow instructions, wherein executing the control flow instructions includes performing at least one logical operation.