A test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core, the test circuit comprising: a bypass terminal configured to receive a bypass signal; a cell function input, CFI, terminal configured to receive a CFI signal from the integrated circuit core or the external circuit; a cell function output, CFO, terminal configured to transmit a CFO signal to the integrated circuit core when the CFI signal has been received from the integrated circuit core or to the external circuit when the CFI signal has been received from the external circuit; a first multiplexer including a first select terminal connected to the bypass terminal, a first input terminal connected to the CFI terminal, a second input terminal, and a first output terminal connected to the CFO terminal, and the first multiplexer configured to transmit the CFI signal to the integrated circuit core when the CFI signal has been received from the integrated circuit core or to the external circuit when the CFI signal has been received from the external circuit through the first output terminal as the CFO signal in response to the bypass signal; a scan flip-flop; a second multiplexer including a second select terminal connected to a safe mode terminal configured to receive a safe mode signal, a third input terminal connected to an output terminal of the scan flip-flop, a fourth input terminal connected to a safe value terminal configured to receive a safe value signal, and a second output terminal connected to the second input terminal of the first multiplexer; a cell test output terminal connected to the output terminal of the scan flip-flop; and a clock gating circuit configured to receive a scan enable signal through a scan enable terminal, a clock signal through a clock signal terminal and a test signal (EXTEST, INTEST), and output a first output signal (OUTPUT1) to control whether the clock signal is gated in response to a combination of the scan enable signal and the test signal, wherein the scan flip-flop includes: a third multiplexer including a third selection terminal connected to the scan enable terminal, a fifth input terminal connected to the CFI terminal, a sixth input terminal connected to a cell test input, CTI, terminal configured to receive a CTI signal, and a third output terminal; and a D-flip-flop configured to capture an output signal output from the third output terminal of the third multiplexer in response to the first output signal received through a clock terminal, and to transmit the captured output signal to the third input terminal of the second multiplexer. a bypass terminal configured to receive a bypass signal; a cell function input, CFI, terminal configured to receive a CFI signal from the integrated circuit core or the external circuit; a cell function output, CFO, terminal configured to transmit a CFO signal to the integrated circuit core when the CFI signal has been received from the integrated circuit core or to the external circuit when the CFI signal has been received from the external circuit; a first multiplexer including a first select terminal connected to the bypass terminal, a first input terminal connected to the CFI terminal, a second input terminal, and a first output terminal connected to the CFO terminal, and the first multiplexer configured to transmit the CFI signal to the integrated circuit core when the CFI signal has been received from the integrated circuit core or to the external circuit when the CFI signal has been received from the external circuit through the first output terminal as the CFO signal in response to the bypass signal; a scan flip-flop; a second multiplexer including a second select terminal connected to a safe mode terminal configured to receive a safe mode signal, a third input terminal connected to an output terminal of the scan flip-flop, a fourth input terminal connected to a safe value terminal configured to receive a safe value signal, and a second output terminal connected to the second input terminal of the first multiplexer; a cell test output terminal connected to the output terminal of the scan flip-flop; and a clock gating circuit configured to receive a scan enable signal through a scan enable terminal, a clock signal through a clock signal terminal and a test signal (EXTEST, INTEST), and output a first output signal (OUTPUT1) to control whether the clock signal is gated in response to a combination of the scan enable signal and the test signal, wherein the scan flip-flop includes: a third multiplexer including a third selection terminal connected to the scan enable terminal, a fifth input terminal connected to the CFI terminal, a sixth input terminal connected to a cell test input, CTI, terminal configured to receive a CTI signal, and a third output terminal; and a D-flip-flop configured to capture an output signal output from the third output terminal of the third multiplexer in response to the first output signal received through a clock terminal, and to transmit the captured output signal to the third input terminal of the second multiplexer. a third multiplexer including a third selection terminal connected to the scan enable terminal, a fifth input terminal connected to the CFI terminal, a sixth input terminal connected to a cell test input, CTI, terminal configured to receive a CTI signal, and a third output terminal; and a D-flip-flop configured to capture an output signal output from the third output terminal of the third multiplexer in response to the first output signal received through a clock terminal, and to transmit the captured output signal to the third input terminal of the second multiplexer.