A device (100, 300) comprising: a plurality of display panels; a plurality of display controllers (116, 304), each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing signal indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel; a processor (106, 306) coupled to the plurality of display controllers to receive the timing signals from the plurality of display controllers, wherein the processor comprises a signal processor configured to implement an AND operation on the timing signals generated by the plurality of display controllers and output a refresh trigger signal accordingly, and send the refresh trigger signal to each display controller of the plurality of display controllers upon receipt of the timing signal from each respective display controller of the plurality of display controllers such that the processor is configured to delay a refresh of the plurality of display panels until the timing signal is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels, the device being characterized in that it comprises an application processor configured to generate image data to be rendered on the plurality of display panels of the device and to provide an enable signal to each display controller of the plurality of display controllers; wherein each display controller of the plurality of display controllers is adapted to be enabled to be responsive to the refresh trigger signal according to the enable signal, and wherein the signal processor is configured to synchronize the plurality of display panels when the application processor is not generating the image data. a plurality of display panels; a plurality of display controllers (116, 304), each display controller of the plurality of display controllers being configured to control a corresponding display panel of the plurality of display panels, each respective display controller of the plurality of display controllers being configured to generate a timing signal indicative of the respective display controller residing in a state ready for refresh of the corresponding display panel; a processor (106, 306) coupled to the plurality of display controllers to receive the timing signals from the plurality of display controllers, wherein the processor comprises a signal processor configured to implement an AND operation on the timing signals generated by the plurality of display controllers and output a refresh trigger signal accordingly, and send the refresh trigger signal to each display controller of the plurality of display controllers upon receipt of the timing signal from each respective display controller of the plurality of display controllers such that the processor is configured to delay a refresh of the plurality of display panels until the timing signal is received from each respective display controller of the plurality of display controllers to synchronize the plurality of display panels, the device being characterized in that it comprises an application processor configured to generate image data to be rendered on the plurality of display panels of the device and to provide an enable signal to each display controller of the plurality of display controllers; wherein each display controller of the plurality of display controllers is adapted to be enabled to be responsive to the refresh trigger signal according to the enable signal, and wherein the signal processor is configured to synchronize the plurality of display panels when the application processor is not generating the image data.