An apparatus including an image array, comprising: a plurality of bias lines to convey a common bias voltage; a plurality of data lines to convey a plurality of data signals; a plurality of address lines to convey a plurality of address signals; a plurality of reference lines to convey a common reference voltage; a plurality of clamp lines to convey a plurality of clamp control signals; and a plurality of pixels disposed along a plurality of rows and a plurality of columns, wherein each pixel includes a photodiode coupled to one of said plurality of bias lines, a switch transistor including first and second switch electrodes coupled to said photodiode and one of said plurality of data lines, respectively, and a switch control electrode coupled to one of said plurality of address lines, and a clamp transistor including first and second clamp electrodes coupled to said photodiode and one of said plurality of reference lines, respectively, and a clamp control electrode coupled to one of said plurality of clamp lines; characterised by: driver circuitry configured to: read a first row of pixels in a first line time period by assertion of a first address signal; and in a subsequent line time period, read a subsequent row of pixels by assertion of a second address signal and meanwhile discharging said first row of pixels by assertion of a corresponding clamp control signal. a plurality of bias lines to convey a common bias voltage; a plurality of data lines to convey a plurality of data signals; a plurality of address lines to convey a plurality of address signals; a plurality of reference lines to convey a common reference voltage; a plurality of clamp lines to convey a plurality of clamp control signals; and a plurality of pixels disposed along a plurality of rows and a plurality of columns, wherein each pixel includes a photodiode coupled to one of said plurality of bias lines, a switch transistor including first and second switch electrodes coupled to said photodiode and one of said plurality of data lines, respectively, and a switch control electrode coupled to one of said plurality of address lines, and a clamp transistor including first and second clamp electrodes coupled to said photodiode and one of said plurality of reference lines, respectively, and a clamp control electrode coupled to one of said plurality of clamp lines; a photodiode coupled to one of said plurality of bias lines, a switch transistor including first and second switch electrodes coupled to said photodiode and one of said plurality of data lines, respectively, and a switch control electrode coupled to one of said plurality of address lines, and a clamp transistor including first and second clamp electrodes coupled to said photodiode and one of said plurality of reference lines, respectively, and a clamp control electrode coupled to one of said plurality of clamp lines; characterised by: driver circuitry configured to: read a first row of pixels in a first line time period by assertion of a first address signal; and in a subsequent line time period, read a subsequent row of pixels by assertion of a second address signal and meanwhile discharging said first row of pixels by assertion of a corresponding clamp control signal. read a first row of pixels in a first line time period by assertion of a first address signal; and in a subsequent line time period, read a subsequent row of pixels by assertion of a second address signal and meanwhile discharging said first row of pixels by assertion of a corresponding clamp control signal.