A device for performing an LDPC processing operation by employing a multi-level permutation, the device comprising: a memory for storing a plurality of Z element vectors, each Z element vector includes Z elements wherein Z is an integer value greater than 1, each element including at least one bit to be processed; a parallel LDPC processing module including Z processing elements arranged to perform parity check operations including one of encoding or decoding operations on Z vector elements in parallel; and a controllable factorable permuter for coupling said memory to said parallel LDPC processing module that reorders the Z element vectors to facilitate processing of the Z element vectors by the Z processing elements, said controllable factorable permuter including switching circuitry, said switching circuitry being responsive to a control signal to perform a factorable permutation operation on a Z element vector being passed through said factorable permuter, said factorable permutation operation including first and second permutation operations which cause first and second re-orderings of vector elements to occur, said first and second reordering operations being performed on n equally sized vector portions of size Z/n, said first permutation operation causing a change in the order of at least two equally sized vector portions, said second permutation operation being performed on each of the Z/n sized portions to cause a change in the ordering of elements within each of said Z/n sized portions, where n is an integer greater than 1 and less than Z; and wherein the LPDC code being processed corresponds to a parity check matrix H that is composed of Z×Z matrices that are either zero or a Z×Z permutation matrix, and wherein the controllable factorable permuter carries out permutations corresponding to Z×Z permutation matrices. a memory for storing a plurality of Z element vectors, each Z element vector includes Z elements wherein Z is an integer value greater than 1, each element including at least one bit to be processed; a parallel LDPC processing module including Z processing elements arranged to perform parity check operations including one of encoding or decoding operations on Z vector elements in parallel; and a controllable factorable permuter for coupling said memory to said parallel LDPC processing module that reorders the Z element vectors to facilitate processing of the Z element vectors by the Z processing elements, said controllable factorable permuter including switching circuitry, said switching circuitry being responsive to a control signal to perform a factorable permutation operation on a Z element vector being passed through said factorable permuter, said factorable permutation operation including first and second permutation operations which cause first and second re-orderings of vector elements to occur, said first and second reordering operations being performed on n equally sized vector portions of size Z/n, said first permutation operation causing a change in the order of at least two equally sized vector portions, said second permutation operation being performed on each of the Z/n sized portions to cause a change in the ordering of elements within each of said Z/n sized portions, where n is an integer greater than 1 and less than Z; and wherein the LPDC code being processed corresponds to a parity check matrix H that is composed of Z×Z matrices that are either zero or a Z×Z permutation matrix, and wherein the controllable factorable permuter carries out permutations corresponding to Z×Z permutation matrices.