An image sensor, comprising an array of pixels, wherein each pixel of the pixel array has a pixel structure comprising: a photosensitive device configured to sense incident light and output a first analog signal, a first node configured to receive the first analog signal, a first in-pixel part of an analog-to-digital converter configured to output at least one current signal and connected to the first node, the at least one current signal being configured to output to at least one output bus line (14, 15) that is connected to a second part of the analog-to-digital converter which is not in the pixel structure, the first part of the analog-to-digital converter being a first differential transconductance amplifier and a second differential transconductance amplifier with a first input of the first and second transconductance amplifier (20, 20') configured to receive a second analog signal present on the first node, the second part of the analog-to-digital converter being adapted to receive the at least one current signal and to generate a digital signal being an analog-to-digital conversion of the second analog signal, wherein the image sensor is adapted for analog-to-digital conversion of a photosignal using the differential transconductance amplifier, wherein the pixel array is on a first die and the second part of the analog-to-digital converter is on a second die, that the first transconductance amplifier comprises a first transistor and a second transistor, wherein a control electrode of the first transistor is coupled to the first node and a control electrode of the second transistor is coupled to a reset ramp signal (Vramp,reset), and that the second transconductance amplifier comprises the first transistor and a third transistor, wherein a gate of the third transistor is coupled to a ramp signal (Vramp, signal), wherein a common source of the first, second and third transistor (27, 28a, 28b) is connected to a bias current source, a drain of the first transistor is coupled to a first output bus and a common drain of the second and third transistor (28a, 28b) is coupled to a second output bus, wherein the first and the second die (52, 53) are stacked together with wafer-to-wafer stacking or die-to-die bonding. a photosensitive device configured to sense incident light and output a first analog signal, a first node configured to receive the first analog signal, a first in-pixel part of an analog-to-digital converter configured to output at least one current signal and connected to the first node, the at least one current signal being configured to output to at least one output bus line (14, 15) that is connected to a second part of the analog-to-digital converter which is not in the pixel structure, the first part of the analog-to-digital converter being a first differential transconductance amplifier and a second differential transconductance amplifier with a first input of the first and second transconductance amplifier (20, 20') configured to receive a second analog signal present on the first node, the second part of the analog-to-digital converter being adapted to receive the at least one current signal and to generate a digital signal being an analog-to-digital conversion of the second analog signal, wherein the image sensor is adapted for analog-to-digital conversion of a photosignal using the differential transconductance amplifier, wherein the pixel array is on a first die and the second part of the analog-to-digital converter is on a second die, that the first transconductance amplifier comprises a first transistor and a second transistor, wherein a control electrode of the first transistor is coupled to the first node and a control electrode of the second transistor is coupled to a reset ramp signal (Vramp,reset), and that the second transconductance amplifier comprises the first transistor and a third transistor, wherein a gate of the third transistor is coupled to a ramp signal (Vramp, signal), wherein a common source of the first, second and third transistor (27, 28a, 28b) is connected to a bias current source, a drain of the first transistor is coupled to a first output bus and a common drain of the second and third transistor (28a, 28b) is coupled to a second output bus, wherein the first and the second die (52, 53) are stacked together with wafer-to-wafer stacking or die-to-die bonding.