A solid-state imaging device in which a plurality of pixel portions (P m,n) are arranged one- or two-dimensionally, wherein the plurality of pixel portions (P m,n) each comprise: a buried photodiode configured to generate charges of an amount corresponding to the intensity of incident light; and a capacitive element connected in parallel to the buried photodiode and configured to accumulate charges generated in the buried photodiode; and a transferring transistor (T 2) connected to the buried photodiode; wherein said buried photodiode includes: a first semiconductor region of first conductivity type; a second semiconductor region of second conductivity type, the second semiconductor region being formed on the first semiconductor region; and wherein the transferring transistor (T 2) includes; a fourth semiconductor region as a source terminal of the transferring transistor (T 2), the fourth semiconductor region being of the second conductivity type and being in contact with said first and second semiconductor regions (11, 12) of the buried photodiode; and a fifth semiconductor region of second conductivity type as a drain terminal of the transferring transistor (T 2), wherein the fifth semiconductor region is formed on the first semiconductor region; wherein the capacitive element comprises a first electrode layer, a second electrode layer and a dielectric layer between the first and second electrode layers; and wherein the second electrode layer is connected electrically with the fourth semiconductor region; characterized in that said buried photodiode further includes: a third semiconductor region of first conductivity type, the third semiconductor region being formed on both the first semiconductor region and the second semiconductor region; and wherein the first electrode layer is connected electrically with the first semiconductor region. a buried photodiode configured to generate charges of an amount corresponding to the intensity of incident light; and a capacitive element connected in parallel to the buried photodiode and configured to accumulate charges generated in the buried photodiode; and a transferring transistor (T 2) connected to the buried photodiode; wherein said buried photodiode includes: a first semiconductor region of first conductivity type; a second semiconductor region of second conductivity type, the second semiconductor region being formed on the first semiconductor region; and a first semiconductor region of first conductivity type; a second semiconductor region of second conductivity type, the second semiconductor region being formed on the first semiconductor region; and wherein the transferring transistor (T 2) includes; a fourth semiconductor region as a source terminal of the transferring transistor (T 2), the fourth semiconductor region being of the second conductivity type and being in contact with said first and second semiconductor regions (11, 12) of the buried photodiode; and a fifth semiconductor region of second conductivity type as a drain terminal of the transferring transistor (T 2), wherein the fifth semiconductor region is formed on the first semiconductor region; a fourth semiconductor region as a source terminal of the transferring transistor (T 2), the fourth semiconductor region being of the second conductivity type and being in contact with said first and second semiconductor regions (11, 12) of the buried photodiode; and a fifth semiconductor region of second conductivity type as a drain terminal of the transferring transistor (T 2), wherein the fifth semiconductor region is formed on the first semiconductor region; wherein the capacitive element comprises a first electrode layer, a second electrode layer and a dielectric layer between the first and second electrode layers; and wherein the second electrode layer is connected electrically with the fourth semiconductor region; characterized in that said buried photodiode further includes: a third semiconductor region of first conductivity type, the third semiconductor region being formed on both the first semiconductor region and the second semiconductor region; and wherein the first electrode layer is connected electrically with the first semiconductor region.