FPGA power management system comprising: a host power management integrated circuit (11, 21) connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device connected to the host power management integrated circuit (11, 21) via a power configuration/monitoring bus and the computing device is further connected to the FPGA system power control block via another configuration/monitoring bus; the host power management integrated circuit comprising a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device; at least one voltage regulator (23, 24, 25) for supplying an output voltage to an FPGA power rail (19, 29; 110, 210; 111, 211) according to a power configuration signal communicated by the configuration and monitoring block; a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail; the FPGA system power control block configured to coordinate and execute a transfer of required communications between the FPGA and the host power management integrated circuit; and the computing device comprising a display and an input device for monitoring and controlling aspects of an FPGA operation and FPGA design tools and power design tools for altering the FPGA configuration or power. a host power management integrated circuit (11, 21) connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device connected to the host power management integrated circuit (11, 21) via a power configuration/monitoring bus and the computing device is further connected to the FPGA system power control block via another configuration/monitoring bus; the host power management integrated circuit comprising a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device; at least one voltage regulator (23, 24, 25) for supplying an output voltage to an FPGA power rail (19, 29; 110, 210; 111, 211) according to a power configuration signal communicated by the configuration and monitoring block; a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail; the FPGA system power control block configured to coordinate and execute a transfer of required communications between the FPGA and the host power management integrated circuit; and the computing device comprising a display and an input device for monitoring and controlling aspects of an FPGA operation and FPGA design tools and power design tools for altering the FPGA configuration or power. a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device; at least one voltage regulator (23, 24, 25) for supplying an output voltage to an FPGA power rail (19, 29; 110, 210; 111, 211) according to a power configuration signal communicated by the configuration and monitoring block; a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail; the FPGA system power control block configured to coordinate and execute a transfer of required communications between the FPGA and the host power management integrated circuit; and the computing device comprising a display and an input device for monitoring and controlling aspects of an FPGA operation and FPGA design tools and power design tools for altering the FPGA configuration or power.