A clock generation circuit comprising: a bias circuit; an oscillator circuit (40, 42, 44, 46, 50) operative to selectively generate a periodic signal, wherein the oscillator circuit is a relaxation oscillator circuit comprising: an integration capacitor (Cint); an amplifier coupled to a first transistor to control a gate of the first transistor so as to control a current through a current generating circuit of the relaxation oscillator circuit; and a current mirror (M2, M3) configured to copy the current through the current generating circuit to an integration circuit of the relaxation oscillator to produce a charging current (Icharge) for charging the integration capacitor (Cint); and an output circuit operative to receive the periodic signal from the oscillator circuit and to output a clock signal; and wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication (ClockRequest, StandBy) provided for the clock generation circuit; wherein: in the first full power mode, the oscillator circuit (40, 42, 44, 46, 50) provides the periodic signal to the output circuit and the output circuit generates a clock signal; in the second sleep mode, the oscillator circuit (40, 42, 44, 46, 50) is disabled; and in the third standby mode, the amplifier is biased to a voltage close to its operating voltage but the oscillator circuit (40, 42, 44, 46, 50) does not generate the periodic signal. a bias circuit; an oscillator circuit (40, 42, 44, 46, 50) operative to selectively generate a periodic signal, wherein the oscillator circuit is a relaxation oscillator circuit comprising: an integration capacitor (Cint); an amplifier coupled to a first transistor to control a gate of the first transistor so as to control a current through a current generating circuit of the relaxation oscillator circuit; and a current mirror (M2, M3) configured to copy the current through the current generating circuit to an integration circuit of the relaxation oscillator to produce a charging current (Icharge) for charging the integration capacitor (Cint); and an output circuit operative to receive the periodic signal from the oscillator circuit and to output a clock signal; and an integration capacitor (Cint); an amplifier coupled to a first transistor to control a gate of the first transistor so as to control a current through a current generating circuit of the relaxation oscillator circuit; and a current mirror (M2, M3) configured to copy the current through the current generating circuit to an integration circuit of the relaxation oscillator to produce a charging current (Icharge) for charging the integration capacitor (Cint); and an output circuit operative to receive the periodic signal from the oscillator circuit and to output a clock signal; wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication (ClockRequest, StandBy) provided for the clock generation circuit; wherein: in the first full power mode, the oscillator circuit (40, 42, 44, 46, 50) provides the periodic signal to the output circuit and the output circuit generates a clock signal; in the second sleep mode, the oscillator circuit (40, 42, 44, 46, 50) is disabled; and in the third standby mode, the amplifier is biased to a voltage close to its operating voltage but the oscillator circuit (40, 42, 44, 46, 50) does not generate the periodic signal. in the first full power mode, the oscillator circuit (40, 42, 44, 46, 50) provides the periodic signal to the output circuit and the output circuit generates a clock signal; in the second sleep mode, the oscillator circuit (40, 42, 44, 46, 50) is disabled; and in the third standby mode, the amplifier is biased to a voltage close to its operating voltage but the oscillator circuit (40, 42, 44, 46, 50) does not generate the periodic signal.