A processor comprising: multiple cores (20A-D); and a power management unit, PMU, comprising a power management control logic configured to perform the following operations: determining a tuned frequency for the cores (20A-D) of the processor, wherein the tuned frequency corresponds to a threshold performance state, P-state, in that a relative amount of power savings that would be saved by using a next lower P-state instead of using the threshold P-state is less than a relative amount of performance that would be lost by using the lower P-state instead of using the threshold P-state; determining (114, 116) a preliminary frequency for each of the cores (20A-D) based on individual efficiency/performance preference, EPP, setting of logical processors, LPs (22, 24), of the respective core (20A-D) and runtime factors; determining a maximum preliminary frequency of the preliminary frequencies that have been determined for the cores (20A-D) of the processor; determining a dynamic tuning frequency which is lower than the maximum preliminary frequency based on the maximum preliminary frequency to which a reduction factor is applied; determining a bump frequency and a floor frequency for each of the cores (20A-D), wherein the bump frequency is the minimum of the tuned frequency and the maximum preliminary frequency, and the floor frequency is the maximum of the preliminary frequency of the respective core (20A-D) and the dynamic tuning frequency; and applying to each of the cores (20A-D) its optimized frequency, wherein the optimized frequency of a respective core (20A-D) is the maximum of the floor frequency and the bump frequency of the respective core (20A-D). multiple cores (20A-D); and a power management unit, PMU, comprising a power management control logic configured to perform the following operations: determining a tuned frequency for the cores (20A-D) of the processor, wherein the tuned frequency corresponds to a threshold performance state, P-state, in that a relative amount of power savings that would be saved by using a next lower P-state instead of using the threshold P-state is less than a relative amount of performance that would be lost by using the lower P-state instead of using the threshold P-state; determining (114, 116) a preliminary frequency for each of the cores (20A-D) based on individual efficiency/performance preference, EPP, setting of logical processors, LPs (22, 24), of the respective core (20A-D) and runtime factors; determining a maximum preliminary frequency of the preliminary frequencies that have been determined for the cores (20A-D) of the processor; determining a dynamic tuning frequency which is lower than the maximum preliminary frequency based on the maximum preliminary frequency to which a reduction factor is applied; determining a bump frequency and a floor frequency for each of the cores (20A-D), wherein the bump frequency is the minimum of the tuned frequency and the maximum preliminary frequency, and the floor frequency is the maximum of the preliminary frequency of the respective core (20A-D) and the dynamic tuning frequency; and applying to each of the cores (20A-D) its optimized frequency, wherein the optimized frequency of a respective core (20A-D) is the maximum of the floor frequency and the bump frequency of the respective core (20A-D). determining a tuned frequency for the cores (20A-D) of the processor, wherein the tuned frequency corresponds to a threshold performance state, P-state, in that a relative amount of power savings that would be saved by using a next lower P-state instead of using the threshold P-state is less than a relative amount of performance that would be lost by using the lower P-state instead of using the threshold P-state; determining (114, 116) a preliminary frequency for each of the cores (20A-D) based on individual efficiency/performance preference, EPP, setting of logical processors, LPs (22, 24), of the respective core (20A-D) and runtime factors; determining a maximum preliminary frequency of the preliminary frequencies that have been determined for the cores (20A-D) of the processor; determining a dynamic tuning frequency which is lower than the maximum preliminary frequency based on the maximum preliminary frequency to which a reduction factor is applied; determining a bump frequency and a floor frequency for each of the cores (20A-D), wherein the bump frequency is the minimum of the tuned frequency and the maximum preliminary frequency, and the floor frequency is the maximum of the preliminary frequency of the respective core (20A-D) and the dynamic tuning frequency; and applying to each of the cores (20A-D) its optimized frequency, wherein the optimized frequency of a respective core (20A-D) is the maximum of the floor frequency and the bump frequency of the respective core (20A-D).