A method for reducing power consumed by a multi-core processor comprising: determining a first voltage offset value that may be applied to a common supply voltage level, with the common supply voltage supplied to all processor cores in the multi-core processor, to reduce the common supply voltage level to a first reduced supply voltage level that does not adversely affect operating stability of a first processor core (16); offsetting the common supply voltage level by the first voltage offset value to form the first reduced supply voltage level; supplying the first reduced supply voltage level to the first core processor (16) to reduce power consumption; further comprising: determining a second voltage offset value that may be applied to the common supply voltage level to reduce the common supply voltage level to a second reduced supply voltage level that does not adversely affect operating stability of a second processor core (16) in the multi-core processor; offsetting the common supply voltage level by the second voltage offset value to form the second reduced supply voltage level; and supplying the second reduced supply voltage supply level to the second core processor (16) to reduce power consumption; characterized by using a voltage margin hint register to supply an indication of which of the first or second reduced supply voltage levels is smaller to an operating system so that the operating system may schedule threads to execute on a processor core that consumes less power. determining a first voltage offset value that may be applied to a common supply voltage level, with the common supply voltage supplied to all processor cores in the multi-core processor, to reduce the common supply voltage level to a first reduced supply voltage level that does not adversely affect operating stability of a first processor core (16); offsetting the common supply voltage level by the first voltage offset value to form the first reduced supply voltage level; supplying the first reduced supply voltage level to the first core processor (16) to reduce power consumption; further comprising: determining a second voltage offset value that may be applied to the common supply voltage level to reduce the common supply voltage level to a second reduced supply voltage level that does not adversely affect operating stability of a second processor core (16) in the multi-core processor; offsetting the common supply voltage level by the second voltage offset value to form the second reduced supply voltage level; and supplying the second reduced supply voltage supply level to the second core processor (16) to reduce power consumption; characterized by using a voltage margin hint register to supply an indication of which of the first or second reduced supply voltage levels is smaller to an operating system so that the operating system may schedule threads to execute on a processor core that consumes less power. determining a second voltage offset value that may be applied to the common supply voltage level to reduce the common supply voltage level to a second reduced supply voltage level that does not adversely affect operating stability of a second processor core (16) in the multi-core processor; offsetting the common supply voltage level by the second voltage offset value to form the second reduced supply voltage level; and supplying the second reduced supply voltage supply level to the second core processor (16) to reduce power consumption; characterized by using a voltage margin hint register to supply an indication of which of the first or second reduced supply voltage levels is smaller to an operating system so that the operating system may schedule threads to execute on a processor core that consumes less power.