An apparatus, for extending data modes within a microprocessor with a x86 instruction set, the apparatus comprising: translation logic, for translating an extended instruction into corresponding micro instructions for execution by the microprocessor, wherein said extended instruction comprises: an extended prefix, for specifying an extended operand size for an operand corresponding to an operation, wherein said extended operand size cannot be specified by an existing instruction set; and an extended instruction tag, for indicating said extended prefix, wherein said extended instruction tag is an otherwise architecturally specified, yet unused, opcode within said existing instruction set, and wherein specification of said extended operand size via said extended instruction continues to allow execution of any other opcode in said existing instruction set; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for performing said operation using said operand; wherein said extended instruction further comprises instruction entities according to said existing instruction set; and said instruction entities prescribe said operation to be executed by the microprocessor, and wherein said operand corresponding to said operation is retrievable/storable from/to a register, wherein said register supports retrieval/storage of operands according to a plurality of operand sizes. translation logic, for translating an extended instruction into corresponding micro instructions for execution by the microprocessor, wherein said extended instruction comprises: an extended prefix, for specifying an extended operand size for an operand corresponding to an operation, wherein said extended operand size cannot be specified by an existing instruction set; and an extended instruction tag, for indicating said extended prefix, wherein said extended instruction tag is an otherwise architecturally specified, yet unused, opcode within said existing instruction set, and wherein specification of said extended operand size via said extended instruction continues to allow execution of any other opcode in said existing instruction set; and an extended prefix, for specifying an extended operand size for an operand corresponding to an operation, wherein said extended operand size cannot be specified by an existing instruction set; and an extended instruction tag, for indicating said extended prefix, wherein said extended instruction tag is an otherwise architecturally specified, yet unused, opcode within said existing instruction set, and wherein specification of said extended operand size via said extended instruction continues to allow execution of any other opcode in said existing instruction set; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for performing said operation using said operand; wherein said extended instruction further comprises instruction entities according to said existing instruction set; and said instruction entities prescribe said operation to be executed by the microprocessor, and wherein said operand corresponding to said operation is retrievable/storable from/to a register, wherein said register supports retrieval/storage of operands according to a plurality of operand sizes.