A semiconductor device comprising: - a semiconductor chip configured for voltages of at least 0.6 kV comprising top contact areas at a chip top side, - a first electric wiring layer in electric contact with the top contact areas having first contact areas electrically assigned to the top contact areas, - a second electric wiring layer on a side of the first electric wiring layer remote from the top contact areas and having second contact areas electrically assigned to the top contact areas, the second contact areas are configured as external contact areas, and - at least one third electric wiring layer located between and electrically connected with the first electric wiring layer and the second electric wiring layer and having third contact areas, wherein - the semiconductor device is a chip-sized package, - the semiconductor chip is a power metal-insulator field-effect transistor, MISFET, or a power insulated-gate bipolar transistor, IGBT, - the first, second and third wiring layers (3, 4, 5) are separated from one another in each case by an insulation layer (61, 62, 63) made of a dielectric material through which electric through-contacts (71, 72, 73) are formed, - a first one of the second contact areas shaped differently from an electrically assigned one of the top contact areas completely runs around a second one of the second contact areas shaped differently from the electrically assigned one of the top contact areas in a coaxial manner, seen in top view of the chip top side, so that the first one and the second one of the second contact areas are arranged rotational symmetrically and/or point symmetrically. - a semiconductor chip configured for voltages of at least 0.6 kV comprising top contact areas at a chip top side, - a first electric wiring layer in electric contact with the top contact areas having first contact areas electrically assigned to the top contact areas, - a second electric wiring layer on a side of the first electric wiring layer remote from the top contact areas and having second contact areas electrically assigned to the top contact areas, the second contact areas are configured as external contact areas, and - at least one third electric wiring layer located between and electrically connected with the first electric wiring layer and the second electric wiring layer and having third contact areas, - the semiconductor device is a chip-sized package, - the semiconductor chip is a power metal-insulator field-effect transistor, MISFET, or a power insulated-gate bipolar transistor, IGBT, - the first, second and third wiring layers (3, 4, 5) are separated from one another in each case by an insulation layer (61, 62, 63) made of a dielectric material through which electric through-contacts (71, 72, 73) are formed, - a first one of the second contact areas shaped differently from an electrically assigned one of the top contact areas completely runs around a second one of the second contact areas shaped differently from the electrically assigned one of the top contact areas in a coaxial manner, seen in top view of the chip top side, so that the first one and the second one of the second contact areas are arranged rotational symmetrically and/or point symmetrically.