An electrostatic discharge protection circuit, comprising: a first n-type transistor, having a first terminal coupled to a supply voltage, a second terminal coupled to a reference voltage, and a gate, wherein the first n-type transistor couples the supply voltage to the reference voltage during an ESD event at an I/O pad; a discharge acceleration circuit (203, 303), coupling the gate of the first n-type transistor to the I/O pad during the ESD event and coupling the gate of the first n-type transistor to the reference voltage when there is no ESD event; and a discharge time circuit (204, 304), coupled to the discharge acceleration circuit and the supply voltage, controlling a discharge time of the first n-type transistor of coupling the supply voltage to the reference voltage during the ESD event at the I/O pad, wherein the supply voltage is coupled to the I/O pad, wherein a voltage potential of the I/O pad is higher than the supply voltage or lower than the reference voltage during the ESD event wherein the discharge acceleration circuit comprises: a second n-type transistor, having a first terminal coupled to the discharge time circuit, a second terminal coupled to the gate of the first n-type transistor, and a gate coupled to the supply voltage; and; a first p-type transistor, having a first terminal coupled to the I/O pad, a second terminal coupled to the gate of the first n-type transistor, and a gate coupled to the supply voltage. a first n-type transistor, having a first terminal coupled to a supply voltage, a second terminal coupled to a reference voltage, and a gate, wherein the first n-type transistor couples the supply voltage to the reference voltage during an ESD event at an I/O pad; a discharge acceleration circuit (203, 303), coupling the gate of the first n-type transistor to the I/O pad during the ESD event and coupling the gate of the first n-type transistor to the reference voltage when there is no ESD event; and a discharge time circuit (204, 304), coupled to the discharge acceleration circuit and the supply voltage, controlling a discharge time of the first n-type transistor of coupling the supply voltage to the reference voltage during the ESD event at the I/O pad, wherein the supply voltage is coupled to the I/O pad, wherein a voltage potential of the I/O pad is higher than the supply voltage or lower than the reference voltage during the ESD event wherein the discharge acceleration circuit comprises: a second n-type transistor, having a first terminal coupled to the discharge time circuit, a second terminal coupled to the gate of the first n-type transistor, and a gate coupled to the supply voltage; and; a first p-type transistor, having a first terminal coupled to the I/O pad, a second terminal coupled to the gate of the first n-type transistor, and a gate coupled to the supply voltage. a second n-type transistor, having a first terminal coupled to the discharge time circuit, a second terminal coupled to the gate of the first n-type transistor, and a gate coupled to the supply voltage; and; a first p-type transistor, having a first terminal coupled to the I/O pad, a second terminal coupled to the gate of the first n-type transistor, and a gate coupled to the supply voltage.