A memory circuit, comprising: a first plurality of bit-cells (208 - 210, 300) organized in a first column, each bit-cell of the first plurality (208 - 210, 300) coupled to a first voltage supply terminal, a second voltage supply terminal, a first bit-line (BL 0, BL), and a second bit-line (BLB 0, BLB); a first word-line (WL 0, WL) coupled to a first bit-cell (208, 300) of the first plurality (208 - 210, 300), the first word-line (WL 0, WL) configured to receive a first voltage during a first write operation; a first voltage generation circuit coupled to a first power supply terminal and the first voltage supply terminal, the first voltage generation circuit configured to provide a first reduced voltage (VDDC) at the first voltage supply terminal during the first write operation, the first reduced voltage (VDDC) being lower than the first voltage, the first voltage generation circuit comprising: a first transistor (410, 412) having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the first voltage supply terminal, and a control electrode coupled to receive a first control signal (VDDPCB), and a first capacitor having a first terminal coupled to a second control signal (BOOST), and a second terminal coupled to the first voltage supply terminal; and a second voltage generation circuit coupled to a second power supply terminal and to the second voltage supply terminal, the second voltage generation circuit configured to provide at the second voltage supply terminal a second reduced voltage (VSSC) during the first write operation. a first plurality of bit-cells (208 - 210, 300) organized in a first column, each bit-cell of the first plurality (208 - 210, 300) coupled to a first voltage supply terminal, a second voltage supply terminal, a first bit-line (BL 0, BL), and a second bit-line (BLB 0, BLB); a first word-line (WL 0, WL) coupled to a first bit-cell (208, 300) of the first plurality (208 - 210, 300), the first word-line (WL 0, WL) configured to receive a first voltage during a first write operation; a first voltage generation circuit coupled to a first power supply terminal and the first voltage supply terminal, the first voltage generation circuit configured to provide a first reduced voltage (VDDC) at the first voltage supply terminal during the first write operation, the first reduced voltage (VDDC) being lower than the first voltage, the first voltage generation circuit comprising: a first transistor (410, 412) having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the first voltage supply terminal, and a control electrode coupled to receive a first control signal (VDDPCB), and a first capacitor having a first terminal coupled to a second control signal (BOOST), and a second terminal coupled to the first voltage supply terminal; and a first transistor (410, 412) having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the first voltage supply terminal, and a control electrode coupled to receive a first control signal (VDDPCB), and a first capacitor having a first terminal coupled to a second control signal (BOOST), and a second terminal coupled to the first voltage supply terminal; and a second voltage generation circuit coupled to a second power supply terminal and to the second voltage supply terminal, the second voltage generation circuit configured to provide at the second voltage supply terminal a second reduced voltage (VSSC) during the first write operation.