A method of operation of a compilable memory array (102, 104), the method comprising: discharging a plurality of bit lines, BL, during an inactive memory access period; stopping the discharging of a select one of the plurality of bit lines during an active memory access period; during the active memory access period: selecting the select one of the plurality of bit lines as a sensed node, and connecting the sensed node to a data line; signals on the sensed node and a reference line being pulled low, due to discharge capacitances of their respective memory array bit lines, when a word line corresponding to a selected memory bit cell becomes active; applying a charging pulse on the sensed node and the reference line, a width of the charging pulse being such that the reference line and the sensed node are drawn to a midpoint voltage; after applying the charging pulse, waiting a delay time before a sense amplifier senses a voltage difference between the data line and the reference line, the delay time sufficient to: (i) allow the reference line to be pulled towards a reference voltage, and (ii) allow the data line to be pulled towards a voltage level corresponding to a stored value in the selected memory bit cell on the select one of the plurality of bit lines. discharging a plurality of bit lines, BL, during an inactive memory access period; stopping the discharging of a select one of the plurality of bit lines during an active memory access period; during the active memory access period: selecting the select one of the plurality of bit lines as a sensed node, and connecting the sensed node to a data line; signals on the sensed node and a reference line being pulled low, due to discharge capacitances of their respective memory array bit lines, when a word line corresponding to a selected memory bit cell becomes active; applying a charging pulse on the sensed node and the reference line, a width of the charging pulse being such that the reference line and the sensed node are drawn to a midpoint voltage; after applying the charging pulse, waiting a delay time before a sense amplifier senses a voltage difference between the data line and the reference line, the delay time sufficient to: (i) allow the reference line to be pulled towards a reference voltage, and (ii) allow the data line to be pulled towards a voltage level corresponding to a stored value in the selected memory bit cell on the select one of the plurality of bit lines. selecting the select one of the plurality of bit lines as a sensed node, and connecting the sensed node to a data line; signals on the sensed node and a reference line being pulled low, due to discharge capacitances of their respective memory array bit lines, when a word line corresponding to a selected memory bit cell becomes active; applying a charging pulse on the sensed node and the reference line, a width of the charging pulse being such that the reference line and the sensed node are drawn to a midpoint voltage; after applying the charging pulse, waiting a delay time before a sense amplifier senses a voltage difference between the data line and the reference line, the delay time sufficient to: (i) allow the reference line to be pulled towards a reference voltage, and (ii) allow the data line to be pulled towards a voltage level corresponding to a stored value in the selected memory bit cell on the select one of the plurality of bit lines. (i) allow the reference line to be pulled towards a reference voltage, and (ii) allow the data line to be pulled towards a voltage level corresponding to a stored value in the selected memory bit cell on the select one of the plurality of bit lines.