A method of fabricating a multi-junction monolithically integrated photovoltaic device using a silicon-cell and module production compatible process, comprising: providing a silicon substrate (102; 250; 502; 602), the silicon substrate having a surface region; providing a first active cell (140A; 540A; 602) on the silicon substrate, the first active cell including a base (102; 502); subjecting the first active cell to thermal process to form a buried emitter region (104; 504) in the first active cell and to cause formation of a first surface region of the first active cell; cleaning the first surface region to be substantially free from organic or metallic contaminants; forming a termination layer overlying the first surface region, the termination layer being a thickness of a gallium and phosphide bearing epitaxially formed material provided using at least a MOCVD or HVPE or VPE process at a first temperature range and the thickness of the gallium and phosphide bearing epitaxial material characterized by a region having a threading dislocation density of 1 × 10 5 cm -2 to 1 × 10 7 cm -2; forming a tunnel junction region (142A; 542A; 604) overlying the buried emitter region, wherein the tunnel junction region comprises a doped gallium and phosphorous bearing layer; forming a back surface field region (114; 514) overlying the tunnel junction region; forming a second active cell (140B; 540B; 606) using a second temperature range, the second active cell overlying the back surface field region, the second active cell including a base (116; 518G) and an emitter (118; 520G), the second active cell formed from one or more III-V semiconductor layers and characterized by a threading dislocation density of 1 × 10 5 cm -2 to 1 × 10 7 cm -2; wherein the first active cell and the second active cell are characterized by a cell level efficiency of about 25% to 37%, and wherein the composition of the termination layer is from Al(50%)Ga(50%)P to Al(90%)Ga(10%)P. providing a silicon substrate (102; 250; 502; 602), the silicon substrate having a surface region; providing a first active cell (140A; 540A; 602) on the silicon substrate, the first active cell including a base (102; 502); subjecting the first active cell to thermal process to form a buried emitter region (104; 504) in the first active cell and to cause formation of a first surface region of the first active cell; cleaning the first surface region to be substantially free from organic or metallic contaminants; forming a termination layer overlying the first surface region, the termination layer being a thickness of a gallium and phosphide bearing epitaxially formed material provided using at least a MOCVD or HVPE or VPE process at a first temperature range and the thickness of the gallium and phosphide bearing epitaxial material characterized by a region having a threading dislocation density of 1 × 10 5 cm -2 to 1 × 10 7 cm -2; forming a tunnel junction region (142A; 542A; 604) overlying the buried emitter region, wherein the tunnel junction region comprises a doped gallium and phosphorous bearing layer; forming a back surface field region (114; 514) overlying the tunnel junction region; forming a second active cell (140B; 540B; 606) using a second temperature range, the second active cell overlying the back surface field region, the second active cell including a base (116; 518G) and an emitter (118; 520G), the second active cell formed from one or more III-V semiconductor layers and characterized by a threading dislocation density of 1 × 10 5 cm -2 to 1 × 10 7 cm -2; wherein the first active cell and the second active cell are characterized by a cell level efficiency of about 25% to 37%, and wherein the composition of the termination layer is from Al(50%)Ga(50%)P to Al(90%)Ga(10%)P.