A convolutional neural network, CNN, engine for an image processing system comprising: an image cache comprising an input port (din) and an output port (dout), said image cache being responsive to a request to read a block of NxM pixels extending from a specified location within an input map to provide said block of NxM pixels at said output port; a convolution engine being arranged to read weights for each layer of convolution processing from a weights cache, said set of weights associated with a given layer of a given CNN and being pre-calculated during a training phase of the CNN, and to read at least one block of NxM pixels from said image cache output port, to combine said at least one block of NxM pixels with a corresponding set of weights to provide a product, and to subject said product to an activation function to provide an output pixel value; said image cache being configured to write output pixel values to a specified write address via said image cache input port; said image cache comprising a plurality of interleaved memories (SRAM0...SRAM3), each memory storing a block of pixel values at a given memory address, the image cache being arranged to determine for a block of NxM pixels to be read from said image cache: a respective one address (Addr0...Addr3) within each of said interleaved memories in which said pixels of said block of NxM pixels are stored; a respective memory of said plurality of interleaved memories within which each pixel of said block of NxM pixels is stored; and a respective offset for each pixel of said block of NxM pixels within each memory address, so that said image cache can simultaneously provide said NxM pixels at said output port in a single clock cycle; and a controller arranged to provide a set of weights to said convolution engine before processing at least one input map, to cause said convolution engine to process said at least one input map by specifying locations for successive blocks of NxM pixels and to generate an output map within said image cache by writing said output pixel values to successive locations within said image cache. an image cache comprising an input port (din) and an output port (dout), said image cache being responsive to a request to read a block of NxM pixels extending from a specified location within an input map to provide said block of NxM pixels at said output port; a convolution engine being arranged to read weights for each layer of convolution processing from a weights cache, said set of weights associated with a given layer of a given CNN and being pre-calculated during a training phase of the CNN, and to read at least one block of NxM pixels from said image cache output port, to combine said at least one block of NxM pixels with a corresponding set of weights to provide a product, and to subject said product to an activation function to provide an output pixel value; said image cache being configured to write output pixel values to a specified write address via said image cache input port; said image cache comprising a plurality of interleaved memories (SRAM0...SRAM3), each memory storing a block of pixel values at a given memory address, the image cache being arranged to determine for a block of NxM pixels to be read from said image cache: a respective one address (Addr0...Addr3) within each of said interleaved memories in which said pixels of said block of NxM pixels are stored; a respective memory of said plurality of interleaved memories within which each pixel of said block of NxM pixels is stored; and a respective offset for each pixel of said block of NxM pixels within each memory address, so that said image cache can simultaneously provide said NxM pixels at said output port in a single clock cycle; and a controller arranged to provide a set of weights to said convolution engine before processing at least one input map, to cause said convolution engine to process said at least one input map by specifying locations for successive blocks of NxM pixels and to generate an output map within said image cache by writing said output pixel values to successive locations within said image cache.