A data storage method, comprising: generating, by controller circuitry (110, 430), metadata (134, 134A-134n, 142, 142A-142n) for each respective one of a plurality of lines of data (132, 132A-132n, 312) stored in memory circuitry (120, 130, 140, 510), the metadata (134, 134A-134n, 142, 142A-142n) including: data representative of a cryptographic message authentication code, MAC, associated with the respective line of data (132, 132A-132n, 312); and data representative of an error correction code, ECC (138A-n), associated with the respective line of data (132, 132A-132n, 312), the error correction code (138A-n) including at least an error detection data portion associated with the respective line of data (132, 132A-132n, 312) and an error correction data portion associated with the respective line of data (132, 132A-132n, 312); and apportioning, by the controller circuitry (110, 430), the metadata (134, 134A-134n, 142, 142A-142n) into a First Tier metadata portion stored in a first memory circuitry portion proximate the respective line of data (132, 132A-132n, 312) and a Second Tier metadata portion stored in a sequestered, second memory circuitry portion remote from the respective line of data (132, 132A-132n, 312); wherein the First Tier metadata portion includes at least the error detection data portion and the message authentication code of the metadata (134, 134A-134n, 142, 142A-142n) associated with the respective line of data (132, 132A-132n, 312); and wherein the Second Tier metadata portion includes at least a portion of the error correction data portion of the metadata (134, 134A-134n, 142, 142A-142n) associated with the respective line of data (132, 132A-132n, 312). generating, by controller circuitry (110, 430), metadata (134, 134A-134n, 142, 142A-142n) for each respective one of a plurality of lines of data (132, 132A-132n, 312) stored in memory circuitry (120, 130, 140, 510), the metadata (134, 134A-134n, 142, 142A-142n) including: data representative of a cryptographic message authentication code, MAC, associated with the respective line of data (132, 132A-132n, 312); and data representative of an error correction code, ECC (138A-n), associated with the respective line of data (132, 132A-132n, 312), the error correction code (138A-n) including at least an error detection data portion associated with the respective line of data (132, 132A-132n, 312) and an error correction data portion associated with the respective line of data (132, 132A-132n, 312); and data representative of a cryptographic message authentication code, MAC, associated with the respective line of data (132, 132A-132n, 312); and data representative of an error correction code, ECC (138A-n), associated with the respective line of data (132, 132A-132n, 312), the error correction code (138A-n) including at least an error detection data portion associated with the respective line of data (132, 132A-132n, 312) and an error correction data portion associated with the respective line of data (132, 132A-132n, 312); and apportioning, by the controller circuitry (110, 430), the metadata (134, 134A-134n, 142, 142A-142n) into a First Tier metadata portion stored in a first memory circuitry portion proximate the respective line of data (132, 132A-132n, 312) and a Second Tier metadata portion stored in a sequestered, second memory circuitry portion remote from the respective line of data (132, 132A-132n, 312); wherein the First Tier metadata portion includes at least the error detection data portion and the message authentication code of the metadata (134, 134A-134n, 142, 142A-142n) associated with the respective line of data (132, 132A-132n, 312); and wherein the Second Tier metadata portion includes at least a portion of the error correction data portion of the metadata (134, 134A-134n, 142, 142A-142n) associated with the respective line of data (132, 132A-132n, 312).