A method of reading a resistive memory bit cell, the method comprising: generating a load voltage at a gate of a mirror transistor, wherein the mirror transistor is diode-connected and coupled to a current mirror, wherein the current mirror supplies a constant current that is invariant with process-voltage-temperature variations; connecting a source/drain terminal of a voltage load transistor in series with a source/drain terminal of the mirror transistor; generating a data voltage by connecting the gate of the mirror transistor to a gate of a data load transistor, the data load transistor being coupled to the resistive memory bit cell, to provide the load voltage to the data load transistor such that the constant current is mirrored as sensing current flowing through the resistive memory bit cell; generating a degeneration voltage by connecting a gate of the voltage load transistor to a gate of a degeneration transistor, the degeneration transistor reducing variations in current through the data load transistor, wherein the degeneration transistor is coupled in series with a source terminal of the data load transistor; connecting the gate of the mirror transistor to gates of reference load transistors (218, 219) coupled to reference cells (230, 231), to provide the load voltage to the reference load transistors (218, 219) such that the constant current is mirrored as reference currents flowing through the reference cells (230, 231); connecting the gate of the voltage load transistor to gates of reference degeneration transistors (264, 265), wherein the reference degeneration transistors (264, 265) are connected in series with source terminals of the reference load transistors (218, 219); deriving a reference voltage at a common node which is coupled to first terminals of diode-connected reference clamp transistors (222, 223), the reference clamp transistors (222, 223) being coupled to the reference cells (230, 231), wherein second terminals and gates of the reference clamp transistors (222, 223) are connected to each other; and coupling the common node to a gate of a data clamp transistor coupled in series to the resistive memory bit cell. generating a load voltage at a gate of a mirror transistor, wherein the mirror transistor is diode-connected and coupled to a current mirror, wherein the current mirror supplies a constant current that is invariant with process-voltage-temperature variations; connecting a source/drain terminal of a voltage load transistor in series with a source/drain terminal of the mirror transistor; generating a data voltage by connecting the gate of the mirror transistor to a gate of a data load transistor, the data load transistor being coupled to the resistive memory bit cell, to provide the load voltage to the data load transistor such that the constant current is mirrored as sensing current flowing through the resistive memory bit cell; generating a degeneration voltage by connecting a gate of the voltage load transistor to a gate of a degeneration transistor, the degeneration transistor reducing variations in current through the data load transistor, wherein the degeneration transistor is coupled in series with a source terminal of the data load transistor; connecting the gate of the mirror transistor to gates of reference load transistors (218, 219) coupled to reference cells (230, 231), to provide the load voltage to the reference load transistors (218, 219) such that the constant current is mirrored as reference currents flowing through the reference cells (230, 231); connecting the gate of the voltage load transistor to gates of reference degeneration transistors (264, 265), wherein the reference degeneration transistors (264, 265) are connected in series with source terminals of the reference load transistors (218, 219); deriving a reference voltage at a common node which is coupled to first terminals of diode-connected reference clamp transistors (222, 223), the reference clamp transistors (222, 223) being coupled to the reference cells (230, 231), wherein second terminals and gates of the reference clamp transistors (222, 223) are connected to each other; and coupling the common node to a gate of a data clamp transistor coupled in series to the resistive memory bit cell.