A method for performing one or more tabular data manipulation operations, the method comprising: a data processing core (103a,..., 103g, 104a,..., 104g) on a chip coupled with a first memory on said chip pushing a particular memory address of a descriptor into a first register within a first register space on said chip that is accessible by a first set of electronic circuits on said chip that is coupled to said first memory; wherein the descriptor indicates a width of a column of tabular data, a number of rows of said column of tabular data, and one or more tabular data manipulation operations to perform on said column of tabular data; in response to said particular memory address of said descriptor being pushed into said first register by said data processing core (103a,..., 103g, 104a,..., 104g): the first set of electronic circuits, using the particular memory address in the first register, accessing the descriptor in the first memory; the first set of electronic circuits determining, based on the descriptor, control information indicating said one or more tabular data manipulation operations to perform on said column of tabular data; in response to determining the control information: the first set of electronic circuits transmitting, using a hardware data channel, the control information to a second set of electronic circuits on said chip to perform said one or more tabular data manipulation operations on said column of tabular data. a data processing core (103a,..., 103g, 104a,..., 104g) on a chip coupled with a first memory on said chip pushing a particular memory address of a descriptor into a first register within a first register space on said chip that is accessible by a first set of electronic circuits on said chip that is coupled to said first memory; wherein the descriptor indicates a width of a column of tabular data, a number of rows of said column of tabular data, and one or more tabular data manipulation operations to perform on said column of tabular data; memory on said chip pushing a particular memory address of a descriptor into a first register within a first register space on said chip that is accessible by a first set of electronic circuits on said chip that is coupled to said first memory; wherein the descriptor indicates a width of a column of tabular data, a number of rows of said column of tabular data, and one or more tabular data manipulation operations to perform on said column of tabular data; in response to said particular memory address of said descriptor being pushed into said first register by said data processing core (103a,..., 103g, 104a,..., 104g): the first set of electronic circuits, using the particular memory address in the first register, accessing the descriptor in the first memory; the first set of electronic circuits determining, based on the descriptor, control information indicating said one or more tabular data manipulation operations to perform on said column of tabular data; the first set of electronic circuits, using the particular memory address in the first register, accessing the descriptor in the first memory; the first set of electronic circuits determining, based on the descriptor, control information indicating said one or more tabular data manipulation operations to perform on said column of tabular data; in response to determining the control information: the first set of electronic circuits transmitting, using a hardware data channel, the control information to a second set of electronic circuits on said chip to perform said one or more tabular data manipulation operations on said column of tabular data.