A method for simulating multiple processors, comprising: Mapping, by a scheduler, debug interface information of a to-be-simulated processor requiring debugging onto the scheduler; Creating, by the scheduler, at least one slave thread according to a configuration file by using a master thread, and determining to-be-simulated processors corresponding to the master thread and the at least one slave thread, wherein each thread corresponds to one or more to-be-simulated processors, the to-be-simulated processor corresponding to the master thread comprises the to-be-simulated processor requiring debugging; wherein the maximum number of the slave threads is equal to a result obtained by subtracting 1 from the number of processors of a host machine where the scheduler is located, and each thread corresponds to one processor of the host machine; the configuration file comprises the number of the slave threads, number information of the to-be-simulated processor requiring debugging and a mapping relationship between the thread and the to-be-simulated processor; and Invoking, by the scheduler, by using the master thread and the at least one slave thread via a first execute interface, the to-be-simulated processors to execute a corresponding instruction, and debugging the to-be-simulated processor requiring debugging by using the master thread via a debug interface of the to-be-simulated processor requiring debugging, wherein the first execute interface registers with the scheduler through the to-be-simulated processors, and the debug interface information points to the debug interface; wherein the mapping step comprises at least one the following situations: assigning, by the scheduler, an address of a single-step interface of the to-be-simulated processor requiring debugging to a single-step interface pointer of the scheduler; assigning, by the scheduler, an address of a status query interface of the to-be-simulated processor requiring debugging to a status query interface pointer of the scheduler; and assigning, by the scheduler, an address of a status setting interface of the to-be-simulated processor requiring debugging to a status setting interface pointer of the scheduler; wherein the method further comprises: delivering, by the scheduler, by using the master thread and the at least one slave thread via a first cycle interface, a cycle parameter to the to-be-simulated processors, so as to control the scheduler to synchronously invoke, by using the master thread and the at least one slave thread, the to-be-simulated processors, wherein the first cycle interface registers with the scheduler through the to-be-simulated processors. Mapping, by a scheduler, debug interface information of a to-be-simulated processor requiring debugging onto the scheduler; Creating, by the scheduler, at least one slave thread according to a configuration file by using a master thread, and determining to-be-simulated processors corresponding to the master thread and the at least one slave thread, wherein each thread corresponds to one or more to-be-simulated processors, the to-be-simulated processor corresponding to the master thread comprises the to-be-simulated processor requiring debugging; wherein the maximum number of the slave threads is equal to a result obtained by subtracting 1 from the number of processors of a host machine where the scheduler is located, and each thread corresponds to one processor of the host machine; the configuration file comprises the number of the slave threads, number information of the to-be-simulated processor requiring debugging and a mapping relationship between the thread and the to-be-simulated processor; and Invoking, by the scheduler, by using the master thread and the at least one slave thread via a first execute interface, the to-be-simulated processors to execute a corresponding instruction, and debugging the to-be-simulated processor requiring debugging by using the master thread via a debug interface of the to-be-simulated processor requiring debugging, wherein the first execute interface registers with the scheduler through the to-be-simulated processors, and the debug interface information points to the debug interface; assigning, by the scheduler, an address of a single-step interface of the to-be-simulated processor requiring debugging to a single-step interface pointer of the scheduler; assigning, by the scheduler, an address of a status query interface of the to-be-simulated processor requiring debugging to a status query interface pointer of the scheduler; and assigning, by the scheduler, an address of a status setting interface of the to-be-simulated processor requiring debugging to a status setting interface pointer of the scheduler; delivering, by the scheduler, by using the master thread and the at least one slave thread via a first cycle interface, a cycle parameter to the to-be-simulated processors, so as to control the scheduler to synchronously invoke, by using the master thread and the at least one slave thread, the to-be-simulated processors, wherein the first cycle interface registers with the scheduler through the to-be-simulated processors.