A method for recognizing an order of signals, consisting in detecting, by means of a main MUTEX circuit, executed during an analog-to-digital conversion step used to determine a value of a bit having index x of an n-bit output digital word, that a source signal was the first to enter its active state, or that a reference signal was the first to enter its active state, and signaling by means of a first output of the main MUTEX circuit to a path configuration circuit that the source signal was the first to enter its active state, or signaling by means of a second output of the main MUTEX circuit to the path configuration circuit, that the reference signal was the first to enter its active state, wherein the source signal is fed by means of a first delay circuit to an input of a source path of the path configuration circuit and simultaneously the reference signal is fed by means of a second delay circuit to an input of a reference path of the path configuration circuit, wherein propagation time of the first delay circuit is equal to propagation time of the second delay circuit and is longer than a nominal propagation delay of the main MUTEX circuit, characterized in that metastability of the main MUTEX circuit (MM x) is detected by means of an additional MUTEX circuit (MA x), by controlling the delay with which the first output of the main MUTEX circuit (MM x) or a second output of the main MUTEX circuit (MM x) is put into active state by means of the main MUTEX circuit (MM x), relative to the time in which the source signal (Sc x) was the first to enter its active state or the reference signal (Rf x) was the first to enter its active state, wherein the metastability of the main MUTEX circuit (MM x) is signaled by means of the additional MUTEX circuit (MA x) by bringing a second output of the additional MUTEX circuit (MAx) into active state, whereas entering active state by the source signal (Sc x) or entering active state by the reference signal (Rf x) is detected by means of a first gate (B1 x) and is signaled by means of an additional delay circuit (T Dx) to the additional MUTEX circuit (MA x), bringing a reset input of the additional MUTEX circuit (MA x) into active state, wherein propagation time (to) of the additional delay circuit (T Dx) is shorter than the propagation time (t M) of the first delay circuit (t M1x) and simultaneously is longer than the nominal propagation delay (t N) of the main MUTEX circuit (MM x), whereas entering active state by the first output of the main MUTEX circuit (MMx) or entering active state by the second output of the main MUTEX circuit (MM x) is detected and is signaled by means of a second gate (B2 x) to the additional MUTEX circuit (MA x), bringing a set input of the additional MUTEX circuit (MA x) into active state, whereas to the bit having index x (b x) of the n-bit output digital word a value is assigned by means of an output module in such a way that if during the analog-to-digital conversion step used to determine the value of the bit having index x (b x) of the n-bit output digital word metastability of the main MUTEX circuit (MM x) is signaled by means of the additional MUTEX circuit (MA x) and a priority input (Prt x) of the output module is put into active state by means of the second output of the additional MUTEX circuit (MA x), then to the bit having index x (b x) and to all possible less significant bits (b x-1,..., b 0) of the n-bit output digital word default logical states are assigned by means of the output module and simultaneously the state indicated by means of the first output of the main MUTEX circuit (MM x) to a data input (D x) of the output module is ignored by the output module during this and any subsequent analog-to-digital conversion steps, if, however, during the analog-to-digital conversion step used to determine the value of the bit having index x (b x) of the n-bit output digital word metastability of the main MUTEX circuit (MMx) is not signaled by means of the additional MUTEX circuit (MA x) and the priority input (Prt x) of the output module is kept in inactive state by means of the second output of the additional MUTEX circuit (MA x) and metastability is not signaled during any of possible earlier analog-to-digital conversion steps used to determine values of more significant bits (b n-1,..., b x+1) of the n-bit output digital word, then to the bit having index x (b x) of the n-bit output digital word a logical state according to the state of the data input (D x) of the output module is assigned by means of the output module, in such a way that if the data input (D x) of the output module is put into active state by means of the first output of the main MUTEX circuit (MM x), then to the bit having index x (b x) of the n-bit output digital word a logical state one is assigned by means of the output module, and otherwise, when the data input (D x) of the output module is kept in the inactive state by means of the first output of the main MUTEX circuit (MMx), to the bit having index x (b x) of the n-bit output digital word a logical state zero is assigned by means of the output module.