A circuit comprising: an input register configured to receive an input vector of input elements; a control register configured to receive a control vector of control elements, wherein each control element of the control vector corresponds to a respective output element of an output vector of output elements corresponding to a permutation of the input vector, and wherein each control element of the control vector specifies a permutation of an input element of the input vector, the permutation specifying a number of positions to rotate the input element of the input vector; a permute execution circuit configured to generate the output vector, wherein generating each output element of the output vector comprises: accessing, at a particular position of the control register, a particular control element of the control vector corresponding to a particular position of the output vector; selecting a particular position of the input register based on the particular control element of the control vector corresponding to the particular position of the output vector; accessing, at the particular position of the input register, a particular input element of the input vector; and outputting the particular input element of the input vector as an output element at the particular position of the output vector; and a flattening register configured to receive information indicating a size of the input vector; receive, in the flattening register, the input vector as a staggered input such that each input element of the input vector is received at each cycle in an order beginning with a lowest-order bit position of the input vector; and pop, from the flattening register and to the input register, all received input elements simultaneously once valid data in a bit corresponding to the size of the input vector is received. an input register configured to receive an input vector of input elements; a control register configured to receive a control vector of control elements, wherein each control element of the control vector corresponds to a respective output element of an output vector of output elements corresponding to a permutation of the input vector, and wherein each control element of the control vector specifies a permutation of an input element of the input vector, the permutation specifying a number of positions to rotate the input element of the input vector; a permute execution circuit configured to generate the output vector, wherein generating each output element of the output vector comprises: accessing, at a particular position of the control register, a particular control element of the control vector corresponding to a particular position of the output vector; selecting a particular position of the input register based on the particular control element of the control vector corresponding to the particular position of the output vector; accessing, at the particular position of the input register, a particular input element of the input vector; and outputting the particular input element of the input vector as an output element at the particular position of the output vector; and accessing, at a particular position of the control register, a particular control element of the control vector corresponding to a particular position of the output vector; selecting a particular position of the input register based on the particular control element of the control vector corresponding to the particular position of the output vector; accessing, at the particular position of the input register, a particular input element of the input vector; and outputting the particular input element of the input vector as an output element at the particular position of the output vector; and a flattening register configured to receive information indicating a size of the input vector; receive, in the flattening register, the input vector as a staggered input such that each input element of the input vector is received at each cycle in an order beginning with a lowest-order bit position of the input vector; and pop, from the flattening register and to the input register, all received input elements simultaneously once valid data in a bit corresponding to the size of the input vector is received. receive information indicating a size of the input vector; receive, in the flattening register, the input vector as a staggered input such that each input element of the input vector is received at each cycle in an order beginning with a lowest-order bit position of the input vector; and pop, from the flattening register and to the input register, all received input elements simultaneously once valid data in a bit corresponding to the size of the input vector is received.