A stacked die CMOS image sensor comprising: a sensor die having a sensor array and opposing faces, a sensor die upper face and a sensor die lower face, wherein the sensor array has a first set and a second set of opposing sides, the first set being a top edge and a bottom edge, the second set being a first edge and a second edge extending from the top edge to the bottom edge of the first set, wherein a height direction is defined between the top edge and the bottom edge and wherein a width direction is defined between the first edge and the second edge; an analog-to-digital conversion, ADC, module comprising first and second ADC submodules (27a, 27b), wherein the first ADC submodule is disposed adjacent to the sensor array and directly adjacent to the first edge, wherein the second ADC submodule is disposed adjacent to the sensor array and directly adjacent to the second edge, wherein the first ADC submodule is configured to convert an output of pixels in odd numbered columns to a digital output, wherein the second ADC submodule is configured to convert an output of the pixels in even numbered columns to a digital output, wherein the ADC module combines the output of the even numbered columns and the output of the odd numbered columns to generate a column-by-column image format, and wherein the first and second ADC submodules (27a, 27b) are positioned directly adjacent to the first edge and the second edge respectively, to minimize a height of the stacked die CMOS sensor; a memory die, the memory die having a first opposing face that is adjacent to the sensor die lower face, wherein the memory die is electrically connected to the sensor die through silicon vias; a processing die that is electrically connected to the memory die through silicon vias, wherein the processing die comprises a central processing unit that is configured to output digital image data; a video sequence converter, located on the memory die or the processing die, that is electrically connected to the output of the sensor die through silicon vias, wherein the video sequence converter is configured to convert the digital image data in the column-by-column image format to digital image data in a row-by-row image format and output the digital image data in the row-by-row image format; a digital logic circuit forming a first row, a timing and clock control circuit; and an analog signal processing circuit; the timing and clock control circuit and the analog signal processing circuit being adjacent and forming a second row; and the first row and the second row extending in the height direction, having similar dimensions and being disposed adjacent the first ADC submodule and the second ADC submodule in the width direction, respectively. a sensor die having a sensor array and opposing faces, a sensor die upper face and a sensor die lower face, wherein the sensor array has a first set and a second set of opposing sides, the first set being a top edge and a bottom edge, the second set being a first edge and a second edge extending from the top edge to the bottom edge of the first set, wherein a height direction is defined between the top edge and the bottom edge and wherein a width direction is defined between the first edge and the second edge; an analog-to-digital conversion, ADC, module comprising first and second ADC submodules (27a, 27b), wherein the first ADC submodule is disposed adjacent to the sensor array and directly adjacent to the first edge, wherein the second ADC submodule is disposed adjacent to the sensor array and directly adjacent to the second edge, wherein the first ADC submodule is configured to convert an output of pixels in odd numbered columns to a digital output, wherein the second ADC submodule is configured to convert an output of the pixels in even numbered columns to a digital output, wherein the ADC module combines the output of the even numbered columns and the output of the odd numbered columns to generate a column-by-column image format, and wherein the first and second ADC submodules (27a, 27b) are positioned directly adjacent to the first edge and the second edge respectively, to minimize a height of the stacked die CMOS sensor; a memory die, the memory die having a first opposing face that is adjacent to the sensor die lower face, wherein the memory die is electrically connected to the sensor die through silicon vias; a processing die that is electrically connected to the memory die through silicon vias, wherein the processing die comprises a central processing unit that is configured to output digital image data; a video sequence converter, located on the memory die or the processing die, that is electrically connected to the output of the sensor die through silicon vias, wherein the video sequence converter is configured to convert the digital image data in the column-by-column image format to digital image data in a row-by-row image format and output the digital image data in the row-by-row image format; a digital logic circuit forming a first row, a timing and clock control circuit; and an analog signal processing circuit; the timing and clock control circuit and the analog signal processing circuit being adjacent and forming a second row; and the first row and the second row extending in the height direction, having similar dimensions and being disposed adjacent the first ADC submodule and the second ADC submodule in the width direction, respectively.