A solid-state imaging apparatus comprising: a plurality of pixels arranged in a matrix, each of the plurality of pixels including a photoelectric conversion element; a reference signal generating circuit, arranged in common for the plurality of columns of the pixels, configured to generate, as a reference signal, a ramp signal of which a signal level changes over time with a slope; a counter circuit configured to perform a counting operation according to the change of the reference signal; and a plurality of AD converting circuits, each arranged for a corresponding column of the pixels, configured to perform analog-to-digital conversion to a pixel signal transferred from the pixel by comparing the pixel signal with the reference signal, wherein each of the plurality of AD converting circuits includes a comparator having a first input terminal, which is connected to a column of pixels for inputting the pixel signal, and a second input terminal, which is connected to the reference signal generating circuit for inputting the reference signal, and a storing unit configured to store a count value of the counter circuit when an output of the comparator is inverted, characterized in that each of the plurality of AD converting circuits further includes a slope converting circuit for adjusting the slope of the reference signal, including a first capacitor connected between an output terminal of the reference signal generating circuit and the second input terminal of the comparator, at least one second capacitor (C22, C51, C60/C61) connected between the second input terminal of the comparator and a reference voltage, and a first switch (24, 53, 62/63) configured to electrically separate the connection between the second input terminal of the comparator and the reference voltage via the at least one second capacitor. a plurality of pixels arranged in a matrix, each of the plurality of pixels including a photoelectric conversion element; a reference signal generating circuit, arranged in common for the plurality of columns of the pixels, configured to generate, as a reference signal, a ramp signal of which a signal level changes over time with a slope; a counter circuit configured to perform a counting operation according to the change of the reference signal; and a plurality of AD converting circuits, each arranged for a corresponding column of the pixels, configured to perform analog-to-digital conversion to a pixel signal transferred from the pixel by comparing the pixel signal with the reference signal, wherein each of the plurality of AD converting circuits includes a comparator having a first input terminal, which is connected to a column of pixels for inputting the pixel signal, and a second input terminal, which is connected to the reference signal generating circuit for inputting the reference signal, and a storing unit configured to store a count value of the counter circuit when an output of the comparator is inverted, a comparator having a first input terminal, which is connected to a column of pixels for inputting the pixel signal, and a second input terminal, which is connected to the reference signal generating circuit for inputting the reference signal, and a storing unit configured to store a count value of the counter circuit when an output of the comparator is inverted, characterized in that each of the plurality of AD converting circuits further includes a slope converting circuit for adjusting the slope of the reference signal, including a first capacitor connected between an output terminal of the reference signal generating circuit and the second input terminal of the comparator, at least one second capacitor (C22, C51, C60/C61) connected between the second input terminal of the comparator and a reference voltage, and a first switch (24, 53, 62/63) configured to electrically separate the connection between the second input terminal of the comparator and the reference voltage via the at least one second capacitor. a slope converting circuit for adjusting the slope of the reference signal, including a first capacitor connected between an output terminal of the reference signal generating circuit and the second input terminal of the comparator, at least one second capacitor (C22, C51, C60/C61) connected between the second input terminal of the comparator and a reference voltage, and a first switch (24, 53, 62/63) configured to electrically separate the connection between the second input terminal of the comparator and the reference voltage via the at least one second capacitor.