A clock and data recovery circuit, comprising: an injection locked oscillator configured to generate a recovered clock signal, the injection locked oscillator comprising: an oscillator (104a, 104b); and an injection switch coupled to the oscillator (104a, 104b); a pulse generator coupled to the injection locked oscillator and configured to generate a pulse signal according to input data for controlling the injection locked oscillator; a sampler coupled to the input data and the injection locked oscillator and configured to sample the input data according to the recovered clock signal; and a frequency locked loop coupled to the injection locked oscillator and configured to correct a frequency error in the injection locked oscillator; characterized in that the oscillator is a two stage ring oscillator; and the frequency locked loop comprises: a sample and hold circuit coupled to the pulse generator and the injection locked oscillator and configured to sample a voltage of an injection terminal of the injection locked oscillator and store the voltage in a hold capacitor according to an even cycle or an odd cycle of the injection locked oscillator; and a loop filter configured to receive a voltage from the sample and hold circuit and generate a control voltage (Vctrl) to control the injection lock oscillator; the loop filter further controls the bandwidth of the frequency locked loop such that the bandwidth of the frequency locked loop is low enough to avoid disturbing injection locking of the clock and data recovery circuit. an injection locked oscillator configured to generate a recovered clock signal, the injection locked oscillator comprising: an oscillator (104a, 104b); and an injection switch coupled to the oscillator (104a, 104b); an oscillator (104a, 104b); and an injection switch coupled to the oscillator (104a, 104b); a pulse generator coupled to the injection locked oscillator and configured to generate a pulse signal according to input data for controlling the injection locked oscillator; a sampler coupled to the input data and the injection locked oscillator and configured to sample the input data according to the recovered clock signal; and a frequency locked loop coupled to the injection locked oscillator and configured to correct a frequency error in the injection locked oscillator; characterized in that the oscillator is a two stage ring oscillator; and the frequency locked loop comprises: a sample and hold circuit coupled to the pulse generator and the injection locked oscillator and configured to sample a voltage of an injection terminal of the injection locked oscillator and store the voltage in a hold capacitor according to an even cycle or an odd cycle of the injection locked oscillator; and a loop filter configured to receive a voltage from the sample and hold circuit and generate a control voltage (Vctrl) to control the injection lock oscillator; the loop filter further controls the bandwidth of the frequency locked loop such that the bandwidth of the frequency locked loop is low enough to avoid disturbing injection locking of the clock and data recovery circuit. a sample and hold circuit coupled to the pulse generator and the injection locked oscillator and configured to sample a voltage of an injection terminal of the injection locked oscillator and store the voltage in a hold capacitor according to an even cycle or an odd cycle of the injection locked oscillator; and a loop filter configured to receive a voltage from the sample and hold circuit and generate a control voltage (Vctrl) to control the injection lock oscillator; the loop filter further controls the bandwidth of the frequency locked loop such that the bandwidth of the frequency locked loop is low enough to avoid disturbing injection locking of the clock and data recovery circuit.