A method, comprising a) simulating execution of an image processing application software program having a plurality of kernels, each kernel comprising load instructions (LD_1, LD_2, LD_3) that read from a line buffer (201_1, 201_2,..., 201_M) storing data produced by another kernel, store instructions (ST_1, ST_2) that write to a line buffer (201_1, 201_2,..., 201_M) storing data to be consumed by another kernel or both, wherein simulating the execution of the image processing application software program comprises: creating a model (K1, K2, K3, K4) of each kernel by stripping each kernel down to its load and store instructions; intercepting communications between the kernel models (K1, K2, K3, K4) with line buffer models (304_1, 304_2, 304_3, 304_4) that store and forward lines of image data communicated from models (K1, K2, K3, K4) of producing kernels to models (K1, K2, K3, K4) of consuming kernels to thereby simulate operations of the plurality of line buffers (201_1, 201_2,..., 201_M) using the respective plurality of line buffer models (304_1, 304_2, 304_3, 304_4), the simulating further comprising tracking respective amounts of image data stored in the respective line buffer models (304_1, 304_2, 304_3, 304_4) over a simulation runtime; and imposing a write policy that prevents a next unit of image data from being written into a line buffer model (304_1, 304_2, 304_3, 304_4) until one or more models (K1, K2, K3, K4) of kernels that consume the image data are waiting to receive the next unit of the image data; b) determining respective hardware memory allocations for corresponding hardware line buffers (201_1, 201_2,..., 201_M) from the tracked respective amounts of image data; and c) generating configuration information for an image processor to execute the image processing application software program, the configuration information describing the hardware memory allocations for the hardware line buffers (201_1, 201_2,..., 201_M) of the image processor. a) simulating execution of an image processing application software program having a plurality of kernels, each kernel comprising load instructions (LD_1, LD_2, LD_3) that read from a line buffer (201_1, 201_2,..., 201_M) storing data produced by another kernel, store instructions (ST_1, ST_2) that write to a line buffer (201_1, 201_2,..., 201_M) storing data to be consumed by another kernel or both, wherein simulating the execution of the image processing application software program comprises: creating a model (K1, K2, K3, K4) of each kernel by stripping each kernel down to its load and store instructions; intercepting communications between the kernel models (K1, K2, K3, K4) with line buffer models (304_1, 304_2, 304_3, 304_4) that store and forward lines of image data communicated from models (K1, K2, K3, K4) of producing kernels to models (K1, K2, K3, K4) of consuming kernels to thereby simulate operations of the plurality of line buffers (201_1, 201_2,..., 201_M) using the respective plurality of line buffer models (304_1, 304_2, 304_3, 304_4), the simulating further comprising tracking respective amounts of image data stored in the respective line buffer models (304_1, 304_2, 304_3, 304_4) over a simulation runtime; and imposing a write policy that prevents a next unit of image data from being written into a line buffer model (304_1, 304_2, 304_3, 304_4) until one or more models (K1, K2, K3, K4) of kernels that consume the image data are waiting to receive the next unit of the image data; creating a model (K1, K2, K3, K4) of each kernel by stripping each kernel down to its load and store instructions; intercepting communications between the kernel models (K1, K2, K3, K4) with line buffer models (304_1, 304_2, 304_3, 304_4) that store and forward lines of image data communicated from models (K1, K2, K3, K4) of producing kernels to models (K1, K2, K3, K4) of consuming kernels to thereby simulate operations of the plurality of line buffers (201_1, 201_2,..., 201_M) using the respective plurality of line buffer models (304_1, 304_2, 304_3, 304_4), the simulating further comprising tracking respective amounts of image data stored in the respective line buffer models (304_1, 304_2, 304_3, 304_4) over a simulation runtime; and imposing a write policy that prevents a next unit of image data from being written into a line buffer model (304_1, 304_2, 304_3, 304_4) until one or more models (K1, K2, K3, K4) of kernels that consume the image data are waiting to receive the next unit of the image data; b) determining respective hardware memory allocations for corresponding hardware line buffers (201_1, 201_2,..., 201_M) from the tracked respective amounts of image data; and c) generating configuration information for an image processor to execute the image processing application software program, the configuration information describing the hardware memory allocations for the hardware line buffers (201_1, 201_2,..., 201_M) of the image processor.