A stacked integrated circuit system (10, 30, 60) comprising: a substrate (12, 32, 70) defining a substrate major surface (13, 33, 71); a contour support (14, 36, 72) comprising: a first support frame (15A, 55A, 87A) attached to the substrate major surface and defining a first lateral contact surface (28A, 56A, 88A) substantially orthogonal to the substrate major surface; a support plate (26, 54A, 84A) comprising a support plate major surface (29, 59A, 85A) that is substantially parallel to the substrate major surface, wherein the support plate is on the first support frame; and a second support frame (15B, 55B, 87B) defining a second lateral contact surface (28B, 56B, 89A) substantially orthogonal to the substrate major surface, wherein the second support frame is on the support plate such that the support plate is between the first and second support frames, and wherein the second lateral contact surface is set back from the first lateral contact surface measured in a lateral direction substantially parallel to the substrate major surface; a first integrated circuit die (16A, 38A, 62C) comprising a first integrated circuit die major surface (27A, 58A) wherein the first integrated circuit die major surface is substantially parallel to the substrate major surface and a first side of the first integrated circuit die abuts the first lateral contact surface, such that at least a portion of the first integrated circuit die is between the support plate and the substrate major surface; and a second integrated circuit die (16B, 38B, 64C) comprising a second integrated circuit die major surface (27B, 58B), wherein the second integrated circuit die major surface is substantially parallel to the substrate major surface and a first side of the second integrated circuit die abuts the second lateral contact surface, such that at least a portion of the first integrated circuit die and at least a portion of the support plate are between the second integrated circuit die and the substrate major surface. a substrate (12, 32, 70) defining a substrate major surface (13, 33, 71); a contour support (14, 36, 72) comprising: a first support frame (15A, 55A, 87A) attached to the substrate major surface and defining a first lateral contact surface (28A, 56A, 88A) substantially orthogonal to the substrate major surface; a support plate (26, 54A, 84A) comprising a support plate major surface (29, 59A, 85A) that is substantially parallel to the substrate major surface, wherein the support plate is on the first support frame; and a second support frame (15B, 55B, 87B) defining a second lateral contact surface (28B, 56B, 89A) substantially orthogonal to the substrate major surface, wherein the second support frame is on the support plate such that the support plate is between the first and second support frames, and wherein the second lateral contact surface is set back from the first lateral contact surface measured in a lateral direction substantially parallel to the substrate major surface; a first support frame (15A, 55A, 87A) attached to the substrate major surface and defining a first lateral contact surface (28A, 56A, 88A) substantially orthogonal to the substrate major surface; a support plate (26, 54A, 84A) comprising a support plate major surface (29, 59A, 85A) that is substantially parallel to the substrate major surface, wherein the support plate is on the first support frame; and a second support frame (15B, 55B, 87B) defining a second lateral contact surface (28B, 56B, 89A) substantially orthogonal to the substrate major surface, wherein the second support frame is on the support plate such that the support plate is between the first and second support frames, and wherein the second lateral contact surface is set back from the first lateral contact surface measured in a lateral direction substantially parallel to the substrate major surface; a first integrated circuit die (16A, 38A, 62C) comprising a first integrated circuit die major surface (27A, 58A) wherein the first integrated circuit die major surface is substantially parallel to the substrate major surface and a first side of the first integrated circuit die abuts the first lateral contact surface, such that at least a portion of the first integrated circuit die is between the support plate and the substrate major surface; and a second integrated circuit die (16B, 38B, 64C) comprising a second integrated circuit die major surface (27B, 58B), wherein the second integrated circuit die major surface is substantially parallel to the substrate major surface and a first side of the second integrated circuit die abuts the second lateral contact surface, such that at least a portion of the first integrated circuit die and at least a portion of the support plate are between the second integrated circuit die and the substrate major surface.