A system for transferring data between programmable logic devices, comprising: a first programmable logic device (12, 40a), comprising: a first portion associated with a first function block configured to process a first set of data; and first network on chip, NOC, circuitry configured to receive the processed first set of data and transfer the processed first set of data to a first node of the first NOC circuitry; and a second programmable logic device, comprising: second NOC circuitry configured to: receive the processed first set of data via the first node and a second node of the second NOC circuitry; and transfer the processed first set of data to a second portion of the second programmable logic device (12, 40b) associated with a second function block, characterized in that the first function block is configured to process the first set of data according to a string of virtual functions that defines an order in which the first set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first function block and a second virtual function identifier associated with the second function block. a first programmable logic device (12, 40a), comprising: a first portion associated with a first function block configured to process a first set of data; and first network on chip, NOC, circuitry configured to receive the processed first set of data and transfer the processed first set of data to a first node of the first NOC circuitry; and a first portion associated with a first function block configured to process a first set of data; and first network on chip, NOC, circuitry configured to receive the processed first set of data and transfer the processed first set of data to a first node of the first NOC circuitry; and a second programmable logic device, comprising: second NOC circuitry configured to: receive the processed first set of data via the first node and a second node of the second NOC circuitry; and transfer the processed first set of data to a second portion of the second programmable logic device (12, 40b) associated with a second function block, characterized in that the first function block is configured to process the first set of data according to a string of virtual functions that defines an order in which the first set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first function block and a second virtual function identifier associated with the second function block. receive the processed first set of data via the first node and a second node of the second NOC circuitry; and transfer the processed first set of data to a second portion of the second programmable logic device (12, 40b) associated with a second function block, characterized in that the first function block is configured to process the first set of data according to a string of virtual functions that defines an order in which the first set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first function block and a second virtual function identifier associated with the second function block.