A fabrication method of a field-effect transistor, comprising: forming a support structure on a semiconductor substrate, wherein the support structure is a fin support structure comprising a strictly periodic multi-layer film that comprises a first semiconductor material layer and a second semiconductor material layer that are alternately disposed in a direction extending from the semiconductor substrate, wherein the first semiconductor material layer and the second semiconductor material layer each has a thickness in a range from several nanometers to tens of nanometers, and an isolation layer is disposed in the semiconductor substrate on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, wherein a length of the dummy gate structure in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction, and the gate length direction is used to indicate a transport direction of a carrier in the field-effect transistor; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove, wherein the sacrificial layer is a projection area of the dummy gate structure in the first semiconductor material layer along a target direction, a dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of the first semiconductor material layer, and the target direction is a direction perpendicular to a bottom of the semiconductor substrate; forming a source _and a drain in a preset source drain area along the gate length direction, wherein the source and the drain are isolated from the sacrificial layer through the insulation groove; and removing the dummy gate structure and the sacrificial layer, characterized by further comprising, after removing the dummy gate structure and the sacrificial layer, reducing a thickness of the second semiconductor material, in a channel area, along a gate structure cross-sectional direction, where the gate structure cross-sectional direction is perpendicular to the gate length direction. forming a support structure on a semiconductor substrate, wherein the support structure is a fin support structure comprising a strictly periodic multi-layer film that comprises a first semiconductor material layer and a second semiconductor material layer that are alternately disposed in a direction extending from the semiconductor substrate, wherein the first semiconductor material layer and the second semiconductor material layer each has a thickness in a range from several nanometers to tens of nanometers, and an isolation layer is disposed in the semiconductor substrate on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, wherein a length of the dummy gate structure in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction, and the gate length direction is used to indicate a transport direction of a carrier in the field-effect transistor; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove, wherein the sacrificial layer is a projection area of the dummy gate structure in the first semiconductor material layer along a target direction, a dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of the first semiconductor material layer, and the target direction is a direction perpendicular to a bottom of the semiconductor substrate; forming a source _and a drain in a preset source drain area along the gate length direction, wherein the source and the drain are isolated from the sacrificial layer through the insulation groove; and removing the dummy gate structure and the sacrificial layer, characterized by further comprising, after removing the dummy gate structure and the sacrificial layer, reducing a thickness of the second semiconductor material, in a channel area, along a gate structure cross-sectional direction, where the gate structure cross-sectional direction is perpendicular to the gate length direction.