A graphics processor (234, 700) comprising: a memory device (224, 714); a level-two, L2, cache memory and a raster operations unit, ROP, coupled with the memory device (224, 714); a compressor to perform lossless compression on data to be written to the memory device (224, 714) using one or more of multiple compression algorithms, the one or more compression algorithms to be used by the compressor being selected based on statistical characteristics of the data to be compressed; and a streaming multiprocessor coupled with the memory device (224, 714), the streaming multiprocessor to concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread, SIMT, architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions; wherein the multiple instructions include a first instruction to be decoded into a first decoded instruction via an instruction decoder of the graphics processor (234, 700), the first decoded instruction to cause at least a first portion of the streaming multiprocessor to perform a floating-point operation on multiple floating-point input operands, and a second instruction to be decoded into a second decoded instruction via the instruction decoder, the second decoded instruction to cause at least a second portion of the streaming multiprocessor to perform an integer operation on multiple integer operands, the first instruction to execute concurrently with the second instruction; and wherein the multiple instructions include a third instruction to be decoded into a third decoded instruction via the instruction decoder and the streaming multiprocessor includes a mixed precision core to perform operations for the third decoded instruction, the mixed precision core to perform a first operation of the third decoded instruction at a first precision and a second operation of the third decoded instruction at a second precision, the first operation is an operation having two or more 16-bit floating-point inputs, and the second operation is an operation having two or more 32-bit floating-point inputs. a memory device (224, 714); a level-two, L2, cache memory and a raster operations unit, ROP, coupled with the memory device (224, 714); a compressor to perform lossless compression on data to be written to the memory device (224, 714) using one or more of multiple compression algorithms, the one or more compression algorithms to be used by the compressor being selected based on statistical characteristics of the data to be compressed; and a streaming multiprocessor coupled with the memory device (224, 714), the streaming multiprocessor to concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread, SIMT, architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions; wherein the multiple instructions include a first instruction to be decoded into a first decoded instruction via an instruction decoder of the graphics processor (234, 700), the first decoded instruction to cause at least a first portion of the streaming multiprocessor to perform a floating-point operation on multiple floating-point input operands, and a second instruction to be decoded into a second decoded instruction via the instruction decoder, the second decoded instruction to cause at least a second portion of the streaming multiprocessor to perform an integer operation on multiple integer operands, the first instruction to execute concurrently with the second instruction; and wherein the multiple instructions include a third instruction to be decoded into a third decoded instruction via the instruction decoder and the streaming multiprocessor includes a mixed precision core to perform operations for the third decoded instruction, the mixed precision core to perform a first operation of the third decoded instruction at a first precision and a second operation of the third decoded instruction at a second precision, the first operation is an operation having two or more 16-bit floating-point inputs, and the second operation is an operation having two or more 32-bit floating-point inputs.