An apparatus for generating a digital value based on a semiconductor process variation, the apparatus comprising: a generating unit configured to generate a plurality of digital values, based on the semiconductor process variation; and a processing unit configured to process (810, 820) the digital values and to provide a first digital value, wherein the generating unit comprises a plurality of physically unclonable functions "PUFs", each PUF comprising a via formed between conductive layers in a semiconductor of the apparatus and configured to generate a respective digital value of the digital values based on whether the conductive layers are shorted by the via, wherein the vias of the PUFs have different sizes, at least a portion of the PUFs manufactured by differently applying at least one parameter causing the semiconductor process variation, the size of each of the vias selected from a range between a minimum value and a maximum value of a size of a via corresponding to whether the via is able to cause a short between the conductive layers determined in a test process performed prior to a process of manufacturing the apparatus, wherein the processing unit is configured to: select, as the first digital value, a value meeting a predesignated condition from among the digital values, the predesignated condition configured to be generated by a PUF comprising a via having a size of the minimum value, each of the PUFs configured to provide a digital value corresponding to a bit sequence including both "0" and "1", perform a logical operation on the digital values for each bit sequence, and calculate the first digital value. a generating unit configured to generate a plurality of digital values, based on the semiconductor process variation; and a processing unit configured to process (810, 820) the digital values and to provide a first digital value, wherein the generating unit comprises a plurality of physically unclonable functions "PUFs", each PUF comprising a via formed between conductive layers in a semiconductor of the apparatus and configured to generate a respective digital value of the digital values based on whether the conductive layers are shorted by the via, wherein the vias of the PUFs have different sizes, at least a portion of the PUFs manufactured by differently applying at least one parameter causing the semiconductor process variation, the size of each of the vias selected from a range between a minimum value and a maximum value of a size of a via corresponding to whether the via is able to cause a short between the conductive layers determined in a test process performed prior to a process of manufacturing the apparatus, wherein the processing unit is configured to: select, as the first digital value, a value meeting a predesignated condition from among the digital values, the predesignated condition configured to be generated by a PUF comprising a via having a size of the minimum value, each of the PUFs configured to provide a digital value corresponding to a bit sequence including both "0" and "1", perform a logical operation on the digital values for each bit sequence, and calculate the first digital value. select, as the first digital value, a value meeting a predesignated condition from among the digital values, the predesignated condition configured to be generated by a PUF comprising a via having a size of the minimum value, each of the PUFs configured to provide a digital value corresponding to a bit sequence including both "0" and "1", perform a logical operation on the digital values for each bit sequence, and calculate the first digital value.