An apparatus comprising: a multi-thread processor adapted to execute at least two threads (T 1 -T n) of program code, the multi-thread processor including: an execution pipeline comprising: an instruction fetch unit; a decoder responsive to the instruction fetch unit; an issue unit responsive to the decoder; and an execution unit responsive to the issue unit; a thread control unit including a plurality of thread allocation counters adapted to control the execution pipeline to execute program code of a first thread and a second thread by storing processor time allocations that have been defined for each of the first and second threads and automatically performing a context switch by determining from which of the first and second threads a next instruction will be fetched by the instruction fetch unit, wherein the thread allocation counters determine a weighting corresponding to processor time allocated to each thread; and a register file adapted to store data associated with each of the first and second threads in separate first and second banks associated with the first and second thread, respectively, wherein the execution pipeline is adapted to contain instructions associated with both the first and second threads while the data associated with each of the first and second threads are maintained separately through the first and second banks, respectively. a multi-thread processor adapted to execute at least two threads (T 1 -T n) of program code, the multi-thread processor including: an execution pipeline comprising: an instruction fetch unit; a decoder responsive to the instruction fetch unit; an issue unit responsive to the decoder; and an execution unit responsive to the issue unit; a thread control unit including a plurality of thread allocation counters adapted to control the execution pipeline to execute program code of a first thread and a second thread by storing processor time allocations that have been defined for each of the first and second threads and automatically performing a context switch by determining from which of the first and second threads a next instruction will be fetched by the instruction fetch unit, wherein the thread allocation counters determine a weighting corresponding to processor time allocated to each thread; and a register file adapted to store data associated with each of the first and second threads in separate first and second banks associated with the first and second thread, respectively, wherein the execution pipeline is adapted to contain instructions associated with both the first and second threads while the data associated with each of the first and second threads are maintained separately through the first and second banks, respectively. an execution pipeline comprising: an instruction fetch unit; a decoder responsive to the instruction fetch unit; an issue unit responsive to the decoder; and an execution unit responsive to the issue unit; an instruction fetch unit; a decoder responsive to the instruction fetch unit; an issue unit responsive to the decoder; and an execution unit responsive to the issue unit; a thread control unit including a plurality of thread allocation counters adapted to control the execution pipeline to execute program code of a first thread and a second thread by storing processor time allocations that have been defined for each of the first and second threads and automatically performing a context switch by determining from which of the first and second threads a next instruction will be fetched by the instruction fetch unit, wherein the thread allocation counters determine a weighting corresponding to processor time allocated to each thread; and a register file adapted to store data associated with each of the first and second threads in separate first and second banks associated with the first and second thread, respectively, wherein the execution pipeline is adapted to contain instructions associated with both the first and second threads while the data associated with each of the first and second threads are maintained separately through the first and second banks, respectively.