A communication device (101; 301) comprising: a control module (103; 303) in the communication device (101; 301) and a line card (105; 305) in the communication device (101; 301) for connection to a communication network, the control module (103; 303) having a processor (109; 309), a control interface (107; 307) in the communication device (101; 301) for transmitting control data from said control module (103; 303) to said line card (105; 305) to control operation thereof, said control interface (107; 307) comprises a bi-directional data bus for transmitting said control data from said control module (103; 305) to said line card (105; 305), said line card (105; 305) comprising: a status detector (129; 329) for detecting an error respectively associated with said control data received from said control module (103; 303), and reporting means (131-139; 329) for generating a message for transmission to said control module (103; 303), said message comprising an indication of said error associated with said received control data and detected by the status detector (129; 329), wherein said control module is configured to determine a value of a parity bit based on bits contained in said control data and to transmit the parity bit with said control data via the control interface, wherein said status detector comprises a parity check module, an address verifier, a control module status detector and a clock signal detector, wherein said parity check module is configured to determine a parity bit from bit values contained in said control data and to compare this with said parity bit transmitted with said control data, wherein said address verifier is configured to, if said control data contains a memory address, check whether the address is valid, wherein said control module status detector is configured to detect a status of the control module, and wherein said clock signal detector is configured to detect a clock signal from said control module transmitted over a clock line. a control module (103; 303) in the communication device (101; 301) and a line card (105; 305) in the communication device (101; 301) for connection to a communication network, the control module (103; 303) having a processor (109; 309), a control interface (107; 307) in the communication device (101; 301) for transmitting control data from said control module (103; 303) to said line card (105; 305) to control operation thereof, said control interface (107; 307) comprises a bi-directional data bus for transmitting said control data from said control module (103; 305) to said line card (105; 305), said line card (105; 305) comprising: a status detector (129; 329) for detecting an error respectively associated with said control data received from said control module (103; 303), and reporting means (131-139; 329) for generating a message for transmission to said control module (103; 303), said message comprising an indication of said error associated with said received control data and detected by the status detector (129; 329), wherein said control module is configured to determine a value of a parity bit based on bits contained in said control data and to transmit the parity bit with said control data via the control interface, wherein said status detector comprises a parity check module, an address verifier, a control module status detector and a clock signal detector, wherein said parity check module is configured to determine a parity bit from bit values contained in said control data and to compare this with said parity bit transmitted with said control data, wherein said address verifier is configured to, if said control data contains a memory address, check whether the address is valid, wherein said control module status detector is configured to detect a status of the control module, and wherein said clock signal detector is configured to detect a clock signal from said control module transmitted over a clock line. a status detector (129; 329) for detecting an error respectively associated with said control data received from said control module (103; 303), and reporting means (131-139; 329) for generating a message for transmission to said control module (103; 303), said message comprising an indication of said error associated with said received control data and detected by the status detector (129; 329), wherein said control module is configured to determine a value of a parity bit based on bits contained in said control data and to transmit the parity bit with said control data via the control interface, wherein said status detector comprises a parity check module, an address verifier, a control module status detector and a clock signal detector, wherein said parity check module is configured to determine a parity bit from bit values contained in said control data and to compare this with said parity bit transmitted with said control data, wherein said address verifier is configured to, if said control data contains a memory address, check whether the address is valid, wherein said control module status detector is configured to detect a status of the control module, and wherein said clock signal detector is configured to detect a clock signal from said control module transmitted over a clock line.