A method of manufacturing a semiconductor device comprising a junction field effect transistor, the junction field effect transistor including: a semiconductor substrate of a first conductivity type; an epitaxial layer of the first conductivity type formed on the semiconductor substrate; a source region of the first conductivity type formed on a surface of the epitaxial layer; a channel region of the first conductivity type formed in a lower layer of the source region; a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween; a pair of gate regions of a second conductivity type opposite to the first conductivity type, formed below a bottom of the pair of trenches, each of the pair of gate regions including: a low concentration gate region; and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, the high concentration gate region being included in the low concentration gate region, the method comprising the steps of: (a) preparing the semiconductor substrate where the epitaxial layer is formed on a main surface; (b) forming the source region on a surface of the epitaxial layer; (c) forming the pair of trenches which penetrate through the source region; and (d) forming the pair of gate regions below a bottom of the pair of trenches, and the step of (d) including the steps of: forming the low concentration gate region below each bottom of the pair of trenches; and forming the high concentration gate region in a region which is below each bottom of the pair of trenches and which is narrower than a formation region of the low concentration gate region, wherein, in the step of, after the step of, a side wall spacer is formed on each side surface of the pair of trenches, and then, the high concentration gate region is formed below each bottom of the pair of trenches. a semiconductor substrate of a first conductivity type; an epitaxial layer of the first conductivity type formed on the semiconductor substrate; a source region of the first conductivity type formed on a surface of the epitaxial layer; a channel region of the first conductivity type formed in a lower layer of the source region; a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween; a pair of gate regions of a second conductivity type opposite to the first conductivity type, formed below a bottom of the pair of trenches, each of the pair of gate regions including: a low concentration gate region; and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, the high concentration gate region being included in the low concentration gate region, the method comprising the steps of: (a) preparing the semiconductor substrate where the epitaxial layer is formed on a main surface; (b) forming the source region on a surface of the epitaxial layer; (c) forming the pair of trenches which penetrate through the source region; and (d) forming the pair of gate regions below a bottom of the pair of trenches, and the step of (d) including the steps of: forming the low concentration gate region below each bottom of the pair of trenches; and forming the high concentration gate region in a region which is below each bottom of the pair of trenches and which is narrower than a formation region of the low concentration gate region, wherein, in the step of, after the step of, a side wall spacer is formed on each side surface of the pair of trenches, and then, the high concentration gate region is formed below each bottom of the pair of trenches. a low concentration gate region; and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, the high concentration gate region being included in the low concentration gate region, the method comprising the steps of: (a) preparing the semiconductor substrate where the epitaxial layer is formed on a main surface; (b) forming the source region on a surface of the epitaxial layer; (c) forming the pair of trenches which penetrate through the source region; and (d) forming the pair of gate regions below a bottom of the pair of trenches, and (a) preparing the semiconductor substrate where the epitaxial layer is formed on a main surface; (b) forming the source region on a surface of the epitaxial layer; (c) forming the pair of trenches which penetrate through the source region; and (d) forming the pair of gate regions below a bottom of the pair of trenches, and the step of (d) including the steps of: forming the low concentration gate region below each bottom of the pair of trenches; and forming the high concentration gate region in a region which is below each bottom of the pair of trenches and which is narrower than a formation region of the low concentration gate region, wherein, in the step of, after the step of, a side wall spacer is formed on each side surface of the pair of trenches, and then, the high concentration gate region is formed below each bottom of the pair of trenches. forming the low concentration gate region below each bottom of the pair of trenches; and forming the high concentration gate region in a region which is below each bottom of the pair of trenches and which is narrower than a formation region of the low concentration gate region, wherein, in the step of, after the step of, a side wall spacer is formed on each side surface of the pair of trenches, and then, the high concentration gate region is formed below each bottom of the pair of trenches.