A Doherty amplifier, comprising: a device package (108, 302) including an output lead (110, 324), a first input lead configured to receive a carrier signal and a second input lead configured to receive a peaking signal, the device package encasing: a carrier transistor formed on a carrier transistor die and having a carrier transistor input connected to the first input lead and a carrier transistor output; a peaking transistor formed on a peaking transistor die and having a peaking transistor input connected to the second input lead and a peaking transistor output; a transmission line (208, 322, 408) having a length, the transmission line formed on a substrate distinct from the carrier transistor die and the peaking transistor die; a first set of bond wires connecting the carrier transistor output to a first end of the transmission line; a second set of bond wires connecting the peaking transistor output to a second end of the transmission line; wherein a length of the transmission line between the first and second ends is configured, in combination with a parasitic capacitance of the carrier transistor, a parasitic capacitance of the peaking transistor, the first set of bond wires and the second set of bond wires, to provide an impedance inverter between the carrier transistor output and the peaking transistor output; characterized by a third set of bond wires connecting the peaking transistor output to the output lead. a device package (108, 302) including an output lead (110, 324), a first input lead configured to receive a carrier signal and a second input lead configured to receive a peaking signal, the device package encasing: a carrier transistor formed on a carrier transistor die and having a carrier transistor input connected to the first input lead and a carrier transistor output; a peaking transistor formed on a peaking transistor die and having a peaking transistor input connected to the second input lead and a peaking transistor output; a transmission line (208, 322, 408) having a length, the transmission line formed on a substrate distinct from the carrier transistor die and the peaking transistor die; a first set of bond wires connecting the carrier transistor output to a first end of the transmission line; a second set of bond wires connecting the peaking transistor output to a second end of the transmission line; wherein a length of the transmission line between the first and second ends is configured, in combination with a parasitic capacitance of the carrier transistor, a parasitic capacitance of the peaking transistor, the first set of bond wires and the second set of bond wires, to provide an impedance inverter between the carrier transistor output and the peaking transistor output; a carrier transistor formed on a carrier transistor die and having a carrier transistor input connected to the first input lead and a carrier transistor output; a peaking transistor formed on a peaking transistor die and having a peaking transistor input connected to the second input lead and a peaking transistor output; a transmission line (208, 322, 408) having a length, the transmission line formed on a substrate distinct from the carrier transistor die and the peaking transistor die; a first set of bond wires connecting the carrier transistor output to a first end of the transmission line; a second set of bond wires connecting the peaking transistor output to a second end of the transmission line; wherein a length of the transmission line between the first and second ends is configured, in combination with a parasitic capacitance of the carrier transistor, a parasitic capacitance of the peaking transistor, the first set of bond wires and the second set of bond wires, to provide an impedance inverter between the carrier transistor output and the peaking transistor output; characterized by a third set of bond wires connecting the peaking transistor output to the output lead.