A barrier synchronization method performed by a barrier synchronization device in a multi-core processor that includes the barrier synchronization device and M processor cores that each form X logic processors to perform parallel processing, the barrier synchronization method comprising: when one logic processor of the X logic processors starts a process to be executed in parallel processing, writing a value, indicating that a process is being performed, to a barrier status register that is provided at the barrier synchronization device and that corresponds to the one logic processor, and when the one logic processor completes the process to be executed in parallel processing, writing a value, indicating that a process is not being performed, to the barrier status register that corresponds to the one logic processor, wherein each of the M logic processors corresponds to one of a plurality of barrier status registers storing one-bit data indicating an execution status of a process executed by a corresponding logic processor; and executing barrier synchronization of the M logic processors by using a plurality of barrier blades, wherein each one of the plurality of barrier blades includes a barrier mask register having X bits, each bit corresponding to one of the X logic processors and indicating whether or not a corresponding logic processor belongs to a synchronization group in which a set of logic processors execute the parallel processing together, and a Last Barrier Synchronization register, whose Last Barrier Synchronization value is inverted when the values of all the barrier status registers in a same synchronization group indicated by the barrier mask register become identical; and copying the Last Barrier Synchronization value stored in the Last Barrier Synchronization register and related to the same synchronization group to a register provided at a processor core that forms logic processors belonging to the same synchronization group, wherein each logic processor which belongs to the same synchronization group indicated by the barrier mask register is prohibited from executing a process assigned to the logic processor for the parallel processing, until the Last Barrier Synchronization value related to the same synchronization group that has been copied to the register provided at a processor core that forms the logic processor is inverted, and N≥2M · X is satisfied, where N indicates a number of the plurality of barrier blades. when one logic processor of the X logic processors starts a process to be executed in parallel processing, writing a value, indicating that a process is being performed, to a barrier status register that is provided at the barrier synchronization device and that corresponds to the one logic processor, and when the one logic processor completes the process to be executed in parallel processing, writing a value, indicating that a process is not being performed, to the barrier status register that corresponds to the one logic processor, wherein each of the M logic processors corresponds to one of a plurality of barrier status registers storing one-bit data indicating an execution status of a process executed by a corresponding logic processor; and executing barrier synchronization of the M logic processors by using a plurality of barrier blades, wherein each one of the plurality of barrier blades includes a barrier mask register having X bits, each bit corresponding to one of the X logic processors and indicating whether or not a corresponding logic processor belongs to a synchronization group in which a set of logic processors execute the parallel processing together, and a Last Barrier Synchronization register, whose Last Barrier Synchronization value is inverted when the values of all the barrier status registers in a same synchronization group indicated by the barrier mask register become identical; and copying the Last Barrier Synchronization value stored in the Last Barrier Synchronization register and related to the same synchronization group to a register provided at a processor core that forms logic processors belonging to the same synchronization group, wherein each logic processor which belongs to the same synchronization group indicated by the barrier mask register is prohibited from executing a process assigned to the logic processor for the parallel processing, until the Last Barrier Synchronization value related to the same synchronization group that has been copied to the register provided at a processor core that forms the logic processor is inverted, and N≥2M · X is satisfied, where N indicates a number of the plurality of barrier blades.