A memory device comprising: at least a first memory cell (102, 302, 502) and a second memory cell (104, 304, 504) on a substrate, each memory cell comprising: a first electrode (106, 306, 506); a second electrode (108, 308, 508); and a volume of variable resistance material (110, 310, 510) between the first electrode (106, 306, 506) and the second electrode (108, 308, 508); and a cavity (122, 222, 322, 422, 522) extending between the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504); a dielectric material (128, 514) extending over and between the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504) on a side thereof opposite the substrate, the dielectric material (128, 514) partially defining a boundary of the cavity (122, 222, 322, 422, 522); and a passivation material (114, 116, 216, 516) on at least a portion of the volume of variable resistance material (110, 310, 510) of each of the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504), characterized by the passivation material (114, 116, 216, 516) partially bounding the cavity (122, 222, 322, 422, 522). at least a first memory cell (102, 302, 502) and a second memory cell (104, 304, 504) on a substrate, each memory cell comprising: a first electrode (106, 306, 506); a second electrode (108, 308, 508); and a volume of variable resistance material (110, 310, 510) between the first electrode (106, 306, 506) and the second electrode (108, 308, 508); and a cavity (122, 222, 322, 422, 522) extending between the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504); a dielectric material (128, 514) extending over and between the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504) on a side thereof opposite the substrate, the dielectric material (128, 514) partially defining a boundary of the cavity (122, 222, 322, 422, 522); and a passivation material (114, 116, 216, 516) on at least a portion of the volume of variable resistance material (110, 310, 510) of each of the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504), characterized by the passivation material (114, 116, 216, 516) partially bounding the cavity (122, 222, 322, 422, 522). a first electrode (106, 306, 506); a second electrode (108, 308, 508); and a volume of variable resistance material (110, 310, 510) between the first electrode (106, 306, 506) and the second electrode (108, 308, 508); and a cavity (122, 222, 322, 422, 522) extending between the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504); a dielectric material (128, 514) extending over and between the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504) on a side thereof opposite the substrate, the dielectric material (128, 514) partially defining a boundary of the cavity (122, 222, 322, 422, 522); and a passivation material (114, 116, 216, 516) on at least a portion of the volume of variable resistance material (110, 310, 510) of each of the at least a first memory cell (102, 302, 502) and the second memory cell (104, 304, 504), characterized by the passivation material (114, 116, 216, 516) partially bounding the cavity (122, 222, 322, 422, 522).