An electronic circuit, characterized by comprising: an IC chip comprising a noise eliminating circuit, a digital circuit, an early-initialization circuit and further comprising an input terminal of a power-on reset signal, an output terminal and an output buffer connected to the output terminal; wherein the noise eliminating circuit is configured to eliminate noise in a power-on reset signal and output a signal obtained by eliminating the noise in the power-on reset signal; wherein the digital circuit is configured to be reset by the signal outputted from the noise eliminating circuit; wherein the early-initialization circuit is connected to the output buffer; wherein the early-initialization circuit is arranged between the digital circuit and the output buffer connected to the output terminal; wherein the early-initialization circuit is configured to produce a fixed value as an output signal until a reset status set by the power-on reset signal is released and directly supplies the output signal of the digital circuit upon the power-on reset status is released; wherein the early-initialization circuit is configured to supply the fixed value to the output buffer from a point of time at power-on to a point of time when the reset status set by the power-on reset signal is released and wherein the early-initialization circuit is further configured to perform a logical operation between the output signal of the digital circuit and the power-on reset signal, and output a result of the logical operation. an IC chip comprising a noise eliminating circuit, a digital circuit, an early-initialization circuit and further comprising an input terminal of a power-on reset signal, an output terminal and an output buffer connected to the output terminal; wherein the noise eliminating circuit is configured to eliminate noise in a power-on reset signal and output a signal obtained by eliminating the noise in the power-on reset signal; wherein the digital circuit is configured to be reset by the signal outputted from the noise eliminating circuit; wherein the early-initialization circuit is connected to the output buffer; wherein the early-initialization circuit is arranged between the digital circuit and the output buffer connected to the output terminal; wherein the early-initialization circuit is configured to produce a fixed value as an output signal until a reset status set by the power-on reset signal is released and directly supplies the output signal of the digital circuit upon the power-on reset status is released; wherein the early-initialization circuit is configured to supply the fixed value to the output buffer from a point of time at power-on to a point of time when the reset status set by the power-on reset signal is released and wherein the early-initialization circuit is further configured to perform a logical operation between the output signal of the digital circuit and the power-on reset signal, and output a result of the logical operation. a noise eliminating circuit, a digital circuit, an early-initialization circuit and further comprising an input terminal of a power-on reset signal, an output terminal and an output buffer connected to the output terminal; wherein the noise eliminating circuit is configured to eliminate noise in a power-on reset signal and output a signal obtained by eliminating the noise in the power-on reset signal; wherein the digital circuit is configured to be reset by the signal outputted from the noise eliminating circuit; wherein the early-initialization circuit is connected to the output buffer; wherein the early-initialization circuit is arranged between the digital circuit and the output buffer connected to the output terminal; wherein the early-initialization circuit is configured to produce a fixed value as an output signal until a reset status set by the power-on reset signal is released and directly supplies the output signal of the digital circuit upon the power-on reset status is released; wherein the early-initialization circuit is configured to supply the fixed value to the output buffer from a point of time at power-on to a point of time when the reset status set by the power-on reset signal is released and wherein the early-initialization circuit is further configured to perform a logical operation between the output signal of the digital circuit and the power-on reset signal, and output a result of the logical operation.