An organic light emitting display device comprising: a first substrate comprising a top surface; a second substrate; an array of organic light emitting pixels interposed between the first substrate and the second substrate; a thin film transistor interposed between the first substrate and the array of organic light emitting pixels, the thin film transistor comprising a semiconductor layer, a gate electrode, a source electrode and a drain electrode, a gate insulation layer arranged between the semi-conductor layer and the gate electrode, and an interlayer insulation layer arranged between the gate electrode and the source and drain electrodes; a plurality of conductive lines (32 and 34) comprising first conductive lines and second conductive lines, wherein the first conductive lines are formed directly on the gate insulation layer and the second conductive lines are formed on the interlayer insulation layer; and a chip on glass region which does not overlap the array of organic light emitting pixels, wherein the first and second conductive lines are disposed in the COG region, characterized in that the gate insulation layer comprises a first extension, and wherein the first conductive lines are interposed between the first extension of the gate insulation layer and the interlayer insulation layer, wherein the interlayer insulation layer comprises a second extension, and wherein the second conductive lines are interposed between the second extension of the interlayer insulation layer and the array of organic light emitting pixels and the first and second conductive lines are substantially parallel to one another and not overlapping when viewed in a direction substantially perpendicular to the top surface. a first substrate comprising a top surface; a second substrate; an array of organic light emitting pixels interposed between the first substrate and the second substrate; a thin film transistor interposed between the first substrate and the array of organic light emitting pixels, the thin film transistor comprising a semiconductor layer, a gate electrode, a source electrode and a drain electrode, a gate insulation layer arranged between the semi-conductor layer and the gate electrode, and an interlayer insulation layer arranged between the gate electrode and the source and drain electrodes; a plurality of conductive lines (32 and 34) comprising first conductive lines and second conductive lines, wherein the first conductive lines are formed directly on the gate insulation layer and the second conductive lines are formed on the interlayer insulation layer; and a chip on glass region which does not overlap the array of organic light emitting pixels, wherein the first and second conductive lines are disposed in the COG region, characterized in that the gate insulation layer comprises a first extension, and wherein the first conductive lines are interposed between the first extension of the gate insulation layer and the interlayer insulation layer, wherein the interlayer insulation layer comprises a second extension, and wherein the second conductive lines are interposed between the second extension of the interlayer insulation layer and the array of organic light emitting pixels and the first and second conductive lines are substantially parallel to one another and not overlapping when viewed in a direction substantially perpendicular to the top surface.