A method comprising: forming a first substrate (no) comprising a first device layer comprising first devices (120A-C) disposed thereon; forming a plurality of first interconnects on the first device layer, the plurality of first interconnects comprising second interconnects and third interconnects which have dimensions compatible with the first devices (120A-C) and a plurality of high speed devices, respectively; defining device layer contacts (125A-C) between the first devices (120A-C) and the second interconnects; forming a second device layer comprising the plurality of high speed devices; defining contacts between the third interconnects and the high speed devices of the second device layer; forming a plurality of fourth interconnects on the second device layer; define contacts between the high speed devices of the second device layer and the fourth interconnects, wherein forming a second device layer comprises coupling one of the second device layer devoid of the plurality of high speed devices and the second device layer comprising the plurality of high speed devices to ones of the plurality of third interconnects, with the proviso that where the second device layer devoid of the plurality of high speed devices is coupled, the method comprises forming the plurality of high speed devices, wherein the first devices (120A-C) comprise devices having a higher voltage range than the plurality of high speed devices of the second device layer; defining memory elements embedded in the fourth interconnects; defining that the high-speed devices of the second device layer are operably connected to said memory elements; defining a metallization layer as contact points on the fourth interconnects, the metallization layer being exposed for metal-to-metal bonding connections; bonding a memory device layer comprising memory elements and circuitry on a carrier wafer to the metallization layer so that the memory device layer is juxtaposed to the plurality of fourth interconnects; removing a portion of the first substrate; performing passivation of the first device layer including the first devices (120A-C); and forming contacts points to the second interconnects, the contact points operable for connection to an external source. forming a first substrate (no) comprising a first device layer comprising first devices (120A-C) disposed thereon; forming a plurality of first interconnects on the first device layer, the plurality of first interconnects comprising second interconnects and third interconnects which have dimensions compatible with the first devices (120A-C) and a plurality of high speed devices, respectively; defining device layer contacts (125A-C) between the first devices (120A-C) and the second interconnects; forming a second device layer comprising the plurality of high speed devices; defining contacts between the third interconnects and the high speed devices of the second device layer; forming a plurality of fourth interconnects on the second device layer; define contacts between the high speed devices of the second device layer and the fourth interconnects, wherein forming a second device layer comprises coupling one of the second device layer devoid of the plurality of high speed devices and the second device layer comprising the plurality of high speed devices to ones of the plurality of third interconnects, with the proviso that where the second device layer devoid of the plurality of high speed devices is coupled, the method comprises forming the plurality of high speed devices, wherein the first devices (120A-C) comprise devices having a higher voltage range than the plurality of high speed devices of the second device layer; defining memory elements embedded in the fourth interconnects; defining that the high-speed devices of the second device layer are operably connected to said memory elements; defining a metallization layer as contact points on the fourth interconnects, the metallization layer being exposed for metal-to-metal bonding connections; bonding a memory device layer comprising memory elements and circuitry on a carrier wafer to the metallization layer so that the memory device layer is juxtaposed to the plurality of fourth interconnects; removing a portion of the first substrate; performing passivation of the first device layer including the first devices (120A-C); and forming contacts points to the second interconnects, the contact points operable for connection to an external source.