A memory module (402, 402') operable in a computer system with a memory controller, the computer system including a set of control signal lines (440, 440') and first number of data signal lines (450, 450') between the memory module (402, 402') and the memory controller, the first number of data signal lines (450, 450') including a second number of sets of data signal lines (450, 450'), each set of data signal lines (450, 450') for conducting an 8-bit section of each data signal between the memory module (402, 402') and the memory controller, the memory module (402, 402') comprising: a module board (410, 410') configured to be coupled to the memory controller via the set of control signal lines (440, 440') and the first number of data signal lines (450, 450'), the module board (410, 410') being mountable in a module slot of the computer system and having an edge connector comprising a plurality of electrical contacts which are positioned on an edge of the module board (410, 410') and are positioned to be releasably coupled to corresponding contacts of a computer system socket; a plurality of memory devices (412, 412') coupled to the module board (410, 410') and arranged in multiple ranks, each rank of the multiple ranks having a bit width equal to a bit width of the memory module (402, 402'); a module controller (430, 430') coupled to the module board (410, 410') and configured to receive input control signals for a read or write operation from the memory controller via the set of control signal lines (440, 440') and to output first module control signals based on the input control signals, the read or write operation being targeted at a specific one of the multiple ranks; and second number of load-reducing circuits (416, 416') coupled to the module board (410, 410') and configured to receive the first module control signals, each respective one of the second number of load-reducing circuits (416, 416') being coupled to a respective set of the second number of sets of data signal lines (450, 450') and to at least one respective memory device (412, 412') in each of the multiple ranks, the second number of load-reducing circuits (416, 416') being disposed on the module board (410, 410') at respective positions corresponding to respective sets of the second number of sets of data signal lines (450, 450'); and wherein the each respective one of the load-reducing circuits (416, 416') includes data paths and logic controlling the data paths in response to the first module control signals so that the second number of load-reducing circuits (416, 416') actively drive a data signal corresponding to the read or write operation between the specific one of the multiple ranks on the memory module (402, 402') and the memory controller, and wherein the first module control signals indicate a direction of data flow. a module board (410, 410') configured to be coupled to the memory controller via the set of control signal lines (440, 440') and the first number of data signal lines (450, 450'), the module board (410, 410') being mountable in a module slot of the computer system and having an edge connector comprising a plurality of electrical contacts which are positioned on an edge of the module board (410, 410') and are positioned to be releasably coupled to corresponding contacts of a computer system socket; a plurality of memory devices (412, 412') coupled to the module board (410, 410') and arranged in multiple ranks, each rank of the multiple ranks having a bit width equal to a bit width of the memory module (402, 402'); a module controller (430, 430') coupled to the module board (410, 410') and configured to receive input control signals for a read or write operation from the memory controller via the set of control signal lines (440, 440') and to output first module control signals based on the input control signals, the read or write operation being targeted at a specific one of the multiple ranks; and second number of load-reducing circuits (416, 416') coupled to the module board (410, 410') and configured to receive the first module control signals, each respective one of the second number of load-reducing circuits (416, 416') being coupled to a respective set of the second number of sets of data signal lines (450, 450') and to at least one respective memory device (412, 412') in each of the multiple ranks, the second number of load-reducing circuits (416, 416') being disposed on the module board (410, 410') at respective positions corresponding to respective sets of the second number of sets of data signal lines (450, 450'); and wherein the each respective one of the load-reducing circuits (416, 416') includes data paths and logic controlling the data paths in response to the first module control signals so that the second number of load-reducing circuits (416, 416') actively drive a data signal corresponding to the read or write operation between the specific one of the multiple ranks on the memory module (402, 402') and the memory controller, and wherein the first module control signals indicate a direction of data flow.