A memory device, comprising: a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the memory cells are arranged in pairs of the memory cells; and each of the pairs of memory cells shares one of the source regions and one of the source lines; each of the memory cells includes: spaced apart source and drain regions (14, 16) in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells; and each of the rows of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the row of memory cells, the memory device characterised in that: each of the columns of the memory cells includes a source line that electrically connects all the source regions for the column of the memory cells. a substrate of semiconductor material; a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the memory cells are arranged in pairs of the memory cells; and each of the pairs of memory cells shares one of the source regions and one of the source lines; each of the memory cells includes: spaced apart source and drain regions (14, 16) in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells; and each of the rows of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the row of memory cells, the memory device characterised in that: spaced apart source and drain regions (14, 16) in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region; each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells; each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells; and each of the rows of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the row of memory cells,