A NAND flash storage device comprising: a plurality of NAND flash chips (170a, 170b) comprising a first NAND flash chip, a second NAND flash chip, a third NAND flash chip and a fourth NAND flash chip; and a controller configured to: designate the first NAND flash chip as a secondary write chip, the second NAND flash chip as a future secondary write chip, the third NAND flash chip as a primary write chip, the fourth NAND flash chip as a future primary write chip, and any remaining NAND flash chips as read-only; receive data over an input/output (I/O) bus; write the received data to the primary write chip and the secondary write chip successively such that write operations to each NAND flash chip (170a, 170b) do not overlap in time; receive a read command over the I/O bus; and responsive to receiving the read command, read data from whichever of the primary write chip or the secondary write chip is not currently executing a write operation such that read operations are not queued behind write operations; copy only valid data from the future primary write chip to the future secondary write chip; and following the writing of the received data and the copying of the valid data, designate the first NAND flash chip as read-only, the second NAND flash chip as the secondary write chip, the third NAND flash chip as the future secondary write chip, and the fourth NAND flash chip as the primary write chip. a plurality of NAND flash chips (170a, 170b) comprising a first NAND flash chip, a second NAND flash chip, a third NAND flash chip and a fourth NAND flash chip; and a controller configured to: designate the first NAND flash chip as a secondary write chip, the second NAND flash chip as a future secondary write chip, the third NAND flash chip as a primary write chip, the fourth NAND flash chip as a future primary write chip, and any remaining NAND flash chips as read-only; receive data over an input/output (I/O) bus; write the received data to the primary write chip and the secondary write chip successively such that write operations to each NAND flash chip (170a, 170b) do not overlap in time; receive a read command over the I/O bus; and responsive to receiving the read command, read data from whichever of the primary write chip or the secondary write chip is not currently executing a write operation such that read operations are not queued behind write operations; copy only valid data from the future primary write chip to the future secondary write chip; and following the writing of the received data and the copying of the valid data, designate the first NAND flash chip as read-only, the second NAND flash chip as the secondary write chip, the third NAND flash chip as the future secondary write chip, and the fourth NAND flash chip as the primary write chip. designate the first NAND flash chip as a secondary write chip, the second NAND flash chip as a future secondary write chip, the third NAND flash chip as a primary write chip, the fourth NAND flash chip as a future primary write chip, and any remaining NAND flash chips as read-only; receive data over an input/output (I/O) bus; write the received data to the primary write chip and the secondary write chip successively such that write operations to each NAND flash chip (170a, 170b) do not overlap in time; receive a read command over the I/O bus; and responsive to receiving the read command, read data from whichever of the primary write chip or the secondary write chip is not currently executing a write operation such that read operations are not queued behind write operations; copy only valid data from the future primary write chip to the future secondary write chip; and following the writing of the received data and the copying of the valid data, designate the first NAND flash chip as read-only, the second NAND flash chip as the secondary write chip, the third NAND flash chip as the future secondary write chip, and the fourth NAND flash chip as the primary write chip.