A switch comprising: an even number of transistors arranged in series, each transistor of the number of transistors having a source, a drain, and a gate, every two successive transistors defining a pair of transistors, the number of transistors being at least six; and a bias network including a control line, for each pair of transistors, a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, between the gates of the pair of transistors and the first node, wherein respectively a first-level resistor is connected between the gate of one of the pair of transistors and the first node, and for two pairs of transistors a second connection including a second node (465, 630) connecting the first nodes, the second node being coupled to the control line, wherein each second connection between the second node and each first node comprises a second-level resistor of a same resistance, characterized in that the switch includes an odd number of pairs, wherein, for a central pair of transistors, the first node is connected by a capacitor to a common node formed by a drain of one transistor of the pair and a source of the other transistor of the pair. an even number of transistors arranged in series, each transistor of the number of transistors having a source, a drain, and a gate, every two successive transistors defining a pair of transistors, the number of transistors being at least six; and a bias network including a control line, for each pair of transistors, a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, between the gates of the pair of transistors and the first node, wherein respectively a first-level resistor is connected between the gate of one of the pair of transistors and the first node, and for two pairs of transistors a second connection including a second node (465, 630) connecting the first nodes, the second node being coupled to the control line, wherein each second connection between the second node and each first node comprises a second-level resistor of a same resistance, characterized in that the switch includes an odd number of pairs, wherein, for a central pair of transistors, the first node is connected by a capacitor to a common node formed by a drain of one transistor of the pair and a source of the other transistor of the pair. a control line, for each pair of transistors, a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, between the gates of the pair of transistors and the first node, wherein respectively a first-level resistor is connected between the gate of one of the pair of transistors and the first node, and for two pairs of transistors a second connection including a second node (465, 630) connecting the first nodes, the second node being coupled to the control line, wherein each second connection between the second node and each first node comprises a second-level resistor of a same resistance, characterized in that the switch includes an odd number of pairs, wherein, for a central pair of transistors, the first node is connected by a capacitor to a common node formed by a drain of one transistor of the pair and a source of the other transistor of the pair.