A memory circuit (10, 50) comprising: a memory array (12, 52) comprising an array portion (14, 54) and an analog bypass portion (16, 56), the array portion (14, 54) comprising rows and columns of memory cells, the array portion (14, 54) stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and to read a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns, wherein each of the memory cells includes a superconducting hysteretic memory element, wherein the analog bypass portion (16, 56) comprises a row of cells coupled to the memory array (12, 52), wherein each of the cells of the analog bypass portion (16, 56) comprises a superconducting read element; a read address decoder (26, 60) that generates the word-read signal to select the given one of the rows to read the memory word from the given one of the rows; and a write-through detection system (28, 58) that receives a read-enable signal (R-EN) during a read operation and activates the analog bypass portion (16, 56) to read the memory word from the analog bypass portion (16, 56) in response to the read address being equal to the write address and in response to the word-read signal being provided approximately concurrently with the word-write signal, the write-through detection system (28, 58) comprising: a comparator that compares the write address and the read address and to generate a control signal (CTRL) in response to the write address being equal to the read address and in response to the word-read signal being provided approximately concurrently with the word-write signal; a first AND-gate that receives the read-enable signal (R-EN) and an inverted state of the control signal (CTRL) and generates an array-enable signal to activate and deactivate the read address decoder (26, 60); and a second AND-gate that receives the read-enable signal (R-EN) and the control signal (CTRL) and generates a write-through signal (W-T) to activate and deactivate the analog bypass portion (16, 56). a memory array (12, 52) comprising an array portion (14, 54) and an analog bypass portion (16, 56), the array portion (14, 54) comprising rows and columns of memory cells, the array portion (14, 54) stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and to read a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns, wherein each of the memory cells includes a superconducting hysteretic memory element, wherein the analog bypass portion (16, 56) comprises a row of cells coupled to the memory array (12, 52), wherein each of the cells of the analog bypass portion (16, 56) comprises a superconducting read element; a read address decoder (26, 60) that generates the word-read signal to select the given one of the rows to read the memory word from the given one of the rows; and a write-through detection system (28, 58) that receives a read-enable signal (R-EN) during a read operation and activates the analog bypass portion (16, 56) to read the memory word from the analog bypass portion (16, 56) in response to the read address being equal to the write address and in response to the word-read signal being provided approximately concurrently with the word-write signal, the write-through detection system (28, 58) comprising: a comparator that compares the write address and the read address and to generate a control signal (CTRL) in response to the write address being equal to the read address and in response to the word-read signal being provided approximately concurrently with the word-write signal; a first AND-gate that receives the read-enable signal (R-EN) and an inverted state of the control signal (CTRL) and generates an array-enable signal to activate and deactivate the read address decoder (26, 60); and a second AND-gate that receives the read-enable signal (R-EN) and the control signal (CTRL) and generates a write-through signal (W-T) to activate and deactivate the analog bypass portion (16, 56). a comparator that compares the write address and the read address and to generate a control signal (CTRL) in response to the write address being equal to the read address and in response to the word-read signal being provided approximately concurrently with the word-write signal; a first AND-gate that receives the read-enable signal (R-EN) and an inverted state of the control signal (CTRL) and generates an array-enable signal to activate and deactivate the read address decoder (26, 60); and a second AND-gate that receives the read-enable signal (R-EN) and the control signal (CTRL) and generates a write-through signal (W-T) to activate and deactivate the analog bypass portion (16, 56).