An interface circuit comprising: a first input terminal (107, 108) operable to receive either one of a single-ended signal (DAT0, DAT1) and a first differential signal (RCLK+, RCLK-) from an external first transmission path; a second input terminal (109, 110) operable to receive a second differential signal (D0+, D0-) from an external second transmission path, the second differential signal (D0+, D0-) being a one-bit serial signal; and a single-ended signal receiver and a differential signal receiver which are connected to the first input terminal (107, 108) by wires, and to which the single-ended signal (DAT0, DAT1) and the first differential signal (RCLK+, RCLK-) input from the first input terminal (107, 108) are supplied in parallel; characterized by a detection circuit that is connected to the second input terminal (109, 110) by wires and is operable to detect an input of the second differential signal (D0+, D0-) thereto from the second input terminal (109, 110), and to output, when the input of the second differential signal (D0+, D0-) is detected, a first enable signal to the differential signal receiver; and a controller operable, when the detection circuit detects the input of the second differential signal (D0+, D0-) thereto from the second input terminal (109, 110), to start constantly outputting a second enable signal to the differential signal receiver, wherein the differential signal receiver is adapted to remain in an active state while at least either one of the first and the second enable signal is being input thereto, and wherein the first differential signal (RCLK+, RCLK-) is a clock signal for the second differential signal (D0+, D0-). a first input terminal (107, 108) operable to receive either one of a single-ended signal (DAT0, DAT1) and a first differential signal (RCLK+, RCLK-) from an external first transmission path; a second input terminal (109, 110) operable to receive a second differential signal (D0+, D0-) from an external second transmission path, the second differential signal (D0+, D0-) being a one-bit serial signal; and a single-ended signal receiver and a differential signal receiver which are connected to the first input terminal (107, 108) by wires, and to which the single-ended signal (DAT0, DAT1) and the first differential signal (RCLK+, RCLK-) input from the first input terminal (107, 108) are supplied in parallel; characterized by a detection circuit that is connected to the second input terminal (109, 110) by wires and is operable to detect an input of the second differential signal (D0+, D0-) thereto from the second input terminal (109, 110), and to output, when the input of the second differential signal (D0+, D0-) is detected, a first enable signal to the differential signal receiver; and a controller operable, when the detection circuit detects the input of the second differential signal (D0+, D0-) thereto from the second input terminal (109, 110), to start constantly outputting a second enable signal to the differential signal receiver, wherein the differential signal receiver is adapted to remain in an active state while at least either one of the first and the second enable signal is being input thereto, and wherein the first differential signal (RCLK+, RCLK-) is a clock signal for the second differential signal (D0+, D0-).