A semiconductor light emitting element having a cross-sectional structure comprising: a support substrate; a semiconductor lamination located over the support substrate, containing at least a p-type semiconductor layer, an active layer having a light emitting characteristic and an n-type semiconductor layer, and having a reverse tapered overall cross-sectional shape relative to the support substrate; and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side, and fixing the positional relationship between the semiconductor lamination and the support substrate by joining the first and second jointing layers (51, 52), wherein in a plan view: the semiconductor lamination has corner portions and side portions along the periphery; the first jointing layer is encompassed by the second jointing layer; the second jointing layer is encompassed by the semiconductor lamination; and an annular region defined between an outline of the semiconductor lamination and an outline of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths (L2, L3) of the first portions being narrower than widths of the second portions. a support substrate; a semiconductor lamination located over the support substrate, containing at least a p-type semiconductor layer, an active layer having a light emitting characteristic and an n-type semiconductor layer, and having a reverse tapered overall cross-sectional shape relative to the support substrate; and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side, and fixing the positional relationship between the semiconductor lamination and the support substrate by joining the first and second jointing layers (51, 52), wherein in a plan view: the semiconductor lamination has corner portions and side portions along the periphery; the first jointing layer is encompassed by the second jointing layer; the second jointing layer is encompassed by the semiconductor lamination; and an annular region defined between an outline of the semiconductor lamination and an outline of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths (L2, L3) of the first portions being narrower than widths of the second portions. the semiconductor lamination has corner portions and side portions along the periphery; the first jointing layer is encompassed by the second jointing layer; the second jointing layer is encompassed by the semiconductor lamination; and an annular region defined between an outline of the semiconductor lamination and an outline of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths (L2, L3) of the first portions being narrower than widths of the second portions.