An apparatus, comprising: an array of memory cells of a memory circuit; a temperature sensor coupled to the array and having an output, said temperature sensor configured to provide an output signal at said output wherein the output signal is a function of the temperature of the array of memory cells; a memory controller electrically coupled to the array of cells of the memory circuit and configured to control the array of memory cells; and multiple mode error correction code logic having an input coupled to the temperature sensor output, said multiple mode error correction code logic configured to encode write data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells, wherein said plurality of error correction modes includes a first error correction mode at a first error correction level at a first memory cell array temperature level, and further includes a second error correction mode at a second error correction level lower than the first error correction level at a second memory cell array temperature level lower than the first memory cell array temperature level, wherein the array of memory cells includes a subarray, and wherein the multiple mode error correction code logic is configured to encode write data for the array of memory cells in the first error correction mode at the first error correction level to provide an error correction code word having a first length, at least a portion of which is stored in the subarray of memory cells, and is configured to encode write data for the array of memory cells in the second error correction mode at the second error correction level to provide an error correction code word having a second length shorter than the first length and which is not stored within the subarray, is configured to decode read data from the array of memory cells encoded in an error correction code word having the first length, and is configured to decode read data from the array of memory cells encoded in an error correction code word having the second length shorter than the first length, and wherein, in the second error correction mode at the second error correction level at the second memory cell array temperature level, the subarray is configured to be dormant in which operation is suspended or otherwise operated at reduced or no power. an array of memory cells of a memory circuit; a temperature sensor coupled to the array and having an output, said temperature sensor configured to provide an output signal at said output wherein the output signal is a function of the temperature of the array of memory cells; a memory controller electrically coupled to the array of cells of the memory circuit and configured to control the array of memory cells; and multiple mode error correction code logic having an input coupled to the temperature sensor output, said multiple mode error correction code logic configured to encode write data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells, wherein said plurality of error correction modes includes a first error correction mode at a first error correction level at a first memory cell array temperature level, and further includes a second error correction mode at a second error correction level lower than the first error correction level at a second memory cell array temperature level lower than the first memory cell array temperature level, wherein the array of memory cells includes a subarray, and wherein the multiple mode error correction code logic is configured to encode write data for the array of memory cells in the first error correction mode at the first error correction level to provide an error correction code word having a first length, at least a portion of which is stored in the subarray of memory cells, and is configured to encode write data for the array of memory cells in the second error correction mode at the second error correction level to provide an error correction code word having a second length shorter than the first length and which is not stored within the subarray, is configured to decode read data from the array of memory cells encoded in an error correction code word having the first length, and is configured to decode read data from the array of memory cells encoded in an error correction code word having the second length shorter than the first length, and wherein, in the second error correction mode at the second error correction level at the second memory cell array temperature level, the subarray is configured to be dormant in which operation is suspended or otherwise operated at reduced or no power.