A method of manufacturing an array substrate, the method comprising: forming a first thin film transistor and a first electrode on a substrate, wherein the forming the first thin film transistor and the first electrode comprises: forming a gate, the first electrode, a gate insulating layer, an active layer, and an etch stop layer on the substrate, and wherein the etch stop layer and the gate insulating layer cover the first electrode; forming first via holes and a second via hole, wherein the first via holes are formed at positions corresponding to the active layer, and pass through the etch stop layer, and wherein the second via hole is formed at a position corresponding to the first electrode, and passes through the etch stop layer and the gate insulating layer; and forming a source and a drain, wherein the source and the drain are electrically connected to the active layer through the first via holes, and wherein a maximal diameter of the first via holes is not greater than a minimal diameter of the second via hole, wherein the forming the first via holes and the second via hole comprises: forming a photoresist covering the etch stop layer; exposing the photoresist by means of a mask, and developing the exposed photoresist to form a photoresist-removed region, a photoresist-retained region, and a photoresist-partially-retained region, wherein the photoresist-removed region is used to form the second via hole, and the photoresist-partially-retained region is used to form the first via holes; etching a portion of the etch stop layer at the second via hole to form a portion of the second via hole; performing an ashing process on the photoresist, to remove a portion of the photoresist at the first via holes; etching a portion of the etch stop layer at the first via holes and etching a portion of the gate insulating layer at the second via hole through the portion of the second via hole to form a remaining portion of the second via hole; and peeling off the photoresist. forming a first thin film transistor and a first electrode on a substrate, wherein the forming the first thin film transistor and the first electrode comprises: forming a gate, the first electrode, a gate insulating layer, an active layer, and an etch stop layer on the substrate, and wherein the etch stop layer and the gate insulating layer cover the first electrode; forming first via holes and a second via hole, wherein the first via holes are formed at positions corresponding to the active layer, and pass through the etch stop layer, and wherein the second via hole is formed at a position corresponding to the first electrode, and passes through the etch stop layer and the gate insulating layer; and forming a source and a drain, wherein the source and the drain are electrically connected to the active layer through the first via holes, and wherein a maximal diameter of the first via holes is not greater than a minimal diameter of the second via hole, wherein the forming the first via holes and the second via hole comprises: forming a photoresist covering the etch stop layer; exposing the photoresist by means of a mask, and developing the exposed photoresist to form a photoresist-removed region, a photoresist-retained region, and a photoresist-partially-retained region, wherein the photoresist-removed region is used to form the second via hole, and the photoresist-partially-retained region is used to form the first via holes; etching a portion of the etch stop layer at the second via hole to form a portion of the second via hole; performing an ashing process on the photoresist, to remove a portion of the photoresist at the first via holes; etching a portion of the etch stop layer at the first via holes and etching a portion of the gate insulating layer at the second via hole through the portion of the second via hole to form a remaining portion of the second via hole; and peeling off the photoresist. forming a photoresist covering the etch stop layer; exposing the photoresist by means of a mask, and developing the exposed photoresist to form a photoresist-removed region, a photoresist-retained region, and a photoresist-partially-retained region, wherein the photoresist-removed region is used to form the second via hole, and the photoresist-partially-retained region is used to form the first via holes; etching a portion of the etch stop layer at the second via hole to form a portion of the second via hole; performing an ashing process on the photoresist, to remove a portion of the photoresist at the first via holes; etching a portion of the etch stop layer at the first via holes and etching a portion of the gate insulating layer at the second via hole through the portion of the second via hole to form a remaining portion of the second via hole; and peeling off the photoresist.