An apparatus for performing forward error correction of data to be transmitted over an optical communications channel, the apparatus comprising: an input interface; a preprocessor comprising circuitry coupled to the input interface and configured to: organize data bits received from the input interface into an arrangement having a plurality of blocks (301, 305, 306, 307, 309) organized into rows and columns, the plurality of blocks further organized into a plurality of strands of blocks including a first strand (303, 308) of blocks, the first strand of blocks comprising: a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and the apparatus further comprising: an encoder comprising circuitry configured to encode at least some of the data bits in the arrangement using a first error correcting code at least in part by: accessing first data bits in the front portion of the first strand (303, 308) of blocks; accessing second data bits in the back portion of the first strand (303, 308) of blocks; and generating first parity bits by applying the first error correcting code to the first data bits and the second data bits; wherein each of the plurality of blocks is part of two strands of the plurality of strands; wherein each of the plurality of blocks is an m by m block, wherein accessing the first data bits comprises accessing Tm data bits in the front portion of the first strand (303, 308) of blocks, wherein T is a positive integer greater than one specifying the number of columns of blocks in the arrangement, and wherein accessing the second data bits comprises accessing Tm-p data bits in the back portion of the first strand (303, 308) of blocks, wherein p is a positive integer, and wherein generating the first parity bits comprises generating p parity bits using the Tm data bits accessed in the front portion of the first strand (303, 308) of blocks and Tm-p data bits accessed in the back portion of the first strand (303, 308) of blocks. an input interface; a preprocessor comprising circuitry coupled to the input interface and configured to: organize data bits received from the input interface into an arrangement having a plurality of blocks (301, 305, 306, 307, 309) organized into rows and columns, the plurality of blocks further organized into a plurality of strands of blocks including a first strand (303, 308) of blocks, the first strand of blocks comprising: a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and an encoder comprising circuitry configured to encode at least some of the data bits in the arrangement using a first error correcting code at least in part by: accessing first data bits in the front portion of the first strand (303, 308) of blocks; accessing second data bits in the back portion of the first strand (303, 308) of blocks; and generating first parity bits by applying the first error correcting code to the first data bits and the second data bits; accessing first data bits in the front portion of the first strand (303, 308) of blocks; accessing second data bits in the back portion of the first strand (303, 308) of blocks; and generating first parity bits by applying the first error correcting code to the first data bits and the second data bits; wherein each of the plurality of blocks is part of two strands of the plurality of strands; wherein each of the plurality of blocks is an m by m block, wherein accessing the first data bits comprises accessing Tm data bits in the front portion of the first strand (303, 308) of blocks, wherein T is a positive integer greater than one specifying the number of columns of blocks in the arrangement, and wherein accessing the second data bits comprises accessing Tm-p data bits in the back portion of the first strand (303, 308) of blocks, wherein p is a positive integer, and wherein generating the first parity bits comprises generating p parity bits using the Tm data bits accessed in the front portion of the first strand (303, 308) of blocks and Tm-p data bits accessed in the back portion of the first strand (303, 308) of blocks.