A transceiver, comprising a receiving circuit and a transmitting circuit; wherein the transmitting circuit comprises: a first digital interface circuit (110, 210, 310, 410, 510, 610, 701, 801, 901, 1001, 1101), configured to obtain, in a predetermined bandwidth, first data to be sent, and decompose the first data into N parallel first sub digital signal flows, wherein a bandwidth occupied by each first sub digital signal flow of the N first sub digital signal flows is smaller than the predetermined bandwidth and N is a positive integer greater than 1; a first digital modulation circuit (120, 220, 320, 420, 520, 620), configured to receive the N first sub digital signal flows, and modulate the N first sub digital signal flows to obtain N first modulated signals; a first frequency relocation circuit (130, 230, 330, 430, 530, 630), configured to receive the N first modulated signals, and perform frequency relocation on the N first modulated signals, so that there is no frequency band gap between adjacent first modulated signals of the N first modulated signals that have undergone frequency relocation; a first synthesizer (140, 240, 340, 440, 540, 640), configured to synthesize M first modulated signals of the N first modulated signals that have undergone frequency relocation into a first bandwidth signal, wherein M is a positive integer smaller than or equal to N; a first digital to analog converter (150, 250, 350, 450, 550, 650), configured to receive the first bandwidth signal, and perform digital to analog conversion on the first bandwidth signal to obtain a first analog signal; and a first up-conversion circuit (160, 260, 360, 460, 560, 660), configured to receive the first analog signal, and convert the first analog signal into a first frequency signal, so that the radio frequency signal is sent to the receiving circuit by a first antenna; wherein the receiving circuit comprises: a down-conversion circuit, configured to convert a radio frequency signal received on a receiving antenna into an analog signal; an intermediate frequency power divider, configured to decompose the analog signal into N parallel sub analog signal flows; a second frequency relocation circuit, configured to perform frequency relocation on the N parallel sub analog signal flows; N analog to digital converters, configured to perform analog to digital conversion on the N parallel sub analog signal flows respectively to obtain N parallel digital signal flows; a digital demodulation circuit, configured to perform demodulation processing on the N parallel digital signal flows to obtain N parallel demodulated signals; and a second digital interface circuit, configured to synthesize the N parallel demodulated signals into second data. a first digital interface circuit (110, 210, 310, 410, 510, 610, 701, 801, 901, 1001, 1101), configured to obtain, in a predetermined bandwidth, first data to be sent, and decompose the first data into N parallel first sub digital signal flows, wherein a bandwidth occupied by each first sub digital signal flow of the N first sub digital signal flows is smaller than the predetermined bandwidth and N is a positive integer greater than 1; a first digital modulation circuit (120, 220, 320, 420, 520, 620), configured to receive the N first sub digital signal flows, and modulate the N first sub digital signal flows to obtain N first modulated signals; a first frequency relocation circuit (130, 230, 330, 430, 530, 630), configured to receive the N first modulated signals, and perform frequency relocation on the N first modulated signals, so that there is no frequency band gap between adjacent first modulated signals of the N first modulated signals that have undergone frequency relocation; a first synthesizer (140, 240, 340, 440, 540, 640), configured to synthesize M first modulated signals of the N first modulated signals that have undergone frequency relocation into a first bandwidth signal, wherein M is a positive integer smaller than or equal to N; a first digital to analog converter (150, 250, 350, 450, 550, 650), configured to receive the first bandwidth signal, and perform digital to analog conversion on the first bandwidth signal to obtain a first analog signal; and a first up-conversion circuit (160, 260, 360, 460, 560, 660), configured to receive the first analog signal, and convert the first analog signal into a first frequency signal, so that the radio frequency signal is sent to the receiving circuit by a first antenna; a down-conversion circuit, configured to convert a radio frequency signal received on a receiving antenna into an analog signal; an intermediate frequency power divider, configured to decompose the analog signal into N parallel sub analog signal flows; a second frequency relocation circuit, configured to perform frequency relocation on the N parallel sub analog signal flows; N analog to digital converters, configured to perform analog to digital conversion on the N parallel sub analog signal flows respectively to obtain N parallel digital signal flows; a digital demodulation circuit, configured to perform demodulation processing on the N parallel digital signal flows to obtain N parallel demodulated signals; and a second digital interface circuit, configured to synthesize the N parallel demodulated signals into second data.