An output waveform synthesizer for a low-power broadband transmitter, the output waveform synthesizer comprising: a clock generator; a 2N number of phase interpolators configured to control rising and falling edges of an N number of different phase clock signals (Φ0, Φ90, Φ180, Φ270) generated by the clock generator, N being a positive even number; an N-to-1 multiplexer; an output driver receiving an output from the N-to-1 multiplexer; an eye open monitoring unit configured to measure an output of the output driver to quantitatively determine a signal eye diagram of the output of the N-to-1 multiplexer; and a micro controller unlit configured to receive the measured signal eye diagram and to update phase control codes for the 2N number of phase interpolators using the measured signal eye diagram and a pre-defined calibration algorithm, wherein a 2N number of outputs (Φ0_rising, Φ0_falling, Φ90_rising, Φ90_falling,..., Φ270_falling) of the 2N number of phase interpolators are inputted as clock signals to the N-to-1 multiplexer, an n-th clock signal of the N number of different phase clock signals having ((n-1)*(2π/N)) phase, n being a natural number between 1 and N, wherein the 2N number of phase interpolators are configured into N number of groups, and all of the n-th clock signal and (n+1)-th clock signal are inputted to each of two phase interpolators included in the n-th group of the N number of groups so as to control rising and falling edges of the clock signals, respectively, by said respective two phase interpolators included in the n-th group based on the phase control codes received from the microcontroller unit so that the two outputs of said respective two phase interpolators are used as a single phase clock with independently controllable rise and fall delays. a clock generator; a 2N number of phase interpolators configured to control rising and falling edges of an N number of different phase clock signals (Φ0, Φ90, Φ180, Φ270) generated by the clock generator, N being a positive even number; an N-to-1 multiplexer; an output driver receiving an output from the N-to-1 multiplexer; an eye open monitoring unit configured to measure an output of the output driver to quantitatively determine a signal eye diagram of the output of the N-to-1 multiplexer; and a micro controller unlit configured to receive the measured signal eye diagram and to update phase control codes for the 2N number of phase interpolators using the measured signal eye diagram and a pre-defined calibration algorithm, wherein a 2N number of outputs (Φ0_rising, Φ0_falling, Φ90_rising, Φ90_falling,..., Φ270_falling) of the 2N number of phase interpolators are inputted as clock signals to the N-to-1 multiplexer, an n-th clock signal of the N number of different phase clock signals having ((n-1)*(2π/N)) phase, n being a natural number between 1 and N, wherein the 2N number of phase interpolators are configured into N number of groups, and all of the n-th clock signal and (n+1)-th clock signal are inputted to each of two phase interpolators included in the n-th group of the N number of groups so as to control rising and falling edges of the clock signals, respectively, by said respective two phase interpolators included in the n-th group based on the phase control codes received from the microcontroller unit so that the two outputs of said respective two phase interpolators are used as a single phase clock with independently controllable rise and fall delays.