An apparatus comprising: a sample-and-hold S/H circuit that is configured to generate a sample voltage from an input signal and store the sample voltage on a first and a second sampling capacitor, wherein the S/H circuit is controlled by a sample clock signal; a digital-to-analog converter DAC that is coupled to an output terminal of the S/H circuit so as to apply at least one of a plurality of currents to the output terminal of the S/H circuit; a comparator that has a first input coupled to the output terminal of the S/H circuit and a second input coupled to a reference voltage; a counter that is configured to determine the length of a first time interval over which a first voltage on the first sampling capacitor of the S/H circuit changes from the sample voltage to the reference voltage using a first current of the plurality of currents from the DAC; and a controller that is coupled to the comparator, the DAC, the counter, and the S/H circuit, wherein the controller is configured to provide the sample clock signal to the S/H circuit, and wherein the controller is configured to provide a clock signal to the counter, and wherein the controller is configured to adjust the DAC to provide a second current after the first voltage on the first sampling capacitor of the S/H circuit reaches the reference voltage, and wherein the counter is configured to determine the length of a second time interval over which a second voltage on the second sampling capacitor of the S/H circuit changes from the sample voltage to the reference voltage using the second current of the plurality of currents from the DAC, wherein the first time interval is shorter than the second time interval; an output circuit coupled to the counter and the controller and configured to determine a digital representation of the sample voltage based on the second time interval if the voltage on the second capacitor reaches the reference voltage using the second current before a subsequent sampling instant; and determine the digital representation of the sample voltage based on the first time interval if the voltage on the second capacitor does not reach the reference voltage using the second current before the subsequent sampling instant. a sample-and-hold S/H circuit that is configured to generate a sample voltage from an input signal and store the sample voltage on a first and a second sampling capacitor, wherein the S/H circuit is controlled by a sample clock signal; a digital-to-analog converter DAC that is coupled to an output terminal of the S/H circuit so as to apply at least one of a plurality of currents to the output terminal of the S/H circuit; a comparator that has a first input coupled to the output terminal of the S/H circuit and a second input coupled to a reference voltage; a counter that is configured to determine the length of a first time interval over which a first voltage on the first sampling capacitor of the S/H circuit changes from the sample voltage to the reference voltage using a first current of the plurality of currents from the DAC; and a controller that is coupled to the comparator, the DAC, the counter, and the S/H circuit, wherein the controller is configured to provide the sample clock signal to the S/H circuit, and wherein the controller is configured to provide a clock signal to the counter, and wherein the controller is configured to adjust the DAC to provide a second current after the first voltage on the first sampling capacitor of the S/H circuit reaches the reference voltage, and wherein the counter is configured to determine the length of a second time interval over which a second voltage on the second sampling capacitor of the S/H circuit changes from the sample voltage to the reference voltage using the second current of the plurality of currents from the DAC, wherein the first time interval is shorter than the second time interval; an output circuit coupled to the counter and the controller and configured to determine a digital representation of the sample voltage based on the second time interval if the voltage on the second capacitor reaches the reference voltage using the second current before a subsequent sampling instant; and determine the digital representation of the sample voltage based on the first time interval if the voltage on the second capacitor does not reach the reference voltage using the second current before the subsequent sampling instant.