A sense amplifier comprising: a differential pair of transistors configured to steer a current responsive to a voltage difference between a pair of bit lines, wherein the differential pair of transistors includes a first differential pair transistor and a second differential pair transistor, and wherein the sense amplifier includes a first output terminal formed by a first terminal for the first differential pair transistor and includes a second output terminal formed by a first terminal for a the second differential pair transistor; a delay circuit configured to delay a sense enable signal to provide a delayed sense enable signal; a pair of first pull-up transistors corresponding to the differential pair of transistors, each first pull-up transistor being having a first terminal electrically connected to the first terminal of the corresponding differential pair transistor and having a second terminal electrically connected to a power supply node, wherein each first pull-up transistor is configured to switch off responsive to an assertion of the delayed sense enable signal; and characterised in that the sense amplifier additionally comprises a pair of second pull-up transistors corresponding to the differential pair of transistors, each second pull-up transistor having a first terminal electrically connected to the first terminal of the corresponding differential pair transistor and having a second terminal electrically connected to the power supply node, wherein each second pull-up transistor is configured to be always on, and wherein a size for each second pull-up transistor is smaller than a size for each first pull-up transistor. a differential pair of transistors configured to steer a current responsive to a voltage difference between a pair of bit lines, wherein the differential pair of transistors includes a first differential pair transistor and a second differential pair transistor, and wherein the sense amplifier includes a first output terminal formed by a first terminal for the first differential pair transistor and includes a second output terminal formed by a first terminal for a the second differential pair transistor; a delay circuit configured to delay a sense enable signal to provide a delayed sense enable signal; a pair of first pull-up transistors corresponding to the differential pair of transistors, each first pull-up transistor being having a first terminal electrically connected to the first terminal of the corresponding differential pair transistor and having a second terminal electrically connected to a power supply node, wherein each first pull-up transistor is configured to switch off responsive to an assertion of the delayed sense enable signal; and characterised in that the sense amplifier additionally comprises a pair of second pull-up transistors corresponding to the differential pair of transistors, each second pull-up transistor having a first terminal electrically connected to the first terminal of the corresponding differential pair transistor and having a second terminal electrically connected to the power supply node, wherein each second pull-up transistor is configured to be always on, and wherein a size for each second pull-up transistor is smaller than a size for each first pull-up transistor.