A semiconductor device comprising a body (1; 100; 100'; 200), the body (1; 100; 100'; 200) including: - a substrate (2; 102; 202) of semiconductor material; - a structural layer (10; 107; 207) of semiconductor material; - a dielectric layer (12; 103; 203) arranged between the substrate (2; 102; 202) and the structural layer (10; 107; 207); and - a through interconnection via (30; 130; 160; 230) traversing the body (1; 100; 100'; 200) and extending from a back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) to a front face (10a; 107a; 207a) of the structural layer (10; 107; 207) through the dielectric layer (12; 103; 203), wherein the through interconnection via (30; 130; 160; 230) comprises a semiconductor front-side interconnection region (17; 113; 113'; 210), including a portion of the structural layer (10; 107; 207), that extends from the dielectric layer (12; 103; 203) to the front face (10a; 107a; 207a) of the structural layer (10; 107; 207) and is laterally separated and insulated from the remainder of the structural layer (10; 107; 207) by a front-side insulation trench (15; 110; 209) that extends from the front face (10a; 107a; 207a) of the structural layer (10; 107; 207) to the dielectric layer (12; 103; 203); characterized in that the through interconnection via (30; 130; 160; 230) comprises: - a semiconductor back-side interconnection region (27; 120; 120'; 217), including a portion of the substrate (2; 102; 202), that extends from the dielectric layer (12; 103; 203) to the back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) and is laterally insulated from the remainder of the substrate (2; 102; 202) by a back-side insulation trench (29; 121; 121'; 215), wherein the back-side insulation trench (29; 121; 121'; 215) extends across the entire substrate (2; 102; 202), from the back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) to the dielectric layer (12; 103; 203); and - a semiconductor continuity region (8; 108; 208), connecting the front-side interconnection region (17; 113; 113'; 210) and the back-side interconnection region (27; 120; 120'; 217) through the dielectric layer (12; 103; 203); wherein the front-side interconnection region (17; 113; 113'; 210), the back-side interconnection region (27; 120; 120'; 217) and the continuity region (8; 108; 208) are all aligned. - a substrate (2; 102; 202) of semiconductor material; - a structural layer (10; 107; 207) of semiconductor material; - a dielectric layer (12; 103; 203) arranged between the substrate (2; 102; 202) and the structural layer (10; 107; 207); and - a through interconnection via (30; 130; 160; 230) traversing the body (1; 100; 100'; 200) and extending from a back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) to a front face (10a; 107a; 207a) of the structural layer (10; 107; 207) through the dielectric layer (12; 103; 203), wherein the through interconnection via (30; 130; 160; 230) comprises a semiconductor front-side interconnection region (17; 113; 113'; 210), including a portion of the structural layer (10; 107; 207), that extends from the dielectric layer (12; 103; 203) to the front face (10a; 107a; 207a) of the structural layer (10; 107; 207) and is laterally separated and insulated from the remainder of the structural layer (10; 107; 207) by a front-side insulation trench (15; 110; 209) that extends from the front face (10a; 107a; 207a) of the structural layer (10; 107; 207) to the dielectric layer (12; 103; 203); characterized in that the through interconnection via (30; 130; 160; 230) comprises: - a semiconductor back-side interconnection region (27; 120; 120'; 217), including a portion of the substrate (2; 102; 202), that extends from the dielectric layer (12; 103; 203) to the back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) and is laterally insulated from the remainder of the substrate (2; 102; 202) by a back-side insulation trench (29; 121; 121'; 215), wherein the back-side insulation trench (29; 121; 121'; 215) extends across the entire substrate (2; 102; 202), from the back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) to the dielectric layer (12; 103; 203); and - a semiconductor continuity region (8; 108; 208), connecting the front-side interconnection region (17; 113; 113'; 210) and the back-side interconnection region (27; 120; 120'; 217) through the dielectric layer (12; 103; 203); wherein the front-side interconnection region (17; 113; 113'; 210), the back-side interconnection region (27; 120; 120'; 217) and the continuity region (8; 108; 208) are all aligned. - a semiconductor back-side interconnection region (27; 120; 120'; 217), including a portion of the substrate (2; 102; 202), that extends from the dielectric layer (12; 103; 203) to the back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) and is laterally insulated from the remainder of the substrate (2; 102; 202) by a back-side insulation trench (29; 121; 121'; 215), wherein the back-side insulation trench (29; 121; 121'; 215) extends across the entire substrate (2; 102; 202), from the back face (2a; 102a; 202a) of the body (1; 100; 100'; 200) to the dielectric layer (12; 103; 203); and - a semiconductor continuity region (8; 108; 208), connecting the front-side interconnection region (17; 113; 113'; 210) and the back-side interconnection region (27; 120; 120'; 217) through the dielectric layer (12; 103; 203); wherein the front-side interconnection region (17; 113; 113'; 210), the back-side interconnection region (27; 120; 120'; 217) and the continuity region (8; 108; 208) are all aligned.