A graphics processing system, comprising: a bus interface configured to receive an external graphics processing command; a graphics processing unit, comprising a thermal sensor, configured to detect temperature information of the graphics processing unit; a plurality of hardware components for graphics processing that are divided into a plurality of partitions (151, 152, 153, 154); and a control circuit configured to control a power state of each partition (151, 152, 153, 154), detect a respective idle state signal from each partition (151, 152, 153, 154) indicating being in an idle state, and generate a full idle state signal in response to the temperature information from the thermal sensor and the respective idle state signals from each partition (151, 152, 153, 154) indicating being in the idle state; and a power management unit configured to control power to the graphics processing unit, wherein the bus interface is external to the graphics processing unit, wherein the bus interface is configured, when the bus interface has received the external graphics processing command, to inform the power management unit to turn on the power to the control circuit, and the control circuit is configured to turn on the power to one or more of the partitions (151, 152, 153, 154) corresponding to the external graphics processing command after the control circuit analyzes the external graphics processing command, wherein the control circuit is configured to turn off the power to the partitions (151, 152, 153, 154) in the idle state when the control circuit has detected that one of the partitions (151, 152, 153, 154) is in the idle state, wherein the bus interface is configured, when the bus interface has detected the full idle state signal from the control circuit indicating that all the partitions (151, 152, 153, 154) are in the idle state, to turn off the power to the control circuit via the power management unit. a bus interface configured to receive an external graphics processing command; a graphics processing unit, comprising a thermal sensor, configured to detect temperature information of the graphics processing unit; a plurality of hardware components for graphics processing that are divided into a plurality of partitions (151, 152, 153, 154); and a control circuit configured to control a power state of each partition (151, 152, 153, 154), detect a respective idle state signal from each partition (151, 152, 153, 154) indicating being in an idle state, and generate a full idle state signal in response to the temperature information from the thermal sensor and the respective idle state signals from each partition (151, 152, 153, 154) indicating being in the idle state; and a thermal sensor, configured to detect temperature information of the graphics processing unit; a plurality of hardware components for graphics processing that are divided into a plurality of partitions (151, 152, 153, 154); and a control circuit configured to control a power state of each partition (151, 152, 153, 154), detect a respective idle state signal from each partition (151, 152, 153, 154) indicating being in an idle state, and generate a full idle state signal in response to the temperature information from the thermal sensor and the respective idle state signals from each partition (151, 152, 153, 154) indicating being in the idle state; and a power management unit configured to control power to the graphics processing unit, wherein the bus interface is external to the graphics processing unit, wherein the bus interface is configured, when the bus interface has received the external graphics processing command, to inform the power management unit to turn on the power to the control circuit, and the control circuit is configured to turn on the power to one or more of the partitions (151, 152, 153, 154) corresponding to the external graphics processing command after the control circuit analyzes the external graphics processing command, wherein the control circuit is configured to turn off the power to the partitions (151, 152, 153, 154) in the idle state when the control circuit has detected that one of the partitions (151, 152, 153, 154) is in the idle state, wherein the bus interface is configured, when the bus interface has detected the full idle state signal from the control circuit indicating that all the partitions (151, 152, 153, 154) are in the idle state, to turn off the power to the control circuit via the power management unit.