A polar modulator comprising: a modulation generator arranged to generate phase modulation data and amplitude modulation data; a phase modulation stage arranged to generate a phase modulated, PM, carrier signal and a PM clock signal, wherein the PM carrier signal has a PM carrier signal frequency and the PM clock signal has a PM clock signal frequency, and the PM carrier signal frequency is higher than the PM clock signal frequency, and the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data; an amplitude modulation stage arranged to employ an amplitude modulation, AM, clock signal to clock the amplitude modulation data into the amplitude modulation stage and arranged to amplitude modulate the PM carrier signal with the amplitude modulation data; characterised by: the phase modulation stage comprising an adjustable delay stage arranged to adjust a relative delay between the PM carrier signal and the PM clock signal to a target value; a re-timing circuit arranged to generate the AM clock signal by re-timing the PM clock signal with the PM carrier signal; an error detection stage arranged to generate an indication of a magnitude of a first deviation of the AM clock signal from a target condition; and a control stage arranged to select the target value of the relative delay by determining, by controlling the adjustment of the relative delay by the adjustable delay stage, a first value of the relative delay that maximises the magnitude of the first deviation of the AM clock signal from the target condition, and applying an offset to the first value of the relative delay. a modulation generator arranged to generate phase modulation data and amplitude modulation data; a phase modulation stage arranged to generate a phase modulated, PM, carrier signal and a PM clock signal, wherein the PM carrier signal has a PM carrier signal frequency and the PM clock signal has a PM clock signal frequency, and the PM carrier signal frequency is higher than the PM clock signal frequency, and the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data; the PM carrier signal has a PM carrier signal frequency and the PM clock signal has a PM clock signal frequency, and the PM carrier signal frequency is higher than the PM clock signal frequency, and the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data; an amplitude modulation stage arranged to employ an amplitude modulation, AM, clock signal to clock the amplitude modulation data into the amplitude modulation stage and arranged to amplitude modulate the PM carrier signal with the amplitude modulation data; characterised by: the phase modulation stage comprising an adjustable delay stage arranged to adjust a relative delay between the PM carrier signal and the PM clock signal to a target value; a re-timing circuit arranged to generate the AM clock signal by re-timing the PM clock signal with the PM carrier signal; an error detection stage arranged to generate an indication of a magnitude of a first deviation of the AM clock signal from a target condition; and a control stage arranged to select the target value of the relative delay by determining, by controlling the adjustment of the relative delay by the adjustable delay stage, a first value of the relative delay that maximises the magnitude of the first deviation of the AM clock signal from the target condition, and applying an offset to the first value of the relative delay. the phase modulation stage comprising an adjustable delay stage arranged to adjust a relative delay between the PM carrier signal and the PM clock signal to a target value; a re-timing circuit arranged to generate the AM clock signal by re-timing the PM clock signal with the PM carrier signal; an error detection stage arranged to generate an indication of a magnitude of a first deviation of the AM clock signal from a target condition; and a control stage arranged to select the target value of the relative delay by determining, by controlling the adjustment of the relative delay by the adjustable delay stage, a first value of the relative delay that maximises the magnitude of the first deviation of the AM clock signal from the target condition, and applying an offset to the first value of the relative delay.