An arithmetic processing apparatus comprising: an OS arithmetic processing unit (10_OS) which executes an instruction included in an Operating System; a plurality of general-purpose arithmetic processing units (10_GE) each executing an instruction included in a program other than the Operating System; a shared cache unit including a shared cache memory, which is shared among the plurality of general-purpose arithmetic processing units (10_GE) and the OS arithmetic processing unit (10_OS), a cache control unit, a cache control pipeline and a request selection circuit which selects a memory access request, among memory access requests from the plurality of general-purpose arithmetic processing units (10_GE) and the OS arithmetic processing unit (10_OS), to enter into the cache control unit, and a data buffer which temporarily stores data that is read from the shared cache memory or a main memory in response to the memory access request that is entered, until the read data stored in the data buffer is transmitted to the requesting OS arithmetic processing unit (10_OS) or one of the plurality of general_purpose arithmetic processing units (10_GE); and a memory access control unit which controls a memory access to the main memory, characterized in that the shared cache unit further has a memory access band control register including a first and a second set values set by a user program, said first set value is a set value that specifies a frequency of entering the selected memory access request from the OS arithmetic processing unit (10_OS) into the cache control pipeline and said second set value sets a capacity of a storage area in the data buffer for storing data corresponding to the memory access request from the OS arithmetic processing unit (10_OS), and wherein when the first set value is set, on the basis of the first set value, the request selection circuit selects the memory access request from the OS arithmetic processing unit (10_OS) to enter into the cache control pipeline and when the second set value is set, on the basis of the second set value, the cache control unit allocates the storage area for storing data corresponding to the selected memory access request from the OS arithmetic processing unit (10_OS). an OS arithmetic processing unit (10_OS) which executes an instruction included in an Operating System; a plurality of general-purpose arithmetic processing units (10_GE) each executing an instruction included in a program other than the Operating System; a shared cache unit including a shared cache memory, which is shared among the plurality of general-purpose arithmetic processing units (10_GE) and the OS arithmetic processing unit (10_OS), a cache control unit, a cache control pipeline and a request selection circuit which selects a memory access request, among memory access requests from the plurality of general-purpose arithmetic processing units (10_GE) and the OS arithmetic processing unit (10_OS), to enter into the cache control unit, and a data buffer which temporarily stores data that is read from the shared cache memory or a main memory in response to the memory access request that is entered, until the read data stored in the data buffer is transmitted to the requesting OS arithmetic processing unit (10_OS) or one of the plurality of general_purpose arithmetic processing units (10_GE); and a memory access control unit which controls a memory access to the main memory, characterized in that the shared cache unit further has a memory access band control register including a first and a second set values set by a user program, said first set value is a set value that specifies a frequency of entering the selected memory access request from the OS arithmetic processing unit (10_OS) into the cache control pipeline and said second set value sets a capacity of a storage area in the data buffer for storing data corresponding to the memory access request from the OS arithmetic processing unit (10_OS), and wherein when the first set value is set, on the basis of the first set value, the request selection circuit selects the memory access request from the OS arithmetic processing unit (10_OS) to enter into the cache control pipeline and when the second set value is set, on the basis of the second set value, the cache control unit allocates the storage area for storing data corresponding to the selected memory access request from the OS arithmetic processing unit (10_OS).