An apparatus for extending a x86 microprocessor instruction set, comprising: translation logic (504, 505; 605), for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: an extended prefix, for directing that an architectural extension be employed in the execution of an operation prescribed by said extended instruction; and an extended instruction tag, for indicating said extended instruction prefix, wherein said extended instruction tag is an otherwise architecturally specified, but unused, opcode within the microprocessor instruction set, and wherein said extended instruction tag comprises opcode F1H (ICE BKPT), and wherein employment of said architectural extension as directed by said extended prefix continues to allow execution of any other opcode in the microprocessor instruction set; and extended execution logic, coupled to said translation logic (504, 505; 605), for receiving said corresponding micro instructions, and for employing said architectural extension in the execution of said operation; wherein said extended instruction further comprises architecturally specified entities according to the microprocessor instruction set; and said extended prefix comprises a plurality of bits, and wherein logic states of said plurality of bits prescribe a plurality of architectural extensions to the microprocessor instruction set. translation logic (504, 505; 605), for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: an extended prefix, for directing that an architectural extension be employed in the execution of an operation prescribed by said extended instruction; and an extended instruction tag, for indicating said extended instruction prefix, wherein said extended instruction tag is an otherwise architecturally specified, but unused, opcode within the microprocessor instruction set, and wherein said extended instruction tag comprises opcode F1H (ICE BKPT), and wherein employment of said architectural extension as directed by said extended prefix continues to allow execution of any other opcode in the microprocessor instruction set; and extended execution logic, coupled to said translation logic (504, 505; 605), for receiving said corresponding micro instructions, and for employing said architectural extension in the execution of said operation; an extended prefix, for directing that an architectural extension be employed in the execution of an operation prescribed by said extended instruction; and an extended instruction tag, for indicating said extended instruction prefix, wherein said extended instruction tag is an otherwise architecturally specified, but unused, opcode within the microprocessor instruction set, and wherein said extended instruction tag comprises opcode F1H (ICE BKPT), and wherein employment of said architectural extension as directed by said extended prefix continues to allow execution of any other opcode in the microprocessor instruction set; and extended execution logic, coupled to said translation logic (504, 505; 605), for receiving said corresponding micro instructions, and for employing said architectural extension in the execution of said operation; wherein said extended instruction further comprises architecturally specified entities according to the microprocessor instruction set; and said extended prefix comprises a plurality of bits, and wherein logic states of said plurality of bits prescribe a plurality of architectural extensions to the microprocessor instruction set.