An apparatus, comprising: an instruction fetch unit configured to fetch instructions including a first control transfer instruction; a branch target array having a plurality of entries, wherein the apparatus is configured to generate a predicted target address for the first control transfer instruction, to cause an entry in the branch target array to be allocated and to associate a tag with an execution of the first control transfer instruction, the tag identifying the allocated entry in the branch target array, wherein the apparatus is configured to determine that the predicted target address for the first control transfer instruction is not definitively determined based on determining that the predicted target address crosses a page boundary, wherein the branch target array is configured to receive the predicted target address for the first control transfer instruction and to store the predicted target address in the allocated entry, wherein the branch target array is accessible, using the tag associated with execution of the first control transfer instruction, to retrieve the predicted target address, and wherein the apparatus is configured to not store a predicted target address of a second control transfer instruction when a target address of the second control transfer instruction is definitively determined before execution of the second control transfer instruction; and a branch execution unit configured to: compute an actual target address of the first control transfer instruction; retrieve the predicted target address from the branch target array using the tag; and compare the actual target address to the predicted target address to determine if the target address of the first control transfer instruction was correctly predicted. an instruction fetch unit configured to fetch instructions including a first control transfer instruction; a branch target array having a plurality of entries, wherein the apparatus is configured to generate a predicted target address for the first control transfer instruction, to cause an entry in the branch target array to be allocated and to associate a tag with an execution of the first control transfer instruction, the tag identifying the allocated entry in the branch target array, wherein the apparatus is configured to determine that the predicted target address for the first control transfer instruction is not definitively determined based on determining that the predicted target address crosses a page boundary, wherein the branch target array is configured to receive the predicted target address for the first control transfer instruction and to store the predicted target address in the allocated entry, wherein the branch target array is accessible, using the tag associated with execution of the first control transfer instruction, to retrieve the predicted target address, and wherein the apparatus is configured to not store a predicted target address of a second control transfer instruction when a target address of the second control transfer instruction is definitively determined before execution of the second control transfer instruction; and wherein the apparatus is configured to generate a predicted target address for the first control transfer instruction, to cause an entry in the branch target array to be allocated and to associate a tag with an execution of the first control transfer instruction, the tag identifying the allocated entry in the branch target array, wherein the apparatus is configured to determine that the predicted target address for the first control transfer instruction is not definitively determined based on determining that the predicted target address crosses a page boundary, wherein the branch target array is configured to receive the predicted target address for the first control transfer instruction and to store the predicted target address in the allocated entry, wherein the branch target array is accessible, using the tag associated with execution of the first control transfer instruction, to retrieve the predicted target address, and wherein the apparatus is configured to not store a predicted target address of a second control transfer instruction when a target address of the second control transfer instruction is definitively determined before execution of the second control transfer instruction; and a branch execution unit configured to: compute an actual target address of the first control transfer instruction; retrieve the predicted target address from the branch target array using the tag; and compare the actual target address to the predicted target address to determine if the target address of the first control transfer instruction was correctly predicted. compute an actual target address of the first control transfer instruction; retrieve the predicted target address from the branch target array using the tag; and compare the actual target address to the predicted target address to determine if the target address of the first control transfer instruction was correctly predicted.