A conditional execution apparatus for a microprocessor with a x86 instruction set, comprising: translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: an extended prefix, for specifying a condition, wherein execution of an operation prescribed by said extended instruction depends upon realization of said condition; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified, but unused, opcode within an instruction set for the microprocessor; and wherein said extended prefix tag comprises opcode F1H (ICE BKPT), and wherein execution of said operation upon realization of said condition as directed by said extended prefix continues to allow execution of any other opcode in the x86 instruction set; and remaining instruction entities, configured to specify said operation; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for evaluating said condition, wherein, if said condition is not realized, then said extended execution logic precludes execution of said operation; wherein said corresponding micro instructions comprise a micro opcode field and a micro opcode extension field; and said extended execution logic employs said micro opcode extension field to determine said condition, and wherein said extended execution logic employs said micro opcode field to determine said operation; where said extended execution logic comprises: a conditional execution controller, configured to evaluate said condition, and to enable/disable execution of said operation according to said condition. translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises: an extended prefix, for specifying a condition, wherein execution of an operation prescribed by said extended instruction depends upon realization of said condition; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified, but unused, opcode within an instruction set for the microprocessor; and wherein said extended prefix tag comprises opcode F1H (ICE BKPT), and wherein execution of said operation upon realization of said condition as directed by said extended prefix continues to allow execution of any other opcode in the x86 instruction set; and remaining instruction entities, configured to specify said operation; and an extended prefix, for specifying a condition, wherein execution of an operation prescribed by said extended instruction depends upon realization of said condition; and an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified, but unused, opcode within an instruction set for the microprocessor; and wherein said extended prefix tag comprises opcode F1H (ICE BKPT), and wherein execution of said operation upon realization of said condition as directed by said extended prefix continues to allow execution of any other opcode in the x86 instruction set; and remaining instruction entities, configured to specify said operation; and extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for evaluating said condition, wherein, if said condition is not realized, then said extended execution logic precludes execution of said operation; wherein said corresponding micro instructions comprise a micro opcode field and a micro opcode extension field; and said extended execution logic employs said micro opcode extension field to determine said condition, and wherein said extended execution logic employs said micro opcode field to determine said operation; where said extended execution logic comprises: a conditional execution controller, configured to evaluate said condition, and to enable/disable execution of said operation according to said condition.