A method for forming a semiconductor structure having a non-volatile memory, NVM, region and a logic region, the method comprising: forming an oxide-containing layer directly on a semiconductor layer in the NVM region; forming a first partial layer of a first material over the oxide-containing layer in the NVM region; forming a first dielectric layer directly on the semiconductor layer in the logic region; forming a first conductive layer over the first dielectric layer in the logic region; forming a second partial layer of the first material directly on the first partial layer in the NVM region and over the first conductive layer in the logic region; forming a logic device in the logic region, wherein the logic device includes a portion of the first dielectric layer and the first conductive layer; and forming an NVM cell in the NVM region using the oxide-containing layer, the first partial layer, and the second partial layer, wherein the first partial layer and the second partial layer together are used to form one of a charge storage layer if the NVM cell is a floating gate NVM cell or a select gate if the NVM cell is a split gate NVM cell, wherein the steps of forming the first dielectric layer and the first conductive layer are characterized by: depositing the first dielectric layer over the first partial layer in the NVM region and on the semiconductor layer in the logic region; depositing the first conductive layer over the first dielectric layer in the NVM region and the logic region; and using the first partial layer in the NVM region as an etch stop layer to remove the first conductive layer and the first dielectric layer from the NVM region, wherein the first dielectric layer has a high dielectric constant. forming an oxide-containing layer directly on a semiconductor layer in the NVM region; forming a first partial layer of a first material over the oxide-containing layer in the NVM region; forming a first dielectric layer directly on the semiconductor layer in the logic region; forming a first conductive layer over the first dielectric layer in the logic region; forming a second partial layer of the first material directly on the first partial layer in the NVM region and over the first conductive layer in the logic region; forming a logic device in the logic region, wherein the logic device includes a portion of the first dielectric layer and the first conductive layer; and forming an NVM cell in the NVM region using the oxide-containing layer, the first partial layer, and the second partial layer, wherein the first partial layer and the second partial layer together are used to form one of a charge storage layer if the NVM cell is a floating gate NVM cell or a select gate if the NVM cell is a split gate NVM cell, wherein the steps of forming the first dielectric layer and the first conductive layer are characterized by: depositing the first dielectric layer over the first partial layer in the NVM region and on the semiconductor layer in the logic region; depositing the first conductive layer over the first dielectric layer in the NVM region and the logic region; and using the first partial layer in the NVM region as an etch stop layer to remove the first conductive layer and the first dielectric layer from the NVM region, wherein the first dielectric layer has a high dielectric constant. depositing the first dielectric layer over the first partial layer in the NVM region and on the semiconductor layer in the logic region; depositing the first conductive layer over the first dielectric layer in the NVM region and the logic region; and using the first partial layer in the NVM region as an etch stop layer to remove the first conductive layer and the first dielectric layer from the NVM region, wherein the first dielectric layer has a high dielectric constant.