Integrated circuit, comprising: - a semiconductor substrate of silicon-on-insulator type lying essentially in a plane called the substrate plane; - a block located on the substrate comprising: • at least first and second oppositely doped semiconductor wells, placed beside each other in a given well plane parallel to the substrate plane; • contiguous standard cells (42, 43), each standard cell comprising first field-effect transistors (60, 62) in FDSOI technology, each first transistor (60, 62) comprising a first semiconductor ground plane (72, 80) located only above a single of the first or second wells, in order to be electrically biased by way of the well (38, 40) above which it is located; and • a clock tree cell encircled by standard cells, so that the clock tree cell is contiguous with standard cells (42, 43), the clock tree cell comprising: - a third semiconductor well, lying in the well plane, the third well having the same doping type as the doping of the first well; - second field-effect transistors (100, 102) in FDSOI technology, each second transistor comprising a second semiconductor ground plane (108, 110), each ground plane of each second transistor of the clock tree cell being located above the third well, in order to be electrically biased by way of this third well; and - a semiconductor strip extending continuously around the third well, in the well plane, the semiconductor strip having the opposite doping type to the doping of the third well, so as to electrically isolate the third well from the first well. - a semiconductor substrate of silicon-on-insulator type lying essentially in a plane called the substrate plane; - a block located on the substrate comprising: • at least first and second oppositely doped semiconductor wells, placed beside each other in a given well plane parallel to the substrate plane; • contiguous standard cells (42, 43), each standard cell comprising first field-effect transistors (60, 62) in FDSOI technology, each first transistor (60, 62) comprising a first semiconductor ground plane (72, 80) located only above a single of the first or second wells, in order to be electrically biased by way of the well (38, 40) above which it is located; and • a clock tree cell encircled by standard cells, so that the clock tree cell is contiguous with standard cells (42, 43), the clock tree cell comprising: - a third semiconductor well, lying in the well plane, the third well having the same doping type as the doping of the first well; - second field-effect transistors (100, 102) in FDSOI technology, each second transistor comprising a second semiconductor ground plane (108, 110), each ground plane of each second transistor of the clock tree cell being located above the third well, in order to be electrically biased by way of this third well; and - a semiconductor strip extending continuously around the third well, in the well plane, the semiconductor strip having the opposite doping type to the doping of the third well, so as to electrically isolate the third well from the first well. • at least first and second oppositely doped semiconductor wells, placed beside each other in a given well plane parallel to the substrate plane; • contiguous standard cells (42, 43), each standard cell comprising first field-effect transistors (60, 62) in FDSOI technology, each first transistor (60, 62) comprising a first semiconductor ground plane (72, 80) located only above a single of the first or second wells, in order to be electrically biased by way of the well (38, 40) above which it is located; and • a clock tree cell encircled by standard cells, so that the clock tree cell is contiguous with standard cells (42, 43), the clock tree cell comprising: - a third semiconductor well, lying in the well plane, the third well having the same doping type as the doping of the first well; - second field-effect transistors (100, 102) in FDSOI technology, each second transistor comprising a second semiconductor ground plane (108, 110), each ground plane of each second transistor of the clock tree cell being located above the third well, in order to be electrically biased by way of this third well; and - a semiconductor strip extending continuously around the third well, in the well plane, the semiconductor strip having the opposite doping type to the doping of the third well, so as to electrically isolate the third well from the first well. - a third semiconductor well, lying in the well plane, the third well having the same doping type as the doping of the first well; - second field-effect transistors (100, 102) in FDSOI technology, each second transistor comprising a second semiconductor ground plane (108, 110), each ground plane of each second transistor of the clock tree cell being located above the third well, in order to be electrically biased by way of this third well; and - a semiconductor strip extending continuously around the third well, in the well plane, the semiconductor strip having the opposite doping type to the doping of the third well, so as to electrically isolate the third well from the first well.