A receiver comprising: an interleaved analog to digital converter having multiple ADC channels (230A-H), wherein the interleaved ADC comprises: a first ADC pipeline unit (610) operating in normal operation mode during a first time period, the first ADC pipeline unit comprising: a first ADC pipeline (630) including an open-loop residue amplifier wherein the first ADC pipeline has non-linear characteristics; and a first lookup table (640), wherein a raw output of the first ADC pipeline provides a memory address to access the first look-up table, and wherein an output of the first ADC pipeline unit comprises content stored at the memory address of the first lookup table, the first lookup table configured to apply a non-linear mapping to compensate for non-linearity of the first ADC pipeline; and a second ADC pipeline unit (610) operating a calibration mode during the first time period, the second ADC pipeline unit (610) comprising: a second ADC pipeline (630) including an open-loop residue amplifier, wherein the second ADC pipeline has non-linear characteristics; and a second lookup table (640), wherein contents of the second lookup table are updated during the calibration mode based on a difference between current content of the second lookup table addressed by output of the second ADC pipeline and an expected output of the second pipeline unit; a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels. an interleaved analog to digital converter having multiple ADC channels (230A-H), wherein the interleaved ADC comprises: a first ADC pipeline unit (610) operating in normal operation mode during a first time period, the first ADC pipeline unit comprising: a first ADC pipeline (630) including an open-loop residue amplifier wherein the first ADC pipeline has non-linear characteristics; and a first lookup table (640), wherein a raw output of the first ADC pipeline provides a memory address to access the first look-up table, and wherein an output of the first ADC pipeline unit comprises content stored at the memory address of the first lookup table, the first lookup table configured to apply a non-linear mapping to compensate for non-linearity of the first ADC pipeline; and a second ADC pipeline unit (610) operating a calibration mode during the first time period, the second ADC pipeline unit (610) comprising: a second ADC pipeline (630) including an open-loop residue amplifier, wherein the second ADC pipeline has non-linear characteristics; and a second lookup table (640), wherein contents of the second lookup table are updated during the calibration mode based on a difference between current content of the second lookup table addressed by output of the second ADC pipeline and an expected output of the second pipeline unit; a first ADC pipeline unit (610) operating in normal operation mode during a first time period, the first ADC pipeline unit comprising: a first ADC pipeline (630) including an open-loop residue amplifier wherein the first ADC pipeline has non-linear characteristics; and a first lookup table (640), wherein a raw output of the first ADC pipeline provides a memory address to access the first look-up table, and wherein an output of the first ADC pipeline unit comprises content stored at the memory address of the first lookup table, the first lookup table configured to apply a non-linear mapping to compensate for non-linearity of the first ADC pipeline; and a first ADC pipeline (630) including an open-loop residue amplifier wherein the first ADC pipeline has non-linear characteristics; and a first lookup table (640), wherein a raw output of the first ADC pipeline provides a memory address to access the first look-up table, and wherein an output of the first ADC pipeline unit comprises content stored at the memory address of the first lookup table, the first lookup table configured to apply a non-linear mapping to compensate for non-linearity of the first ADC pipeline; and a second ADC pipeline unit (610) operating a calibration mode during the first time period, the second ADC pipeline unit (610) comprising: a second ADC pipeline (630) including an open-loop residue amplifier, wherein the second ADC pipeline has non-linear characteristics; and a second lookup table (640), wherein contents of the second lookup table are updated during the calibration mode based on a difference between current content of the second lookup table addressed by output of the second ADC pipeline and an expected output of the second pipeline unit; a second ADC pipeline (630) including an open-loop residue amplifier, wherein the second ADC pipeline has non-linear characteristics; and a second lookup table (640), wherein contents of the second lookup table are updated during the calibration mode based on a difference between current content of the second lookup table addressed by output of the second ADC pipeline and an expected output of the second pipeline unit; a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels.