An integrated circuit comprising: a semiconductor substrate; a first fin, a second fin, and a third fin wherein the first fin, the second fin and the third fin are comprised of undoped semiconductor material, and the first fin, the second fin and the third fin are disposed on the semiconductor substrate; a first gate electrode, of a first n-type metal-oxide-semiconductor, NMOS, transistor device having a first threshold voltage, on a top surface and sidewalls of the first fin, the first gate electrode including a layer of a first electrode material having a thickness above the top surface of the first fin and a layer of a second electrode material having a thickness over the layer of the first electrode material in the first gate electrode, the second electrode material having a different chemical composition than the first electrode material; a second gate electrode, of a second NMOS transistor device having a second threshold voltage, on a top surface and sidewalls of the second fin, wherein the second gate electrode includes a layer of the first electrode material having a thickness above the top surface of the second fin and a layer of the second electrode material having a thickness over the layer of the first electrode material in the second gate electrode, the thickness of the layer of the first electrode material in the second gate electrode being less than the thickness of the layer of the first electrode material in the first gate electrode; a third gate electrode, of a third n-type metal-oxide-semiconductor, NMOS, transistor device having a third threshold voltage, on a top surface and sidewalls of the third fin, the third gate electrode including a layer of the second electrode material having a thickness above the top surface of the third fin; and a first gate dielectric between the first gate electrode and the first fin, a second gate dielectric between the second gate electrode and the second fin, and a third gate dielectric between the third gate electrode and the third fin; wherein, the third threshold voltage is less than the second threshold voltage, the second threshold voltage is less than the first threshold voltage. a semiconductor substrate; a first fin, a second fin, and a third fin wherein the first fin, the second fin and the third fin are comprised of undoped semiconductor material, and the first fin, the second fin and the third fin are disposed on the semiconductor substrate; a first gate electrode, of a first n-type metal-oxide-semiconductor, NMOS, transistor device having a first threshold voltage, on a top surface and sidewalls of the first fin, the first gate electrode including a layer of a first electrode material having a thickness above the top surface of the first fin and a layer of a second electrode material having a thickness over the layer of the first electrode material in the first gate electrode, the second electrode material having a different chemical composition than the first electrode material; a second gate electrode, of a second NMOS transistor device having a second threshold voltage, on a top surface and sidewalls of the second fin, wherein the second gate electrode includes a layer of the first electrode material having a thickness above the top surface of the second fin and a layer of the second electrode material having a thickness over the layer of the first electrode material in the second gate electrode, the thickness of the layer of the first electrode material in the second gate electrode being less than the thickness of the layer of the first electrode material in the first gate electrode; a third gate electrode, of a third n-type metal-oxide-semiconductor, NMOS, transistor device having a third threshold voltage, on a top surface and sidewalls of the third fin, the third gate electrode including a layer of the second electrode material having a thickness above the top surface of the third fin; and a first gate dielectric between the first gate electrode and the first fin, a second gate dielectric between the second gate electrode and the second fin, and a third gate dielectric between the third gate electrode and the third fin; wherein, the third threshold voltage is less than the second threshold voltage, the second threshold voltage is less than the first threshold voltage.