A method to perform an auto erase-suspend operation by using an erase-suspend feature in a memory device that includes a control circuit, a trim set register, a feature set register and a host interface, the method comprising: sending, by a memory controller, an erase-suspend enable setting and an erase segment duration value, separate from each other, to the memory device to enable the auto erase-suspend feature, the erase-suspend enable setting to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments, and the erase segment duration value to specify a length of time for the erase segments, wherein the erase segment duration value is changed less frequently than the erase-suspend enable setting; initiating, by the memory controller, an erase operation to be performed at the memory device; suspending, at the memory device, the erase operation based on the erase segment duration value being satisfied by an elapsed length of time for erasing one of the plurality of erase segments; when the erase operation is suspended, initiating, by the memory controller, a second memory operation to be performed at the memory device; and after determining, by the memory controller, that the second memory operation is complete, initiating resumption of the erase operation, wherein the sending of the erase-suspend enable setting to the memory device is in order to program the feature set register of the memory device to cause the memory device to suspend the erase operation between the erase segments, the feature set register being implemented in a latch, the control circuit of the memory device receiving the erase-suspend enable setting from the memory controller via the host interface of the memory device and programming the erase-suspend enable setting in the feature set register, and wherein the sending of the erase segment duration value to the memory device is in order to program the trim set register of the memory device, the control circuit of the memory device receiving the erase segment duration value from the memory controller via the host interface of the memory device and programming the erase segment duration value in the trim set register, the trim set register being implemented in static random access memory, the static random access memory being less flexible for writing than the latch due to an static random access memory cell having less transistors to provide its bit storage capabilities relative to the latch. sending, by a memory controller, an erase-suspend enable setting and an erase segment duration value, separate from each other, to the memory device to enable the auto erase-suspend feature, the erase-suspend enable setting to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments, and the erase segment duration value to specify a length of time for the erase segments, wherein the erase segment duration value is changed less frequently than the erase-suspend enable setting; initiating, by the memory controller, an erase operation to be performed at the memory device; suspending, at the memory device, the erase operation based on the erase segment duration value being satisfied by an elapsed length of time for erasing one of the plurality of erase segments; when the erase operation is suspended, initiating, by the memory controller, a second memory operation to be performed at the memory device; and after determining, by the memory controller, that the second memory operation is complete, initiating resumption of the erase operation, wherein the sending of the erase-suspend enable setting to the memory device is in order to program the feature set register of the memory device to cause the memory device to suspend the erase operation between the erase segments, the feature set register being implemented in a latch, the control circuit of the memory device receiving the erase-suspend enable setting from the memory controller via the host interface of the memory device and programming the erase-suspend enable setting in the feature set register, and wherein the sending of the erase segment duration value to the memory device is in order to program the trim set register of the memory device, the control circuit of the memory device receiving the erase segment duration value from the memory controller via the host interface of the memory device and programming the erase segment duration value in the trim set register, the trim set register being implemented in static random access memory, the static random access memory being less flexible for writing than the latch due to an static random access memory cell having less transistors to provide its bit storage capabilities relative to the latch.