A high temperature capacitive pressure sensor (10B; 10C) comprising: a first sapphire wafer (12B; 12C) having a first exterior wafer surface (26B; 26C) and a first interior wafer surface (28B;28C); a first recess (32B; 32C) extending into the first sapphire wafer (12B; 12C) at the first interior wafer surface (28B;28C); a second sapphire wafer (18B; 18C) having a second exterior wafer surface (40B; 40C) and a second interior wafer surface (42B; 42C), wherein the second sapphire wafer (18B; 18C) is bonded to the first sapphire wafer (12B; 12C) at the first interior wafer surface (28B;28C) and the second interior wafer surface (42B; 42C) to form a capacitor chamber (24B; 24C); a first hole (30B; 30C) defined by and extending through the first sapphire wafer (12B; 12C); a second hole (44B; 44C) defined by and extending through the first sapphire wafer (12B; 12C); a first electrically conductive via (14B; 14C) that fills the first hole (30B; 30C), the first via (14B; 14C) including a first interior via surface (36B; 36C); a second electrically conductive via (20B; 20C) that fills the second hole (44B; 44C), the second via (20B; 20C) including a second interior via surface (48B; 48C); a first electrode (16B; 16C) deposited on the first interior wafer surface (28B; 28C) within the first recess (32B; 32C) and contacting the first interior via surface (36B; 36C); and a second electrode (22B; 22C) deposited on the second interior wafer surface (42B; 42C) and electrically connected to the second via (20B; 20C) through an electrically conductive connector (52B; 52C) that extends between the second electrode (22B; 22C) and the second interior via surface (48B; 48C); the capacitive pressure sensor, wherein the first electrically conductive via (14B; 14C) solidly fills the first hole (30B; 30C); wherein the second electrically conductive via (20B; 20C) solidly fills the second hole (44B; 44C); wherein the first interior wafer surface, the first interior via surface (36B; 36C) and the second interior via surface (48B; 48C) are polished so that the first interior via surface and the second interior via surface are flush with the first interior wafer surface (28B; 28C), and the first via (14B; 14C) and the second via are hermetically sealed to the first sapphire wafer (12B; 12C) and the second sapphire wafer (18B; 18C) is hermetically bonded to the first sapphire wafer (12B; 12C); and wherein the first electrode (16B; 16C) covers the first interior via surface (36B; 36C). a first sapphire wafer (12B; 12C) having a first exterior wafer surface (26B; 26C) and a first interior wafer surface (28B;28C); a first recess (32B; 32C) extending into the first sapphire wafer (12B; 12C) at the first interior wafer surface (28B;28C); a second sapphire wafer (18B; 18C) having a second exterior wafer surface (40B; 40C) and a second interior wafer surface (42B; 42C), wherein the second sapphire wafer (18B; 18C) is bonded to the first sapphire wafer (12B; 12C) at the first interior wafer surface (28B;28C) and the second interior wafer surface (42B; 42C) to form a capacitor chamber (24B; 24C); a first hole (30B; 30C) defined by and extending through the first sapphire wafer (12B; 12C); a second hole (44B; 44C) defined by and extending through the first sapphire wafer (12B; 12C); a first electrically conductive via (14B; 14C) that fills the first hole (30B; 30C), the first via (14B; 14C) including a first interior via surface (36B; 36C); a second electrically conductive via (20B; 20C) that fills the second hole (44B; 44C), the second via (20B; 20C) including a second interior via surface (48B; 48C); a first electrode (16B; 16C) deposited on the first interior wafer surface (28B; 28C) within the first recess (32B; 32C) and contacting the first interior via surface (36B; 36C); and a second electrode (22B; 22C) deposited on the second interior wafer surface (42B; 42C) and electrically connected to the second via (20B; 20C) through an electrically conductive connector (52B; 52C) that extends between the second electrode (22B; 22C) and the second interior via surface (48B; 48C); the capacitive pressure sensor, wherein the first electrically conductive via (14B; 14C) solidly fills the first hole (30B; 30C); wherein the second electrically conductive via (20B; 20C) solidly fills the second hole (44B; 44C); wherein the first interior wafer surface, the first interior via surface (36B; 36C) and the second interior via surface (48B; 48C) are polished so that the first interior via surface and the second interior via surface are flush with the first interior wafer surface (28B; 28C), and the first via (14B; 14C) and the second via are hermetically sealed to the first sapphire wafer (12B; 12C) and the second sapphire wafer (18B; 18C) is hermetically bonded to the first sapphire wafer (12B; 12C); and wherein the first electrode (16B; 16C) covers the first interior via surface (36B; 36C).