A Two-Transistor AND flash memory array comprising: a plurality of AND memory sectors (104-1; 104-2) of Two-Transistor memory cells (MC(1,1,1), MC(1,1,2), MC(1,1,3)), wherein each sector (104-1; 104-2) comprises at least one row of sector selection transistors (SST(1,1), SST(1,2), SST(1,3); SST(2,1), SST(2,2), SST(2,3)), a sector selector transistor voltage line (SSTL1; SSTL2) corresponding to the row of sector selection transistors, a plurality of memory rows (ROW1, ROW2, ROW3), a plurality of word lines (WL1, WL2, WL3), and a plurality of local source lines; a plurality of memory columns (COLUMN1, COLUMN2, COLUMN3); a plurality of bit lines (BL1, BL2, BL3); and a plurality of global source lines (GSL1, GSL2, GSL3); wherein each one of the memory cells (MC(1,1,1)) is located in one of the memory rows and in one of the memory columns (COLUMN1), each one of the word lines is associated with one memory row, wherein each one of the local source lines is associated with one memory column, wherein each one of the bit lines is associated with one memory column (COLUMN1), wherein each one of the global source lines is associated with one memory column (COLUMN1), and wherein the global source lines (GSL1, GSL2, GSL3) and the bit lines (BL1, BL2, BL3) run in the same direction and perpendicular to the word lines (WL1, WL2, WL3), and each particular one (SST(1,1)) of the sector selection transistors in a particular row of sector selection transistors (SST(1,1), SST(1,2), SST(1,3)) is connected to the corresponding sector selector transistor voltage line (SSTL1), to a particular one of the memory cells (MC(1,2,1)) in a particular one of the memory columns (COLUMN1), and to the global source line associated with the particular one of the memory columns (COLUMN1) comprising the memory cell (MC(1,2,1)); characterized in that each of the memory sectors (104-1, 104-2) includes a first row of sector selection transistors at top of the memory sector and a second row of sector selection transistors at bottom of the memory sector, and in that each one of the local source lines is connected to one sector selection transistor in the first row of sector selection transistors and to one sector selection transistor in the second row of sector selection transistors. a plurality of AND memory sectors (104-1; 104-2) of Two-Transistor memory cells (MC(1,1,1), MC(1,1,2), MC(1,1,3)), wherein each sector (104-1; 104-2) comprises at least one row of sector selection transistors (SST(1,1), SST(1,2), SST(1,3); SST(2,1), SST(2,2), SST(2,3)), a sector selector transistor voltage line (SSTL1; SSTL2) corresponding to the row of sector selection transistors, a plurality of memory rows (ROW1, ROW2, ROW3), a plurality of word lines (WL1, WL2, WL3), and a plurality of local source lines; a plurality of memory columns (COLUMN1, COLUMN2, COLUMN3); a plurality of bit lines (BL1, BL2, BL3); and a plurality of global source lines (GSL1, GSL2, GSL3); wherein each one of the memory cells (MC(1,1,1)) is located in one of the memory rows and in one of the memory columns (COLUMN1), each one of the word lines is associated with one memory row, wherein each one of the local source lines is associated with one memory column, wherein each one of the bit lines is associated with one memory column (COLUMN1), wherein each one of the global source lines is associated with one memory column (COLUMN1), and wherein the global source lines (GSL1, GSL2, GSL3) and the bit lines (BL1, BL2, BL3) run in the same direction and perpendicular to the word lines (WL1, WL2, WL3), and each particular one (SST(1,1)) of the sector selection transistors in a particular row of sector selection transistors (SST(1,1), SST(1,2), SST(1,3)) is connected to the corresponding sector selector transistor voltage line (SSTL1), to a particular one of the memory cells (MC(1,2,1)) in a particular one of the memory columns (COLUMN1), and to the global source line associated with the particular one of the memory columns (COLUMN1) comprising the memory cell (MC(1,2,1)); characterized in that each of the memory sectors (104-1, 104-2) includes a first row of sector selection transistors at top of the memory sector and a second row of sector selection transistors at bottom of the memory sector, and in that each one of the local source lines is connected to one sector selection transistor in the first row of sector selection transistors and to one sector selection transistor in the second row of sector selection transistors.