A semiconductor device comprising: a silicon substrate having an n-type region; a gate insulating film formed on the n-type region, said gate insulating film being made of one of a nitrogen-containing silicon oxide layer, a lamination of a silicon oxide layer and a silicon nitride layer, a lamination of a silicon oxide layer and a hafnium oxide layer, a lamination of a silicon oxide layer and a silicon oxynitride layer, and a lamination of a silicon oxynitride layer of a lower N concentration and a silicon oxynitride layer of higher N concentration; a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon; p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode; side wall spacers formed on side walls of said gate electrode, using silicon oxide; a first interlayer insulating film having a planarized first surface and covering said gate electrode and said side wall spacers; a second interlayer insulating film formed on said first interlayer insulating film and having a second surface; a wiring trench formed in said second interlayer insulating film above the gate electrode; a connection hole formed through said first interlayer insulating film, reaching a bottom of said wiring trench and a top portion of said gate electrode; a conductive plug formed in said connection hole; an underlying barrier metal layer covering inside wall of said wiring trench; a copper wiring pattern formed on said underlying barrier metal layer and filling said wiring trench; and a silicon carbide layer formed on said second interlayer insulating film covering said copper wiring pattern. a silicon substrate having an n-type region; a gate insulating film formed on the n-type region, said gate insulating film being made of one of a nitrogen-containing silicon oxide layer, a lamination of a silicon oxide layer and a silicon nitride layer, a lamination of a silicon oxide layer and a hafnium oxide layer, a lamination of a silicon oxide layer and a silicon oxynitride layer, and a lamination of a silicon oxynitride layer of a lower N concentration and a silicon oxynitride layer of higher N concentration; a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon; p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode; side wall spacers formed on side walls of said gate electrode, using silicon oxide; a first interlayer insulating film having a planarized first surface and covering said gate electrode and said side wall spacers; a second interlayer insulating film formed on said first interlayer insulating film and having a second surface; a wiring trench formed in said second interlayer insulating film above the gate electrode; a connection hole formed through said first interlayer insulating film, reaching a bottom of said wiring trench and a top portion of said gate electrode; a conductive plug formed in said connection hole; an underlying barrier metal layer covering inside wall of said wiring trench; a copper wiring pattern formed on said underlying barrier metal layer and filling said wiring trench; and a silicon carbide layer formed on said second interlayer insulating film covering said copper wiring pattern.