A differential amplifier circuit, comprising: a differential pre-amplifying stage which is arranged to allow an input signal with a first common mode voltage range, and to generate an output which has a narrower common mode voltage variation; a first differential amplifying stage which is arranged to allow an input signal with a second common mode voltage range smaller than the first common mode voltage range, wherein the output of the pre-amplifying stage has a smaller common mode voltage variation than the second common mode voltage range; wherein the pre-amplifying stage comprises two branches between a high voltage rail and a sink current source, each branch comprising, in series, a top current source (IS10,IS11) connected to the high voltage rail (Vddio) and an NMOS input transistor (MN1,MN2) connected to the sink current source wherein a gate of an NMOS input transistor of one of the branches of the differential pre-amplifying stage is controlled by a positive input terminal and a gate of an NMOS input transistor of the other of the branches of the differential pre-amplifying stage is controlled by a negative input terminal; and wherein the first differential amplifying stage comprises two branches between a supply current source and ground, the supply current source comprising a PMOS transistor and being connected to the high voltage rail (vddio) each branch of the first differential amplifying stage comprising, in series, an input PMOS transistor (MP6,MP7) connected to the supply current source and a resistor connected to ground; wherein the differential pre-amplifying stage is arranged to generate a differential current output to two output branches and comprises a differential current to differential voltage conversion circuit (MP4,MP5,R10,R11) at each of the output branches wherein the differential current to differential voltage conversion circuit comprises PMOS transistors (MP4, MP5) configured to act as switches to steer current to respective termination resistors (R10, R11) based on the voltage difference at the positive and negative input terminals (INP and INN) configured to receive the input signal; wherein each of the two top current sources (IS10, IS11) comprises a PMOS transistor which is configured to receive a bias signal equals Vb1, wherein Vb 1 = vddio − Vtp IS 10 − VOD IS 10 in which vddio is the voltage value of the high voltage rail, Vtp is the absolute value of threshold voltage of the PMOS transistor and VOD is the overdrive voltage of the PMOS transistor and wherein the PMOS transistors of the two top current sources (IS10, IS11) have the same threshold voltage and overdrive voltage. a differential pre-amplifying stage which is arranged to allow an input signal with a first common mode voltage range, and to generate an output which has a narrower common mode voltage variation; a first differential amplifying stage which is arranged to allow an input signal with a second common mode voltage range smaller than the first common mode voltage range, wherein the output of the pre-amplifying stage has a smaller common mode voltage variation than the second common mode voltage range; wherein the pre-amplifying stage comprises two branches between a high voltage rail and a sink current source, each branch comprising, in series, a top current source (IS10,IS11) connected to the high voltage rail (Vddio) and an NMOS input transistor (MN1,MN2) connected to the sink current source wherein a gate of an NMOS input transistor of one of the branches of the differential pre-amplifying stage is controlled by a positive input terminal and a gate of an NMOS input transistor of the other of the branches of the differential pre-amplifying stage is controlled by a negative input terminal; and wherein the first differential amplifying stage comprises two branches between a supply current source and ground, the supply current source comprising a PMOS transistor and being connected to the high voltage rail (vddio) each branch of the first differential amplifying stage comprising, in series, an input PMOS transistor (MP6,MP7) connected to the supply current source and a resistor connected to ground; wherein the differential pre-amplifying stage is arranged to generate a differential current output to two output branches and comprises a differential current to differential voltage conversion circuit (MP4,MP5,R10,R11) at each of the output branches wherein the differential current to differential voltage conversion circuit comprises PMOS transistors (MP4, MP5) configured to act as switches to steer current to respective termination resistors (R10, R11) based on the voltage difference at the positive and negative input terminals (INP and INN) configured to receive the input signal; wherein each of the two top current sources (IS10, IS11) comprises a PMOS transistor which is configured to receive a bias signal equals Vb1, wherein Vb 1 = vddio − Vtp IS 10 − VOD IS 10 in which vddio is the voltage value of the high voltage rail, Vtp is the absolute value of threshold voltage of the PMOS transistor and VOD is the overdrive voltage of the PMOS transistor and wherein the PMOS transistors of the two top current sources (IS10, IS11) have the same threshold voltage and overdrive voltage.