An array of non-volatile memory cells comprising: a semiconductor substrate of a first conductivity type having a top surface; a plurality of spaced apart first regions of a second conductivity type in said substrate along the top surface, said first regions being spaced apart along a row direction; a plurality of spaced apart second regions of the second conductivity type, in said substrate along the top surface, each second region extending in said row direction and each second region spaced apart from an associated first region in a column direction, perpendicular to the row direction; a plurality of spaced apart channel regions, with each channel region between a second region and its associated first region in the column direction; each of said channel regions having a first portion and a second portion; a plurality of spaced apart word line gates extending in the row direction, with each word line gate positioned over and insulated from the first portion of a plurality of channel regions, with each first portion of channel region immediately adjacent to the first region; a plurality of spaced apart floating gates, each floating gate positioned over the second portion of a corresponding channel region of the plurality of channel regions and insulated therefrom; a plurality of spaced apart coupling gates extending in the row direction, with each coupling gate extending over and insulated from a plurality of floating gates; a plurality of spaced apart metal strapping lines extending in the row direction, with each metal strapping line associated with and overlying a coupling gate, with a first metal strapping line in a first row electrically connected to the associated underlying coupling gate in a plurality of periodically spaced first locations, and a second metal strapping line in a row immediately adjacent to the first row electrically connected to the associated underlying coupling gate in a plurality of periodically spaced second locations, wherein the periodicity of said first locations is the same as the periodicity of said second locations; and a plurality of spaced apart erase gates, extending in said row direction, with each erase gate positioned over a second region and insulated therefrom, and adjacent to and insulated from a floating gate and coupling gate, characterized in that said second metal strapping line lacks any electrical connections to the associated underlying coupling gate in any column that contains the first locations, and said first metal strapping line lacks any electrical connections to the associated underlying coupling gate in any column that contains said second locations. a semiconductor substrate of a first conductivity type having a top surface; a plurality of spaced apart first regions of a second conductivity type in said substrate along the top surface, said first regions being spaced apart along a row direction; a plurality of spaced apart second regions of the second conductivity type, in said substrate along the top surface, each second region extending in said row direction and each second region spaced apart from an associated first region in a column direction, perpendicular to the row direction; a plurality of spaced apart channel regions, with each channel region between a second region and its associated first region in the column direction; each of said channel regions having a first portion and a second portion; a plurality of spaced apart word line gates extending in the row direction, with each word line gate positioned over and insulated from the first portion of a plurality of channel regions, with each first portion of channel region immediately adjacent to the first region; a plurality of spaced apart floating gates, each floating gate positioned over the second portion of a corresponding channel region of the plurality of channel regions and insulated therefrom; a plurality of spaced apart coupling gates extending in the row direction, with each coupling gate extending over and insulated from a plurality of floating gates; a plurality of spaced apart metal strapping lines extending in the row direction, with each metal strapping line associated with and overlying a coupling gate, with a first metal strapping line in a first row electrically connected to the associated underlying coupling gate in a plurality of periodically spaced first locations, and a second metal strapping line in a row immediately adjacent to the first row electrically connected to the associated underlying coupling gate in a plurality of periodically spaced second locations, wherein the periodicity of said first locations is the same as the periodicity of said second locations; and a plurality of spaced apart erase gates, extending in said row direction, with each erase gate positioned over a second region and insulated therefrom, and adjacent to and insulated from a floating gate and coupling gate, characterized in that said second metal strapping line lacks any electrical connections to the associated underlying coupling gate in any column that contains the first locations, and said first metal strapping line lacks any electrical connections to the associated underlying coupling gate in any column that contains said second locations.