A method of fabricating a normally-off III-nitride field-effect transistor comprising: forming a plurality of semiconductor layers; forming a source electrode contacting at least one of the semiconductor layers; forming a drain electrode contacting at least one of the semiconductor layers; forming a first dielectric layer covering a portion of a top surface of the semiconductor layers between the source electrode and the drain electrode; forming a first trench extending through the first dielectric layer and having a bottom located within one of the semiconductor layers; forming a second dielectric layer lining the first trench and covering a portion of the first dielectric layer; forming a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer; forming a second trench extending through the third dielectric layer and having a bottom located in the first trench on the surface of or within the second dielectric layer, and extending over a portion of the second dielectric layer on the first dielectric layer; and forming a gate electrode filling the second trench; wherein forming said second dielectric layer comprises: growing a single crystalline AlN layer at the bottom of the first trench at a temperature greater than 900°C and less than 1100°C; growing a polycrystalline AlN layer at a temperature greater than 300°C and less than 600°C on the single crystalline AlN layer; and forming an insulating layer comprising SiN on the polycrystalline AlN layer. forming a plurality of semiconductor layers; forming a source electrode contacting at least one of the semiconductor layers; forming a drain electrode contacting at least one of the semiconductor layers; forming a first dielectric layer covering a portion of a top surface of the semiconductor layers between the source electrode and the drain electrode; forming a first trench extending through the first dielectric layer and having a bottom located within one of the semiconductor layers; forming a second dielectric layer lining the first trench and covering a portion of the first dielectric layer; forming a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer; forming a second trench extending through the third dielectric layer and having a bottom located in the first trench on the surface of or within the second dielectric layer, and extending over a portion of the second dielectric layer on the first dielectric layer; and forming a gate electrode filling the second trench; wherein forming said second dielectric layer comprises: growing a single crystalline AlN layer at the bottom of the first trench at a temperature greater than 900°C and less than 1100°C; growing a polycrystalline AlN layer at a temperature greater than 300°C and less than 600°C on the single crystalline AlN layer; and forming an insulating layer comprising SiN on the polycrystalline AlN layer. growing a single crystalline AlN layer at the bottom of the first trench at a temperature greater than 900°C and less than 1100°C; growing a polycrystalline AlN layer at a temperature greater than 300°C and less than 600°C on the single crystalline AlN layer; and forming an insulating layer comprising SiN on the polycrystalline AlN layer.