An adaptive pre-emphasis gain tuning hardware control circuit for adaptively controlling pre-emphasis gain in a low voltage differential signaling, LVDS, driver circuit, the adaptive pre-emphasis gain tuning hardware control circuit comprising: a clock transmit pad connected over a first transmission channel in a clock loopback configuration to a clock receiver pad; a data transmit pad connected over a second transmission channel in a data loopback configuration to a data receiver pad; a pre-emphasis controller connected to control transmission of a clock signal from the clock transmit pad and configured to control transmission of a data pulse signal comprising a plurality of single data pulses from the data transmit pad using one of a plurality of adjustable pre-emphasis gain settings for the data transmit pad; wherein the pre-emphasis controller is configured to control transmission of the data pulse signal for each of the plurality of adjustable pre-emphasis gain settings; and a jitter measurement hardware circuit connected to the clock receive pad and data receiver pad and configured to: detect for each of the plurality of adjustable pre-emphasis gain settings a jitter pulsewidth measure of a signal transition skew between a received clock signal pulse and a received single data pulse, wherein the jitter measurement hardware circuit is configured to compare the received clock signal pulse and the received single data pulse when generating the jitter pulsewidth measure; and compare the jitter pulsewidth measure to a variable delay measure that is incremented until a final incremented delay measure exceeds the jitter pulsewidth measure, wherein the adaptive pre-emphasis gain tuning hardware control circuit is configured to periodically tune the pre-emphasis gain by selecting an optimum pre-emphasis gain setting from the plurality of adjustable pre-emphasis settings which has a minimal final incremented variable delay measure. a clock transmit pad connected over a first transmission channel in a clock loopback configuration to a clock receiver pad; a data transmit pad connected over a second transmission channel in a data loopback configuration to a data receiver pad; a pre-emphasis controller connected to control transmission of a clock signal from the clock transmit pad and configured to control transmission of a data pulse signal comprising a plurality of single data pulses from the data transmit pad using one of a plurality of adjustable pre-emphasis gain settings for the data transmit pad; wherein the pre-emphasis controller is configured to control transmission of the data pulse signal for each of the plurality of adjustable pre-emphasis gain settings; and a jitter measurement hardware circuit connected to the clock receive pad and data receiver pad and configured to: detect for each of the plurality of adjustable pre-emphasis gain settings a jitter pulsewidth measure of a signal transition skew between a received clock signal pulse and a received single data pulse, wherein the jitter measurement hardware circuit is configured to compare the received clock signal pulse and the received single data pulse when generating the jitter pulsewidth measure; and compare the jitter pulsewidth measure to a variable delay measure that is incremented until a final incremented delay measure exceeds the jitter pulsewidth measure, wherein the adaptive pre-emphasis gain tuning hardware control circuit is configured to periodically tune the pre-emphasis gain by selecting an optimum pre-emphasis gain setting from the plurality of adjustable pre-emphasis settings which has a minimal final incremented variable delay measure. detect for each of the plurality of adjustable pre-emphasis gain settings a jitter pulsewidth measure of a signal transition skew between a received clock signal pulse and a received single data pulse, wherein the jitter measurement hardware circuit is configured to compare the received clock signal pulse and the received single data pulse when generating the jitter pulsewidth measure; and compare the jitter pulsewidth measure to a variable delay measure that is incremented until a final incremented delay measure exceeds the jitter pulsewidth measure, wherein the adaptive pre-emphasis gain tuning hardware control circuit is configured to periodically tune the pre-emphasis gain by selecting an optimum pre-emphasis gain setting from the plurality of adjustable pre-emphasis settings which has a minimal final incremented variable delay measure.