A driver circuit comprising: a first plurality of series-connected inverters (413 - 419), each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input terminal of a subsequent inverter; a second plurality of series-connected inverters (446 - 452), each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input terminal of a subsequent inverter, a first transistor having a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output terminal of a last inverter (222, 419) in the first plurality of series-connected inverters (413 - 419), and a second current electrode coupled to an output terminal; a second transistor having a first current electrode coupled to the output terminal, a control electrode coupled to the output terminal of a last inverter (232, 452) in the second plurality of series-connected inverters (446 - 452), and a second current electrode coupled to ground; and, wherein each inverter of the first plurality of series-connected inverters (413 - 419) has a first power supply terminal (VDDO) coupled to receive the first power supply voltage (VDDO), and a second power supply terminal (VSSR) coupled to receive a second power supply voltage (VSSR) regulated to a predetermined voltage level above ground, a first discharge circuit (470 - 474) coupled between the second power supply terminal (VSSR) of the inverter of the first plurality of series-connected inverters (413 - 419) and ground, the first discharge circuit (470 - 474) for discharging the second power supply terminal (VSSR) of the first plurality of series-connected inverters (413 - 419) in response to a transition of an input signal of the driver circuit from a first logic level to a second logic level, characterized in that the driver circuit further comprises: the second plurality of series-connected inverters having a same number of inverters as the first plurality of series-connected inverters; and a plurality of capacitors, each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters (413-419; 446-452). a first plurality of series-connected inverters (413 - 419), each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input terminal of a subsequent inverter; a second plurality of series-connected inverters (446 - 452), each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input terminal of a subsequent inverter, a first transistor having a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output terminal of a last inverter (222, 419) in the first plurality of series-connected inverters (413 - 419), and a second current electrode coupled to an output terminal; a second transistor having a first current electrode coupled to the output terminal, a control electrode coupled to the output terminal of a last inverter (232, 452) in the second plurality of series-connected inverters (446 - 452), and a second current electrode coupled to ground; and, wherein each inverter of the first plurality of series-connected inverters (413 - 419) has a first power supply terminal (VDDO) coupled to receive the first power supply voltage (VDDO), and a second power supply terminal (VSSR) coupled to receive a second power supply voltage (VSSR) regulated to a predetermined voltage level above ground, a first discharge circuit (470 - 474) coupled between the second power supply terminal (VSSR) of the inverter of the first plurality of series-connected inverters (413 - 419) and ground, the first discharge circuit (470 - 474) for discharging the second power supply terminal (VSSR) of the first plurality of series-connected inverters (413 - 419) in response to a transition of an input signal of the driver circuit from a first logic level to a second logic level, characterized in that the driver circuit further comprises: the second plurality of series-connected inverters having a same number of inverters as the first plurality of series-connected inverters; and a plurality of capacitors, each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters (413-419; 446-452).