An electronic memory cell (100, 400) including: - a substrate on which a channel active zone made of a semiconductor material and including a channel disposed between a drain extension region and a source extension region is formed; - a first gate structure, called a selection gate, on top of a first part (103 1) of said channel; - a side spacer disposed against at least one side flank of said selection transistor gate, said side spacer comprising a second gate structure, called a memory transistor gate, on top of a second part (103 2) of said channel, said memory transistor gate including: ∘ a stack of layers of which one of said layers is adapted to store electric charges, said stack including a first stack zone (110 1) in contact with said second part of said channel (103 2) and a second stack zone (110 2) in contact with said side flank of said selection transistor gate; ∘ a gate conductive zone of the memory transistor including ▪ a first side face in contact with said second stack zone (110 2) such that the latter separates said side flank from the selection transistor gate and said first side face; ▪ a substantially planar lower face parallel to the plane of the substrate, said lower face being in contact with said first stack zone (110 1) such that said first stack zone (110 1) separates said second part (103 2) from said channel and said lower face; ▪ a substantially planar upper face parallel to the plane of the substrate; ▪ a second side face, said first and second side faces (113, 116) connecting said lower face to said upper face, said electronic memory cell being characterized in that said second side face is tilted by an angle α strictly between 0 and 90° with respect to the plane of the substrate such that the length of said upper face is strictly higher than the length (L MG) of said lower face, said lengths (L, L MG) being measured as the distance between said first and second side faces along the length of said channel. - a substrate on which a channel active zone made of a semiconductor material and including a channel disposed between a drain extension region and a source extension region is formed; - a first gate structure, called a selection gate, on top of a first part (103 1) of said channel; - a side spacer disposed against at least one side flank of said selection transistor gate, said side spacer comprising a second gate structure, called a memory transistor gate, on top of a second part (103 2) of said channel, said memory transistor gate including: ∘ a stack of layers of which one of said layers is adapted to store electric charges, said stack including a first stack zone (110 1) in contact with said second part of said channel (103 2) and a second stack zone (110 2) in contact with said side flank of said selection transistor gate; ∘ a gate conductive zone of the memory transistor including ▪ a first side face in contact with said second stack zone (110 2) such that the latter separates said side flank from the selection transistor gate and said first side face; ▪ a substantially planar lower face parallel to the plane of the substrate, said lower face being in contact with said first stack zone (110 1) such that said first stack zone (110 1) separates said second part (103 2) from said channel and said lower face; ▪ a substantially planar upper face parallel to the plane of the substrate; ▪ a second side face, said first and second side faces (113, 116) connecting said lower face to said upper face, said electronic memory cell being characterized in that said second side face is tilted by an angle α strictly between 0 and 90° with respect to the plane of the substrate such that the length of said upper face is strictly higher than the length (L MG) of said lower face, said lengths (L, L MG) being measured as the distance between said first and second side faces along the length of said channel. ∘ a stack of layers of which one of said layers is adapted to store electric charges, said stack including a first stack zone (110 1) in contact with said second part of said channel (103 2) and a second stack zone (110 2) in contact with said side flank of said selection transistor gate; ∘ a gate conductive zone of the memory transistor including ▪ a first side face in contact with said second stack zone (110 2) such that the latter separates said side flank from the selection transistor gate and said first side face; ▪ a substantially planar lower face parallel to the plane of the substrate, said lower face being in contact with said first stack zone (110 1) such that said first stack zone (110 1) separates said second part (103 2) from said channel and said lower face; ▪ a substantially planar upper face parallel to the plane of the substrate; ▪ a second side face, said first and second side faces (113, 116) connecting said lower face to said upper face, ▪ a first side face in contact with said second stack zone (110 2) such that the latter separates said side flank from the selection transistor gate and said first side face; ▪ a substantially planar lower face parallel to the plane of the substrate, said lower face being in contact with said first stack zone (110 1) such that said first stack zone (110 1) separates said second part (103 2) from said channel and said lower face; ▪ a substantially planar upper face parallel to the plane of the substrate; ▪ a second side face, said first and second side faces (113, 116) connecting said lower face to said upper face,