A nonvolatile memory device (100, 210) of a vertical structure comprising means to determine a channel error, a ground selection transistor error, and to distinguish in between them, the nonvolatile memory device comprising: a memory cell array including cell strings, wherein each of the cell strings includes a ground selection transistor, memory cells, and a string selection transistor (SSTa, SSTb) stacked in a direction perpendicular to a substrate; a row decoder connected to the ground selection transistor of each of the cell strings through a ground selection line, connected to the memory cells of each of the cell strings through word lines, and connected to the string selection transistor (SSTa, SSTb) of each of the cell strings through a string selection line; and a page buffer connected to the cell strings through bit lines, wherein, the page buffer is configured to apply (S110, S210) a first bias voltage to the bit lines in a first period of a check operation, wherein, the row decoder is configured to, in the first period of the check operation: apply (S120, S210) a turn-off voltage (VOFF) to the ground selection line, apply a turn-on voltage to the string selection line, and apply a first check voltage to the word lines, wherein, the page buffer is configured to, in a second period of the check operation, sense (S150, S220) whether there has been any changes in voltages of the bit lines, wherein the page buffer is configured to apply (S110, S230) a second bias voltage to the bit lines in a third period of the check operation, wherein the row decoder is configured to, in the third period of the check operation: apply (S120, S230) the turn-off voltage (VOFF) to the ground selection line, apply the turn-on voltage to the string selection line, and apply a second check voltage to the word lines, the second check voltage being different from the first check voltage, wherein the page buffer is configured to, in a fourth period of the check operation, sense (S150, S240) whether there has been any changes in the voltages of the bit lines, wherein, the nonvolatile memory device (100, 210) is configured to output a status fail signal in response to determining that a number of bit lines that were determined to have changed voltage in the second period is not equal to a number of bit lines that were determined to have changed voltage in the fourth period, wherein the nonvolatile memory (100, 210) is configured to omit an output of the status fail signal in response to determining that a number of bit lines that were determined to have changed voltage in the second period is equal to a number of bit lines that were determined to have changed voltage in the fourth period. a memory cell array including cell strings, wherein each of the cell strings includes a ground selection transistor, memory cells, and a string selection transistor (SSTa, SSTb) stacked in a direction perpendicular to a substrate; a row decoder connected to the ground selection transistor of each of the cell strings through a ground selection line, connected to the memory cells of each of the cell strings through word lines, and connected to the string selection transistor (SSTa, SSTb) of each of the cell strings through a string selection line; and a page buffer connected to the cell strings through bit lines, wherein, the page buffer is configured to apply (S110, S210) a first bias voltage to the bit lines in a first period of a check operation, wherein, the row decoder is configured to, in the first period of the check operation: apply (S120, S210) a turn-off voltage (VOFF) to the ground selection line, apply a turn-on voltage to the string selection line, and apply a first check voltage to the word lines, wherein, the page buffer is configured to, in a second period of the check operation, sense (S150, S220) whether there has been any changes in voltages of the bit lines, wherein the page buffer is configured to apply (S110, S230) a second bias voltage to the bit lines in a third period of the check operation, wherein the row decoder is configured to, in the third period of the check operation: apply (S120, S230) the turn-off voltage (VOFF) to the ground selection line, apply the turn-on voltage to the string selection line, and apply a second check voltage to the word lines, the second check voltage being different from the first check voltage, wherein the page buffer is configured to, in a fourth period of the check operation, sense (S150, S240) whether there has been any changes in the voltages of the bit lines, wherein, the nonvolatile memory device (100, 210) is configured to output a status fail signal in response to determining that a number of bit lines that were determined to have changed voltage in the second period is not equal to a number of bit lines that were determined to have changed voltage in the fourth period, wherein the nonvolatile memory (100, 210) is configured to omit an output of the status fail signal in response to determining that a number of bit lines that were determined to have changed voltage in the second period is equal to a number of bit lines that were determined to have changed voltage in the fourth period.