A circuit, wherein: - i) the circuit comprises a set of LED driver devices (#1, #2,...) comprising a finite state machine configured to generate LED drive PWM-modulated signal patterns (CHx) as well as an oscillator generating a clock signal (osc_out) for the finite state machine; - ii) the LED driver devices in the set of LED driver devices (#1, #2,..) are coupled (SDA, SCL) via a bus (I2C bus), the LED driver devices in the set of LED driver devices (#1, #2,...) having bus pins (I2C) coupled to said bus (SDA, SCL) as well a set of slave address pins comprising at least one first and one second slave address pin, - iii) the LED driver devices in the set of LED driver devices (#1, #2,..) comprise: - a first signal path (14, 20) activatable (en_A1, chain_in_en) between the first slave address pin and the finite state machine; - a second signal path (12, 16) activatable (en_A0, chain_out_en) between the finite state machine and the second slave address pin, - iv) the circuit comprises a controller having a set of nodes (A, B, C) coupled to the slave address pins (A0, A1) in the LED driver devices in the set of LED driver devices (#1, #2,...), wherein the controller is configured to: - provide via the slave address pins (A0, A1) of the LED driver devices in the set of LED driver devices (#1, #2,...) at least one inter-device clock signal propagation path from the second slave address pin in one LED driver device (#1, #2,...) in the set of LED driver devices (#1, #2,...) to the first slave address pin in another (#2, #3...) LED driver device in the set of LED driver devices (#1, #2,...), and - activate (en_A0, chain_out_en, en_A1, chain_in_en) the second signal path (12, 16) between the finite state machine and the second slave address pin in said one LED driver device (#1, #2,...) and the first signal path (14, 20) between the first slave address pin and the finite state machine in said another (#2, #3...) LED driver device in the set of LED driver devices (#1, #2,...), wherein a clock signal (osc_out; EXT CLK) coupled to the finite state machine in said one (#1, #2...) LED driver device in the set of LED driver devices (#1, #2,...) is coupled to the finite state machine in said another (#2, #3...) LED driver device in the set of LED driver devices (#1, #2,...) via said activated (en_A0, chain_out_en, en_A1, chain_in_en) second signal path (12, 16) and first signal path (14, 20) and said at least one inter-device clock signal propagation path. - i) the circuit comprises a set of LED driver devices (#1, #2,...) comprising a finite state machine configured to generate LED drive PWM-modulated signal patterns (CHx) as well as an oscillator generating a clock signal (osc_out) for the finite state machine; - ii) the LED driver devices in the set of LED driver devices (#1, #2,..) are coupled (SDA, SCL) via a bus (I2C bus), the LED driver devices in the set of LED driver devices (#1, #2,...) having bus pins (I2C) coupled to said bus (SDA, SCL) as well a set of slave address pins comprising at least one first and one second slave address pin, - iii) the LED driver devices in the set of LED driver devices (#1, #2,..) comprise: - a first signal path (14, 20) activatable (en_A1, chain_in_en) between the first slave address pin and the finite state machine; - a second signal path (12, 16) activatable (en_A0, chain_out_en) between the finite state machine and the second slave address pin, - a first signal path (14, 20) activatable (en_A1, chain_in_en) between the first slave address pin and the finite state machine; - a second signal path (12, 16) activatable (en_A0, chain_out_en) between the finite state machine and the second slave address pin, - iv) the circuit comprises a controller having a set of nodes (A, B, C) coupled to the slave address pins (A0, A1) in the LED driver devices in the set of LED driver devices (#1, #2,...), wherein the controller is configured to: - provide via the slave address pins (A0, A1) of the LED driver devices in the set of LED driver devices (#1, #2,...) at least one inter-device clock signal propagation path from the second slave address pin in one LED driver device (#1, #2,...) in the set of LED driver devices (#1, #2,...) to the first slave address pin in another (#2, #3...) LED driver device in the set of LED driver devices (#1, #2,...), and - provide via the slave address pins (A0, A1) of the LED driver devices in the set of LED driver devices (#1, #2,...) at least one inter-device clock signal propagation path from the second slave address pin in one LED driver device (#1, #2,...) in the set of LED driver devices (#1, #2,...) to the first slave address pin in another (#2, #3...) LED driver device in the set of LED driver devices (#1, #2,...), and - activate (en_A0, chain_out_en, en_A1, chain_in_en) the second signal path (12, 16) between the finite state machine and the second slave address pin in said one LED driver device (#1, #2,...) and the first signal path (14, 20) between the first slave address pin and the finite state machine in said another (#2, #3...) LED driver device in the set of LED driver devices (#1, #2,...), wherein a clock signal (osc_out; EXT CLK) coupled to the finite state machine in said one (#1, #2...) LED driver device in the set of LED driver devices (#1, #2,...) is coupled to the finite state machine in said another (#2, #3...) LED driver device in the set of LED driver devices (#1, #2,...) via said activated (en_A0, chain_out_en, en_A1, chain_in_en) second signal path (12, 16) and first signal path (14, 20) and said at least one inter-device clock signal propagation path.