A data storage circuit of NOR type comprising: - a three-dimensional memory structure, produced on a first semiconductor substrate, and comprising a plurality of memory planes (P i) of rank i ranging from 1 to N, with N a natural number greater than 1, each plane forming a two-dimensional array of non-volatile, resistive and programmable memory cells, each memory cell having a selection node, a first input/output node and a second input/output node; said array comprising M rows (L j) of rank j ranging from 1 to M and K columns (C k) of rank k ranging from 1 to K, with M and K two non-zero natural numbers; for each memory plane (Pi): the first input/output nodes of the memory cells belonging to one and the same column (C k) are interconnected; and the second input/output nodes of the memory cells belonging to one and the same column (C k) are interconnected; the three-dimensional memory structure having an upper surface comprising a plurality of connectors (BL k, SL k, BL kb) distributed over said surface; each connector (BL k, SL k, BL kb) being connected to at least one among the first or second input/output nodes (SL, BL) of a given column (C k); - a control circuit configured to apply control voltages (VBL, VSL, VWL) to the nodes of each memory cell; and produced on a second semiconductor substrate; the control circuit is superposed on said upper surface; - an interconnection structure comprising: • a plurality of bonding pads (31, 32, 33) placed between the control circuit and said upper surface; each bonding pad (31, 32, 33) connects the control circuit to a dedicated connector (BL k, SL k, BL kb); each bonding pad (31, 32, 33) being connected to an elementary group of memory cells belonging to separate memory planes (P i), said plurality of bonding pads forming a periodic repetition of a unit pattern in a plane parallel to the upper surface. - a three-dimensional memory structure, produced on a first semiconductor substrate, and comprising a plurality of memory planes (P i) of rank i ranging from 1 to N, with N a natural number greater than 1, each plane forming a two-dimensional array of non-volatile, resistive and programmable memory cells, each memory cell having a selection node, a first input/output node and a second input/output node; said array comprising M rows (L j) of rank j ranging from 1 to M and K columns (C k) of rank k ranging from 1 to K, with M and K two non-zero natural numbers; for each memory plane (Pi): the first input/output nodes of the memory cells belonging to one and the same column (C k) are interconnected; and the second input/output nodes of the memory cells belonging to one and the same column (C k) are interconnected; the three-dimensional memory structure having an upper surface comprising a plurality of connectors (BL k, SL k, BL kb) distributed over said surface; each connector (BL k, SL k, BL kb) being connected to at least one among the first or second input/output nodes (SL, BL) of a given column (C k); - a control circuit configured to apply control voltages (VBL, VSL, VWL) to the nodes of each memory cell; and produced on a second semiconductor substrate; the control circuit is superposed on said upper surface; - an interconnection structure comprising: • a plurality of bonding pads (31, 32, 33) placed between the control circuit and said upper surface; • a plurality of bonding pads (31, 32, 33) placed between the control circuit and said upper surface;