A delay-locked loop comprising: an adjustable frequency source for generating a clock signal having an adjustable frequency; an adjustment and tap selection controller coupled to the adjustable frequency source for: (i) determining a first frequency (F clkvariable) as a function of a desired output frequency (F out), the number of taps, and a range (F min -F max) of possible frequency values for the first frequency, the desired output frequency being the desired frequency of a first output signal; (ii) causing a second period, corresponding to the desired output frequency (F out), to be an integer multiple of a delay, the delay being a first period corresponding to the first frequency (F clkvariable) divided by the number of taps; and (iii) causing said adjustable frequency source to adjust the frequency of said clock signal to said first frequency (F clkvariable); a delay line configured to receive the clock signal for generating a plurality of phase-shifted clock signals, each phase-shifted clock signal having said first frequency (F clkvariable) and being shifted in phase with respect to the clock signal and with respect to the other phase-shifted clock signals; and a first selection circuit for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating said first output signal having said desired output frequency (F out). an adjustable frequency source for generating a clock signal having an adjustable frequency; an adjustment and tap selection controller coupled to the adjustable frequency source for: (i) determining a first frequency (F clkvariable) as a function of a desired output frequency (F out), the number of taps, and a range (F min -F max) of possible frequency values for the first frequency, the desired output frequency being the desired frequency of a first output signal; (ii) causing a second period, corresponding to the desired output frequency (F out), to be an integer multiple of a delay, the delay being a first period corresponding to the first frequency (F clkvariable) divided by the number of taps; and (iii) causing said adjustable frequency source to adjust the frequency of said clock signal to said first frequency (F clkvariable); (i) determining a first frequency (F clkvariable) as a function of a desired output frequency (F out), the number of taps, and a range (F min -F max) of possible frequency values for the first frequency, the desired output frequency being the desired frequency of a first output signal; (ii) causing a second period, corresponding to the desired output frequency (F out), to be an integer multiple of a delay, the delay being a first period corresponding to the first frequency (F clkvariable) divided by the number of taps; and (iii) causing said adjustable frequency source to adjust the frequency of said clock signal to said first frequency (F clkvariable); a delay line configured to receive the clock signal for generating a plurality of phase-shifted clock signals, each phase-shifted clock signal having said first frequency (F clkvariable) and being shifted in phase with respect to the clock signal and with respect to the other phase-shifted clock signals; and a first selection circuit for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating said first output signal having said desired output frequency (F out).