A cache memory apparatus comprising: a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a received set address with upper bits of a received tag address, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons; and an update controller configured to, in response to the cache miss being determined, determine, as an update candidate, a piece among pieces of cache data included in the set and corresponding to the pieces of the tag data based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data and characterized in that the update controller is configured to, in response to the cache memory apparatus receiving a plurality of data requests each having a same set address: determine the piece of the cache data as the update candidate for each of pieces of data of the data requests based on the result of the comparison of the upper bits of the tag address that is received for each of the pieces of the data and the upper bits of each of the pieces of the tag data; and update, with the new data, the piece among the pieces of the cache data that is most frequently determined as the update candidate. a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a received set address with upper bits of a received tag address, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons; and compare upper bits of each of pieces of tag data included in a set indicated by a received set address with upper bits of a received tag address, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons; and an update controller configured to, in response to the cache miss being determined, determine, as an update candidate, a piece among pieces of cache data included in the set and corresponding to the pieces of the tag data based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data determine, as an update candidate, a piece among pieces of cache data included in the set and corresponding to the pieces of the tag data based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data and characterized in that the update controller is configured to, in response to the cache memory apparatus receiving a plurality of data requests each having a same set address: determine the piece of the cache data as the update candidate for each of pieces of data of the data requests based on the result of the comparison of the upper bits of the tag address that is received for each of the pieces of the data and the upper bits of each of the pieces of the tag data; and update, with the new data, the piece among the pieces of the cache data that is most frequently determined as the update candidate. determine the piece of the cache data as the update candidate for each of pieces of data of the data requests based on the result of the comparison of the upper bits of the tag address that is received for each of the pieces of the data and the upper bits of each of the pieces of the tag data; and update, with the new data, the piece among the pieces of the cache data that is most frequently determined as the update candidate.