An organic light emitting diode (OLED) display device comprising a pixel circuit comprising: a first transistor, wherein a source electrode of the first transistor is connected to a high-potential power supply voltage (Vdd) and a drain electrode of the first transistor is connected to a second node; a switching transistor, (Tsw) wherein a source electrode of the switching transistor (Tsw) is connected to a data line and a drain electrode of the switching transistor (Tsw) is connected to the second node; a second transistor, wherein a source electrode of the second transistor is connected to a drain electrode of a driver transistor (Tdr) and a drain electrode of the second transistor is connected to a first node; the driver transistor (Tdr) being connected to the second node and the first node, wherein a source electrode of the driver transistor (Tdr) is connected to the second node and a gate electrode of the driver transistor (Tdr) is connected to the first node; an emission control transistor (Tem), wherein a source electrode of the emission control transistor (Tem) is connected to the drain electrode of the driver transistor (Tdr), and a drain electrode of the emission control transistor (Tem) is connected to one electrode of an OLED; a third transistor connected to the one electrode of the OLED and configured to reduce the voltage on the one electrode of the OLED, wherein a gate electrode of the third transistor is connected to a gate electrode of the second transistor; and a first capacitor connected between the high-potential power supply voltage (Vdd) terminal and the first node, wherein an initialization voltage (V L, V SS) applied on a drain electrode of the third transistor is applied to the first node through the third transistor, the emission control transistor (Tem) and the second transistor while the second transistor, the third transistor and the emission control transistor (Tem) are turned on at the same time. a first transistor, wherein a source electrode of the first transistor is connected to a high-potential power supply voltage (Vdd) and a drain electrode of the first transistor is connected to a second node; a switching transistor, (Tsw) wherein a source electrode of the switching transistor (Tsw) is connected to a data line and a drain electrode of the switching transistor (Tsw) is connected to the second node; a second transistor, wherein a source electrode of the second transistor is connected to a drain electrode of a driver transistor (Tdr) and a drain electrode of the second transistor is connected to a first node; the driver transistor (Tdr) being connected to the second node and the first node, wherein a source electrode of the driver transistor (Tdr) is connected to the second node and a gate electrode of the driver transistor (Tdr) is connected to the first node; an emission control transistor (Tem), wherein a source electrode of the emission control transistor (Tem) is connected to the drain electrode of the driver transistor (Tdr), and a drain electrode of the emission control transistor (Tem) is connected to one electrode of an OLED; a third transistor connected to the one electrode of the OLED and configured to reduce the voltage on the one electrode of the OLED, wherein a gate electrode of the third transistor is connected to a gate electrode of the second transistor; and a first capacitor connected between the high-potential power supply voltage (Vdd) terminal and the first node, wherein an initialization voltage (V L, V SS) applied on a drain electrode of the third transistor is applied to the first node through the third transistor, the emission control transistor (Tem) and the second transistor while the second transistor, the third transistor and the emission control transistor (Tem) are turned on at the same time.