An apparatus comprising: a controller for a memory device that includes logic, at least a portion of which comprises hardware, the logic to: program a first set of values to a first set of registers at the memory device to establish one or more internal resistance termination, RTT, settings for on die termination. ODT, at the memory device, wherein the first set of values include a first resistance value for RTT_PARK, a second resistance value for RTT_WR, a third resistance value for RTT_NOM_WR or a fourth resistance value for RTT_NOM_RD; program a second set of values to a second set of registers at the memory device to establish one or more settings for timing of ODT latency, tODTL, to turn on or turn off respective RTT settings from among one or more RTT settings for the memory device, wherein the second set of values include a first timing value for tODTLon_WR to activate resistance for RTT_WR responsive to a write command targeted to the memory device, a second timing value for tODTLoff WR to deactivate resistance for RTT WR responsive to a write command targeted to the memory device, a third timing value for tODTLon _WR_NT to activate resistance for RTT_NOM_WR responsive to a write command not targeted to the memory device, a fourth timing value for tODTLoff_WR_NT to deactivate resistance for RTT_NOM_WR responsive to a write command not targeted to the memory device, a fifth timing value for tODTLon_RD to activate resistance for RTT_RD responsive to a read command targeted to the memory device, a sixth timing value for tODTLoff RD to deactivate resistance for RTT_RD responsive to a read command targeted to the memory device, a seventh timing value for tODTLon_RD_NT to activate resistance for RTT_NOM_RD responsive to a read command not targeted to the memory device, an eighth timing value for tODTLoff WR_NT to deactivate resistance for RTT_NOM_WR responsive to a write command not targeted to the memory device; change the first set of values to the first set of registers or change the second set of values to the second set of registers to adjust a signal integrity for the memory device during a read or write operation. program a first set of values to a first set of registers at the memory device to establish one or more internal resistance termination, RTT, settings for on die termination. ODT, at the memory device, wherein the first set of values include a first resistance value for RTT_PARK, a second resistance value for RTT_WR, a third resistance value for RTT_NOM_WR or a fourth resistance value for RTT_NOM_RD; program a second set of values to a second set of registers at the memory device to establish one or more settings for timing of ODT latency, tODTL, to turn on or turn off respective RTT settings from among one or more RTT settings for the memory device, wherein the second set of values include a first timing value for tODTLon_WR to activate resistance for RTT_WR responsive to a write command targeted to the memory device, a second timing value for tODTLoff WR to deactivate resistance for RTT WR responsive to a write command targeted to the memory device, a third timing value for tODTLon _WR_NT to activate resistance for RTT_NOM_WR responsive to a write command not targeted to the memory device, a fourth timing value for tODTLoff_WR_NT to deactivate resistance for RTT_NOM_WR responsive to a write command not targeted to the memory device, a fifth timing value for tODTLon_RD to activate resistance for RTT_RD responsive to a read command targeted to the memory device, a sixth timing value for tODTLoff RD to deactivate resistance for RTT_RD responsive to a read command targeted to the memory device, a seventh timing value for tODTLon_RD_NT to activate resistance for RTT_NOM_RD responsive to a read command not targeted to the memory device, an eighth timing value for tODTLoff WR_NT to deactivate resistance for RTT_NOM_WR responsive to a write command not targeted to the memory device; change the first set of values to the first set of registers or change the second set of values to the second set of registers to adjust a signal integrity for the memory device during a read or write operation.