An integrated circuit device (100; 300) having a system for handling software-trace messages, the integrated circuit device (100; 300) comprising: a processor (128; 328, 358, 388); a software-trace message handling system (110; 310); characterized in that the integrated circuit device further comprises: a software-trace message sink peripheral (122; 322, 352, 382); and a hardware interconnect system (132; 332, 362, 392), wherein: the hardware interconnect system (132; 332, 362, 392) connects the processor (128; 328, 358, 388) with the software-trace message handling system (110; 310) and with the software-trace message sink peripheral (122; 322, 352, 382); the hardware interconnect system (132; 332, 362, 392) is capable of directing software-trace messages from the processor to the software-trace message handling system (110; 310); the hardware interconnect system (132; 332, 362, 392) is capable of directing software-trace messages from the processor (128; 328, 358, 388) to the software-trace message sink peripheral (122; 322, 352, 382); and the software-trace message sink peripheral (122; 322, 352, 382) is configured to present an interconnect delay to the processor (128; 328, 358, 388), or comprises a configurable delay unit for configuring an interconnect delay presented by the software-trace message sink peripheral (122; 322, 352, 382) to the processor (128; 328, 358, 388), when receiving a software-trace message from the processor (128; 328, 358, 388), that is equal to or within one bus clock cycle of an interconnect delay that the software-trace message handling system (110; 310) would have presented to the processor (128; 328, 358, 388) if the software-trace message handling system (110; 310) were to have received the software-trace message. a processor (128; 328, 358, 388); a software-trace message handling system (110; 310); characterized in that the integrated circuit device further comprises: a software-trace message sink peripheral (122; 322, 352, 382); and a hardware interconnect system (132; 332, 362, 392), a software-trace message sink peripheral (122; 322, 352, 382); and a hardware interconnect system (132; 332, 362, 392), wherein: the hardware interconnect system (132; 332, 362, 392) connects the processor (128; 328, 358, 388) with the software-trace message handling system (110; 310) and with the software-trace message sink peripheral (122; 322, 352, 382); the hardware interconnect system (132; 332, 362, 392) is capable of directing software-trace messages from the processor to the software-trace message handling system (110; 310); the hardware interconnect system (132; 332, 362, 392) is capable of directing software-trace messages from the processor (128; 328, 358, 388) to the software-trace message sink peripheral (122; 322, 352, 382); and the software-trace message sink peripheral (122; 322, 352, 382) is configured to present an interconnect delay to the processor (128; 328, 358, 388), or comprises a configurable delay unit for configuring an interconnect delay presented by the software-trace message sink peripheral (122; 322, 352, 382) to the processor (128; 328, 358, 388), when receiving a software-trace message from the processor (128; 328, 358, 388), that is equal to or within one bus clock cycle of an interconnect delay that the software-trace message handling system (110; 310) would have presented to the processor (128; 328, 358, 388) if the software-trace message handling system (110; 310) were to have received the software-trace message. the hardware interconnect system (132; 332, 362, 392) connects the processor (128; 328, 358, 388) with the software-trace message handling system (110; 310) and with the software-trace message sink peripheral (122; 322, 352, 382); the hardware interconnect system (132; 332, 362, 392) is capable of directing software-trace messages from the processor to the software-trace message handling system (110; 310); the hardware interconnect system (132; 332, 362, 392) is capable of directing software-trace messages from the processor (128; 328, 358, 388) to the software-trace message sink peripheral (122; 322, 352, 382); and the software-trace message sink peripheral (122; 322, 352, 382) is configured to present an interconnect delay to the processor (128; 328, 358, 388), or comprises a configurable delay unit for configuring an interconnect delay presented by the software-trace message sink peripheral (122; 322, 352, 382) to the processor (128; 328, 358, 388), when receiving a software-trace message from the processor (128; 328, 358, 388), that is equal to or within one bus clock cycle of an interconnect delay that the software-trace message handling system (110; 310) would have presented to the processor (128; 328, 358, 388) if the software-trace message handling system (110; 310) were to have received the software-trace message.