A microprocessor, comprising: a processing unit; a translation lookaside buffer comprising a plurality of TLB slots; a memory cache comprising a plurality of cache slots; and control logic that is characterized to configure the microprocessor to at least: identify a TLB entry within one of the plurality of TLB slots, the TLB entry comprising a mapping between a virtual address of a virtual memory page within a virtual address space and a physical address of a physical memory page within a hardware memory; initiate logging of the TLB entry into an execution trace, including initiating logging of at least (i) the virtual address, and (ii) an identifier for the TLB entry, the identifier uniquely identifying the TLB entry from among a plurality of live entries in the TLB; subsequent to identifying the TLB entry, identify a cache entry within one of the plurality of cache slots, the cache entry comprising (i) a physical memory address corresponding to a cache line, and (ii) data of the cache line, the physical memory address comprising a physical memory page identification portion and an offset portion; and initiate logging of the cache entry into the execution trace, including, matching the physical memory page identification portion of the physical memory address with the TLB entry, and based on matching the physical memory page identification portion of the physical memory address with the TLB entry, initiating logging of at least: (i) the identifier for the TLB entry and (ii) the offset portion. a processing unit; a translation lookaside buffer comprising a plurality of TLB slots; a memory cache comprising a plurality of cache slots; and control logic that is characterized to configure the microprocessor to at least: identify a TLB entry within one of the plurality of TLB slots, the TLB entry comprising a mapping between a virtual address of a virtual memory page within a virtual address space and a physical address of a physical memory page within a hardware memory; initiate logging of the TLB entry into an execution trace, including initiating logging of at least (i) the virtual address, and (ii) an identifier for the TLB entry, the identifier uniquely identifying the TLB entry from among a plurality of live entries in the TLB; subsequent to identifying the TLB entry, identify a cache entry within one of the plurality of cache slots, the cache entry comprising (i) a physical memory address corresponding to a cache line, and (ii) data of the cache line, the physical memory address comprising a physical memory page identification portion and an offset portion; and initiate logging of the cache entry into the execution trace, including, matching the physical memory page identification portion of the physical memory address with the TLB entry, and based on matching the physical memory page identification portion of the physical memory address with the TLB entry, initiating logging of at least: (i) the identifier for the TLB entry and (ii) the offset portion. identify a TLB entry within one of the plurality of TLB slots, the TLB entry comprising a mapping between a virtual address of a virtual memory page within a virtual address space and a physical address of a physical memory page within a hardware memory; initiate logging of the TLB entry into an execution trace, including initiating logging of at least (i) the virtual address, and (ii) an identifier for the TLB entry, the identifier uniquely identifying the TLB entry from among a plurality of live entries in the TLB; subsequent to identifying the TLB entry, identify a cache entry within one of the plurality of cache slots, the cache entry comprising (i) a physical memory address corresponding to a cache line, and (ii) data of the cache line, the physical memory address comprising a physical memory page identification portion and an offset portion; and initiate logging of the cache entry into the execution trace, including, matching the physical memory page identification portion of the physical memory address with the TLB entry, and based on matching the physical memory page identification portion of the physical memory address with the TLB entry, initiating logging of at least: (i) the identifier for the TLB entry and (ii) the offset portion. matching the physical memory page identification portion of the physical memory address with the TLB entry, and based on matching the physical memory page identification portion of the physical memory address with the TLB entry, initiating logging of at least: (i) the identifier for the TLB entry and (ii) the offset portion.