Voltage regulation circuit suitable for an RFID circuit, the voltage regulation circuit comprising: - an input connectable to a rectifier circuit, - an output connectable to a processor of the RFID circuit, - at least one switch arranged between the input and the output and connected to the input and to the output wherein the switch is capable to electrically connect the output to the input and to disconnect the output from the input, the switch including a switch PMOS transistor, wherein a drain of the switch PMOS transistor is connected to the output and wherein a source of the switch PMOS transistor is connected to the input, in that the voltage regulation circuit further comprises a diode connected to the source and to the drain of the switch PMOS transistor, characterized in that the active switch further includes a current mirror having at least a first mirror PMOS transistor and a second mirror PMOS transistor for which gates (41g, 42g) of the first mirror PMOS transistor and the second mirror PMOS transistor are connected to each other, in that a source of the first mirror PMOS transistor is connected to the output, in that a source of the second mirror PMOS transistor is connected to the input, in that a drain of the second mirror PMOS transistor is connected to the gates (41g, 42g) of the first and the second mirror PMOS transistors (41, 42), in that a drain of the first mirror PMOS transistor is connected to the gate of the switch PMOS transistor to be controlled, and in that there are further a first biasing NMOS transistor and a second biasing NMOS transistor, a drain of the first biasing NMOS transistor being connected to the drain of the first mirror PMOS transistor, a source of the first biasing NMOS transistor being connected to ground via a resistor and via a first additional long channel NMOS transistor, the drain of the second biasing NMOS transistor being connected to the drain of the second mirror PMOS transistor, a source of the second biasing NMOS transistor being connected to ground via the resistor and via a second additional long channel NMOS transistor, wherein by means of said long channel NMOS transistors (45, 46) and the resistor in series with the two parallel connected long channel NMOS transistors (45, 46), a comparator is implemented by the interaction and connection of the first and second mirror PMOS transistors (41, 42), and the first and second biasing NMOS transistors (43, 44), and a gate of the first biasing NMOS transistor is connected to the input and a gate of the second biasing NMOS transistor is connected to the output. - an input connectable to a rectifier circuit, - an output connectable to a processor of the RFID circuit, - at least one switch arranged between the input and the output and connected to the input and to the output the switch including a switch PMOS transistor, wherein a drain of the switch PMOS transistor is connected to the output and wherein a source of the switch PMOS transistor is connected to the input, in that the voltage regulation circuit further comprises a diode connected to the source and to the drain of the switch PMOS transistor, characterized in that the active switch further includes a current mirror having at least a first mirror PMOS transistor and a second mirror PMOS transistor for which gates (41g, 42g) of the first mirror PMOS transistor and the second mirror PMOS transistor are connected to each other, in that a source of the first mirror PMOS transistor is connected to the output, in that a source of the second mirror PMOS transistor is connected to the input, in that a drain of the second mirror PMOS transistor is connected to the gates (41g, 42g) of the first and the second mirror PMOS transistors (41, 42), in that a drain of the first mirror PMOS transistor is connected to the gate of the switch PMOS transistor to be controlled, and in that there are further a first biasing NMOS transistor and a second biasing NMOS transistor, a drain of the first biasing NMOS transistor being connected to the drain of the first mirror PMOS transistor, a source of the first biasing NMOS transistor being connected to ground via a resistor and via a first additional long channel NMOS transistor, the drain of the second biasing NMOS transistor being connected to the drain of the second mirror PMOS transistor, a source of the second biasing NMOS transistor being connected to ground via the resistor and via a second additional long channel NMOS transistor,