An electronic apparatus (DD, DD1, DD2, DD3, DD4, DD-1, DD-2, DD-T) comprising: a display panel (DP, DP-1, DP-C, DP-C1) comprising: a base substrate comprising an active area and a peripheral area adjacent to the active area; a plurality of pixels on the active area; a plurality of pads arranged in a first direction on the peripheral area; a plurality of signal lines (SL, SL-T) connecting the pixels to the pads; and a vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) on the peripheral area and spaced apart from the pads and the signal lines (SL, SL-T); a circuit board connected to the display panel (DP, DP-1, DP-C, DP-C1) and comprising: a base film; and leads on the base film, the leads overlapping with the pads in a plan view; and a conductive adhesive member extending in the first direction and located between the display panel (DP, DP-1, DP-C, DP-C1) and the circuit board to connect the pads to the leads, and wherein the conductive adhesive member overlaps with the vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) when viewed in a second direction intersecting the first direction, characterized in that a bottom end of the vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) is aligned with top ends of the pads along an imaginary line extending in the first direction when viewed in a plan view; and wherein the vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) comprises a plurality of patterns (LP, LP1, LP2-H, LP3-H) spaced apart from each other in the second direction at a uniform interval, and wherein one or more of the patterns (LP, LP1, LP2-H, LP3-H) are exposed from the conductive adhesive member. a display panel (DP, DP-1, DP-C, DP-C1) comprising: a base substrate comprising an active area and a peripheral area adjacent to the active area; a plurality of pixels on the active area; a plurality of pads arranged in a first direction on the peripheral area; a plurality of signal lines (SL, SL-T) connecting the pixels to the pads; and a vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) on the peripheral area and spaced apart from the pads and the signal lines (SL, SL-T); a base substrate comprising an active area and a peripheral area adjacent to the active area; a plurality of pixels on the active area; a plurality of pads arranged in a first direction on the peripheral area; a plurality of signal lines (SL, SL-T) connecting the pixels to the pads; and a vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) on the peripheral area and spaced apart from the pads and the signal lines (SL, SL-T); a circuit board connected to the display panel (DP, DP-1, DP-C, DP-C1) and comprising: a base film; and leads on the base film, the leads overlapping with the pads in a plan view; and a conductive adhesive member extending in the first direction and located between the display panel (DP, DP-1, DP-C, DP-C1) and the circuit board to connect the pads to the leads, and wherein the conductive adhesive member overlaps with the vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) when viewed in a second direction intersecting the first direction, characterized in that a bottom end of the vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) is aligned with top ends of the pads along an imaginary line extending in the first direction when viewed in a plan view; and wherein the vernier mark (VM, VM-1, VM-2, VM-3, VM1, VM2, VM-T, VM-T1) comprises a plurality of patterns (LP, LP1, LP2-H, LP3-H) spaced apart from each other in the second direction at a uniform interval, and wherein one or more of the patterns (LP, LP1, LP2-H, LP3-H) are exposed from the conductive adhesive member.