A frequency synthesizer system with cycle slip prevention including: a voltage controlled oscillator; a VCO divider; a VCO divider controller configured to define a predetermined divisor for said VCO divider; a phase frequency detector responsive to a reference signal and said VCO divider output signal configured to determine a phase error between said reference and VCO divider output, the PFD comprising: a main reference flip flop and a main VCO flip flop; a saturation circuit configured to indicate whether a phase error of a full cycle slip has occurred and the direction of the cycle slip, the saturation circuit including a saturation reference flip flop being set in response to a second reference pulse occurring while said main reference flip flop is set to provide an up saturation signal identifying an up cycle slip and a saturation VCO flip flop being set in response to a second VCO pulse occurring while said main VCO flip flop is set to provide a down saturation signal indicating a down cycle slip; a reset circuit (16a, 18a) for resetting said main reference flip flop and main VCO flip flop; and a reset saturation resolver circuit configured to identify a cycle slip saturation which occurs during a reset period when the reset circuit resets said main reference flip flop and said main VCO flip flop; and a state machine, responsive to the direction of the cycle slip configured to reset said saturation reference flip flop and said saturation VCO flip flop and drive said VCO divider controller to modify said predetermined divisor to alter the phase of the divided signal at said PFD in the direction to reduce the phase error to less than one reference cycle. a voltage controlled oscillator; a VCO divider; a VCO divider controller configured to define a predetermined divisor for said VCO divider; a phase frequency detector responsive to a reference signal and said VCO divider output signal configured to determine a phase error between said reference and VCO divider output, the PFD comprising: a main reference flip flop and a main VCO flip flop; a saturation circuit configured to indicate whether a phase error of a full cycle slip has occurred and the direction of the cycle slip, the saturation circuit including a saturation reference flip flop being set in response to a second reference pulse occurring while said main reference flip flop is set to provide an up saturation signal identifying an up cycle slip and a saturation VCO flip flop being set in response to a second VCO pulse occurring while said main VCO flip flop is set to provide a down saturation signal indicating a down cycle slip; a reset circuit (16a, 18a) for resetting said main reference flip flop and main VCO flip flop; and a reset saturation resolver circuit configured to identify a cycle slip saturation which occurs during a reset period when the reset circuit resets said main reference flip flop and said main VCO flip flop; and a main reference flip flop and a main VCO flip flop; a saturation circuit configured to indicate whether a phase error of a full cycle slip has occurred and the direction of the cycle slip, the saturation circuit including a saturation reference flip flop being set in response to a second reference pulse occurring while said main reference flip flop is set to provide an up saturation signal identifying an up cycle slip and a saturation VCO flip flop being set in response to a second VCO pulse occurring while said main VCO flip flop is set to provide a down saturation signal indicating a down cycle slip; a reset circuit (16a, 18a) for resetting said main reference flip flop and main VCO flip flop; and a reset saturation resolver circuit configured to identify a cycle slip saturation which occurs during a reset period when the reset circuit resets said main reference flip flop and said main VCO flip flop; and a state machine, responsive to the direction of the cycle slip configured to reset said saturation reference flip flop and said saturation VCO flip flop and drive said VCO divider controller to modify said predetermined divisor to alter the phase of the divided signal at said PFD in the direction to reduce the phase error to less than one reference cycle.