A semiconductor device comprising: a main-MOSFET comprising a main-MOSFET source region, the device comprising: a plurality of parallel main trenches, wherein said main trenches comprise a first electrode coupled to a gate of said main-MOSFET; and a plurality of main mesas between said main trenches, wherein said main mesas comprise the source region and a main body of said main-MOSFET; and a current sensing FET, sense-FET,, configured to produce a signal corresponding to a drain source current of said main-MOSFET, wherein a gate and a drain of said sense-FET are coupled to a gate and a drain of said main-MOSFET, respectively, wherein sections of a subset of said plurality of main trenches are used as trenches to form said sense-FET, said sense-FET comprising: a plurality of first isolation trenches (221, 222, 223, 224) formed in a first horizontal dimension and configured to isolate a sense-FET source region from said main-MOSFET source region, and a plurality of second isolation trenches (210B, 210C,210A, 440) formed in a second horizontal dimension perpendicular to the first horizonal dimension, the plurality of second isolation trenches located between said sense-FET source region and said main-MOSFET source region and configured to isolate said sense-FET source region from said main-FET source region; wherein each of said plurality of main trenches, each of said plurality of first isolation trenches and each of said plurality of second isolation trenches comprises multiple alternating layers of conductors (340, 350) and dielectrics in a vertical dimension; a buffer region separating said sense-FET source region and said main-FET source region, wherein said buffer region is formed as square annulus around the sense-FET and between two sets of two first isolation trenches (221, 222, 223, 224), located on two opposite sides of the sense-FET in the first horizontal dimension perpendicular to the main trenches, and between two sets of at least two second isolation trenches (210B, 210C, 210A, 440), located on two opposite sides of the sense-FET in the second horizontal dimension, the buffer region configured to electrically isolate said main-MOSFET from said sense-FET. a main-MOSFET comprising a main-MOSFET source region, the device comprising: a plurality of parallel main trenches, wherein said main trenches comprise a first electrode coupled to a gate of said main-MOSFET; and a plurality of main mesas between said main trenches, wherein said main mesas comprise the source region and a main body of said main-MOSFET; and a plurality of parallel main trenches, wherein said main trenches comprise a first electrode coupled to a gate of said main-MOSFET; and a plurality of main mesas between said main trenches, wherein said main mesas comprise the source region and a main body of said main-MOSFET; and a current sensing FET, sense-FET,, configured to produce a signal corresponding to a drain source current of said main-MOSFET, wherein a gate and a drain of said sense-FET are coupled to a gate and a drain of said main-MOSFET, respectively, wherein sections of a subset of said plurality of main trenches are used as trenches to form said sense-FET, said sense-FET comprising: a plurality of first isolation trenches (221, 222, 223, 224) formed in a first horizontal dimension and configured to isolate a sense-FET source region from said main-MOSFET source region, and a plurality of second isolation trenches (210B, 210C,210A, 440) formed in a second horizontal dimension perpendicular to the first horizonal dimension, the plurality of second isolation trenches located between said sense-FET source region and said main-MOSFET source region and configured to isolate said sense-FET source region from said main-FET source region; a plurality of first isolation trenches (221, 222, 223, 224) formed in a first horizontal dimension and configured to isolate a sense-FET source region from said main-MOSFET source region, and a plurality of second isolation trenches (210B, 210C,210A, 440) formed in a second horizontal dimension perpendicular to the first horizonal dimension, the plurality of second isolation trenches located between said sense-FET source region and said main-MOSFET source region and configured to isolate said sense-FET source region from said main-FET source region; wherein each of said plurality of main trenches, each of said plurality of first isolation trenches and each of said plurality of second isolation trenches comprises multiple alternating layers of conductors (340, 350) and dielectrics in a vertical dimension; a buffer region separating said sense-FET source region and said main-FET source region, wherein said buffer region is formed as square annulus around the sense-FET and between two sets of two first isolation trenches (221, 222, 223, 224), located on two opposite sides of the sense-FET in the first horizontal dimension perpendicular to the main trenches, and between two sets of at least two second isolation trenches (210B, 210C, 210A, 440), located on two opposite sides of the sense-FET in the second horizontal dimension, the buffer region configured to electrically isolate said main-MOSFET from said sense-FET.