An oscillator circuit having a programmable output frequency comprising: a circuit output configured to output an output signal; a first delay section, wherein the first delay section: has an input end and an output end, has a negative gain between the input end and the output end, has a buffer and a first RC network comprising a first resistor (R 1) and a first variable capacitor (C 1), a first terminal of the first variable capacitor (C 1) connected to the output end of the first delay section and a second terminal of the first variable capacitor (C 1) connected to ground, wherein the variable capacitor (C 1) of the first RC network comprises a plurality of switched capacitors (C x) to control a variable delay, and is configured to provide the variable delay that is set by a control signal provided to the first delay section, wherein the control signal is configured to selectively set each of the plurality of switched capacitors (C x) to an ON state or an OFF state; and a second delay section electrically connected in series between the first delay section and the circuit output, wherein the second delay section: has an input end and an output end, has a negative gain between the input end and the output end, is configured to provide a fixed delay, and comprises a RC network comprising a fixed value resistive component and a fixed value capacitive component, wherein the fixed value resistive component has a first terminal connected at the input end of the second delay section, and the fixed value capacitive component has a first terminal connected at the output end of the second delay section and the second terminal of fixed value resistive component and the second terminal of fixed value capacitive component are connected with each other to the input of the buffer of the first delay section; wherein the output signal has a frequency that is a function of the variable delay due to the first delay section and the delay due to the second delay section. a circuit output configured to output an output signal; a first delay section, wherein the first delay section: has an input end and an output end, has a negative gain between the input end and the output end, has a buffer and a first RC network comprising a first resistor (R 1) and a first variable capacitor (C 1), a first terminal of the first variable capacitor (C 1) connected to the output end of the first delay section and a second terminal of the first variable capacitor (C 1) connected to ground, wherein the variable capacitor (C 1) of the first RC network comprises a plurality of switched capacitors (C x) to control a variable delay, and is configured to provide the variable delay that is set by a control signal provided to the first delay section, wherein the control signal is configured to selectively set each of the plurality of switched capacitors (C x) to an ON state or an OFF state; and has an input end and an output end, has a negative gain between the input end and the output end, has a buffer and a first RC network comprising a first resistor (R 1) and a first variable capacitor (C 1), a first terminal of the first variable capacitor (C 1) connected to the output end of the first delay section and a second terminal of the first variable capacitor (C 1) connected to ground, wherein the variable capacitor (C 1) of the first RC network comprises a plurality of switched capacitors (C x) to control a variable delay, and is configured to provide the variable delay that is set by a control signal provided to the first delay section, wherein the control signal is configured to selectively set each of the plurality of switched capacitors (C x) to an ON state or an OFF state; and a second delay section electrically connected in series between the first delay section and the circuit output, wherein the second delay section: has an input end and an output end, has a negative gain between the input end and the output end, is configured to provide a fixed delay, and comprises a RC network comprising a fixed value resistive component and a fixed value capacitive component, wherein the fixed value resistive component has a first terminal connected at the input end of the second delay section, and the fixed value capacitive component has a first terminal connected at the output end of the second delay section and the second terminal of fixed value resistive component and the second terminal of fixed value capacitive component are connected with each other to the input of the buffer of the first delay section; has an input end and an output end, has a negative gain between the input end and the output end, is configured to provide a fixed delay, and comprises a RC network comprising a fixed value resistive component and a fixed value capacitive component, wherein the fixed value resistive component has a first terminal connected at the input end of the second delay section, and the fixed value capacitive component has a first terminal connected at the output end of the second delay section and the second terminal of fixed value resistive component and the second terminal of fixed value capacitive component are connected with each other to the input of the buffer of the first delay section; wherein the output signal has a frequency that is a function of the variable delay due to the first delay section and the delay due to the second delay section.