A circuit for outputting a regulated voltage (Vreg), comprising: a source follower configured to provide the regulated voltage (Vreg), wherein the source follower comprises a first transistor and a second transistor connected in series; a current sensing circuit configured to measure a sensing current (I_sense) corresponding to a regulated current available at a node for the regulated voltage (Vreg), wherein the current sensing circuit comprises third, fourth, fifth, and sixth transistors (M7, M8, M9, M10) connected in series; a current source configured to supply a reference current (Iref); a current mode comparator configured to compare the sensing current (I_sense) with the reference current (Iref) and control a bias of the source follower based on the comparison; and a power supply level connected with the source follower, the current sensing circuit, the current source, and the current mode comparator, wherein a drain of the third transistor is connected with the power supply level, wherein a gate of the third transistor is connected with a gate of the first transistor, wherein a source of the third transistor is connected with a drain of the fourth transistor, wherein a gate of the fourth transistor is connected with a gate of the second transistor, wherein a source of the fourth transistor is connected with a drain of the fifth transistor, and wherein a source of the fifth transistor is connected with a drain of the sixth transistor; wherein the current sensing circuit comprises an amplifier having a negative input, a positive input, and an output, wherein the positive input is connected with the node for the regulated voltage (Vreg), wherein the negative input is connected with at least one of the source of the fourth transistor or the drain of the fifth transistor, and wherein the output is connected with a gate of the sixth transistor, such that the sensing current (I_sense) flows through the third, fourth, fifth, and sixth transistors (M7, M8, M9, M10), wherein the current mode comparator comprises a seventh transistor (Ml 1) and an eighth transistor connected in series, wherein a drain of the seventh transistor is connected with the current source and with the gate of the second transistor to form a feedback loop (Vfb) for controlling the bias of the source follower, wherein a gate of the seventh transistor is connected with a gate of the fifth transistor, wherein a source of the seventh transistor is connected with a drain of the eighth transistor, and wherein a gate of the eighth transistor is connected with the gate of the sixth transistor. a source follower configured to provide the regulated voltage (Vreg), wherein the source follower comprises a first transistor and a second transistor connected in series; a current sensing circuit configured to measure a sensing current (I_sense) corresponding to a regulated current available at a node for the regulated voltage (Vreg), wherein the current sensing circuit comprises third, fourth, fifth, and sixth transistors (M7, M8, M9, M10) connected in series; a current source configured to supply a reference current (Iref); a current mode comparator configured to compare the sensing current (I_sense) with the reference current (Iref) and control a bias of the source follower based on the comparison; and a power supply level connected with the source follower, the current sensing circuit, the current source, and the current mode comparator, wherein a drain of the third transistor is connected with the power supply level, wherein a gate of the third transistor is connected with a gate of the first transistor, wherein a source of the third transistor is connected with a drain of the fourth transistor, wherein a gate of the fourth transistor is connected with a gate of the second transistor, wherein a source of the fourth transistor is connected with a drain of the fifth transistor, and wherein a source of the fifth transistor is connected with a drain of the sixth transistor; wherein the current sensing circuit comprises an amplifier having a negative input, a positive input, and an output, wherein the positive input is connected with the node for the regulated voltage (Vreg), wherein the negative input is connected with at least one of the source of the fourth transistor or the drain of the fifth transistor, and wherein the output is connected with a gate of the sixth transistor, such that the sensing current (I_sense) flows through the third, fourth, fifth, and sixth transistors (M7, M8, M9, M10), wherein the current mode comparator comprises a seventh transistor (Ml 1) and an eighth transistor connected in series, wherein a drain of the seventh transistor is connected with the current source and with the gate of the second transistor to form a feedback loop (Vfb) for controlling the bias of the source follower, wherein a gate of the seventh transistor is connected with a gate of the fifth transistor, wherein a source of the seventh transistor is connected with a drain of the eighth transistor, and wherein a gate of the eighth transistor is connected with the gate of the sixth transistor.