A semiconductor device, comprising: a substrate that includes an integrated circuit region; a first interlayer insulation film formed above the substrate; a second interlayer insulation film (111, 112) formed above the first interlayer insulation film; a first metal embedded in a contact hole, a first trench and a second trench that are formed in the first interlayer insulation film; a second metal embedded in a third trench, a fourth trench and a fifth trench that are formed in the second interlayer insulation film (111, 112); a main-wall part that is formed in the first interlayer insulation film and in the second interlayer insulation film (111, 112), the main-wall part including the first metal embedded in the first trench and the second metal embedded in the third trench, the main-wall part surrounding the integrated circuit region in a plan view and including a first bend section of the first metal embedded in the first trench and the second metal embedded in the third trench in a corner region of the semiconductor device in a plan view, and the third trench being located directly above the first trench; and a first sub-wall part (3a, 3c, 3d1, 3e1, 3f2), which is located between the integrated circuit region and the first bend section in a plan view, the first sub-wall part being formed in the first interlayer insulation film and in the second interlayer insulation film (117, 118), the first sub-wall part (3a, 3c, 3d1, 3e1, 3f2) including the first metal embedded in the second trench and the second metal embedded in the fourth trench, and the fourth trench being located directly above the second trench; wherein: the contact hole is formed in the integrated circuit region in a plan view; the second trench is apart from the first trench in the corner region in a plan view; the third trench is wider than the first trench in a plan view; the fourth trench is wider than the second trench in a plan view, and the fourth trench is apart from the third trench in the corner region in a plan view; and the fifth trench is formed in the integrated circuit region in a plan view. a substrate that includes an integrated circuit region; a first interlayer insulation film formed above the substrate; a second interlayer insulation film (111, 112) formed above the first interlayer insulation film; a first metal embedded in a contact hole, a first trench and a second trench that are formed in the first interlayer insulation film; a second metal embedded in a third trench, a fourth trench and a fifth trench that are formed in the second interlayer insulation film (111, 112); a main-wall part that is formed in the first interlayer insulation film and in the second interlayer insulation film (111, 112), the main-wall part including the first metal embedded in the first trench and the second metal embedded in the third trench, the main-wall part surrounding the integrated circuit region in a plan view and including a first bend section of the first metal embedded in the first trench and the second metal embedded in the third trench in a corner region of the semiconductor device in a plan view, and the third trench being located directly above the first trench; and a first sub-wall part (3a, 3c, 3d1, 3e1, 3f2), which is located between the integrated circuit region and the first bend section in a plan view, the first sub-wall part being formed in the first interlayer insulation film and in the second interlayer insulation film (117, 118), the first sub-wall part (3a, 3c, 3d1, 3e1, 3f2) including the first metal embedded in the second trench and the second metal embedded in the fourth trench, and the fourth trench being located directly above the second trench; wherein: the contact hole is formed in the integrated circuit region in a plan view; the second trench is apart from the first trench in the corner region in a plan view; the third trench is wider than the first trench in a plan view; the fourth trench is wider than the second trench in a plan view, and the fourth trench is apart from the third trench in the corner region in a plan view; and the fifth trench is formed in the integrated circuit region in a plan view. the contact hole is formed in the integrated circuit region in a plan view; the second trench is apart from the first trench in the corner region in a plan view; the third trench is wider than the first trench in a plan view; the fourth trench is wider than the second trench in a plan view, and the fourth trench is apart from the third trench in the corner region in a plan view; and the fifth trench is formed in the integrated circuit region in a plan view.