A resistive non-volatile memory circuit, comprising: an array of resistive non-volatile memory cells comprising a plurality of word lines (WL1-WL6), a plurality of bit lines (BL1-BLN), and a plurality of source lines (SL1-SLN), wherein: each non-volatile memory cell is coupled to a corresponding word line, a corresponding bit line (BL1-BLN), and a corresponding source line (SL1-SLN), and each source line (SL1-SLN) corresponds to one bit line (BL1-BLN) and is shared by all memory cells of a memory column coupled to the corresponding one bit line (BL1-BLN); a sense amplifier coupled to a first bit line of the plurality of bit lines (BL1-BLN) and a corresponding first source line of the plurality of source lines (SL1-SLN), wherein the sense amplifier includes: a first capacitor, a first switch configured to couple the first source line to a first terminal of the first capacitor in a first position and configured to decouple the first source line from the first terminal of the first capacitor in a second position, a first amplifier having a non-inverting input coupled to the first terminal of the first capacitor and an inverting input coupled to an output of the first amplifier, a second switch configured to decouple the output of the first amplifier from the first source line in a first position and to couple the output of the first amplifier to the first source line in a second position, a second capacitor; a third switch configured to couple the output of the first amplifier to a first terminal of the second capacitor in a first position and to couple the first bit line to the first terminal of the second capacitor in a second position; a second amplifier having an inverting input coupled to a second terminal of the second capacitor; and a fourth switch configured to couple an output of the second amplifier to the inverting input of the second amplifier in a first position and to decouple the output of the second amplifier from the inverting input of the second amplifier in a second position. an array of resistive non-volatile memory cells comprising a plurality of word lines (WL1-WL6), a plurality of bit lines (BL1-BLN), and a plurality of source lines (SL1-SLN), wherein: each non-volatile memory cell is coupled to a corresponding word line, a corresponding bit line (BL1-BLN), and a corresponding source line (SL1-SLN), and each source line (SL1-SLN) corresponds to one bit line (BL1-BLN) and is shared by all memory cells of a memory column coupled to the corresponding one bit line (BL1-BLN); each non-volatile memory cell is coupled to a corresponding word line, a corresponding bit line (BL1-BLN), and a corresponding source line (SL1-SLN), and each source line (SL1-SLN) corresponds to one bit line (BL1-BLN) and is shared by all memory cells of a memory column coupled to the corresponding one bit line (BL1-BLN); a sense amplifier coupled to a first bit line of the plurality of bit lines (BL1-BLN) and a corresponding first source line of the plurality of source lines (SL1-SLN), wherein the sense amplifier includes: a first capacitor, a first switch configured to couple the first source line to a first terminal of the first capacitor in a first position and configured to decouple the first source line from the first terminal of the first capacitor in a second position, a first amplifier having a non-inverting input coupled to the first terminal of the first capacitor and an inverting input coupled to an output of the first amplifier, a second switch configured to decouple the output of the first amplifier from the first source line in a first position and to couple the output of the first amplifier to the first source line in a second position, a second capacitor; a third switch configured to couple the output of the first amplifier to a first terminal of the second capacitor in a first position and to couple the first bit line to the first terminal of the second capacitor in a second position; a second amplifier having an inverting input coupled to a second terminal of the second capacitor; and a fourth switch configured to couple an output of the second amplifier to the inverting input of the second amplifier in a first position and to decouple the output of the second amplifier from the inverting input of the second amplifier in a second position. a first capacitor, a first switch configured to couple the first source line to a first terminal of the first capacitor in a first position and configured to decouple the first source line from the first terminal of the first capacitor in a second position, a first amplifier having a non-inverting input coupled to the first terminal of the first capacitor and an inverting input coupled to an output of the first amplifier, a second switch configured to decouple the output of the first amplifier from the first source line in a first position and to couple the output of the first amplifier to the first source line in a second position, a second capacitor; a third switch configured to couple the output of the first amplifier to a first terminal of the second capacitor in a first position and to couple the first bit line to the first terminal of the second capacitor in a second position; a second amplifier having an inverting input coupled to a second terminal of the second capacitor; and a fourth switch configured to couple an output of the second amplifier to the inverting input of the second amplifier in a first position and to decouple the output of the second amplifier from the inverting input of the second amplifier in a second position.