An apparatus, comprising: a block of memory cells (BLK0-BLK3; BLK_0-BLK_8), the memory cells (702-716, 722-736, 742-756, 762-776) are arranged in a plurality of NAND strings (700n, 710n, 720n, 730n), each NAND string comprising a source end connected to a substrate, a drain end, a channel (700a, 710a, 720a, 730a) extending between the source end and the drain end, and a drain end select gate transistor (717, 718, 737, 738, 757, 758, 777, 778); a plurality of bit lines (BL0-BL3) connected to the drain ends; a voltage detector connected to a bit line of the plurality of bit lines; and a control circuit (110, 122), the control circuit, to perform an erase operation for the block, is configured to: apply a voltage to the substrate to charge up the channel, the voltage applied to the substrate is increased to, and held at, a first level; hold control gate voltages of the drain end select gate transistors (Vsgd) at a fixed level while the voltage applied to the substrate is increased to, and held at, the first level; establish floating of the control gate voltages of the drain end select gate transistors based on when the voltage detector indicates that a voltage of the bit line exceeds a reference voltage (Vref); increase the voltage applied to the substrate to a second level, higher than the first level, and hold the voltage applied to the substrate at the second level. a block of memory cells (BLK0-BLK3; BLK_0-BLK_8), the memory cells (702-716, 722-736, 742-756, 762-776) are arranged in a plurality of NAND strings (700n, 710n, 720n, 730n), each NAND string comprising a source end connected to a substrate, a drain end, a channel (700a, 710a, 720a, 730a) extending between the source end and the drain end, and a drain end select gate transistor (717, 718, 737, 738, 757, 758, 777, 778); a plurality of bit lines (BL0-BL3) connected to the drain ends; a voltage detector connected to a bit line of the plurality of bit lines; and a control circuit (110, 122), the control circuit, to perform an erase operation for the block, is configured to: apply a voltage to the substrate to charge up the channel, the voltage applied to the substrate is increased to, and held at, a first level; hold control gate voltages of the drain end select gate transistors (Vsgd) at a fixed level while the voltage applied to the substrate is increased to, and held at, the first level; establish floating of the control gate voltages of the drain end select gate transistors based on when the voltage detector indicates that a voltage of the bit line exceeds a reference voltage (Vref); increase the voltage applied to the substrate to a second level, higher than the first level, and hold the voltage applied to the substrate at the second level. apply a voltage to the substrate to charge up the channel, the voltage applied to the substrate is increased to, and held at, a first level; hold control gate voltages of the drain end select gate transistors (Vsgd) at a fixed level while the voltage applied to the substrate is increased to, and held at, the first level; establish floating of the control gate voltages of the drain end select gate transistors based on when the voltage detector indicates that a voltage of the bit line exceeds a reference voltage (Vref); increase the voltage applied to the substrate to a second level, higher than the first level, and hold the voltage applied to the substrate at the second level.