A circuit comprising: a phase rotator core having a first input coupled to receive a first radio frequency signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal; a phase control block coupled to the phase rotator core, the phase control block comprising: a first transistor having a control electrode coupled to receive a first control signal; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled to a first current electrode of the first transistor; a third transistor having a control electrode and a first current electrode coupled to the first current electrodes of the first and second transistors; a first filter having first terminal coupled to the control electrode and the first current electrode of the third transistor; a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal characterized in that the phase control block is comprising: a first switch having a first terminal coupled to the first current electrodes of the first and second transistors (208, 212), a second terminal coupled to the control electrode and the first current electrode of the third transistor, and a control terminal coupled to receive a third control signal; wherein the first switch is configured to be: closed based on a first state of the third control signal in order to define a sample mode; and open based on a second state of the third control signal in order to define a hold mode. a phase rotator core having a first input coupled to receive a first radio frequency signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal; a phase control block coupled to the phase rotator core, the phase control block comprising: a first transistor having a control electrode coupled to receive a first control signal; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled to a first current electrode of the first transistor; a third transistor having a control electrode and a first current electrode coupled to the first current electrodes of the first and second transistors; a first filter having first terminal coupled to the control electrode and the first current electrode of the third transistor; a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal a first transistor having a control electrode coupled to receive a first control signal; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled to a first current electrode of the first transistor; a third transistor having a control electrode and a first current electrode coupled to the first current electrodes of the first and second transistors; a first filter having first terminal coupled to the control electrode and the first current electrode of the third transistor; a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal characterized in that the phase control block is comprising: a first switch having a first terminal coupled to the first current electrodes of the first and second transistors (208, 212), a second terminal coupled to the control electrode and the first current electrode of the third transistor, and a control terminal coupled to receive a third control signal; wherein the first switch is configured to be: closed based on a first state of the third control signal in order to define a sample mode; and open based on a second state of the third control signal in order to define a hold mode. a first switch having a first terminal coupled to the first current electrodes of the first and second transistors (208, 212), a second terminal coupled to the control electrode and the first current electrode of the third transistor, and a control terminal coupled to receive a third control signal; wherein the first switch is configured to be: closed based on a first state of the third control signal in order to define a sample mode; and open based on a second state of the third control signal in order to define a hold mode. closed based on a first state of the third control signal in order to define a sample mode; and open based on a second state of the third control signal in order to define a hold mode.