A discharge circuit for a DC-Link capacitor within a power-distribution-unit, the discharge circuit comprising: a first sub-circuit connected in parallel to the DC-Link capacitor and comprising a series connection of a first switching element, SE, (Q_FDa) and a first discharge resistor (R_FDa), wherein the DC-link capacitor is connected in parallel to a power supply, a second sub-circuit connected in parallel to the DC-Link capacitor and comprising a series connection of a second switching element, SE, (Q_FDb) and a second discharge resistor (R_FDb), and a control device comprising a plurality of delay circuits connected to the plurality of SEs (Q_FDa, Q_FDb), wherein the control device is configured to control the plurality of SEs (Q_FDa, Q_FDb) within the sub-circuits by scheduling switching of the plurality of SEs (Q_FDa, Q_FDb), wherein said scheduling, performed by the delay-circuits, comprises switching ON of the second SE (Q_FDb) after a switching ON of the first SE (Q_FDa) for enabling a discharging of the DC link capacitor within a predetermined duration, wherein the control device comprises a gate driver configured to output a control signal; wherein the plurality of delay-circuits are connected to the gate driver and comprise a first branch and a second branch connected to the first SE (Q_FDa) and the second SE (Q_FDb) respectively, characterized in that the plurality of delay-circuits further comprises series connected RC circuits, which comprise: a first resistor disposed on the first branch, and a second resistor disposed on the second branch, the second resistor being connected in series with the first resistor; a gate of the first SE (Q_FDa) is connected to a connection point within the first branch between the first resistor and the second resistor, and a gate of the second SE (Q_FDb) is connected to a connection point within the second branch, that is connected to the second resistor at a side opposite to the first resistor. a first sub-circuit connected in parallel to the DC-Link capacitor and comprising a series connection of a first switching element, SE, (Q_FDa) and a first discharge resistor (R_FDa), wherein the DC-link capacitor is connected in parallel to a power supply, a second sub-circuit connected in parallel to the DC-Link capacitor and comprising a series connection of a second switching element, SE, (Q_FDb) and a second discharge resistor (R_FDb), and a control device comprising a plurality of delay circuits connected to the plurality of SEs (Q_FDa, Q_FDb), wherein the control device is configured to control the plurality of SEs (Q_FDa, Q_FDb) within the sub-circuits by scheduling switching of the plurality of SEs (Q_FDa, Q_FDb), wherein said scheduling, performed by the delay-circuits, comprises switching ON of the second SE (Q_FDb) after a switching ON of the first SE (Q_FDa) for enabling a discharging of the DC link capacitor within a predetermined duration, wherein the control device comprises a gate driver configured to output a control signal; wherein the plurality of delay-circuits are connected to the gate driver and comprise a first branch and a second branch connected to the first SE (Q_FDa) and the second SE (Q_FDb) respectively, characterized in that the plurality of delay-circuits further comprises series connected RC circuits, which comprise: a first resistor disposed on the first branch, and a second resistor disposed on the second branch, the second resistor being connected in series with the first resistor; a first resistor disposed on the first branch, and a second resistor disposed on the second branch, the second resistor being connected in series with the first resistor; a gate of the first SE (Q_FDa) is connected to a connection point within the first branch between the first resistor and the second resistor, and a gate of the second SE (Q_FDb) is connected to a connection point within the second branch, that is connected to the second resistor at a side opposite to the first resistor.