A multiprocessor system comprising: one or a plurality of main processors and a plurality of sub-processors (30 to 3n) which execute a command issued; and an execution control circuit which conducts execution control of each of said plurality of sub-processors, wherein said execution control circuit comprises a status bus input unit which inputs a status notification indicative of a processing state of a command issued to each of said plurality of sub-processors from each of said plurality of sub-processors, a control bus output unit which outputs said command to each of said plurality of sub-processors, a status FIFO control unit which stores said status notification, and an execution control processor which obtains from the status FIFO control unit said status notification stored therein to issue said command to said control bus output unit by software processing, and the multiprocessor system is characterized in that said execution control circuit includes a status accelerator which issues said command to said control bus output unit by hardware processing which is faster than said software processing, and a determination circuit which determines whether or not said processing state indicated by said status notification that is input has one-to-one dependency with a command to be issued next on an operation sequence, said status accelerator issues said command by said hardware processing when said determination circuit determines that said processing state has said one-to-one dependency, and said execution control processor issues said command by said software processing when said determination circuit determines that said processing state does not have said one-to-one dependency. one or a plurality of main processors and a plurality of sub-processors (30 to 3n) which execute a command issued; and an execution control circuit which conducts execution control of each of said plurality of sub-processors, wherein said execution control circuit comprises a status bus input unit which inputs a status notification indicative of a processing state of a command issued to each of said plurality of sub-processors from each of said plurality of sub-processors, a control bus output unit which outputs said command to each of said plurality of sub-processors, a status FIFO control unit which stores said status notification, and an execution control processor which obtains from the status FIFO control unit said status notification stored therein to issue said command to said control bus output unit by software processing, and the multiprocessor system is characterized in that said execution control circuit includes a status accelerator which issues said command to said control bus output unit by hardware processing which is faster than said software processing, and a determination circuit which determines whether or not said processing state indicated by said status notification that is input has one-to-one dependency with a command to be issued next on an operation sequence, a status accelerator which issues said command to said control bus output unit by hardware processing which is faster than said software processing, and a determination circuit which determines whether or not said processing state indicated by said status notification that is input has one-to-one dependency with a command to be issued next on an operation sequence, said status accelerator issues said command by said hardware processing when said determination circuit determines that said processing state has said one-to-one dependency, and said execution control processor issues said command by said software processing when said determination circuit determines that said processing state does not have said one-to-one dependency.