A CMOS image sensor comprising: (a) a plurality of pixels arranged in an array; (b) a plurality of sample and hold arrays; and (c) a routing matrix which is configured to receive signals from lines of the pixel array and to route the signals to the plurality of sample and hold arrays, wherein each line contains pixels corresponding to four different colours, and wherein the routing matrix: (i) is configured to electronically divide the plurality of pixels in a line into four groups of N/4 pixels, N being the number of pixels in a line, each group containing only pixels in that line corresponding to a same color; (ii) has a common bus consisting of N/4 lines where N is the number of pixels in a line; (iii) has switches for routing signals from each group of pixels to one respective sample and hold array, the switches being composed of: (a) a first series of switches composed of four sets (F1-F4), each set in the first series of switches having N/4 switches, wherein each set in the first series of switches is adapted to simultaneously route all signals from pixels in one of said groups to the common bus; (b) a second series of switches also composed of four sets (F1-F4), each set in the second series of switches having N/4 switches, wherein each set in the second series of switches is adapted to simultaneously connect and route signals from pixels in a respective one of said groups on the common bus to the sample and hold array corresponding to said one of said groups; (iv) wherein the sets of switches are operable so as to route signals from pixels in only one group at a time to the sample and hold array corresponding to that group, and to route signals from pixels in each of the groups sequentially in time in a predetermined order. (a) a plurality of pixels arranged in an array; (b) a plurality of sample and hold arrays; and (c) a routing matrix which is configured to receive signals from lines of the pixel array and to route the signals to the plurality of sample and hold arrays, wherein each line contains pixels corresponding to four different colours, and wherein the routing matrix: (i) is configured to electronically divide the plurality of pixels in a line into four groups of N/4 pixels, N being the number of pixels in a line, each group containing only pixels in that line corresponding to a same color; (ii) has a common bus consisting of N/4 lines where N is the number of pixels in a line; (iii) has switches for routing signals from each group of pixels to one respective sample and hold array, the switches being composed of: (a) a first series of switches composed of four sets (F1-F4), each set in the first series of switches having N/4 switches, wherein each set in the first series of switches is adapted to simultaneously route all signals from pixels in one of said groups to the common bus; (b) a second series of switches also composed of four sets (F1-F4), each set in the second series of switches having N/4 switches, wherein each set in the second series of switches is adapted to simultaneously connect and route signals from pixels in a respective one of said groups on the common bus to the sample and hold array corresponding to said one of said groups; (iv) wherein the sets of switches are operable so as to route signals from pixels in only one group at a time to the sample and hold array corresponding to that group, and to route signals from pixels in each of the groups sequentially in time in a predetermined order. (i) is configured to electronically divide the plurality of pixels in a line into four groups of N/4 pixels, N being the number of pixels in a line, each group containing only pixels in that line corresponding to a same color; (ii) has a common bus consisting of N/4 lines where N is the number of pixels in a line; (iii) has switches for routing signals from each group of pixels to one respective sample and hold array, the switches being composed of: (a) a first series of switches composed of four sets (F1-F4), each set in the first series of switches having N/4 switches, wherein each set in the first series of switches is adapted to simultaneously route all signals from pixels in one of said groups to the common bus; (b) a second series of switches also composed of four sets (F1-F4), each set in the second series of switches having N/4 switches, wherein each set in the second series of switches is adapted to simultaneously connect and route signals from pixels in a respective one of said groups on the common bus to the sample and hold array corresponding to said one of said groups; (a) a first series of switches composed of four sets (F1-F4), each set in the first series of switches having N/4 switches, wherein each set in the first series of switches is adapted to simultaneously route all signals from pixels in one of said groups to the common bus; (b) a second series of switches also composed of four sets (F1-F4), each set in the second series of switches having N/4 switches, wherein each set in the second series of switches is adapted to simultaneously connect and route signals from pixels in a respective one of said groups on the common bus to the sample and hold array corresponding to said one of said groups; (iv) wherein the sets of switches are operable so as to route signals from pixels in only one group at a time to the sample and hold array corresponding to that group, and to route signals from pixels in each of the groups sequentially in time in a predetermined order.