A data processing device comprising: a data conversion processing unit configured to divide and input configuration bits of data to be processed into a plurality of lines, and to repeatedly execute a data conversion processing as to the data in each line; wherein the data conversion processing unit includes an F function executing unit configured to input one line of data configuring the plurality of lines, and to generate conversion data; wherein the F function executing unit includes a non-linear conversion processing unit configured to execute a non-linear conversion processing; wherein the non-linear conversion processing unit includes a repeating structure of a bit replacement unit and a non-linear calculation unit; wherein each respective non-linear calculation unit included in the repeating structure is a calculation unit configured of either one NAND or NOR calculation unit and either one XOR or XNOR calculation unit; wherein the non-linear conversion processing unit is configured to output one bit of the calculation result from either the NAND or the NOR calculation unit with 2-bit input and 1-bit output to either the XOR or the XNOR calculation unit, configured to execute either the XOR or the XNOR calculation with the other one bit of input data, and configured to output the 1-bit data generated from the calculation result of either the XOR or the XNOR as the configuration bit as the non-linear conversion processing result; and wherein the repeating structure of the non-linear conversion processing unit is a configuration including both a non-linear portion with a XOR calculation unit and a non-linear portion with a XNOR calculation unit. a data conversion processing unit configured to divide and input configuration bits of data to be processed into a plurality of lines, and to repeatedly execute a data conversion processing as to the data in each line; wherein the data conversion processing unit includes an F function executing unit configured to input one line of data configuring the plurality of lines, and to generate conversion data; wherein the F function executing unit includes a non-linear conversion processing unit configured to execute a non-linear conversion processing; wherein the non-linear conversion processing unit includes a repeating structure of a bit replacement unit and a non-linear calculation unit; wherein each respective non-linear calculation unit included in the repeating structure is a calculation unit configured of either one NAND or NOR calculation unit and either one XOR or XNOR calculation unit; wherein the non-linear conversion processing unit is configured to output one bit of the calculation result from either the NAND or the NOR calculation unit with 2-bit input and 1-bit output to either the XOR or the XNOR calculation unit, configured to execute either the XOR or the XNOR calculation with the other one bit of input data, and configured to output the 1-bit data generated from the calculation result of either the XOR or the XNOR as the configuration bit as the non-linear conversion processing result; and wherein the repeating structure of the non-linear conversion processing unit is a configuration including both a non-linear portion with a XOR calculation unit and a non-linear portion with a XNOR calculation unit.