An integrated device comprising: a hard logic portion comprising a plurality of hard logic blocks (710, 720, 722, 724, 726, 728, 730, 740, 742) wherein a first hard logic block of the plurality of hard logic blocks (710, 720, 722, 724, 726, 728, 730, 740, 742) is configured to provide a first data signal; and a field programmable gate array fabric, FPGA fabric, comprising control logic configured to provide a control signal and a plurality of soft logic modules, wherein a first soft logic module of the soft logic modules is configured to provide a second data signal; characterized by an interface configured to route signals between the hard logic portion and the FPGA fabric, wherein the interface comprises: a combiner circuit; a first multiplexer disposed in the hard logic portion, and configured to provide one of a first data signal and a zero value signal to the combiner circuit based on the control signal; a second multiplexer disposed in the hard logic portion, and configured to provide one of a second data signal and the zero value signal to the combiner circuit based on the control signal; and the combiner circuit is configured to combine the signals provided by the first and second multiplexers (726, 728) and to output a combined signal at a first node in the hard logic portion;wherein, responsive to a control signal from the control logic, the interface is further configured to selectively couple the first node in the hard logic portion to one of the first soft logic module and a first hard logic block. a hard logic portion comprising a plurality of hard logic blocks (710, 720, 722, 724, 726, 728, 730, 740, 742) wherein a first hard logic block of the plurality of hard logic blocks (710, 720, 722, 724, 726, 728, 730, 740, 742) is configured to provide a first data signal; and a field programmable gate array fabric, FPGA fabric, comprising control logic configured to provide a control signal and a plurality of soft logic modules, wherein a first soft logic module of the soft logic modules is configured to provide a second data signal; characterized by an interface configured to route signals between the hard logic portion and the FPGA fabric, wherein the interface comprises: a combiner circuit; a first multiplexer disposed in the hard logic portion, and configured to provide one of a first data signal and a zero value signal to the combiner circuit based on the control signal; a second multiplexer disposed in the hard logic portion, and configured to provide one of a second data signal and the zero value signal to the combiner circuit based on the control signal; and the combiner circuit is configured to combine the signals provided by the first and second multiplexers (726, 728) and to output a combined signal at a first node in the hard logic portion;wherein, responsive to a control signal from the control logic, the interface is further configured to selectively couple the first node in the hard logic portion to one of the first soft logic module and a first hard logic block. a combiner circuit; a first multiplexer disposed in the hard logic portion, and configured to provide one of a first data signal and a zero value signal to the combiner circuit based on the control signal; a second multiplexer disposed in the hard logic portion, and configured to provide one of a second data signal and the zero value signal to the combiner circuit based on the control signal; and the combiner circuit is configured to combine the signals provided by the first and second multiplexers (726, 728) and to output a combined signal at a first node in the hard logic portion;wherein, responsive to a control signal from the control logic, the interface is further configured to selectively couple the first node in the hard logic portion to one of the first soft logic module and a first hard logic block.