A system on chip, SoC, comprising: at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in one or more first packets of a first communication protocol, each first packet including a first header portion and a first data portion and the first communication protocol comprising an enhanced serial peripheral interface protocol; a selection logic coupled to the first host device to receive the one or more first packets and to selectively provide the one or more first packets to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol, selection being based on a determination of whether any interface (320, 330) is designed for tunneling operation, which is indicated via internal fuse setting or through external straps; the conversion logic to receive the one or more first packets under selection of the selection logic and to encapsulate the one or more first packets into one or more second packets of a second communication protocol, each second packet including a second header portion and a second data portion and the second communication protocol comprising a peripheral component interconnect express protocol; and a second interface coupled to the conversion logic to receive the one or more second packets and to communicate the one or more second packets to a second device via a second interconnect of the second communication protocol, wherein the second device comprises a second SoC or a central component to couple between the SoC and a shared resource, the shared resource to communicate according to the first communication protocol, wherein the shared resource comprises a non-volatile storage to store a basic input/output system, BIOS, wherein the SoC is to receive boot code of the BIOS from the non-volatile storage via the second interconnect during initialization, and wherein the conversion logic is to include a tunnel indicator in the second header portion of the one or more second packets of the second communication protocol to indicate presence of the encapsulated one or more first packets of the first communication protocol, incorporate a cycle type of the first header portion of the first packet into a cycle type field of the second header portion of the second packet, incorporate an address portion of the first header portion of the first packed into the second data portion of the second packet, and place the first data portion of the first packet into the second data portion of the second packet. at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in one or more first packets of a first communication protocol, each first packet including a first header portion and a first data portion and the first communication protocol comprising an enhanced serial peripheral interface protocol; a selection logic coupled to the first host device to receive the one or more first packets and to selectively provide the one or more first packets to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol, selection being based on a determination of whether any interface (320, 330) is designed for tunneling operation, which is indicated via internal fuse setting or through external straps; the conversion logic to receive the one or more first packets under selection of the selection logic and to encapsulate the one or more first packets into one or more second packets of a second communication protocol, each second packet including a second header portion and a second data portion and the second communication protocol comprising a peripheral component interconnect express protocol; and a second interface coupled to the conversion logic to receive the one or more second packets and to communicate the one or more second packets to a second device via a second interconnect of the second communication protocol, wherein the second device comprises a second SoC or a central component to couple between the SoC and a shared resource, the shared resource to communicate according to the first communication protocol, wherein the shared resource comprises a non-volatile storage to store a basic input/output system, BIOS, wherein the SoC is to receive boot code of the BIOS from the non-volatile storage via the second interconnect during initialization, and wherein the conversion logic is to include a tunnel indicator in the second header portion of the one or more second packets of the second communication protocol to indicate presence of the encapsulated one or more first packets of the first communication protocol, incorporate a cycle type of the first header portion of the first packet into a cycle type field of the second header portion of the second packet, incorporate an address portion of the first header portion of the first packed into the second data portion of the second packet, and place the first data portion of the first packet into the second data portion of the second packet.