An electronic apparatus comprising: a display device; and a host-side device, the display device including a first data transfer circuit, the first data transfer circuit serving as a timing controller for transferring data, which is indicative of the image, to a source driver, and the host-side device including a second data transfer circuit, the second data transfer circuit serving as a graphic controller for transferring data, which is indicative of an image, to the timing controller, each of the first data transfer circuit and the second data transfer circuit being a data transfer circuit for transferring data with use of at least one of a plurality of data lanes, said data transfer circuit comprising: determining means for determining, based on information in relation to an amount of data to be transferred during a predetermined time period, the number of data lanes via which the data is transferred, wherein the data is indicative of an image to be displayed on a display panel and the information defines a transfer period and a halt period; transferring means for transferring the data with use of a determined number of data lane(s), which number has been determined by the determining means, out of the plurality of data lanes; and data lane deactivating means for deactivating a data lane(s), which is not used to transfer the data, out of the plurality of data lanes; wherein one vertical period for displaying the image is divided into the transfer period during which the data is transferred to a receiver circuit and the halt period during which the data is not transferred; and the determining means is adapted to set the number of data lanes to zero during the halt period. a display device; and a host-side device, the display device including a first data transfer circuit, the first data transfer circuit serving as a timing controller for transferring data, which is indicative of the image, to a source driver, and the host-side device including a second data transfer circuit, the second data transfer circuit serving as a graphic controller for transferring data, which is indicative of an image, to the timing controller, each of the first data transfer circuit and the second data transfer circuit being a data transfer circuit for transferring data with use of at least one of a plurality of data lanes, said data transfer circuit comprising: determining means for determining, based on information in relation to an amount of data to be transferred during a predetermined time period, the number of data lanes via which the data is transferred, wherein the data is indicative of an image to be displayed on a display panel and the information defines a transfer period and a halt period; transferring means for transferring the data with use of a determined number of data lane(s), which number has been determined by the determining means, out of the plurality of data lanes; and data lane deactivating means for deactivating a data lane(s), which is not used to transfer the data, out of the plurality of data lanes; wherein one vertical period for displaying the image is divided into the transfer period during which the data is transferred to a receiver circuit and the halt period during which the data is not transferred; and the determining means is adapted to set the number of data lanes to zero during the halt period. determining means for determining, based on information in relation to an amount of data to be transferred during a predetermined time period, the number of data lanes via which the data is transferred, wherein the data is indicative of an image to be displayed on a display panel and the information defines a transfer period and a halt period; transferring means for transferring the data with use of a determined number of data lane(s), which number has been determined by the determining means, out of the plurality of data lanes; and data lane deactivating means for deactivating a data lane(s), which is not used to transfer the data, out of the plurality of data lanes; wherein one vertical period for displaying the image is divided into the transfer period during which the data is transferred to a receiver circuit and the halt period during which the data is not transferred; and the determining means is adapted to set the number of data lanes to zero during the halt period.