A memory system comprising: an interface circuit; a memory controller configured to exchange data with the interface circuit according to a first clock, the data including one or more of read data and write data; and a memory device including a plurality of non-volatile memories (320_1, 320_2, 320_N) and the interface circuit connected to the memory controller and the plurality of non-volatile memories, the interface circuit configured to, divide the first clock into a second clock based on a number of the plurality of non-volatile memories, and exchange the data with the plurality of non-volatile memories, according to the second clock; wherein the interface circuit comprises: a deserializer configured to receive the write data from the memory controller, divide the first clock into the second clock based on the number of the plurality of non-volatile memories, divide the write data to generate divided write data, and to transmit the divided write data to respective ones of the plurality of non-volatile memories based on the second clock; and a serializer configured to receive divided read data from the plurality of non-volatile memories based on the second clock, buffer the divided read data, generate the read data based on the divided read data, and transmit the read data to the memory controller based on the first clock, wherein the serializer comprises: a plurality of buffer registers (370_1. 370_2) connected to respective ones of the plurality of non-volatile memories, the plurality of buffer registers configured to buffer the divided read data received from the respective ones of the plurality of non-volatile memories; and a combiner configured to generate the read data from the divided read data, wherein the interface circuit further comprises: a time-to-digital converter TDC configured to receive data strobe signals from the plurality of non-volatile memories, and detect a skew based on a difference between times when the data strobe signals are received from the plurality of non-volatile memories; wherein the interface circuit is further configured to determine, based on the skew, a delay time associated with the divided read data such that the divided read data buffered in different ones of the plurality of buffer registers correspond to each other, wherein the interface circuit is further configured to variably determine an additional delay based on memory sizes of the plurality of buffer registers. an interface circuit; a memory controller configured to exchange data with the interface circuit according to a first clock, the data including one or more of read data and write data; and a memory device including a plurality of non-volatile memories (320_1, 320_2, 320_N) and the interface circuit connected to the memory controller and the plurality of non-volatile memories, the interface circuit configured to, divide the first clock into a second clock based on a number of the plurality of non-volatile memories, and exchange the data with the plurality of non-volatile memories, according to the second clock; wherein the interface circuit comprises: a deserializer configured to receive the write data from the memory controller, divide the first clock into the second clock based on the number of the plurality of non-volatile memories, divide the write data to generate divided write data, and to transmit the divided write data to respective ones of the plurality of non-volatile memories based on the second clock; and a serializer configured to receive divided read data from the plurality of non-volatile memories based on the second clock, buffer the divided read data, generate the read data based on the divided read data, and transmit the read data to the memory divide the first clock into a second clock based on a number of the plurality of non-volatile memories, and exchange the data with the plurality of non-volatile memories, according to the second clock; a deserializer configured to receive the write data from the memory controller, divide the first clock into the second clock based on the number of the plurality of non-volatile memories, divide the write data to generate divided write data, and to transmit the divided write data to respective ones of the plurality of non-volatile memories based on the second clock; and a serializer configured to receive divided read data from the plurality of non-volatile memories based on the second clock, buffer the divided read data, generate the read data based on the divided read data, and transmit the read data to the memory controller based on the first clock, a plurality of buffer registers (370_1. 370_2) connected to respective ones of the plurality of non-volatile memories, the plurality of buffer registers configured to buffer the divided read data received from the respective ones of the plurality of non-volatile memories; and a combiner configured to generate the read data from the divided read data, wherein the interface circuit further comprises: a time-to-digital converter TDC configured to receive data strobe signals from the plurality of non-volatile memories, and detect a skew based on a difference between times when the data strobe signals are received from the plurality of non-volatile memories;