A successive approximation register, SAR, analog-to-digital converter, ADC, configured to receive an analog input signal and provide a digital output signal, the SAR ADC comprising: a capacitor bank (210, 220) for successively providing a plurality of signal levels (252, 253) based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal; and controlling circuitry configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal, wherein the controlling circuitry is configured to dynamically control a respective selector (231, 236) of each capacitor (211, 216, 221, 226) of the capacitor bank to charge the capacitor using either the sample value of the analog input signal or an opposed version of the sample value of the analog input signal by connecting, at a sampling phase, a first plate of each capacitor to the analog input signal or to the opposed version of the analog input signal, wherein a setting of the respective selectors, at the sampling phase, is controlled by a digital representation of a scaling value for the dynamically scaled version of the sample value of the analog input signal such that the setting of the respective selectors corresponds to the digital representation of the scaling value in that the analog input signal and the opposed version of the analog input signal represent respective binary values of the digital representation, and wherein the scaling value is selected as a digital representation of a sample value of an oscillator signal, to perform down-conversion on the analog input signal. a capacitor bank (210, 220) for successively providing a plurality of signal levels (252, 253) based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal; and controlling circuitry configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal, wherein the controlling circuitry is configured to dynamically control a respective selector (231, 236) of each capacitor (211, 216, 221, 226) of the capacitor bank to charge the capacitor using either the sample value of the analog input signal or an opposed version of the sample value of the analog input signal by connecting, at a sampling phase, a first plate of each capacitor to the analog input signal or to the opposed version of the analog input signal, wherein a setting of the respective selectors, at the sampling phase, is controlled by a digital representation of a scaling value for the dynamically scaled version of the sample value of the analog input signal such that the setting of the respective selectors corresponds to the digital representation of the scaling value in that the analog input signal and the opposed version of the analog input signal represent respective binary values of the digital representation, and wherein the scaling value is selected as a digital representation of a sample value of an oscillator signal, to perform down-conversion on the analog input signal.