A data processing apparatus, wherein: code bits of a Low Density Parity Check, LDPC, code, the LDPC code being an LDPC code which is prescribed in the DVB-S.2 standard ETSI EN 302 307 V1.1.2 and having a code length of N of 64,800 bits and an encoding rate of 5/6, are written in a column direction of a storage means for storing the code bits in a row direction and the column direction and m bits of the code bits of the LDPC code read out in the row direction are set as one symbol, and besides a predetermined positive integer is represented by b, said storage means stores mb bits in the row direction and stores N/(mb) bits in the column direction, where the m bits are 12 bits and the integer b is 1 and besides 12 code bits are mapped as one symbol to one of 2 12 or 4,096 signal points prescribed in 4096QAM; the code bits of the LDPC code being written in the column direction of said storage means and read out in the row direction; where the mb code bits read out in the row direction of said storage means are set as b symbols, in accordance with an allocation rule for allocating the code bits of the LDPC code to symbol bits representative of the symbols, said data processing apparatus comprising replacement means for allocating the mb code bits to mb symbol bits, said storage means having 12 columns for storing 12 × 1 bits in the row direction and storing 64,800/(12 × 1) bits in the column direction; said replacement means carrying out, where the ith bit from the most significant bit of the 12 × 1 code bits read out in the row direction of said storage means is represented as bit b i and the ith bit from the most significant bit of the 12 × 1 symbol bits of one symbol is represented as bit y i, in accordance with the allocation rule, allocating the bit b 0 to the bit y 8, the bit b 1 to the bit y 0, the bit b 2 to the bit y 6, the bit b 3 to the bit y 1, the bit b 4 to the bit y 4, the bit b 5 to the bit y 5, the bit b 6 to the bit y 2, the bit b 7 to the bit y 3, the bit b 8 to the bit y 7, the bit b 9 to the bit y 10, the bit b 10 to the bit y 11, and the bit b 11 to the bit y 9. code bits of a Low Density Parity Check, LDPC, code, the LDPC code being an LDPC code which is prescribed in the DVB-S.2 standard ETSI EN 302 307 V1.1.2 and having a code length of N of 64,800 bits and an encoding rate of 5/6, are written in a column direction of a storage means for storing the code bits in a row direction and the column direction and m bits of the code bits of the LDPC code read out in the row direction are set as one symbol, and besides a predetermined positive integer is represented by b, said storage means stores mb bits in the row direction and stores N/(mb) bits in the column direction, where the m bits are 12 bits and the integer b is 1 and besides 12 code bits are mapped as one symbol to one of 2 12 or 4,096 signal points prescribed in 4096QAM; the code bits of the LDPC code being written in the column direction of said storage means and read out in the row direction; where the mb code bits read out in the row direction of said storage means are set as b symbols, in accordance with an allocation rule for allocating the code bits of the LDPC code to symbol bits representative of the symbols, said data processing apparatus comprising replacement means for allocating the mb code bits to mb symbol bits, said storage means having 12 columns for storing 12 × 1 bits in the row direction and storing 64,800/(12 × 1) bits in the column direction; said replacement means carrying out, where the ith bit from the most significant bit of the 12 × 1 code bits read out in the row direction of said storage means is represented as bit b i and the ith bit from the most significant bit of the 12 × 1 symbol bits of one symbol is represented as bit y i, in accordance with the allocation rule, allocating the bit b 0 to the bit y 8, the bit b 1 to the bit y 0, the bit b 2 to the bit y 6, the bit b 3 to the bit y 1, the bit b 4 to the bit y 4, the bit b 5 to the bit y 5, the bit b 6 to the bit y 2, the bit b 7 to the bit y 3, the bit b 8 to the bit y 7, the bit b 9 to the bit y 10, the bit b 10 to the bit y 11, and the bit b 11 to the bit y 9.