A semiconductor device (30,50) comprising: a first insulation layer; a wiring layer formed on a first surface of the first insulation layer, the wiring layer including an external connection pad formed on a first surface of the wiring layer and located at a periphery of the first insulation layer, and an internal connection pad formed on the first surface of the wiring layer and located at an inner portion of the wiring layer; a resist layer (31,32) that covers the first surface of the wiring layer, the resist layer (31,32) including a first opening that exposes the internal connection pad, and a second opening that exposes the external connection pad; a semiconductor element located facing the first surface of the first insulation layer so as not to be overlapped with the external connection pad in a plan view, the semiconductor element being a sensor chip and including an electrode pad formed on a first surface of the sensor chip that faces the first surface of the first insulation layer and located at a position corresponding to the internal connection pad, a bump formed on the electrode pad and connected to the internal connection pad, a circuit element region defined in the first surface of the sensor chip so as not to be overlapped with the wiring layer in a plan view, and sensor elements formed in the circuit element region; a second insulation layer that fills a gap between the first surface of the sensor chip and the first surface of the first insulation layer, wherein the second insulation layer covers a side surface of the sensor chip; a third insulation layer that covers a second surface of the sensor chip and the second insulation layer, wherein the third insulation layer includes an opening at a position corresponding to the external connection pad, and the second surface of the sensor chip is located at a side opposite to the first surface of the sensor chip; an external connection terminal connected to the external connection pad; and a step formed at an edge portion of the semiconductor device (50 or 30) by an edge portion of the first insulation layer, an edge portion of the resist layer (13 or 31,32), and an edge portion of the third insulation layer. a first insulation layer; a wiring layer formed on a first surface of the first insulation layer, the wiring layer including an external connection pad formed on a first surface of the wiring layer and located at a periphery of the first insulation layer, and an internal connection pad formed on the first surface of the wiring layer and located at an inner portion of the wiring layer; a resist layer (31,32) that covers the first surface of the wiring layer, the resist layer (31,32) including a first opening that exposes the internal connection pad, and a second opening that exposes the external connection pad; an external connection pad formed on a first surface of the wiring layer and located at a periphery of the first insulation layer, and an internal connection pad formed on the first surface of the wiring layer and located at an inner portion of the wiring layer; a resist layer (31,32) that covers the first surface of the wiring layer, the resist layer (31,32) including a first opening that exposes the internal connection pad, and a second opening that exposes the external connection pad; a semiconductor element located facing the first surface of the first insulation layer so as not to be overlapped with the external connection pad in a plan view, the semiconductor element being a sensor chip and including an electrode pad formed on a first surface of the sensor chip that faces the first surface of the first insulation layer and located at a position corresponding to the internal connection pad, a bump formed on the electrode pad and connected to the internal connection pad, a circuit element region defined in the first surface of the sensor chip so as not to be overlapped with the wiring layer in a plan view, and sensor elements formed in the circuit element region; an electrode pad formed on a first surface of the sensor chip that faces the first surface of the first insulation layer and located at a position corresponding to the internal connection pad, a bump formed on the electrode pad and connected to the internal connection pad, a circuit element region defined in the first surface of the sensor chip so as not to be overlapped with the wiring layer in a plan view, and sensor elements formed in the circuit element region; a second insulation layer that fills a gap between the first surface of the sensor chip and the first surface of the first insulation layer, wherein the second insulation layer covers a side surface of the sensor chip; a third insulation layer that covers a second surface of the sensor chip and the second insulation layer, wherein the third insulation layer includes an opening at a position corresponding to the external connection pad, and the second surface of the sensor chip is located at a side opposite to the first surface of the sensor chip; an external connection terminal connected to the external connection pad; and a step formed at an edge portion of the semiconductor device (50 or 30) by an edge portion of the first insulation layer, an edge portion of the resist layer (13 or 31,32), and an edge portion of the third insulation layer.