A current latched sense amplifier comprising: a cross coupled first and second inverter (P1, P2, N3, N4) a first transistor having a first source coupled to a first bit line and a first gate configured to receive a sense signal from a sense input (SENSE), wherein the first transistor is configured to couple the first bit line to a first output node (sout) of said inverter (P1, N3) to supply a first voltage to the first output node from the first bit line when the sense signal has a first logic level and to isolate the first output node from the first bit line when the sense signal has a second logic level; a second transistor having a second source coupled to a second bit line (BITB) and a second gate configured to receive the sense signal, wherein the second transistor is configured to couple the second bit line to a second output node (soutb) of said second inverter (P2, N4) to supply a second voltage to the second output node from the second bit line when the sense signal has the first logic level and to isolate the second output node from the second bit line when the sense signal has the second logic level; characterized in composing a third transistor having a third gate coupled to the second bit line (BITB) and coupled to the second source of the second transistor, the third transistor configured to receive the second voltage from the second bit line (BITB) when the sense signal (SENSE) has the second logic level in order to discharge the first output node (sout); and a fourth transistor having a fourth gate coupled to the first bit line and coupled to the first source of the first transistor, the fourth transistor configured to receive the first voltage from the first bit line when the sense signal (SENSE) has the second logic level in order to discharge the second output node (soutb). a cross coupled first and second inverter (P1, P2, N3, N4) a first transistor having a first source coupled to a first bit line and a first gate configured to receive a sense signal from a sense input (SENSE), wherein the first transistor is configured to couple the first bit line to a first output node (sout) of said inverter (P1, N3) to supply a first voltage to the first output node from the first bit line when the sense signal has a first logic level and to isolate the first output node from the first bit line when the sense signal has a second logic level; a second transistor having a second source coupled to a second bit line (BITB) and a second gate configured to receive the sense signal, wherein the second transistor is configured to couple the second bit line to a second output node (soutb) of said second inverter (P2, N4) to supply a second voltage to the second output node from the second bit line when the sense signal has the first logic level and to isolate the second output node from the second bit line when the sense signal has the second logic level; characterized in composing a third transistor having a third gate coupled to the second bit line (BITB) and coupled to the second source of the second transistor, the third transistor configured to receive the second voltage from the second bit line (BITB) when the sense signal (SENSE) has the second logic level in order to discharge the first output node (sout); and a fourth transistor having a fourth gate coupled to the first bit line and coupled to the first source of the first transistor, the fourth transistor configured to receive the first voltage from the first bit line when the sense signal (SENSE) has the second logic level in order to discharge the second output node (soutb).