A pixel array, the pixel array comprising: a Si x Ge y layer disposed directly on a back side of a first semiconductor layer; a plurality of pixels (161, 163, 165, 167) disposed in the first semiconductor layer proximate to a front side of the first semiconductor layer, the plurality of pixels (161, 163, 165, 167) including: a first portion of pixels (161, 163, 167), wherein each of the first portion of pixels (161, 163, 167) includes a first doped region that is separated from the Si x Ge y layer by a spacer region, wherein the spacer region is of an opposite majority charge carrier type to the Si x Ge y layer; and a second portion of pixels, wherein each one of the second portion of pixels includes a first doped region in contact with the Si x Ge y layer, wherein the first doped region of each one of the second portion of pixels is of the same majority charge carrier type as the Si x Ge y layer; and pinning wells (113, 115) disposed between individual pixels in the plurality of pixels (161, 163, 165, 167), wherein the pinning wells (113, 115) are of an opposite majority charge carrier type to the Si x Ge y layer, and wherein a first portion of the pinning wells extends only through the first semiconductor layer, and a second portion of the pinning wells extends through the first semiconductor layer and the Si x Ge y layer; wherein each one of the individual pixels (161, 163, 165, 167) includes a transfer gate on the front side coupled to transfer charge from a second doped region to a floating diffusion, wherein the second doped region is in contact with the first doped region (119, 120) of the pixel and is of an opposite majority charge carrier type as the first doped region (119, 120). a Si x Ge y layer disposed directly on a back side of a first semiconductor layer; a plurality of pixels (161, 163, 165, 167) disposed in the first semiconductor layer proximate to a front side of the first semiconductor layer, the plurality of pixels (161, 163, 165, 167) including: a first portion of pixels (161, 163, 167), wherein each of the first portion of pixels (161, 163, 167) includes a first doped region that is separated from the Si x Ge y layer by a spacer region, wherein the spacer region is of an opposite majority charge carrier type to the Si x Ge y layer; and a second portion of pixels, wherein each one of the second portion of pixels includes a first doped region in contact with the Si x Ge y layer, wherein the first doped region of each one of the second portion of pixels is of the same majority charge carrier type as the Si x Ge y layer; and a first portion of pixels (161, 163, 167), wherein each of the first portion of pixels (161, 163, 167) includes a first doped region that is separated from the Si x Ge y layer by a spacer region, wherein the spacer region is of an opposite majority charge carrier type to the Si x Ge y layer; and a second portion of pixels, wherein each one of the second portion of pixels includes a first doped region in contact with the Si x Ge y layer, wherein the first doped region of each one of the second portion of pixels is of the same majority charge carrier type as the Si x Ge y layer; and pinning wells (113, 115) disposed between individual pixels in the plurality of pixels (161, 163, 165, 167), wherein the pinning wells (113, 115) are of an opposite majority charge carrier type to the Si x Ge y layer, and wherein a first portion of the pinning wells extends only through the first semiconductor layer, and a second portion of the pinning wells extends through the first semiconductor layer and the Si x Ge y layer; wherein each one of the individual pixels (161, 163, 165, 167) includes a transfer gate on the front side coupled to transfer charge from a second doped region to a floating diffusion, wherein the second doped region is in contact with the first doped region (119, 120) of the pixel and is of an opposite majority charge carrier type as the first doped region (119, 120).