Driver circuit for a power amplifier of class D type comprising: - at least a first output terminal; - a high power supply rail adapted to receive a high power supply voltage (Vbat) and a low power supply rail adapted to receive a low supply voltage (Gnd); - at least first and second current branches (21;22) arranged in parallel between the high power supply rail and the low power supply rail, each comprising at least a first switch (LSS1;LSS2) and being adapted to drive power to the output terminal, and said second current branch is adapted to be powered in a first configuration of the driver circuit and powered down in a second configuration of the driver circuit; wherein: - the first switch of the first branch comprises a switching Metal Oxyde Semiconductor, MOS, transistor of a first conduction type, wherein the first conduction type is the N conduction type, which is adapted to be controlled by a first switching signal, in series with a cascode MOS transistor (MN casc1) of said first conduction type, which is adapted to be controlled by first static bias control signal (VcascN); - the first switch of the second branch comprises a switching NMOS transistor of a given deep submicron CMOS technology, which is adapted to be controlled by a second switching signal, in series with a cascode NMOS transistor (MN casc2), which is adapted to be controlled by a first dynamic bias control signal (DyncascN); and, - the driver circuit further comprising a first bias circuitry adapted to dynamically generate the first dynamic bias control signal (DyncascN) from the first static bias control signal (VcascN) and from at least one additional control signal (EN_LP) enabling operation of the driver circuit in the second configuration, said first bias circuitry being further adapted to cause the cascode NMOS transistor (MN casc2) of the first switch of the second branch to be 'Off' in said second configuration of the driver circuit and being furthermore adapted to cause a gate terminal of the cascode NMOS transistor of the first switch of the second branch to receive the first static bias control signal (VcascN) if the voltage at the output node goes above the voltage of said first static bias control signal (VcascN) plus a threshold voltage (VthN) of NMOS transistors in the CMOS technology, or to be connected to the output terminal if the voltage at the output node goes below the first static bias control signal (VcascN) minus said threshold voltage. - at least a first output terminal; - a high power supply rail adapted to receive a high power supply voltage (Vbat) and a low power supply rail adapted to receive a low supply voltage (Gnd); - at least first and second current branches (21;22) arranged in parallel between the high power supply rail and the low power supply rail, each comprising at least a first switch (LSS1;LSS2) and being adapted to drive power to the output terminal, and said second current branch is adapted to be powered in a first configuration of the driver circuit and powered down in a second configuration of the driver circuit; - the first switch of the first branch comprises a switching Metal Oxyde Semiconductor, MOS, transistor of a first conduction type, wherein the first conduction type is the N conduction type, which is adapted to be controlled by a first switching signal, in series with a cascode MOS transistor (MN casc1) of said first conduction type, which is adapted to be controlled by first static bias control signal (VcascN); - the first switch of the second branch comprises a switching NMOS transistor of a given deep submicron CMOS technology, which is adapted to be controlled by a second switching signal, in series with a cascode NMOS transistor (MN casc2), which is adapted to be controlled by a first dynamic bias control signal (DyncascN); and, - the driver circuit further comprising a first bias circuitry adapted to dynamically generate the first dynamic bias control signal (DyncascN) from the first static bias control signal (VcascN) and from at least one additional control signal (EN_LP) enabling operation of the driver circuit in the second configuration, said first bias circuitry being further adapted to cause the cascode NMOS transistor (MN casc2) of the first switch of the second branch to be 'Off' in said second configuration of the driver circuit and being furthermore adapted to cause a gate terminal of the cascode NMOS transistor of the first switch of the second branch to receive the first static bias control signal (VcascN) if the voltage at the output node goes above the voltage of said first static bias control signal (VcascN) plus a threshold voltage (VthN) of NMOS transistors in the CMOS technology, or to be connected to the output terminal if the voltage at the output node goes below the first static bias control signal (VcascN) minus said threshold voltage.