A method (1200, 1400) comprising the following steps: analyzing, by a computer system, a hardware description language implementation of a circuit design for a programmable logic device; generating, by the computer system, a hierarchical representation of the circuit design based on the analysis, the hierarchical representation including a plurality of modules; receiving, by the computer system, input to partition the hierarchical representation of the circuit design into a first portion and a second portion, each of the first and the second portions including at least one of the modules; generating, by the computer system, a first programming file that includes configuration settings in the form of programming bits for both the first and second portions; generating, by the computer system, a second programming file that includes configuration settings in the form of programming bits for the second portion based on the partition, the second programming file including default programming bits in the portions of the second programming file associated with the first portion; generating, by the computer system, a bitmask that identifies the bits in the second programming file associated with the second configuration settings; verifying, by the computer system, at least the second configuration settings for the second portion; receiving, by the computer system, input for revising the first portion; generating, by the computer system, a third programming file that includes configuration settings in the form of programming bits for the revised first portion; and merging, by the computer system, the second programming file, including the verified configuration settings for the second portion, with the third programming file using the bitmask. analyzing, by a computer system, a hardware description language implementation of a circuit design for a programmable logic device; generating, by the computer system, a hierarchical representation of the circuit design based on the analysis, the hierarchical representation including a plurality of modules; receiving, by the computer system, input to partition the hierarchical representation of the circuit design into a first portion and a second portion, each of the first and the second portions including at least one of the modules; generating, by the computer system, a first programming file that includes configuration settings in the form of programming bits for both the first and second portions; generating, by the computer system, a second programming file that includes configuration settings in the form of programming bits for the second portion based on the partition, the second programming file including default programming bits in the portions of the second programming file associated with the first portion; generating, by the computer system, a bitmask that identifies the bits in the second programming file associated with the second configuration settings; verifying, by the computer system, at least the second configuration settings for the second portion; receiving, by the computer system, input for revising the first portion; generating, by the computer system, a third programming file that includes configuration settings in the form of programming bits for the revised first portion; and merging, by the computer system, the second programming file, including the verified configuration settings for the second portion, with the third programming file using the bitmask.