A transient voltage suppressor device, comprising: a transient voltage suppression circuit connected between a voltage source lead for connection to a positive terminal of a voltage source, and a voltage return lead for connection to a negative terminal of the voltage source; a first voltage monitor lead connected to a first voltage monitor at one end and to the TVS circuit at an opposite end; a second voltage monitor lead connected to a second voltage monitor at one end and to the TVS circuit at an opposite end; and a voltage injection circuit with a plurality of output voltage levels connected to the TVS circuit to provide indication via the voltage monitors if the TVS circuit is shorted or open; wherein the TVS device further includes a first resistor leg connected in parallel with the TVS circuit, the first resistor leg including a first resistor connected in series with a second resistor; the TVS device further including a second resistor leg connected in parallel with the first resistor leg; wherein the TVS circuit comprises a first diode and a second diode connected in series between the voltage source and return leads; and wherein the voltage injection circuit is connected to the TVS circuit at a voltage node interposed between the first and second diodes; wherein the second voltage monitor lead is connected at the voltage node interposed between the first and second diodes; and wherein the second voltage monitor lead is further connected to a voltage node interposed between the first and second resistors, the device further including a source disconnect switch connected to the voltage source lead in such a way that, when a voltage source is connected to the transient voltage suppressor device, the source disconnect switch is connected between the voltage source and the TVS circuit; and wherein the first voltage monitor lead is connected between the source disconnect switch and the TVS circuit; and a processor communicative with a memory and operative associated with the source disconnect switch, the voltage injection circuit, first voltage monitor, and second voltage monitor, the memory having instructions recorded thereon that, when read by the processor, cause the processor to: determine if the first diode is shorted; determine if the first diode is open; determine if the second diode is shorted; and determine if the second diode is open. a transient voltage suppression circuit connected between a voltage source lead for connection to a positive terminal of a voltage source, and a voltage return lead for connection to a negative terminal of the voltage source; a first voltage monitor lead connected to a first voltage monitor at one end and to the TVS circuit at an opposite end; a second voltage monitor lead connected to a second voltage monitor at one end and to the TVS circuit at an opposite end; and a voltage injection circuit with a plurality of output voltage levels connected to the TVS circuit to provide indication via the voltage monitors if the TVS circuit is shorted or open; wherein the TVS device further includes a first resistor leg connected in parallel with the TVS circuit, the first resistor leg including a first resistor connected in series with a second resistor; the TVS device further including a second resistor leg connected in parallel with the first resistor leg; wherein the TVS circuit comprises a first diode and a second diode connected in series between the voltage source and return leads; and wherein the voltage injection circuit is connected to the TVS circuit at a voltage node interposed between the first and second diodes; wherein the second voltage monitor lead is connected at the voltage node interposed between the first and second diodes; and wherein the second voltage monitor lead is further connected to a voltage node interposed between the first and second resistors, the device further including a source disconnect switch connected to the voltage source lead in such a way that, when a voltage source is connected to the transient voltage suppressor device, the source disconnect switch is connected between the voltage source and the TVS circuit; and wherein the first voltage monitor lead is connected between the source disconnect switch and the TVS circuit; and a processor communicative with a memory and operative associated with the source disconnect switch, the voltage injection circuit, first voltage monitor, and second voltage monitor, the memory having instructions recorded thereon that, when read by the processor, cause the processor to: determine if the first diode is shorted; determine if the first diode is open; determine if the second diode is shorted; and determine if the second diode is open. determine if the first diode is shorted; determine if the first diode is open; determine if the second diode is shorted; and determine if the second diode is open.