A memory controller comprising: input/output, I/O, circuitry configured to receive channel temperature information from a plurality of DRAM stacked memory dies (102, 104) being high-bandwidth memories, HBM, compatible with a Joint Electronic Device Engineering Council, JEDEC, HBM standard, wherein the channel temperature information indicate a temperature of a channel of a memory die of the plurality of DRAM stacked memory dies, and the channel is configured to be divided into at least two pseudo sub-channels that share row and command buses of the channel; at least one channel command circuitry that includes: two pairs each of a combination of a command generator (482, 484) and a buffer (486, 488), each pair allocated to each pseudo sub-channel, the command generator configured to generate, based on a memory access request received by the buffer to the memory die, associated row and column commands; and a memory command arbitration circuitry configured to receive the row and column commands generated by the respective command generators, and to determine an appropriate order to transmit the received row and column commands to the channel; and a thermal handling circuitry configured to, based on the channel temperature information, generate and transmit, to the at least one channel command circuitry, row and column command throttling signals (490, 492) which are inverted and combined in a logical AND operation with the row and column commands generated by the respective channel command generators, before said row and column commands are being received by the memory command arbitration circuitry, the row and column command throttling signals are arranged to throttle the row commands transmitted to the channel at a first rate, wherein a row command is an ACTIVATE command to select a memory die of the plurality of DRAM stacked memory dies and a row address in the selected memory die to be activated; and throttle the column commands transmitted to the channel at a second rate, wherein a column command is a READ command or a WRITE command, the READ command is to decode a column along a row indicated by the activated row address, and the WRITE command is to store data in the selected memory die. input/output, I/O, circuitry configured to receive channel temperature information from a plurality of DRAM stacked memory dies (102, 104) being high-bandwidth memories, HBM, compatible with a Joint Electronic Device Engineering Council, JEDEC, HBM standard, wherein the channel temperature information indicate a temperature of a channel of a memory die of the plurality of DRAM stacked memory dies, and the channel is configured to be divided into at least two pseudo sub-channels that share row and command buses of the channel; at least one channel command circuitry that includes: two pairs each of a combination of a command generator (482, 484) and a buffer (486, 488), each pair allocated to each pseudo sub-channel, the command generator configured to generate, based on a memory access request received by the buffer to the memory die, associated row and column commands; and a memory command arbitration circuitry configured to receive the row and column commands generated by the respective command generators, and to determine an appropriate order to transmit the received row and column commands to the channel; and two pairs each of a combination of a command generator (482, 484) and a buffer (486, 488), each pair allocated to each pseudo sub-channel, the command generator configured to generate, based on a memory access request received by the buffer to the memory die, associated row and column commands; and a memory command arbitration circuitry configured to receive the row and column commands generated by the respective command generators, and to determine an appropriate order to transmit the received row and column commands to the channel; and a thermal handling circuitry configured to, based on the channel temperature information, generate and transmit, to the at least one channel command circuitry, row and column command throttling signals (490, 492) which are inverted and combined in a logical AND operation with the row and column commands generated by the respective channel command generators, before said row and column commands are being received by the memory command arbitration circuitry, the row and column command throttling signals are arranged to throttle the row commands transmitted to the channel at a first rate, wherein a row command is an ACTIVATE command to select a memory die of the plurality of DRAM stacked memory dies and a row address in the selected memory die to be activated; and throttle the column commands transmitted to the channel at a second rate, wherein a column command is a READ command or a WRITE command, the READ command is to decode a column along a row indicated by the activated row address, and the WRITE command is to store data in the selected memory die. throttle the row commands transmitted to the channel at a first rate, wherein a row command is an ACTIVATE command to select a memory die of the plurality of DRAM stacked memory dies and a row address in the selected memory die to be activated; and throttle the column commands transmitted to the channel at a second rate, wherein a column command is a READ command or a WRITE command, the READ command is to decode a column along a row indicated by the activated row address, and the WRITE command is to store data in the selected memory die.