A memory array (200, 400), comprising: first (255 1, 455 2) and second (255 2, 455 2) substantially vertical, adjacent semiconductor structures, wherein the first (255 1, 455 2) and the second (255 2, 455 2) semiconductor structures each comprise a sidewall having a curved surface; first and second charge storage structures, wherein the first charge storage structures is adjacent to the first semiconductor structure (255 1, 455 2) and wraps at least partially around the curved surface of the sidewall of the first semiconductor structure (255 1, 455 2), and wherein the second charge storage structures is adjacent to the second semiconductor structure (255 2, 455 2) and wraps at least partially around the curved surface of the sidewall of the second semiconductor structure (255 2, 455 2); a plurality of first (265 2,1, 465 2,1) and second control gates (265 2,2, 465 2,2), wherein the first control gates (265 2,1, 465 2,1) are each adjacent to a respective portion of the first charge storage structures, and wherein the second control gates (265 2,2, 465 2,2) are each adjacent to a respective portion of the second charge storage structures; wherein each memory cell (272 1, 472 2,1) of a first serially-coupled string of memory cells (272 1, 472 2,1) comprises a respective one of the first control gates (265 2,1, 465 2,1) and a respective portion of the first charge storage structures; wherein each memory cell (272 2, 472 2,2) of a second serially-coupled string of memory cells (272 2, 472 2,2) comprises a respective one of the second control gates (265 2,2, 465 2,2) and a respective portion of the second charge storage structures; and wherein no control gates are interposed between the first (255 1, 455 2) and the second semiconductor structures (255 2, 455 2). first (255 1, 455 2) and second (255 2, 455 2) substantially vertical, adjacent semiconductor structures, wherein the first (255 1, 455 2) and the second (255 2, 455 2) semiconductor structures each comprise a sidewall having a curved surface; first and second charge storage structures, wherein the first charge storage structures is adjacent to the first semiconductor structure (255 1, 455 2) and wraps at least partially around the curved surface of the sidewall of the first semiconductor structure (255 1, 455 2), and wherein the second charge storage structures is adjacent to the second semiconductor structure (255 2, 455 2) and wraps at least partially around the curved surface of the sidewall of the second semiconductor structure (255 2, 455 2); a plurality of first (265 2,1, 465 2,1) and second control gates (265 2,2, 465 2,2), wherein the first control gates (265 2,1, 465 2,1) are each adjacent to a respective portion of the first charge storage structures, and wherein the second control gates (265 2,2, 465 2,2) are each adjacent to a respective portion of the second charge storage structures; wherein each memory cell (272 1, 472 2,1) of a first serially-coupled string of memory cells (272 1, 472 2,1) comprises a respective one of the first control gates (265 2,1, 465 2,1) and a respective portion of the first charge storage structures; wherein each memory cell (272 2, 472 2,2) of a second serially-coupled string of memory cells (272 2, 472 2,2) comprises a respective one of the second control gates (265 2,2, 465 2,2) and a respective portion of the second charge storage structures; and wherein no control gates are interposed between the first (255 1, 455 2) and the second semiconductor structures (255 2, 455 2).