A memory array comprising a first bit line, a first word line, a first antifuse control line, a second antifuse control line and a first one time programming memory cell, wherein the first one time programming memory cell comprises: a first antifuse storing circuit including a first terminal connected with the first antifuse control line, a second terminal and a third terminal; a second antifuse storing circuit including a first terminal connected with the second antifuse control line, a second terminal connected with the second terminal of the first antifuse storing circuit and a third terminal; and a first selecting circuit (S1, S2) including four separate terminals, wherein a first terminal of the first selecting circuit (S1, S2) is connected with the first bit line, a second terminal of the first selecting circuit (S1, S2) is connected with the first word line, a third terminal of the first selecting circuit (S1, S2) is connected with the third terminal of the first antifuse storing circuit and a fourth terminal of the first selecting circuit (S1, S2) is connected with the third terminal of the second antifuse storing circuit; wherein during a program cycle, a select voltage is provided to the first word line, a ground voltage is provided to the first bit line, and a program voltage is provided to the first antifuse control line and the second antifuse control line, wherein the first selecting circuit (S1, S2) provides the ground voltage to the first antifuse storing circuit and the second antifuse storing circuit, and the program voltage is applied to both of the first antifuse storing circuit and the second antifuse storing circuit, so that a storing state of the first antifuse storing circuit or the second antifuse storing circuit is changed, wherein the storing states of the first and second antifuse storing circuits (A1, A2) are complementary to each other, wherein during a read cycle, the select voltage is provided to the first word line, the ground voltage is provided to the first bit line, a read voltage is provided to the first antifuse control line, and the ground voltage is provided to the second antifuse control line, so that the first antifuse storing circuit generates a first read current to the first bit line, wherein the first antifuse storing circuit is judged to have a first storing state or a second storing state according to the first read current, and one bit of a random code for a physically unclonable function technology is realized according to the first storing state or the second storing state of the first antifuse storing circuit. a first antifuse storing circuit including a first terminal connected with the first antifuse control line, a second terminal and a third terminal; a second antifuse storing circuit including a first terminal connected with the second antifuse control line, a second terminal connected with the second terminal of the first antifuse storing circuit and a third terminal; and a first selecting circuit (S1, S2) including four separate terminals, wherein a first terminal of the first selecting circuit (S1, S2) is connected with the first bit line, a second terminal of the first selecting circuit (S1, S2) is connected with the first word line, a third terminal of the first selecting circuit (S1, S2) is connected with the third terminal of the first antifuse storing circuit and a fourth terminal of the first selecting circuit (S1, S2) is connected with the third terminal of the second antifuse storing circuit; wherein during a program cycle, a select voltage is provided to the first word line, a ground voltage is provided to the first bit line, and a program voltage is provided to the first antifuse control line and the second antifuse control line, wherein the first selecting circuit (S1, S2) provides the ground voltage to the first antifuse storing circuit and the second antifuse storing circuit, and the program voltage is applied to both of the first antifuse storing circuit and the second antifuse storing circuit, so that a storing state of the first antifuse storing circuit or the second antifuse storing circuit is changed, wherein the storing states of the first and second antifuse storing circuits (A1, A2) are complementary to each other, wherein during a read cycle, the select voltage is provided to the first word line, the ground voltage is provided to the first bit line, a read voltage is provided to the first antifuse control line, and the ground voltage is provided to the second antifuse control line, so that the first antifuse storing circuit generates a first read current to the first bit line, wherein the first antifuse storing circuit is judged to have a first storing state or a second storing state according to the first read current, and one bit of a random code for a physically unclonable function technology is realized according to the first storing state or the second storing state of the first antifuse storing circuit.