A variable π-attenuator, wherein each of the two shunt circuits of the π-attenuator is a switching circuit including a first switch (4, 6, 17, 20) connected in parallel with a circuit element and a second switch (5, 7, 15, 18) connected in series with a parallel circuit constituted by the circuit element and the first switch (4, 6, 17, 20), wherein the first switch (4, 6, 17, 20) and the second switch (5, 7, 15, 18) alternately perform on-off operation so that in a first state, the second switch (5, 7, 15, 18) is on and the first switch (4, 6, 17, 20) is off, and in a second state, the second switch (5, 7, 15, 18) is off and the first switch (4, 6, 17, 20) is on, and the second switch (5, 7, 15, 18) has a parasitic capacitance or a parasitic inductance set in such a way that a parasitic capacitance or correspondingly a parasitic inductance occurring at the parallel circuit in a first state in which the first switch (4, 6, 17, 20) is controlled to be off and the second switch (5, 7, 15, 18) is controlled to be on and a parasitic capacitance or correspondingly a parasitic inductance occurring at the second switch (5, 7, 15, 18) in a second state in which the first switch (4, 6, 17, 20) is controlled to be on and the second switch (5, 7, 15, 18) is controlled to be off are equal to each other; wherein the circuit element of the switching circuit is a resistor (13, 16, 19), and wherein the first switches (4, 6, 17, 20) of each of the switching circuits of the two shunts are controlled to be off in the first state and to be on in the second state, and the second switches (5, 7, 15, 18) of each of the switching circuits of the two shunts are controlled to be on in the first state and to be off in the second state. each of the two shunt circuits of the π-attenuator is a switching circuit including a first switch (4, 6, 17, 20) connected in parallel with a circuit element and a second switch (5, 7, 15, 18) connected in series with a parallel circuit constituted by the circuit element and the first switch (4, 6, 17, 20), wherein the first switch (4, 6, 17, 20) and the second switch (5, 7, 15, 18) alternately perform on-off operation so that in a first state, the second switch (5, 7, 15, 18) is on and the first switch (4, 6, 17, 20) is off, and in a second state, the second switch (5, 7, 15, 18) is off and the first switch (4, 6, 17, 20) is on, and the second switch (5, 7, 15, 18) has a parasitic capacitance or a parasitic inductance set in such a way that a parasitic capacitance or correspondingly a parasitic inductance occurring at the parallel circuit in a first state in which the first switch (4, 6, 17, 20) is controlled to be off and the second switch (5, 7, 15, 18) is controlled to be on and a parasitic capacitance or correspondingly a parasitic inductance occurring at the second switch (5, 7, 15, 18) in a second state in which the first switch (4, 6, 17, 20) is controlled to be on and the second switch (5, 7, 15, 18) is controlled to be off are equal to each other; wherein the circuit element of the switching circuit is a resistor (13, 16, 19), and wherein the first switches (4, 6, 17, 20) of each of the switching circuits of the two shunts are controlled to be off in the first state and to be on in the second state, and the second switches (5, 7, 15, 18) of each of the switching circuits of the two shunts are controlled to be on in the first state and to be off in the second state.