A capacitive fingerprint sensor, comprising: a first electrode plate layer, a second electrode plate layer and a third electrode plate layer that are sequentially arranged, wherein the second electrode plate layer includes a second metal electrode, and the third electrode plate layer includes a third metal electrode; wherein the first electrode plate layer forms a fingerprint capacitor (C f) with a finger, at least one fourth electrode plate layer is arranged between the first electrode plate layer and the second electrode plate layer, a first parasitic capacitor (C 1/p1') is formed between the first electrode plate layer and the fourth electrode plate layer, and a second parasitic capacitor (C 2/p5') is formed between the second metal electrode and the fourth electrode plate layer; an integrator having an integrating capacitor (C i) and an amplifier and being configured to perform integration for charges from the fingerprint capacitor (C f), and the integrating capacitor (C i) is configured to store charges from the fingerprint capacitor (C f) and is formed between the second metal electrode and the third electrode plate layer, wherein the third metal electrode is connected to a negative input terminal of the amplifier and wherein the second metal electrode is connected to an output voltage (Vo) of the amplifier so that the second parasitic capacitor (C 2/p5') have no impact on the integrating capacitor (Ci); a first switch circuit, wherein the first switch circuit is configured to cause, via a switch-on or switch-off action, a voltage of the fourth electrode plate layer to be a power-supply voltage (Vc) or a common-mode voltage (Vm); and a second switch circuit, wherein the second switch circuit is configured to cause, via a switch-on or switch-off action, the voltage of the first electrode plate layer to be the power-supply voltage (Vc) or the common-mode voltage (Vm), wherein when the first electrode plate layer and the fourth electrode plate layer are both connected to the power-supply voltage (Vc) or both connected to the common-mode voltage (Vm), the first parasitic capacitor (C 1/p1') has no impact on the integrating capacitor (Ci). a first electrode plate layer, a second electrode plate layer and a third electrode plate layer that are sequentially arranged, wherein the second electrode plate layer includes a second metal electrode, and the third electrode plate layer includes a third metal electrode; wherein the first electrode plate layer forms a fingerprint capacitor (C f) with a finger, at least one fourth electrode plate layer is arranged between the first electrode plate layer and the second electrode plate layer, a first parasitic capacitor (C 1/p1') is formed between the first electrode plate layer and the fourth electrode plate layer, and a second parasitic capacitor (C 2/p5') is formed between the second metal electrode and the fourth electrode plate layer; an integrator having an integrating capacitor (C i) and an amplifier and being configured to perform integration for charges from the fingerprint capacitor (C f), and the integrating capacitor (C i) is configured to store charges from the fingerprint capacitor (C f) and is formed between the second metal electrode and the third electrode plate layer, wherein the third metal electrode is connected to a negative input terminal of the amplifier and wherein the second metal electrode is connected to an output voltage (Vo) of the amplifier so that the second parasitic capacitor (C 2/p5') have no impact on the integrating capacitor (Ci); a first switch circuit, wherein the first switch circuit is configured to cause, via a switch-on or switch-off action, a voltage of the fourth electrode plate layer to be a power-supply voltage (Vc) or a common-mode voltage (Vm); and a second switch circuit, wherein the second switch circuit is configured to cause, via a switch-on or switch-off action, the voltage of the first electrode plate layer to be the power-supply voltage (Vc) or the common-mode voltage (Vm), wherein when the first electrode plate layer and the fourth electrode plate layer are both connected to the power-supply voltage (Vc) or both connected to the common-mode voltage (Vm), the first parasitic capacitor (C 1/p1') has no impact on the integrating capacitor (Ci).