A phase interpolator, comprising: a pair of load resistors (R1,R2) coupled to a supply voltage (V DD) and including a first load resistor and a second load resistor; a plurality of branches (310,320,330,340) coupled to the pair of load resistors, each branch including a differential pair of source-coupled transistors including a first transistor (M1,M3,M5,M7) and a second transistor, (M2,M4,M6,M8) the first transistor receiving a first differential input signal at a first gate terminal and the second transistor receiving a second differential input signal complementary in phase to the first differential input signal at a second gate terminal, the first transistor also having a first drain terminal and a first source terminal and the second transistor also having a second drain terminal and a second source terminal, the first source terminal connected to the second source terminal to form a source node (S1,S2,S3,S4), the plurality of branches configured to produce a first differential output signal (OUTN) at a first output terminal and to produce a second differential output signal (OUTP) complementary to the first differential output signal at a second output terminal, wherein the first output terminal is connected to the first load resistor and the first drain terminal and the second output terminal is connected to the second load resistor and the second drain terminal; a plurality of tail current sources (I CC1,I CC2,I CC3,I CC4), each tail current source coupled to one of the source nodes; characterized by a plurality of coupling capacitors (C CC1-2,C CC2-3,C CC3-4,C CC4-1), each coupling capacitor is directly coupled between the source nodes in two adjacent branches of the plurality of branches whereby each source node is coupled to source nodes in two adjacent branches of the plurality of branches. a pair of load resistors (R1,R2) coupled to a supply voltage (V DD) and including a first load resistor and a second load resistor; a plurality of branches (310,320,330,340) coupled to the pair of load resistors, each branch including a differential pair of source-coupled transistors including a first transistor (M1,M3,M5,M7) and a second transistor, (M2,M4,M6,M8) the first transistor receiving a first differential input signal at a first gate terminal and the second transistor receiving a second differential input signal complementary in phase to the first differential input signal at a second gate terminal, the first transistor also having a first drain terminal and a first source terminal and the second transistor also having a second drain terminal and a second source terminal, the first source terminal connected to the second source terminal to form a source node (S1,S2,S3,S4), the plurality of branches configured to produce a first differential output signal (OUTN) at a first output terminal and to produce a second differential output signal (OUTP) complementary to the first differential output signal at a second output terminal, wherein the first output terminal is connected to the first load resistor and the first drain terminal and the second output terminal is connected to the second load resistor and the second drain terminal; a plurality of tail current sources (I CC1,I CC2,I CC3,I CC4), each tail current source coupled to one of the source nodes; characterized by a plurality of coupling capacitors (C CC1-2,C CC2-3,C CC3-4,C CC4-1), each coupling capacitor is directly coupled between the source nodes in two adjacent branches of the plurality of branches whereby each source node is coupled to source nodes in two adjacent branches of the plurality of branches.