A tunable coplanar capacitor, comprising: a substrate (103, 303, 403, 503); a layer of voltage-tunable dielectric (107, 307, 407, 507) over the substrate (103, 303, 403, 503); a plurality of bias lines (105A, 105B, 322A, 322B, 422, 522A, 522B) encapsulated between the substrate (103, 303, 403, 503) and the voltage-tunable dielectric (107, 307, 407, 507), wherein the plurality of bias lines (105A, 105B, 322A, 322B, 422, 522A, 522B) are spaced laterally apart; a first metal layer (109, 309, 409, 509) over the voltage-tunable dielectric (107, 307, 407, 507), wherein a plurality of first gaps are disposed in the first metal layer (109, 309, 409, 509), and wherein each of the plurality of first gaps is located at least partially above a respective one of the plurality of bias lines (105A, 105B, 322A, 322B, 422, 522A, 522B); an upper bias layer (112, 312, 412, 525) over the first metal layer (109, 309, 409, 509), wherein each of a plurality of portions of the upper bias layer (112, 312, 412, 525) extend through a respective one of the plurality of first gaps in the first metal layer (109, 309, 409, 509) to come into contact with the voltage-tunable dielectric (107, 307, 407, 507), and wherein at least a second gap is disposed in the upper bias layer (112, 312, 412, 525); and a second metal layer (113, 313, 413, 534), wherein a portion of the second metal layer (113, 313, 413, 534) extends through the second gap in the upper bias layer (112, 312, 412, 525) to come into contact with the first metal layer (109, 309, 409, 509); wherein a thickness of the voltage-tunable dielectric (107, 307, 407, 507) is smaller than a size of each of the plurality of first gaps; and wherein, when the tunable coplanar capacitor (101, 301, 401, 501) is in operation, an RF electric field and a DC biasing electric field are perpendicular and the DC biasing electric field is applied across the thickness of the voltage-tunable dielectric (107, 307, 407, 507). a substrate (103, 303, 403, 503); a layer of voltage-tunable dielectric (107, 307, 407, 507) over the substrate (103, 303, 403, 503); a plurality of bias lines (105A, 105B, 322A, 322B, 422, 522A, 522B) encapsulated between the substrate (103, 303, 403, 503) and the voltage-tunable dielectric (107, 307, 407, 507), wherein the plurality of bias lines (105A, 105B, 322A, 322B, 422, 522A, 522B) are spaced laterally apart; a first metal layer (109, 309, 409, 509) over the voltage-tunable dielectric (107, 307, 407, 507), wherein a plurality of first gaps are disposed in the first metal layer (109, 309, 409, 509), and wherein each of the plurality of first gaps is located at least partially above a respective one of the plurality of bias lines (105A, 105B, 322A, 322B, 422, 522A, 522B); an upper bias layer (112, 312, 412, 525) over the first metal layer (109, 309, 409, 509), wherein each of a plurality of portions of the upper bias layer (112, 312, 412, 525) extend through a respective one of the plurality of first gaps in the first metal layer (109, 309, 409, 509) to come into contact with the voltage-tunable dielectric (107, 307, 407, 507), and wherein at least a second gap is disposed in the upper bias layer (112, 312, 412, 525); and a second metal layer (113, 313, 413, 534), wherein a portion of the second metal layer (113, 313, 413, 534) extends through the second gap in the upper bias layer (112, 312, 412, 525) to come into contact with the first metal layer (109, 309, 409, 509); wherein a thickness of the voltage-tunable dielectric (107, 307, 407, 507) is smaller than a size of each of the plurality of first gaps; and wherein, when the tunable coplanar capacitor (101, 301, 401, 501) is in operation, an RF electric field and a DC biasing electric field are perpendicular and the DC biasing electric field is applied across the thickness of the voltage-tunable dielectric (107, 307, 407, 507).