A memory device, comprising: an array of memory cells (100, 400, 600); and control circuitry coupled to the array (100, 400, 600) having: a ramping sensing signal generator arranged to apply a sensing signal to a selected memory cell (111-1,..., 111-N) of the array of memory cells; a binary counter coupled to the ramping sensing signal generator, wherein the binary counter is configured to count incrementally corresponding to an increase in magnitude of the ramping sensing signal and provide a count while the sensing signal is applied to the selected memory cell (111-1,...,111-N), wherein the count comprises an n-bit value representing m-bits of hard data and p-bits of soft data, wherein m and p are each less than n, wherein bits of the count nominally representing a data state of the selected memory cell are referred to as hard data, and wherein remaining bits of the count are referred to as soft data; and logic having: an enable input,, the logic configured to control the count such that the count corresponds to the particular quantization of data, when enabled, for outputting the particular quantization of data, and to output the count when not enabled, wherein the particular quantization of data comprises the m-bit value representing the hard data, and a trim configured to adjust an incrementation of the count such that different hard data states correspond to different relative increments. an array of memory cells (100, 400, 600); and control circuitry coupled to the array (100, 400, 600) having: a ramping sensing signal generator arranged to apply a sensing signal to a selected memory cell (111-1,..., 111-N) of the array of memory cells; a binary counter coupled to the ramping sensing signal generator, wherein the binary counter is configured to count incrementally corresponding to an increase in magnitude of the ramping sensing signal and provide a count while the sensing signal is applied to the selected memory cell (111-1,...,111-N), wherein the count comprises an n-bit value representing m-bits of hard data and p-bits of soft data, wherein m and p are each less than n, wherein bits of the count nominally representing a data state of the selected memory cell are referred to as hard data, and wherein remaining bits of the count are referred to as soft data; and logic having: an enable input,, the logic configured to control the count such that the count corresponds to the particular quantization of data, when enabled, for outputting the particular quantization of data, and to output the count when not enabled, wherein the particular quantization of data comprises the m-bit value representing the hard data, and a trim configured to adjust an incrementation of the count such that different hard data states correspond to different relative increments. a ramping sensing signal generator arranged to apply a sensing signal to a selected memory cell (111-1,..., 111-N) of the array of memory cells; a binary counter coupled to the ramping sensing signal generator, wherein the binary counter is configured to count incrementally corresponding to an increase in magnitude of the ramping sensing signal and provide a count while the sensing signal is applied to the selected memory cell (111-1,...,111-N), wherein the count comprises an n-bit value representing m-bits of hard data and p-bits of soft data, wherein m and p are each less than n, wherein bits of the count nominally representing a data state of the selected memory cell are referred to as hard data, and wherein remaining bits of the count are referred to as soft data; and logic having: an enable input,, the logic configured to control the count such that the count corresponds to the particular quantization of data, when enabled, for outputting the particular quantization of data, and to output the count when not enabled, wherein the particular quantization of data comprises the m-bit value representing the hard data, and a trim configured to adjust an incrementation of the count such that different hard data states correspond to different relative increments. an enable input,, the logic configured to control the count such that the count corresponds to the particular quantization of data, when enabled, for outputting the particular quantization of data, and to output the count when not enabled, wherein the particular quantization of data comprises the m-bit value representing the hard data, and a trim configured to adjust an incrementation of the count such that different hard data states correspond to different relative increments.