A scan driving circuit, comprising: a first shift register connected to one group of clock signals having a first clock cycle (CLKA) and configured to output a first scanning signal, progressively, driven by the one group of clock signals; a second shift register connected to another group of clock signals having a second clock cycle (CLKB), and configured to output a second scanning signal, progressively, driven by the another group of clock signals; and a logic arithmetic device connected to a first clock signal having a third clock cycle, connected to the first shift register and the second shift register, and configured to output compensation signals of multiple rows; a compensation signal of any row has a wave shape the same as the first clock signal when a second scanning signal of a present row is at a first level, and has a wave shape the same as a first scanning signal of the present row when the second scanning signal of the present row is at a second level; and the third clock cycle is smaller than the second clock cycle, characterized in that corresponding to the compensation signal of any row, the logic arithmetic device comprises a first AND arithmetic unit, a second AND arithmetic unit, a NOT arithmetic unit and an OR arithmetic unit, the first AND arithmetic unit is connected to the first clock signal and the second shift register, and configured to perform logic AND arithmetic on the first clock signal and the second scanning signal of the present row (GB_N), to obtain a first arithmetic signal; the NOT arithmetic unit is connected to the second shift register, and configured to perform logic NOT arithmetic on the second scanning signal of the present row, to obtain a second arithmetic signal; the second AND arithmetic unit is connected to the NOT arithmetic unit and the first shift register, and configured to perform logic AND arithmetic on the first scanning signal of the present row (GA_N) and the second arithmetic signal from the NOT arithmetic unit, to obtain a third arithmetic signal; and the OR arithmetic unit is connected to the first AND arithmetic unit and the second AND arithmetic unit and is configured to perform logic OR arithmetic on the first arithmetic signal from the first AND arithmetic unit and the third arithmetic signal from the second AND arithmetic unit, to obtain the compensation signal of the present row (SC_N). a first shift register connected to one group of clock signals having a first clock cycle (CLKA) and configured to output a first scanning signal, progressively, driven by the one group of clock signals; a second shift register connected to another group of clock signals having a second clock cycle (CLKB), and configured to output a second scanning signal, progressively, driven by the another group of clock signals; and a logic arithmetic device connected to a first clock signal having a third clock cycle, connected to the first shift register and the second shift register, and configured to output compensation signals of multiple rows; a compensation signal of any row has a wave shape the same as the first clock signal when a second scanning signal of a present row is at a first level, and has a wave shape the same as a first scanning signal of the present row when the second scanning signal of the present row is at a second level; and the third clock cycle is smaller than the second clock cycle, characterized in that corresponding to the compensation signal of any row, the logic arithmetic device comprises a first AND arithmetic unit, a second AND arithmetic unit, a NOT arithmetic unit and an OR arithmetic unit, the first AND arithmetic unit is connected to the first clock signal and the second shift register, and configured to perform logic AND arithmetic on the first clock signal and the second scanning signal of the present row (GB_N), to obtain a first arithmetic signal; the NOT arithmetic unit is connected to the second shift register, and configured to perform logic NOT arithmetic on the second scanning signal of the present row, to obtain a second arithmetic signal; the second AND arithmetic unit is connected to the NOT arithmetic unit and the first shift register, and configured to perform logic AND arithmetic on the first scanning signal of the present row (GA_N) and the second arithmetic signal from the NOT arithmetic unit, to obtain a third arithmetic signal; and the OR arithmetic unit is connected to the first AND arithmetic unit and the second AND arithmetic unit and is configured to perform logic OR arithmetic on the first arithmetic signal from the first AND arithmetic unit and the third arithmetic signal from the second AND arithmetic unit, to obtain the compensation signal of the present row (SC_N).