A data latch circuit comprising: a first n-channel transistor; a second n-channel transistor connected in series to the first n-channel transistor; a first p-channel transistor; a second p-channel transistor; a first analog switch comprising a first control terminal and a second control terminal; a second analog switch comprising a first control terminal and a second control terminal; a third analog switch comprising a first control terminal and a second control terminal; and an inverter comprising an input terminal and an output terminal, wherein a gate electrode of the second n-channel transistor and a gate electrode of the first p-channel transistor are connected to each other so that the gate electrode of the second n-channel transistor and the gate electrode of the first p-channel transistor are arranged to receive a first control signal (SAMPB); wherein a first electrode of the first p-channel transistor and a first electrode of the second p-channel transistor are arranged to be connected to a first power source, wherein a first electrode of the second n-channel transistor is arranged to be connected to a second power source, wherein a second electrode of the second n-channel transistor is connected to a first electrode of the first n-channel transistor, wherein a second electrode of the first n-channel transistor, a second electrode of the first p-channel transistor, the input terminal of the inverter, and a second electrode of the second p-channel transistor are connected to each other, wherein one of input/output terminals of the second analog switch and one of input/output terminals of the third analog switch are connected to the output terminal of the inverter, wherein the other of the input/output terminals of the second analog switch and the other of the input/output terminals of the third analog switch are respectively connected to the gate electrode of the second p-channel transistor and the gate electrode of the first n-channel transistor, wherein the gate electrode of the first n-channel transistor is connected to one of input/output terminals of the first analog switch, wherein the other of the input/output terminals of the first analog switch is arranged to receive an input data signal, wherein the first analog switch is further arranged to receive the first control signal (SAMPB) at its first control terminal and a second control signal (SAMP) at its second control terminal, wherein each of the second analog switch and the third analog switch is further arranged to receive a third control signal (SAMP1) at its first control terminal and a fourth control signal (SAMP1 B) at its second control terminal, and wherein the data latch circuit is designed to receive an input signal whose amplitude is smaller than a potential difference between the first power source and the second power source. a first n-channel transistor; a second n-channel transistor connected in series to the first n-channel transistor; a first p-channel transistor; a second p-channel transistor; a first analog switch comprising a first control terminal and a second control terminal; a second analog switch comprising a first control terminal and a second control terminal; a third analog switch comprising a first control terminal and a second control terminal; and an inverter comprising an input terminal and an output terminal, wherein a gate electrode of the second n-channel transistor and a gate electrode of the first p-channel transistor are connected to each other so that the gate electrode of the second n-channel transistor and the gate electrode of the first p-channel transistor are arranged to receive a first control signal (SAMPB); wherein a first electrode of the first p-channel transistor and a first electrode of the second p-channel transistor are arranged to be connected to a first power source, wherein a first electrode of the second n-channel transistor is arranged to be connected to a second power source, wherein a second electrode of the second n-channel transistor is connected to a first electrode of the first n-channel transistor, wherein a second electrode of the first n-channel transistor, a second electrode of the first p-channel transistor, the input terminal of the inverter, and a second electrode of the second p-channel transistor are connected to each other, wherein one of input/output terminals of the second analog switch and one of input/output terminals of the third analog switch are connected to the output terminal of the inverter, wherein the other of the input/output terminals of the second analog switch and the other of the input/output terminals of the third analog switch are respectively connected to the gate electrode of the second p-channel transistor and the gate electrode of the first n-channel transistor, wherein the gate electrode of the first n-channel transistor is connected to one of input/output terminals of the first analog switch, wherein the other of the input/output terminals of the first analog switch is arranged to receive an input data signal, wherein the first analog switch is further arranged to receive the first control signal (SAMPB) at its first control terminal and a second control signal (SAMP) at its second control terminal, wherein each of the second analog switch and the third analog switch is further arranged to receive a third control signal (SAMP1) at its first control terminal and a fourth control signal (SAMP1 B) at its second control terminal, and wherein the data latch circuit is designed to receive an input signal whose amplitude is smaller than a potential difference between the first power source and the second power source.