A method for producing an interconnect structure on the back side of a semiconductor substrate portion of an integrated circuit chip, the interconnect structure being connected to the front side of said semiconductor substrate portion by means of at least one through-semiconductor via connection, the method comprising the steps of: - providing a substrate formed of a bulk semiconductor wafer, a blanket etch stop layer on the bulk semiconductor wafer, and a top semiconductor layer on the etch stop layer, wherein said semiconductor substrate portion of the IC chip is a portion of said top layer, - thereafter, etching at least one TSV-related via opening in the top semiconductor layer, stopping on the blanket etch stop layer that forms the bottom of the via opening, - thereafter, filling the etched via opening with a sacrificial material, thereby forming a pillar formed of the sacrificial material, - thereafter, producing a front end of line (FEOL) portion of the IC chip on the front side of the top semiconductor layer, wherein at least one electrically conductive structure (18,40) of the FEOL portion is in physical contact with the pillar, - thereafter, producing a back end of line (BEOL) portion of the IC chip on top of the FEOL portion, - thereafter, bonding the substrate with its front side to a carrier substrate, - thereafter, thinning the substrate by removing the bulk semiconductor wafer, the thinning step ending with an etch process that stops on the blanket etch stop layer, - thereafter, removing the blanket etch stop layer, - thereafter, removing the sacrificial material of the pillar in order to create an open cavity wherein said conductive structure (18,40) of the FEOL portion is exposed in said open cavity, - thereafter, filling the open cavity with an electrically conductive material, thereby creating a through semiconductor via connection from the front of the top semiconductor layer to the back thereof, - thereafter, producing said interconnect structure on the back side of the top semiconductor layer, the interconnect structure contacting the TSV connection. - providing a substrate formed of a bulk semiconductor wafer, a blanket etch stop layer on the bulk semiconductor wafer, and a top semiconductor layer on the etch stop layer, wherein said semiconductor substrate portion of the IC chip is a portion of said top layer, - thereafter, etching at least one TSV-related via opening in the top semiconductor layer, stopping on the blanket etch stop layer that forms the bottom of the via opening, - thereafter, filling the etched via opening with a sacrificial material, thereby forming a pillar formed of the sacrificial material, - thereafter, producing a front end of line (FEOL) portion of the IC chip on the front side of the top semiconductor layer, wherein at least one electrically conductive structure (18,40) of the FEOL portion is in physical contact with the pillar, - thereafter, producing a back end of line (BEOL) portion of the IC chip on top of the FEOL portion, - thereafter, bonding the substrate with its front side to a carrier substrate, - thereafter, thinning the substrate by removing the bulk semiconductor wafer, the thinning step ending with an etch process that stops on the blanket etch stop layer, - thereafter, removing the blanket etch stop layer, - thereafter, removing the sacrificial material of the pillar in order to create an open cavity wherein said conductive structure (18,40) of the FEOL portion is exposed in said open cavity, - thereafter, filling the open cavity with an electrically conductive material, thereby creating a through semiconductor via connection from the front of the top semiconductor layer to the back thereof, - thereafter, producing said interconnect structure on the back side of the top semiconductor layer, the interconnect structure contacting the TSV connection.