A package, comprising: - a package body with a package top side, a package footprint side and package sidewalls, the package sidewalls extending from the package footprint side to the package top side; - a plurality of controllable power semiconductor chips electrically connected in parallel to each other, each power semiconductor chip having a control terminal, a first load terminal and a second load terminal and being configured to block a blocking voltage applied between said load terminals (101, 102) and to conduct a chip load current between said load terminals (101, 102); - a lead frame structure for electrically and mechanically coupling the package to a carrier with the package footprint side facing to the carrier, the lead frame structure comprising a first load terminal bar and at least one first outside terminal, the at least one first outside terminal extending out of the package body for interfacing with the carrier and being electrically connected with each of the first load terminals of the plurality of power semiconductor chips by means of the first load terminal bar; wherein - the plurality of power semiconductor chips are arranged horizontally adjacent to each other along a first lateral direction in the package body; - the first load terminal bar extends along the first lateral direction so as to subsequently establish electrical contact with the first load terminals of the power semiconductor chips; - the package comprises a control terminal bar extending along the first lateral direction so as to subsequently establish electrical contact with the control terminals, the first load terminal bar and the control terminal bar are arranged adjacent to each other along a second lateral direction perpendicular to the first lateral direction; and - the package further comprises a plurality of first connecting members that connect the first load terminals of the power semiconductor chips with the first load terminal bar, characterized in that - the control terminal bar is arranged between the power semiconductor chips and the first load terminal bar, and wherein the first connecting members extend either below or above the control terminal bar so as to connect to the first load terminal bar. - a package body with a package top side, a package footprint side and package sidewalls, the package sidewalls extending from the package footprint side to the package top side; - a plurality of controllable power semiconductor chips electrically connected in parallel to each other, each power semiconductor chip having a control terminal, a first load terminal and a second load terminal and being configured to block a blocking voltage applied between said load terminals (101, 102) and to conduct a chip load current between said load terminals (101, 102); - a lead frame structure for electrically and mechanically coupling the package to a carrier with the package footprint side facing to the carrier, the lead frame structure comprising a first load terminal bar and at least one first outside terminal, the at least one first outside terminal extending out of the package body for interfacing with the carrier and being electrically connected with each of the first load terminals of the plurality of power semiconductor chips by means of the first load terminal bar; wherein - the plurality of power semiconductor chips are arranged horizontally adjacent to each other along a first lateral direction in the package body; - the first load terminal bar extends along the first lateral direction so as to subsequently establish electrical contact with the first load terminals of the power semiconductor chips; - the package comprises a control terminal bar extending along the first lateral direction so as to subsequently establish electrical contact with the control terminals, the first load terminal bar and the control terminal bar are arranged adjacent to each other along a second lateral direction perpendicular to the first lateral direction; and - the package further comprises a plurality of first connecting members that connect the first load terminals of the power semiconductor chips with the first load terminal bar, characterized in that - the control terminal bar is arranged between the power semiconductor chips and the first load terminal bar, and wherein the first connecting members extend either below or above the control terminal bar so as to connect to the first load terminal bar.