An instruction generation unit configured to interface a host computer to a specialized processor, the instruction generation unit comprising: an attribute stage configured to receive from the host computer a host-program operation code and a first virtual host-program operand, wherein the first virtual host-program operand represents a first operand for the specialized processor, and identify a first operand descriptor corresponding to the first virtual host-program operand, wherein the first operand descriptor provides a description of the first operand in terms of one or more operand attributes; a decode stage configured to receive from the attribute stage the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more translated instructions for execution by the specialized processor, and allocate storage locations, within the specialized processor, for use by the specialized processor in executing the translated instructions; an instruction buffer stage configured to receive the translated instruction from the decode stage, place the one or more translated instructions into one or more instruction queues, and issue translated instructions from at least one of the one or more instruction queues for execution by the specialized processor; and a memory configured to store an attribute table comprising one or more operand descriptors, and wherein the attribute stage is further configured to determine whether the host-program operation code corresponds to an initial declaration of the first operand; and in response to a determination that the host-program operation code does correspond to an initial declaration of the first operand, store in the attribute table an entry comprising the first operand descriptor, and return to the host computer an address of the stored attribute table entry. an attribute stage configured to receive from the host computer a host-program operation code and a first virtual host-program operand, wherein the first virtual host-program operand represents a first operand for the specialized processor, and identify a first operand descriptor corresponding to the first virtual host-program operand, wherein the first operand descriptor provides a description of the first operand in terms of one or more operand attributes; receive from the host computer a host-program operation code and a first virtual host-program operand, wherein the first virtual host-program operand represents a first operand for the specialized processor, and identify a first operand descriptor corresponding to the first virtual host-program operand, wherein the first operand descriptor provides a description of the first operand in terms of one or more operand attributes; a decode stage configured to receive from the attribute stage the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more translated instructions for execution by the specialized processor, and allocate storage locations, within the specialized processor, for use by the specialized processor in executing the translated instructions; receive from the attribute stage the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more translated instructions for execution by the specialized processor, and allocate storage locations, within the specialized processor, for use by the specialized processor in executing the translated instructions; an instruction buffer stage configured to receive the translated instruction from the decode stage, place the one or more translated instructions into one or more instruction queues, and issue translated instructions from at least one of the one or more instruction queues for execution by the specialized processor; and a memory configured to store an attribute table comprising one or more operand descriptors, and wherein the attribute stage is further configured to receive the translated instruction from the decode stage, place the one or more translated instructions into one or more instruction queues, and issue translated instructions from at least one of the one or more instruction queues for execution by the specialized processor; and a memory configured to store an attribute table comprising one or more operand descriptors, and wherein the attribute stage is further configured to determine whether the host-program operation code corresponds to an initial declaration of the first operand; and in response to a determination that the host-program operation code does correspond to an initial declaration of the first operand, store in the attribute table an entry comprising the first operand descriptor, and return to the host computer an address of the stored attribute table entry.