A silicon carbide power semiconductor device, comprising: a first silicon carbide layer having a first conductivity type; a source region in the first silicon carbide layer and having the first conductivity type, the source region having a higher carrier concentration than a carrier concentration of the first silicon carbide layer and extending to a first surface of the first silicon carbide layer; a buried region of silicon carbide of the second conductivity type in the first silicon carbide layer adjacent a bottom portion of the source region and at a depth in the first silicon carbide layer greater than a depth of the source region; a well region of silicon carbide of the second conductivity type in the first silicon carbide layer on a first side of the source region and extending toward, but not to, the first surface of the first silicon carbide layer, the well region having a lower carrier concentration than a carrier concentration of the buried region; a threshold adjustment region of silicon carbide of the first conductivity type in the first silicon carbide layer and extending from the source region and being disposed between the well region and the first surface of the first layer of silicon carbide; a plug region of silicon carbide of the second conductivity type on a second side of the source region opposite the first side of the source region and spaced apart from the well region of silicon carbide, the plug region of silicon carbide extending to the first face of the first silicon carbide layer and wherein a depth of the plug region in the first silicon carbide layer is less than a depth of the buried region of silicon carbide and sufficient to contact the buried region; a first silicon carbide epitaxial layer of the first conductivity type on the first surface of the first silicon carbide layer; and a gate oxide (24,54,64) on the first silicon carbide epitaxial layer, the well region and the source region; a gate contact on the gate oxide; a source contact on the plug region and the source region; and a drain contact on the first silicon carbide layer opposite the first surface of the first silicon carbide layer. a first silicon carbide layer having a first conductivity type; a source region in the first silicon carbide layer and having the first conductivity type, the source region having a higher carrier concentration than a carrier concentration of the first silicon carbide layer and extending to a first surface of the first silicon carbide layer; a buried region of silicon carbide of the second conductivity type in the first silicon carbide layer adjacent a bottom portion of the source region and at a depth in the first silicon carbide layer greater than a depth of the source region; a well region of silicon carbide of the second conductivity type in the first silicon carbide layer on a first side of the source region and extending toward, but not to, the first surface of the first silicon carbide layer, the well region having a lower carrier concentration than a carrier concentration of the buried region; a threshold adjustment region of silicon carbide of the first conductivity type in the first silicon carbide layer and extending from the source region and being disposed between the well region and the first surface of the first layer of silicon carbide; a plug region of silicon carbide of the second conductivity type on a second side of the source region opposite the first side of the source region and spaced apart from the well region of silicon carbide, the plug region of silicon carbide extending to the first face of the first silicon carbide layer and wherein a depth of the plug region in the first silicon carbide layer is less than a depth of the buried region of silicon carbide and sufficient to contact the buried region; a first silicon carbide epitaxial layer of the first conductivity type on the first surface of the first silicon carbide layer; and a gate oxide (24,54,64) on the first silicon carbide epitaxial layer, the well region and the source region; a gate contact on the gate oxide; a source contact on the plug region and the source region; and a drain contact on the first silicon carbide layer opposite the first surface of the first silicon carbide layer.