An endoscopic device comprising: a lumen; an imaging sensor disposed near the distal tip of said lumen; wherein said imaging sensor comprises: a plurality of substrates (310, 311) comprising at least a first substrate and a second substrate; a pixel array located on the first substrate and comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as one pixel in width and a plurality of pixels in length; a plurality of signal processing circuits located on the second substrate and comprising a plurality of circuit columns, where each of the plurality of circuit columns corresponds with a respective one of the plurality of pixel columns, wherein each of the plurality of circuit columns is defined as having an area that is the same as an area of a corresponding pixel column; a plurality of buses (330, 340), wherein there is one pixel column bus per one pixel column residing on the first substrate and one circuit column bus per one circuit column residing on said second substrate; wherein at least a portion of each of the pixel column buses is superimposed with at least a portion of each of the corresponding circuit column buses; and at least one interconnect providing electrical communication between one pixel column bus and one corresponding circuit column bus, wherein said at least one interconnect is located anywhere along the superimposed path of the pixel column bus and the corresponding circuit column bus. a lumen; an imaging sensor disposed near the distal tip of said lumen; wherein said imaging sensor comprises: a plurality of substrates (310, 311) comprising at least a first substrate and a second substrate; a pixel array located on the first substrate and comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as one pixel in width and a plurality of pixels in length; a plurality of signal processing circuits located on the second substrate and comprising a plurality of circuit columns, where each of the plurality of circuit columns corresponds with a respective one of the plurality of pixel columns, wherein each of the plurality of circuit columns is defined as having an area that is the same as an area of a corresponding pixel column; a plurality of buses (330, 340), wherein there is one pixel column bus per one pixel column residing on the first substrate and one circuit column bus per one circuit column residing on said second substrate; wherein at least a portion of each of the pixel column buses is superimposed with at least a portion of each of the corresponding circuit column buses; and at least one interconnect providing electrical communication between one pixel column bus and one corresponding circuit column bus, wherein said at least one interconnect is located anywhere along the superimposed path of the pixel column bus and the corresponding circuit column bus. a plurality of substrates (310, 311) comprising at least a first substrate and a second substrate; a pixel array located on the first substrate and comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as one pixel in width and a plurality of pixels in length; a plurality of signal processing circuits located on the second substrate and comprising a plurality of circuit columns, where each of the plurality of circuit columns corresponds with a respective one of the plurality of pixel columns, wherein each of the plurality of circuit columns is defined as having an area that is the same as an area of a corresponding pixel column; a plurality of buses (330, 340), wherein there is one pixel column bus per one pixel column residing on the first substrate and one circuit column bus per one circuit column residing on said second substrate; wherein at least a portion of each of the pixel column buses is superimposed with at least a portion of each of the corresponding circuit column buses; and at least one interconnect providing electrical communication between one pixel column bus and one corresponding circuit column bus, wherein said at least one interconnect is located anywhere along the superimposed path of the pixel column bus and the corresponding circuit column bus.