A reference voltage circuit with low temperature drift, comprising a first voltage unit, a second voltage unit and a K times' amplification unit; wherein, the first voltage unit is configured to generate a first voltage, a first end of the first voltage unit is grounded; the K times' amplification unit is configured to amplify the first voltage by K times, wherein K is a constant greater than zero; a first end of the K times' amplification unit is connected to a second end of the first voltage unit; a second end of the K times' amplification unit is connected to a first end of the second voltage unit,; the second voltage unit is configured to generate a second voltage; the first end of the second voltage unit is connected to a third end of the first voltage unit and to a current source circuit; a second end of the second voltage unit serves as an output end of a reference voltage; the first voltage unit comprises a first P-channel Metal-Oxide Semiconductor Field-Effect Transistor, PMOSFET, and a first N-channel Metal-Oxide Semiconductor Field-Effect Transistor, NMOSFET; the second voltage unit comprises a second NMOSFET and a third NMOSFET; the K times' amplification unit comprises a first resistor and a second resistor; wherein, a source of the second NMOSFET is connected to a drain of the third NMOSFET and serves as the output end of the reference voltage; a gate and a drain of the second NMOSFET are connected to the current source circuit; a gate of the third NMOSFET is connected to a gate and a drain of the first NMOSFET and to a drain of the first PMOSFET; a source of the third NMOSFET is grounded; a gate of the first PMOSFET is connected to a first end of the first resistor and a first end of the second resistor; a source of the first PMOSFET is connected to a second end of the first resistor and to the current source circuit; a source of the first NMOSFET is grounded; a second end of the second resistor is grounded. the first voltage unit is configured to generate a first voltage, a first end of the first voltage unit is grounded; the K times' amplification unit is configured to amplify the first voltage by K times, wherein K is a constant greater than zero; a first end of the K times' amplification unit is connected to a second end of the first voltage unit; a second end of the K times' amplification unit is connected to a first end of the second voltage unit,; the second voltage unit is configured to generate a second voltage; the first end of the second voltage unit is connected to a third end of the first voltage unit and to a current source circuit; a second end of the second voltage unit serves as an output end of a reference voltage; the first voltage unit comprises a first P-channel Metal-Oxide Semiconductor Field-Effect Transistor, PMOSFET, and a first N-channel Metal-Oxide Semiconductor Field-Effect Transistor, NMOSFET; the second voltage unit comprises a second NMOSFET and a third NMOSFET; the K times' amplification unit comprises a first resistor and a second resistor; wherein, a source of the second NMOSFET is connected to a drain of the third NMOSFET and serves as the output end of the reference voltage; a gate and a drain of the second NMOSFET are connected to the current source circuit; a gate of the third NMOSFET is connected to a gate and a drain of the first NMOSFET and to a drain of the first PMOSFET; a source of the third NMOSFET is grounded; a gate of the first PMOSFET is connected to a first end of the first resistor and a first end of the second resistor; a source of the first PMOSFET is connected to a second end of the first resistor and to the current source circuit; a source of the first NMOSFET is grounded; a second end of the second resistor is grounded.