An electronic device comprising a peripheral sensor interface 5 transceiver, the PSI5 transceiver comprising: a first NMOS transistor coupled between a first current-sensing node and a low voltage signal (VDD-LV), the first NMOS transistor being diode coupled; a first resistor coupled in series with a second NMOS transistor between a medium voltage signal (VDD-MV) and the low voltage signal, a gate of the second NMOS transistor being coupled to a gate of the first NMOS transistor; a second resistor coupled in series with a third NMOS transistor between the medium voltage signal and the low voltage signal, a gate of the third NMOS transistor being coupled to the first current-sensing node through a third resistor and an NMOS switching transistor, the NMOS switching transistor receiving a base current sampling signal (CtrlS) on a gate; a comparator having a non-inverting input coupled to a second current-sensing node between the first resistor and the second transistor, an inverting input coupled to a third current-sensing node between the second resistor and the third transistor, and an output coupled to a data output node; a base-current-renewal circuit having an input coupled to the data output node and an output coupled to provide the base current sampling signal, the base-current-renewal circuit comprising an idle-time counting circuit coupled to count a first number of clock cycles between edge transitions detected on the data output node and to set a first sampling signal high when the first number is greater than a second number of clock cycles that represents a defined gap time and an OR circuit having the first sampling signal as a first input, a second sampling signal as a second input, and an output coupled to provide the base current sampling signal, the second sampling signal being set high at a periodically scheduled time. a first NMOS transistor coupled between a first current-sensing node and a low voltage signal (VDD-LV), the first NMOS transistor being diode coupled; a first resistor coupled in series with a second NMOS transistor between a medium voltage signal (VDD-MV) and the low voltage signal, a gate of the second NMOS transistor being coupled to a gate of the first NMOS transistor; a second resistor coupled in series with a third NMOS transistor between the medium voltage signal and the low voltage signal, a gate of the third NMOS transistor being coupled to the first current-sensing node through a third resistor and an NMOS switching transistor, the NMOS switching transistor receiving a base current sampling signal (CtrlS) on a gate; a comparator having a non-inverting input coupled to a second current-sensing node between the first resistor and the second transistor, an inverting input coupled to a third current-sensing node between the second resistor and the third transistor, and an output coupled to a data output node; a base-current-renewal circuit having an input coupled to the data output node and an output coupled to provide the base current sampling signal, the base-current-renewal circuit comprising an idle-time counting circuit coupled to count a first number of clock cycles between edge transitions detected on the data output node and to set a first sampling signal high when the first number is greater than a second number of clock cycles that represents a defined gap time and an OR circuit having the first sampling signal as a first input, a second sampling signal as a second input, and an output coupled to provide the base current sampling signal, the second sampling signal being set high at a periodically scheduled time. an idle-time counting circuit coupled to count a first number of clock cycles between edge transitions detected on the data output node and to set a first sampling signal high when the first number is greater than a second number of clock cycles that represents a defined gap time and an OR circuit having the first sampling signal as a first input, a second sampling signal as a second input, and an output coupled to provide the base current sampling signal, the second sampling signal being set high at a periodically scheduled time.