Multi-level logic analyzer (100, 200, 300, 400) for analyzing multi-level digital signals (101, 102, 201, 202, 301, 302, 401, 402), the multi-level logic analyzer (100, 200, 300, 400) comprising: a plurality of signal inputs (103, 104, 203, 204, 303, 304, 403, 404), each signal input (103, 104, 203, 204, 303, 304, 403, 404) being configured to receive a multi-level digital signal (101, 102, 201, 202, 301, 302, 401, 402), a plurality of comparison units (105, 106, 205, 206, 305, 306, 405, 406), each comparison unit (105, 106, 205, 206, 305, 306, 405, 406) comprising a first comparator input (107, 108, 207, 208, 307, 308, 407, 408) and a second comparator input (109, 110, 209, 210, 309, 310, 409, 410) and being configured to compare a signal received at the first comparator input (107, 108, 207, 208, 307, 308, 407, 408) with a signal received at the second comparator input (109, 110, 209, 210, 309, 310, 409, 410), first switching means (113, 114, 213, 214, 313, 314, 413, 414) configured to couple at least one of the signal inputs (103, 104, 203, 204, 303, 304, 403, 404) with the first comparator inputs (107, 108, 207, 208, 307, 308, 407, 408) of at least two of the comparison units (105, 106, 205, 206, 305, 306, 405, 406), and a plurality of signal outputs (115, 116, 215, 216, 315, 316, 415, 416), each signal output (115, 116, 215, 216, 315, 316, 415, 416) being configured to output an output signal, the multi-level logic analyzer (100, 200, 300, 400) being characterized by further comprising second switching means (217, 317) configured to controllably couple comparison units (105, 106, 205, 206, 305, 306, 405, 406) that are coupled on their first comparison input with the same signal input (103, 104, 203, 204, 303, 304, 403, 404) on their output side with one of the signal outputs (115, 116, 215, 216, 315, 316, 415, 416). a plurality of signal inputs (103, 104, 203, 204, 303, 304, 403, 404), each signal input (103, 104, 203, 204, 303, 304, 403, 404) being configured to receive a multi-level digital signal (101, 102, 201, 202, 301, 302, 401, 402), a plurality of comparison units (105, 106, 205, 206, 305, 306, 405, 406), each comparison unit (105, 106, 205, 206, 305, 306, 405, 406) comprising a first comparator input (107, 108, 207, 208, 307, 308, 407, 408) and a second comparator input (109, 110, 209, 210, 309, 310, 409, 410) and being configured to compare a signal received at the first comparator input (107, 108, 207, 208, 307, 308, 407, 408) with a signal received at the second comparator input (109, 110, 209, 210, 309, 310, 409, 410), first switching means (113, 114, 213, 214, 313, 314, 413, 414) configured to couple at least one of the signal inputs (103, 104, 203, 204, 303, 304, 403, 404) with the first comparator inputs (107, 108, 207, 208, 307, 308, 407, 408) of at least two of the comparison units (105, 106, 205, 206, 305, 306, 405, 406), and a plurality of signal outputs (115, 116, 215, 216, 315, 316, 415, 416), each signal output (115, 116, 215, 216, 315, 316, 415, 416) being configured to output an output signal, the multi-level logic analyzer (100, 200, 300, 400) being characterized by further comprising second switching means (217, 317) configured to controllably couple comparison units (105, 106, 205, 206, 305, 306, 405, 406) that are coupled on their first comparison input with the same signal input (103, 104, 203, 204, 303, 304, 403, 404) on their output side with one of the signal outputs (115, 116, 215, 216, 315, 316, 415, 416).