A data processing device comprising: an encoder device; and a decoder device, wherein the encoder device comprises: a first encoder unit to generate an Error Correction Code, ECC (E0-E4) capable of single error correction and double error detection by performing operations according to a first ECC generation matrix; and a second encoder unit to generate an ECC (F0-F4) capable of the single error correction and double error detection by performing operations according to a second ECC generation matrix obtained by permutating, with respect to column number, part or all of the columns of the first ECC generation matrix, wherein the first encoder unit receives first data (D0-D7) to generate a first ECC (E0-E4) for the first data (D0-D7), wherein the second encoder unit receives second data (D7, D0-D6) obtained by permutating, with respect to bit position, part or all of the bits of the first data (D0-D7) so as to correspond to the permutation applied to the first ECC generation matrix, to generate a second ECC (F0-F4) for the second data (D7, D0-D6), wherein the encoder device stores the first data (D0-D7), the first ECC (E0-E4), and the second ECC (F0-F4) in a memory, wherein the number of columns and the number of rows of the first ECC generation matrix correspond to the number of bits comprised in the first data and the number of check bits of the first ECC, respectively, and wherein the decoder device determines a presence of errors in the first data (D0-D7) based on the first data (D0-D7) and the first ECC (E0-E4) read from the memory, determines a presence of errors in the second data (D7, D0-D6) based on the second data (D7, D0-D6) and the second ECC (F0-F4) read from the memory, and generates, based on the determination results, a notification signal indicating that there is either no error, a single-bit error or two or more-bit error of the first data. an encoder device; and a decoder device, wherein the encoder device comprises: a first encoder unit to generate an Error Correction Code, ECC (E0-E4) capable of single error correction and double error detection by performing operations according to a first ECC generation matrix; and a second encoder unit to generate an ECC (F0-F4) capable of the single error correction and double error detection by performing operations according to a second ECC generation matrix obtained by permutating, with respect to column number, part or all of the columns of the first ECC generation matrix, a first encoder unit to generate an Error Correction Code, ECC (E0-E4) capable of single error correction and double error detection by performing operations according to a first ECC generation matrix; and a second encoder unit to generate an ECC (F0-F4) capable of the single error correction and double error detection by performing operations according to a second ECC generation matrix obtained by permutating, with respect to column number, part or all of the columns of the first ECC generation matrix, wherein the first encoder unit receives first data (D0-D7) to generate a first ECC (E0-E4) for the first data (D0-D7), wherein the second encoder unit receives second data (D7, D0-D6) obtained by permutating, with respect to bit position, part or all of the bits of the first data (D0-D7) so as to correspond to the permutation applied to the first ECC generation matrix, to generate a second ECC (F0-F4) for the second data (D7, D0-D6), wherein the encoder device stores the first data (D0-D7), the first ECC (E0-E4), and the second ECC (F0-F4) in a memory, wherein the number of columns and the number of rows of the first ECC generation matrix correspond to the number of bits comprised in the first data and the number of check bits of the first ECC, respectively, and wherein the decoder device determines a presence of errors in the first data (D0-D7) based on the first data (D0-D7) and the first ECC (E0-E4) read from the memory, determines a presence of errors in the second data (D7, D0-D6) based on the second data (D7, D0-D6) and the second ECC (F0-F4) read from the memory, and generates, based on the determination results, a notification signal indicating that there is either no error, a single-bit error or two or more-bit error of the first data.