A pair of memory cells, comprising: a substrate of semiconductor material having a first conductivity type and a surface; a trench formed into the surface of the substrate and including a pair of opposing sidewalls; a first region formed in the substrate under the trench; a pair of second regions formed in the substrate, with a pair of channel regions each in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, said second conductivity type being opposite to said first conductivity type, and wherein each of the channel regions includes a first portion that extends along one of the opposing trench sidewalls and a second portion that extends along the substrate surface; a pair of electrically conductive floating gates each at least partially disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion, and over and insulated from the first region; an electrically conductive erase gate having a lower portion disposed in the trench and disposed adjacent to and insulated from the floating gates, wherein the erase gate includes a pair of notches and each of the floating gates includes an edge that directly faces and is insulated from one of the pair of notches, and wherein the erase gate includes an upper portion having a first width, and wherein the erase gate lower portion has a second width that is less than the first width, and wherein the pair of notches are disposed where the first and second portions of the erase gate meet, wherein the erase gate is for inducing tunneling of electrons from said edge of the floating gate to said notch of the erase gate; a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion, characterised in that said pair of memory cells further comprises an electrically conductive coupling gate disposed in the trench, disposed between and insulated from the floating gates, disposed over and insulated from the first region, and disposed under and insulated from the erase gate. a substrate of semiconductor material having a first conductivity type and a surface; a trench formed into the surface of the substrate and including a pair of opposing sidewalls; a first region formed in the substrate under the trench; a pair of second regions formed in the substrate, with a pair of channel regions each in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, said second conductivity type being opposite to said first conductivity type, and wherein each of the channel regions includes a first portion that extends along one of the opposing trench sidewalls and a second portion that extends along the substrate surface; a pair of electrically conductive floating gates each at least partially disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion, and over and insulated from the first region; an electrically conductive erase gate having a lower portion disposed in the trench and disposed adjacent to and insulated from the floating gates, wherein the erase gate includes a pair of notches and each of the floating gates includes an edge that directly faces and is insulated from one of the pair of notches, and wherein the erase gate includes an upper portion having a first width, and wherein the erase gate lower portion has a second width that is less than the first width, and wherein the pair of notches are disposed where the first and second portions of the erase gate meet, wherein the erase gate is for inducing tunneling of electrons from said edge of the floating gate to said notch of the erase gate; a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion, characterised in that said pair of memory cells further comprises an electrically conductive coupling gate disposed in the trench, disposed between and insulated from the floating gates, disposed over and insulated from the first region, and disposed under and insulated from the erase gate.