A memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element (106A, 202A, 802A) programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element (106B, 202B, 802B) programmable to store a second bit of data; wherein a physical characteristic of the first resistive element is different from a corresponding physical characteristic of the second resistive element resulting in said first resistive element having a first data retention duration, and said second resistive element having a second data retention duration different from said first data retention duration, the memory device being configured to receive a control signal indicating a retention duration for selecting one of the first and second resistive elements to store an input data value, said retention duration being associated with the input data value; and characterised in that: - said first and second memory cells are each coupled to read-write circuitry (810, 1010) allowing data to be read from and written to the first and second memory cells, the read-write circuitry comprising a comparator having an input coupled to a first bit line and an output coupled to a latch, the latch being coupled in turn to drive elements (816, 818), which have their outputs coupled respectively to the first bit line and to a second bit line, the latch receiving a data signal representing data to be stored to the first or second memory cell, and providing data read from one of the first and second memory cells; - the read-write circuitry (810, 1010) is configured to transfer data between said first and second memory cells; and - said first memory cell is coupled to said read-write circuitry via the first and a second bit line (806, 808), and said second memory cell is coupled to said read-write circuitry either via the first and second bit lines (806, 808), or via third and fourth bit lines (1006, 1008). a first memory cell comprising a first resistive non-volatile data storage element (106A, 202A, 802A) programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element (106B, 202B, 802B) programmable to store a second bit of data; wherein a physical characteristic of the first resistive element is different from a corresponding physical characteristic of the second resistive element resulting in said first resistive element having a first data retention duration, and said second resistive element having a second data retention duration different from said first data retention duration, the memory device being configured to receive a control signal indicating a retention duration for selecting one of the first and second resistive elements to store an input data value, said retention duration being associated with the input data value; and characterised in that: - said first and second memory cells are each coupled to read-write circuitry (810, 1010) allowing data to be read from and written to the first and second memory cells, the read-write circuitry comprising a comparator having an input coupled to a first bit line and an output coupled to a latch, the latch being coupled in turn to drive elements (816, 818), which have their outputs coupled respectively to the first bit line and to a second bit line, the latch receiving a data signal representing data to be stored to the first or second memory cell, and providing data read from one of the first and second memory cells; - the read-write circuitry (810, 1010) is configured to transfer data between said first and second memory cells; and - said first memory cell is coupled to said read-write circuitry via the first and a second bit line (806, 808), and said second memory cell is coupled to said read-write circuitry either via the first and second bit lines (806, 808), or via third and fourth bit lines (1006, 1008). - said first and second memory cells are each coupled to read-write circuitry (810, 1010) allowing data to be read from and written to the first and second memory cells, the read-write circuitry comprising a comparator having an input coupled to a first bit line and an output coupled to a latch, the latch being coupled in turn to drive elements (816, 818), which have their outputs coupled respectively to the first bit line and to a second bit line, the latch receiving a data signal representing data to be stored to the first or second memory cell, and providing data read from one of the first and second memory cells; - the read-write circuitry (810, 1010) is configured to transfer data between said first and second memory cells; and - said first memory cell is coupled to said read-write circuitry via the first and a second bit line (806, 808), and said second memory cell is coupled to said read-write circuitry either via the first and second bit lines (806, 808), or via third and fourth bit lines (1006, 1008).