A computer-implemented method to design, and optionally fabricate, a configurable accelerator framework arranged to implement a portion of a deep convolutional neural network, the configurable accelerator framework comprising a reconfigurable interconnect framework, the method comprising: accessing a configuration template directed toward the reconfigurable interconnect framework in said configurable accelerator framework; editing parameters of the configuration template, the editing including: editing a value of a first number of output ports of a reconfigurable stream switch in said configurable accelerator framework, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; editing a value of a second number of input ports of the reconfigurable stream switch in said configurable accelerator framework, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs; and editing default values of a set of control registers associated with the reconfigurable stream switch in said configurable accelerator framework, the set of control registers arranged for programming at run time, the set of control registers arranged to control a reconfigurable coupling of input ports and output ports; functionally combining the configuration template with a plurality of modules from an Intellectual Property library to produce a register transfer level, RTL, circuit model of said configurable accelerator framework; generating at least one automated test-bench function; and generating at least one logic synthesis script; wherein the method optionally comprises: fabricating the configurable accelerator framework. accessing a configuration template directed toward the reconfigurable interconnect framework in said configurable accelerator framework; editing parameters of the configuration template, the editing including: editing a value of a first number of output ports of a reconfigurable stream switch in said configurable accelerator framework, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; editing a value of a second number of input ports of the reconfigurable stream switch in said configurable accelerator framework, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs; and editing default values of a set of control registers associated with the reconfigurable stream switch in said configurable accelerator framework, the set of control registers arranged for programming at run time, the set of control registers arranged to control a reconfigurable coupling of input ports and output ports; editing a value of a first number of output ports of a reconfigurable stream switch in said configurable accelerator framework, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; editing a value of a second number of input ports of the reconfigurable stream switch in said configurable accelerator framework, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs; and editing default values of a set of control registers associated with the reconfigurable stream switch in said configurable accelerator framework, the set of control registers arranged for programming at run time, the set of control registers arranged to control a reconfigurable coupling of input ports and output ports; functionally combining the configuration template with a plurality of modules from an Intellectual Property library to produce a register transfer level, RTL, circuit model of said configurable accelerator framework; generating at least one automated test-bench function; and generating at least one logic synthesis script;