A shift register, comprising a signal writing circuit, a voltage control circuit, and an output circuit, the voltage control circuit and the output circuit being coupled to a first node, and the signal writing circuit, the voltage control circuit and the output circuit being coupled to a second node, wherein the signal writing circuit is configured to write an inverted signal of an input signal provided by a signal input terminal into the second node in response to a control of a second clock signal provided by a second clock signal terminal; the voltage control circuit comprises a first control circuit and a second control circuit, the first control circuit comprises a sixth transistor and a seventh transistor, a control electrode of the sixth transistor is coupled to the second node, a first electrode of the sixth transistor is coupled to the second clock signal terminal, and a second electrode of the sixth transistor is coupled to a third node, a control electrode of the seventh transistor is coupled to the second clock signal terminal, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to a second power supply terminal, the second control circuit comprises a first capacitor, an eighth transistor, a ninth transistor, and a tenth transistor, a first terminal of the first capacitor is coupled to a control electrode of the eighth transistor and the third node, and a second terminal of the first capacitor is coupled to the first electrode of the eighth transistor and a second electrode of the ninth transistor, a second electrode of the eighth transistor is coupled to a first clock signal terminal, a control electrode of the ninth transistor is coupled to the first clock signal terminal, and a first electrode of the ninth transistor is coupled to the first node, a control electrode of the tenth transistor is coupled to the second node, and a first electrode of the tenth transistor is 1 coupled to a first power supply terminal, the second power supply terminal supplies an active-level voltage, and the first power supply terminal supplies an inactive-level voltage; and the output circuit comprises a thirteenth transistor and a fourteenth transistor, a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to the second power supply terminal, and a second electrode of the thirteenth transistor is coupled to a signal output terminal, a control electrode of the fourteenth transistor is coupled to the second node, a first electrode of the fourteenth transistor is coupled to the signal output terminal, and a second electrode of the fourteenth transistor is coupled to the first power supply terminal. the signal writing circuit is configured to write an inverted signal of an input signal provided by a signal input terminal into the second node in response to a control of a second clock signal provided by a second clock signal terminal; the voltage control circuit comprises a first control circuit and a second control circuit, the first control circuit comprises a sixth transistor and a seventh transistor, a control electrode of the sixth transistor is coupled to the second node, a first electrode of the sixth transistor is coupled to the second clock signal terminal, and a second electrode of the sixth transistor is coupled to a third node, a control electrode of the seventh transistor is coupled to the second clock signal terminal, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to a second power supply terminal, the second control circuit comprises a first capacitor, an eighth transistor, a ninth transistor, and a tenth transistor, a first terminal of the first capacitor is coupled to a control electrode of the eighth transistor and the third node, and a second terminal of the first capacitor is coupled to the first electrode of the eighth transistor and a second electrode of the ninth transistor, a second electrode of the eighth transistor is coupled to a first clock signal terminal, a control electrode of the ninth transistor is coupled to the first clock signal terminal, and a first electrode of the ninth transistor is coupled to the first node, a control electrode of the tenth transistor is coupled to the second node, and a first electrode of the tenth transistor is 1 coupled to a first power supply terminal, the second power supply terminal supplies an active-level voltage, and the first power supply terminal supplies an inactive-level voltage; and the output circuit comprises a thirteenth transistor and a fourteenth transistor, a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to the second power supply terminal, and a second electrode of the thirteenth transistor is coupled to a signal output terminal, a control electrode of the fourteenth transistor is coupled to the second node, a first electrode of the fourteenth transistor is coupled to the signal output terminal, and a second electrode of the fourteenth transistor is coupled to the first power supply terminal.