A clock divider comprising: a first clock divider circuit (59a,59b) comprising: a first MOSFET transistor, wherein the gate of the first MOSFET transistor is coupled to a first input of the first clock divider circuit; a second MOSFET transistor coupled in parallel to the first MOSFET transistor, wherein the gate of the second MOSFET transistor is coupled to a second input of the first clock divider circuit; a third MOSFET transistor coupled in series with both the first MOSFET transistor and the second MOSFET transistor wherein the gate of the third MOSFET transistor is coupled to the first input of the first clock divider circuit; a fourth MOSFET transistor coupled in series with the third MOSFET transistor, wherein the gate of the fourth MOSFET transistor is coupled to the second input of the first clock divider circuit, wherein the first and the second MOSFET transistors, the third MOSFET transistor, and the fourth MOSFET transistor, are disposed in the recited order from Vcc to ground; and a node, between the third MOSFET transistor and the first and the second MOSFET transistors, for providing an output signal of the first clock divider circuit. a first clock divider circuit (59a,59b) comprising: a first MOSFET transistor, wherein the gate of the first MOSFET transistor is coupled to a first input of the first clock divider circuit; a second MOSFET transistor coupled in parallel to the first MOSFET transistor, wherein the gate of the second MOSFET transistor is coupled to a second input of the first clock divider circuit; a third MOSFET transistor coupled in series with both the first MOSFET transistor and the second MOSFET transistor wherein the gate of the third MOSFET transistor is coupled to the first input of the first clock divider circuit; a fourth MOSFET transistor coupled in series with the third MOSFET transistor, wherein the gate of the fourth MOSFET transistor is coupled to the second input of the first clock divider circuit, wherein the first and the second MOSFET transistors, the third MOSFET transistor, and the fourth MOSFET transistor, are disposed in the recited order from Vcc to ground; and a node, between the third MOSFET transistor and the first and the second MOSFET transistors, for providing an output signal of the first clock divider circuit. a first MOSFET transistor, wherein the gate of the first MOSFET transistor is coupled to a first input of the first clock divider circuit; a second MOSFET transistor coupled in parallel to the first MOSFET transistor, wherein the gate of the second MOSFET transistor is coupled to a second input of the first clock divider circuit; a third MOSFET transistor coupled in series with both the first MOSFET transistor and the second MOSFET transistor wherein the gate of the third MOSFET transistor is coupled to the first input of the first clock divider circuit; a fourth MOSFET transistor coupled in series with the third MOSFET transistor, wherein the gate of the fourth MOSFET transistor is coupled to the second input of the first clock divider circuit, wherein the first and the second MOSFET transistors, the third MOSFET transistor, and the fourth MOSFET transistor, are disposed in the recited order from Vcc to ground; and a node, between the third MOSFET transistor and the first and the second MOSFET transistors, for providing an output signal of the first clock divider circuit.