A three-level inverter, comprising: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, a second capacitor, a first diode, a second diode, an inductor, and a third capacitor, wherein: the first capacitor is connected in series with the second capacitor, the first capacitor and the second capacitor are connected in series between a positive terminal (+BUS) of a direct current bus and a negative terminal (-BUS) of the direct current bus, and the first capacitor and the second capacitor are connected to a fourth node; the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are in series connected in parallel to the first capacitor and the second capacitor; the first switching transistor and the second switching transistor are connected to a first node, the second switching transistor and the third switching transistor are connected to a second node, and the third switching transistor and the fourth switching transistor are connected to a third node; an anode of the first diode is connected to the fourth node, a cathode of the first diode is connected to the first node, a cathode of the second diode is connected to the fourth node, and an anode of the second diode is connected to the third node; the inductor is connected in series with the third capacitor between the second node and the fourth node, and the inductor and the third capacitor are connected to a fifth node; characterized in that a clamp circuit is connected in parallel between both ends of the third capacitor, wherein the clamp circuit comprises a first clamp thyristor and a second clamp thyristor, wherein an anode of the first clamp thyristor is connected with the fifth node, and a cathode of the first clamp thyristor is connected with the fourth node; a cathode of the second clamp thyristor is connected with the fifth node, and an anode of the second clamp thyristor is connected with the fourth node; and a controllable electrode of the first clamp thyristor and a controllable electrode of the second clamp thyristor each are configured to receive a drive signal; and in a positive half cycle of an output voltage of the inverter, the controllable electrode of the second clamp thyristor receives a drive signal which is enabled; in a negative half cycle of the output voltage, the controllable electrode of the first clamp thyristor receives a drive signal which is enabled, and the circuit is adapted, when a current of the inductor reaches a set protection threshold, current limitation begins and only the first switching transistor and the fourth switching transistor are turned off forcefully. the first capacitor is connected in series with the second capacitor, the first capacitor and the second capacitor are connected in series between a positive terminal (+BUS) of a direct current bus and a negative terminal (-BUS) of the direct current bus, and the first capacitor and the second capacitor are connected to a fourth node; the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are in series connected in parallel to the first capacitor and the second capacitor; the first switching transistor and the second switching transistor are connected to a first node, the second switching transistor and the third switching transistor are connected to a second node, and the third switching transistor and the fourth switching transistor are connected to a third node; an anode of the first diode is connected to the fourth node, a cathode of the first diode is connected to the first node, a cathode of the second diode is connected to the fourth node, and an anode of the second diode is connected to the third node; the inductor is connected in series with the third capacitor between the second node and the fourth node, and the inductor and the third capacitor are connected to a fifth node; characterized in that a clamp circuit is connected in parallel between both ends of the third capacitor, wherein the clamp circuit comprises a first clamp thyristor and a second clamp thyristor, wherein an anode of the first clamp thyristor is connected with the fifth node, and a cathode of the first clamp thyristor is connected with the fourth node; a cathode of the second clamp thyristor is connected with the fifth node, and an anode of the second clamp thyristor is connected with the fourth node; and a controllable electrode of the first clamp thyristor and a controllable electrode of the second clamp thyristor each are configured to receive a drive signal; and in a positive half cycle of an output voltage of the inverter, the controllable electrode of the second clamp thyristor receives a drive signal which is enabled; in a negative half cycle of the output voltage, the controllable electrode of the first clamp thyristor receives a drive signal which is enabled, and the circuit is adapted, when a current of the inductor reaches a set protection threshold, current limitation begins and only the first switching transistor and the fourth switching transistor are turned off forcefully.