A method for controlling memory system calibration, comprising: adjusting a data signal driver circuit to impair impedance matching on a data signal channel during a plurality of system-level memory tests; performing the plurality of system-level memory tests using a memory controller and a synchronous dynamic random access memory, SDRAM, each memory test corresponding to one of a plurality of phase skew values between a data strobe signal and a data signal on the data signal channel, each memory test comprising: setting a data strobe signal delay for the memory controller to correspond to one of the plurality of phase skew values; writing a plurality of data words to the SDRAM over the data signal channel; reading the plurality of data words from the SDRAM over the data signal channel; and determining an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM; determining, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and setting the data strobe signal delay for the memory controller to correspond to the optimal phase skew value. adjusting a data signal driver circuit to impair impedance matching on a data signal channel during a plurality of system-level memory tests; performing the plurality of system-level memory tests using a memory controller and a synchronous dynamic random access memory, SDRAM, each memory test corresponding to one of a plurality of phase skew values between a data strobe signal and a data signal on the data signal channel, each memory test comprising: setting a data strobe signal delay for the memory controller to correspond to one of the plurality of phase skew values; writing a plurality of data words to the SDRAM over the data signal channel; reading the plurality of data words from the SDRAM over the data signal channel; and determining an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM; determining, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and setting the data strobe signal delay for the memory controller to correspond to the optimal phase skew value. setting a data strobe signal delay for the memory controller to correspond to one of the plurality of phase skew values; writing a plurality of data words to the SDRAM over the data signal channel; reading the plurality of data words from the SDRAM over the data signal channel; and determining an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM; determining, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and setting the data strobe signal delay for the memory controller to correspond to the optimal phase skew value.