An analog neuromorphic memory system, comprising: a plurality of vector-by-matrix multiplication systems (2221, 2222, 2223, 2320), each vector-by-matrix multiplication system comprising: an array of memory cells, a low voltage row decoder for providing a bias voltage to one or more rows of memory cells in the array of memory cells during read and program operations and for providing a decoding signal; a high voltage row decoder for receiving the decoding signal and providing a high voltage bias signal to one or more rows of memory cells in the array of memory cells during program and erase operations; and a low voltage column decoder; a plurality of output blocks (2207, 2208, 2209), each output block providing an output in response to current received from at least one of the plurality of vector-by-matrix multiplication systems; and a shared high voltage generator block (2211, 3600) comprising a charge pump for outputting a high voltage and a charge pump regulator for receiving the high voltage from the charge pump and generating a trimmed high voltage in response to input trim bits, the shared high voltage generator block configured to concurrently provide voltages comprising one or more of the high voltage and the trimmed high voltage to the high voltage row decoder in each of the plurality of vector-by-matrix multiplication systems for one or more of erase operations and programming operations. a plurality of vector-by-matrix multiplication systems (2221, 2222, 2223, 2320), each vector-by-matrix multiplication system comprising: an array of memory cells, a low voltage row decoder for providing a bias voltage to one or more rows of memory cells in the array of memory cells during read and program operations and for providing a decoding signal; a high voltage row decoder for receiving the decoding signal and providing a high voltage bias signal to one or more rows of memory cells in the array of memory cells during program and erase operations; and a low voltage column decoder; an array of memory cells, a low voltage row decoder for providing a bias voltage to one or more rows of memory cells in the array of memory cells during read and program operations and for providing a decoding signal; a high voltage row decoder for receiving the decoding signal and providing a high voltage bias signal to one or more rows of memory cells in the array of memory cells during program and erase operations; and a low voltage column decoder; a plurality of output blocks (2207, 2208, 2209), each output block providing an output in response to current received from at least one of the plurality of vector-by-matrix multiplication systems; and a shared high voltage generator block (2211, 3600) comprising a charge pump for outputting a high voltage and a charge pump regulator for receiving the high voltage from the charge pump and generating a trimmed high voltage in response to input trim bits, the shared high voltage generator block configured to concurrently provide voltages comprising one or more of the high voltage and the trimmed high voltage to the high voltage row decoder in each of the plurality of vector-by-matrix multiplication systems for one or more of erase operations and programming operations.