A peripheral communication system comprising: a processor; a plurality of peripherals (18, 20, 22, 24, 26), connected to the processor; and a programmable peripheral interconnect, connected to each peripheral, wherein: at least one of the peripherals (18, 20, 22, 24, 26) is event-generating, being configured to signal an event to the programmable peripheral interconnect; at least one of the peripherals (18, 20, 22, 24) is task-receiving, being configured to respond to a task signal from the programmable peripheral interconnect by performing a task; and said task-receiving peripheral comprises a task register (32, 40, 42, 48, 50, 54), addressable by the processor, associated with the task, and is configured to perform the task in response to a change in the contents of the task register, characterised in that: the programmable peripheral interconnect is configured to access a memory in which a mapping can be stored between an event of a first peripheral and a task of a second peripheral, the mapping comprising (i) an identification of the event of the first peripheral, and (ii) the address of a task register associated with the task; and the programmable peripheral interconnect is configured so that, if a mapping is stored in memory between an event of a first peripheral and a task of a second peripheral, the interconnect will provide a channel by sending a task signal to the second peripheral in response to a signal of the event from the first peripheral. a processor; a plurality of peripherals (18, 20, 22, 24, 26), connected to the processor; and a programmable peripheral interconnect, connected to each peripheral, wherein: at least one of the peripherals (18, 20, 22, 24, 26) is event-generating, being configured to signal an event to the programmable peripheral interconnect; at least one of the peripherals (18, 20, 22, 24) is task-receiving, being configured to respond to a task signal from the programmable peripheral interconnect by performing a task; and said task-receiving peripheral comprises a task register (32, 40, 42, 48, 50, 54), addressable by the processor, associated with the task, and is configured to perform the task in response to a change in the contents of the task register, characterised in that: the programmable peripheral interconnect is configured to access a memory in which a mapping can be stored between an event of a first peripheral and a task of a second peripheral, the mapping comprising (i) an identification of the event of the first peripheral, and (ii) the address of a task register associated with the task; and the programmable peripheral interconnect is configured so that, if a mapping is stored in memory between an event of a first peripheral and a task of a second peripheral, the interconnect will provide a channel by sending a task signal to the second peripheral in response to a signal of the event from the first peripheral. at least one of the peripherals (18, 20, 22, 24, 26) is event-generating, being configured to signal an event to the programmable peripheral interconnect; at least one of the peripherals (18, 20, 22, 24) is task-receiving, being configured to respond to a task signal from the programmable peripheral interconnect by performing a task; and said task-receiving peripheral comprises a task register (32, 40, 42, 48, 50, 54), addressable by the processor, associated with the task, and is configured to perform the task in response to a change in the contents of the task register, characterised in that: the programmable peripheral interconnect is configured to access a memory in which a mapping can be stored between an event of a first peripheral and a task of a second peripheral, the mapping comprising (i) an identification of the event of the first peripheral, and (ii) the address of a task register associated with the task; and the programmable peripheral interconnect is configured so that, if a mapping is stored in memory between an event of a first peripheral and a task of a second peripheral, the interconnect will provide a channel by sending a task signal to the second peripheral in response to a signal of the event from the first peripheral. the programmable peripheral interconnect is configured to access a memory in which a mapping can be stored between an event of a first peripheral and a task of a second peripheral, the mapping comprising (i) an identification of the event of the first peripheral, and (ii) the address of a task register associated with the task; and the programmable peripheral interconnect is configured so that, if a mapping is stored in memory between an event of a first peripheral and a task of a second peripheral, the interconnect will provide a channel by sending a task signal to the second peripheral in response to a signal of the event from the first peripheral.