A memory structure comprising a memory element, said memory element comprising: a first terminal coupled to an N-doped region of said memory element; a second terminal coupled to a P-doped region of said memory element, wherein said N-doped region and P-doped region provide a polysilicon diode anti-fuse; and a silicide layer overlaying said N-doped region and P-doped region, wherein said silicide layer provides a poly fuse in parallel with said polysilicon diode anti-fuse, resulting in an initial programming state of said memory element; wherein said poly fuse provides a closed state in parallel with said polysilicon diode anti-fuse in said initial programming state, and wherein said memory element is configured to act as a short circuit between said first terminal and said second terminal in said initial programming state; said memory structure further comprises means adapted to apply a first current between said first terminal and said second terminal of said memory element, wherein said silicide layer is opened by said first current so that said memory element provides a first programming state different from said initial programming state, wherein a first impedance of said memory element in said first programming state is higher than an initial impedance of said memory element in said initial programming state, and wherein said polysilicon diode anti-fuse provides said first impedance of said memory element in said first programming state; characterized in that said means are further adapted to provide a high voltage between said first and second terminals of said memory element to set the polysilicon diode anti-fuse into a reversed biased state so that said memory element provides a second programming state different from said initial and first programming states, wherein a second impedance of said memory element in said second programming state is lower than said first impedance of said memory element in said first programming state; said polysilicon diode anti-fuse acts as a resistive element in said second programming state and provides said second impedance of said memory element; and said means are further adapted to provide a high current through a n-p junction formed by said N-doped region and P-doped region of said memory element, thereby opening the junction to act as an open circuit between said first terminal and said second terminal so that said memory element provides a third programming state different from said initial, first and second programming states, wherein a third impedance of said memory element in said third programming state is higher than said second impedance of said memory element in said second programming state. a first terminal coupled to an N-doped region of said memory element; a second terminal coupled to a P-doped region of said memory element, wherein said N-doped region and P-doped region provide a polysilicon diode anti-fuse; and a silicide layer overlaying said N-doped region and P-doped region, wherein said silicide layer provides a poly fuse in parallel with said polysilicon diode anti-fuse, resulting in an initial programming state of said memory element; wherein said poly fuse provides a closed state in parallel with said polysilicon diode anti-fuse in said initial programming state, and wherein said memory element is configured to act as a short circuit between said first terminal and said second terminal in said initial programming state; said memory structure further comprises means adapted to apply a first current between said first terminal and said second terminal of said memory element, wherein said silicide layer is opened by said first current so that said memory element provides a first programming state different from said initial programming state, wherein a first impedance of said memory element in said first programming state is higher than an initial impedance of said memory element in said initial programming state, and wherein said polysilicon diode anti-fuse provides said first impedance of said memory element in said first programming state; characterized in that said means are further adapted to provide a high voltage between said first and second terminals of said memory element to set the polysilicon diode anti-fuse into a reversed biased state so that said memory element provides a second programming state different from said initial and first programming states, wherein a second impedance of said memory element in said second programming state is lower than said first impedance of said memory element in said first programming state; said polysilicon diode anti-fuse acts as a resistive element in said second programming state and provides said second impedance of said memory element; and said means are further adapted to provide a high current through a n-p junction formed by said N-doped region and P-doped region of said memory element, thereby opening the junction to act as an open circuit between said first terminal and said second terminal so that said memory element provides a third programming state different from said initial, first and second programming states, wherein a third impedance of said memory element in said third programming state is higher than said second impedance of said memory element in said second programming state.