An emission signal control circuit for an organic light emitting display device, the EM signal control circuit comprising: a first transistor having a drain electrode coupled to a first emission power source (EVGH) and a gate electrode coupled to a first node, wherein the first transistor is configured to output a voltage of the first emission power source to an output node (N out) coupled to a source electrode thereof in response to a set signal; a second transistor having a source electrode coupled to a second emission power source (EVGL) and a gate electrode coupled to a second node, wherein the second transistor is configured to output a voltage of the second emission power source to the output node coupled to a drain electrode thereof in response to a reset signal; a fifth transistor having a source electrode coupled to a second gate power source and a drain electrode coupled to the second node, wherein the fifth transistor is configured to transfer the voltage of the second gate power source to the second node in response to the reset signal; a second capacitor coupled between the second node and the output node; the EM signal control circuit characterized by: a third transistor having a source electrode coupled to the second gate power source (GVGL) and a drain electrode coupled to the first node, wherein the third transistor is configured to transfer a voltage of the second gate power source to the first node in response to the set signal; a fourth transistor having a drain electrode coupled to a first gate power source (GVGH), a source electrode coupled to the first node and a gate electrode coupled to the second node, wherein the fourth transistor is configured to transfer a voltage of the first gate power source to the first node in response to the reset signal; and a first capacitor coupled between the first node and the drain electrode of the first transistor. a first transistor having a drain electrode coupled to a first emission power source (EVGH) and a gate electrode coupled to a first node, wherein the first transistor is configured to output a voltage of the first emission power source to an output node (N out) coupled to a source electrode thereof in response to a set signal; a second transistor having a source electrode coupled to a second emission power source (EVGL) and a gate electrode coupled to a second node, wherein the second transistor is configured to output a voltage of the second emission power source to the output node coupled to a drain electrode thereof in response to a reset signal; a fifth transistor having a source electrode coupled to a second gate power source and a drain electrode coupled to the second node, wherein the fifth transistor is configured to transfer the voltage of the second gate power source to the second node in response to the reset signal; a second capacitor coupled between the second node and the output node; the EM signal control circuit characterized by: a third transistor having a source electrode coupled to the second gate power source (GVGL) and a drain electrode coupled to the first node, wherein the third transistor is configured to transfer a voltage of the second gate power source to the first node in response to the set signal; a fourth transistor having a drain electrode coupled to a first gate power source (GVGH), a source electrode coupled to the first node and a gate electrode coupled to the second node, wherein the fourth transistor is configured to transfer a voltage of the first gate power source to the first node in response to the reset signal; and a first capacitor coupled between the first node and the drain electrode of the first transistor. a third transistor having a source electrode coupled to the second gate power source (GVGL) and a drain electrode coupled to the first node, wherein the third transistor is configured to transfer a voltage of the second gate power source to the first node in response to the set signal; a fourth transistor having a drain electrode coupled to a first gate power source (GVGH), a source electrode coupled to the first node and a gate electrode coupled to the second node, wherein the fourth transistor is configured to transfer a voltage of the first gate power source to the first node in response to the reset signal; and a first capacitor coupled between the first node and the drain electrode of the first transistor.