Two-stage operational amplifier in class AB for driving a load (R LB, R LA) comprising: - an input stage comprising differential input terminals (I N, I P) and a first differential output terminal and a second differential output terminal for providing a first differential driving signal (Out1P) and a second differential driving signal (Out1N), respectively; - an output stage comprising a first output branch having a first differential input terminal (I1P) operatively connected to the first differential output terminal of the input stage to receive the first differential driving signal (OUT1P) and a second output branch having a second differential input terminal (I1N) operatively connected to the second differential output terminal of the output stage to receive the second differential driving signal (Out1N), - a control circuit configured to control the output current (I OUTPB, I OUTPA) on the first output branch and the second output branch of the output stage, the control circuit comprising: - a first PMOS transistor (M BP2B) in a diode configuration and operatively connected in a current mirror configuration to a second PMOS transistor (M L2B) of the first output branch of the output stage, - a first NMOS transistor (M BNB) connected in series with the first PMOS transistor (M BP2B) and having a gate terminal connected to a bias voltage (V BN2), - a third PMOS transistor (M BP2A) in a diode configuration and operatively connected in a current mirror configuration to a fourth PMOS transistor (M L2A) of the second output branch of the output stage, - a second NMOS transistor (M BNA) connected in series with the third PMOS transistor (M BP2A) and having a gate terminal connected to the bias voltage (V BN2), - a third NMOS transistor (M N3B) operatively connected in parallel with the first NMOS transistor (M BNB) and having a gate terminal arranged to receive the second differential driving signal (Out1N), and - a fourth NMOS transistor (M N3A) operatively connected in parallel with the second NMOS transistor (M BNA) and having a gate terminal arranged to receive the first differential driving signal (Out1P), the operational amplifier further comprising: a reference NMOS transistor having a gate terminal connected to the bias voltage (V BN2), said reference NMOS transistor being connected with both the first NMOS transistor (M BNB) and the second NMOS transistor (M BNA) in a current mirror configuration. - an input stage comprising differential input terminals (I N, I P) and a first differential output terminal and a second differential output terminal for providing a first differential driving signal (Out1P) and a second differential driving signal (Out1N), respectively; - an output stage comprising a first output branch having a first differential input terminal (I1P) operatively connected to the first differential output terminal of the input stage to receive the first differential driving signal (OUT1P) and a second output branch having a second differential input terminal (I1N) operatively connected to the second differential output terminal of the output stage to receive the second differential driving signal (Out1N), - a control circuit configured to control the output current (I OUTPB, I OUTPA) on the first output branch and the second output branch of the output stage, the control circuit comprising: - a first PMOS transistor (M BP2B) in a diode configuration and operatively connected in a current mirror configuration to a second PMOS transistor (M L2B) of the first output branch of the output stage, - a first NMOS transistor (M BNB) connected in series with the first PMOS transistor (M BP2B) and having a gate terminal connected to a bias voltage (V BN2), - a third PMOS transistor (M BP2A) in a diode configuration and operatively connected in a current mirror configuration to a fourth PMOS transistor (M L2A) of the second output branch of the output stage, - a second NMOS transistor (M BNA) connected in series with the third PMOS transistor (M BP2A) and having a gate terminal connected to the bias voltage (V BN2), - a third NMOS transistor (M N3B) operatively connected in parallel with the first NMOS transistor (M BNB) and having a gate terminal arranged to receive the second differential driving signal (Out1N), and - a fourth NMOS transistor (M N3A) operatively connected in parallel with the second NMOS transistor (M BNA) and having a gate terminal arranged to receive the first differential driving signal (Out1P),