A data processing device comprising: an encoding unit configured to perform LDPC encoding in which a code length is 16200 bits and an encoding rate is 2/5, based on a parity check matrix of an LDPC code; and an interchanging unit configured to allocate code bits of the LDPC code to symbol bits of a symbol corresponding to any one of 16 signal points determined by 16QAM, wherein the LDPC code includes a plurality of information bits and a plurality of parity bits, wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, wherein the information matrix portion has dimension MxK and the parity matrix portion has dimension MxM, where M is a parity length and K is an information length, and K = 6480 and M = 9720; wherein the information matrix portion is represented by a parity check matrix initial value table, which shows in a j-th row, where 1 ≤ j ≤ 18, the positions of elements '1' in the (1+360x(j-1))-th column of the information matrix, and wherein based on each (1+360x(j-1)))-th column, where 1≤j≤18, columns (2+360x(j-1)) through of the information matrix are determined by cyclically shifting the respective preceding column in a downward direction by M/360, and is configured as follows, 5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658 5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016 3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931 4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254 4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963 9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134 1652 8171 1435 3366 6543 3745 9286 8509 4645 7397 5790 8972 6597 4422 1799 9276 4041 3847 8683 7378 4946 5348 1993 9186 6724 9015 5646 4502 4439 8474 5107 7342 9442 1387 8910 2660, and the parity matrix portion has a staircase structure in which elements of 1 are arranged in a staircase shape, where the row weight of the parity matrix portion is 1 with respect to the first row and 2 with respect to the remaining rows, and the column weight of the parity matrix portion is 1 with respect to the final column and 2 with respect to remaining columns; wherein 8 code bits that are stored in eight storage units each having a storage capacity of 16200/8 bits and are read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the interchanging unit sets the (#i + 1)-th code bit counted starting with the most significant bit of the 8 code bits as the bit b#i, 0≤i≤7, and the (#i + 1)-th symbol bit counted starting with the most significant bit of the 8 symbol bits of the two symbols as a bit y#i and allocates code bits b0, b1, b2, b3, b4, b5, b6, and b7 to symbol bits y7, y5, y4, y0, y3, y1, y2, and y6, respectively. an encoding unit configured to perform LDPC encoding in which a code length is 16200 bits and an encoding rate is 2/5, based on a parity check matrix of an LDPC code; and an interchanging unit configured to allocate code bits of the LDPC code to symbol bits of a symbol corresponding to any one of 16 signal points determined by 16QAM, wherein the LDPC code includes a plurality of information bits and a plurality of parity bits, wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, wherein the information matrix portion has dimension MxK and the parity matrix portion has dimension MxM, where M is a parity length and K is an information length, and K = 6480 and M = 9720; wherein the information matrix portion is represented by a parity check matrix initial value table, which shows in a j-th row, where 1 ≤ j ≤ 18, the positions of elements '1' in the (1+360x(j-1))-th column of the information matrix, and wherein based on each (1+360x(j-1)))-th column, where 1≤j≤18, columns (2+360x(j-1)) through of the information matrix are determined by cyclically shifting the respective preceding column in a downward direction by M/360, and is configured as follows, 5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658 5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016 3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931 4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254 4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963 9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134 1652 8171 1435 3366 6543 3745 9286 8509 4645 7397 5790 8972 6597 4422 1799 9276 4041 3847 8683 7378 4946 5348 1993 9186 6724 9015 5646 4502 4439 8474 5107 7342 9442 1387 8910 2660, and the parity matrix portion has a staircase structure in which elements of 1 are arranged in a staircase shape, where the row weight of the parity matrix portion is 1 with respect to the first row and 2 with respect to the remaining rows, and the column weight of the parity matrix portion is 1 with respect to the final column and 2 with respect to remaining columns; wherein 8 code bits that are stored in eight storage units each having a storage capacity of 16200/8 bits and are read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the interchanging unit sets the (#i + 1)-th code bit counted starting with the most significant bit of the 8 code bits as the bit b#i, 0≤i≤7, and the (#i + 1)-th symbol bit counted starting with the most significant bit of the 8 symbol bits of the two symbols as a bit y#i and allocates code bits b0, b1, b2, b3, b4, b5, b6, and b7 to symbol bits y7, y5, y4, y0, y3, y1, y2, and y6, respectively.