A non-volatile memory comprising: n data cells (1201; 1301; 1401) for storing an n-bit entry (1210; 1310; 1410), where a defective data cell of the n data cells is settable to a permanent logic state; at least two inversion status cells (1202a, 1202b; 1302a, 1302b; 1402a, 1402b, 1402c), each programmable between two states, where a first combination of logic states of the at least two inversion status cells together indicates that an inversion operation is to be performed on all the n data cells (1201; 1301; 1401) and a second combination of logic states of the at least two inversion status cells together indicates that an inversion operation is not to be performed on all the n data cells, a defective cell of the at least two inversion status cells being programmable to one of two permanent logic states, wherein the defective inversion status cell is a weak cell or leaky cell, and an operational cell of the at least two inversion status cells programmable to one of two logic states to achieve either the first or second combination of logic states; and an inversion processor (1222; 1322; 1422) coupled to the n data cells (1201; 1301; 1401) and the at least two inversion status cells (1202a, 1202b; 1302a; 1302b; 1402a, 1402b, 1402c), the inversion processor (1222; 1322; 1422) being configured to output either the n-bit entry or an inverse of the n-bit entry based on the first or the second combination of logic states of the at least two inversion status cells (1202a, 1202b; 1302a, 1302b; 1402a, 1402b, 1402c), the inversion processor (1222; 1322; 1422) including: first logic circuitry (1212; 1312; 1412) configured to receive logic states of the at least two inversion status cells and provide an inversion control signal, and second logic circuitry (1220; 1320; 1420) configured to receive logic states of the n-bit entry, and to invert the n-bit entry in response to the inversion control signal. n data cells (1201; 1301; 1401) for storing an n-bit entry (1210; 1310; 1410), where a defective data cell of the n data cells is settable to a permanent logic state; at least two inversion status cells (1202a, 1202b; 1302a, 1302b; 1402a, 1402b, 1402c), each programmable between two states, where a first combination of logic states of the at least two inversion status cells together indicates that an inversion operation is to be performed on all the n data cells (1201; 1301; 1401) and a second combination of logic states of the at least two inversion status cells together indicates that an inversion operation is not to be performed on all the n data cells, a defective cell of the at least two inversion status cells being programmable to one of two permanent logic states, wherein the defective inversion status cell is a weak cell or leaky cell, and an operational cell of the at least two inversion status cells programmable to one of two logic states to achieve either the first or second combination of logic states; and an inversion processor (1222; 1322; 1422) coupled to the n data cells (1201; 1301; 1401) and the at least two inversion status cells (1202a, 1202b; 1302a; 1302b; 1402a, 1402b, 1402c), the inversion processor (1222; 1322; 1422) being configured to output either the n-bit entry or an inverse of the n-bit entry based on the first or the second combination of logic states of the at least two inversion status cells (1202a, 1202b; 1302a, 1302b; 1402a, 1402b, 1402c), the inversion processor (1222; 1322; 1422) including: first logic circuitry (1212; 1312; 1412) configured to receive logic states of the at least two inversion status cells and provide an inversion control signal, and second logic circuitry (1220; 1320; 1420) configured to receive logic states of the n-bit entry, and to invert the n-bit entry in response to the inversion control signal. first logic circuitry (1212; 1312; 1412) configured to receive logic states of the at least two inversion status cells and provide an inversion control signal, and second logic circuitry (1220; 1320; 1420) configured to receive logic states of the n-bit entry, and to invert the n-bit entry in response to the inversion control signal.