A scan-type display device control circuit, suitable for receiving a plurality of successive frame data and driving a light-emitting diode display device accordingly, comprising: - a ping-pong buffer, comprising a first storage area and a second storage area; - a data storage controller, for receiving the frame data in sequence and storing the frame data in the first storage area or the second storage area alternately; - a line scan controller having an external clock signal input port for inputting an external clock signal, the line scan controller logically connected to the ping-pong buffer, for sequentially and circularly capturing a plurality of line data in the frame data from the first storage area or the second storage area; - a display buffer, logically connected to the line scan controller, for storing the line data; and - a scrambled pulse width modulation signal generating device, logically connected to the display buffer and the line scan controller, for capturing the line data and generating a scrambled PMW signal according to the line data, so as to drive the LED display device, wherein the scrambled PWM signal comprises a main signal and a compensation signal and the scrambled pulse width modulation comprises - a first counter for computing a first numerical signal; - a first comparator, having a first input end and a second input end, wherein the first input end is used to input first N most significant bits (MSBs) of the line data, the second input end is used to input the first numerical signal, and the first comparator outputs the main signal according to the first input end and the second input end; - a second counter for outputting a second numerical signal, wherein an output value of the second numerical signal changes every other sub-period; and - a second comparator, having a third input end and a fourth input end, wherein the third input end is used to input last L least significant bits (LSBs) of the line data, the fourth input end is used to input the second numerical signal, and the second comparator outputs the compensation signal according to the third end and the fourth input end; wherein the line data is M bits, after elapsing of a scan line changing period, the scrambled PWM signal generating device captures another line data and generates another scrambled PWM signal according to the other line data, wherein each frame data is corresponding to a frame to be displayed a number of times T per input frame, and wherein T is equal to the number of sub-period within the frame. - a ping-pong buffer, comprising a first storage area and a second storage area; - a data storage controller, for receiving the frame data in sequence and storing the frame data in the first storage area or the second storage area alternately; - a line scan controller having an external clock signal input port for inputting an external clock signal, the line scan controller logically connected to the ping-pong buffer, for sequentially and circularly capturing a plurality of line data in the frame data from the first storage area or the second storage area; - a display buffer, logically connected to the line scan controller, for storing the line data; and - a scrambled pulse width modulation signal generating device, logically connected to the display buffer and the line scan controller, for capturing the line data and generating a scrambled PMW signal according to the line data, so as to drive the LED display device, wherein the scrambled PWM signal comprises a main signal and a compensation signal and the scrambled pulse width modulation comprises - a first counter for computing a first numerical signal; - a first comparator, having a first input end and a second input end, wherein the first input end is used to input first N most significant bits (MSBs) of the line data, the second input end is used to input the first numerical signal, and the first comparator outputs the main signal according to the first input end and the second input end; - a second counter for outputting a second numerical signal, wherein an output value of the second numerical signal changes every other sub-period; and - a second comparator, having a third input end and a fourth input end, wherein the third input end is used to input last L least significant bits (LSBs) of the line data, the fourth input end is used to input the second numerical signal, and the second comparator outputs the compensation signal according to the third end and the fourth input end;