A decoder system that decodes a bi-phase modulated signal to generate an output code, wherein each bit-window of the bi-phase modulated signal represents a single logic bit with each bit-window beginning with a logic state transition, each bit having a first logic state represented by substantially constant logic state through the bit-window or a second logic state represented by additional logic state transition in the approximate center of the bit-window, the system comprising: a first filter associated with a first logic state configured to generate a first filter value of a plurality of consecutive digital samples of the bi-phase modulated signal relative to a respective plurality of tap weights of the first filter; a second filter associated with a second logic state configured to generate a second filter value of the plurality of consecutive digital samples of the bi-phase modulated signal relative to a respective plurality of tap weights of the second filter; and a comparator configured to compare the first and second filter values and to provide the output code as a bit having one of the first logic state and the second logic state based on the comparison, the system is characterized in that the plurality of tap weights of the first filter comprises a range of values that are greater than or equal to a reference value, and wherein the plurality of tap weights of the second filter comprises a first range of values corresponding to a first portion of the plurality of consecutive digital samples of the bi-phase modulated signal that are greater than the reference value and a second range of values corresponding to a second portion of the plurality of consecutive digital samples of the bi-phase modulated signal that are less than the reference value, the plurality of tap weights of each of the first and second filters being normalized. a first filter associated with a first logic state configured to generate a first filter value of a plurality of consecutive digital samples of the bi-phase modulated signal relative to a respective plurality of tap weights of the first filter; a second filter associated with a second logic state configured to generate a second filter value of the plurality of consecutive digital samples of the bi-phase modulated signal relative to a respective plurality of tap weights of the second filter; and a comparator configured to compare the first and second filter values and to provide the output code as a bit having one of the first logic state and the second logic state based on the comparison, the system is characterized in that the plurality of tap weights of the first filter comprises a range of values that are greater than or equal to a reference value, and wherein the plurality of tap weights of the second filter comprises a first range of values corresponding to a first portion of the plurality of consecutive digital samples of the bi-phase modulated signal that are greater than the reference value and a second range of values corresponding to a second portion of the plurality of consecutive digital samples of the bi-phase modulated signal that are less than the reference value, the plurality of tap weights of each of the first and second filters being normalized.