A non-volatile memory, NVM, bitcell (300, 400, 570), comprising: a first NVM one-time-write element (302, 402, 412, 502) directly coupled to a write bitline (322, 430, WBL0); a first write access transistor (306, 406, 506) coupling the first NVM one-time-write element (302, 402, 412, 502) to a ground, a gate of the first write access transistor (306, 406, 416, 506) coupled to a write wordline (316, 410, 420, WWL0); a first read access transistor (304, 404, 414, 504) directly coupled to the first NVM one-time-write element (302, 402, 412, 502) and directly coupled to a read bitline (324, 442, 444, RBL0), a gate of the first read access transistor (304, 404, 414, 504) coupled to a read wordline (314, 408, 418, RWL0); the NVM bitcell being characterised by further comprising: a second NVM one-time-write element (302, 402, 412, 502) coupled to the write bitline (322, 430, WBL0); a second write access transistor (306, 406, 506) coupling the second NVM one-time-write element (302, 402, 412, 502) to the ground, a gate of the second write access transistor (306, 406, 506) coupled to an odd write wordline (316, 410, 420, WWL0); and a second read access transistor (304, 404, 414, 504) coupling the second NVM one-time-write element (302, 402, 412, 502) to an odd read bitline (324, 442, 444, RBL0), a gate of the second read access transistor (304, 404, 414, 504) coupled to an odd read wordline (314, 408, 418, RWL0), in which the first NVM one-time-write element (302, 402, 412, 502) is coupled to an even read bitline (324, 442, 444, RBLO) and the gate of the first read access transistor (304, 404, 414, 504) is coupled to an even read wordline (314, 408, 418, RWL0). a first NVM one-time-write element (302, 402, 412, 502) directly coupled to a write bitline (322, 430, WBL0); a first write access transistor (306, 406, 506) coupling the first NVM one-time-write element (302, 402, 412, 502) to a ground, a gate of the first write access transistor (306, 406, 416, 506) coupled to a write wordline (316, 410, 420, WWL0); a first read access transistor (304, 404, 414, 504) directly coupled to the first NVM one-time-write element (302, 402, 412, 502) and directly coupled to a read bitline (324, 442, 444, RBL0), a gate of the first read access transistor (304, 404, 414, 504) coupled to a read wordline (314, 408, 418, RWL0); the NVM bitcell being characterised by further comprising: a second NVM one-time-write element (302, 402, 412, 502) coupled to the write bitline (322, 430, WBL0); a second write access transistor (306, 406, 506) coupling the second NVM one-time-write element (302, 402, 412, 502) to the ground, a gate of the second write access transistor (306, 406, 506) coupled to an odd write wordline (316, 410, 420, WWL0); and a second read access transistor (304, 404, 414, 504) coupling the second NVM one-time-write element (302, 402, 412, 502) to an odd read bitline (324, 442, 444, RBL0), a gate of the second read access transistor (304, 404, 414, 504) coupled to an odd read wordline (314, 408, 418, RWL0), a second NVM one-time-write element (302, 402, 412, 502) coupled to the write bitline (322, 430, WBL0); a second write access transistor (306, 406, 506) coupling the second NVM one-time-write element (302, 402, 412, 502) to the ground, a gate of the second write access transistor (306, 406, 506) coupled to an odd write wordline (316, 410, 420, WWL0); and a second read access transistor (304, 404, 414, 504) coupling the second NVM one-time-write element (302, 402, 412, 502) to an odd read bitline (324, 442, 444, RBL0), a gate of the second read access transistor (304, 404, 414, 504) coupled to an odd read wordline (314, 408, 418, RWL0), in which the first NVM one-time-write element (302, 402, 412, 502) is coupled to an even read bitline (324, 442, 444, RBLO) and the gate of the first read access transistor (304, 404, 414, 504) is coupled to an even read wordline (314, 408, 418, RWL0).