A multi-input-multi-output-system, MIMO, comprising: a first input signal and a second input signal; and a first analog-to-digital converter, ADC, cell structure (2, 44), a second ADC cell structure (2, 46) and a third ADC cell structure (2, 48), each configured to receive as input a combination of the first input signal and the second input signal, to thereby generate a noise quantization signal; wherein the MIMO is characterized in that the first ADC cell structure (2, 44) is configured to receive an addition of the first and second input signals (U1+U2) and an addition of the quantization noise signals generated by the second and third ADC cell structures (2, 46, 46), to thereby generate a first output signal (V1'); the second ADC cell structure (2, 46) is configured to receive a subtraction (U1-U2) of the second input signal from the first input signal and a subtraction (Q1-Q3) of the quantization noise signal generated by the third ADC cell structure (2, 48) from the quantization noise signal generated by the first ADC cell structure (2, 44), to thereby generate a second output signal (V2'); and the third ADC cell structure (2, 48) is configured to receive an addition (U1+U2) of the first and second input signals and a subtraction (Q1-Q2) of the quantization noise signal generated by the second ADC cell structure (2, 46) from the quantization noise signal generated by the first ADC cell structure (2, 44), to thereby generate a third output signal (V3'); wherein the MIMO further comprises: a first adder module that is configured to perform an addition of the first and second output signals (V1', V2'), to thereby generate a further first output signal; a second adder module that is configured to perform a subtraction of the second output signal (V2') from the third output signal (V3'), to thereby generate a further second output signal; a first division module that is configured to receive the further first output signal and perform a division operation on the further first output signal by a predetermined factor which is equal to two, to thereby generate a final first output signal of the MIMO; and a second division module that is configured to receive the further second output signal and perform a division operation on the further second output signal by the predetermined factor, to thereby generate a final second output signal of the MIMO. a first input signal and a second input signal; and a first analog-to-digital converter, ADC, cell structure (2, 44), a second ADC cell structure (2, 46) and a third ADC cell structure (2, 48), each configured to receive as input a combination of the first input signal and the second input signal, to thereby generate a noise quantization signal; wherein the MIMO is characterized in that the first ADC cell structure (2, 44) is configured to receive an addition of the first and second input signals (U1+U2) and an addition of the quantization noise signals generated by the second and third ADC cell structures (2, 46, 46), to thereby generate a first output signal (V1'); the second ADC cell structure (2, 46) is configured to receive a subtraction (U1-U2) of the second input signal from the first input signal and a subtraction (Q1-Q3) of the quantization noise signal generated by the third ADC cell structure (2, 48) from the quantization noise signal generated by the first ADC cell structure (2, 44), to thereby generate a second output signal (V2'); and the third ADC cell structure (2, 48) is configured to receive an addition (U1+U2) of the first and second input signals and a subtraction (Q1-Q2) of the quantization noise signal generated by the second ADC cell structure (2, 46) from the quantization noise signal generated by the first ADC cell structure (2, 44), to thereby generate a third output signal (V3'); wherein the MIMO further comprises: a first adder module that is configured to perform an addition of the first and second output signals (V1', V2'), to thereby generate a further first output signal; a second adder module that is configured to perform a subtraction of the second output signal (V2') from the third output signal (V3'), to thereby generate a further second output signal; a first division module that is configured to receive the further first output signal and perform a division operation on the further first output signal by a predetermined factor which is equal to two, to thereby generate a final first output signal of the MIMO; and a second division module that is configured to receive the further second output signal and perform a division operation on the further second output signal by the predetermined factor, to thereby generate a final second output signal of the MIMO.