A semiconductor device including: an n-type well region (201, 101), one surface of which is in contact with a p-type semiconductor layer; a p-type conductivity type well region in contact with the n-type well region and the p-type semiconductor layer and enclosing the n-type well region (201, 101), wherein the n-type well region is adapted for a potential higher than that of other regions partitioned off by the p-type well region; an n-type high concentration region provided in the n-type well region and having an impurity concentration higher than that of the n-type well region; a p-type high concentration region provided in the p-type well region and having an impurity concentration higher than that of the p-type well region; a resistive thin film layer provided across a dielectric on the other surface of the n-type well region; a first electrode (121, 125, 161) disposed so as to enclose the resistive thin film layer and connected to the p-type high concentration region; a second electrode (122, 162), connected to the n-type high concentration region; and a third electrode (120, 160, 170), disposed in an inner peripheral side of the first electrode and the resistive thin film layer, wherein the second electrode (122, 162) is connected to the positive electrode side of a bootstrap capacitor configuring a bootstrap circuit, the third electrode (120, 160, 170) is connected to the negative electrode side of the bootstrap capacitor, and the first electrode (121, 125, 161) is adapted to be grounded to a common potential (Gnd, COM); and wherein one end portion of the resistive thin film layer is connected to the first electrode (121, 125, 161), while the other end portion of the resistive thin film layer is connected to the third electrode (120, 160, 170), wherein the semiconductor device further comprises a high side drive circuit, connected to the second electrode (122, 162) and the third electrode (120, 160, 170), whereby the bootstrap capacitor is adapted to work as a power supply for the high side drive circuit; wherein the high side drive circuit and the negative electrode side of the bootstrap capacitor are adapted to be connected to an out terminal of an inverter, wherein the p-type semiconductor layer is adapted to be grounded to the common potential (Gnd, COM), wherein a driver circuit contained in the high side drive circuit is adapted to be connected to a gate of a semiconductor switching element contained in the inverter. an n-type well region (201, 101), one surface of which is in contact with a p-type semiconductor layer; a p-type conductivity type well region in contact with the n-type well region and the p-type semiconductor layer and enclosing the n-type well region (201, 101), wherein the n-type well region is adapted for a potential higher than that of other regions partitioned off by the p-type well region; an n-type high concentration region provided in the n-type well region and having an impurity concentration higher than that of the n-type well region; a p-type high concentration region provided in the p-type well region and having an impurity concentration higher than that of the p-type well region; a resistive thin film layer provided across a dielectric on the other surface of the n-type well region; a first electrode (121, 125, 161) disposed so as to enclose the resistive thin film layer and connected to the p-type high concentration region; a second electrode (122, 162), connected to the n-type high concentration region; and a third electrode (120, 160, 170), disposed in an inner peripheral side of the first electrode and the resistive thin film layer, wherein the second electrode (122, 162) is connected to the positive electrode side of a bootstrap capacitor configuring a bootstrap circuit, the third electrode (120, 160, 170) is connected to the negative electrode side of the bootstrap capacitor, and the first electrode (121, 125, 161) is adapted to be grounded to a common potential (Gnd, COM); and wherein one end portion of the resistive thin film layer is connected to the first electrode (121, 125, 161), while the other end portion of the resistive thin film layer is connected to the third electrode (120, 160, 170), wherein the semiconductor device further comprises a high side drive circuit, connected to the second electrode (122, 162) and the third electrode (120, 160, 170), whereby the bootstrap capacitor is adapted to work as a power supply for the high side drive circuit; wherein the high side drive circuit and the negative electrode side of the bootstrap capacitor are adapted to be connected to an out terminal of an inverter, wherein the p-type semiconductor layer is adapted to be grounded to the common potential (Gnd, COM), wherein a driver circuit contained in the high side drive circuit is adapted to be connected to a gate of a semiconductor switching element contained in the inverter.