A back contact structure of a solar cell, wherein the back contact structure comprises: a silicon substrate, the silicon substrate comprising a back surface comprising a plurality of recesses disposed at intervals; a first dielectric layer disposed directly on and entirely covering the bottom wall of the plurality of recesses, and being enclosed in the plurality of recesses; a plurality of P-type doped regions and a plurality of N-type doped regions disposed on the first dielectric layer and disposed alternately in the plurality of recesses a second dielectric layer disposed between the plurality of P-type doped regions and the plurality of N-type doped regions, wherein the second dielectric layer is at least one in number; and a conductive layer disposed on the plurality of P-type doped regions and the plurality of N-type doped regions respectively; wherein: a total thickness of the first dielectric layer and the plurality of P-type doped regions and a total thickness of the first dielectric layer and the plurality of N-type doped regions disposed in the plurality of recesses are less than a depth of the plurality of recesses, and the plurality of P-type doped regions and the plurality of N-type doped regions are enclosed inside the plurality of recesses; in each recess the first dielectric layer entirely covers and is directly on the side walls of the recesses except at an upper portion of the side walls, the portion of the side walls covered by the first dielectric layer having a height corresponding to the total thickness of the first dielectric layer and the corresponding doped region (30 and 40) respectively; in each recess the corresponding doped region (30 and 40) entirely covers and is directly on the first dielectric layer and fills the recess up to an height corresponding to the total thickness of the first dielectric layer and the corresponding doped region (30 and 40); the first dielectric layer corresponding to the P-type doped region is different from the first dielectric layer corresponding to the N-type doped region, and the second dielectric layer covers the regions between the recesses, extends to cover the upper portion of the side walls of the plurality of recesses which are not covered by the first dielectric layer, and further extends to partially cover the P-type doped regions and the N-type doped regions. a silicon substrate, the silicon substrate comprising a back surface comprising a plurality of recesses disposed at intervals; a first dielectric layer disposed directly on and entirely covering the bottom wall of the plurality of recesses, and being enclosed in the plurality of recesses; a plurality of P-type doped regions and a plurality of N-type doped regions disposed on the first dielectric layer and disposed alternately in the plurality of recesses a second dielectric layer disposed between the plurality of P-type doped regions and the plurality of N-type doped regions, wherein the second dielectric layer is at least one in number; and a conductive layer disposed on the plurality of P-type doped regions and the plurality of N-type doped regions respectively; a total thickness of the first dielectric layer and the plurality of P-type doped regions and a total thickness of the first dielectric layer and the plurality of N-type doped regions disposed in the plurality of recesses are less than a depth of the plurality of recesses, and the plurality of P-type doped regions and the plurality of N-type doped regions are enclosed inside the plurality of recesses; in each recess the first dielectric layer entirely covers and is directly on the side walls of the recesses except at an upper portion of the side walls, the portion of the side walls covered by the first dielectric layer having a height corresponding to the total thickness of the first dielectric layer and the corresponding doped region (30 and 40) respectively; in each recess the corresponding doped region (30 and 40) entirely covers and is directly on the first dielectric layer and fills the recess up to an height corresponding to the total thickness of the first dielectric layer and the corresponding doped region (30 and 40); the first dielectric layer corresponding to the P-type doped region is different from the first dielectric layer corresponding to the N-type doped region, and the second dielectric layer covers the regions between the recesses, extends to cover the upper portion of the side walls of the plurality of recesses which are not covered by the first dielectric layer, and further extends to partially cover the P-type doped regions and the N-type doped regions.