Phase-locked loop device comprising: - a phase comparator with a first comparator input intended for receiving a reference signal comprised of a reference cycle repeated at a reference frequency (F REF), a second comparator input for receiving a frequency-converted signal, and a comparator output adapted for producing an error signal representative of a phase time-shift existing between the reference signal and the frequency-converted signal; - a loop filter, with a filter input connected to the comparator output, and suitable for producing a control voltage (V tune) based on a time-filtering of the error signal at a filter output; - a voltage-controlled oscillator module, having a control input connected to the filter output, and a VCO output for producing a VCO signal having a VCO frequency (Fvco) varying as a function of the control voltage; - a frequency divider, connected at a divider input to the VCO output, and adapted for producing at a divider output the frequency-converted signal based on the VCO signal, said divider ouput being connected to the second comparator input (1 b); and - synchronization means (5, 50) arranged to control a stop in an operation of the frequency divider so that said stop is triggered by a signal transition occurring in one cycle of the frequency-converted signal, and allow said operation of the frequency divider to start again so that the frequency-converted signal is triggered at operation restart by a signal transition occurring in one later repetition of the reference cycle after the stop of the frequency divider operation, characterized in that the synchronization means (5, 50) comprise at least: - a first D-flipflop with a synchronization input connected for receiving the frequency-converted signal, a data input (51 b) connected to an upper-level voltage terminal, and an output; - a second D-flipflop with a synchronization input connected for receiving the reference signal, a data input connected to the output of the first D-flipflop, and an output; and - combination means with first input connected to the output (51 c) of the first D-flipflop, and second input connected for receiving a binary value derived at least partly from the output of the second D-flipflop, and said combination means being adapted for producing a combination signal containing a stop-controlling transition and then a restart-controlling transition, the stop-controlling transition corresponding to a binary value transition occurring at the output (51 c) of the first D-flipflop, and the restart-controlling transition corresponding to a transition in the binary value derived at least partly from the output of the second D-flipflop, and the synchronization means (5, 50) are arranged at output so that the combination signal controls the stop and the restart of the operation of the frequency divider. - a phase comparator with a first comparator input intended for receiving a reference signal comprised of a reference cycle repeated at a reference frequency (F REF), a second comparator input for receiving a frequency-converted signal, and a comparator output adapted for producing an error signal representative of a phase time-shift existing between the reference signal and the frequency-converted signal; - a loop filter, with a filter input connected to the comparator output, and suitable for producing a control voltage (V tune) based on a time-filtering of the error signal at a filter output; - a voltage-controlled oscillator module, having a control input connected to the filter output, and a VCO output for producing a VCO signal having a VCO frequency (Fvco) varying as a function of the control voltage; - a frequency divider, connected at a divider input to the VCO output, and adapted for producing at a divider output the frequency-converted signal based on the VCO signal, said divider ouput being connected to the second comparator input (1 b); and - synchronization means (5, 50) arranged to control a stop in an operation of the frequency divider so that said stop is triggered by a signal transition occurring in one cycle of the frequency-converted signal, and allow said operation of the frequency divider to start again so that the frequency-converted signal is triggered at operation restart by a signal transition occurring in one later repetition of the reference cycle after the stop of the frequency divider operation, characterized in that the synchronization means (5, 50) comprise at least: - a first D-flipflop with a synchronization input connected for receiving the frequency-converted signal, a data input (51 b) connected to an upper-level voltage terminal, and an output; - a second D-flipflop with a synchronization input connected for receiving the reference signal, a data input connected to the output of the first D-flipflop, and an output; and - combination means with first input connected to the output (51 c) of the first D-flipflop, and second input connected for receiving a binary value derived at least partly from the output of the second D-flipflop, and said combination means being adapted for producing a combination signal containing a stop-controlling transition and then a restart-controlling transition, the stop-controlling transition corresponding to a binary value transition occurring at the output (51 c) of the first D-flipflop, and the restart-controlling transition corresponding to a transition in the binary value derived at least partly from the output of the second D-flipflop, and the synchronization means (5, 50) are arranged at output so that the combination signal controls the stop and the restart of the operation of the frequency divider.