An apparatus, comprising: an array (130; 230) of memory cells; and a sense amplifier (206; 306; 606) coupled to the array of memory cells via a sense line (205; 305; 605); and a controller coupled to the array of memory cells, the controller being configured to: cause a first charge corresponding to a first operand of a logical operation to be stored to a plurality of memory cells coupled to the sense line (205; 305; 605); subsequent to storing the first operand to the plurality of memory cells, precharge the sense line to an equilibrate voltage via activation of equilibrate circuitry; subsequent to deactivation of the equilibrate circuitry, charge an access line (204-0,..., 204-7) for the plurality of the memory cells to a voltage greater than the equilibrate voltage to which the sense line (205; 305; 605) is precharged but less than the equilibrate voltage plus a threshold voltage of a memory cell access device; isolate the plurality of memory cells from the sense line (205; 305; 605); couple a memory cell storing a charge corresponding to a second operand of the logical operation to the sense line (205; 305; 605); and sense a voltage of the sense line (205; 305; 605), the sensed voltage indicating a result of the logical operation. an array (130; 230) of memory cells; and a sense amplifier (206; 306; 606) coupled to the array of memory cells via a sense line (205; 305; 605); and a controller coupled to the array of memory cells, the controller being configured to: cause a first charge corresponding to a first operand of a logical operation to be stored to a plurality of memory cells coupled to the sense line (205; 305; 605); subsequent to storing the first operand to the plurality of memory cells, precharge the sense line to an equilibrate voltage via activation of equilibrate circuitry; subsequent to deactivation of the equilibrate circuitry, charge an access line (204-0,..., 204-7) for the plurality of the memory cells to a voltage greater than the equilibrate voltage to which the sense line (205; 305; 605) is precharged but less than the equilibrate voltage plus a threshold voltage of a memory cell access device; isolate the plurality of memory cells from the sense line (205; 305; 605); couple a memory cell storing a charge corresponding to a second operand of the logical operation to the sense line (205; 305; 605); and sense a voltage of the sense line (205; 305; 605), the sensed voltage indicating a result of the logical operation. cause a first charge corresponding to a first operand of a logical operation to be stored to a plurality of memory cells coupled to the sense line (205; 305; 605); subsequent to storing the first operand to the plurality of memory cells, precharge the sense line to an equilibrate voltage via activation of equilibrate circuitry; subsequent to deactivation of the equilibrate circuitry, charge an access line (204-0,..., 204-7) for the plurality of the memory cells to a voltage greater than the equilibrate voltage to which the sense line (205; 305; 605) is precharged but less than the equilibrate voltage plus a threshold voltage of a memory cell access device; isolate the plurality of memory cells from the sense line (205; 305; 605); couple a memory cell storing a charge corresponding to a second operand of the logical operation to the sense line (205; 305; 605); and sense a voltage of the sense line (205; 305; 605), the sensed voltage indicating a result of the logical operation.