A display device comprising: a substrate; a first conductive layer including a lower pattern disposed over the substrate; a first insulating layer disposed over the first conductive layer; an active pattern (130a, 130b, 130c) disposed over the first insulating layer and including a source region (133a, 133b, 133c), a channel region (134a, 13b, 134c), and a drain region (135a, 135b, 135c); a second conductive layer disposed over the active pattern (130a, 130b, 130c) and including a gate electrode overlapping the channel region (134a, 13b, 134c) and a first capacitor electrode connected to the gate electrode; a second insulating layer disposed over the second conductive layer; a third conductive layer disposed over the second insulating layer and including a second capacitor electrode overlapping the first capacitor electrode, the third conductive layer further comprising a driving voltage line; a third insulating layer disposed over the third conductive layer; a fourth conductive layer disposed over the third insulating layer and including an third capacitor electrode overlapping the second capacitor electrode; a fourth insulating layer disposed over the fourth conductive layer; and a pixel electrode layer including a pixel electrode (191a, 191b, 191c) disposed over the fourth insulating layer, wherein the first capacitor electrode and the second capacitor electrode form a storage capacitor (Cst), the pixel electrode (191a, 191b, 191c) and the third capacitor electrode form a first additional capacitor (Ca), and the second capacitor electrode and the third capacitor electrode form a second additional capacitor (Cb). a substrate; a first conductive layer including a lower pattern disposed over the substrate; a first insulating layer disposed over the first conductive layer; an active pattern (130a, 130b, 130c) disposed over the first insulating layer and including a source region (133a, 133b, 133c), a channel region (134a, 13b, 134c), and a drain region (135a, 135b, 135c); a second conductive layer disposed over the active pattern (130a, 130b, 130c) and including a gate electrode overlapping the channel region (134a, 13b, 134c) and a first capacitor electrode connected to the gate electrode; a second insulating layer disposed over the second conductive layer; a third conductive layer disposed over the second insulating layer and including a second capacitor electrode overlapping the first capacitor electrode, the third conductive layer further comprising a driving voltage line; a third insulating layer disposed over the third conductive layer; a fourth conductive layer disposed over the third insulating layer and including an third capacitor electrode overlapping the second capacitor electrode; a fourth insulating layer disposed over the fourth conductive layer; and a pixel electrode layer including a pixel electrode (191a, 191b, 191c) disposed over the fourth insulating layer, wherein the first capacitor electrode and the second capacitor electrode form a storage capacitor (Cst), the pixel electrode (191a, 191b, 191c) and the third capacitor electrode form a first additional capacitor (Ca), and the second capacitor electrode and the third capacitor electrode form a second additional capacitor (Cb).