A transmitter circuit configured to generate a Single-Carrier Discrete Cosine Transform, SC-DCT, OFDM signal for transmission, said transmitter circuit comprising: a signal processing chain configured to map K u input subcarriers to N output subcarriers, according to the formula N = 2 S K u, wherein S indicates the integer number of DCT precoder stages included in series within the signal processing chain, wherein S ≥ 1, and wherein said signal processing chain includes a serial-to-parallel converter configured to generate the K u input subcarriers according to a series of information symbols to be transmitted, a prefix or padding circuit configured to add a cyclic prefix or a zero padding to the N output subcarriers, for input to a parallel-to-serial converter that is included in said signal processing chain and is configured to form the SC-DCT OFDM signal; and wherein said integer number of DCT precoder stages comprises one or more DCT precoder stages included in series within the signal processing chain between the serial-to-parallel converter and the prefix or padding circuit, each such stage i, where i=1, 2,..., S, configured to generate 2Mi output subcarriers from Mi input subcarriers, and to map the Mi input subcarriers to even-numbered or odd-numbered ones of the 2 Mi output subcarriers, in dependence on an even/odd shift control signal applied to the stage, and each such stage comprising a DCT circuit followed by an IDCT circuit, said 2Mi output subcarriers output by said IDCT circuit; and wherein a first one of the DCT precoder stages is configured to receive the K u subcarriers as its Mi input subcarriers, and a last one of the DCT precoder stages is configured to provide the N output subcarriers as its 2 Mi output subcarriers; and wherein at least one DCT precoder stage in the signal processing chain comprises a direct-mapping DCT precoder stage wherein the M i input subcarriers are a length- M i ordered sequence and wherein the IDCT circuit is configured to output the 2 M i output subcarriers as a length-2 M i output vector that includes the original ordered sequence interspersed with a time-reversed and mirrored version of the original ordered sequence, and wherein said direct-mapping DCT precoder stage is configured to negate or not negate the time-reversed mirrored version of the original ordered sequence included in the length-2 M i output vector, in dependence on the even/odd shift control signal applied to the direct-mapping DCT precoder stage. a signal processing chain configured to map K u input subcarriers to N output subcarriers, according to the formula N = 2 S K u, wherein S indicates the integer number of DCT precoder stages included in series within the signal processing chain, wherein S ≥ 1, and wherein said signal processing chain includes a serial-to-parallel converter configured to generate the K u input subcarriers according to a series of information symbols to be transmitted, a prefix or padding circuit configured to add a cyclic prefix or a zero padding to the N output subcarriers, for input to a parallel-to-serial converter that is included in said signal processing chain and is configured to form the SC-DCT OFDM signal; and wherein said integer number of DCT precoder stages comprises one or more DCT precoder stages included in series within the signal processing chain between the serial-to-parallel converter and the prefix or padding circuit, each such stage i, where i=1, 2,..., S, configured to generate 2Mi output subcarriers from Mi input subcarriers, and to map the Mi input subcarriers to even-numbered or odd-numbered ones of the 2 Mi output subcarriers, in dependence on an even/odd shift control signal applied to the stage, and each such stage comprising a DCT circuit followed by an IDCT circuit, said 2Mi output subcarriers output by said IDCT circuit; and wherein a first one of the DCT precoder stages is configured to receive the K u subcarriers as its Mi input subcarriers, and a last one of the DCT precoder stages is configured to provide the N output subcarriers as its 2 Mi output subcarriers; and wherein at least one DCT precoder stage in the signal processing chain comprises a direct-mapping DCT precoder stage wherein the M i input subcarriers are a length- M i ordered sequence and wherein the IDCT circuit is configured to output the 2 M i output subcarriers as a length-2 M i output vector that includes the original ordered sequence interspersed with a time-reversed and mirrored version of the original ordered sequence, and wherein said direct-mapping DCT precoder stage is configured to negate or not negate the time-reversed mirrored version of the original ordered sequence included in the length-2 M i output vector, in dependence on the even/odd shift control signal applied to the direct-mapping DCT precoder stage.