A memory device comprising: a memory cell array including normal memory cells (NMC1, NMC2) and redundant memory cells (RMC1, RMC2); first page buffers (PB0-PB11) connected to the normal memory cells (NMC1, NMC2) through first bit lines, the first bit lines divided into at least a first bit line group including a first plurality of bit lines and a second bit line group including a second plurality of bit lines, the first page buffers (PB0-PB11) divided into a first repair group corresponding to the first bit line group and a second repair group corresponding to the second bit line group, the first and second repair groups (RG1, RG2) arranged in a first area and collinear in a first direction, the first area corresponding to the first bit lines extending in the first direction; and second page buffers (PB0-PB11) connected to the redundant memory cells (RMC1, RMC2) through second bit lines divided into at least a third bit line group including a third plurality of bit lines and a fourth bit line group including a fourth plurality of bit lines, the second page buffers (PB0-PB11) divided into a third repair group corresponding to the third bit line group and a fourth repair group corresponding to the fourth bit line group, the third and fourth repair groups (RG3, RG4) arranged in a second area and collinear in the first direction, the second area corresponding to the second bit lines extending in the first direction, wherein the memory device is configured to, in response to at least one normal memory cell connected to the first bit line group being determined as a defective cell, replace normal memory cells connected to the first bit line group with redundant memory cells connected to the third bit line group, the replaced normal memory cells comprising at least the defective cell; said memory device being characterized in that the first repair group is above the second repair group in the first direction, the third repair group is above the fourth repair group in the first direction. a memory cell array including normal memory cells (NMC1, NMC2) and redundant memory cells (RMC1, RMC2); first page buffers (PB0-PB11) connected to the normal memory cells (NMC1, NMC2) through first bit lines, the first bit lines divided into at least a first bit line group including a first plurality of bit lines and a second bit line group including a second plurality of bit lines, the first page buffers (PB0-PB11) divided into a first repair group corresponding to the first bit line group and a second repair group corresponding to the second bit line group, the first and second repair groups (RG1, RG2) arranged in a first area and collinear in a first direction, the first area corresponding to the first bit lines extending in the first direction; and second page buffers (PB0-PB11) connected to the redundant memory cells (RMC1, RMC2) through second bit lines divided into at least a third bit line group including a third plurality of bit lines and a fourth bit line group including a fourth plurality of bit lines, the second page buffers (PB0-PB11) divided into a third repair group corresponding to the third bit line group and a fourth repair group corresponding to the fourth bit line group, the third and fourth repair groups (RG3, RG4) arranged in a second area and collinear in the first direction, the second area corresponding to the second bit lines extending in the first direction, wherein the memory device is configured to, in response to at least one normal memory cell connected to the first bit line group being determined as a defective cell, replace normal memory cells connected to the first bit line group with redundant memory cells connected to the third bit line group, the replaced normal memory cells comprising at least the defective cell; said memory device being characterized in that the first repair group is above the second repair group in the first direction, the third repair group is above the fourth repair group in the first direction.