A Low Density Parity Check (LDPC) encoder for encoding codewords using a lifted LDPC code with a lifting factor Z, comprising: a memory module including at least N x L x K storage locations, where N and L are positive integers and K is an integer >1, wherein N is the implementation parallelism of the encoder, K indicates the total number of N x L bit blocks in the memory module, and L is the length of a bit block in the memory module; a controllable permuter configured to perform element re-ordering operations on at least N elements, wherein said controllable permuter is coupled to said memory module; a vector accumulator module including N accumulators arranged in parallel, said vector accumulator module including: i) a first input at least N bits wide, wherein said first input is coupled to an output of said controllable permuter, ii) a second input at least N bits wide, and iii) a vector accumulator output at least N bits wide; a controllable storage device including: i) N x K storage locations; ii) a block select control signal input configured to receive a signal indicating a block of at least N storage locations to be accessed; and iii) a storage device output at least N bits wide, wherein said storage device output is configured to output values read from said controllable storage device; and a code lifting based block selection module coupled to said controllable storage device, wherein said block selection module is configured to supply a block selection control signal to said controllable storage device, wherein the implementation parallelism N is the lifting factor Z divided by K. a memory module including at least N x L x K storage locations, where N and L are positive integers and K is an integer >1, wherein N is the implementation parallelism of the encoder, K indicates the total number of N x L bit blocks in the memory module, and L is the length of a bit block in the memory module; a controllable permuter configured to perform element re-ordering operations on at least N elements, wherein said controllable permuter is coupled to said memory module; a vector accumulator module including N accumulators arranged in parallel, said vector accumulator module including: i) a first input at least N bits wide, wherein said first input is coupled to an output of said controllable permuter, ii) a second input at least N bits wide, and iii) a vector accumulator output at least N bits wide; i) a first input at least N bits wide, wherein said first input is coupled to an output of said controllable permuter, ii) a second input at least N bits wide, and iii) a vector accumulator output at least N bits wide; a controllable storage device including: i) N x K storage locations; ii) a block select control signal input configured to receive a signal indicating a block of at least N storage locations to be accessed; and iii) a storage device output at least N bits wide, wherein said storage device output is configured to output values read from said controllable storage device; and i) N x K storage locations; ii) a block select control signal input configured to receive a signal indicating a block of at least N storage locations to be accessed; and iii) a storage device output at least N bits wide, wherein said storage device output is configured to output values read from said controllable storage device; and a code lifting based block selection module coupled to said controllable storage device, wherein said block selection module is configured to supply a block selection control signal to said controllable storage device, wherein the implementation parallelism N is the lifting factor Z divided by K.