An optical receiver for receiving an incoming optical signal carrying symbols, comprising: an analog-to-digital converter, ADC, operating at a fractional sampling clock rate to convert an analog signal carrying the symbols to digital ADC output samples; and an interpolator to interpolate at an interpolation clock rate different than the fractional sampling clock rate between digital values derived from said the digital ADC output samples to provide moving interpolations; characterized in that it also comprises an interpolation feedback loop to synchronize the moving interpolations with the symbols; the interpolation feedback loop comprising: an accumulator to provide interpolation fractions at the interpolation clock rate, wherein the interpolator is configured to use the interpolation fractions to interpolate between the digital values to compute values of the moving interpolations; and a seed generator to compute seeds based in part on a ratio between the fractional sampling clock rate and the interpolation clock rate, the accumulator being configured to increment by the seeds to compute the interpolation fractions; wherein the accumulator is configured with a modulus to generate an overflow when an increment by a current one of the seeds causes the modulus to be exceeded; and wherein the interpolator is configured to operate with the interpolation clock rate to respond to the overflow by reading a new one of the digital values; and to use a current one of the interpolation fractions to interpolate between the new digital value and a previous one of the digital values when the accumulator generates the overflow or to interpolate by the current interpolation fraction between a previous one of the digital values and a second previous one of the digital values when the accumulator does not generate the overflow. an analog-to-digital converter, ADC, operating at a fractional sampling clock rate to convert an analog signal carrying the symbols to digital ADC output samples; and an interpolator to interpolate at an interpolation clock rate different than the fractional sampling clock rate between digital values derived from said the digital ADC output samples to provide moving interpolations; characterized in that it also comprises an interpolation feedback loop to synchronize the moving interpolations with the symbols; the interpolation feedback loop comprising: an accumulator to provide interpolation fractions at the interpolation clock rate, wherein the interpolator is configured to use the interpolation fractions to interpolate between the digital values to compute values of the moving interpolations; and a seed generator to compute seeds based in part on a ratio between the fractional sampling clock rate and the interpolation clock rate, the accumulator being configured to increment by the seeds to compute the interpolation fractions; wherein the accumulator is configured with a modulus to generate an overflow when an increment by a current one of the seeds causes the modulus to be exceeded; and wherein the interpolator is configured to operate with the interpolation clock rate to respond to the overflow by reading a new one of the digital values; and to use a current one of the interpolation fractions to interpolate between the new digital value and a previous one of the digital values when the accumulator generates the overflow or to interpolate by the current interpolation fraction between a previous one of the digital values and a second previous one of the digital values when the accumulator does not generate the overflow.