An apparatus for protecting a basic input/output system, BIOS, in a computing system, the apparatus comprising: a BIOS read only memory, ROM, comprising: BIOS contents, stored as plaintext, and an encrypted message digest, comprising an encrypted version of a first message digest that corresponds to the BIOS contents; a tamper detection microcode storage, storing tamper protection microcode; a microprocessor (104, 204) comprising a random number generator (430, 830) configured to generate a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied; and a tamper detector (314,814), operatively coupled to the BIOS ROM, configured to generate a BIOS check interrupt that interrupts normal operation of the computing system at a combination of prescribed intervals and event occurrences to access the BIOS contents and the encrypted message digest upon assertion of a BIOS check interrupt, to direct the microprocessor (104, 204) to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, to compare the second message digest with the decrypted message digest, and to preclude the operation of the microprocessor (104, 204) if the second message digest and the decrypted message digest are not equal; characterised in that the event occurrences comprise input/output accesses; the apparatus further comprises a JTAG control chain, configured to program the combination of prescribed intervals and event occurrences within the tamper detection microcode storage, whereby associated JTAG commands are routed though the JTAG control chain to the tamper detection microcode storage in order to_program the combination of prescribed intervals and event occurrences, the microprocessor (104, 204) further comprises a fuse which is blown to indicate that harmful or unauthorized JTAG activity is to be disabled, and the apparatus further comprises an access control element, configured to detect the state of the fuse and if the fuse is blown, to direct the JTAG control chain to disable all JTAG operations outside of normal boundary scan and test operations. a BIOS read only memory, ROM, comprising: BIOS contents, stored as plaintext, and an encrypted message digest, comprising an encrypted version of a first message digest that corresponds to the BIOS contents; a tamper detection microcode storage, storing tamper protection microcode; a microprocessor (104, 204) comprising a random number generator (430, 830) configured to generate a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied; and BIOS contents, stored as plaintext, and an encrypted message digest, comprising an encrypted version of a first message digest that corresponds to the BIOS contents; a tamper detection microcode storage, storing tamper protection microcode; a microprocessor (104, 204) comprising a random number generator (430, 830) configured to generate a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied; and a tamper detector (314,814), operatively coupled to the BIOS ROM, configured to generate a BIOS check interrupt that interrupts normal operation of the computing system at a combination of prescribed intervals and event occurrences to access the BIOS contents and the encrypted message digest upon assertion of a BIOS check interrupt, to direct the microprocessor (104, 204) to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, to compare the second message digest with the decrypted message digest, and to preclude the operation of the microprocessor (104, 204) if the second message digest and the decrypted message digest are not equal; characterised in that the event occurrences comprise input/output accesses; the apparatus further comprises a JTAG control chain, configured to program the combination of prescribed intervals and event occurrences within the tamper detection microcode storage, whereby associated JTAG commands are routed though the JTAG control chain to the tamper detection microcode storage in order to_program the combination of prescribed intervals and event occurrences, the microprocessor (104, 204) further comprises a fuse which is blown to indicate that harmful or unauthorized JTAG activity is to be disabled, and the apparatus further comprises an access control element, configured to detect the state of the fuse and if the fuse is blown, to direct the JTAG control chain to disable all JTAG operations outside of normal boundary scan and test operations.