A data processing system comprising: a first processor; a second processor; a cache configured to be shared by the first processor and the second processor, the cache having N sets, each set including a plurality of cache lines, wherein N is any integer greater than or equal to two, and each cache line is configured to store a tag, at least one status bit, and corresponding cache line data, wherein: the cache is divided into a first cache portion corresponding to a first requestor identifier and a second cache portion corresponding to a second requestor ID, the first cache portion and the second cache portion each including a unique and non-overlapping subset of the N sets, in which the first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID; a memory controller configured to communicate with a shared memory, the shared memory corresponding to a backing store for the cache; wherein a corresponding requestor ID is received with each memory access request, and each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID, in which each corresponding index portion includes fewer than 2 N bits; and characterized by: wherein the cache further comprises allocation circuitry which includes a priority encoder and line fill status storage circuitry, wherein the allocation circuitry is configured to: in response to a read access request from the first processor missing in the cache, initiate a line fill from the shared memory into an allocated cache line in the first portion of the cache; in response to a subsequent read access request from the second processor missing in the cache and determining from the priority encoder that the second processor has priority over the first processor, pause the line fill to the allocated cache line in the first portion of the cache; and prior to completing the line fill to the allocated cache line in the first portion of the cache, complete a line fill from the shared memory into an allocated cache line in the second portion of the cache. a first processor; a second processor; a cache configured to be shared by the first processor and the second processor, the cache having N sets, each set including a plurality of cache lines, wherein N is any integer greater than or equal to two, and each cache line is configured to store a tag, at least one status bit, and corresponding cache line data, wherein: the cache is divided into a first cache portion corresponding to a first requestor identifier and a second cache portion corresponding to a second requestor ID, the first cache portion and the second cache portion each including a unique and non-overlapping subset of the N sets, in which the first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID; a memory controller configured to communicate with a shared memory, the shared memory corresponding to a backing store for the cache; wherein a corresponding requestor ID is received with each memory access request, and each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID, in which each corresponding index portion includes fewer than 2 N bits; and characterized by: wherein the cache further comprises allocation circuitry which includes a priority encoder and line fill status storage circuitry, wherein the allocation circuitry is configured to: in response to a read access request from the first processor missing in the cache, initiate a line fill from the shared memory into an allocated cache line in the first portion of the cache; in response to a subsequent read access request from the second processor missing in the cache and determining from the priority encoder that the second processor has priority over the first processor, pause the line fill to the allocated cache line in the first portion of the cache; and prior to completing the line fill to the allocated cache line in the first portion of the cache, complete a line fill from the shared memory into an allocated cache line in the second portion of the cache. in response to a read access request from the first processor missing in the cache, initiate a line fill from the shared memory into an allocated cache line in the first portion of the cache; in response to a subsequent read access request from the second processor missing in the cache and determining from the priority encoder that the second processor has priority over the first processor, pause the line fill to the allocated cache line in the first portion of the cache; and prior to completing the line fill to the allocated cache line in the first portion of the cache, complete a line fill from the shared memory into an allocated cache line in the second portion of the cache.