A system comprising: a first voltage input; a second voltage input; and a system on a programmable chip, SOPC, including: a control block, a core, an interface, a plurality of configuration shift registers (308, 202, 204), and a plurality of multiplexers (402, 404), wherein each of the multiplexers (402, 404) is configured to provide an output (416, 418) to the interface and is configured to multiplex between signals provided by the first or second voltage input (408, 412) and at least one of the plurality configuration shift registers (308, 202, 204) based on a value of a user-mode bit controlled by the control block; wherein the SOPC is adapted to configure the interface via the first voltage input or the second voltage input during a power-up mode, wherein the control block is configured to set the user mode bit to a first value causing the plurality of multiplexers (402, 404) to output signals provided by the first or second voltage input (408, 412) to the interface as a first set of interface configuration data to configure the interface; wherein the SOPC is adapted to, during a configuration mode that follows the power-up mode, store a second set of interface configuration data in the plurality of configuration shift registers and to configure the core with core configuration data and the configuration shift registers with shift register configuration data, wherein the interface of the SOPC is adapted to access the shift register configuration data and the core configuration data from the host, and wherein the control block is adapted to maintain, during the configuration mode, the user mode bit at the first value set during the power-up mode; and wherein the SOPC is adapted to, during a user mode that follows the configuration mode, to configure the interface using the second set of configuration data stored in the plurality of configuration shift registers during the user mode, wherein the control block is configured to change the user mode bit from the first value to a second value to cause the multiplexers (402, 404) to output the second set of configuration data to the interface. a first voltage input; a second voltage input; and a system on a programmable chip, SOPC, including: a control block, a core, an interface, a plurality of configuration shift registers (308, 202, 204), and a plurality of multiplexers (402, 404), wherein each of the multiplexers (402, 404) is configured to provide an output (416, 418) to the interface and is configured to multiplex between signals provided by the first or second voltage input (408, 412) and at least one of the plurality configuration shift registers (308, 202, 204) based on a value of a user-mode bit controlled by the control block; a control block, a core, an interface, a plurality of configuration shift registers (308, 202, 204), and a plurality of multiplexers (402, 404), wherein each of the multiplexers (402, 404) is configured to provide an output (416, 418) to the interface and is configured to multiplex between signals provided by the first or second voltage input (408, 412) and at least one of the plurality configuration shift registers (308, 202, 204) based on a value of a user-mode bit controlled by the control block; wherein the SOPC is adapted to configure the interface via the first voltage input or the second voltage input during a power-up mode, wherein the control block is configured to set the user mode bit to a first value causing the plurality of multiplexers (402, 404) to output signals provided by the first or second voltage input (408, 412) to the interface as a first set of interface configuration data to configure the interface; wherein the SOPC is adapted to, during a configuration mode that follows the power-up mode, store a second set of interface configuration data in the plurality of configuration shift registers and to configure the core with core configuration data and the configuration shift registers with shift register configuration data, wherein the interface of the SOPC is adapted to access the shift register configuration data and the core configuration data from the host, and wherein the control block is adapted to maintain, during the configuration mode, the user mode bit at the first value set during the power-up mode; and wherein the SOPC is adapted to, during a user mode that follows the configuration mode, to configure the interface using the second set of configuration data stored in the plurality of configuration shift registers during the user mode, wherein the control block is configured to change the user mode bit from the first value to a second value to cause the multiplexers (402, 404) to output the second set of configuration data to the interface.