A DC-DC converter comprising: a high side switch and a low side switch coupled in series, with a first end of an output inductor coupled to a node between the high side switch and the low side switch and a second end of the output inductor providing a regulated output for a load, with an output capacitor coupled to the second end of the output inductor; a pulse width modulation, PWM, signal generator configured to generate a PWM signal having a duty cycle; a first comparator configured to determine if voltage of the regulated output is greater than a desired output voltage plus a tolerance voltage; a second comparator configured to determine if voltage of the regulated output is less than a desired output voltage minus a tolerance voltage; characterised in that the DC-DC converter further comprises: a bypass switch coupling the first end and second end of the output inductor logic circuitry to control the high side switch, the low side switch, and the bypass switch based on at least the PWM signal and the output of the first comparator; first averaging circuitry configured to determine a first average value over time of the output of the first comparator; second averaging circuitry configured to determine a second average value over time of the output of the second comparator; first evaluation circuitry configured to determine a first indication of load current based on the first average value over time of the output of the first comparator, wherein the first indication of load current is load current during pulse frequency modulation mode operation of the high side and low side switches; and second evaluation circuitry configured to determine a second indication of load current based on the second average value over time of the output of the second comparator, wherein the second indication of load current is load current during pulse width modulation mode operation of the high side and low side switches. a high side switch and a low side switch coupled in series, with a first end of an output inductor coupled to a node between the high side switch and the low side switch and a second end of the output inductor providing a regulated output for a load, with an output capacitor coupled to the second end of the output inductor; a pulse width modulation, PWM, signal generator configured to generate a PWM signal having a duty cycle; a first comparator configured to determine if voltage of the regulated output is greater than a desired output voltage plus a tolerance voltage; a second comparator configured to determine if voltage of the regulated output is less than a desired output voltage minus a tolerance voltage; characterised in that the DC-DC converter further comprises: a bypass switch coupling the first end and second end of the output inductor logic circuitry to control the high side switch, the low side switch, and the bypass switch based on at least the PWM signal and the output of the first comparator; first averaging circuitry configured to determine a first average value over time of the output of the first comparator; second averaging circuitry configured to determine a second average value over time of the output of the second comparator; first evaluation circuitry configured to determine a first indication of load current based on the first average value over time of the output of the first comparator, wherein the first indication of load current is load current during pulse frequency modulation mode operation of the high side and low side switches; and second evaluation circuitry configured to determine a second indication of load current based on the second average value over time of the output of the second comparator, wherein the second indication of load current is load current during pulse width modulation mode operation of the high side and low side switches. a bypass switch coupling the first end and second end of the output inductor logic circuitry to control the high side switch, the low side switch, and the bypass switch based on at least the PWM signal and the output of the first comparator; first averaging circuitry configured to determine a first average value over time of the output of the first comparator; second averaging circuitry configured to determine a second average value over time of the output of the second comparator; first evaluation circuitry configured to determine a first indication of load current based on the first average value over time of the output of the first comparator, wherein the first indication of load current is load current during pulse frequency modulation mode operation of the high side and low side switches; and second evaluation circuitry configured to determine a second indication of load current based on the second average value over time of the output of the second comparator, wherein the second indication of load current is load current during pulse width modulation mode operation of the high side and low side switches.