A system, comprising: a processor configured to perform a convolution on a vector, wherein to perform the convolution on the vector the processor is configured to execute a plurality of vector instructions, wherein each of the plurality of vector instructions is configured to cause the processor to perform an operation on one or more data registers comprising a plurality of data lanes of multiple data bits, and wherein the plurality of vector instructions are configured to cause the processor to: load a plurality of source vectors into respective data registers, each of the respective data registers having a plurality of data lanes, wherein to load the plurality of source vectors into the respective data registers, the plurality of vector instructions is configured to cause the processor to load a center vector, a left vector where vector alignment has been shifted left one or more data lanes relative to the center vector; and a right vector where vector alignment has been shifted right one or more data lanes relative to the center vector; load one or more weighting vectors (410A,410B,410C) comprising a plurality of weighting values for the convolution; and generate one or more output vectors, wherein to generate the one or more output vectors the plurality of vector instructions are configured to cause the processor to add to the one or more output vectors each of the plurality of source vectors scaled by respective weighting values for the convolution, wherein to add to a particular one of the one or more the output vectors each of the plurality of source vectors scaled by respective weighting values for the convolution, the plurality of vector instructions comprises a vector scaling instruction for each one of the plurality of source vectors configured to cause the processor to: load a respective weighting value for the convolution from a specified lane of a specified one of the one or more weighting vectors; multiply each of a plurality of data lanes of the one of the plurality of source vectors by the respective weighting value to generate a scaled vector; add the scaled vector to the particular one of the one or more output vectors. load a plurality of source vectors into respective data registers, each of the respective data registers having a plurality of data lanes, wherein to load the plurality of source vectors into the respective data registers, the plurality of vector instructions is configured to cause the processor to load a center vector, a left vector where vector alignment has been shifted left one or more data lanes relative to the center vector; and a right vector where vector alignment has been shifted right one or more data lanes relative to the center vector; load one or more weighting vectors (410A,410B,410C) comprising a plurality of weighting values for the convolution; and generate one or more output vectors, wherein to generate the one or more output vectors the plurality of vector instructions are configured to cause the processor to add to the one or more output vectors each of the plurality of source vectors scaled by respective weighting values for the convolution, wherein to add to a particular one of the one or more the output vectors each of the plurality of source vectors scaled by respective weighting values for the convolution, the plurality of vector instructions comprises a vector scaling instruction for each one of the plurality of source vectors configured to cause the processor to: load a respective weighting value for the convolution from a specified lane of a specified one of the one or more weighting vectors; multiply each of a plurality of data lanes of the one of the plurality of source vectors by the respective weighting value to generate a scaled vector; add the scaled vector to the particular one of the one or more output vectors. load a respective weighting value for the convolution from a specified lane of a specified one of the one or more weighting vectors; multiply each of a plurality of data lanes of the one of the plurality of source vectors by the respective weighting value to generate a scaled vector; add the scaled vector to the particular one of the one or more output vectors.