A processing apparatus comprising: an instruction fetch unit to fetch a single instruction to perform memory conflict detection for a vectorized iterative scalar operation, the instruction including a first source operand indicating a first vector register and a second source operand indicating a second vector register, each vector register including a vectorized array including memory locations for a set of vectorized iterative scalar iterations; decode logic to decode the instruction into a decoded instruction; and an execution unit to execute the decoded instruction to perform the memory conflict detection for the vectorized iterative scalar operation and derive a partition vector including at least one conflict free group of scalar iterations; and a register file unit to commit the partition vector to a location specified by a destination operand, wherein the execution unit is to execute the decoded instruction to for each pair of elements of the vectorized arrays, a pair of elements including an element of a first vectorized array at a first index and an element of a second vectorized array at a second index, the second index being less than the first index, determine a conflict in the pair of elements if the element at the first index is equal to the element at the second index; write a path length if the conflict is determined; and set an element of the partition vector at the first index by bitwise OR-ing the element of the partition vector at the first index and an element of the partition vector at the second index left-shifted by the path length, wherein elements of the partition vector having the same value forming a conflict free group of scalar iterations. an instruction fetch unit to fetch a single instruction to perform memory conflict detection for a vectorized iterative scalar operation, the instruction including a first source operand indicating a first vector register and a second source operand indicating a second vector register, each vector register including a vectorized array including memory locations for a set of vectorized iterative scalar iterations; decode logic to decode the instruction into a decoded instruction; and an execution unit to execute the decoded instruction to perform the memory conflict detection for the vectorized iterative scalar operation and derive a partition vector including at least one conflict free group of scalar iterations; and a register file unit to commit the partition vector to a location specified by a destination operand, wherein the execution unit is to execute the decoded instruction to for each pair of elements of the vectorized arrays, a pair of elements including an element of a first vectorized array at a first index and an element of a second vectorized array at a second index, the second index being less than the first index, determine a conflict in the pair of elements if the element at the first index is equal to the element at the second index; write a path length if the conflict is determined; and set an element of the partition vector at the first index by bitwise OR-ing the element of the partition vector at the first index and an element of the partition vector at the second index left-shifted by the path length, determine a conflict in the pair of elements if the element at the first index is equal to the element at the second index; write a path length if the conflict is determined; and set an element of the partition vector at the first index by bitwise OR-ing the element of the partition vector at the first index and an element of the partition vector at the second index left-shifted by the path length, wherein elements of the partition vector having the same value forming a conflict free group of scalar iterations.