A method of implementing a function of a network function virtualisation infrastructure that requires hardware acceleration in a network function virtualisation system, comprising: combining, by an acceleration processing device, a first acceleration application and a second acceleration application to obtain a first combined application, wherein the first acceleration application, the second acceleration application, and the first combined application are hardware description language, HDL, code, the HDL code describing a logical function that requires hardware acceleration, the logical function used to respond to invocation for an API of an acceleration capability, wherein the logical function described by the HDL code includes a logical function described by the first acceleration application and a logical function described by the second acceleration application, wherein the first combined application comprises a top module, the first acceleration application, and the second acceleration application, and the top module comprises a statement used to invoke the first acceleration application and a statement used to invoke the second acceleration application; and burning, by the acceleration processing device, the first combined application to a first acceleration resource, such that after the first combined application is burnt to the first acceleration resource, the first acceleration resource executes both an invocation request for the first acceleration application and an invocation request for the second acceleration application, wherein the first acceleration resource is an area in a field programmable gate array, FPGA, wherein burning includes: synthesising the HDL code to generate a netlist, performing placement and routing based on the netlist by using a verification method, to generate a binary file, and transmitting the binary file to the FPGA. combining, by an acceleration processing device, a first acceleration application and a second acceleration application to obtain a first combined application, wherein the first acceleration application, the second acceleration application, and the first combined application are hardware description language, HDL, code, the HDL code describing a logical function that requires hardware acceleration, the logical function used to respond to invocation for an API of an acceleration capability, wherein the logical function described by the HDL code includes a logical function described by the first acceleration application and a logical function described by the second acceleration application, wherein the first combined application comprises a top module, the first acceleration application, and the second acceleration application, and the top module comprises a statement used to invoke the first acceleration application and a statement used to invoke the second acceleration application; and wherein the first acceleration application, the second acceleration application, and the first combined application are hardware description language, HDL, code, the HDL code describing a logical function that requires hardware acceleration, the logical function used to respond to invocation for an API of an acceleration capability, wherein the logical function described by the HDL code includes a logical function described by the first acceleration application and a logical function described by the second acceleration application, wherein the first combined application comprises a top module, the first acceleration application, and the second acceleration application, and the top module comprises a statement used to invoke the first acceleration application and a statement used to invoke the second acceleration application; and burning, by the acceleration processing device, the first combined application to a first acceleration resource, such that after the first combined application is burnt to the first acceleration resource, the first acceleration resource executes both an invocation request for the first acceleration application and an invocation request for the second acceleration application, wherein the first acceleration resource is an area in a field programmable gate array, FPGA, wherein burning includes: synthesising the HDL code to generate a netlist, performing placement and routing based on the netlist by using a verification method, to generate a binary file, and transmitting the binary file to the FPGA.