A processor system comprising: a plurality of processor tiles (154a/154b/154c), each comprising: a supply adjustment circuit adapted to receive a supply voltage from an external voltage supply, the supply adjustment circuit comprising a plurality of selectable resistive elements for regulating an adjusted supply voltage based on said supply voltage and a control signal, wherein said supply adjustment circuit is connected between a corresponding processor core and at least one of said external voltage supply and circuit common or ground; a second regulator coupled to said supply adjustment circuit and configured to generate a charge injection signal based upon a detected droop when a droop level of said adjusted supply voltage falls below a droop threshold value; and a charge selection logic circuit configured to select one or more of said plurality of selectable resistive elements to regulate the adjusted supply voltage to said corresponding processor core when the charge injection signal is asserted, wherein said charge selection logic circuit is coupled to said supply adjustment circuit; characterised in that the processor system further comprises a first regulator coupled to receive a target supply voltage indication (target V) and a plurality of voltage level indications from the plurality of processor tiles (154a/154b/154c), the first regulator configured to produce a charge control signal based upon the target supply voltage indication (target V) and the average of the plurality of voltage level indications wherein the charge selection logic circuit generates the control signal further based on the charge control signal. a plurality of processor tiles (154a/154b/154c), each comprising: a supply adjustment circuit adapted to receive a supply voltage from an external voltage supply, the supply adjustment circuit comprising a plurality of selectable resistive elements for regulating an adjusted supply voltage based on said supply voltage and a control signal, wherein said supply adjustment circuit is connected between a corresponding processor core and at least one of said external voltage supply and circuit common or ground; a second regulator coupled to said supply adjustment circuit and configured to generate a charge injection signal based upon a detected droop when a droop level of said adjusted supply voltage falls below a droop threshold value; and a charge selection logic circuit configured to select one or more of said plurality of selectable resistive elements to regulate the adjusted supply voltage to said corresponding processor core when the charge injection signal is asserted, wherein said charge selection logic circuit is coupled to said supply adjustment circuit; a supply adjustment circuit adapted to receive a supply voltage from an external voltage supply, the supply adjustment circuit comprising a plurality of selectable resistive elements for regulating an adjusted supply voltage based on said supply voltage and a control signal, wherein said supply adjustment circuit is connected between a corresponding processor core and at least one of said external voltage supply and circuit common or ground; a second regulator coupled to said supply adjustment circuit and configured to generate a charge injection signal based upon a detected droop when a droop level of said adjusted supply voltage falls below a droop threshold value; and a charge selection logic circuit configured to select one or more of said plurality of selectable resistive elements to regulate the adjusted supply voltage to said corresponding processor core when the charge injection signal is asserted, wherein said charge selection logic circuit is coupled to said supply adjustment circuit; characterised in that the processor system further comprises a first regulator coupled to receive a target supply voltage indication (target V) and a plurality of voltage level indications from the plurality of processor tiles (154a/154b/154c), the first regulator configured to produce a charge control signal based upon the target supply voltage indication (target V) and the average of the plurality of voltage level indications wherein the charge selection logic circuit generates the control signal further based on the charge control signal.