A method of forming a non-volatile memory cell comprising: providing a semiconductor substrate having a memory cell region and a logic circuit region; forming a pair of conductive floating gates disposed over and insulated from the memory cell region of the substrate; forming a first source region in the substrate between the pair of floating gates; forming a polysilicon layer over and insulated from the substrate in the memory cell region and the logic circuit region, wherein the polysilicon layer extends up and over, and is insulated from, the pair of conductive floating gates; forming oxide spacers on the polysilicon layer in the memory cell region; forming a first block of the polysilicon layer disposed over the substrate and between the pair of conductive floating gate; forming a second block of the polysilicon layer disposed over the substrate with one of the pair of floating gates disposed between the first and second blocks of the polysilicon layer, wherein a side of the second block of the polysilicon layer is aligned with a side of one of the oxide spacers; forming a third block of the polysilicon layer disposed over the substrate with the other of the pair of floating gates disposed between the first and third blocks of the polysilicon layer, wherein a side of the third block of the polysilicon layer is aligned with a side of one of the oxide spacers; forming a fourth block of the polysilicon layer disposed over and insulated from the logic circuit region of the substrate; wherein the forming of the first, second, third and fourth blocks of the polysilicon layer comprises selectively removing portions of the polysilicon layer, and wherein the forming of the second and third blocks of the polysilicon layer comprises performing a polysilicon etch during which the oxide spacers serve as a mask for the polysilicon etch; forming a first drain region in the substrate adjacent the side of the second block of the polysilicon layer; forming a second drain region in the substrate adjacent the side of the third block of the polysilicon layer; forming a third drain region in the substrate adjacent a first side of the fourth block of the polysilicon layer; and forming a second source region in the substrate adjacent a second side of the fourth block of the polysilicon layer opposite the first side of the fourth block. providing a semiconductor substrate having a memory cell region and a logic circuit region; forming a pair of conductive floating gates disposed over and insulated from the memory cell region of the substrate; forming a first source region in the substrate between the pair of floating gates; forming a polysilicon layer over and insulated from the substrate in the memory cell region and the logic circuit region, wherein the polysilicon layer extends up and over, and is insulated from, the pair of conductive floating gates; forming oxide spacers on the polysilicon layer in the memory cell region; forming a first block of the polysilicon layer disposed over the substrate and between the pair of conductive floating gate; forming a second block of the polysilicon layer disposed over the substrate with one of the pair of floating gates disposed between the first and second blocks of the polysilicon layer, wherein a side of the second block of the polysilicon layer is aligned with a side of one of the oxide spacers; forming a third block of the polysilicon layer disposed over the substrate with the other of the pair of floating gates disposed between the first and third blocks of the polysilicon layer, wherein a side of the third block of the polysilicon layer is aligned with a side of one of the oxide spacers; forming a fourth block of the polysilicon layer disposed over and insulated from the logic circuit region of the substrate; wherein the forming of the first, second, third and fourth blocks of the polysilicon layer comprises selectively removing portions of the polysilicon layer, and wherein the forming of the second and third blocks of the polysilicon layer comprises performing a polysilicon etch during which the oxide spacers serve as a mask for the polysilicon etch; forming a first drain region in the substrate adjacent the side of the second block of the polysilicon layer; forming a second drain region in the substrate adjacent the side of the third block of the polysilicon layer; forming a third drain region in the substrate adjacent a first side of the fourth block of the polysilicon layer; and forming a second source region in the substrate adjacent a second side of the fourth block of the polysilicon layer opposite the first side of the fourth block.