A time-interleaved analog-to-digital converter "ADC" circuit comprising: at least a first, a second, and a third ADC slice configured to sample an analog input signal and transmit a digitally converted signal thereof representative of a first, a second, and a third value of the analog input signal at first, second, and third consecutively sampled time points thereof, respectively; at least one reference ADC slice configured to sample the analog input signal and transmit a digitally converted reference value, corresponding to a reference time, to facilitate determining an error value, wherein the error value is determined by subtracting a digitally converted value of the second value of the analog input signal from the digitally converted reference value; a first, a second, and a third register coupled to said first, second, and third ADC slices, and configured to store digitally converted values of the first, second, and third values, respectively; a reference register coupled to said at least one reference ADC slice, and configured to store the digitally converted reference value; a delay register comprising an input and an output, and configured to produce a sample time adjustment signal, wherein the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the analog input signal by said second ADC slice; and a plurality of computational circuit elements (222A, 222B, 222C, 224) coupled to said input, said output, said first, second, and third registers, and said reference register, and configured to determine the error value, a value of an approximate time derivative of the analog input signal estimated from the digitally converted values at the third, the second, and the first sampled time points, and a value of the sample time adjustment signal, wherein: said plurality of computational circuit elements comprises a first summer, a second summer, a third summer, and a multiplier, wherein: said first summer is coupled to and between said first register and said third register, said first summer being further coupled to said multiplier; said second summer is coupled to and between said second register and said reference register, said second summer being further coupled to said multiplier; said multiplier is coupled to and between said first summer and said second summer, said multiplier being further coupled to said third summer; and said third summer is coupled to and between said multiplier and said input. at least a first, a second, and a third ADC slice configured to sample an analog input signal and transmit a digitally converted signal thereof representative of a first, a second, and a third value of the analog input signal at first, second, and third consecutively sampled time points thereof, respectively; at least one reference ADC slice configured to sample the analog input signal and transmit a digitally converted reference value, corresponding to a reference time, to facilitate determining an error value, wherein the error value is determined by subtracting a digitally converted value of the second value of the analog input signal from the digitally converted reference value; a first, a second, and a third register coupled to said first, second, and third ADC slices, and configured to store digitally converted values of the first, second, and third values, respectively; a reference register coupled to said at least one reference ADC slice, and configured to store the digitally converted reference value; a delay register comprising an input and an output, and configured to produce a sample time adjustment signal, wherein the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the analog input signal by said second ADC slice; and a plurality of computational circuit elements (222A, 222B, 222C, 224) coupled to said input, said output, said first, second, and third registers, and said reference register, and configured to determine the error value, a value of an approximate time derivative of the analog input signal estimated from the digitally converted values at the third, the second, and the first sampled time points, and a value of the sample time adjustment signal, wherein: said plurality of computational circuit elements comprises a first summer, a second summer, a third summer, and a multiplier, wherein: said first summer is coupled to and between said first register and said third register, said first summer being further coupled to said multiplier; said second summer is coupled to and between said second register and said reference register, said second summer being further coupled to said multiplier; said multiplier is coupled to and between said first summer and said second summer, said multiplier being further coupled to said third summer; and said third summer is coupled to and between said multiplier and said input. said plurality of computational circuit elements comprises a first summer, a second summer, a third summer, and a multiplier, wherein: said first summer is coupled to and between said first register and said third register, said first summer being further coupled to said multiplier; said second summer is coupled to and between said second register and said reference register, said second summer being further coupled to said multiplier; said multiplier is coupled to and between said first summer and said second summer, said multiplier being further coupled to said third summer; and said third summer is coupled to and between said multiplier and said input.