A write operation circuit used in a semiconductor memory, the semiconductor memory comprising a Data Queue, DQ, port, a Data Bus Inversion, DBI, port, and a memory bank, the write operation circuit comprising: a serial-to-parallel conversion circuit, a data buffer, a DBI decoder, and a precharge module; wherein the serial-to-parallel conversion circuit is connected to the DBI port and the DQ port, and the serial-to-parallel conversion circuit is configured to perform serial-to-parallel conversion on first DBI data of the DBI port to generate second DBI data for transmission through a DBI signal line and is further configured to generate input data of the data buffer according to the second DBI data and input data of the DQ port, wherein when a number of high bits of external data is greater than a preset value, the first DBI data is set to high, and the input data of the DQ port is inversion data of the external data, and when the number of the high bits of the external data is less than or equal to the preset value, the first DBI data is set to low, and the input data of the DQ port is the external data, and wherein the input data of the data buffer comprises inverted data of the input data of the DQ port; the data buffer comprises a plurality of Positive Channel Metal Oxide Semiconductor (PMOS) transistors, a gate electrode of each PMOS transistor is connected to the serial-to-parallel conversion circuit to receive the input data of the data buffer, a drain electrode of each PMOS transistor is connected to a global bus, and the data buffer is configured to determine, according to the input data of the data buffer, whether to invert the global bus; the DBI decoder is connected to the memory bank, receives global bus data over the global bus, receives the second DBI data through the DBI signal line, and is configured to decode the global bus data according to the second DBI data and write the decoded global bus data into the memory bank, wherein the decoding comprises determining whether to invert the global bus data; the precharge module is connected to a precharge signal line and is configured to set an initial state of the global bus to Low. the serial-to-parallel conversion circuit is connected to the DBI port and the DQ port, and the serial-to-parallel conversion circuit is configured to perform serial-to-parallel conversion on first DBI data of the DBI port to generate second DBI data for transmission through a DBI signal line and is further configured to generate input data of the data buffer according to the second DBI data and input data of the DQ port, wherein when a number of high bits of external data is greater than a preset value, the first DBI data is set to high, and the input data of the DQ port is inversion data of the external data, and when the number of the high bits of the external data is less than or equal to the preset value, the first DBI data is set to low, and the input data of the DQ port is the external data, and wherein the input data of the data buffer comprises inverted data of the input data of the DQ port; the data buffer comprises a plurality of Positive Channel Metal Oxide Semiconductor (PMOS) transistors, a gate electrode of each PMOS transistor is connected to the serial-to-parallel conversion circuit to receive the input data of the data buffer, a drain electrode of each PMOS transistor is connected to a global bus, and the data buffer is configured to determine, according to the input data of the data buffer, whether to invert the global bus; the DBI decoder is connected to the memory bank, receives global bus data over the global bus, receives the second DBI data through the DBI signal line, and is configured to decode the global bus data according to the second DBI data and write the decoded global bus data into the memory bank, wherein the decoding comprises determining whether to invert the global bus data; the precharge module is connected to a precharge signal line and is configured to set an initial state of the global bus to Low.