An integrated circuit comprising: an array of logic regions, wherein the logic regions are arranged in rows; wherein each logic region in a particular row includes: a first adder adapted to produce a first adder propagate signal (ptop) at an output and a first carry signal (ctop) at another output in response to a plurality of n input bits (A[0:4], B[0:4]); a second adder adapted to produce a second adder propagate signal (pbot) at an output and a second carry signal (cbot) at another output in response to a plurality of another n input bits (A[5:9], B[5:9]), wherein the first and second adders (102, 104) are chained together to form a 2 n -bit adder; and means for providing a static redundancy signal (ADJBAD), wherein the static redundancy signal (ADJBAD) indicates whether a logic region in an adjacent row of the array of logic regions that is adjacent to said particular row is defective or operating properly; a multiplexer having a first input adapted to receive a carry signal (C IN (row-1)) from the logic region in said adjacent row, a second input adapted to receive a carry signal (C IN (row-2)) from another logic region in a row of the array of logic regions that is adjacent to said adjacent row, a third input adapted to receive the first carry signal (ctop) from the first adder, and a fourth input adapted to receive the second carry signal (cbot) from the second adder; wherein in the multiplexer is adapted to select one of the signals at its inputs as a logic region-carry out signal (LABC OUT) in response to control signals, the control signals being the static redundancy signal (ADJBAD), the first adder propagate signal (ptop), and the second adder propagate signal (pbot). an array of logic regions, wherein the logic regions are arranged in rows; wherein each logic region in a particular row includes: a first adder adapted to produce a first adder propagate signal (ptop) at an output and a first carry signal (ctop) at another output in response to a plurality of n input bits (A[0:4], B[0:4]); a second adder adapted to produce a second adder propagate signal (pbot) at an output and a second carry signal (cbot) at another output in response to a plurality of another n input bits (A[5:9], B[5:9]), wherein the first and second adders (102, 104) are chained together to form a 2 n -bit adder; and means for providing a static redundancy signal (ADJBAD), wherein the static redundancy signal (ADJBAD) indicates whether a logic region in an adjacent row of the array of logic regions that is adjacent to said particular row is defective or operating properly; a multiplexer having a first input adapted to receive a carry signal (C IN (row-1)) from the logic region in said adjacent row, a second input adapted to receive a carry signal (C IN (row-2)) from another logic region in a row of the array of logic regions that is adjacent to said adjacent row, a third input adapted to receive the first carry signal (ctop) from the first adder, and a fourth input adapted to receive the second carry signal (cbot) from the second adder; wherein in the multiplexer is adapted to select one of the signals at its inputs as a logic region-carry out signal (LABC OUT) in response to control signals, the control signals being the static redundancy signal (ADJBAD), the first adder propagate signal (ptop), and the second adder propagate signal (pbot). a first adder adapted to produce a first adder propagate signal (ptop) at an output and a first carry signal (ctop) at another output in response to a plurality of n input bits (A[0:4], B[0:4]); a second adder adapted to produce a second adder propagate signal (pbot) at an output and a second carry signal (cbot) at another output in response to a plurality of another n input bits (A[5:9], B[5:9]), wherein the first and second adders (102, 104) are chained together to form a 2 n -bit adder; and means for providing a static redundancy signal (ADJBAD), wherein the static redundancy signal (ADJBAD) indicates whether a logic region in an adjacent row of the array of logic regions that is adjacent to said particular row is defective or operating properly; a multiplexer having a first input adapted to receive a carry signal (C IN (row-1)) from the logic region in said adjacent row, a second input adapted to receive a carry signal (C IN (row-2)) from another logic region in a row of the array of logic regions that is adjacent to said adjacent row, a third input adapted to receive the first carry signal (ctop) from the first adder, and a fourth input adapted to receive the second carry signal (cbot) from the second adder; wherein in the multiplexer is adapted to select one of the signals at its inputs as a logic region-carry out signal (LABC OUT) in response to control signals, the control signals being the static redundancy signal (ADJBAD), the first adder propagate signal (ptop), and the second adder propagate signal (pbot).