A data path interface circuit for a memory, comprising: a writing path module, connected to an internal port and an external port of the memory respectively, and configured to transmit data to the internal port from the external port; a reading path module, connected to the internal port and the external port respectively, and configured to transmit the data to the external port from the internal port; a first delay module, connected to the external port and the internal port respectively, and configured to obtain the data from the external port or the internal port, perform delay processing on the data, and transmit delayed data to the writing path module or the reading path module respectively; and a delay control module, connected to the first delay module and configured to receive a signal instruction input by an external electronic device and generate a control signal on an output end, according to the signal instruction, said control signal being configured to control delay time for the first delay module to perform the delay processing, characterized in that the first delay module comprises: a selection unit, input ends of the selection unit being connected to the external port and the internal port respectively, and a control end of the selection unit being configured to receive the signal instruction; and a temporary storage unit, a data input end of the temporary storage unit being connected to an output end of the selection unit, an output end of the temporary storage unit being connected to the writing path module and the reading path module, and a control end of the temporary storage unit being connected to the output end of the delay control module for receiving the control signal and being configured to store a signal on its data input end in response to the control signal. a writing path module, connected to an internal port and an external port of the memory respectively, and configured to transmit data to the internal port from the external port; a reading path module, connected to the internal port and the external port respectively, and configured to transmit the data to the external port from the internal port; a first delay module, connected to the external port and the internal port respectively, and configured to obtain the data from the external port or the internal port, perform delay processing on the data, and transmit delayed data to the writing path module or the reading path module respectively; and a delay control module, connected to the first delay module and configured to receive a signal instruction input by an external electronic device and generate a control signal on an output end, according to the signal instruction, said control signal being configured to control delay time for the first delay module to perform the delay processing, characterized in that the first delay module comprises: a selection unit, input ends of the selection unit being connected to the external port and the internal port respectively, and a control end of the selection unit being configured to receive the signal instruction; and a temporary storage unit, a data input end of the temporary storage unit being connected to an output end of the selection unit, an output end of the temporary storage unit being connected to the writing path module and the reading path module, and a control end of the temporary storage unit being connected to the output end of the delay control module for receiving the control signal and being configured to store a signal on its data input end in response to the control signal. a selection unit, input ends of the selection unit being connected to the external port and the internal port respectively, and a control end of the selection unit being configured to receive the signal instruction; and a temporary storage unit, a data input end of the temporary storage unit being connected to an output end of the selection unit, an output end of the temporary storage unit being connected to the writing path module and the reading path module, and a control end of the temporary storage unit being connected to the output end of the delay control module for receiving the control signal and being configured to store a signal on its data input end in response to the control signal.