A processor (100, 200) comprising: a vector register (210, 300, 400) file comprising a multi-port memory; and a plurality of tiles (114, 116, 118 and 232, 234, 236) configured to process an N by N matrix of data elements and an N by 1 vector of data elements, wherein N is an integer equal to or greater than 8, and wherein each of the plurality of tiles (114, 116, 118 and 232, 234, 236) is configured to process N data elements, and wherein the vector register file is configured to: in response to a write instruction, during a single clock cycle store N data elements in the multi-port memory and during each one of out of P clock cycles provide N data elements to each one of P input interface circuits (401, 403, 405) of the multi-port memory, wherein P is an integer equal to N divided by L, wherein L is an integer equal to or greater than 2, and wherein each of the P input interface circuits (401, 403, 405) comprises an input lane configured to carry L data elements in parallel, and wherein during the each one of the P clock cycles the multi-port memory is configured to receive N data elements via a selected at least one of the P input interface circuits (401, 403, 405), and in response to a read instruction, during a single clock cycle retrieve N data elements from the multi-port memory and during each one of out of Q clock cycles provide L data elements from each one of Q output interface circuits (451, 453, 455) of the multi-port memory, wherein Q is an integer equal to N divided by L, and wherein each of the Q output interface circuits (451, 453, 455) comprises an output lane configured to carry L data elements in parallel, and wherein during the each one of the Q clock cycles the multi-port memory is configured to provide N data elements to a selected at least one of the Q output interface circuits (451, 453, 455). a vector register (210, 300, 400) file comprising a multi-port memory; and a plurality of tiles (114, 116, 118 and 232, 234, 236) configured to process an N by N matrix of data elements and an N by 1 vector of data elements, wherein N is an integer equal to or greater than 8, and wherein each of the plurality of tiles (114, 116, 118 and 232, 234, 236) is configured to process N data elements, and wherein the vector register file is configured to: in response to a write instruction, during a single clock cycle store N data elements in the multi-port memory and during each one of out of P clock cycles provide N data elements to each one of P input interface circuits (401, 403, 405) of the multi-port memory, wherein P is an integer equal to N divided by L, wherein L is an integer equal to or greater than 2, and wherein each of the P input interface circuits (401, 403, 405) comprises an input lane configured to carry L data elements in parallel, and wherein during the each one of the P clock cycles the multi-port memory is configured to receive N data elements via a selected at least one of the P input interface circuits (401, 403, 405), and in response to a read instruction, during a single clock cycle retrieve N data elements from the multi-port memory and during each one of out of Q clock cycles provide L data elements from each one of Q output interface circuits (451, 453, 455) of the multi-port memory, wherein Q is an integer equal to N divided by L, and wherein each of the Q output interface circuits (451, 453, 455) comprises an output lane configured to carry L data elements in parallel, and wherein during the each one of the Q clock cycles the multi-port memory is configured to provide N data elements to a selected at least one of the Q output interface circuits (451, 453, 455). in response to a write instruction, during a single clock cycle store N data elements in the multi-port memory and during each one of out of P clock cycles provide N data elements to each one of P input interface circuits (401, 403, 405) of the multi-port memory, wherein P is an integer equal to N divided by L, wherein L is an integer equal to or greater than 2, and wherein each of the P input interface circuits (401, 403, 405) comprises an input lane configured to carry L data elements in parallel, and wherein during the each one of the P clock cycles the multi-port memory is configured to receive N data elements via a selected at least one of the P input interface circuits (401, 403, 405), and in response to a read instruction, during a single clock cycle retrieve N data elements from the multi-port memory and during each one of out of Q clock cycles provide L data elements from each one of Q output interface circuits (451, 453, 455) of the multi-port memory, wherein Q is an integer equal to N divided by L, and wherein each of the Q output interface circuits (451, 453, 455) comprises an output lane configured to carry L data elements in parallel, and wherein during the each one of the Q clock cycles the multi-port memory is configured to provide N data elements to a selected at least one of the Q output interface circuits (451, 453, 455).