A circuit, comprising: at least one bit cell having a first input/output "I/O" terminal coupled to a first bit line, the coupling of the first I/O terminal to the first bit line controlled by a state of a word-line, and a second I/O terminal coupled to a second bit line, the coupling of the second I/O terminal to the second bit line controlled by the state of the word-line; and a word-line driver having an output terminal coupled to the word-line; characterized by: a selector having a first input terminal coupled to a first power supply node (VDDR), a second input terminal coupled to a second power supply node (VDDW), a third input terminal coupled to a first control signal source, and an output terminal coupled to a supply rail of the word-line driver; wherein the first control signal source provides a first control signal that is in a first state for a memory write operation, and in a second state for a memory read operation; and wherein a second control signal source (TMODE) provides a second control signal that is in a first state for a test mode operation and in a second state for a normal memory transaction; wherein the selector is configured, responsive to the first control signal being in a first state, to couple the first power supply node (VDDR) to the output terminal of the selector, and responsive to the first control signal being in a second state, to couple the second power supply node (VDDW) to the output terminal of the selector; and a voltage regulator having a first input terminal coupled to a third power supply node (VDDA), a second input terminal coupled to the second control signal source (TMODE), and an output terminal coupled to the second power supply node (VDDW); wherein the voltage regulator is configured, responsive to the second control signal being in a first state, to provide a voltage lower than the voltage of the third power supply node (VDDA) at the output terminal of the voltage regulator, and responsive to the second control signal being in a second state, to provide a voltage nominally equal to the voltage of the third power supply node (VDDA) at the output terminal of the voltage regulator. at least one bit cell having a first input/output "I/O" terminal coupled to a first bit line, the coupling of the first I/O terminal to the first bit line controlled by a state of a word-line, and a second I/O terminal coupled to a second bit line, the coupling of the second I/O terminal to the second bit line controlled by the state of the word-line; and a word-line driver having an output terminal coupled to the word-line; a selector having a first input terminal coupled to a first power supply node (VDDR), a second input terminal coupled to a second power supply node (VDDW), a third input terminal coupled to a first control signal source, and an output terminal coupled to a supply rail of the word-line driver; wherein the first control signal source provides a first control signal that is in a first state for a memory write operation, and in a second state for a memory read operation; and wherein a second control signal source (TMODE) provides a second control signal that is in a first state for a test mode operation and in a second state for a normal memory transaction; wherein the selector is configured, responsive to the first control signal being in a first state, to couple the first power supply node (VDDR) to the output terminal of the selector, and responsive to the first control signal being in a second state, to couple the second power supply node (VDDW) to the output terminal of the selector; and a voltage regulator having a first input terminal coupled to a third power supply node (VDDA), a second input terminal coupled to the second control signal source (TMODE), and an output terminal coupled to the second power supply node (VDDW); wherein the voltage regulator is configured, responsive to the second control signal being in a first state, to provide a voltage lower than the voltage of the third power supply node (VDDA) at the output terminal of the voltage regulator, and responsive to the second control signal being in a second state, to provide a voltage nominally equal to the voltage of the third power supply node (VDDA) at the output terminal of the voltage regulator.