An apparatus, comprising: a set of vector registers; two or more control registers (70, 75); and processing circuitry to execute a sequence of instructions including a splice instruction identifying at least a first vector register (100, 140, 175, 200, 300), a second vector register (105, 145, 175, 205, 305) and at least two control registers (355, 360; 365, 370; 375, 380), the first vector register storing a first vector of data elements having a vector length, the second vector register storing a second vector of data elements, and the at least two control registers storing control data identifying a sequence of one or more data elements occupying sequential data element positions within the first vector of data elements, wherein the at least two control registers comprise a first control register (355; 365; 380) storing location data identifying a location of a first data element of said sequence within the first vector register, and a second control register (360; 370; 375) storing length data used to identify a length of said sequence, the length indicating a number of data elements, including the first data element, to extract from the first vector of data elements; and the processing circuitry being responsive to execution of the splice instruction to: extract from the first vector each data element identified by the control data in the at least two control registers; output the extracted data elements within sequential data element positions of a result vector (120, 160, 185, 245) of data elements starting from a first end of the result vector; and include, at each data element position in the result vector unoccupied by the extracted data elements, a data element from the second vector of data elements; wherein at least one of the first control register and the second control register comprises a scalar register. a set of vector registers; two or more control registers (70, 75); and processing circuitry to execute a sequence of instructions including a splice instruction identifying at least a first vector register (100, 140, 175, 200, 300), a second vector register (105, 145, 175, 205, 305) and at least two control registers (355, 360; 365, 370; 375, 380), the first vector register storing a first vector of data elements having a vector length, the second vector register storing a second vector of data elements, and the at least two control registers storing control data identifying a sequence of one or more data elements occupying sequential data element positions within the first vector of data elements, wherein the at least two control registers comprise a first control register (355; 365; 380) storing location data identifying a location of a first data element of said sequence within the first vector register, and a second control register (360; 370; 375) storing length data used to identify a length of said sequence, the length indicating a number of data elements, including the first data element, to extract from the first vector of data elements; and the processing circuitry being responsive to execution of the splice instruction to: extract from the first vector each data element identified by the control data in the at least two control registers; output the extracted data elements within sequential data element positions of a result vector (120, 160, 185, 245) of data elements starting from a first end of the result vector; and include, at each data element position in the result vector unoccupied by the extracted data elements, a data element from the second vector of data elements; wherein at least one of the first control register and the second control register comprises a scalar register. the processing circuitry being responsive to execution of the splice instruction to: extract from the first vector each data element identified by the control data in the at least two control registers; output the extracted data elements within sequential data element positions of a result vector (120, 160, 185, 245) of data elements starting from a first end of the result vector; and include, at each data element position in the result vector unoccupied by the extracted data elements, a data element from the second vector of data elements; extract from the first vector each data element identified by the control data in the at least two control registers; output the extracted data elements within sequential data element positions of a result vector (120, 160, 185, 245) of data elements starting from a first end of the result vector; and include, at each data element position in the result vector unoccupied by the extracted data elements, a data element from the second vector of data elements; wherein at least one of the first control register and the second control register comprises a scalar register.