A sense amplifier circuit, comprising an amplification circuit, comprising: a first inverting amplifier and a second inverting amplifier, wherein an input of the first inverting amplifier is connected to an output of the second inverting amplifier at a first node, and an input of the second inverting amplifier is connected to an output of the first inverting amplifier at a second node, wherein the first inverting amplifier comprises a first transistor and a second transistor, a gate terminal of the first transistor and a gate terminal of the second transistor are directly connected together to form the input of the first inverting amplifier at the first node; the second inverting amplifier comprises a third transistor and a fourth transistor, and a gate terminal of the third transistor and a gate terminal of the fourth transistor are directly connected together to form the input of the second inverting amplifier at the second node; and a compensation circuit coupled to the amplification circuit and configured to: in a equalization stage, control a first bitline to connect to the first node and the second node, and control a second bitline to connect to the first node and the second node; in an offset compensation stage, remain on a connection between the first bitline and the first node, remain on a connection between the second bitline and the second node, switch off a connection between the first bitline and the second node, and switch off a connection between the second bitline and the first node until an amount of charges injected into the first bitline and the second bitline is equal to a pre-calculated amount of charges that is able to compensate an input-referred offset voltage of the amplification circuit; and switch off the connection between the first bitline and the first node, and switch off the connection between the second bitline and the second node. an amplification circuit, comprising: a first inverting amplifier and a second inverting amplifier, wherein an input of the first inverting amplifier is connected to an output of the second inverting amplifier at a first node, and an input of the second inverting amplifier is connected to an output of the first inverting amplifier at a second node, wherein the first inverting amplifier comprises a first transistor and a second transistor, a gate terminal of the first transistor and a gate terminal of the second transistor are directly connected together to form the input of the first inverting amplifier at the first node; the second inverting amplifier comprises a third transistor and a fourth transistor, and a gate terminal of the third transistor and a gate terminal of the fourth transistor are directly connected together to form the input of the second inverting amplifier at the second node; and a compensation circuit coupled to the amplification circuit and configured to: in a equalization stage, control a first bitline to connect to the first node and the second node, and control a second bitline to connect to the first node and the second node; in an offset compensation stage, remain on a connection between the first bitline and the first node, remain on a connection between the second bitline and the second node, switch off a connection between the first bitline and the second node, and switch off a connection between the second bitline and the first node until an amount of charges injected into the first bitline and the second bitline is equal to a pre-calculated amount of charges that is able to compensate an input-referred offset voltage of the amplification circuit; and switch off the connection between the first bitline and the first node, and switch off the connection between the second bitline and the second node. in a equalization stage, control a first bitline to connect to the first node and the second node, and control a second bitline to connect to the first node and the second node; in an offset compensation stage, remain on a connection between the first bitline and the first node, remain on a connection between the second bitline and the second node, switch off a connection between the first bitline and the second node, and switch off a connection between the second bitline and the first node until an amount of charges injected into the first bitline and the second bitline is equal to a pre-calculated amount of charges that is able to compensate an input-referred offset voltage of the amplification circuit; and switch off the connection between the first bitline and the first node, and switch off the connection between the second bitline and the second node.