Time base including: - an oscillator generating a periodic signal (Sp) having a natural frequency higher than a reference value, - a frequency divider circuit formed by a division chain defining several division stages (1 to X), said divider circuit receiving, at input, said periodic signal and delivering, at output, at least one clock signal (S cl 1 S cl 2) having a divided frequency, - a divided frequency adjustment circuit functioning by inhibiting, in each inhibition period of a plurality of successive inhibition periods, an integer number of clocking pulses (N inh) at the input of a given stage of said division chain, characterized in that the time base is arranged to produce, in each inhibition period, a first real number (Net) corresponding to said inhibition period multiplied by the difference between a determined clocking frequency, produced by the division stage preceding said given stage or by the oscillator when said given stage is the first stage of the division chain, and a reference frequency for clocking said given stage, and in that the adjustment circuit is arranged to calculate, in each inhibition period, a second real number, which, in a first inhibition period, is equal to said first real number and then, in each subsequent inhibition period, is equal to the addition of said first real number and the fractional part of the second real number obtained in the preceding inhibition period, said integer number of clocking pulses (N inh) to be inhibited in each inhibition period being given by the integer part of said second real number calculated in said inhibition period. - an oscillator generating a periodic signal (Sp) having a natural frequency higher than a reference value, - a frequency divider circuit formed by a division chain defining several division stages (1 to X), said divider circuit receiving, at input, said periodic signal and delivering, at output, at least one clock signal (S cl 1 S cl 2) having a divided frequency, - a divided frequency adjustment circuit functioning by inhibiting, in each inhibition period of a plurality of successive inhibition periods, an integer number of clocking pulses (N inh) at the input of a given stage of said division chain, characterized in that the time base is arranged to produce, in each inhibition period, a first real number (Net) corresponding to said inhibition period multiplied by the difference between a determined clocking frequency, produced by the division stage preceding said given stage or by the oscillator when said given stage is the first stage of the division chain, and a reference frequency for clocking said given stage, and in that the adjustment circuit is arranged to calculate, in each inhibition period, a second real number, which, in a first inhibition period, is equal to said first real number and then, in each subsequent inhibition period, is equal to the addition of said first real number and the fractional part of the second real number obtained in the preceding inhibition period, said integer number of clocking pulses (N inh) to be inhibited in each inhibition period being given by the integer part of said second real number calculated in said inhibition period.