A system for bit-serial computation in a deep neural network, the system comprising: one or more bit-serial tiles for performing bit-serial computations in a neural network, each bit-serial tile receiving input neurons and synapses, and generating output neurons; an activation memory for storing neurons and in communication with the one or more bit-serial tiles via a dispatcher and a reducer, wherein the dispatcher reads neurons from the activation memory and communicates the neurons to the one or more bit-serial tiles via a first interface, and wherein the dispatcher reads synapses from a memory and communicates the synapses to the one or more bit-serial tiles via a second interface, and wherein the reducer receives the output neurons from the one or more bit-serial tiles, and communicates the output neurons to the activation memory via a third interface; and wherein the first interface communicates the neurons to the one or more bit-serial tiles bit-serially and the second interface communicates the synapses to the one or more bit-serial tiles bit-parallelly; and wherein each of the one or more bit-serial tiles comprises: a synapse buffer, an input neuron buffer holding input neurons communicated from the dispatcher, and a neuron output buffer holding output neurons pending communication to the reducer; wherein the input neuron buffer comprises one or more window lanes, wherein each of the one or more window lanes comprises one or more bit-serial neuron lanes; wherein the synapse buffer comprises one of more filter lanes, wherein the one or more filter lanes each comprise one or more synapse lanes; wherein the filter lanes of the synapse buffer and the window lanes of the input neuron buffer are in communication with a 2-dimensional array of one or more serial inner product subunits, comprised in each of the one or more bit-serial tiles, wherein each of the one or more serial inner product subunits produces one output neuron by ANDing, in each of p cycles, one neuron bit communicated via one of the one or more bit-serial neuron lanes with each synapse bit communicated via the one or more synapse lanes of one of the one or more filter lanes and summing the produced results using a multiple-input adder tree, wherein p represents the precision of the neurons in bits. one or more bit-serial tiles for performing bit-serial computations in a neural network, each bit-serial tile receiving input neurons and synapses, and generating output neurons; an activation memory for storing neurons and in communication with the one or more bit-serial tiles via a dispatcher and a reducer, wherein the dispatcher reads neurons from the activation memory and communicates the neurons to the one or more bit-serial tiles via a first interface, and wherein the dispatcher reads synapses from a memory and communicates the synapses to the one or more bit-serial tiles via a second interface, and wherein the reducer receives the output neurons from the one or more bit-serial tiles, and communicates the output neurons to the activation memory via a third interface; and wherein the first interface communicates the neurons to the one or more bit-serial tiles bit-serially and the second interface communicates the synapses to the one or more bit-serial tiles bit-parallelly; and wherein each of the one or more bit-serial tiles comprises: a synapse buffer, an input neuron buffer holding input neurons communicated from the dispatcher, and a neuron output buffer holding output neurons pending communication to the reducer; wherein the input neuron buffer comprises one or more window lanes, wherein each of the one or more window lanes comprises one or more bit-serial neuron lanes; wherein the synapse buffer comprises one of more filter lanes, wherein the one or more filter lanes each comprise one or more synapse lanes; wherein the filter lanes of the synapse buffer and the window lanes of the input neuron buffer are in communication with a 2-dimensional array of one or more serial inner product subunits, comprised in each of the one or more bit-serial tiles, wherein each of the one or more serial inner product subunits produces one output neuron by ANDing, in each of p cycles, one neuron bit communicated via one of the one or more bit-serial neuron lanes with each synapse bit communicated via the one or more synapse lanes of one of the one or more filter lanes and summing the produced results using a multiple-input adder tree, wherein p represents the precision of the neurons in bits. a synapse buffer, an input neuron buffer holding input neurons communicated from the dispatcher, and a neuron output buffer holding output neurons pending communication to the reducer; wherein the input neuron buffer comprises one or more window lanes, wherein each of the one or more window lanes comprises one or more bit-serial neuron lanes; wherein the synapse buffer comprises one of more filter lanes, wherein the one or more filter lanes each comprise one or more synapse lanes; wherein the filter lanes of the synapse buffer and the window lanes of the input neuron buffer are in communication with a 2-dimensional array of one or more serial inner product subunits, comprised in each of the one or more bit-serial tiles, wherein each of the one or more serial inner product subunits produces one output neuron by ANDing, in each of p cycles, one neuron bit communicated via one of the one or more bit-serial neuron lanes with each synapse bit communicated via the one or more synapse lanes of one of the one or more filter lanes and summing the produced results using a multiple-input adder tree, wherein p represents the precision of the neurons in bits.