A CMOS image sensor apparatus configured for providing high dynamic range digital images, comprising: an image sensor for generating a first and a second set of digital image samples at a first bit depth, each set of digital image samples generated by a different column readout circuit path, the image sensor including: (a) an array of pixels arranged in a plurality of row lines and column lines; (b) a plurality of first and second column readout circuits (420, 425) connected in parallel to the plurality of column lines (410, 600) such that each column line is connected to a respective first column readout circuit and a respective second column readout circuit, each first column readout circuit being in a first column readout circuit path and each second column readout circuit being in a second column readout circuit path, the first and second column readout circuits (420, 425) having different amplification responses; and (c) a first output stage connected to all the first column readout circuits (420, 610) and a separate second output stage connected to all the second column readout circuits (425, 615), wherein the first and second output stages each comprise, respectively, a differential amplifier (515, 525, 825, 835) and an analog-to-digital converter (520, 530, 830, 840) having the first bit depth; and a processor for combining the first and the second set of digital image samples to generate a digital image at a second bit depth, the second bit depth being higher than the first bit depth. an image sensor for generating a first and a second set of digital image samples at a first bit depth, each set of digital image samples generated by a different column readout circuit path, the image sensor including: (a) an array of pixels arranged in a plurality of row lines and column lines; (b) a plurality of first and second column readout circuits (420, 425) connected in parallel to the plurality of column lines (410, 600) such that each column line is connected to a respective first column readout circuit and a respective second column readout circuit, each first column readout circuit being in a first column readout circuit path and each second column readout circuit being in a second column readout circuit path, the first and second column readout circuits (420, 425) having different amplification responses; and (c) a first output stage connected to all the first column readout circuits (420, 610) and a separate second output stage connected to all the second column readout circuits (425, 615), (a) an array of pixels arranged in a plurality of row lines and column lines; (b) a plurality of first and second column readout circuits (420, 425) connected in parallel to the plurality of column lines (410, 600) such that each column line is connected to a respective first column readout circuit and a respective second column readout circuit, each first column readout circuit being in a first column readout circuit path and each second column readout circuit being in a second column readout circuit path, the first and second column readout circuits (420, 425) having different amplification responses; and (c) a first output stage connected to all the first column readout circuits (420, 610) and a separate second output stage connected to all the second column readout circuits (425, 615), wherein the first and second output stages each comprise, respectively, a differential amplifier (515, 525, 825, 835) and an analog-to-digital converter (520, 530, 830, 840) having the first bit depth; and a processor for combining the first and the second set of digital image samples to generate a digital image at a second bit depth, the second bit depth being higher than the first bit depth.