A memory device comprising: a memory cell comprising: a resistance-based memory element; a first diode coupled to the resistance-based memory element; and a second diode coupled to the resistance-based memory element; wherein a current through the resistance-based memory element flows through one of the first diode or the second diode; and wherein a cathode of the first diode is coupled to a bit line of the memory cell and an anode of the second diode is coupled to a sense line of the memory cell; characterised in that a ratio of an area of the first diode to an area of the second diode is approximately equal to a ratio of a first critical switching current of the resistance-based memory element to a second critical switching current of the resistance-based memory element; wherein the first critical switching current corresponds to a threshold current that switches the resistance-based memory element from a logical zero state to a logical one state, and wherein the second critical switching current corresponds to a threshold current that switches the resistance-based memory element from the logical one state to the logical zero state. a memory cell comprising: a resistance-based memory element; a first diode coupled to the resistance-based memory element; and a second diode coupled to the resistance-based memory element; wherein a current through the resistance-based memory element flows through one of the first diode or the second diode; and wherein a cathode of the first diode is coupled to a bit line of the memory cell and an anode of the second diode is coupled to a sense line of the memory cell; characterised in that a ratio of an area of the first diode to an area of the second diode is approximately equal to a ratio of a first critical switching current of the resistance-based memory element to a second critical switching current of the resistance-based memory element; wherein the first critical switching current corresponds to a threshold current that switches the resistance-based memory element from a logical zero state to a logical one state, and wherein the second critical switching current corresponds to a threshold current that switches the resistance-based memory element from the logical one state to the logical zero state. a resistance-based memory element; a first diode coupled to the resistance-based memory element; and a second diode coupled to the resistance-based memory element; wherein a current through the resistance-based memory element flows through one of the first diode or the second diode; and wherein a cathode of the first diode is coupled to a bit line of the memory cell and an anode of the second diode is coupled to a sense line of the memory cell; characterised in that a ratio of an area of the first diode to an area of the second diode is approximately equal to a ratio of a first critical switching current of the resistance-based memory element to a second critical switching current of the resistance-based memory element; wherein the first critical switching current corresponds to a threshold current that switches the resistance-based memory element from a logical zero state to a logical one state, and wherein the second critical switching current corresponds to a threshold current that switches the resistance-based memory element from the logical one state to the logical zero state. wherein a current through the resistance-based memory element flows through one of the first diode or the second diode; and wherein a cathode of the first diode is coupled to a bit line of the memory cell and an anode of the second diode is coupled to a sense line of the memory cell; characterised in that a ratio of an area of the first diode to an area of the second diode is approximately equal to a ratio of a first critical switching current of the resistance-based memory element to a second critical switching current of the resistance-based memory element; wherein the first critical switching current corresponds to a threshold current that switches the resistance-based memory element from a logical zero state to a logical one state, and wherein the second critical switching current corresponds to a threshold current that switches the resistance-based memory element from the logical one state to the logical zero state. wherein the first critical switching current corresponds to a threshold current that switches the resistance-based memory element from a logical zero state to a logical one state, and wherein the second critical switching current corresponds to a threshold current that switches the resistance-based memory element from the logical one state to the logical zero state.