An apparatus comprising: a physical layer, PHY, circuitry; a memory configured to implement a message bus register (615, 620), wherein a set of control and status signals are mapped to bits of the message bus register (615, 620), and the set of control and status signals comprises a recalibration request signal mapped to a particular one of the bits of the message bus register; a controller; an interface to couple to the controller, wherein the interface comprises a PHY Interface for the PCI Express, PIPE, -based interface, and the interface comprises: a set of data pins comprising transmit data pins configured to send data to the controller and receive data pins configured to receive data from the controller; a particular set of pins configured to implement a message bus interface, wherein a write command is configured to be received from the controller over the message bus interface to write a value to the particular bit; and a recalibration circuitry configured to perform a recalibration of the PHY circuitry based on the value written to the particular bit; a detection circuitry configured to: detect one or more attributes of the PHY circuitry; and determine that the recalibration should be performed based on the one or more attributes; characterized by the physical layer, PHY, circuitry configured to: send a write command to the controller over the message bus interface to write a value to the message bus register of the controller to indicate to the controller a request to perform a recalibration. a physical layer, PHY, circuitry; a memory configured to implement a message bus register (615, 620), wherein a set of control and status signals are mapped to bits of the message bus register (615, 620), and the set of control and status signals comprises a recalibration request signal mapped to a particular one of the bits of the message bus register; a controller; an interface to couple to the controller, wherein the interface comprises a PHY Interface for the PCI Express, PIPE, -based interface, and the interface comprises: a set of data pins comprising transmit data pins configured to send data to the controller and receive data pins configured to receive data from the controller; a particular set of pins configured to implement a message bus interface, wherein a write command is configured to be received from the controller over the message bus interface to write a value to the particular bit; and a recalibration circuitry configured to perform a recalibration of the PHY circuitry based on the value written to the particular bit; a set of data pins comprising transmit data pins configured to send data to the controller and receive data pins configured to receive data from the controller; a particular set of pins configured to implement a message bus interface, wherein a write command is configured to be received from the controller over the message bus interface to write a value to the particular bit; and a recalibration circuitry configured to perform a recalibration of the PHY circuitry based on the value written to the particular bit; a detection circuitry configured to: detect one or more attributes of the PHY circuitry; and determine that the recalibration should be performed based on the one or more attributes; detect one or more attributes of the PHY circuitry; and determine that the recalibration should be performed based on the one or more attributes; characterized by the physical layer, PHY, circuitry configured to: send a write command to the controller over the message bus interface to write a value to the message bus register of the controller to indicate to the controller a request to perform a recalibration.