A display device having a bankless structure, the display device comprising: a substrate on which at least one pixel is disposed, the pixel including an emission area and a non-emission area; the at least one pixel including: a first conductive layer (LS, BE) disposed on the substrate, and forming a lower electrode of a storage capacitor (Cst) of the pixel; an active layer formed on the first conductive layer; a second conductive layer formed on the active layer, and forming electrodes of at least one transistor (ST, DT, SST) of the pixel and an upper electrode of the storage capacitor (Cst) which is integrally formed with at least one of the electrodes of the at least one transistor; an overcoat layer covering the second conductive layer; and a light-emitting element disposed on the overcoat layer, and connected to the upper electrode of the storage capacitor through a via hole, wherein the via hole is laterally spaced apart from each of the at least one transistor (ST, DT, SST); wherein the at least one transistor includes a driving transistor configured to control an amount of current flowing to the light-emitting element in response to a voltage stored in the storage capacitor (Cst), and wherein the driving transistor comprises: a first electrode formed by the second conductive layer, and connected to a power line of the display device; a second electrode formed by the second conductive layer, and connected to the lower electrode of the storage capacitor; and a third electrode formed by the second conductive layer, integrally formed with the upper electrode of the storage capacitor (Cst), and connected to the light-emitting element via the upper electrode of the storage capacitor (Cst). a substrate on which at least one pixel is disposed, the pixel including an emission area and a non-emission area; the at least one pixel including: a first conductive layer (LS, BE) disposed on the substrate, and forming a lower electrode of a storage capacitor (Cst) of the pixel; an active layer formed on the first conductive layer; a second conductive layer formed on the active layer, and forming electrodes of at least one transistor (ST, DT, SST) of the pixel and an upper electrode of the storage capacitor (Cst) which is integrally formed with at least one of the electrodes of the at least one transistor; an overcoat layer covering the second conductive layer; and a light-emitting element disposed on the overcoat layer, and connected to the upper electrode of the storage capacitor through a via hole, wherein the via hole is laterally spaced apart from each of the at least one transistor (ST, DT, SST); wherein the at least one transistor includes a driving transistor configured to control an amount of current flowing to the light-emitting element in response to a voltage stored in the storage capacitor (Cst), and wherein the driving transistor comprises: a first electrode formed by the second conductive layer, and connected to a power line of the display device; a second electrode formed by the second conductive layer, and connected to the lower electrode of the storage capacitor; and a third electrode formed by the second conductive layer, integrally formed with the upper electrode of the storage capacitor (Cst), and connected to the light-emitting element via the upper electrode of the storage capacitor (Cst). a first conductive layer (LS, BE) disposed on the substrate, and forming a lower electrode of a storage capacitor (Cst) of the pixel; an active layer formed on the first conductive layer; a second conductive layer formed on the active layer, and forming electrodes of at least one transistor (ST, DT, SST) of the pixel and an upper electrode of the storage capacitor (Cst) which is integrally formed with at least one of the electrodes of the at least one transistor; an overcoat layer covering the second conductive layer; and a light-emitting element disposed on the overcoat layer, and connected to the upper electrode of the storage capacitor through a via hole, wherein the via hole is laterally spaced apart from each of the at least one transistor (ST, DT, SST); wherein the at least one transistor includes a driving transistor configured to control an amount of current flowing to the light-emitting element in response to a voltage stored in the storage capacitor (Cst), and wherein the driving transistor comprises: a first electrode formed by the second conductive layer, and connected to a power line of the display device; a second electrode formed by the second conductive layer, and connected to the lower electrode of the storage capacitor; and a third electrode formed by the second conductive layer, integrally formed with the upper electrode of the storage capacitor (Cst), and connected to the light-emitting element via the upper electrode of the storage capacitor (Cst). a first electrode formed by the second conductive layer, and connected to a power line of the display device; a second electrode formed by the second conductive layer, and connected to the lower electrode of the storage capacitor; and a third electrode formed by the second conductive layer, integrally formed with the upper electrode of the storage capacitor (Cst), and connected to the light-emitting element via the upper electrode of the storage capacitor (Cst).