A non-volatile memory integrated on a semiconductor, the non-volatile memory being of the flash EEPROM type, the non-volatile memory comprising: a memory matrix being divided into physical sectors and organised in rows and columns of flash memory cells; the memory_matrix being divided into at least a first and a second physical memory portion of flash memory cells, said at least first and second physical memory portions share the structures of the columns, said first and second physical portions having different minimum erasable sector sizes and different data storage capacities, wherein the structures of columns belonging respectively to said first and second memory portions have the same numerosity; and a decoupling switch to capacitively decouple the first and second physical portions, characterized in that the non-volatile memory is of NAND architecture; said first and second physical portions have different column capacitances and different access speeds due to the different column capacitances; each column of the first portion is the continuation of the homonymous column of the second portion wherein each column of the first portion has a different length than the continuation of the homonymous column of the second portion causing the different column capacitances; at least one row of a given physical sector is electrically connected to at least one row of an adjacent physical sector to form a single logic sector, the electrically connected rows are coupled in groups of two or multiples of two, wherein source terminals of corresponding cells of the connected rows coupled in groups of two or multiples of two referring to a same selection line of a source line. a memory matrix being divided into physical sectors and organised in rows and columns of flash memory cells; the memory_matrix being divided into at least a first and a second physical memory portion of flash memory cells, said at least first and second physical memory portions share the structures of the columns, said first and second physical portions having different minimum erasable sector sizes and different data storage capacities, wherein the structures of columns belonging respectively to said first and second memory portions have the same numerosity; and a decoupling switch to capacitively decouple the first and second physical portions, characterized in that the non-volatile memory is of NAND architecture; said first and second physical portions have different column capacitances and different access speeds due to the different column capacitances; each column of the first portion is the continuation of the homonymous column of the second portion wherein each column of the first portion has a different length than the continuation of the homonymous column of the second portion causing the different column capacitances; at least one row of a given physical sector is electrically connected to at least one row of an adjacent physical sector to form a single logic sector, the electrically connected rows are coupled in groups of two or multiples of two, wherein source terminals of corresponding cells of the connected rows coupled in groups of two or multiples of two referring to a same selection line of a source line.