A device for systolically processing data according to a neural network, the device comprising: a first arrangement of processing units including at least first (P 2,k-1), second (P 2,k), third (P 2,k+1), and fourth (P 2,k+2) processing units, wherein the first and second processing units are connected to systolically pulse data to one another, and wherein the third and fourth processing units are connected to systolically pulse data to one another; and a second arrangement of processing units including at least fifth (P 3,k-1), sixth (P 3,k), seventh (P 3,k+1), and eighth (P 3,k+2) processing units, wherein the fifth and sixth processing units are connected to systolically pulse data to one another, and wherein the seventh and eighth processing units are connected to systolically pulse data to one another, characterised by further comprising: a first interconnect between the second and seventh processing units, wherein the second processing unit is configured to systolically pulse data to the seventh processing unit along the first interconnect; a second interconnect between the third and sixth processing units, wherein the third processing unit is configured to systolically pulse data to the sixth processing unit along the second interconnect; a third interconnect between an uppermost (P 21) processing unit in the first arrangement and an uppermost (P 31) processing unit in the second arrangement; and a fourth interconnect between a lowermost (P 2,N) processing unit in the first arrangement and a lowermost (P 3,N) processing unit in the second arrangement, wherein at least a subset of the processing units of the first arrangement are assigned to perform computations of a first layer of the neural network, and wherein at least a subset of the processing units of the second arrangement are assigned to perform computations of a second layer of the neural network. a first arrangement of processing units including at least first (P 2,k-1), second (P 2,k), third (P 2,k+1), and fourth (P 2,k+2) processing units, wherein the first and second processing units are connected to systolically pulse data to one another, and wherein the third and fourth processing units are connected to systolically pulse data to one another; and a second arrangement of processing units including at least fifth (P 3,k-1), sixth (P 3,k), seventh (P 3,k+1), and eighth (P 3,k+2) processing units, wherein the fifth and sixth processing units are connected to systolically pulse data to one another, and wherein the seventh and eighth processing units are connected to systolically pulse data to one another, characterised by further comprising: a first interconnect between the second and seventh processing units, wherein the second processing unit is configured to systolically pulse data to the seventh processing unit along the first interconnect; a second interconnect between the third and sixth processing units, wherein the third processing unit is configured to systolically pulse data to the sixth processing unit along the second interconnect; a third interconnect between an uppermost (P 21) processing unit in the first arrangement and an uppermost (P 31) processing unit in the second arrangement; and a fourth interconnect between a lowermost (P 2,N) processing unit in the first arrangement and a lowermost (P 3,N) processing unit in the second arrangement, wherein at least a subset of the processing units of the first arrangement are assigned to perform computations of a first layer of the neural network, and wherein at least a subset of the processing units of the second arrangement are assigned to perform computations of a second layer of the neural network. a first interconnect between the second and seventh processing units, wherein the second processing unit is configured to systolically pulse data to the seventh processing unit along the first interconnect; a second interconnect between the third and sixth processing units, wherein the third processing unit is configured to systolically pulse data to the sixth processing unit along the second interconnect; a third interconnect between an uppermost (P 21) processing unit in the first arrangement and an uppermost (P 31) processing unit in the second arrangement; and a fourth interconnect between a lowermost (P 2,N) processing unit in the first arrangement and a lowermost (P 3,N) processing unit in the second arrangement, wherein at least a subset of the processing units of the first arrangement are assigned to perform computations of a first layer of the neural network, and wherein at least a subset of the processing units of the second arrangement are assigned to perform computations of a second layer of the neural network.