An input selector for generating an encoder input bit stream of a IEEE 802.11-2016, rate 1⁄2, 64-state, non-systematic, convolution encoder of a transmitter, the encoder generating an encoder output bit stream based on the encoder input bit stream and the transmitter further having an output interleaver that re-orders the bits of the encoder output bit stream to generate an interleaved output bit stream and a mapper configured to map the interleaved output bit stream to symbols in a modulation constellation, the input selector comprising: a shaper block configured to receive an input comprising a first number of input bits, the shaper block configured to generate a shaped bit stream comprising a second number, n, of amplitudes corresponding to the first number of input bits, each amplitude selected from the amplitudes of a set of symbols distributed within an n -dimensional hypersphere in a modulation constellation, the radius of the hypersphere determined by a maximum symbol energy; an inverse interleaver configured to re-order the bits of the shaped bit stream to generate an interleaved shaped bit stream such that, when the output interleaver of the transmitter re-orders the bits of the encoder output stream, the bits are restored to their original order in the shaped bit stream; and an input-select block configured to generate the encoder input bit stream for the encoder based on the interleaved shaped bit stream, wherein the input-select block generates the encoder input bit stream such that, when input into the encoder, a first bit of the encoder input bit stream sets a state of the encoder in order that a subsequent second bit of the encoder input bit stream causes the encoder to generate a bit of the interleaved shaped bit stream at a pre-determined position in the encoder output bit stream; and wherein the encoder generates two output bits v0, v1 of the encoder output bit stream for each input bit b of the encoder input bit stream according to: v 0 m = b m ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 5 ⊕ b m − 6, v 1 m = b m ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 6, wherein v 0 [ m], v 1 [ m] are the m th output bits of the respective two output bits, b[m] is the m th encoder input bit and b[m-x] are the preceding encoder input bits; and wherein the input-select block is configured to generate the encoder input bit stream according to one of: (i) b m = v 0 m ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 5 ⊕ b m − 6, (ii) b m = v 1 m ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 6, or (iii) b m + 1 = v 0 m + 1 ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 4 ⊕ b m − 5 and b m = v 1 m + 1 ⊕ b m + 1 ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 5. a shaper block configured to receive an input comprising a first number of input bits, the shaper block configured to generate a shaped bit stream comprising a second number, n, of amplitudes corresponding to the first number of input bits, each amplitude selected from the amplitudes of a set of symbols distributed within an n -dimensional hypersphere in a modulation constellation, the radius of the hypersphere determined by a maximum symbol energy; an inverse interleaver configured to re-order the bits of the shaped bit stream to generate an interleaved shaped bit stream such that, when the output interleaver of the transmitter re-orders the bits of the encoder output stream, the bits are restored to their original order in the shaped bit stream; and an input-select block configured to generate the encoder input bit stream for the encoder based on the interleaved shaped bit stream, wherein the input-select block generates the encoder input bit stream such that, when input into the encoder, a first bit of the encoder input bit stream sets a state of the encoder in order that a subsequent second bit of the encoder input bit stream causes the encoder to generate a bit of the interleaved shaped bit stream at a pre-determined position in the encoder output bit stream; and wherein the encoder generates two output bits v0, v1 of the encoder output bit stream for each input bit b of the encoder input bit stream according to: v 0 m = b m ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 5 ⊕ b m − 6, v 1 m = b m ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 6, wherein v 0 [ m], v 1 [ m] are the m th output bits of the respective two output bits, b[m] is the m th encoder input bit and b[m-x] are the preceding encoder input bits; and wherein the input-select block is configured to generate the encoder input bit stream according to one of: (i) b m = v 0 m ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 5 ⊕ b m − 6, (ii) b m = v 1 m ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 6, or (iii) b m + 1 = v 0 m + 1 ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 4 ⊕ b m − 5 and b m = v 1 m + 1 ⊕ b m + 1 ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 5. (i) b m = v 0 m ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 5 ⊕ b m − 6, (ii) b m = v 1 m ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 3 ⊕ b m − 6, or (iii) b m + 1 = v 0 m + 1 ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 4 ⊕ b m − 5 and b m = v 1 m + 1 ⊕ b m + 1 ⊕ b m − 1 ⊕ b m − 2 ⊕ b m − 5.