Non-Volatile Static Random-Access Memory, NV-SRAM, device including a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell comprising a first storage node and a second storage node; a first bit-line connected via a first access element to the first storage node; another first bit-line connected via another first access element to the second storage node; a non-volatile bit-cell comprising a first resistive memory element and a second resistive memory element connected together via a second restore-line; a second bit-line connected via a second access element to the first resistive memory element; and another second bit-line connected via another second access element to the second resistive memory element; wherein: the first resistive memory element is connected via a switch to the first storage node, the second resistive memory element is connected via another switch to the second storage node, the first access element comprises a transistor, the another first access element comprises a transistor, the switch comprises a transistor, the another switch comprises a transistor, a gate of the transistor comprised by the first access element is connected to a first word-line, a gate of the transistor comprised by the another first access element is connected to the first word-line, a gate of the transistor comprised by the switch is connected to a gate of the transistor comprised by the another switch via a first restore-line, the second access element comprises a transistor, the another second access element comprises a transistor, a gate of the transistor comprised by the second access element is connected to a second word-line, a gate of the transistor comprised by the another second access element is connected to the second word-line, and the NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and, respectively, from the second bit-line into the non-volatile bit-cell through the second access element. an SRAM bit-cell comprising a first storage node and a second storage node; a first bit-line connected via a first access element to the first storage node; another first bit-line connected via another first access element to the second storage node; a non-volatile bit-cell comprising a first resistive memory element and a second resistive memory element connected together via a second restore-line; a second bit-line connected via a second access element to the first resistive memory element; and another second bit-line connected via another second access element to the second resistive memory element; wherein: the first resistive memory element is connected via a switch to the first storage node, the second resistive memory element is connected via another switch to the second storage node, the first access element comprises a transistor, the another first access element comprises a transistor, the switch comprises a transistor, the another switch comprises a transistor, a gate of the transistor comprised by the first access element is connected to a first word-line, a gate of the transistor comprised by the another first access element is connected to the first word-line, a gate of the transistor comprised by the switch is connected to a gate of the transistor comprised by the another switch via a first restore-line, the second access element comprises a transistor, the another second access element comprises a transistor, a gate of the transistor comprised by the second access element is connected to a second word-line, a gate of the transistor comprised by the another second access element is connected to the second word-line, and the NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and, respectively, from the second bit-line into the non-volatile bit-cell through the second access element. the first resistive memory element is connected via a switch to the first storage node, the second resistive memory element is connected via another switch to the second storage node, the first access element comprises a transistor, the another first access element comprises a transistor, the switch comprises a transistor, the another switch comprises a transistor, a gate of the transistor comprised by the first access element is connected to a first word-line, a gate of the transistor comprised by the another first access element is connected to the first word-line, a gate of the transistor comprised by the switch is connected to a gate of the transistor comprised by the another switch via a first restore-line, the second access element comprises a transistor, the another second access element comprises a transistor, a gate of the transistor comprised by the second access element is connected to a second word-line, a gate of the transistor comprised by the another second access element is connected to the second word-line, and the NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and, respectively, from the second bit-line into the non-volatile bit-cell through the second access element.