A method, comprising: injecting a randomly determined amount of dither into a digital-to-analog converter component in a first stage of a multi-stage pipelined analog-to-digital converter, the DAC having a switched capacitor network comprising a plurality of capacitors that are switchably connected to an input signal source to the ADC, wherein the dither is injected by: connecting a first capacitor (CCal) to a first or second reference voltage (Vref+, Vref-) in accordance with a randomly generated number when the switched capacitor network is disconnected from the input signal source during a hold phase of the switched capacitor network, and connecting the first capacitor in parallel with the capacitors of the switched capacitor network when the switched capacitor network is connected to the input signal source to sample an input signal (Vin+, Vin-) during a subsequent sampling phase of the switched capacitor network, such that in the presence of kickback between the switched capacitor network and the input signal source, at least some charge from the first capacitor is sampled by the switched capacitor network with the input signal at the end of the subsequent sampling phase; after injecting the dither, determining at least one gain coefficient by correlating the random number and an overall digital output of the ADC corresponding to the input signal sampled during the subsequent sampling phase, wherein the gain coefficient is indicative of a transfer function of the kick-back; generating, as a function of the at least one gain coefficient, the random number and a digital output of the first stage corresponding to a previous input sample, at least two correction values corresponding to a contribution of the kick-back to the overall digital output of the ADC; and subtracting the correction values from the overall digital output of the ADC, thereby correcting for kick-back errors in the overall digital output. injecting a randomly determined amount of dither into a digital-to-analog converter component in a first stage of a multi-stage pipelined analog-to-digital converter, the DAC having a switched capacitor network comprising a plurality of capacitors that are switchably connected to an input signal source to the ADC, wherein the dither is injected by: connecting a first capacitor (CCal) to a first or second reference voltage (Vref+, Vref-) in accordance with a randomly generated number when the switched capacitor network is disconnected from the input signal source during a hold phase of the switched capacitor network, and connecting the first capacitor in parallel with the capacitors of the switched capacitor network when the switched capacitor network is connected to the input signal source to sample an input signal (Vin+, Vin-) during a subsequent sampling phase of the switched capacitor network, such that in the presence of kickback between the switched capacitor network and the input signal source, at least some charge from the first capacitor is sampled by the switched capacitor network with the input signal at the end of the subsequent sampling phase; connecting a first capacitor (CCal) to a first or second reference voltage (Vref+, Vref-) in accordance with a randomly generated number when the switched capacitor network is disconnected from the input signal source during a hold phase of the switched capacitor network, and connecting the first capacitor in parallel with the capacitors of the switched capacitor network when the switched capacitor network is connected to the input signal source to sample an input signal (Vin+, Vin-) during a subsequent sampling phase of the switched capacitor network, such that in the presence of kickback between the switched capacitor network and the input signal source, at least some charge from the first capacitor is sampled by the switched capacitor network with the input signal at the end of the subsequent sampling phase; after injecting the dither, determining at least one gain coefficient by correlating the random number and an overall digital output of the ADC corresponding to the input signal sampled during the subsequent sampling phase, wherein the gain coefficient is indicative of a transfer function of the kick-back; generating, as a function of the at least one gain coefficient, the random number and a digital output of the first stage corresponding to a previous input sample, at least two correction values corresponding to a contribution of the kick-back to the overall digital output of the ADC; and subtracting the correction values from the overall digital output of the ADC, thereby correcting for kick-back errors in the overall digital output.