An array substrate, comprising a first base material, and a display circuit layer and a recognition circuit layer laminated on the first base material; the display circuit layer comprising a plurality of gate lines, a plurality of data lines, and a plurality of thin-film transistors, TFT, projections of the plurality of gate lines on the first base material and projections of the plurality of data lines on the first base material defining a plurality of sub-pixel projection areas, and each of projections of the plurality of TFTs on the first base material falling into a corresponding area of the plurality of sub-pixel projection areas; and the recognition circuit layer comprising a plurality of photoelectric sensors, projections of the plurality of photoelectric sensors on the first base material falling into a corresponding area of the sub-pixel projection areas, and each of the plurality of photoelectric sensors comprising a first electrode, a photosensitive layer, and a second electrode sequentially laminated one on the other and each of the plurality of photoelectric sensors being configured to sense target lights carrying user fingerprint information; wherein the first electrode is located on one side of the photosensitive layer towards the first base material; and the second electrode is located on one side of the photosensitive layer away from the first electrode, and the second electrode is made of a transparent conductive material; wherein the recognition circuit layer further comprises a plurality of output wires, the plurality of output wires being respectively coupled with first electrodes of the plurality of photoelectric sensors, and the plurality of output wires and the first electrodes of the plurality of photoelectric sensors being disposed on the same layer and made of the same material; wherein projections of the plurality of output wires on the first base material and the projections of the plurality of data lines on the first base material are partially overlapped; or the projections of the plurality of output wires on the first base material and the projections of the plurality of gate lines on the first base material are partially overlapped. the display circuit layer comprising a plurality of gate lines, a plurality of data lines, and a plurality of thin-film transistors, TFT, projections of the plurality of gate lines on the first base material and projections of the plurality of data lines on the first base material defining a plurality of sub-pixel projection areas, and each of projections of the plurality of TFTs on the first base material falling into a corresponding area of the plurality of sub-pixel projection areas; and the recognition circuit layer comprising a plurality of photoelectric sensors, projections of the plurality of photoelectric sensors on the first base material falling into a corresponding area of the sub-pixel projection areas, and each of the plurality of photoelectric sensors comprising a first electrode, a photosensitive layer, and a second electrode sequentially laminated one on the other and each of the plurality of photoelectric sensors being configured to sense target lights carrying user fingerprint information; wherein the first electrode is located on one side of the photosensitive layer towards the first base material; and the second electrode is located on one side of the photosensitive layer away from the first electrode, and the second electrode is made of a transparent conductive material; wherein the recognition circuit layer further comprises a plurality of output wires, the plurality of output wires being respectively coupled with first electrodes of the plurality of photoelectric sensors, and the plurality of output wires and the first electrodes of the plurality of photoelectric sensors being disposed on the same layer and made of the same material; wherein projections of the plurality of output wires on the first base material and the projections of the plurality of data lines on the first base material are partially overlapped; or the projections of the plurality of output wires on the first base material and the projections of the plurality of gate lines on the first base material are partially overlapped.