A semiconductor device comprising a negative-voltage level shifter, wherein the negative-voltage level shifter includes a first level shifter that converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage, the first medium voltage being higher than the first power-supply voltage and being lower than a second power-supply voltage, wherein the negative-voltage level shifter further includes a second level shifter that converts a low level of an output signal of the first level shifter from a third power-supply voltage to a fourth power-supply voltage lower than the third power-supply voltage, and characterized by further comprising a first medium-voltage generating circuit (133; 133A) that generates the first medium voltage, and wherein the first medium-voltage generating circuit (133; 133A) includes a first NMOS (N-channel Metal Oxide Semiconductor) transistor coupled between a first medium-voltage node outputting the first medium voltage and a first power-supply node to which the second power-supply voltage is supplied, and a first PMOS (P-channel MOS) transistor that is coupled to the first medium-voltage node to be used as a path for discharging electric charges of the first medium-voltage node, wherein the negative-voltage level shifter further includes a first control-signal generating circuit (134; 134A) that generates a first control signal (biasg) and a second control signal (biasc), the first control signal controlling a gate voltage of the first NMOS transistor, the second control signal controlling a gate voltage of the first PMOS transistor, wherein the first level shifter includes a third PMOS transistor (MNINP) and a third NMOS transistor (MNINN) to which the input signal is input, and wherein the first control-signal generating circuit includes a fourth PMOS transistor that is a replica of the third PMOS transistor (MNINP), a fourth NMOS transistor that is a replica of the third NMOS transistor (MNINN), and a current mirror circuit for supplying currents having a predetermined current ratio to the fourth PMOS transistor and the fourth NMOS transistor. wherein the negative-voltage level shifter includes a first level shifter that converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage, the first medium voltage being higher than the first power-supply voltage and being lower than a second power-supply voltage, wherein the negative-voltage level shifter further includes a second level shifter that converts a low level of an output signal of the first level shifter from a third power-supply voltage to a fourth power-supply voltage lower than the third power-supply voltage, and characterized by further comprising a first medium-voltage generating circuit (133; 133A) that generates the first medium voltage, and wherein the first medium-voltage generating circuit (133; 133A) includes a first NMOS (N-channel Metal Oxide Semiconductor) transistor coupled between a first medium-voltage node outputting the first medium voltage and a first power-supply node to which the second power-supply voltage is supplied, and a first PMOS (P-channel MOS) transistor that is coupled to the first medium-voltage node to be used as a path for discharging electric charges of the first medium-voltage node, wherein the negative-voltage level shifter further includes a first control-signal generating circuit (134; 134A) that generates a first control signal (biasg) and a second control signal (biasc), the first control signal controlling a gate voltage of the first NMOS transistor, the second control signal controlling a gate voltage of the first PMOS transistor, wherein the first level shifter includes a third PMOS transistor (MNINP) and a third NMOS transistor (MNINN) to which the input signal is input, and wherein the first control-signal generating circuit includes a fourth PMOS transistor that is a replica of the third PMOS transistor (MNINP), a fourth NMOS transistor that is a replica of the third NMOS transistor (MNINN), and a current mirror circuit for supplying currents having a predetermined current ratio to the fourth PMOS transistor and the fourth NMOS transistor.