A gate driving circuit comprising multiple cascaded stages each consisting of one shift register unit, the shift register unit comprising: an input module connected to a first signal input terminal (INPUT) and a pull-up control node respectively, and configured to control potential of the pull-up control node according to a signal input by the first signal input terminal (INPUT); a pull-up module connected to a first clock signal terminal (CLKB), the pull-up control node and a signal output terminal (OUTPUT) of a present stage respectively, and configured to make the signal output terminal (OUTPUT) of the present stage output a signal of the first clock signal terminal (CLKB) under the control of the pull-up control node; a pull-down control module connected to a voltage terminal, the pull-up control node, the first signal input terminal (INPUT), and a pull-down control node respectively, and configured to control the level of the pull-down control node according to the signal input by the first signal input terminal (INPUT) and the level of the pull-up control node; a first pull-down module connected to the voltage terminal, the pull-down control node and the signal output terminal (OUTPUT) of the present stage respectively, and configured to pull down a signal output by the signal output terminal (OUTPUT) of the present stage to a low level under the control of the pull-down control node; a second pull-down module connected to the voltage terminal, a second clock signal terminal and the signal output terminal (OUTPUT) of the present stage respectively, and configured to pull down the signal output by the signal output terminal (OUTPUT) of the present stage to a low level according to a signal input by the second clock signal terminal; a reset module connected to the voltage terminal, a second signal input terminal (RESET), the pull-up control node and the signal output terminal (OUTPUT) of the present stage respectively, and configured to reset the potential of the pull-up control node and the signal output by the signal output terminal (OUTPUT) of the present stage according to a signal input by the second signal input terminal (RESET); characterised in that a first trigger transistor whose first electrode is connected to the first clock signal terminal (CLKB), gate is connected to the pull-up control node, and second electrode is connected to a signal trigger terminal (COUT) of an adjacent next stage; and a second trigger transistor whose first electrode is connected to the second electrode of the first trigger transistor, gate is connected to the pull-down control node, and second electrode is connected to the voltage terminal; and the first signal input terminal (INPUT) of each shift register unit except for the first stage is connected to the signal trigger terminal (COUT) of the shift register unit of its adjacent previous stage. an input module connected to a first signal input terminal (INPUT) and a pull-up control node respectively, and configured to control potential of the pull-up control node according to a signal input by the first signal input terminal (INPUT); a pull-up module connected to a first clock signal terminal (CLKB), the pull-up control node and a signal output terminal (OUTPUT) of a present stage respectively, and configured to make the signal output terminal (OUTPUT) of the present stage output a signal of the first clock signal terminal (CLKB) under the control of the pull-up control node; a pull-down control module connected to a voltage terminal, the pull-up control node, the first signal input terminal (INPUT), and a pull-down control node respectively, and configured to control the level of the pull-down control node according to the signal input by the first signal input terminal (INPUT) and the level of the pull-up control node; a first pull-down module connected to the voltage terminal, the pull-down control node and the signal output terminal (OUTPUT) of the present stage respectively, and configured to pull down a signal output by the signal output terminal (OUTPUT) of the present stage to a low level under the control of the pull-down control node; a second pull-down module connected to the voltage terminal, a second clock signal terminal and the signal output terminal (OUTPUT) of the present stage respectively, and configured to pull down the signal output by the signal output terminal (OUTPUT) of the present stage to a low level according to a signal input by the second clock signal terminal; a reset module connected to the voltage terminal, a second signal input terminal (RESET), the pull-up control node and the signal output terminal (OUTPUT) of the present stage respectively, and configured to reset the potential of the pull-up control node and the signal output by the signal output terminal (OUTPUT) of the present stage according to a signal input by the second signal input terminal (RESET); characterised in that a first trigger transistor whose first electrode is connected to the first clock signal terminal (CLKB), gate is connected to the pull-up control node, and second electrode is connected to a signal trigger terminal (COUT) of an adjacent next stage; and a second trigger transistor whose first electrode is connected to the second electrode of the first trigger transistor, gate is connected to the pull-down control node, and second electrode is connected to the voltage terminal; and the first signal input terminal (INPUT) of each shift register unit except for the first stage is connected to the signal trigger terminal (COUT) of the shift register unit of its adjacent previous stage.