A processor element (1, 2, 3, 4, 5) comprising: an arithmetic unit (11, 11a, 11b, 11c, 11n) that performs arithmetic processing based on a function in which an instruction set is implemented, the instruction set being generated according to a program; a register (12, 12a, 12b, 12c, 12n) that stores an argument of the function; a first bypass switch (13, 13a, 13b, 13n) that switches whether to bypass the arithmetic unit (11, 11a, 11b, 11c, 11n); a second bypass switch (14, 14a, 14b, 14n) that switches whether to bypass the register (12, 12a, 12b, 12c, 12n); a plurality of function units (20, 20a, 20b, 20n); a connection setting unit for switching connection of one of the plurality of function units (20, 20a, 20b, 20n) comprising the register (12, 12a, 12b, 12c, 12n), the arithmetic unit (11, 11a, 11b, 11c, 11n), the first bypass switch (13, 13a, 13b, 13n) and the second bypass switch (14, 14a, 14b, 14n); a multiplexer that switches an input to the connection setting unit; a demultiplexer that switches an output destination of an output from the connection setting unit; and a selection unit for performing, according to a state, switching of the first bypass switch (13, 13a, 13b, 13n), the second bypass switch (14, 14a, 14b, 14n), the connection setting unit, a multiplexer, and a demultiplexer, thereby selecting a required function unit associated with the state from among the plurality of function units (20, 20a, 20b, 20n) and selecting a processing sequence of the required function unit, wherein in a case where the first bypass switch (13, 13a, 13b, 13n) is instructed to bypass the arithmetic unit (11, 11a, 11b, 11c, 11n), input to the arithmetic unit (11, 11a, 11b, 11c, 11n) is input to the register (12, 12a, 12b, 12c, 12n), and in a case where the second bypass switch (14, 14a, 14b, 14n) is instructed to bypass the register (12, 12a, 12b, 12c, 12n), output of the arithmetic unit (11, 11a, 11b, 11c, 11n) is input to the connection setting unit. an arithmetic unit (11, 11a, 11b, 11c, 11n) that performs arithmetic processing based on a function in which an instruction set is implemented, the instruction set being generated according to a program; a register (12, 12a, 12b, 12c, 12n) that stores an argument of the function; a first bypass switch (13, 13a, 13b, 13n) that switches whether to bypass the arithmetic unit (11, 11a, 11b, 11c, 11n); a second bypass switch (14, 14a, 14b, 14n) that switches whether to bypass the register (12, 12a, 12b, 12c, 12n); a plurality of function units (20, 20a, 20b, 20n); a connection setting unit for switching connection of one of the plurality of function units (20, 20a, 20b, 20n) comprising the register (12, 12a, 12b, 12c, 12n), the arithmetic unit (11, 11a, 11b, 11c, 11n), the first bypass switch (13, 13a, 13b, 13n) and the second bypass switch (14, 14a, 14b, 14n); a multiplexer that switches an input to the connection setting unit; a demultiplexer that switches an output destination of an output from the connection setting unit; and a selection unit for performing, according to a state, switching of the first bypass switch (13, 13a, 13b, 13n), the second bypass switch (14, 14a, 14b, 14n), the connection setting unit, a multiplexer, and a demultiplexer, thereby selecting a required function unit associated with the state from among the plurality of function units (20, 20a, 20b, 20n) and selecting a processing sequence of the required function unit, wherein in a case where the first bypass switch (13, 13a, 13b, 13n) is instructed to bypass the arithmetic unit (11, 11a, 11b, 11c, 11n), input to the arithmetic unit (11, 11a, 11b, 11c, 11n) is input to the register (12, 12a, 12b, 12c, 12n), and in a case where the second bypass switch (14, 14a, 14b, 14n) is instructed to bypass the register (12, 12a, 12b, 12c, 12n), output of the arithmetic unit (11, 11a, 11b, 11c, 11n) is input to the connection setting unit.