A modulation apparatus using a mixed-radix fast Fourier transform. FFT, comprising: two memories (102, 103) each configured to include four banks; a first data exchange configured to obtain read symbols by reading one symbol from each of the four banks included in one of the two memories, and output the read symbols; a butterfly configured to perform butterfly calculation for the read symbols in a radix-4 mode or a radix-2 mode according to a number 2" of the read symbols, and output an output sequence including calculated symbols being a result of the butterfly calculation; a second data exchange configured to store the calculated symbols in one of the two memories; and an address generator configured to control an output of the second data exchange according to an in-place calculation in which when a symbol read from the first data exchange is output through the second data exchange after being calculated, a bank and an address where the symbol was read from the first data exchange are identical to an output bank and an output address of the second data exchange, wherein, as a result of the in-place calculation, a n-bit counter of the 2" bits of the output sequence is in a symmetric reverse form if n is even, and in an asymmetric reverse form if n is odd, wherein data exchange is performed for any n to ensure that any asymmetric reverse form is converted into a symmetric reverse form by digit reversing the high two bits with the low two bits and by bit reversing all the intermediate bits between the high two bits and the low two bits, wherein the address generator is further configured to determine a bank index for writing the next input symbol to be computed in the banks of one of the two memories to enable simultaneously performing input and output in the memories, by performing modulo-4 addition on 2-bit digits of the n-bit counter if n is even, and, if n is odd, by: exchanging positions of the two most significant bits of the n-bit counter; dividing the position-exchanged bits of the n-bit counter into 2-bit digits from low performing modulo-4 addition on the divided 2-bit digits and on the remaining most significant bit; and performing a final modulo-4 addition on results of the modulo-4 addition. two memories (102, 103) each configured to include four banks; a first data exchange configured to obtain read symbols by reading one symbol from each of the four banks included in one of the two memories, and output the read symbols; a butterfly configured to perform butterfly calculation for the read symbols in a radix-4 mode or a radix-2 mode according to a number 2" of the read symbols, and output an output sequence including calculated symbols being a result of the butterfly calculation; a second data exchange configured to store the calculated symbols in one of the two memories; and an address generator configured to control an output of the second data exchange according to an in-place calculation in which when a symbol read from the first data exchange is output through the second data exchange after being calculated, a bank and an address where the symbol was read from the first data exchange are identical to an output bank and an output address of the second data exchange, wherein, as a result of the in-place calculation, a n-bit counter of the 2" bits of the output sequence is in a symmetric reverse form if n is even, and in an asymmetric reverse form if n is odd, wherein data exchange is performed for any n to ensure that any asymmetric reverse form is converted into a symmetric reverse form by digit reversing the high two bits with the low two bits and by bit reversing all the intermediate bits between the high two bits and the low two bits, wherein the address generator is further configured to determine a bank index for writing the next input symbol to be computed in the banks of one of the two memories to enable simultaneously performing input and output in the memories, by performing modulo-4 addition on 2-bit digits of the n-bit counter if n is even, and, if n is odd, by: exchanging positions of the two most significant bits of the n-bit counter; dividing the position-exchanged bits of the n-bit counter into 2-bit digits from low performing modulo-4 addition on the divided 2-bit digits and on the remaining most significant bit; and performing a final modulo-4 addition on results of the modulo-4 addition. exchanging positions of the two most significant bits of the n-bit counter; dividing the position-exchanged bits of the n-bit counter into 2-bit digits from low performing modulo-4 addition on the divided 2-bit digits and on the remaining most significant bit; and performing a final modulo-4 addition on results of the modulo-4 addition.