A magnetic memory including a magnetoresistive element comprising: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer in a direction intersecting with a stacking direction of the free layer and the pin layer and is configured to apply a pressure to the magnetostrictive layer; and an electrode, wherein the electrode is located so as to surround at least a part of the piezoelectric substance and wherein the piezoelectric substance is dielectrically polarized in a direction from the magnetostrictive layer to the electrode or a direction from the electrode to the magnetostrictive layer; the magnetic memory including further a write circuit configured to apply voltages to the electrode, the free layer and the pin layer, wherein the voltage applied to the electrode is different from the voltage applied to the free layer and the voltage applied to the pin layer, the write circuit being configured to apply a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer, wherein the piezoelectric substance is configured to, in response to the voltages applied by the write circuit, apply a pressure to the magnetostrictive layer in an identical direction when a parallel state is rewritten to an antiparallel state and when the antiparallel state is rewritten to the parallel state, a magnetization direction of the free layer being parallel to that of the pin layer in the parallel state, the magnetization direction of the free layer being opposite to that of the pin layer in the antiparallel state; and wherein the write circuit is configured to apply a first voltage to the pin layer with respect to the free layer and a second voltage to the electrode with respect to the free layer to write the parallel state and to apply a third voltage to the pin layer with respect to the free layer and a fourth voltage to the electrode with respect to the free layer to write the antiparallel state, wherein the polarities of the first and third voltages are reversed and the polarities of the second and fourth voltages are the same. a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer in a direction intersecting with a stacking direction of the free layer and the pin layer and is configured to apply a pressure to the magnetostrictive layer; and an electrode, wherein the electrode is located so as to surround at least a part of the piezoelectric substance and wherein the piezoelectric substance is dielectrically polarized in a direction from the magnetostrictive layer to the electrode or a direction from the electrode to the magnetostrictive layer; the magnetic memory including further a write circuit configured to apply voltages to the electrode, the free layer and the pin layer, wherein the voltage applied to the electrode is different from the voltage applied to the free layer and the voltage applied to the pin layer, the write circuit being configured to apply a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer, wherein the piezoelectric substance is configured to, in response to the voltages applied by the write circuit, apply a pressure to the magnetostrictive layer in an identical direction when a parallel state is rewritten to an antiparallel state and when the antiparallel state is rewritten to the parallel state, a magnetization direction of the free layer being parallel to that of the pin layer in the parallel state, the magnetization direction of the free layer being opposite to that of the pin layer in the antiparallel state; and wherein the write circuit is configured to apply a first voltage to the pin layer with respect to the free layer and a second voltage to the electrode with respect to the free layer to write the parallel state and to apply a third voltage to the pin layer with respect to the free layer and a fourth voltage to the electrode with respect to the free layer to write the antiparallel state, wherein the polarities of the first and third voltages are reversed and the polarities of the second and fourth voltages are the same.