A magnetic random access memory, hence forth termed MRAM, comprising: a resistive memory having a first bank having a plurality of I/Os (202A, 202B, 302A, 302B, 402A, 402B), and a second bank having another plurality of I/Os (204A, 204B, 304A, 304B, 404A, 404B), each I/O having an array of resistive memory cells; a reference node; and a read mode switch circuit (2062, 2064), configured to selectively switch between a first read mode and a second read mode, wherein the first read mode couples a selectable one of the resistive memory cells of a first I/O of the first bank to a first read node, couples a first two or more of the resistive memory cells of the second bank to the reference node, the second read mode couples a selectable one of the resistive memory cells of a first I/O of the second bank's plurality of I/Os to the first read node, couples a second two or more of the resistive memory cells of the first bank to the reference node, one of the first two or more of the resistive memory cells is in the first I/O of the second bank's plurality of I/Os and is a designated binary 0 reference cell programmed to a state representing a binary 0, one of the second two or more of the resistive memory cells is in the first I/O of the first bank's plurality of I/Os, and characterised in that the first read mode couples a selectable one of the resistive memory cells of a second I/O of the first bank's plurality of I/Os to a second read node; the second read mode couples a selectable one of the resistive memory cells of a second I/O of the second bank's plurality of I/Os to the second read node; another of the first two or more of the resistive memory cells is in a second I/O of the second bank's plurality of I/Os and is a designated binary 1 reference cell programmed to a state representing a binary 1; and another of the second two or more of the resistive memory cells is in the second I/O of the first bank's plurality of I/Os. a resistive memory having a first bank having a plurality of I/Os (202A, 202B, 302A, 302B, 402A, 402B), and a second bank having another plurality of I/Os (204A, 204B, 304A, 304B, 404A, 404B), each I/O having an array of resistive memory cells; a reference node; and a read mode switch circuit (2062, 2064), configured to selectively switch between a first read mode and a second read mode, wherein the first read mode couples a selectable one of the resistive memory cells of a first I/O of the first bank to a first read node, couples a first two or more of the resistive memory cells of the second bank to the reference node, the second read mode couples a selectable one of the resistive memory cells of a first I/O of the second bank's plurality of I/Os to the first read node, couples a second two or more of the resistive memory cells of the first bank to the reference node, one of the first two or more of the resistive memory cells is in the first I/O of the second bank's plurality of I/Os and is a designated binary 0 reference cell programmed to a state representing a binary 0, one of the second two or more of the resistive memory cells is in the first I/O of the first bank's plurality of I/Os, and characterised in that the first read mode couples a selectable one of the resistive memory cells of a second I/O of the first bank's plurality of I/Os to a second read node; the second read mode couples a selectable one of the resistive memory cells of a second I/O of the second bank's plurality of I/Os to the second read node; another of the first two or more of the resistive memory cells is in a second I/O of the second bank's plurality of I/Os and is a designated binary 1 reference cell programmed to a state representing a binary 1; and another of the second two or more of the resistive memory cells is in the second I/O of the first bank's plurality of I/Os.