A PWM signal generating apparatus configured to generate a PWM signal, comprising: a clock generating circuit configured to generate a plurality of clock signals having same frequency and mutually different phases; a conversion circuit configured to convert input data which indicates a pulse width of the PWM signal into a bit pattern including a plurality of bit data; a buffer circuit configured to temporarily store the bit pattern converted by the conversion circuit, and output a plurality of bit data on an uppermost bit side included in the bit pattern stored in the buffer circuit in synchronization with one clock signal of the plurality of clock signals; an encoding circuit configured to generate a plurality of encoded signals synchronized with respective clocks of the plurality of clock signals generated by the clock generating circuit based on the plurality of bit data output from the buffer circuit; and a decoding circuit configured to generate the PWM signal from the plurality of encoded signals output from the encoding circuit, characterized in that the encoding circuit comprises a plurality of encoders into which respective different clock signals of the plurality of clock signals and respective parts of the plurality of bit data are input, the parts of the plurality of bit data output from the buffer circuit are out of phase with each other and input to the plurality of encoders, respectively, the plurality of encoders are configured to generate the plurality of encoded signals based on the input bit data, and the decoding circuit comprises an exclusive OR circuit to obtain an exclusive OR of the plurality of encoded signals generated by the plurality of encoders to generate the PWM signal. a clock generating circuit configured to generate a plurality of clock signals having same frequency and mutually different phases; a conversion circuit configured to convert input data which indicates a pulse width of the PWM signal into a bit pattern including a plurality of bit data; a buffer circuit configured to temporarily store the bit pattern converted by the conversion circuit, and output a plurality of bit data on an uppermost bit side included in the bit pattern stored in the buffer circuit in synchronization with one clock signal of the plurality of clock signals; an encoding circuit configured to generate a plurality of encoded signals synchronized with respective clocks of the plurality of clock signals generated by the clock generating circuit based on the plurality of bit data output from the buffer circuit; and a decoding circuit configured to generate the PWM signal from the plurality of encoded signals output from the encoding circuit, characterized in that the encoding circuit comprises a plurality of encoders into which respective different clock signals of the plurality of clock signals and respective parts of the plurality of bit data are input, the parts of the plurality of bit data output from the buffer circuit are out of phase with each other and input to the plurality of encoders, respectively, the plurality of encoders are configured to generate the plurality of encoded signals based on the input bit data, and the decoding circuit comprises an exclusive OR circuit to obtain an exclusive OR of the plurality of encoded signals generated by the plurality of encoders to generate the PWM signal.