A method for testing a circuit including a resistance realization part configured to realize a resistance equal to a desired resistance by one of combinations of a plurality of semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5; 32p-0 to 32p-5), wherein the plurality of semiconductor devices comprises a combination of a plurality of pairs of first (31 n-0 to 31 n-5; 32n-0 to 32n-5)) and second (32p-0 to 32p-5) semiconductor devices of different channel types, the method including the step of: (a) verifying whether a resistance range realizable by the combinations of the semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5; 32p-0 to 32p-5) includes the desired resistance; wherein said step (a) comprises the steps of: determining whether a resistance realized by a predetermined first combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is higher than the desired resistance, and determining whether a resistance realized by a predetermined second combination of the first semiconductor devices is lower than the desired resistance, the resistance realized by the predetermined second combination being lower than the resistance realized by the predetermined first combination; and determining whether a resistance realized by a predetermined third combination of the second semiconductor devices (32p-0 to 32p-5) for realizing a higher resistance than the predetermined first combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is higher than the resistance realized by the predetermined first combination, and determining whether a resistance realized by a predetermined fourth combination of the second semiconductor devices (32p-0 to 32p-5) for realizing a lower resistance than the predetermined second combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is lower than the resistance realized by the predetermined second combination. (a) verifying whether a resistance range realizable by the combinations of the semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5; 32p-0 to 32p-5) includes the desired resistance; wherein said step (a) comprises the steps of: determining whether a resistance realized by a predetermined first combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is higher than the desired resistance, and determining whether a resistance realized by a predetermined second combination of the first semiconductor devices is lower than the desired resistance, the resistance realized by the predetermined second combination being lower than the resistance realized by the predetermined first combination; and determining whether a resistance realized by a predetermined third combination of the second semiconductor devices (32p-0 to 32p-5) for realizing a higher resistance than the predetermined first combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is higher than the resistance realized by the predetermined first combination, and determining whether a resistance realized by a predetermined fourth combination of the second semiconductor devices (32p-0 to 32p-5) for realizing a lower resistance than the predetermined second combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is lower than the resistance realized by the predetermined second combination. determining whether a resistance realized by a predetermined first combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is higher than the desired resistance, and determining whether a resistance realized by a predetermined second combination of the first semiconductor devices is lower than the desired resistance, the resistance realized by the predetermined second combination being lower than the resistance realized by the predetermined first combination; and determining whether a resistance realized by a predetermined third combination of the second semiconductor devices (32p-0 to 32p-5) for realizing a higher resistance than the predetermined first combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is higher than the resistance realized by the predetermined first combination, and determining whether a resistance realized by a predetermined fourth combination of the second semiconductor devices (32p-0 to 32p-5) for realizing a lower resistance than the predetermined second combination of the first semiconductor devices (31 n-0 to 31 n-5; 32n-0 to 32n-5) is lower than the resistance realized by the predetermined second combination.