A multiplier-adder to calculate a sum of an integer third operand with a product of integer first and second operands, the multiplier-adder comprising: a multiplier having first and second inputs for receiving said first and second operands, a first output for providing a sum signal, and a second output for providing a carry signal; a biased addend generator having first and second inputs for receiving sign bits of said first and second operands, a third input for receiving said third operand, a first output for providing a biased addend signal, and a second output for providing a signal representative of a sign of a product of said first and second operands; an adder having first and second inputs coupled to said first and second outputs of said multiplier, a third input for receiving said biased addend signal, and an output for providing a signal representative of a sum of said first, second, and third inputs; a multiplexer having a first input coupled to said first output of said adder to receive the least significant portion of the sum of said first, second, and third inputs, a second input for receiving a saturated minimum value, a third input for receiving a saturated maximum value, a control input and an output for providing a multiply-add result with saturation signal; and select logic having a first input coupled to said second output of said biased addend generator and a second input for receiving a signal representative of a sign of said sum represented by said signal provided by said adder, and an output coupled to said control input of said multiplexer; and wherein said bias addend signal causes any result that would have exceeded the range associated with the least significant portion of the sum to provide an indication of an underflow or an overflow in a sign bit of said signal output by said adder. a multiplier having first and second inputs for receiving said first and second operands, a first output for providing a sum signal, and a second output for providing a carry signal; a biased addend generator having first and second inputs for receiving sign bits of said first and second operands, a third input for receiving said third operand, a first output for providing a biased addend signal, and a second output for providing a signal representative of a sign of a product of said first and second operands; an adder having first and second inputs coupled to said first and second outputs of said multiplier, a third input for receiving said biased addend signal, and an output for providing a signal representative of a sum of said first, second, and third inputs; a multiplexer having a first input coupled to said first output of said adder to receive the least significant portion of the sum of said first, second, and third inputs, a second input for receiving a saturated minimum value, a third input for receiving a saturated maximum value, a control input and an output for providing a multiply-add result with saturation signal; and select logic having a first input coupled to said second output of said biased addend generator and a second input for receiving a signal representative of a sign of said sum represented by said signal provided by said adder, and an output coupled to said control input of said multiplexer; and wherein said bias addend signal causes any result that would have exceeded the range associated with the least significant portion of the sum to provide an indication of an underflow or an overflow in a sign bit of said signal output by said adder.