An order management device for managing orders in response to input commands, each command comprising a command operation identifier, an object identifier and data related to an order, an order comprising at least a value and a quantity information and being related to an object, the order management device being implemented on an integrated circuit, wherein said order management device comprises: - an order aggregation memory associated with one or more objects, said order aggregation memory being configured to aggregate orders, said order management device being configured to associate the aggregated orders with limits in said order aggregation memory, in response to input commands related to said orders, each limit being associated with a value and a quantity, each order being aggregated into the limit that has the same value as the order value, the quantity associated with a limit corresponding to the sum of the quantities of the orders which are aggregated, characterised in that said order aggregation memory comprises: - a first data structure having a fixed size, said first data structure being configured to store orders associated with a set of P limits, the P limits being a subset of N limits and being selected based upon performance selection criteria, and - a second data structure comprising the limits in the list of N limits that are not contained in the subset P, the entries in said second data structure being allocated dynamically, wherein said order book management device further comprises a first management core configured in said integrated circuit to process an input command related to an order, update said first data structure in response to the processing of said input command and generate at least one update command; - a second management core configured in said integrated circuit to update the second data structure in response to said update command received from said first management core, wherein the first management core is configured to process input commands independently of the update command processing performed by the second processing core, the first management core being further configured to process the input command in a fixed number of clock cycles. - an order aggregation memory associated with one or more objects, said order aggregation memory being configured to aggregate orders, said order management device being configured to associate the aggregated orders with limits in said order aggregation memory, in response to input commands related to said orders, each limit being associated with a value and a quantity, each order being aggregated into the limit that has the same value as the order value, the quantity associated with a limit corresponding to the sum of the quantities of the orders which are aggregated, said order aggregation memory comprises: - a first data structure having a fixed size, said first data structure being configured to store orders associated with a set of P limits, the P limits being a subset of N limits and being selected based upon performance selection criteria, and - a second data structure comprising the limits in the list of N limits that are not contained in the subset P, the entries in said second data structure being allocated dynamically, - a first data structure having a fixed size, said first data structure being configured to store orders associated with a set of P limits, the P limits being a subset of N limits and being selected based upon performance selection criteria, and - a second data structure comprising the limits in the list of N limits that are not contained in the subset P, the entries in said second data structure being allocated dynamically, wherein said order book management device further comprises a first management core configured in said integrated circuit to process an input command related to an order, update said first data structure in response to the processing of said input command and generate at least one update command; - a second management core configured in said integrated circuit to update the second data structure in response to said update command received from said first management core, - a second management core configured in said integrated circuit to update the second data structure in response to said update command received from said first management core, wherein the first management core is configured to process input commands independently of the update command processing performed by the second processing core, the first management core being further configured to process the input command in a fixed number of clock cycles.