A method of operating an apparatus (100/130), comprising: advancing a timer; and establishing a negative potential in a body of a memory cell of a memory in response to a value of the timer having a desired value; wherein the memory cell is a particular memory cell of a string of series-connected memory cells, with each memory cell of the string of series-connected memory cells connected to a respective word line of a plurality of word lines; wherein the memory cell of the string of series-connected memory cells is formed adjacent a semiconductor pillar, a portion of which acts as the body of the memory cell; and wherein establishing the negative potential in the body of the memory cell comprises: applying a reference potential to each word line of the plurality of word lines, to a first select line connected to a first select gate selectively connecting a memory cell located at one end of the string of series-connected memory cells to a source, to a second select line connected to a second select gate selectively connecting the memory cell located at the other end of the string of series-connected memory cells to a bit line, and to the source; and transitioning the source to a second voltage level lower than the reference potential and sufficient to establish the negative potential in the body of the memory cell with the plurality of word lines, the first select line and the second select line at the reference potential. advancing a timer; and establishing a negative potential in a body of a memory cell of a memory in response to a value of the timer having a desired value; wherein the memory cell is a particular memory cell of a string of series-connected memory cells, with each memory cell of the string of series-connected memory cells connected to a respective word line of a plurality of word lines; wherein the memory cell of the string of series-connected memory cells is formed adjacent a semiconductor pillar, a portion of which acts as the body of the memory cell; and wherein establishing the negative potential in the body of the memory cell comprises: applying a reference potential to each word line of the plurality of word lines, to a first select line connected to a first select gate selectively connecting a memory cell located at one end of the string of series-connected memory cells to a source, to a second select line connected to a second select gate selectively connecting the memory cell located at the other end of the string of series-connected memory cells to a bit line, and to the source; and transitioning the source to a second voltage level lower than the reference potential and sufficient to establish the negative potential in the body of the memory cell with the plurality of word lines, the first select line and the second select line at the reference potential. applying a reference potential to each word line of the plurality of word lines, to a first select line connected to a first select gate selectively connecting a memory cell located at one end of the string of series-connected memory cells to a source, to a second select line connected to a second select gate selectively connecting the memory cell located at the other end of the string of series-connected memory cells to a bit line, and to the source; and transitioning the source to a second voltage level lower than the reference potential and sufficient to establish the negative potential in the body of the memory cell with the plurality of word lines, the first select line and the second select line at the reference potential.