A signal processing device comprising a first discrete time analog signal infinite impulse response filter section, said first filter section comprising: an input for accepting a time series of input signal values; an output for providing a time series of output signal values; an analog signal storage section (1030, 1040) comprising a first storage section and a second storage section, each storage section comprising a plurality of capacitors (1076, 1082); switching circuit elements configurable to (a) charge successive subsets of capacitors of a first plurality of subsets of the plurality of capacitors according to successive values of the input signal values, wherein the subsets of capacitors of the first plurality of subsets are formed from capacitors of the first storage section, (b) couple capacitors of successive subsets of capacitors of a second plurality of subsets of the plurality of capacitors to one another to form successive values of a time series of intermediate signal values based on a shared total charge of the coupled capacitors of each successive subset of capacitors of the second plurality of subsets, wherein each subset of capacitors of the second plurality of subsets is formed from capacitors of both the first storage section and the second storage section, and (c) charge successive subsets of capacitors of a third plurality of subsets of the plurality of capacitors according to successive values of the output signal values, wherein the subsets of capacitors of the third plurality of subsets are formed from capacitors of the second storage section; an amplifier for forming the time series of output signal values according to the time series of intermediate values and for charging the successive subsets of the third plurality of subsets of capacitors according to the successive output signal values; and control logic for controlling configuration of the switching circuit elements in successive phases of a clock signal to form the time series of output signal values as an application of a desired infinite impulse response filter to the time series of input signal values. an input for accepting a time series of input signal values; an output for providing a time series of output signal values; an analog signal storage section (1030, 1040) comprising a first storage section and a second storage section, each storage section comprising a plurality of capacitors (1076, 1082); switching circuit elements configurable to (a) charge successive subsets of capacitors of a first plurality of subsets of the plurality of capacitors according to successive values of the input signal values, wherein the subsets of capacitors of the first plurality of subsets are formed from capacitors of the first storage section, (b) couple capacitors of successive subsets of capacitors of a second plurality of subsets of the plurality of capacitors to one another to form successive values of a time series of intermediate signal values based on a shared total charge of the coupled capacitors of each successive subset of capacitors of the second plurality of subsets, wherein each subset of capacitors of the second plurality of subsets is formed from capacitors of both the first storage section and the second storage section, and (c) charge successive subsets of capacitors of a third plurality of subsets of the plurality of capacitors according to successive values of the output signal values, wherein the subsets of capacitors of the third plurality of subsets are formed from capacitors of the second storage section; (a) charge successive subsets of capacitors of a first plurality of subsets of the plurality of capacitors according to successive values of the input signal values, wherein the subsets of capacitors of the first plurality of subsets are formed from capacitors of the first storage section, (b) couple capacitors of successive subsets of capacitors of a second plurality of subsets of the plurality of capacitors to one another to form successive values of a time series of intermediate signal values based on a shared total charge of the coupled capacitors of each successive subset of capacitors of the second plurality of subsets, wherein each subset of capacitors of the second plurality of subsets is formed from capacitors of both the first storage section and the second storage section, and (c) charge successive subsets of capacitors of a third plurality of subsets of the plurality of capacitors according to successive values of the output signal values, wherein the subsets of capacitors of the third plurality of subsets are formed from capacitors of the second storage section; an amplifier for forming the time series of output signal values according to the time series of intermediate values and for charging the successive subsets of the third plurality of subsets of capacitors according to the successive output signal values; and control logic for controlling configuration of the switching circuit elements in successive phases of a clock signal to form the time series of output signal values as an application of a desired infinite impulse response filter to the time series of input signal values.