A 1/n-rate decision feedback equalizer, DFE,, comprising: a plurality of branches, each branch including: a summer amplifier circuit configured to add a feedback signal to a received data input; a latch configured to receive an output of the summer amplifier circuit in accordance with a clock signal; and a feedback circuit; including: characterised in that the feedback circuit comprises: a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence; and a filter for filtering the feedback signal to the summing amplifier circuit including a continuous-time infinite impulse response, IIR, filter with a frequency-domain transfer function (Gs), for cancelling of intersymbol interference, ISI, from the received input to be provided to the summer amplifier circuit of each branch, wherein the impulse response of the IIR filter is convolved with the received data input. a plurality of branches, each branch including: a summer amplifier circuit configured to add a feedback signal to a received data input; a latch configured to receive an output of the summer amplifier circuit in accordance with a clock signal; and a feedback circuit; including: characterised in that the feedback circuit comprises: a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence; and a filter for filtering the feedback signal to the summing amplifier circuit including a continuous-time infinite impulse response, IIR, filter with a frequency-domain transfer function (Gs), for cancelling of intersymbol interference, ISI, from the received input to be provided to the summer amplifier circuit of each branch, wherein the impulse response of the IIR filter is convolved with the received data input. a summer amplifier circuit configured to add a feedback signal to a received data input; a latch configured to receive an output of the summer amplifier circuit in accordance with a clock signal; and a feedback circuit; including: characterised in that the feedback circuit comprises: a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence; and a filter for filtering the feedback signal to the summing amplifier circuit including a continuous-time infinite impulse response, IIR, filter with a frequency-domain transfer function (Gs), for cancelling of intersymbol interference, ISI, from the received input to be provided to the summer amplifier circuit of each branch, wherein the impulse response of the IIR filter is convolved with the received data input. characterised in that the feedback circuit comprises: a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence; and a filter for filtering the feedback signal to the summing amplifier circuit including a continuous-time infinite impulse response, IIR, filter with a frequency-domain transfer function (Gs), for cancelling of intersymbol interference, ISI, from the received input to be provided to the summer amplifier circuit of each branch, wherein the impulse response of the IIR filter is convolved with the received data input. a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence; and a filter for filtering the feedback signal to the summing amplifier circuit including a continuous-time infinite impulse response, IIR, filter with a frequency-domain transfer function (Gs), for cancelling of intersymbol interference, ISI, from the received input to be provided to the summer amplifier circuit of each branch, wherein the impulse response of the IIR filter is convolved with the received data input.