A module assembly comprising: a plurality of modules capable of transmitting/receiving data by forming an open drain based one-wire communication bus upon mutual combination, at least one module requiring the data transmission/ reception among the plurality of modules is configured to perform a first declaration for a transmission intention by outputting a low signal within a predetermined first arbitration time when at least one module is in an on state by sensing the one-wire communication bus state, said at least one module performing the first declaration for the transmission intention is configured to perform a second declaration for the transmission intention by outputting a high signal within a second arbitration time, and a module which outputs the high signal last within the second arbitration time secures final bus occupation, wherein the module includes: a processor for outputting a control signal for the first declaration and the second declaration when there is data to transmit; and a UART communication unit for outputting a low signal or a high signal within an arbitration time by switching connection of the one-wire communication bus connection according to the output control signal, and wherein the plurality of modules, being the master module, sends and receives data using a data frame that includes, in order, a start section (SoF), a control section, a data section, a CRC section, an ACK section, and an arbitration section, and wherein the arbitration section determines which module will send the next data, notifies the end of the communication with an end-of-frame (EoF) bit, and is arbitrated using a time table, so that the plurality of modules output a low signal at random time. a plurality of modules capable of transmitting/receiving data by forming an open drain based one-wire communication bus upon mutual combination, at least one module requiring the data transmission/ reception among the plurality of modules is configured to perform a first declaration for a transmission intention by outputting a low signal within a predetermined first arbitration time when at least one module is in an on state by sensing the one-wire communication bus state, said at least one module performing the first declaration for the transmission intention is configured to perform a second declaration for the transmission intention by outputting a high signal within a second arbitration time, and a module which outputs the high signal last within the second arbitration time secures final bus occupation, wherein the module includes: a processor for outputting a control signal for the first declaration and the second declaration when there is data to transmit; and a UART communication unit for outputting a low signal or a high signal within an arbitration time by switching connection of the one-wire communication bus connection according to the output control signal, and wherein the plurality of modules, being the master module, sends and receives data using a data frame that includes, in order, a start section (SoF), a control section, a data section, a CRC section, an ACK section, and an arbitration section, and wherein the arbitration section determines which module will send the next data, notifies the end of the communication with an end-of-frame (EoF) bit, and is arbitrated using a time table, so that the plurality of modules output a low signal at random time. wherein the module includes: a processor for outputting a control signal for the first declaration and the second declaration when there is data to transmit; and a UART communication unit for outputting a low signal or a high signal within an arbitration time by switching connection of the one-wire communication bus connection according to the output control signal, and wherein the plurality of modules, being the master module, sends and receives data using a data frame that includes, in order, a start section (SoF), a control section, a data section, a CRC section, an ACK section, and an arbitration section, and wherein the arbitration section determines which module will send the next data, notifies the end of the communication with an end-of-frame (EoF) bit, and is arbitrated using a time table, so that the plurality of modules output a low signal at random time.