An integrated circuit, comprising: a substrate including semiconductor material extending to a top surface of the substrate; field oxide disposed in the substrate; a first gate structure over the semiconductor material proximate to the field oxide, the first gate structure including: a gate dielectric layer over the semiconductor material; and a gate on the gate dielectric layer of the first gate structure; a second gate structure over the field oxide, the second gate structure including a gate on the gate dielectric layer of the second gate structure, such that the gate of the second gate structure does not overlap a sidewall of the field oxide; a silicon-germanium source/drain region in the substrate between the first gate structure and the second gate structure, the source/drain region having a top surface that is slanted with respect to the top surface of the substrate due to limited growth of the source/drain region on the sidewall of the field oxide and -such that a top edge of a boundary between the silicon-germanium source/drain region and the field oxide does not extend more than one third of a depth of the silicon-germanium source/drain region from a top surface of the semiconductor material; dielectric spacers adjacent to lateral surfaces of the gate of the second gate structure, extending onto the slanted surface of the silicon-germanium source/drain region; metal silicide on the silicon-germanium source/drain region; and a contact for making electrical connections to the top surface of the first silicon-germanium source/drain region, between the first gate structure and the second gate structure, such that at least half of a bottom of the contact directly contacts the metal silicide on the silicon-germanium source/drain region. a substrate including semiconductor material extending to a top surface of the substrate; field oxide disposed in the substrate; a first gate structure over the semiconductor material proximate to the field oxide, the first gate structure including: a gate dielectric layer over the semiconductor material; and a gate on the gate dielectric layer of the first gate structure; a gate dielectric layer over the semiconductor material; and a gate on the gate dielectric layer of the first gate structure; a second gate structure over the field oxide, the second gate structure including a gate on the gate dielectric layer of the second gate structure, such that the gate of the second gate structure does not overlap a sidewall of the field oxide; a silicon-germanium source/drain region in the substrate between the first gate structure and the second gate structure, the source/drain region having a top surface that is slanted with respect to the top surface of the substrate due to limited growth of the source/drain region on the sidewall of the field oxide and -such that a top edge of a boundary between the silicon-germanium source/drain region and the field oxide does not extend more than one third of a depth of the silicon-germanium source/drain region from a top surface of the semiconductor material; dielectric spacers adjacent to lateral surfaces of the gate of the second gate structure, extending onto the slanted surface of the silicon-germanium source/drain region; metal silicide on the silicon-germanium source/drain region; and a contact for making electrical connections to the top surface of the first silicon-germanium source/drain region, between the first gate structure and the second gate structure, such that at least half of a bottom of the contact directly contacts the metal silicide on the silicon-germanium source/drain region.