A semiconductor device comprising a plurality of plane pattern configurations; each plane pattern configuration comprising: a first unit element (20, 30, 24, 42, 14); a second unit element (14, 32, 24, 30, 20); and a drain electrode placed on a first surface of a substrate region (10,12,18), wherein the unit elements are arranged such that the first unit element is folded over to face the second unit element such that the first and second unit elements are centred on the drain electrode, wherein each unit element comprises: a gate electrode, and a source electrode which are placed on the first surface of the substrate region (10,12,18); a first active area placed between the gate electrode and the source electrode; a second active area placed between the gate electrode and the drain electrode; a third active area formed in the substrate region (10, 12, 18) in a part underneath the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the third active area, the first active area, and the second active area, wherein in each unit element, the width of the first active area along the long-side direction of the gate electrode and the source electrode is larger than the width of the second active area along the long-side direction of the gate electrode and the drain electrode, and the largest width of the first active area along the long-side direction of the gate electrode and the source electrode is respectively equal to a width of the source electrode along the long-side direction of the source electrode, a width of the gate electrode along the long-side direction of the gate electrode, and a width of the drain electrode along the long-side direction of the drain electrode; and the first active area has a tapered form where the width gradually narrows from the source electrode toward the gate electrode, and wherein each plane pattern configuration is positioned in parallel with the others so as to extend the channel width of the semiconductor device. a gate electrode, and a source electrode which are placed on the first surface of the substrate region (10,12,18); a first active area placed between the gate electrode and the source electrode; a second active area placed between the gate electrode and the drain electrode; a third active area formed in the substrate region (10, 12, 18) in a part underneath the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the third active area, the first active area, and the second active area, wherein in each unit element, the width of the first active area along the long-side direction of the gate electrode and the source electrode is larger than the width of the second active area along the long-side direction of the gate electrode and the drain electrode, and the largest width of the first active area along the long-side direction of the gate electrode and the source electrode is respectively equal to a width of the source electrode along the long-side direction of the source electrode, a width of the gate electrode along the long-side direction of the gate electrode, and a width of the drain electrode along the long-side direction of the drain electrode; and the first active area has a tapered form where the width gradually narrows from the source electrode toward the gate electrode, and wherein each plane pattern configuration is positioned in parallel with the others so as to extend the channel width of the semiconductor device.