A time-interleaved, bootstrapped sample and hold apparatus (10, 30) comprising an input terminal (V in+) and four output terminals (V out1+, V out2+, V out3+, V out4+), comprising: first, second, third, and fourth sample and hold circuits (16, 36, 18, 38, 20, 40, 22, 42), each connected to the input terminal (V in+) and a different output terminal (V out1+, V out2+, V out3+, V out4+), and mutually exclusively operative to sample a voltage at the input terminal (V in+) in response to respective first, second, third, and fourth sample clock signals (Clk 1, Clk 2, Clk 3, Clk 4), wherein each of the first, second, third, and fourth sample clock signals (Clk 1, Clk 2, Clk 3, Clk 4) is asserted for one different half-period of two successive periods of a master clock signal (Clk); and in that the apparatus (10, 30) comprises: a first shared circuit (12, 32) operative to charge a first capacitance during one half-period of each period of the master clock signal (Clk); and a second shared circuit (14, 34) operative to charge a second capacitance during the other half-period of each period of the master clock signal (Clk); wherein the first and third sample and hold circuits (16, 36, 20, 40) are connected to the first shared circuit (12, 32), and wherein the first capacitance is connected between the input terminal (V in+) and a gate terminal of a sampling transistor in, alternately, one of the first and third sample and hold circuits (16, 36, 20, 40), in response to the respective first and third sample clock signals (Clk 1, Clk 3), during half-periods of the master clock signal (Clk) in which the first shared circuit (12, 32) is not charging the first capacitance; and wherein the second and fourth sample and hold circuits (18, 38, 22, 42) are connected to the second shared circuit (14, 34), and wherein the second capacitance is connected between the input terminal (V in+) and a gate terminal of a sampling transistor in, alternately, one of the second and fourth sample and hold circuits (18, 38, 22, 42), in response to the respective second and fourth sample clock signals (Clk 2, Clk 4), during half-periods of the master clock signal (Clk) in which the second shared circuit (14, 34) is not charging the second capacitance. first, second, third, and fourth sample and hold circuits (16, 36, 18, 38, 20, 40, 22, 42), each connected to the input terminal (V in+) and a different output terminal (V out1+, V out2+, V out3+, V out4+), and mutually exclusively operative to sample a voltage at the input terminal (V in+) in response to respective first, second, third, and fourth sample clock signals (Clk 1, Clk 2, Clk 3, Clk 4), wherein each of the first, second, third, and fourth sample clock signals (Clk 1, Clk 2, Clk 3, Clk 4) is asserted for one different half-period of two successive periods of a master clock signal (Clk); and in that the apparatus (10, 30) comprises: a first shared circuit (12, 32) operative to charge a first capacitance during one half-period of each period of the master clock signal (Clk); and a second shared circuit (14, 34) operative to charge a second capacitance during the other half-period of each period of the master clock signal (Clk); a first shared circuit (12, 32) operative to charge a first capacitance during one half-period of each period of the master clock signal (Clk); and a second shared circuit (14, 34) operative to charge a second capacitance during the other half-period of each period of the master clock signal (Clk); wherein the first and third sample and hold circuits (16, 36, 20, 40) are connected to the first shared circuit (12, 32), and wherein the first capacitance is connected between the input terminal (V in+) and a gate terminal of a sampling transistor in, alternately, one of the first and third sample and hold circuits (16, 36, 20, 40), in response to the respective first and third sample clock signals (Clk 1, Clk 3), during half-periods of the master clock signal (Clk) in which the first shared circuit (12, 32) is not charging the first capacitance; and wherein the second and fourth sample and hold circuits (18, 38, 22, 42) are connected to the second shared circuit (14, 34), and wherein the second capacitance is connected between the input terminal (V in+) and a gate terminal of a sampling transistor in, alternately, one of the second and fourth sample and hold circuits (18, 38, 22, 42), in response to the respective second and fourth sample clock signals (Clk 2, Clk 4), during half-periods of the master clock signal (Clk) in which the second shared circuit (14, 34) is not charging the second capacitance.