A multi-processor system comprising: a first cache (810; 930; 1122, 1102) and a second cache (820; 940; 1123, 1130) having different cache levels (L1, L2) with respect to each other; and at least one processor core (1120, 1101) configured to determine a placement policy with respect to future operations that are to be performed on a plurality of cache lines stored in the first cache (1122, 1102) and the second cache (1123, 1130), based on reuse information recorded in a behavior history table (870; 970; 1000; 1210), wherein the reuse information is information about reuse of learning cache lines stored in at least one of the first cache (1122, 1102) and the second cache (1122, 1102), wherein the reuse information consists of a single reuse bit that records if a cache line, region or page has been accessed at all after its initial installation or storage at a specific level and wherein only cache lines belonging to certain pages, regions or other type of address ranges, which may be referred to as learning pages, learning regions or learning address ranges, are learning cache lines and wherein the at least one processor core comprises a first core and second core, and the first core and the second core share the first cache and the second cache, characterized in that the behavior history table includes a first core reuse counter and a second core reuse counter, the first core reuse counter is incremented in response to at least one of the learning cache lines being accessed by the first core and the second core reuse counter is incremented in response to at least one of the learning cache lines being accessed by the second core. a first cache (810; 930; 1122, 1102) and a second cache (820; 940; 1123, 1130) having different cache levels (L1, L2) with respect to each other; and at least one processor core (1120, 1101) configured to determine a placement policy with respect to future operations that are to be performed on a plurality of cache lines stored in the first cache (1122, 1102) and the second cache (1123, 1130), based on reuse information recorded in a behavior history table (870; 970; 1000; 1210), wherein the reuse information is information about reuse of learning cache lines stored in at least one of the first cache (1122, 1102) and the second cache (1122, 1102), wherein the reuse information consists of a single reuse bit that records if a cache line, region or page has been accessed at all after its initial installation or storage at a specific level and wherein only cache lines belonging to certain pages, regions or other type of address ranges, which may be referred to as learning pages, learning regions or learning address ranges, are learning cache lines and wherein the at least one processor core comprises a first core and second core, and the first core and the second core share the first cache and the second cache, characterized in that the behavior history table includes a first core reuse counter and a second core reuse counter, the first core reuse counter is incremented in response to at least one of the learning cache lines being accessed by the first core and the second core reuse counter is incremented in response to at least one of the learning cache lines being accessed by the second core.