A display device comprising: a substrate comprising an active area and a bending area; a first thin-film transistor disposed in the active area and comprising a first semiconductor layer; a second thin-film transistor disposed in the active area and comprising a second semiconductor layer; a plurality of contact holes (160S, 160D, 110S, 110D, 188, 144, 120, 164, 174) formed in at least one inorganic insulation layer (210, 140, 112, 114, 116, 118, 122, 124) disposed in the active area; a first opening and a second opening in the at least one inorganic insulation layer and located in the bending area, the first opening having a same or greater depth as at least one of a first source contact hole or a first drain contact hole of the plurality of contact holes and exposing a respective side surface of each of a multilayered buffer layer, a lower buffer layer, a lower gate insulation layer and first and second lower interlayer insulation layers (116, 118) of the at least one inorganic insulation layer (210, 140, 112, 114, 116, 118, 122, 124), the second opening exposing a side surface of an upper interlayer insulation layer of the at least one inorganic insulation layer and having a second depth smaller than the first depth and the same as a first pixel contact hole, of the plurality of contact holes, formed in the upper interlayer insulation layer; a signal link (LK, 176) connected to a signal line, the signal line being disposed in the active area, the signal link being disposed in the bending area; and a first planarization layer (208, 126) formed of an organic insulation material in the bending area and contacting the respective side surface of each of the multilayered buffer layer, the lower buffer layer, the lower gate insulation layer, the first and second lower interlayer insulation layers and the upper interlayer insulation layer. a substrate comprising an active area and a bending area; a first thin-film transistor disposed in the active area and comprising a first semiconductor layer; a second thin-film transistor disposed in the active area and comprising a second semiconductor layer; a plurality of contact holes (160S, 160D, 110S, 110D, 188, 144, 120, 164, 174) formed in at least one inorganic insulation layer (210, 140, 112, 114, 116, 118, 122, 124) disposed in the active area; a first opening and a second opening in the at least one inorganic insulation layer and located in the bending area, the first opening having a same or greater depth as at least one of a first source contact hole or a first drain contact hole of the plurality of contact holes and exposing a respective side surface of each of a multilayered buffer layer, a lower buffer layer, a lower gate insulation layer and first and second lower interlayer insulation layers (116, 118) of the at least one inorganic insulation layer (210, 140, 112, 114, 116, 118, 122, 124), the second opening exposing a side surface of an upper interlayer insulation layer of the at least one inorganic insulation layer and having a second depth smaller than the first depth and the same as a first pixel contact hole, of the plurality of contact holes, formed in the upper interlayer insulation layer; a signal link (LK, 176) connected to a signal line, the signal line being disposed in the active area, the signal link being disposed in the bending area; and a first planarization layer (208, 126) formed of an organic insulation material in the bending area and contacting the respective side surface of each of the multilayered buffer layer, the lower buffer layer, the lower gate insulation layer, the first and second lower interlayer insulation layers and the upper interlayer insulation layer.