An integrated circuit memory device that transmits data signals unaccompanied by source- synchronous timing references, the integrated circuit memory device comprising: an open-loop clock distribution circuit to generate a transmit clock signal (MCK 4) in response to an externally-supplied clock signal, the transmit clock signal having the same frequency or half the frequency of the externally-supplied clock signal; a transmit circuit to output a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal, wherein each of the symbols is valid at the output of the transmit circuit for a symbol time and wherein a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time, wherein said transmit circuit contains a serializer (235, 415) for converting a parallel data packet read from the memory device into a serial data packet, the open-loop clock distribution circuit additionally generates, in response to the externally-supplied clock signal, a receive clock signal having a frequency lower than the frequency of the externally-supplied clock signal and a phase that is permitted to drift by at least a symbol time relative to the externally-supplied clock signal and to drift relative to the transmit clock signal; and a receive circuit to generate, by sampling the external signal line in response to the receive clock signal, a received data signal having a phase that also is permitted to drift relative to the externally-supplied clock signal, wherein said receive circuit contains a deserializer (236, 400) converting an externally-supplied serial data packet into a parallel data packet, wherein the receive clock signal is used to clock both the output stage of the deserializer (236, 400) and the input stage of the serialzier (235, 415); and the transmit clock signal is used to clock both the input stage of the deserialzier (236, 400) and the output stage of the serializer (235, 415). an open-loop clock distribution circuit to generate a transmit clock signal (MCK 4) in response to an externally-supplied clock signal, the transmit clock signal having the same frequency or half the frequency of the externally-supplied clock signal; a transmit circuit to output a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal, wherein each of the symbols is valid at the output of the transmit circuit for a symbol time and wherein a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time, wherein said transmit circuit contains a serializer (235, 415) for converting a parallel data packet read from the memory device into a serial data packet, the open-loop clock distribution circuit additionally generates, in response to the externally-supplied clock signal, a receive clock signal having a frequency lower than the frequency of the externally-supplied clock signal and a phase that is permitted to drift by at least a symbol time relative to the externally-supplied clock signal and to drift relative to the transmit clock signal; and a receive circuit to generate, by sampling the external signal line in response to the receive clock signal, a received data signal having a phase that also is permitted to drift relative to the externally-supplied clock signal, wherein said receive circuit contains a deserializer (236, 400) converting an externally-supplied serial data packet into a parallel data packet, wherein the receive clock signal is used to clock both the output stage of the deserializer (236, 400) and the input stage of the serialzier (235, 415); and the transmit clock signal is used to clock both the input stage of the deserialzier (236, 400) and the output stage of the serializer (235, 415).