An encryption circuit based on a multiple-round block cipher, comprising: an encryption accelerator comprising, connected in a ring: a substitute-bytes circuit, a shift-rows circuit, a mix-columns circuit, an add round-key circuit, a ciphertext register connected to store an output of the add round-key circuit at the rhythm of a round clock, a first multiplexer connected to insert a plaintext message in the ring in a first round, at an input of the add round-key circuit; characterised by a decryption accelerator comprising, connected in series: an inverse shift-rows circuit, an inverse substitute-bytes circuit, an add round-key circuit, an inverse mix-columns circuit, and a plaintext register connected to store an output of the inverse mix-columns circuit at the rhythm of the round clock; an intermediate state register connected between an output of the shift-rows circuit and an input of the inverse shift-rows circuit, and clocked by the round clock; a second multiplexer connected to select an output of the add round-key circuit of the decryption accelerator in the first round, and an output of the plaintext register in the other rounds; a third multiplexer connected to select the plaintext message in the first round and an output of the intermediate state register in the other rounds; a checkpoint state register connected to store an output of the third multiplexer at the rhythm of the round clock; and a fault-detector connected to check equality between an output of the second multiplexer and an output of the checkpoint state register. a substitute-bytes circuit, a shift-rows circuit, a mix-columns circuit, an add round-key circuit, a ciphertext register connected to store an output of the add round-key circuit at the rhythm of a round clock, a first multiplexer connected to insert a plaintext message in the ring in a first round, at an input of the add round-key circuit; characterised by a decryption accelerator comprising, connected in series: an inverse shift-rows circuit, an inverse substitute-bytes circuit, an add round-key circuit, an inverse mix-columns circuit, and a plaintext register connected to store an output of the inverse mix-columns circuit at the rhythm of the round clock; an inverse shift-rows circuit, an inverse substitute-bytes circuit, an add round-key circuit, an inverse mix-columns circuit, and a plaintext register connected to store an output of the inverse mix-columns circuit at the rhythm of the round clock; an intermediate state register connected between an output of the shift-rows circuit and an input of the inverse shift-rows circuit, and clocked by the round clock; a second multiplexer connected to select an output of the add round-key circuit of the decryption accelerator in the first round, and an output of the plaintext register in the other rounds; a third multiplexer connected to select the plaintext message in the first round and an output of the intermediate state register in the other rounds; a checkpoint state register connected to store an output of the third multiplexer at the rhythm of the round clock; and a fault-detector connected to check equality between an output of the second multiplexer and an output of the checkpoint state register.