A computer program product comprising a computer readable storage medium retaining program instructions, which program instructions when read by a processor, cause the processor to perform: obtaining a design of a circuit, wherein the circuit comprises nodes which are elements of a circuit design, wherein each node receives a value, wherein the nodes are assigned values during execution, wherein the circuit comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles; obtaining a hard error fault on a node, wherein the hard error fault is potentially capable of causing a wrong value to reach the one or more critical nodes; identifying one or more interesting nodes, wherein a Logic of Influence of each of the one or more interesting nodes comprises at least one monitoring signal and at least one critical node; determining, by a processor, a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault, characterised in that said simulating comprises: determining a sub-set of the interesting nodes the value of which is potentially different than the recorded value in a corresponding cycle in the reference execution; for each node of the interesting nodes that is not in the sub-set of the at least portion of nodes, using the recorded value as the value of the node; and for each node in the sub-set of the interesting nodes, computing the value of the node; and outputting an indication of the hard-error test coverage. obtaining a design of a circuit, wherein the circuit comprises nodes which are elements of a circuit design, wherein each node receives a value, wherein the nodes are assigned values during execution, wherein the circuit comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles; obtaining a hard error fault on a node, wherein the hard error fault is potentially capable of causing a wrong value to reach the one or more critical nodes; identifying one or more interesting nodes, wherein a Logic of Influence of each of the one or more interesting nodes comprises at least one monitoring signal and at least one critical node; determining, by a processor, a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault, characterised in that said simulating comprises: determining a sub-set of the interesting nodes the value of which is potentially different than the recorded value in a corresponding cycle in the reference execution; for each node of the interesting nodes that is not in the sub-set of the at least portion of nodes, using the recorded value as the value of the node; and for each node in the sub-set of the interesting nodes, computing the value of the node; and outputting an indication of the hard-error test coverage. determining a sub-set of the interesting nodes the value of which is potentially different than the recorded value in a corresponding cycle in the reference execution; for each node of the interesting nodes that is not in the sub-set of the at least portion of nodes, using the recorded value as the value of the node; and for each node in the sub-set of the interesting nodes, computing the value of the node; and outputting an indication of the hard-error test coverage.