Power semiconductor device with an active region comprising - a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side, - a second layer of a second conductivity type, which is arranged in a central region of the first layer on the first main side, wherein the second layer corresponds to the active region, - a junction termination region arranged in a circumferential region of the first layer on the first main side and surrounding the second layer, the junction termination region comprising at least one sub-region of the second conductivity type implemented into a sub-region of the first conductivity type and surrounding the second layer, wherein subsequent sub-regions (26, 28) of the second conductivity type laterally enclose each other and are implemented into corresponding subsequent subregions of the first conductivity type so as to be spaced apart from each other, - a third electrically conductive layer, which is arranged on the second layer on the side opposite the first layer, - a fourth electrically conductive layer, which is arranged on the second main side, - a spacer region arranged in an intermediate region of the first layer on the first main side between the second layer and the junction termination region and surrounding the second layer, the spacer region comprising a spacer sub-region of the second conductivity type having a width of at least 10 μm, the spacer sub-region being implemented into a sub-region of the first conductivity type, such that the spacer sub-region is electrically disconnected from the second layer and from the innermost sub-region of the second conductivity type, a lifetime control region comprising defects reducing a carrier lifetime within adjacent semiconductor material, the lifetime control region extending at least throughout the second layer and throughout a portion of the spacer sub-region and not extending into the junction termination region. - a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side, - a second layer of a second conductivity type, which is arranged in a central region of the first layer on the first main side, wherein the second layer corresponds to the active region, - a junction termination region arranged in a circumferential region of the first layer on the first main side and surrounding the second layer, the junction termination region comprising at least one sub-region of the second conductivity type implemented into a sub-region of the first conductivity type and surrounding the second layer, wherein subsequent sub-regions (26, 28) of the second conductivity type laterally enclose each other and are implemented into corresponding subsequent subregions of the first conductivity type so as to be spaced apart from each other, - a third electrically conductive layer, which is arranged on the second layer on the side opposite the first layer, - a fourth electrically conductive layer, which is arranged on the second main side, - a spacer region arranged in an intermediate region of the first layer on the first main side between the second layer and the junction termination region and surrounding the second layer, the spacer region comprising a spacer sub-region of the second conductivity type having a width of at least 10 μm, the spacer sub-region being implemented into a sub-region of the first conductivity type, such that the spacer sub-region is electrically disconnected from the second layer and from the innermost sub-region of the second conductivity type, a lifetime control region comprising defects reducing a carrier lifetime within adjacent semiconductor material, the lifetime control region extending at least throughout the second layer and throughout a portion of the spacer sub-region and not extending into the junction termination region.