A method for manufacturing a vertical tunneling field effect transistor comprising the steps of: - Providing a semiconductor substrate; - providing a vertical core region extending perpendicularly from the semiconductor substrate, the vertical core region having a top surface, an outer part and a middle part; - providing a vertical source region by doping at least an outer part of the vertical core region; - providing a layer of semiconductor drain material along the sidewalls and on the top surface of the vertical core region; - providing a layer of gate dielectric material on the layer of semiconductor drain material; - providing a layer of gate material on the layer of gate dielectric material; - thereafter, removing part of the layer of gate dielectric material and part of the layer of gate material thereby forming a gate dielectric layer and a gate layer; - after forming the gate dielectric layer and gate layer, removing part of the layer of drain material, thereby forming a vertical drain region; - after the step of forming the vertical drain region, selectively etching part of the vertical source region thereby leaving a cavity so that the vertical drain region comprises along its longitudinal direction a first drain part and above and in contact with the first drain part a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part extending above the gate layer and gate dielectric layer, wherein the gate dielectric layer is directly aside of the first drain part of the vertical drain region and wherein the gate layer is directly aside of said gate dielectric layer; - providing an isolation region between the vertical source region and a drain contact to be provided by forming an insulating dielectric material in the cavity present in between the vertical source region and the drain contact to be provided, - providing the drain contact to a third drain part, the third drain part being an upper part of the second drain part of the vertical drain region; - providing a source contact to the vertical source region; and - providing a gate contact to the gate layer. - Providing a semiconductor substrate; - providing a vertical core region extending perpendicularly from the semiconductor substrate, the vertical core region having a top surface, an outer part and a middle part; - providing a vertical source region by doping at least an outer part of the vertical core region; - providing a layer of semiconductor drain material along the sidewalls and on the top surface of the vertical core region; - providing a layer of gate dielectric material on the layer of semiconductor drain material; - providing a layer of gate material on the layer of gate dielectric material; - thereafter, removing part of the layer of gate dielectric material and part of the layer of gate material thereby forming a gate dielectric layer and a gate layer; - after forming the gate dielectric layer and gate layer, removing part of the layer of drain material, thereby forming a vertical drain region; - after the step of forming the vertical drain region, selectively etching part of the vertical source region thereby leaving a cavity so that the vertical drain region comprises along its longitudinal direction a first drain part and above and in contact with the first drain part a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part extending above the gate layer and gate dielectric layer, wherein the gate dielectric layer is directly aside of the first drain part of the vertical drain region and wherein the gate layer is directly aside of said gate dielectric layer; - providing an isolation region between the vertical source region and a drain contact to be provided by forming an insulating dielectric material in the cavity present in between the vertical source region and the drain contact to be provided, - providing the drain contact to a third drain part, the third drain part being an upper part of the second drain part of the vertical drain region; - providing a source contact to the vertical source region; and - providing a gate contact to the gate layer.