A semiconductor device comprising: an integrated circuit part in which an integrated circuit is formed; a main wall part including a first metallization stack extending through a sequence of via-level and trench-level dielectric layers (107, 108, 111, 112, 115, 116, 117, 118) the via-level portion of the first metallization stack being a continuous line, thereby constituting a wall surrounding said integrated circuit part; and sub-wall parts each including a second metallization stack extending through the sequence of via-level and trench-level dielectric layers, the via-level portion of the second metallization stack being a continuous line, thereby constituting a wall between said integrated circuit part and said main wall part, wherein said integrated circuit part, said main wall part and said sub-wall parts share: a semiconductor substrate; and the sequence of via-level and trench-level dielectric layers formed above said semiconductor substrate, and wherein a part of wires (120, 120a) constituting said integrated circuit and a part of said metallization stacks provided to each of said main wall part and said sub-wall parts are formed in the same respective via-level or trench-level dielectric layer, and wherein a shape of the semiconductor device is substantially a polygon, and the sub-wall parts are arranged between corners of the polygon and the integrated circuit part. an integrated circuit part in which an integrated circuit is formed; a main wall part including a first metallization stack extending through a sequence of via-level and trench-level dielectric layers (107, 108, 111, 112, 115, 116, 117, 118) the via-level portion of the first metallization stack being a continuous line, thereby constituting a wall surrounding said integrated circuit part; and sub-wall parts each including a second metallization stack extending through the sequence of via-level and trench-level dielectric layers, the via-level portion of the second metallization stack being a continuous line, thereby constituting a wall between said integrated circuit part and said main wall part, wherein said integrated circuit part, said main wall part and said sub-wall parts share: a semiconductor substrate; and the sequence of via-level and trench-level dielectric layers formed above said semiconductor substrate, and wherein a part of wires (120, 120a) constituting said integrated circuit and a part of said metallization stacks provided to each of said main wall part and said sub-wall parts are formed in the same respective via-level or trench-level dielectric layer, and wherein a shape of the semiconductor device is substantially a polygon, and the sub-wall parts are arranged between corners of the polygon and the integrated circuit part. a semiconductor substrate; and the sequence of via-level and trench-level dielectric layers formed above said semiconductor substrate, and wherein a part of wires (120, 120a) constituting said integrated circuit and a part of said metallization stacks provided to each of said main wall part and said sub-wall parts are formed in the same respective via-level or trench-level dielectric layer, and wherein a shape of the semiconductor device is substantially a polygon, and the sub-wall parts are arranged between corners of the polygon and the integrated circuit part.