A backlight (60, 120, 130, 133, 136) for a display, the backlight (60, 120, 130, 133, 136) comprising: a plurality of groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of light emitters (64, 126, 131), each group (62, 125, 131A-131D, 132A-132D, 134A-134D) comprising at least one light emitter (64, 126, 131); a power supply, the power supply configured to supply power to the groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of light emitters (64, 126, 131); and one or more controllers (66, 72, 122A-122D), the controllers (66, 72, 122A-122D) configured to control brightness levels of the light emitters (64, 126, 131) within the groups (62, 125, 131A-131D, 132A-132D, 134A-134D) by applying pulse width modulation driving signals (74, 123) to each light emitter (64, 126, 131), the PWM driving signals (74, 123) having a PWM cycle having a period T1, T2, a duty cycle proportional to the brightness level, and a phase offset that varies between the groups (62, 125, 131A-131D, 132A-132D, 134A-134D), wherein the brightness levels depend upon received image data representing an image to be displayed and wherein the brightness levels of at least two light emitters (64, 126, 131) are independently controllable, characterized in that: the one or more controllers (66, 72, 122A-122D) are adapted to control, for a given frame cycle, the duration T1 of the first PWM cycle of the frame cycle of the PWM driving signals (74, 123) for all groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of the light emitters (64, 126, 131) to be longer than the period T2 of the subsequent PWM cycles of the frame cycle, wherein the first PWM cycle of the frame cycle of the PWM driving signals (74, 123) occurs at the same time for all groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of the light emitters (64, 126, 131), and either (i) each PWM cycle of the applied PWM driving signals (74, 123) comprises a first percentage of time that corresponds to the duty cycle in an ON state preceding a remaining percentage of time in an OFF state, or (ii) each PWM cycle of the applied PWM driving signals (74, 123) comprises a first percentage of time in an OFF state preceding a remaining percentage of time that corresponds to the duty cycle in an ON state. a plurality of groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of light emitters (64, 126, 131), each group (62, 125, 131A-131D, 132A-132D, 134A-134D) comprising at least one light emitter (64, 126, 131); a power supply, the power supply configured to supply power to the groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of light emitters (64, 126, 131); and one or more controllers (66, 72, 122A-122D), the controllers (66, 72, 122A-122D) configured to control brightness levels of the light emitters (64, 126, 131) within the groups (62, 125, 131A-131D, 132A-132D, 134A-134D) by applying pulse width modulation driving signals (74, 123) to each light emitter (64, 126, 131), the PWM driving signals (74, 123) having a PWM cycle having a period T1, T2, a duty cycle proportional to the brightness level, and a phase offset that varies between the groups (62, 125, 131A-131D, 132A-132D, 134A-134D), the one or more controllers (66, 72, 122A-122D) are adapted to control, for a given frame cycle, the duration T1 of the first PWM cycle of the frame cycle of the PWM driving signals (74, 123) for all groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of the light emitters (64, 126, 131) to be longer than the period T2 of the subsequent PWM cycles of the frame cycle, wherein the first PWM cycle of the frame cycle of the PWM driving signals (74, 123) occurs at the same time for all groups (62, 125, 131A-131D, 132A-132D, 134A-134D) of the light emitters (64, 126, 131), and either (i) each PWM cycle of the applied PWM driving signals (74, 123) comprises a first percentage of time that corresponds to the duty cycle in an ON state preceding a remaining percentage of time in an OFF state, or (ii) each PWM cycle of the applied PWM driving signals (74, 123) comprises a first percentage of time in an OFF state preceding a remaining percentage of time that corresponds to the duty cycle in an ON state.