An active matrix substrate, comprising: a scanning signal line extending in a row direction; a data signal line extending in a column direction; a first transistor connected with the scanning signal line and the data signal line; a second transistor connected with the scanning signal line and the data signal line; and a first and a second pixel electrode, the first pixel electrode, the second pixel electrode, the first transistor, and the second transistor being provided in a pixel region, the scanning signal line including an opening (29, 29a), a first scanning electrode section, and a second scanning electrode section, wherein the opening (29, 29a) is located between the first and the second scanning electrode sections, such that the second scanning electrode section is facing to the first scanning electrode section in the column direction, the first transistor being connected with the first scanning electrode section by a first gate extending section being drawn from the first scanning electrode section in a direction away from the opening (29, 29a), the second transistor being connected with the second scanning electrode section by a second gate extending section being drawn from the second scanning electrode section in a direction away from the opening (29, 29a), characterized in that: the opening extends from outside of the pixel region into the pixel region by crossing under the data signal line, the first and second scanning electrode sections extending from outside of the pixel region into the pixel region by crossing under the data signal line, a first end portion is an end portion of the first scanning electrode section adjacent to the first gate extending section in the pixel region, a second end portion is an end portion of the second scanning electrode section adjacent to the second gate extending section in the pixel region, a source electrode and a drain electrode of the first transistor are formed so as not to overlap the first end portion, and a source electrode and a drain electrode of the second transistor are formed so as not to overlap the second end portion, each of the first and the second end portion is formed to have a respective notch section (7a, 7b) so as to facilitate cutting off of the first and second scanning electrode section, respectively. a scanning signal line extending in a row direction; a data signal line extending in a column direction; a first transistor connected with the scanning signal line and the data signal line; a second transistor connected with the scanning signal line and the data signal line; and a first and a second pixel electrode, the first pixel electrode, the second pixel electrode, the first transistor, and the second transistor being provided in a pixel region, the scanning signal line including an opening (29, 29a), a first scanning electrode section, and a second scanning electrode section, wherein the opening (29, 29a) is located between the first and the second scanning electrode sections, such that the second scanning electrode section is facing to the first scanning electrode section in the column direction, the first transistor being connected with the first scanning electrode section by a first gate extending section being drawn from the first scanning electrode section in a direction away from the opening (29, 29a), the second transistor being connected with the second scanning electrode section by a second gate extending section being drawn from the second scanning electrode section in a direction away from the opening (29, 29a), characterized in that: the opening extends from outside of the pixel region into the pixel region by crossing under the data signal line, the first and second scanning electrode sections extending from outside of the pixel region into the pixel region by crossing under the data signal line, a first end portion is an end portion of the first scanning electrode section adjacent to the first gate extending section in the pixel region, a second end portion is an end portion of the second scanning electrode section adjacent to the second gate extending section in the pixel region, a source electrode and a drain electrode of the first transistor are formed so as not to overlap the first end portion, and a source electrode and a drain electrode of the second transistor are formed so as not to overlap the second end portion, each of the first and the second end portion is formed to have a respective notch section (7a, 7b) so as to facilitate cutting off of the first and second scanning electrode section, respectively. the opening extends from outside of the pixel region into the pixel region by crossing under the data signal line, the first and second scanning electrode sections extending from outside of the pixel region into the pixel region by crossing under the data signal line, a first end portion is an end portion of the first scanning electrode section adjacent to the first gate extending section in the pixel region, a second end portion is an end portion of the second scanning electrode section adjacent to the second gate extending section in the pixel region, a source electrode and a drain electrode of the first transistor are formed so as not to overlap the first end portion, and a source electrode and a drain electrode of the second transistor are formed so as not to overlap the second end portion, each of the first and the second end portion is formed to have a respective notch section (7a, 7b) so as to facilitate cutting off of the first and second scanning electrode section, respectively.