A memory adapted for deep learning, the memory comprising: a first databank (615, 705), comprising: a plurality of first flip-flop arrays, each first flip-flop array comprising a plurality of first flip-flops (720A-P) adapted for storing data, and a plurality of first logic gates (710A-P) adapted for gating the plurality of first flip-flop arrays, each first logic gate (710A-P) coupled to a different one of the plurality of first flip-flop arrays, wherein the first databank (615, 705) is coupled to a first multiplexer and a plurality of second multiplexers, the plurality of first flip-flop arrays is configured to store a plurality of bytes, each byte stored in a different one of the plurality of first flip-flop arrays, the first multiplexer is configured to read the plurality of bytes from the plurality of first flip-flop arrays, and the plurality of second multiplexers is configured to read bits in the plurality of bytes from the first multiplexer, wherein the first multiplexer or the second multiplexer is configured to read based on a sequence of addresses, and an order of the sequence of addresses is determined based on Gray codes so that two adjacent addresses in the sequence are different by one bit; and a second databank (615, 705), comprising: a plurality of second flip-flop arrays, each second flip-flop array comprising a plurality of second flip-flops (720A-P) adapted for storing data, and a plurality of second logic gates (710A-P) adapted for gating the plurality of second flip-flop arrays, each second logic gate (710A-P) coupled to a different one of the plurality of second flip-flop arrays, wherein the plurality of first logic gates (710A-P) and the plurality of second logic gates (710A-P) are configured to prevent data from being written into the first databank (615, 705) and the second databank (615, 705) at a same time. a plurality of first flip-flop arrays, each first flip-flop array comprising a plurality of first flip-flops (720A-P) adapted for storing data, and a plurality of first logic gates (710A-P) adapted for gating the plurality of first flip-flop arrays, each first logic gate (710A-P) coupled to a different one of the plurality of first flip-flop arrays, wherein the first databank (615, 705) is coupled to a first multiplexer and a plurality of second multiplexers, the plurality of first flip-flop arrays is configured to store a plurality of bytes, each byte stored in a different one of the plurality of first flip-flop arrays, the first multiplexer is configured to read the plurality of bytes from the plurality of first flip-flop arrays, and the plurality of second multiplexers is configured to read bits in the plurality of bytes from the first multiplexer, wherein the first multiplexer or the second multiplexer is configured to read based on a sequence of addresses, and an order of the sequence of addresses is determined based on Gray codes so that two adjacent addresses in the sequence are different by one bit; and a second databank (615, 705), comprising: a plurality of second flip-flop arrays, each second flip-flop array comprising a plurality of second flip-flops (720A-P) adapted for storing data, and a plurality of second logic gates (710A-P) adapted for gating the plurality of second flip-flop arrays, each second logic gate (710A-P) coupled to a different one of the plurality of second flip-flop arrays, wherein the plurality of first logic gates (710A-P) and the plurality of second logic gates (710A-P) are configured to prevent data from being written into the first databank (615, 705) and the second databank (615, 705) at a same time. a plurality of second flip-flop arrays, each second flip-flop array comprising a plurality of second flip-flops (720A-P) adapted for storing data, and a plurality of second logic gates (710A-P) adapted for gating the plurality of second flip-flop arrays, each second logic gate (710A-P) coupled to a different one of the plurality of second flip-flop arrays, wherein the plurality of first logic gates (710A-P) and the plurality of second logic gates (710A-P) are configured to prevent data from being written into the first databank (615, 705) and the second databank (615, 705) at a same time.