A plasmonic circuit comprising a plurality of plasmonic majority gate devices each comprising an odd number of at least three input waveguides and at least one output waveguide, wherein the waveguides (110, 120) are adapted for guiding a surface plasmon polariton wave at an interface between a metal and a dielectric, wherein the at least three input waveguides are connected to the output waveguide at a waveguide junction, and wherein each plasmonic majority gate device is configured such that surface plasmon polariton waves inserted in the input waveguides interfere at the waveguide junction of the plasmonic majority gate devices in a combined surface plasmon polariton wave, wherein the inserted surface plasmon polariton waves have a phase at the waveguide junction which is either a first phase or a second phase wherein the second phase is shifted over π with regard to the first phase and wherein the first phase is a predetermined phase and characterized in that the plasmonic majority gate devices are arranged in cascaded stages, wherein the output waveguide of a plasmonic majority gate device of one stage is connected with an input waveguide of a plasmonic majority gate device of the following stage, the plasmonic circuit comprising a reference waveguide connected with an output waveguide of a plasmonic majority gate device in a last stage and wherein a phase of a reference wave on the reference waveguide is configured such that the reference wave on the reference waveguide has the same phase as an output wave of the output waveguide of the last stage or a phase difference of π with the output wave of the output waveguide of the last stage, by taking into consideration the path lengths for the inserted surface plasmon polariton waves in the input waveguides and the path length of the reference wave inserted in the reference waveguide. wherein the waveguides (110, 120) are adapted for guiding a surface plasmon polariton wave at an interface between a metal and a dielectric, wherein the at least three input waveguides are connected to the output waveguide at a waveguide junction, and wherein each plasmonic majority gate device is configured such that surface plasmon polariton waves inserted in the input waveguides interfere at the waveguide junction of the plasmonic majority gate devices in a combined surface plasmon polariton wave, wherein the inserted surface plasmon polariton waves have a phase at the waveguide junction which is either a first phase or a second phase wherein the second phase is shifted over π with regard to the first phase and wherein the first phase is a predetermined phase and characterized in that the plasmonic majority gate devices are arranged in cascaded stages, wherein the output waveguide of a plasmonic majority gate device of one stage is connected with an input waveguide of a plasmonic majority gate device of the following stage, the plasmonic circuit comprising a reference waveguide connected with an output waveguide of a plasmonic majority gate device in a last stage and wherein a phase of a reference wave on the reference waveguide is configured such that the reference wave on the reference waveguide has the same phase as an output wave of the output waveguide of the last stage or a phase difference of π with the output wave of the output waveguide of the last stage, by taking into consideration the path lengths for the inserted surface plasmon polariton waves in the input waveguides and the path length of the reference wave inserted in the reference waveguide.