An integrated circuit, comprising: a two-dimensional array of functional blocks (110, 120, 130; 910A,..., 910Z) comprising a plurality of pipelined programmable routing resources (300, 870, 860); routing circuitry for connecting the functional blocks (110, 120, 130; 910A,..., 910Z); a first plurality of interconnects that conveys a first plurality of clock signals; a second plurality of interconnects (520, 620, 720, 820) that conveys a second plurality of clock signals; a first selector circuit (540, 640, 740, 840) coupled between the first and second plurality of interconnects, wherein the first selector circuit (540, 640, 740, 840) receives the first plurality of clock signals and selects among the received first plurality of clock signals to produce the second plurality of clock signals; and a second selector circuit (550, 650, 750, 850) coupled to the second plurality of interconnects, wherein the second selector circuit (550, 650, 750, 850) receives from the second plurality of interconnects (520, 620, 720, 820) at least a portion of the second plurality of clock signals, and selects a signal from the received portion of the second plurality of clock signals, whereby a first one of said functional blocks (110, 120, 130; 910A,..., 910Z) is adapted to send a signal from a first pipelined programmable routing resource (300, 870, 860) within said first functional block to a second pipelined programmable routing resource (300, 870, 860) within a second one of the functional blocks (110, 120, 130; 910A,..., 910Z); and the second selector circuit (550, 650, 750, 850) provides the selected clock signal to a by passable register (206, 306) within each of the first and second pipelined programmable routing resources (300, 870, 860). a two-dimensional array of functional blocks (110, 120, 130; 910A,..., 910Z) comprising a plurality of pipelined programmable routing resources (300, 870, 860); routing circuitry for connecting the functional blocks (110, 120, 130; 910A,..., 910Z); a first plurality of interconnects that conveys a first plurality of clock signals; a second plurality of interconnects (520, 620, 720, 820) that conveys a second plurality of clock signals; a first selector circuit (540, 640, 740, 840) coupled between the first and second plurality of interconnects, wherein the first selector circuit (540, 640, 740, 840) receives the first plurality of clock signals and selects among the received first plurality of clock signals to produce the second plurality of clock signals; and a second selector circuit (550, 650, 750, 850) coupled to the second plurality of interconnects, wherein the second selector circuit (550, 650, 750, 850) receives from the second plurality of interconnects (520, 620, 720, 820) at least a portion of the second plurality of clock signals, and selects a signal from the received portion of the second plurality of clock signals, whereby a first one of said functional blocks (110, 120, 130; 910A,..., 910Z) is adapted to send a signal from a first pipelined programmable routing resource (300, 870, 860) within said first functional block to a second pipelined programmable routing resource (300, 870, 860) within a second one of the functional blocks (110, 120, 130; 910A,..., 910Z); and the second selector circuit (550, 650, 750, 850) provides the selected clock signal to a by passable register (206, 306) within each of the first and second pipelined programmable routing resources (300, 870, 860).