A static random access memory, SRAM, bit cell (300) comprising: a plurality of tracks employed in a first metal layer; a write wordline employed in a second metal layer; a first read wordline employed in a third metal layer; a second read wordline employed in a fourth metal layer, characterized in that: each first read wordline landing pad (312) of a plurality of first read wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each first read wordline landing pad (312) and corresponding track (308) is disposed on a first side (404) of a boundary edge (402) of the SRAM bit cell (300); each second read wordline landing pad (314) of a plurality of second read wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each second read wordline landing pad (314) and corresponding track (308) is disposed on a second side (404) of a boundary edge (402) of the SRAM bit cell (300); and each write wordline landing pad (316) of a plurality of write wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each write wordline landing pad (316) and corresponding track (308) is disposed within each boundary edge of a plurality of boundary edges of the SRAM bit cell (300). a plurality of tracks employed in a first metal layer; a write wordline employed in a second metal layer; a first read wordline employed in a third metal layer; a second read wordline employed in a fourth metal layer, characterized in that: each first read wordline landing pad (312) of a plurality of first read wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each first read wordline landing pad (312) and corresponding track (308) is disposed on a first side (404) of a boundary edge (402) of the SRAM bit cell (300); each second read wordline landing pad (314) of a plurality of second read wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each second read wordline landing pad (314) and corresponding track (308) is disposed on a second side (404) of a boundary edge (402) of the SRAM bit cell (300); and each write wordline landing pad (316) of a plurality of write wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each write wordline landing pad (316) and corresponding track (308) is disposed within each boundary edge of a plurality of boundary edges of the SRAM bit cell (300). each first read wordline landing pad (312) of a plurality of first read wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each first read wordline landing pad (312) and corresponding track (308) is disposed on a first side (404) of a boundary edge (402) of the SRAM bit cell (300); each second read wordline landing pad (314) of a plurality of second read wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each second read wordline landing pad (314) and corresponding track (308) is disposed on a second side (404) of a boundary edge (402) of the SRAM bit cell (300); and each write wordline landing pad (316) of a plurality of write wordline landing pads is disposed on a corresponding track (308) of the plurality of tracks, wherein each write wordline landing pad (316) and corresponding track (308) is disposed within each boundary edge of a plurality of boundary edges of the SRAM bit cell (300).