A method for testing a memory in a chip, wherein the chip comprises a plurality of operation modules, and the method comprising: generating a first test vector for a first operation module of the operation modules, wherein each of the operation modules comprises a plurality of operation units, each of the operation units is a unit implementing a basic operation algorithm or function, and each of the plurality of operation modules is a module implementing certain functions or operations, characterised in that each of the at least one operation unit comprises a circuit for executing a corresponding operation logic and a plurality of memories, wherein generating the first test vector comprises: generating a sub-test vector for one operation unit of the operation module; and generating the first test vector by reusing the sub-test vector between all operation units in the first operation module; and testing the memory in the first operation module by using the generated first test vector, independently of other operation modules of the plurality of operation modules, wherein the first test vector is output to the first operation module, the a first test result returned by the first operation module is received, and a test result as to whether the memory in the first operation module is valid is obtained based on the first test result, wherein a memory test for the first operation module is performed by performing a corresponding memory sub-test for each operation unit in the first operation module. generating a first test vector for a first operation module of the operation modules, wherein each of the operation modules comprises a plurality of operation units, each of the operation units is a unit implementing a basic operation algorithm or function, and each of the plurality of operation modules is a module implementing certain functions or operations, characterised in that each of the at least one operation unit comprises a circuit for executing a corresponding operation logic and a plurality of memories, wherein generating the first test vector comprises: generating a sub-test vector for one operation unit of the operation module; and generating the first test vector by reusing the sub-test vector between all operation units in the first operation module; and testing the memory in the first operation module by using the generated first test vector, independently of other operation modules of the plurality of operation modules, wherein the first test vector is output to the first operation module, the a first test result returned by the first operation module is received, and a test result as to whether the memory in the first operation module is valid is obtained based on the first test result, wherein a memory test for the first operation module is performed by performing a corresponding memory sub-test for each operation unit in the first operation module. generating a sub-test vector for one operation unit of the operation module; and generating the first test vector by reusing the sub-test vector between all operation units in the first operation module; and testing the memory in the first operation module by using the generated first test vector, independently of other operation modules of the plurality of operation modules, wherein the first test vector is output to the first operation module, the a first test result returned by the first operation module is received, and a test result as to whether the memory in the first operation module is valid is obtained based on the first test result, wherein a memory test for the first operation module is performed by performing a corresponding memory sub-test for each operation unit in the first operation module.