A display device, comprising: gate lines (G1a, G1b, G2a, G2b, G3a, G3b, G4a, G4b; G5-G8) in an active area; the active area comprising a first area having a non-parallelogram portion and a second area having a parallelogram portion, wherein number of pixels horizontally disposed for each gate line in the first area of the active area is smaller than number of pixels horizontally disposed for each gate line in the second area of the active area; a bezel area comprising a third area close to the first area and having a non-parallelogram portion and a fourth area close to the second area and having a parallelogram portion, a first power supply electrode (VDLb) positioned in the third area of the bezel area; a semiconductor pattern (ACT1, ACT2) positioned in the third area of the bezel area and overlapping the first power supply electrode (VDLb), wherein the semiconductor pattern is connected to the first power supply electrode (VDLb); and a plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4) disposed in the third area of the bezel area and positioned between the semiconductor pattern and the first power supply electrode (VDLb) and overlapping the semiconductor pattern to form a second compensation capacitance and overlapping the first power supply electrode (VDLb) to form a first compensation capacitance, wherein the plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4) are connected to a plurality of gate lines (G1a, G1b, G2a, G2b, G3a, G3b, G4a, G4b) of the first area of the active area, respectively; and wherein the display device further comprises a first opening part formed in the semiconductor pattern overlapping the plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4) and a second opening part formed in the first power supply electrode (VDLb) overlapping the plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4), characterized in that the second opening part does not overlap the first opening part. gate lines (G1a, G1b, G2a, G2b, G3a, G3b, G4a, G4b; G5-G8) in an active area; the active area comprising a first area having a non-parallelogram portion and a second area having a parallelogram portion, wherein number of pixels horizontally disposed for each gate line in the first area of the active area is smaller than number of pixels horizontally disposed for each gate line in the second area of the active area; a bezel area comprising a third area close to the first area and having a non-parallelogram portion and a fourth area close to the second area and having a parallelogram portion, a first power supply electrode (VDLb) positioned in the third area of the bezel area; a semiconductor pattern (ACT1, ACT2) positioned in the third area of the bezel area and overlapping the first power supply electrode (VDLb), wherein the semiconductor pattern is connected to the first power supply electrode (VDLb); and a plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4) disposed in the third area of the bezel area and positioned between the semiconductor pattern and the first power supply electrode (VDLb) and overlapping the semiconductor pattern to form a second compensation capacitance and overlapping the first power supply electrode (VDLb) to form a first compensation capacitance, wherein the plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4) are connected to a plurality of gate lines (G1a, G1b, G2a, G2b, G3a, G3b, G4a, G4b) of the first area of the active area, respectively; and wherein the display device further comprises a first opening part formed in the semiconductor pattern overlapping the plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4) and a second opening part formed in the first power supply electrode (VDLb) overlapping the plurality of dummy gate lines (GD1a, GD1b, GD2a, GD2b, GD3, GD4), characterized in that the second opening part does not overlap the first opening part.