A shift register (SR1, SR2), comprising: an initial stage, a first intermediate stage (UC5, UCm, UCj), a second intermediate stage (UC9, UCm, UCi), and a final stage (UCn), wherein: each of the first and second intermediate stages (UC5, UC9, UCm, UCj, UCi) includes a first input terminal supplied with a clock signal, a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, an output terminal (OTm, OTi, OTj) connected to the first input terminal via an output transistor, and a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor; the second intermediate stage (UC9, UCm, UCi) includes a control circuit which is connected to the setting circuit and supplied with a control signal; an operation period starts at a time when a shift start signal (SPX, SPY, SPx, SPy) supplied to the initial stage is activated and ends at a time when an output of the final stage (UCn) changes from activation to inactivation; and when the clock signal supplied to the first input terminal of the second intermediate stage (UC9, UCm, UCi) is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage (UC9, UCm, UCi) is inactive; wherein the setting circuit includes a first setting transistor and a second setting transistor; wherein the second setting transistor has a control terminal connected via the first setting transistor to the second input terminal; wherein the control terminal of the output transistor is connected to a constant electric potential source via the second setting transistor; when the clock signal supplied to the second input terminal is active, the output transistor is turned off; and wherein the control circuit includes a control transistor which is connected to the control terminal of the second setting transistor or the output transistor, and has a control terminal supplied with the control signal. an initial stage, a first intermediate stage (UC5, UCm, UCj), a second intermediate stage (UC9, UCm, UCi), and a final stage (UCn), wherein: each of the first and second intermediate stages (UC5, UC9, UCm, UCj, UCi) includes a first input terminal supplied with a clock signal, a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, an output terminal (OTm, OTi, OTj) connected to the first input terminal via an output transistor, and a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor; the second intermediate stage (UC9, UCm, UCi) includes a control circuit which is connected to the setting circuit and supplied with a control signal; an operation period starts at a time when a shift start signal (SPX, SPY, SPx, SPy) supplied to the initial stage is activated and ends at a time when an output of the final stage (UCn) changes from activation to inactivation; and when the clock signal supplied to the first input terminal of the second intermediate stage (UC9, UCm, UCi) is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage (UC9, UCm, UCi) is inactive; each of the first and second intermediate stages (UC5, UC9, UCm, UCj, UCi) includes a first input terminal supplied with a clock signal, a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, an output terminal (OTm, OTi, OTj) connected to the first input terminal via an output transistor, and a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor; the second intermediate stage (UC9, UCm, UCi) includes a control circuit which is connected to the setting circuit and supplied with a control signal; an operation period starts at a time when a shift start signal (SPX, SPY, SPx, SPy) supplied to the initial stage is activated and ends at a time when an output of the final stage (UCn) changes from activation to inactivation; and when the clock signal supplied to the first input terminal of the second intermediate stage (UC9, UCm, UCi) is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage (UC9, UCm, UCi) is inactive; wherein the setting circuit includes a first setting transistor and a second setting transistor; wherein the second setting transistor has a control terminal connected via the first setting transistor to the second input terminal; wherein the control terminal of the output transistor is connected to a constant electric potential source via the second setting transistor; when the clock signal supplied to the second input terminal is active, the output transistor is turned off; and wherein the control circuit includes a control transistor which is connected to the control terminal of the second setting transistor or the output transistor, and has a control terminal supplied with the control signal.