A memory device comprising a matrix of memory cells, the matrix being provided with at least one first column (COL 1) of cells wherein each of said cells (C 0, C n-1) comprises: - at least one first storage node to store logical data, particularly "1" or "0", the value of which corresponds to the value of at least one potential at said first storage node, - at least one read port that, when activated, transmits the potential of the first storage node to a first bit line (RBL1, RBLT) shared by the cells (C 0, C n-1) in the first column of cells, the device further being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical '1', is greater than a predetermined threshold, said test circuit comprising: - a first read node (NL1, NL10) coupled to one end of the first bit line (RBL1, RBLT), - a second read node (NL2, NL20) coupled to one end of a second bit line (RBL_Dum, RBL2), the second bit line forming a reference bit line associated with a plurality of second logical information storage nodes, said second storage nodes being configured to all store the same logical information or belonging to said cells in said first column respectively, and being storage nodes complementary to said first nodes, characterized it further comprises: - at least one stage (20, 110) forming a variable resistance to adjust said predetermined threshold, said stage being coupled to at least the first read node, said test circuit (10, 100) being configured to: - concomitantly activate k read ports of a number k of cells in said first column while simultaneously activating k other read ports of a corresponding number k of second storage nodes with which these other read ports are associated, to cause discharge of the first bit line and discharge of the second bit line and consequently cause a variation of the potential at said first read node and at the second read node and then, after a predetermined duration, depending on the difference in potentials between said first read node and said second read node: - produce at least one logical test result signal (S_OUT, L_OUT) indicating whether or not the proportion of cells in said column storing a given logical level, in particular a logical "1", is greater than said predetermined threshold, as a function of its value. - at least one first storage node to store logical data, particularly "1" or "0", the value of which corresponds to the value of at least one potential at said first storage node, - at least one read port that, when activated, transmits the potential of the first storage node to a first bit line (RBL1, RBLT) shared by the cells (C 0, C n-1) in the first column of cells, the device further being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical '1', is greater than a predetermined threshold, said test circuit comprising: - a first read node (NL1, NL10) coupled to one end of the first bit line (RBL1, RBLT), - a second read node (NL2, NL20) coupled to one end of a second bit line (RBL_Dum, RBL2), the second bit line forming a reference bit line associated with a plurality of second logical information storage nodes, said second storage nodes being configured to all store the same logical information or belonging to said cells in said first column respectively, and being storage nodes complementary to said first nodes, characterized it further comprises: - at least one stage (20, 110) forming a variable resistance to adjust said predetermined threshold, said stage being coupled to at least the first read node, said test circuit (10, 100) being configured to: - concomitantly activate k read ports of a number k of cells in said first column while simultaneously activating k other read ports of a corresponding number k of second storage nodes with which these other read ports are associated, to cause discharge of the first bit line and discharge of the second bit line and consequently cause a variation of the potential at said first read node and at the second read node and then, after a predetermined duration, depending on the difference in potentials between said first read node and said second read node: - produce at least one logical test result signal (S_OUT, L_OUT) indicating whether or not the proportion of cells in said column storing a given logical level, in particular a logical "1", is greater than said predetermined threshold, as a function of its value.