An apparatus, comprising; a plurality of planes (P0-P3) arranged on one or more die; a plurality of blocks (B0-0 to BO-n-1, B1-0 to B1-n-1, B2-0 to B2-n-1, B3-0 to B3-n-1) of memory cells (703-714, 723-734, 743-754, 763-774) arranged in the plurality of planes, the plurality of blocks comprise a respective block arranged in each plane, each respective block comprising a set of memory cells connected to a set of word lines (WL0-WL95), the set of word lines in each respective block comprise programmed word lines and unprogrammed word lines; and a control circuit (110, 122), the control circuit is configured to: receive a read command identifying a selected word line (WLn) of each respective block, and in response to the read command, identifying a last-programmed word line for each respective block, and determine whether the last-programmed word line is equal for each respective block; if the last-programmed word line is equal for each respective block, read the selected word lines of the respective blocks by applying a control gate read voltage (Vcgr) to the selected word line and a same baseline read pass voltage (Vread_UP_base) to the unprogrammed word lines of each respective block; and if the last-programmed word line is not equal for each respective block, identify one or more lesser-programmed blocks of the respective blocks and one or more greater-programmed blocks of the respective blocks based on the last-programmed word lines of the respective blocks, and read the selected word lines of the respective blocks by applying a control gate read voltage to the selected word lines while applying a lower read pass voltage (Vread_UP_L1, Vread_UP_L2, Vread_UP_L3), lower than the same baseline read pass voltage, to the unprogrammed word lines of the one or more lesser-programmed blocks. a plurality of planes (P0-P3) arranged on one or more die; a plurality of blocks (B0-0 to BO-n-1, B1-0 to B1-n-1, B2-0 to B2-n-1, B3-0 to B3-n-1) of memory cells (703-714, 723-734, 743-754, 763-774) arranged in the plurality of planes, the plurality of blocks comprise a respective block arranged in each plane, each respective block comprising a set of memory cells connected to a set of word lines (WL0-WL95), the set of word lines in each respective block comprise programmed word lines and unprogrammed word lines; and a control circuit (110, 122), the control circuit is configured to: receive a read command identifying a selected word line (WLn) of each respective block, and in response to the read command, identifying a last-programmed word line for each respective block, and determine whether the last-programmed word line is equal for each respective block; if the last-programmed word line is equal for each respective block, read the selected word lines of the respective blocks by applying a control gate read voltage (Vcgr) to the selected word line and a same baseline read pass voltage (Vread_UP_base) to the unprogrammed word lines of each respective block; and if the last-programmed word line is not equal for each respective block, identify one or more lesser-programmed blocks of the respective blocks and one or more greater-programmed blocks of the respective blocks based on the last-programmed word lines of the respective blocks, and read the selected word lines of the respective blocks by applying a control gate read voltage to the selected word lines while applying a lower read pass voltage (Vread_UP_L1, Vread_UP_L2, Vread_UP_L3), lower than the same baseline read pass voltage, to the unprogrammed word lines of the one or more lesser-programmed blocks. receive a read command identifying a selected word line (WLn) of each respective block, and in response to the read command, identifying a last-programmed word line for each respective block, and determine whether the last-programmed word line is equal for each respective block; if the last-programmed word line is equal for each respective block, read the selected word lines of the respective blocks by applying a control gate read voltage (Vcgr) to the selected word line and a same baseline read pass voltage (Vread_UP_base) to the unprogrammed word lines of each respective block; and if the last-programmed word line is not equal for each respective block, identify one or more lesser-programmed blocks of the respective blocks and one or more greater-programmed blocks of the respective blocks based on the last-programmed word lines of the respective blocks, and read the selected word lines of the respective blocks by applying a control gate read voltage to the selected word lines while applying a lower read pass voltage (Vread_UP_L1, Vread_UP_L2, Vread_UP_L3), lower than the same baseline read pass voltage, to the unprogrammed word lines of the one or more lesser-programmed blocks.