An apparatus for processing an instruction for accessing an N-dimensional tensor, the apparatus comprising: for each dimension of the N-dimensional tensor, a partial address offset value element that stores a partial address offset value for the dimension based at least on an initial value for the dimension, a step value for the dimension, a number of iterations of a loop for the dimension, and a limit value for the dimension; one or more processors configured to obtain an instruction to access a particular element of the N-dimensional tensor, wherein the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and wherein N is an integer that is equal to or greater than one, one or more hardware adders; characterized by the one or more processors being further configured to: determine, for each dimension, the partial address offset value for the dimension after each iteration of a nested loop for the dimension by adding the step value to a previous address offset value for the dimension; and determine, for each dimension, whether the determined partial address offset value for a dimension equals the limit value for the dimension and, in response to determining that the determined partial address offset value for a first dimension that corresponds to a first nested loop equals the limit value for the first dimension, resetting the partial address offset value for the first dimension to the initial value for the first dimension, and updating, for a second dimension that corresponds to a second nested loop in which the first nested loop is nested and using the one or more hardware adders, the partial address offset value for the second dimension to equal a sum of the step value for the second dimension and the partial address offset value for the second dimension, and determine, using the one or more hardware adders, an address of the particular element by determining a sum of the partial address offset values for each dimension stored in the respective partial address offset value elements, and output data indicating the determined address for accessing the particular element of the N-dimensional tensor. for each dimension of the N-dimensional tensor, a partial address offset value element that stores a partial address offset value for the dimension based at least on an initial value for the dimension, a step value for the dimension, a number of iterations of a loop for the dimension, and a limit value for the dimension; one or more processors configured to obtain an instruction to access a particular element of the N-dimensional tensor, wherein the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and wherein N is an integer that is equal to or greater than one, one or more hardware adders; determine, for each dimension, the partial address offset value for the dimension after each iteration of a nested loop for the dimension by adding the step value to a previous address offset value for the dimension; and determine, for each dimension, whether the determined partial address offset value for a dimension equals the limit value for the dimension and, in response to determining that the determined partial address offset value for a first dimension that corresponds to a first nested loop equals the limit value for the first dimension, resetting the partial address offset value for the first dimension to the initial value for the first dimension, and updating, for a second dimension that corresponds to a second nested loop in which the first nested loop is nested and using the one or more hardware adders, the partial address offset value for the second dimension to equal a sum of the step value for the second dimension and the partial address offset value for the second dimension, and resetting the partial address offset value for the first dimension to the initial value for the first dimension, and updating, for a second dimension that corresponds to a second nested loop in which the first nested loop is nested and using the one or more hardware adders, the partial address offset value for the second dimension to equal a sum of the step value for the second dimension and the partial address offset value for the second dimension, and determine, using the one or more hardware adders, an address of the particular element by determining a sum of the partial address offset values for each dimension stored in the respective partial address offset value elements, and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.