A circuit comprising: a plurality of ring oscillators (23, 24, 34), wherein each of the plurality of ring oscillators is configured to generate a respective one of a plurality of periodic signals; a selection unit coupled to receive each of the plurality of periodic signals, wherein the selection unit is configured to convey a first clock edge into each of the plurality of ring oscillators responsive to determining that each of the periodic signals being at a first level, and wherein the selection unit is further configured to convey a second clock edge into each of the plurality of ring oscillators responsive to determining that each of the periodic signals is at a second logic level, wherein the first and second clock edges occur in opposite directions, wherein the selection unit includes a first logic gate having a first plurality of inputs, wherein the first plurality of inputs includes a first subset of inputs each coupled to receive a respective one of the plurality of periodic signals, a second logic gate having a second plurality of inputs each coupled to receive a respective one of the plurality of periodic signals, a set-reset, "SR", flop having a set input coupled to receive an output from the first logic gate, a reset input coupled to receive an output from the second logic gate, and an output coupled to convey the first and second clock edges into each of the plurality of ring oscillators, and an enable input (En), wherein the selection unit is configured to inhibit the SR flop from providing the first and second clock edges to each of the plurality of ring oscillators responsive to de-assertion of an enable signal received on the enable input. a plurality of ring oscillators (23, 24, 34), wherein each of the plurality of ring oscillators is configured to generate a respective one of a plurality of periodic signals; a selection unit coupled to receive each of the plurality of periodic signals, wherein the selection unit is configured to convey a first clock edge into each of the plurality of ring oscillators responsive to determining that each of the periodic signals being at a first level, and wherein the selection unit is further configured to convey a second clock edge into each of the plurality of ring oscillators responsive to determining that each of the periodic signals is at a second logic level, wherein the first and second clock edges occur in opposite directions, wherein the selection unit includes a first logic gate having a first plurality of inputs, wherein the first plurality of inputs includes a first subset of inputs each coupled to receive a respective one of the plurality of periodic signals, a second logic gate having a second plurality of inputs each coupled to receive a respective one of the plurality of periodic signals, a set-reset, "SR", flop having a set input coupled to receive an output from the first logic gate, a reset input coupled to receive an output from the second logic gate, and an output coupled to convey the first and second clock edges into each of the plurality of ring oscillators, and an enable input (En), a first logic gate having a first plurality of inputs, wherein the first plurality of inputs includes a first subset of inputs each coupled to receive a respective one of the plurality of periodic signals, a second logic gate having a second plurality of inputs each coupled to receive a respective one of the plurality of periodic signals, a set-reset, "SR", flop having a set input coupled to receive an output from the first logic gate, a reset input coupled to receive an output from the second logic gate, and an output coupled to convey the first and second clock edges into each of the plurality of ring oscillators, and an enable input (En), wherein the selection unit is configured to inhibit the SR flop from providing the first and second clock edges to each of the plurality of ring oscillators responsive to de-assertion of an enable signal received on the enable input.