A matrix processor (240, 300, 606) for performing arithmetic operations, the matrix processor (240, 300, 606) comprising: a plurality of sub-circuits (242, 350, 400) coupled within a two-dimensional array, a first input circuit arranged in a first dimension of the two-dimensional array, the first input circuit being coupled to receive N operands from a first logic circuit, the N operands being formatted in accordance with a first width related to the first dimension and being representative of a row in an input data matrix, wherein columns (610, 612) of the input data matrix are vectorized forms of input matrices corresponding to areas of input data; and a second input circuit arranged in a second dimension of the two-dimensional array, the second input circuit coupled to receive M operands from a second logic circuit, the M operands being formatted in accordance with a second width related to the second dimension and being representative of a column in a weight data matrix, wherein rows of the weight data matrix are vectorized forms of weight matrices corresponding to filters of a convolution operation, wherein: the plurality of sub-circuits (242, 350, 400) is configured to perform dot multiplications of the N operands and the M operands to generate dot products (514, 630, 632) with each of the sub-circuits (242, 350, 400) being configured to perform a dot multiplication of a respective column (610, 612) of the input data matrix and a respective row of the weight data matrix to generate a dot product (514, 630, 632) representing the convolution of the corresponding area of the input data with the corresponding filter of the convolution operation. a plurality of sub-circuits (242, 350, 400) coupled within a two-dimensional array, a first input circuit arranged in a first dimension of the two-dimensional array, the first input circuit being coupled to receive N operands from a first logic circuit, the N operands being formatted in accordance with a first width related to the first dimension and being representative of a row in an input data matrix, wherein columns (610, 612) of the input data matrix are vectorized forms of input matrices corresponding to areas of input data; and a second input circuit arranged in a second dimension of the two-dimensional array, the second input circuit coupled to receive M operands from a second logic circuit, the M operands being formatted in accordance with a second width related to the second dimension and being representative of a column in a weight data matrix, wherein rows of the weight data matrix are vectorized forms of weight matrices corresponding to filters of a convolution operation, wherein: the plurality of sub-circuits (242, 350, 400) is configured to perform dot multiplications of the N operands and the M operands to generate dot products (514, 630, 632) with each of the sub-circuits (242, 350, 400) being configured to perform a dot multiplication of a respective column (610, 612) of the input data matrix and a respective row of the weight data matrix to generate a dot product (514, 630, 632) representing the convolution of the corresponding area of the input data with the corresponding filter of the convolution operation.