An electrically erasable flash memory, comprising: a memory array comprising at least one row (24, 44) comprising a plurality of memory cells (10, 30), each of said plurality of memory cells (10, 30) having a data state; and a voltage sensing circuit selectively coupled to individual ones of said plurality of memory cells and configured to bias said individual ones of said plurality of memory cells with at least one of a bias current and a bias resistance and to read said data states of said individual ones of said plurality of memory cells; each of said plurality of memory cells has a performance margin; wherein said voltage sensing circuit is configured to selectively bias said plurality of memory cells with said bias being at least one of a read bias and a margin bias; and wherein, when said voltage sensing circuit biases said individual one of said plurality of memory cells with said margin bias, said individual one of said plurality of memory cells induces a response indicative of said performance margin of said individual one of said plurality of memory cells; and wherein said voltage sensing circuit comprises: a sensor; and a biasing circuit configured to bias said sensor with said bias current and/or bias resistance; wherein each of said plurality of memory cells induces a response in said sensor indicative of said data state of a selected one of said plurality of memory cells; wherein said plurality of memory cells are organized into a plurality of bitlines along the at least one row starting from a line electronics circuitry; and characterized in that said memory further comprises a pre-discharge circuit operatively coupled to said plurality of bitlines; wherein said pre-discharge circuit is configured to drive at least one of said plurality of bitlines which is physically positioned at a far end of each row relative to the line electronics circuitry, to a predetermined voltage level prior to said individual one of said plurality of memory cells inducing said response indicative of said data state in said individual one of said plurality of memory cells. a memory array comprising at least one row (24, 44) comprising a plurality of memory cells (10, 30), each of said plurality of memory cells (10, 30) having a data state; and a voltage sensing circuit selectively coupled to individual ones of said plurality of memory cells and configured to bias said individual ones of said plurality of memory cells with at least one of a bias current and a bias resistance and to read said data states of said individual ones of said plurality of memory cells; each of said plurality of memory cells has a performance margin; wherein said voltage sensing circuit is configured to selectively bias said plurality of memory cells with said bias being at least one of a read bias and a margin bias; and wherein, when said voltage sensing circuit biases said individual one of said plurality of memory cells with said margin bias, said individual one of said plurality of memory cells induces a response indicative of said performance margin of said individual one of said plurality of memory cells; and wherein said voltage sensing circuit comprises: a sensor; and a biasing circuit configured to bias said sensor with said bias current and/or bias resistance; wherein each of said plurality of memory cells induces a response in said sensor indicative of said data state of a selected one of said plurality of memory cells; wherein said plurality of memory cells are organized into a plurality of bitlines along the at least one row starting from a line electronics circuitry; and characterized in that said memory further comprises a pre-discharge circuit operatively coupled to said plurality of bitlines; a sensor; and a biasing circuit configured to bias said sensor with said bias current and/or bias resistance; wherein each of said plurality of memory cells induces a response in said sensor indicative of said data state of a selected one of said plurality of memory cells; wherein said plurality of memory cells are organized into a plurality of bitlines along the at least one row starting from a line electronics circuitry; and characterized in that said memory further comprises a pre-discharge circuit operatively coupled to said plurality of bitlines; wherein said pre-discharge circuit is configured to drive at least one of said plurality of bitlines which is physically positioned at a far end of each row relative to the line electronics circuitry, to a predetermined voltage level prior to said individual one of said plurality of memory cells inducing said response indicative of said data state in said individual one of said plurality of memory cells.