A mask read-only memory, comprising: a substrate; a first gate structure (521, 513-1) formed on a surface of the substrate for receiving a word line voltage during a read cycle; a second gate structure (520, 513-2) formed on the surface of the substrate for receiving a read voltage during the read cycle; a third gate structure (522, 513-3) formed on the surface of the substrate; a first diffusion region formed in the surface of the substrate and located adjacent to a first side of the first gate structure (521, 513-1) for generating a first bit line voltage during the read cycle; a second diffusion region formed in the surface of the substrate, and located adjacent to a second side of the first gate structure (521, 513-1) and extended to a first side of the second gate structure (520, 513-2) and a first side of the third gate structure (522, 513-31); a fourth gate structure (571, 563-1) formed on the surface of the substrate for receiving the word line voltage during the read cycle; a fifth gate structure (570, 563-2) formed on the surface of the substrate for receiving the read voltage during the read cycle; a sixth gate structure (572, 563-3) formed on the surface of the substrate; a third diffusion region formed in the surface of the substrate and located adjacent to a first side of the fourth gate structure (571, 563-1) for generating a second bit line voltage during the read cycle; and a fourth diffusion region formed in the surface of the substrate, and located adjacent to a second side of the fourth gate structure (571, 563-1) and extended to a first side of the fifth gate structure (570, 563-2) and a first side of the sixth gate structure (572, 563-3), wherein the fourth diffusion region receives the read voltage during the read cycle, wherein the first bit line voltage is different from the second bit line voltage. a substrate; a first gate structure (521, 513-1) formed on a surface of the substrate for receiving a word line voltage during a read cycle; a second gate structure (520, 513-2) formed on the surface of the substrate for receiving a read voltage during the read cycle; a third gate structure (522, 513-3) formed on the surface of the substrate; a first diffusion region formed in the surface of the substrate and located adjacent to a first side of the first gate structure (521, 513-1) for generating a first bit line voltage during the read cycle; a second diffusion region formed in the surface of the substrate, and located adjacent to a second side of the first gate structure (521, 513-1) and extended to a first side of the second gate structure (520, 513-2) and a first side of the third gate structure (522, 513-31); a fourth gate structure (571, 563-1) formed on the surface of the substrate for receiving the word line voltage during the read cycle; a fifth gate structure (570, 563-2) formed on the surface of the substrate for receiving the read voltage during the read cycle; a sixth gate structure (572, 563-3) formed on the surface of the substrate; a third diffusion region formed in the surface of the substrate and located adjacent to a first side of the fourth gate structure (571, 563-1) for generating a second bit line voltage during the read cycle; and a fourth diffusion region formed in the surface of the substrate, and located adjacent to a second side of the fourth gate structure (571, 563-1) and extended to a first side of the fifth gate structure (570, 563-2) and a first side of the sixth gate structure (572, 563-3), wherein the fourth diffusion region receives the read voltage during the read cycle, wherein the first bit line voltage is different from the second bit line voltage.