An image sensor comprising: a plurality of vertical charge-coupled device (VCCD) shift registers; a plurality of independently-controllable gate electrodes (702/704/706/708/710/712/714/716) disposed over the VCCD shift registers and arranged into physically separate and distinct sections (718/720), the physically separate and distinct sections (718/720) being separated by a physical gap in the gate electrodes extending vertically between the sections to electrically isolate the gate electrodes of one section from the gate electrodes of the other section; a plurality of horizontal charge-coupled device (HCCD) shift registers (1204/1206/1304/1306) each including a plurality of charge storage elements, wherein each charge storage element is connected to a respective VCCD shift register to receive charge directly from the respective VCCD shift register, wherein each one of said physically separate and distinct sections (718/720) comprises respective first (1206/1304) and second (1306/1204) corresponding HCCDs; and one or more timing generators configured to produce VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and into respective HCCD shift registers (1206/1306) and configured to produce HCCD clocking signals applied to respective gate electrodes for shifting charge through the HCCD shift registers (1206/1306), characterized in that: the one or more timing generators produce VCCD and HCCD clocking signals for a full resolution image readout mode to shift charge packets from each of the physically separate and distinct sections (718/720) into one of its HCCDs (1204/1206) and then to a first output circuit, and for a full resolution charge multiplication mode to shift charge packets in one direction from a first section within its first HCCD to the second HCCD of a second section operated in charge multiplication mode to the first output circuit and to shift charge packets in the opposite direction from a second section within its first HCCD to the second HCCD of the first section operated in charge multiplication mode to a second output circuit. a plurality of vertical charge-coupled device (VCCD) shift registers; a plurality of independently-controllable gate electrodes (702/704/706/708/710/712/714/716) disposed over the VCCD shift registers and arranged into physically separate and distinct sections (718/720), the physically separate and distinct sections (718/720) being separated by a physical gap in the gate electrodes extending vertically between the sections to electrically isolate the gate electrodes of one section from the gate electrodes of the other section; a plurality of horizontal charge-coupled device (HCCD) shift registers (1204/1206/1304/1306) each including a plurality of charge storage elements, wherein each charge storage element is connected to a respective VCCD shift register to receive charge directly from the respective VCCD shift register, wherein each one of said physically separate and distinct sections (718/720) comprises respective first (1206/1304) and second (1306/1204) corresponding HCCDs; and one or more timing generators configured to produce VCCD clocking signals applied to respective independently-controllable gate electrodes for shifting charge through the VCCD shift registers and into respective HCCD shift registers (1206/1306) and configured to produce HCCD clocking signals applied to respective gate electrodes for shifting charge through the HCCD shift registers (1206/1306), characterized in that: the one or more timing generators produce VCCD and HCCD clocking signals for a full resolution image readout mode to shift charge packets from each of the physically separate and distinct sections (718/720) into one of its HCCDs (1204/1206) and then to a first output circuit, and for a full resolution charge multiplication mode to shift charge packets in one direction from a first section within its first HCCD to the second HCCD of a second section operated in charge multiplication mode to the first output circuit and to shift charge packets in the opposite direction from a second section within its first HCCD to the second HCCD of the first section operated in charge multiplication mode to a second output circuit.