A memory device provided with: - a set of memory cells (C 1m, C 2m, C 3m, C 4m, C 5m, C 6m, C 7m, C 8m, C i, C k), each memory cell of said set comprising: - a first node and a second node, - a first inverter and a second inverter connected in a manner crossed between said first node and said second node, the memory device further comprising: - a first supply line (LVDD1) connected to one of a first transistor of the first inverter and a second transistor of the second inverter, - a second supply line (LVDD2) connected to the other of said first transistor of the first inverter and said second transistor of the second inverter, the second supply line being distinct from the first supply line, the memory device being provided with a circuit (40, 50, 60) configured for, during an initialisation sequence: - during a first phase, applying a first pair of potentials (VDD1 high, VDD2 low), respectively to the first supply line (LVDD1) and the second supply line (LVDD2), so as to impose on the cells of said set, pre-load logic data the respective values of which depend on the supply line of said first and second supply lines to which the first transistor thereof and the second transistor thereof are respectively connected, then - during a second phase, applying a second pair of potentials (VDD1 low, VDD2 high) respectively to said first supply line (LVDD1) and the second supply line (LVDD2), the second pair of potentials being different from the first pair of potentials and provided so as to keep said pre-load logic data and make the cells of said set readable and writeable, and wherein two neighbouring memory cells (C 1m, C 2m) of said set share a first common connection area with one of said first supply line (LVDD1) or second supply line (LVDD2) that is chosen according to the desired value of the pre-load logic data to be imposed on one of the two neighbouring memory cells of said set during the first phase of the initialisation sequence, first cell (C 1m, C i) of said set having the first inverter thereof connected to the first supply line and the second inverter thereof connected to the second supply line, the second cell (C 2m, C k) of said set having the two inverters thereof connected to the same given supply line from said first supply line and second supply line or having the first inverter thereof connected to the second supply line and the second inverter thereof connected to the first supply line. - a set of memory cells (C 1m, C 2m, C 3m, C 4m, C 5m, C 6m, C 7m, C 8m, C i, C k), each memory cell of said set comprising: - a first node and a second node, - a first inverter and a second inverter connected in a manner crossed between said first node and said second node, - a first supply line (LVDD1) connected to one of a first transistor of the first inverter and a second transistor of the second inverter, - a second supply line (LVDD2) connected to the other of said first transistor of the first inverter and said second transistor of the second inverter, the second supply line being distinct from the first supply line, - during a first phase, applying a first pair of potentials (VDD1 high, VDD2 low), respectively to the first supply line (LVDD1) and the second supply line (LVDD2), so as to impose on the cells of said set, pre-load logic data the respective values of which depend on the supply line of said first and second supply lines to which the first transistor thereof and the second transistor thereof are respectively connected, then - during a second phase, applying a second pair of potentials (VDD1 low, VDD2 high) respectively to said first supply line (LVDD1) and the second supply line (LVDD2), the second pair of potentials being different from the first pair of potentials and provided so as to keep said pre-load logic data and make the cells of said set readable and writeable, first cell (C 1m, C i) of said set having the first inverter thereof connected to the first supply line and the second inverter thereof connected to the second supply line, the second cell (C 2m, C k) of said set having the two inverters thereof connected to the same given supply line from said first supply line and second supply line or having the first inverter thereof connected to the second supply line and the second inverter thereof connected to the first supply line.