A processor comprising: a coprocessor issue circuit comprising a queue, wherein the processor is configured to store coprocessor instructions for a coprocessor to which the processor is coupled in the queue; a data cache; and an interface unit coupled to the coprocessor issue circuit, the interface uni comprising a buffer including a plurality of entries; wherein: the interface unit is configured to allocate a first entry of the plurality of entries in response to receiving first data corresponding to one or more first coprocessor instructions issued by the coprocessor issue circuit from the queue to the interface unit, and the interface unit is configured to write the first data to the entry; the interface unit is configured to merge second data corresponding to one or more additional coprocessor instructions in the first entry in response to receiving the second data issued by the coprocessor issue circuit; the interface unit is configured to transmit a command describing the one or more first coprocessor instructions and the one or more additional coprocessor instructions, the first data, and the second data to the coprocessor; the command, the first data, and the second data identify the one or more first coprocessor instructions and the one or more additional coprocessor instructions to the coprocessor; and the interface unit is configured to allocate a second entry of the plurality of entries in the buffer to store a cache line of data evicted from the data cache for transmission to a next level cache external to the processor. a coprocessor issue circuit comprising a queue, wherein the processor is configured to store coprocessor instructions for a coprocessor to which the processor is coupled in the queue; a data cache; and an interface unit coupled to the coprocessor issue circuit, the interface uni comprising a buffer including a plurality of entries; wherein: the interface unit is configured to allocate a first entry of the plurality of entries in response to receiving first data corresponding to one or more first coprocessor instructions issued by the coprocessor issue circuit from the queue to the interface unit, and the interface unit is configured to write the first data to the entry; the interface unit is configured to merge second data corresponding to one or more additional coprocessor instructions in the first entry in response to receiving the second data issued by the coprocessor issue circuit; the interface unit is configured to transmit a command describing the one or more first coprocessor instructions and the one or more additional coprocessor instructions, the first data, and the second data to the coprocessor; the command, the first data, and the second data identify the one or more first coprocessor instructions and the one or more additional coprocessor instructions to the coprocessor; and the interface unit is configured to allocate a second entry of the plurality of entries in the buffer to store a cache line of data evicted from the data cache for transmission to a next level cache external to the processor. the interface unit is configured to allocate a first entry of the plurality of entries in response to receiving first data corresponding to one or more first coprocessor instructions issued by the coprocessor issue circuit from the queue to the interface unit, and the interface unit is configured to write the first data to the entry; the interface unit is configured to merge second data corresponding to one or more additional coprocessor instructions in the first entry in response to receiving the second data issued by the coprocessor issue circuit; the interface unit is configured to transmit a command describing the one or more first coprocessor instructions and the one or more additional coprocessor instructions, the first data, and the second data to the coprocessor; the command, the first data, and the second data identify the one or more first coprocessor instructions and the one or more additional coprocessor instructions to the coprocessor; and the interface unit is configured to allocate a second entry of the plurality of entries in the buffer to store a cache line of data evicted from the data cache for transmission to a next level cache external to the processor.