A multi-port memory cell of a multi-port memory array, wherein the multi-port memory cell is written using a plurality of write word lines (WWL0-3) and a plurality of write bit lines (WBL0-1, WBL2B-3B), comprising: a storage circuit (514, 516) comprising: a first inverter having an input and an output, wherein the first inverter is disabled by a first subset (WWL0-1) of the plurality of write word lines; and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, wherein the second inverter is disabled by a second subset (WWL2-3) of the plurality of write word lines; a first selection circuit (502, 504, 506) having data inputs coupled to a first subset (WBL0-1) of the plurality of write bit lines, selection inputs coupled to the first subset (WWL0-1) of the plurality of write word lines, and an output coupled to the input of the second inverter; and a second selection circuit (510, 512, 508) having data inputs coupled to a second subset (WBL2B-3B) of the plurality of write bit lines, selection inputs coupled to the second subset (WWL2-3) of the plurality of write word lines, and an output coupled to the input of the first inverter, wherein the first selection circuit (502, 504, 506) comprises a multiplexor (502, 504) coupled to the first subset (WBL0-1) of the plurality of write bit lines and further comprises a third inverter having an input coupled to an output of the multiplexor (502, 504) and an output coupled to the input of the second inverter and the output of the first inverter, and wherein the third inverter is a tristate device controlled by the first subset (WWL0-1) of the plurality of write word lines and configured to be enabled when the first inverter is disabled. a storage circuit (514, 516) comprising: a first inverter having an input and an output, wherein the first inverter is disabled by a first subset (WWL0-1) of the plurality of write word lines; and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, wherein the second inverter is disabled by a second subset (WWL2-3) of the plurality of write word lines; a first inverter having an input and an output, wherein the first inverter is disabled by a first subset (WWL0-1) of the plurality of write word lines; and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, wherein the second inverter is disabled by a second subset (WWL2-3) of the plurality of write word lines; a first selection circuit (502, 504, 506) having data inputs coupled to a first subset (WBL0-1) of the plurality of write bit lines, selection inputs coupled to the first subset (WWL0-1) of the plurality of write word lines, and an output coupled to the input of the second inverter; and a second selection circuit (510, 512, 508) having data inputs coupled to a second subset (WBL2B-3B) of the plurality of write bit lines, selection inputs coupled to the second subset (WWL2-3) of the plurality of write word lines, and an output coupled to the input of the first inverter, wherein the first selection circuit (502, 504, 506) comprises a multiplexor (502, 504) coupled to the first subset (WBL0-1) of the plurality of write bit lines and further comprises a third inverter having an input coupled to an output of the multiplexor (502, 504) and an output coupled to the input of the second inverter and the output of the first inverter, and wherein the third inverter is a tristate device controlled by the first subset (WWL0-1) of the plurality of write word lines and configured to be enabled when the first inverter is disabled.