An inverting charge pump configured to generate a negative voltage, the inverting charge pump comprising: a first terminal configured to receive a dc input voltage; a second and a third terminal configured to connect to a flying capacitor; a fourth terminal configured to supply the negative voltage as output; a charging path comprising: a first pre-driver circuit connected to the first terminal and driving a first switching arrangement, the first switching arrangement being connected to the second terminal; a first current limit Metal Oxide Semiconductor, MOS, transistor device connected with the first switching arrangement and configured to limit a first switching arrangement peak current; and a second pre-driver circuit connected to the first terminal and driving a second switching arrangement connected to the third terminal through a first cascode device; and a dumping path comprising: a third pre-driver circuit connected to the first terminal and driving a third switching arrangement, the third switching arrangement being connected to the second terminal and the fourth terminal; a second current limiting MOS transistor device connected in series to a negative feedback controlled device and to a second cascode device, the second current limiting MOS transistor device being configured to limit a negative feedback controller device peak current, the second cascode device being connected to the third terminal; and the negative feedback controller being connected to the fourth terminal and being configured to regulate the output negative voltage. a first terminal configured to receive a dc input voltage; a second and a third terminal configured to connect to a flying capacitor; a fourth terminal configured to supply the negative voltage as output; a charging path comprising: a first pre-driver circuit connected to the first terminal and driving a first switching arrangement, the first switching arrangement being connected to the second terminal; a first current limit Metal Oxide Semiconductor, MOS, transistor device connected with the first switching arrangement and configured to limit a first switching arrangement peak current; and a second pre-driver circuit connected to the first terminal and driving a second switching arrangement connected to the third terminal through a first cascode device; and a first pre-driver circuit connected to the first terminal and driving a first switching arrangement, the first switching arrangement being connected to the second terminal; a first current limit Metal Oxide Semiconductor, MOS, transistor device connected with the first switching arrangement and configured to limit a first switching arrangement peak current; and a second pre-driver circuit connected to the first terminal and driving a second switching arrangement connected to the third terminal through a first cascode device; and a dumping path comprising: a third pre-driver circuit connected to the first terminal and driving a third switching arrangement, the third switching arrangement being connected to the second terminal and the fourth terminal; a second current limiting MOS transistor device connected in series to a negative feedback controlled device and to a second cascode device, the second current limiting MOS transistor device being configured to limit a negative feedback controller device peak current, the second cascode device being connected to the third terminal; and the negative feedback controller being connected to the fourth terminal and being configured to regulate the output negative voltage. a third pre-driver circuit connected to the first terminal and driving a third switching arrangement, the third switching arrangement being connected to the second terminal and the fourth terminal; a second current limiting MOS transistor device connected in series to a negative feedback controlled device and to a second cascode device, the second current limiting MOS transistor device being configured to limit a negative feedback controller device peak current, the second cascode device being connected to the third terminal; and the negative feedback controller being connected to the fourth terminal and being configured to regulate the output negative voltage.