A computer-implemented method executed by a computing system having one or more processors, the method comprising: monitoring execution of program code by a first processor component, the first processor component being configured to execute at least a first portion of the program code; monitoring execution of the program code by a second processor component, the second processor component being configured to execute at least a second portion of the program code; storing, by the computing system, data identifying one or more hardware events (322, 324) occurring across processor units that include the first processor component and the second processor component, each hardware event representing at least one of data communications associated with a memory access operation of the program code, an issued instruction of the program code, or an executed instruction of the program code, wherein the data identifying each of the one or more hardware events comprises a hardware event time stamp and metadata characterizing the hardware event; generating, by the computing system, a data structure that identifies the one or more hardware events, the data structure being configured to arrange the one or more hardware events in a time ordered sequence of events that are associated with at least the first processor component and the second processor component, and storing, by the computing system, the generated data structure in a memory bank of a host device, characterized in that: the data structure comprises a particular trace identifier, ID, that is associated with multiple hardware events, corresponding to a particular memory access operation, that occur across the processor units, and wherein the particular trace ID is used to correlate one or more hardware events of the multiple hardware events. monitoring execution of program code by a first processor component, the first processor component being configured to execute at least a first portion of the program code; monitoring execution of the program code by a second processor component, the second processor component being configured to execute at least a second portion of the program code; storing, by the computing system, data identifying one or more hardware events (322, 324) occurring across processor units that include the first processor component and the second processor component, each hardware event representing at least one of data communications associated with a memory access operation of the program code, an issued instruction of the program code, or an executed instruction of the program code, wherein the data identifying each of the one or more hardware events comprises a hardware event time stamp and metadata characterizing the hardware event; generating, by the computing system, a data structure that identifies the one or more hardware events, the data structure being configured to arrange the one or more hardware events in a time ordered sequence of events that are associated with at least the first processor component and the second processor component, and storing, by the computing system, the generated data structure in a memory bank of a host device, characterized in that: the data structure comprises a particular trace identifier, ID, that is associated with multiple hardware events, corresponding to a particular memory access operation, that occur across the processor units, and wherein the particular trace ID is used to correlate one or more hardware events of the multiple hardware events.