A method of fabricating a polycrystalline silicon thin film transistor, comprising: forming an amorphous silicon layer (aSi) on a base substrate having a pattern corresponding to a polycrystalline silicon active layer (LTPS) of the thin film transistor, the amorphous silicon layer (aSi) having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer (LTPS) and a second region corresponding to a channel region in the polycrystalline silicon active layer (LTPS); forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; crystallizing the amorphous silicon layer (aSi) to form the polycrystalline silicon active layer (LTPS), a dopant of the first dopant layer diffusing into the second region and a dopant of the second dopant layer diffusing into the first region during the step of crystallizing the amorphous silicon layer (aSi), wherein the first dopant layer is formed on a side of both the first region and the second region distal to the base substrate; and the polycrystalline silicon active layer (LTPS) in the first region is doped with both the dopant of the first dopant layer and the dopant of the second dopant layer, wherein after the step of crystallizing the amorphous silicon layer (aSi), the method further comprises: forming a gate insulating layer on a side of the polycrystalline silicon active layer (LTPS) distal to the base substrate; forming a gate electrode layer on a side of the gate insulating layer distal to the polycrystalline silicon active layer (LTPS); forming a source via and a drain via in areas corresponding to the first region, the source via and the drain via extending through the gate insulating layer, exposing the first region of the polycrystalline silicon active layer (LTPS); and forming a source electrode and a drain electrode on a side of the gate insulating layer distal to the base substrate, the source electrode extending through the source via and in contact with the polycrystalline silicon active layer (LTPS), the drain electrode extending through the drain via and in contact with the polycrystalline silicon active layer (LTPS). forming an amorphous silicon layer (aSi) on a base substrate having a pattern corresponding to a polycrystalline silicon active layer (LTPS) of the thin film transistor, the amorphous silicon layer (aSi) having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer (LTPS) and a second region corresponding to a channel region in the polycrystalline silicon active layer (LTPS); forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; crystallizing the amorphous silicon layer (aSi) to form the polycrystalline silicon active layer (LTPS), a dopant of the first dopant layer diffusing into the second region and a dopant of the second dopant layer diffusing into the first region during the step of crystallizing the amorphous silicon layer (aSi), wherein the first dopant layer is formed on a side of both the first region and the second region distal to the base substrate; and the polycrystalline silicon active layer (LTPS) in the first region is doped with both the dopant of the first dopant layer and the dopant of the second dopant layer, wherein after the step of crystallizing the amorphous silicon layer (aSi), the method further comprises: forming a gate insulating layer on a side of the polycrystalline silicon active layer (LTPS) distal to the base substrate; forming a gate electrode layer on a side of the gate insulating layer distal to the polycrystalline silicon active layer (LTPS); forming a source via and a drain via in areas corresponding to the first region, the source via and the drain via extending through the gate insulating layer, exposing the first region of the polycrystalline silicon active layer (LTPS); and forming a source electrode and a drain electrode on a side of the gate insulating layer distal to the base substrate, the source electrode extending through the source via and in contact with the polycrystalline silicon active layer (LTPS), the drain electrode extending through the drain via and in contact with the polycrystalline silicon active layer (LTPS). forming a gate insulating layer on a side of the polycrystalline silicon active layer (LTPS) distal to the base substrate; forming a gate electrode layer on a side of the gate insulating layer distal to the polycrystalline silicon active layer (LTPS); forming a source via and a drain via in areas corresponding to the first region, the source via and the drain via extending through the gate insulating layer, exposing the first region of the polycrystalline silicon active layer (LTPS); and forming a source electrode and a drain electrode on a side of the gate insulating layer distal to the base substrate, the source electrode extending through the source via and in contact with the polycrystalline silicon active layer (LTPS), the drain electrode extending through the drain via and in contact with the polycrystalline silicon active layer (LTPS).