A heterostructure semiconductor device (100, 200, 300, 400) comprising: a first active layer (222, 322, 422, 522); a second active layer (224, 324, 424, 524) disposed on the first active layer, an electrical charge layer being disposed at a heterojunction between the first and second active layers; a power transistor (102, 202, 302, 402) having a first active area which includes a first portion of the first active layer and a first portion of the second active layer, in operation, a current flowing through a first portion of the electrical charge layer; a gate array (116, 216, 316, 416) that laterally extends over the first active area of the power transistor, the gate array functioning as a gate of the power transistor, wherein the gate array comprises a plurality of fingers, each of which extends in a first lateral direction over the first active area, and a connecting portion that extends in a second lateral direction that is substantially perpendicular to the first lateral direction, the plurality of fingers being connected to each other via the connecting portion; a gate resistor (104, 204, 304, 404, 504) having a second active area which includes a second portion of the first active layer, a second portion of the second active layer, and a second portion of the electrical charge layer (226, 326, 426, 526), the second active area being electrically isolated from the first active area; first and second via ohmic contacts (214, 218, 314, 318, 414, 418) respectively disposed at first and second lateral ends of the gate resistor, the first and second via ohmic contacts being electrically connected to the second portion of the second active layer, the second via ohmic contact also being electrically connected to an overlying portion of the gate array; and a gate bus (112, 212, 312, 412) electrically connected to a gate and control terminal of the power transistor and to the first via ohmic contact, wherein the gate bus and the gate array are in a single layer of gate metal that is patterned into separate sections, wherein the gate bus overlays a portion of the gate resistor, and wherein the gate array and the gate bus are insulated from the second active layer by a gate dielectric layer (228, 328, 428, 528). a first active layer (222, 322, 422, 522); a second active layer (224, 324, 424, 524) disposed on the first active layer, an electrical charge layer being disposed at a heterojunction between the first and second active layers; a power transistor (102, 202, 302, 402) having a first active area which includes a first portion of the first active layer and a first portion of the second active layer, in operation, a current flowing through a first portion of the electrical charge layer; a gate array (116, 216, 316, 416) that laterally extends over the first active area of the power transistor, the gate array functioning as a gate of the power transistor, wherein the gate array comprises a plurality of fingers, each of which extends in a first lateral direction over the first active area, and a connecting portion that extends in a second lateral direction that is substantially perpendicular to the first lateral direction, the plurality of fingers being connected to each other via the connecting portion; a plurality of fingers, each of which extends in a first lateral direction over the first active area, and a connecting portion that extends in a second lateral direction that is substantially perpendicular to the first lateral direction, the plurality of fingers being connected to each other via the connecting portion; a gate resistor (104, 204, 304, 404, 504) having a second active area which includes a second portion of the first active layer, a second portion of the second active layer, and a second portion of the electrical charge layer (226, 326, 426, 526), the second active area being electrically isolated from the first active area; first and second via ohmic contacts (214, 218, 314, 318, 414, 418) respectively disposed at first and second lateral ends of the gate resistor, the first and second via ohmic contacts being electrically connected to the second portion of the second active layer, the second via ohmic contact also being electrically connected to an overlying portion of the gate array; and a gate bus (112, 212, 312, 412) electrically connected to a gate and control terminal of the power transistor and to the first via ohmic contact, wherein the gate bus and the gate array are in a single layer of gate metal that is patterned into separate sections, wherein the gate bus overlays a portion of the gate resistor, and wherein the gate array and the gate bus are insulated from the second active layer by a gate dielectric layer (228, 328, 428, 528).