A processor, characterized by: an approximation control register, configured to hold information specifying an approximation policy for the processor, the approximation policy being used on data in order to render pixels on a display (606A, 606B, 606C) of the computer system (602A, 602B, 602C), wherein the approximation control register includes an approximation flag configured to provide an indication to selectively indicate one of a full accuracy mode in which computations are to be performed with a full degree of accuracy and an approximate computation mode in which the computations are to be performed approximately according to a display resolution of the display (606A, 606B, 606C), an approximation amount configured to specify multiple degrees of approximation that are less than the full degree of accuracy, and an error threshold that specifies an amount of accumulated error that can be tolerated, and the approximation control register is writable by an instruction set instruction; architectural registers configured to hold operands; error storage associated with each architectural register that is configured to provide an indication of an amount of error in a result stored in each architectural register; and an execution unit, configured to receive one or more operands from the architectural registers and error amounts from the associated error storages, perform computations according to the approximation policy stored in the approximation control register, with a full degree of accuracy when the approximation control register so indicates, and approximately to a selected degree of approximation that is specified by the approximation policy being used on data in order to render pixels on a display (606A, 606B, 606C) of the computer system (602A, 602B, 602C) when the approximation policy so indicates. an approximation control register, configured to hold information specifying an approximation policy for the processor, the approximation policy being used on data in order to render pixels on a display (606A, 606B, 606C) of the computer system (602A, 602B, 602C), wherein the approximation control register includes an approximation flag configured to provide an indication to selectively indicate one of a full accuracy mode in which computations are to be performed with a full degree of accuracy and an approximate computation mode in which the computations are to be performed approximately according to a display resolution of the display (606A, 606B, 606C), an approximation amount configured to specify multiple degrees of approximation that are less than the full degree of accuracy, and an error threshold that specifies an amount of accumulated error that can be tolerated, and the approximation control register is writable by an instruction set instruction; architectural registers configured to hold operands; error storage associated with each architectural register that is configured to provide an indication of an amount of error in a result stored in each architectural register; and an execution unit, configured to receive one or more operands from the architectural registers and error amounts from the associated error storages, perform computations according to the approximation policy stored in the approximation control register, with a full degree of accuracy when the approximation control register so indicates, and approximately to a selected degree of approximation that is specified by the approximation policy being used on data in order to render pixels on a display (606A, 606B, 606C) of the computer system (602A, 602B, 602C) when the approximation policy so indicates.