A protection system comprising: a power terminal, wherein a predetermined power supply voltage being configured to be supplied to the power terminal from an external power supply; a semiconductor integrated circuit connected to the power terminal; and a protection circuit comprising a switch connected to the semiconductor integrated circuit, a first N-channel MOSFET (NMOS) transistor, a third NMOS transistor, a fourth NMOS transistor and a zener diode, the switch configured to prevent an electrical conduction to the semiconductor integrated circuit when the external power supply is reverse-connected to the power terminal, wherein the switch is a second NMOS transistor, a gate of the second NMOS transistor is connected to a gate and a source of the first NMOS transistor of which a drain is connected to the power terminal, a drain of the second NMOS transistor is connected to an earth terminal, and a source of the second NMOS transistor is connected to the semiconductor integrated circuit, wherein a drain of the third NMOS transistor and a gate and a source of the fourth NMOS transistor are connected to a backgate of the second NMOS transistor, a gate of the third NMOS transistor is connected to the gate and the source of the first NMOS transistor, a source of the third NMOS transistor is connected to the earth terminal, and a drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor, wherein the first NMOS transistor and the fourth NMOS transistor are respectively depletion mode N-channel MOSFETs, and the second NMOS transistor and the third NMOS transistor are respectively enhancement mode N-channel MOSFETs wherein an anode of the Zener diode is connected to the source of the second NMOS transistor and a cathode of the Zener diode is connected to the gate and the source of the first NMOS transistor, wherein when the external power supply is configured to be reverse-connected to the power terminal, the protection circuit is configured to turn off the third NMOS transistor, turn on the fourth NMOS transistor and turn off the second NMOS transistor, and further to interrupt a current path from the earth terminal side to the power terminal side, thereby protecting the semiconductor integrated circuit from a breakdown. a power terminal, wherein a predetermined power supply voltage being configured to be supplied to the power terminal from an external power supply; a semiconductor integrated circuit connected to the power terminal; and a protection circuit comprising a switch connected to the semiconductor integrated circuit, a first N-channel MOSFET (NMOS) transistor, a third NMOS transistor, a fourth NMOS transistor and a zener diode, the switch configured to prevent an electrical conduction to the semiconductor integrated circuit when the external power supply is reverse-connected to the power terminal, wherein the switch is a second NMOS transistor, a gate of the second NMOS transistor is connected to a gate and a source of the first NMOS transistor of which a drain is connected to the power terminal, a drain of the second NMOS transistor is connected to an earth terminal, and a source of the second NMOS transistor is connected to the semiconductor integrated circuit, wherein a drain of the third NMOS transistor and a gate and a source of the fourth NMOS transistor are connected to a backgate of the second NMOS transistor, a gate of the third NMOS transistor is connected to the gate and the source of the first NMOS transistor, a source of the third NMOS transistor is connected to the earth terminal, and a drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor, wherein the first NMOS transistor and the fourth NMOS transistor are respectively depletion mode N-channel MOSFETs, and the second NMOS transistor and the third NMOS transistor are respectively enhancement mode N-channel MOSFETs wherein an anode of the Zener diode is connected to the source of the second NMOS transistor and a cathode of the Zener diode is connected to the gate and the source of the first NMOS transistor, wherein when the external power supply is configured to be reverse-connected to the power terminal, the protection circuit is configured to turn off the third NMOS transistor, turn on the fourth NMOS transistor and turn off the second NMOS transistor, and further to interrupt a current path from the earth terminal side to the power terminal side, thereby protecting the semiconductor integrated circuit from a breakdown.