A band-pass filter circuit comprising: a first high-pass filter circuit comprising: a first capacitor configured to input an input signal; a first resistor connected between a first output terminal of the first capacitor and a prescribed bias voltage; and wherein the first resistor is formed on an SOI semiconductor substrate and includes a first N-channel MOS transistor and a second N-channel MOS transistor that are inversely connected to each other in parallel, the first and second MOS transistors (6, 7) operate within a first cutoff range, a drain of the first MOS transistor and a gate, source, and back gate of the second MOS transistor are connected to the first output terminal of the first capacitor, and a gate, source, and back gate of the first MOS transistor and a drain of the second MOS transistor are connected to the bias voltage; a second high-pass filter circuit comprising: a second capacitor configured to input the input signal; a second resistor connected between a second output terminal of the second capacitor and the prescribed bias voltage; and wherein the second resistor is formed on an SOI semiconductor substrate and includes a third P-channel MOS transistor and a fourth P-channel MOS transistor that are inversely connected to each other in parallel, the third and fourth MOS transistors (8, 9) operate within a second cutoff range, a gate, source, and back gate of the third MOS transistor and a drain of the fourth MOS transistor are connected to the second output terminal of the second capacitor, and a drain of the third MOS transistor and a gate, source, and back gate of the fourth MOS transistor are connected to the bias voltage; and a signal output circuit configured to generate and output a difference signal between a signal output from the first high-pass filter circuit and a signal output from the second high-pass filter circuit, wherein the second high-pass filter circuit has a frequency characteristic different from that of the first high-pass filter circuit. a first high-pass filter circuit comprising: a first capacitor configured to input an input signal; a first resistor connected between a first output terminal of the first capacitor and a prescribed bias voltage; and wherein the first resistor is formed on an SOI semiconductor substrate and includes a first N-channel MOS transistor and a second N-channel MOS transistor that are inversely connected to each other in parallel, the first and second MOS transistors (6, 7) operate within a first cutoff range, a drain of the first MOS transistor and a gate, source, and back gate of the second MOS transistor are connected to the first output terminal of the first capacitor, and a gate, source, and back gate of the first MOS transistor and a drain of the second MOS transistor are connected to the bias voltage; a first capacitor configured to input an input signal; a first resistor connected between a first output terminal of the first capacitor and a prescribed bias voltage; and wherein the first resistor is formed on an SOI semiconductor substrate and includes a first N-channel MOS transistor and a second N-channel MOS transistor that are inversely connected to each other in parallel, the first and second MOS transistors (6, 7) operate within a first cutoff range, a drain of the first MOS transistor and a gate, source, and back gate of the second MOS transistor are connected to the first output terminal of the first capacitor, and a gate, source, and back gate of the first MOS transistor and a drain of the second MOS transistor are connected to the bias voltage; a second high-pass filter circuit comprising: a second capacitor configured to input the input signal; a second resistor connected between a second output terminal of the second capacitor and the prescribed bias voltage; and wherein the second resistor is formed on an SOI semiconductor substrate and includes a third P-channel MOS transistor and a fourth P-channel MOS transistor that are inversely connected to each other in parallel, the third and fourth MOS transistors (8, 9) operate within a second cutoff range, a gate, source, and back gate of the third MOS transistor and a drain of the fourth MOS transistor are connected to the second output terminal of the second capacitor, and a drain of the third MOS transistor and a gate, source, and back gate of the fourth MOS transistor are connected to the bias voltage; and a second capacitor configured to input the input signal; a second resistor connected between a second output terminal of the second capacitor and the prescribed bias voltage; and wherein the second resistor is formed on an SOI semiconductor substrate and includes a third P-channel MOS transistor and a fourth P-channel MOS transistor that are inversely connected to each other in parallel, the third and fourth MOS transistors (8, 9) operate within a second cutoff range, a gate, source, and back gate of the third MOS transistor and a drain of the fourth MOS transistor are connected to the second output terminal of the second capacitor, and a drain of the third MOS transistor and a gate, source, and back gate of the fourth MOS transistor are connected to the bias voltage; and a signal output circuit configured to generate and output a difference signal between a signal output from the first high-pass filter circuit and a signal output from the second high-pass filter circuit, wherein the second high-pass filter circuit has a frequency characteristic different from that of the first high-pass filter circuit.