A transformer provided between a power supply and a load, and composed of a front stage circuit and a rear stage circuit, the transformer wherein: the front stage circuit comprises, a switch series unit composed of a plurality of switches, the plurality being a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply, and under a condition that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and connect the odd nodes to a first output port (Px), the second electrical path being configured to combine even nodes and connect the even nodes to a second output port (Py), the capacitors in total of the first electrical path and the second electrical path being present so as to correspond to at least (m - 1) nodes; the rear stage circuit comprises, an element series unit composed of a pair of semiconductor elements (D11, D12) that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being directly connected to the first output port (Px) while the other end thereof being directly connected to the second output port (Py), and inductors (L1, L2) provided on at least one electrical path of a third electrical path and a fourth electrical path, the third electrical path being configured to combine two nodes that are points at the both ends of the element series unit and to connect the two nodes to one of both ends of the load, the fourth electrical path being configured to connect one node that is a mutual connection point of the pair of semiconductor elements to the other end of the load, the inductors (L1, L2) being present so as to correspond to at least two nodes of the three nodes in total; and a control section configured to control ON/OFF operations of the switches. the front stage circuit comprises, a switch series unit composed of a plurality of switches, the plurality being a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply, and under a condition that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and connect the odd nodes to a first output port (Px), the second electrical path being configured to combine even nodes and connect the even nodes to a second output port (Py), the capacitors in total of the first electrical path and the second electrical path being present so as to correspond to at least (m - 1) nodes; the rear stage circuit comprises, an element series unit composed of a pair of semiconductor elements (D11, D12) that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being directly connected to the first output port (Px) while the other end thereof being directly connected to the second output port (Py), and inductors (L1, L2) provided on at least one electrical path of a third electrical path and a fourth electrical path, the third electrical path being configured to combine two nodes that are points at the both ends of the element series unit and to connect the two nodes to one of both ends of the load, the fourth electrical path being configured to connect one node that is a mutual connection point of the pair of semiconductor elements to the other end of the load, the inductors (L1, L2) being present so as to correspond to at least two nodes of the three nodes in total; and a control section configured to control ON/OFF operations of the switches.