A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate (9, 10); an array of memory stack structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced along a second horizontal direction, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures along the first horizontal direction and the second horizontal direction, wherein each of the drain select level assemblies comprises a drain select level channel portion contacting a respective memory level channel portion; drain select gate electrodes (152, 154) laterally surrounding respective rows of drain select level assemblies; and a drain select level isolation strip comprising at least one dielectric material and located between a neighboring pair of drain select gate electrodes (152, 154); wherein one of the drain select gate electrodes (152, 154) comprises: a plurality of cylindrical electrode portions that laterally surround a respective one of the drain select level channel portions; and a strip electrode portion on a first subset of the plurality of cylindrical electrode portions, the strip electrode portion including a pair of lengthwise sidewalls that generally extend along the first horizontal direction; characterised in that the drain select level isolation strip comprises a perforated dielectric strip portion including two rows of cylindrical openings therethrough, wherein each of the cylindrical openings laterally surrounds a respective one of a second subset of the drain select level assemblies that is arranged in two rows that extend along the first horizontal direction. an alternating stack of insulating layers and electrically conductive layers located over a substrate (9, 10); an array of memory stack structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced along a second horizontal direction, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures along the first horizontal direction and the second horizontal direction, wherein each of the drain select level assemblies comprises a drain select level channel portion contacting a respective memory level channel portion; drain select gate electrodes (152, 154) laterally surrounding respective rows of drain select level assemblies; and a drain select level isolation strip comprising at least one dielectric material and located between a neighboring pair of drain select gate electrodes (152, 154); wherein one of the drain select gate electrodes (152, 154) comprises: a plurality of cylindrical electrode portions that laterally surround a respective one of the drain select level channel portions; and a strip electrode portion on a first subset of the plurality of cylindrical electrode portions, the strip electrode portion including a pair of lengthwise sidewalls that generally extend along the first horizontal direction; characterised in that the drain select level isolation strip comprises a perforated dielectric strip portion including two rows of cylindrical openings therethrough, wherein each of the cylindrical openings laterally surrounds a respective one of a second subset of the drain select level assemblies that is arranged in two rows that extend along the first horizontal direction. a plurality of cylindrical electrode portions that laterally surround a respective one of the drain select level channel portions; and a strip electrode portion on a first subset of the plurality of cylindrical electrode portions, the strip electrode portion including a pair of lengthwise sidewalls that generally extend along the first horizontal direction; characterised in that the drain select level isolation strip comprises a perforated dielectric strip portion including two rows of cylindrical openings therethrough, wherein each of the cylindrical openings laterally surrounds a respective one of a second subset of the drain select level assemblies that is arranged in two rows that extend along the first horizontal direction.