An organic light emitting diode display (OLED) comprising: a plurality of subpixels (P11-P22) comprising first subpixels (P11, P21) having driving transistors of a first configuration and second subpixels (P12, P22) having driving transistors of a second configuration different from the first configuration, wherein subpixels having driving transistors of the first configuration and subpixels having driving transistors of the second configuration are set as respective first and second blocks (BL1, BL2); a sensing circuit (ADC, DAC) configured to supply a sensing data voltage to subpixels of said first blocks and a sensing data voltage to subpixels of said second blocks, each said first block comprising at least two of the first subpixels (P11, P12; P11, P21) but none of the second subpixels (P12, P22; P21, P22), and each said second block comprising at least two of the second subpixels (P21, P22) but none of the first subpixels (P11, P12); a gate driver configured to transmit scan line signals (S1, S2) to said first blocks and said second blocks and; a data modulator configured to: select one previously set compensation value; and to apply the selected one compensation value to data (DATA) to modulate the data (DATA) to be written to first subpixels (P11, P12) in the first block or second subpixels (P21, P22) in the second block; characterized in that said sensing circuit (ADC, DAC) further comprises a sample and hold circuit, and wherein said sensing circuit is further configured to receive a combined sensing signal via a signal path connected to at least one of a said first block and/or a said second block, the combined sensing signal generated by combining sensing signals through the signal path shared by entire first subpixels (P11, P12) in the first block and/or entire second subpixels (P21, P22) in the second block, each of the sensing signals representing a property of each of the first subpixels (P11, P12) in the first block or each of the second subpixels (P21, P22) in the second block, wherein the sample and hold circuit configured to convert a sum of currents of each block into a sensing voltage to thereby generate the combined sensing signal; and said data modulator is configured to: select one previously set compensation value based on the combined sensing signal; and to apply the selected one compensation value to data (DATA) to thereby modulate the data (DATA) to be written to each of the first subpixels (P11, P12) in the first block or each of the second subpixels (P21, P22) in the second block. a plurality of subpixels (P11-P22) comprising first subpixels (P11, P21) having driving transistors of a first configuration and second subpixels (P12, P22) having driving transistors of a second configuration different from the first configuration, wherein subpixels having driving transistors of the first configuration and subpixels having driving transistors of the second configuration are set as respective first and second blocks (BL1, BL2); a sensing circuit (ADC, DAC) configured to supply a sensing data voltage to subpixels of said first blocks and a sensing data voltage to subpixels of said second blocks, each said first block comprising at least two of the first subpixels (P11, P12; P11, P21) but none of the second subpixels (P12, P22; P21, P22), and each said second block comprising at least two of the second subpixels (P21, P22) but none of the first subpixels (P11, P12); a gate driver configured to transmit scan line signals (S1, S2) to said first blocks and said second blocks and; a data modulator configured to: select one previously set compensation value; and to apply the selected one compensation value to data (DATA) to modulate the data (DATA) to be written to first subpixels (P11, P12) in the first block or second subpixels (P21, P22) in the second block; select one previously set compensation value; and to apply the selected one compensation value to data (DATA) to modulate the data (DATA) to be written to first subpixels (P11, P12) in the first block or second subpixels (P21, P22) in the second block; characterized in that said sensing circuit (ADC, DAC) further comprises a sample and hold circuit, and wherein said sensing circuit is further configured to receive a combined sensing signal via a signal path connected to at least one of a said first block and/or a said second block, the combined sensing signal generated by combining sensing signals through the signal path shared by entire first subpixels (P11, P12) in the first block and/or entire second subpixels (P21, P22) in the second block, each of the sensing signals representing a property of each of the first subpixels (P11, P12) in the first block or each of the second subpixels (P21, P22) in the second block, wherein the sample and hold circuit configured to convert a sum of currents of each block into a sensing voltage to thereby generate the combined sensing signal; and said data modulator is configured to: select one previously set compensation value based on the combined sensing signal; and to apply the selected one compensation value to data (DATA) to thereby modulate the data (DATA) to be written to each of the first subpixels (P11, P12) in the first block or each of the second subpixels (P21, P22) in the second block. select one previously set compensation value based on the combined sensing signal; and to apply the selected one compensation value to data (DATA) to thereby modulate the data (DATA) to be written to each of the first subpixels (P11, P12) in the first block or each of the second subpixels (P21, P22) in the second block.