A multi-thread content-addressable memory, CAM, device comprising: a first input configured to receive a first virtual address corresponding to a first thread; a second input configured to receive a second virtual address corresponding to a second thread; a register bank configured to store translation lookaside buffer, TLB, linear virtual address information including a plurality of registers, wherein each register is configured to store a binary word corresponding to a TLB entry mapped to one of a plurality of physical addresses; a first comparator bank including a first plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration configured to output a first comparison result of the first plurality of comparators, wherein each of the first plurality of comparators is configured to compare one of the first virtual address and a previous first virtual address, based on an active state of the first thread, to a binary word corresponding to a TLB entry stored in a register of the plurality of registers associated therewith for determining whether a first match is present, wherein the first virtual address is received while the first thread is active and valid, and the previous first virtual address is received while the first thread is inactive or invalid, wherein the previous first virtual address is a first virtual address received by the first input a last time the first thread was active and valid; and a second comparator bank including a second plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration configured to output a second comparison result of the second plurality of comparators, wherein each of the second plurality of comparators is configured to compare one of the second virtual address and a previous second virtual address, based on an active state of the second thread, to a binary word corresponding to a TLB entry stored in a register of the plurality of registers associated therewith for determining whether a second match is present, wherein the second virtual address is received while the second thread is active and valid, and the previous second virtual address is received while the second thread is inactive or invalid, wherein the previous second virtual address is a second virtual address received by the second input a last time the second thread was active and valid. a first input configured to receive a first virtual address corresponding to a first thread; a second input configured to receive a second virtual address corresponding to a second thread; a register bank configured to store translation lookaside buffer, TLB, linear virtual address information including a plurality of registers, wherein each register is configured to store a binary word corresponding to a TLB entry mapped to one of a plurality of physical addresses; a first comparator bank including a first plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration configured to output a first comparison result of the first plurality of comparators, wherein each of the first plurality of comparators is configured to compare one of the first virtual address and a previous first virtual address, based on an active state of the first thread, to a binary word corresponding to a TLB entry stored in a register of the plurality of registers associated therewith for determining whether a first match is present, wherein the first virtual address is received while the first thread is active and valid, and the previous first virtual address is received while the first thread is inactive or invalid, wherein the previous first virtual address is a first virtual address received by the first input a last time the first thread was active and valid; and a second comparator bank including a second plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration configured to output a second comparison result of the second plurality of comparators, wherein each of the second plurality of comparators is configured to compare one of the second virtual address and a previous second virtual address, based on an active state of the second thread, to a binary word corresponding to a TLB entry stored in a register of the plurality of registers associated therewith for determining whether a second match is present, wherein the second virtual address is received while the second thread is active and valid, and the previous second virtual address is received while the second thread is inactive or invalid, wherein the previous second virtual address is a second virtual address received by the second input a last time the second thread was active and valid.