A semiconductor structure comprising: a memory-level assembly located over a semiconductor substrate and comprising at least one first alternating stack of electrically conductive layers (146, 246) and first portions of insulating layers (132, 232), and further comprising memory stack structures vertically extending through the at least one first alternating stack (132, 146, 232, 246); a plurality of laterally-elongated contact via structures that are located within respective trenches, vertically extend through the memory-level assembly, and laterally extend along a first horizontal direction, wherein a first subset of the plurality of laterally-elongated contact via structures laterally divides the at least one alternating stack (132, 246) into a plurality of laterally spaced-apart blocks (B1, B2, B3), wherein the plurality of blocks (B1, B2, B3) comprises a set of three neighboring blocks including, in order, a first block, a second block, and third block arranged along a second horizontal direction that is perpendicular to the first horizontal direction; at least one second alternating stack (132, 142', 232, 242') adjoining the second block and including alternating layers of spacer dielectric layers (142', 242') and second portions of the insulating layers (132, 232), and each of the spacer dielectric layers (142', 242') is located at a same level as a respective electrically conductive layer (146, 246); and at least one through-memory-level via structure comprising a conductive material and vertically extending through the at least one second alternating stack (132, 142', 232, 242'); characterised in that: the at least one second alternating stack (132, 142', 232, 242') comprises concave substantially vertical sidewalls of the spacer dielectric layers (142', 242'), which are vertical or deviate from a vertical line by less than 5 degrees; and the concave substantially vertical sidewalls of spacer dielectric layers (142', 242') are vertically coincident among one another and are substantially equidistant from a respective most proximal first trench of the trenches. a memory-level assembly located over a semiconductor substrate and comprising at least one first alternating stack of electrically conductive layers (146, 246) and first portions of insulating layers (132, 232), and further comprising memory stack structures vertically extending through the at least one first alternating stack (132, 146, 232, 246); a plurality of laterally-elongated contact via structures that are located within respective trenches, vertically extend through the memory-level assembly, and laterally extend along a first horizontal direction, wherein a first subset of the plurality of laterally-elongated contact via structures laterally divides the at least one alternating stack (132, 246) into a plurality of laterally spaced-apart blocks (B1, B2, B3), wherein the plurality of blocks (B1, B2, B3) comprises a set of three neighboring blocks including, in order, a first block, a second block, and third block arranged along a second horizontal direction that is perpendicular to the first horizontal direction; at least one second alternating stack (132, 142', 232, 242') adjoining the second block and including alternating layers of spacer dielectric layers (142', 242') and second portions of the insulating layers (132, 232), and each of the spacer dielectric layers (142', 242') is located at a same level as a respective electrically conductive layer (146, 246); and at least one through-memory-level via structure comprising a conductive material and vertically extending through the at least one second alternating stack (132, 142', 232, 242'); characterised in that: the at least one second alternating stack (132, 142', 232, 242') comprises concave substantially vertical sidewalls of the spacer dielectric layers (142', 242'), which are vertical or deviate from a vertical line by less than 5 degrees; and the concave substantially vertical sidewalls of spacer dielectric layers (142', 242') are vertically coincident among one another and are substantially equidistant from a respective most proximal first trench of the trenches. the at least one second alternating stack (132, 142', 232, 242') comprises concave substantially vertical sidewalls of the spacer dielectric layers (142', 242'), which are vertical or deviate from a vertical line by less than 5 degrees; and the concave substantially vertical sidewalls of spacer dielectric layers (142', 242') are vertically coincident among one another and are substantially equidistant from a respective most proximal first trench of the trenches.