A data caching system for an Ethernet device, wherein the data caching system comprises: an input package process device, IPC, configured to receive data frames from various Ethernet interfaces, and convert the data frames received from the Ethernet interfaces into data frames having a uniform bit width and a uniform encapsulation format; a package address management device, PMG, configured to maintain a cache address in which data has already been written and a currently idle cache address in a cache; a memory control device, MCT, configured to receive the currently idle cache address from the PMG, generate a write instruction for the cache, and perform a write operation to write the data received and processed by the IPC into a currently idle cache, wherein the write instruction is based on an internal write request of the system, receive the cache address from the PMG, generate a read instruction for the cache, and perform a read operation to read data from the cache, wherein the read instruction is based on an internal read request or is generated according to a read request received from the outside of the system; and an output package process device, OPC, configured to perform bit conversion and format encapsulation on the data that is read by the MCT based on the read request, and output the data subjected to the bit conversion and the format encapsulation through a corresponding Ethernet interface; the data caching system being characterized in that the PMG is further configured to maintain cache addresses according to a group data cache region and acquire an idle cache address through interleaving access, wherein after a first group of data cache regions are accessed, the other regions excluding the first group of data cache regions are accessed during a second access, and the first group of data cache regions are accessed again only when there is no idle cache address in the other regions excluding the first group of data cache regions; likewise, the other regions excluding a second group of data cache regions are accessed during a third access, and the second group of data cache regions are accessed again only when there is no idle cache address in the other regions excluding the second group of data cache regions; and if no idle cache address is found after each group of data cache regions are traversed, the current write operation is given up to discard data and not resumed unless there is an idle cache address available, and in that the group data cache region corresponds to a group of bank addresses of the cache, wherein a first bank is precharged after the first bank is accessed and before the first bank is accessed again. an input package process device, IPC, configured to receive data frames from various Ethernet interfaces, and convert the data frames received from the Ethernet interfaces into data frames having a uniform bit width and a uniform encapsulation format; a package address management device, PMG, configured to maintain a cache address in which data has already been written and a currently idle cache address in a cache; a memory control device, MCT, configured to receive the currently idle cache address from the PMG, generate a write instruction for the cache, and perform a write operation to write the data received and processed by the IPC into a currently idle cache, wherein the write instruction is based on an internal write request of the system, receive the cache address from the PMG, generate a read instruction for the cache, and perform a read operation to read data from the cache, wherein the read instruction is based on an internal read request or is generated according to a read request received from the outside of the system; and an output package process device, OPC, configured to perform bit conversion and format encapsulation on the data that is read by the MCT based on the read request, and output the data subjected to the bit conversion and the format encapsulation through a corresponding Ethernet interface;