Differential output stage (200; 300) of an amplification device, for driving a load (R LOAD, L LOAD), comprising: - a first differential output stage portion (201; 301) having a first differential input terminal (IN1, IN2) and a first differential output terminal, said first differential input terminal (IN1, IN2) comprising a first input terminal and a second input terminal; - a second differential output stage portion (202; 302) having a second differential input terminal (IN3, IN4) and a second differential output terminal, said second differential input terminal (IN3, IN4) comprising a third input terminal and a fourth input terminal, the load (R LOAD, L LOAD) being electrically connected between said first and second differential output terminal (O1, O2); the first differential output stage portion (201; 301) further comprising: - a first output circuit (M1PSW; M1PSW, M1PCASC) connected between a first reference potential and said first differential output terminal; - a second output circuit (M1NSW; M1NSW, M1NCASC) connected between a second reference potential and said first differential output terminal; - a first driving circuit (210; 310) of the first output circuit (M1PSW; M1PSW, M1PCASC) arranged to connect said first input terminal to a first driving terminal of said first output circuit (M1PSW; M1PSW, M1PCASC), said first driving circuit (210; 310) comprising a first biasing circuit (M2P, M3N, M4N, R11, I11) arranged to provide to the first driving terminal a first driving signal (DRIVEPSW); - a second driving circuit (220; 320) of the second output circuit (M1NSW; M1NSW, M1NCASC) arranged to connect said second input terminal to a second driving terminal of said second output circuit (M1NSW; M1NSW, M1NCASC), said second driving circuit (220; 320) comprising a second biasing circuit (141, R41, M4P, M3P, M2N) arranged to provide to the second driving terminal a second driving signal (DRIVENSW); characterized in that the first differential output stage portion (201; 301) further comprises: - a third output circuit (M2PSW; M2PSW, M2PCASC) connected between a first node of said first biasing circuit (M2P, M3N, M4N, R11, I11) and the first differential output terminal, said third output circuit (M2PSW; M2PSW, M2PCASC) having a third driving terminal connected to said first driving terminal, - a fourth output circuit (M2NSW; M2NSW, M2NCASC) connected between a first node of said second biasing circuit (141, R41, M4P, M3P, M2N) and the first differential output terminal, said fourth output circuit (M2NSW; M2NSW, M2NCASC) having a fourth driving terminal connected to said second driving terminal. - a first differential output stage portion (201; 301) having a first differential input terminal (IN1, IN2) and a first differential output terminal, said first differential input terminal (IN1, IN2) comprising a first input terminal and a second input terminal; - a second differential output stage portion (202; 302) having a second differential input terminal (IN3, IN4) and a second differential output terminal, said second differential input terminal (IN3, IN4) comprising a third input terminal and a fourth input terminal, the load (R LOAD, L LOAD) being electrically connected between said first and second differential output terminal (O1, O2); the first differential output stage portion (201; 301) further comprising: - a first output circuit (M1PSW; M1PSW, M1PCASC) connected between a first reference potential and said first differential output terminal; - a second output circuit (M1NSW; M1NSW, M1NCASC) connected between a second reference potential and said first differential output terminal; - a first driving circuit (210; 310) of the first output circuit (M1PSW; M1PSW, M1PCASC) arranged to connect said first input terminal to a first driving terminal of said first output circuit (M1PSW; M1PSW, M1PCASC), said first driving circuit (210; 310) comprising a first biasing circuit (M2P, M3N, M4N, R11, I11) arranged to provide to the first driving terminal a first driving signal (DRIVEPSW); - a second driving circuit (220; 320) of the second output circuit (M1NSW; M1NSW, M1NCASC) arranged to connect said second input terminal to a second driving terminal of said second output circuit (M1NSW; M1NSW, M1NCASC), said second driving circuit (220; 320) comprising a second biasing circuit (141, R41, M4P, M3P, M2N) arranged to provide to the second driving terminal a second driving signal (DRIVENSW); characterized in that the first differential output stage portion (201; 301) further comprises: - a third output circuit (M2PSW; M2PSW, M2PCASC) connected between a first node of said first biasing circuit (M2P, M3N, M4N, R11, I11) and the first differential output terminal, said third output circuit (M2PSW; M2PSW, M2PCASC) having a third driving terminal connected to said first driving terminal, - a fourth output circuit (M2NSW; M2NSW, M2NCASC) connected between a first node of said second biasing circuit (141, R41, M4P, M3P, M2N) and the first differential output terminal, said fourth output circuit (M2NSW; M2NSW, M2NCASC) having a fourth driving terminal connected to said second driving terminal.