A digital synthesizer, comprising: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter, TDC,, wherein the feedback loop is configured to feed back the DCO output signal; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto; wherein the TDC is configured to receive a representation of the DCO output signal and a reference frequency signal to sample the representation of the DCO output signal and output multiple selectable delayed versions of the representation of the DCO output signal, a digital synthesizer circuit sensor configured to sense an operational condition of the digital synthesizer circuit; characterized in that the digital synthesizer further comprises: a multiplexer configured to receive the multiple selectable delayed versions from the TDC and select one delayed version of the multiple selectable delayed versions output from the TDC in response to the sensed operational condition; and a re-timer circuit coupled to the digital synthesizer circuit sensor, configured to receive the representation of the DCO output signal and the selected one of the multiple selectable delayed versions output from multiplexer and further configured to resynchronize the representation of the DCO output signal with a clock edge of the reference frequency signal using the selected delayed version. a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter, TDC,, wherein the feedback loop is configured to feed back the DCO output signal; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto; wherein the TDC is configured to receive a representation of the DCO output signal and a reference frequency signal to sample the representation of the DCO output signal and output multiple selectable delayed versions of the representation of the DCO output signal, a digital synthesizer circuit sensor configured to sense an operational condition of the digital synthesizer circuit; characterized in that the digital synthesizer further comprises: a multiplexer configured to receive the multiple selectable delayed versions from the TDC and select one delayed version of the multiple selectable delayed versions output from the TDC in response to the sensed operational condition; and a re-timer circuit coupled to the digital synthesizer circuit sensor, configured to receive the representation of the DCO output signal and the selected one of the multiple selectable delayed versions output from multiplexer and further configured to resynchronize the representation of the DCO output signal with a clock edge of the reference frequency signal using the selected delayed version. a multiplexer configured to receive the multiple selectable delayed versions from the TDC and select one delayed version of the multiple selectable delayed versions output from the TDC in response to the sensed operational condition; and a re-timer circuit coupled to the digital synthesizer circuit sensor, configured to receive the representation of the DCO output signal and the selected one of the multiple selectable delayed versions output from multiplexer and further configured to resynchronize the representation of the DCO output signal with a clock edge of the reference frequency signal using the selected delayed version.