A data processing device comprising: an encoding unit that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 1/3, based on a parity check matrix of an LDPC code; and an interchanging unit that allocates code bits of the LDPC code to symbol bits of a symbol corresponding to any one of 16 signal points determined by 16QAM, wherein the LDPC code includes a plurality of information bits and a plurality of parity bits, wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, wherein the information matrix portion has dimension M x K and the parity matrix portion has dimension M x M, where M is a parity length and K is an information length, and K=5400 and M=10800; wherein the information matrix portion is represented by a parity check matrix initial value table which shows in a j-th row, where 1≤j ≤15, the positions of elements '1' in the (1+360x(j-1))-th column of the information matrix, and wherein based on each (1+360x(j-1))-th column, where 1 ≤ j ≤15, columns (2+360x(j-1)) through of the information matrix are determined by cyclically shifting the respective preceding column in a downward direction by M/360, and is configured as follows, 416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 6912 8978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 3575 3383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 2291 2797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 5420 6110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 4306 1505 5682 7778 7172 6830 6623 7281 3941 3505 10270 8669 914 3622 7563 9388 9930 5058 4554 4844 9609 2707 6883 3237 1714 4768 3878 10017 10127 3334 8267, and the parity matrix portion has a staircase structure in which elements of 1 are arranged in a staircase shape, where the row weight of the parity matrix portion is 1 with respect to the first row and 2 with respect to the remaining rows, and the column weight of the parity matrix portion is 1 with respect to the final column and 2 with respect to remaining columns; wherein 8 code bits that are stored in eight storage units each having a storage capacity of 16200/8 bits and are read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the interchanging unit sets the (#i + 1)-th code bit counted starting with the most significant bit of the 8 code bits as the bit b#i, 0≤ i ≤7, and the (#i + 1)-th symbol bit counted starting with the most significant bit of the 8 symbol bits of the two symbols as a bit y#i and allocates code bits b0, b1, b2, b3, b4, b5, b6, and b7 to symbol bits y6, y0, y3, y4, y5, y2, y1, and y7, respectively. an encoding unit that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 1/3, based on a parity check matrix of an LDPC code; and an interchanging unit that allocates code bits of the LDPC code to symbol bits of a symbol corresponding to any one of 16 signal points determined by 16QAM, 416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 6912 8978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 3575 3383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 2291 2797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 5420 6110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 4306 1505 5682 7778 7172 6830 6623 7281 3941 3505 10270 8669 914 3622 7563 9388 9930 5058 4554 4844 9609 2707 6883 3237 1714 4768 3878 10017 10127 3334 8267,