A processing device comprising: a vector register configured to store a data set including data elements of a vector operation; a vector processing unit configured to perform the vector operation, wherein the vector register is selectively connected as an input to the vector processing unit; and a swizzle pattern generator connected to the vector register and the vector processing unit and comprising: a swizzling network configured to combine or change the order of the data elements of the data set to simultaneously create a swizzle pattern when the data set is input to the vector register; and a swizzled register configured to store the swizzle pattern and selectively connected as an input to the vector processing unit, wherein the swizzling network includes: a plurality of data lines that are reconfigurable to create various swizzle patterns; a switch including reconfigurable connections for each of the plurality of data lines configured to generate the various swizzle patterns based on the reconfigurable connections; and a switching table connected to the switch configured to store various switch connections for the reconfigurable connections for the plurality of data lines, corresponding to the various swizzle patterns and characterized in that each data line of the plurality of data lines has an input end connected to an output of the vector processing unit and an output end connected to the swizzled register. a vector register configured to store a data set including data elements of a vector operation; a vector processing unit configured to perform the vector operation, wherein the vector register is selectively connected as an input to the vector processing unit; and a swizzle pattern generator connected to the vector register and the vector processing unit and comprising: a swizzling network configured to combine or change the order of the data elements of the data set to simultaneously create a swizzle pattern when the data set is input to the vector register; and a swizzled register configured to store the swizzle pattern and selectively connected as an input to the vector processing unit, a swizzling network configured to combine or change the order of the data elements of the data set to simultaneously create a swizzle pattern when the data set is input to the vector register; and a swizzled register configured to store the swizzle pattern and selectively connected as an input to the vector processing unit, wherein the swizzling network includes: a plurality of data lines that are reconfigurable to create various swizzle patterns; a switch including reconfigurable connections for each of the plurality of data lines configured to generate the various swizzle patterns based on the reconfigurable connections; and a switching table connected to the switch configured to store various switch connections for the reconfigurable connections for the plurality of data lines, corresponding to the various swizzle patterns and characterized in that each data line of the plurality of data lines has an input end connected to an output of the vector processing unit and an output end connected to the swizzled register. a plurality of data lines that are reconfigurable to create various swizzle patterns; a switch including reconfigurable connections for each of the plurality of data lines configured to generate the various swizzle patterns based on the reconfigurable connections; and a switching table connected to the switch configured to store various switch connections for the reconfigurable connections for the plurality of data lines, corresponding to the various swizzle patterns and characterized in that each data line of the plurality of data lines has an input end connected to an output of the vector processing unit and an output end connected to the swizzled register.