A digital unit cell comprising: a photodiode; an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode responsive to an input light signal incident on the photodiode over a first integration period and a second integration period; a comparator coupled to the integration capacitor and configured to compare a voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time a determination is made that the voltage across the integration capacitor is greater than the threshold voltage; a charge subtraction circuit coupled to the integration capacitor and to the comparator and configured to receive the control signal at the first level from the comparator and to discharge the accumulated charge on the integration capacitor each time the control signal at the first level is received from the comparator; at least two analog counters, the at least two analog counters comprising a first analog counter and a second analog counter, wherein, in the first integration period, the first analog counter is coupled to the comparator and is configured to receive the control signal at the first level from the comparator and to decrease a first count voltage by a fixed amount each time the control signal at the first level is received from the comparator; and wherein, in the second integration period, the second analog counter is coupled to the comparator and is configured to receive the control signal at the first level from the comparator and to decrease a second count voltage by a fixed amount each time the control signal at the first level is received from the comparator; a counter readout circuit coupled to the at least 2. two analog counters and configured, in the second integration period, to provide the first count voltage to an image processing circuit, a first counter selection switch configured to selectively couple the first analog counter to the counter readout circuit, and a second counter selection switch configured to selectively couple the count capacitor of the second analog counter to the counter readout circuit. a photodiode; an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode responsive to an input light signal incident on the photodiode over a first integration period and a second integration period; a comparator coupled to the integration capacitor and configured to compare a voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time a determination is made that the voltage across the integration capacitor is greater than the threshold voltage; a charge subtraction circuit coupled to the integration capacitor and to the comparator and configured to receive the control signal at the first level from the comparator and to discharge the accumulated charge on the integration capacitor each time the control signal at the first level is received from the comparator; at least two analog counters, the at least two analog counters comprising a first analog counter and a second analog counter, wherein, in the first integration period, the first analog counter is coupled to the comparator and is configured to receive the control signal at the first level from the comparator and to decrease a first count voltage by a fixed amount each time the control signal at the first level is received from the comparator; and wherein, in the second integration period, the second analog counter is coupled to the comparator and is configured to receive the control signal at the first level from the comparator and to decrease a second count voltage by a fixed amount each time the control signal at the first level is received from the comparator; wherein, in the first integration period, the first analog counter is coupled to the comparator and is configured to receive the control signal at the first level from the comparator and to decrease a first count voltage by a fixed amount each time the control signal at the first level is received from the comparator; and wherein, in the second integration period, the second analog counter is coupled to the comparator and is configured to receive the control signal at the first level from the comparator and to decrease a second count voltage by a fixed amount each time the control signal at the first level is received from the comparator; a counter readout circuit coupled to the at least 2. two analog counters and configured, in the second integration period, to provide the first count voltage to an image processing circuit, a first counter selection switch configured to selectively couple the first analog counter to the counter readout circuit, and a second counter selection switch configured to selectively couple the count capacitor of the second analog counter to the counter readout circuit.