A semiconductor storage device comprising: a plurality of memory cells arranged in a matrix; a word line connected to a memory cell row and formed in a first metal interconnection layer; a dummy word line formed in a second metal interconnection layer adjacent to the first metal interconnection layer, wherein said dummy word line is arranged in parallel with said word line; a word driver circuit including a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and a ground voltage lower than the power supply voltage, wherein the word driver circuit is configured to connect the power supply voltage to the word line in response to a row address signal and a control signal; and a dummy word driver circuit including a second PMOS transistor and a second NMOS transistor connected in series between the power supply voltage and the ground voltage, wherein the dummy word driver circuit is configured to connect the power supply voltage to the dummy word line in response to the row address signal and the control signal; an address decoder configured to receive the row address signal and output a decode signal; the semiconductor storage device characterized in that it further comprises: a first inverter configured to receive the control signal and output a signal obtained by inverting the control signal as a first signal; a second inverter configured to receive the first signal and output a signal obtained by inverting the first signal as a second signal; a third inverter configured to receive the decode signal and output a signal obtained by inverting the decode signal as a third signal; a first NAND circuit configured to receive the first signal and the decode signal; and a second NAND circuit configured to receive the second signal and the decode signal, wherein a gate of the first PMOS transistor is connected to an output terminal of the first NAND circuit, a gate of the first NMOS transistor is connected to an output terminal of the third inverter, and gates of the second PMOS transistor and the second NMOS transistor are connected to an output terminal of the second NAND circuit. a plurality of memory cells arranged in a matrix; a word line connected to a memory cell row and formed in a first metal interconnection layer; a dummy word line formed in a second metal interconnection layer adjacent to the first metal interconnection layer, wherein said dummy word line is arranged in parallel with said word line; a word driver circuit including a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and a ground voltage lower than the power supply voltage, wherein the word driver circuit is configured to connect the power supply voltage to the word line in response to a row address signal and a control signal; and a dummy word driver circuit including a second PMOS transistor and a second NMOS transistor connected in series between the power supply voltage and the ground voltage, wherein the dummy word driver circuit is configured to connect the power supply voltage to the dummy word line in response to the row address signal and the control signal; an address decoder configured to receive the row address signal and output a decode signal; the semiconductor storage device characterized in that it further comprises: a first inverter configured to receive the control signal and output a signal obtained by inverting the control signal as a first signal; a second inverter configured to receive the first signal and output a signal obtained by inverting the first signal as a second signal; a third inverter configured to receive the decode signal and output a signal obtained by inverting the decode signal as a third signal; a first NAND circuit configured to receive the first signal and the decode signal; and a second NAND circuit configured to receive the second signal and the decode signal, wherein a gate of the first PMOS transistor is connected to an output terminal of the first NAND circuit, a gate of the first NMOS transistor is connected to an output terminal of the third inverter, and gates of the second PMOS transistor and the second NMOS transistor are connected to an output terminal of the second NAND circuit.