A display device comprising: a panel, a plurality of gate lines and a plurality of data lines being arranged in the panel; a data driver configured to supply data voltages to the plurality of data lines arranged in the panel; and a gate driver including a plurality of stages sequentially driven according to a start signal, wherein the gate driver is configured to control an output of a scan signal from at least one of the plurality of stages according to an enable signal; characterized in that the gate driver further comprises a blocking unit, the blocking unit comprising: a first transistor connected to a pull-up transistor and a terminal receiving a clock which is supplied to at least one of the plurality of stages and is used as the scan signal, the first transistor including a gate connected to a gate of the pull-up transistor; a second transistor connected to the terminal receiving the clock and a gate of the first transistor and turned on or off by the clock; and a third transistor (T5i) connected to a low-level voltage source and the gate of the first transistor and turned on or off according to the enable signal, wherein when the pull-up transistor is in a turn-on state and the clock has a high voltage level and the enable signal is deactivated, the second transistor is turned off and the third transistor (T5i) is turned on for outputting of the scan signal to the gate line connected to the at least one of the plurality of stages according to the enable signal in a one frame period; and wherein when the pull-up transistor is in a turn-on state and the clock has a high voltage level and the enable signal is activated, the second transistor and the third transistor (T5i) are turned on for stopping an output of the scan signal to the gate line connected to the at least one of the plurality of stages according to the enable signal in a one frame period. a panel, a plurality of gate lines and a plurality of data lines being arranged in the panel; a data driver configured to supply data voltages to the plurality of data lines arranged in the panel; and a gate driver including a plurality of stages sequentially driven according to a start signal, wherein the gate driver is configured to control an output of a scan signal from at least one of the plurality of stages according to an enable signal; characterized in that the gate driver further comprises a blocking unit, the blocking unit comprising: a first transistor connected to a pull-up transistor and a terminal receiving a clock which is supplied to at least one of the plurality of stages and is used as the scan signal, the first transistor including a gate connected to a gate of the pull-up transistor; a second transistor connected to the terminal receiving the clock and a gate of the first transistor and turned on or off by the clock; and a third transistor (T5i) connected to a low-level voltage source and the gate of the first transistor and turned on or off according to the enable signal, wherein when the pull-up transistor is in a turn-on state and the clock has a high voltage level and the enable signal is deactivated, the second transistor is turned off and the third transistor (T5i) is turned on for outputting of the scan signal to the gate line connected to the at least one of the plurality of stages according to the enable signal in a one frame period; and wherein when the pull-up transistor is in a turn-on state and the clock has a high voltage level and the enable signal is activated, the second transistor and the third transistor (T5i) are turned on for stopping an output of the scan signal to the gate line connected to the at least one of the plurality of stages according to the enable signal in a one frame period. a first transistor connected to a pull-up transistor and a terminal receiving a clock which is supplied to at least one of the plurality of stages and is used as the scan signal, the first transistor including a gate connected to a gate of the pull-up transistor; a second transistor connected to the terminal receiving the clock and a gate of the first transistor and turned on or off by the clock; and a third transistor (T5i) connected to a low-level voltage source and the gate of the first transistor and turned on or off according to the enable signal, wherein when the pull-up transistor is in a turn-on state and the clock has a high voltage level and the enable signal is deactivated, the second transistor is turned off and the third transistor (T5i) is turned on for outputting of the scan signal to the gate line connected to the at least one of the plurality of stages according to the enable signal in a one frame period; and wherein when the pull-up transistor is in a turn-on state and the clock has a high voltage level and the enable signal is activated, the second transistor and the third transistor (T5i) are turned on for stopping an output of the scan signal to the gate line connected to the at least one of the plurality of stages according to the enable signal in a one frame period.