An apparatus, comprising: a switching circuit comprising a plurality of NMOS transistors (332, 334) connected in series between a first node and a second node to enable, responsive to a mode select signal, a current path between the first node and the second node in a first mode and disable the current path in a second mode, wherein the switching circuit includes a first transistor having a source and a drain electrically connected in the current path and a gate electrically connected to a control node, wherein the transistor is configured to enable the current path in response to a gate-source voltage exceeding the threshold voltage and disable the current path in response to the gate-source voltage being less than the threshold voltage; a biasing circuit configured to, in the second mode, prevent a voltage surge at the first node from enabling the current path to the second node by biasing a voltage of the control node of the switching circuit, wherein the biasing circuit is configured to reduce the voltage of the gate, in response to the first node having a voltage below an operating voltage range of the switching circuit, by an amount sufficient to prevent the gate-source voltage from exceeding the threshold voltage, wherein the biasing circuit includes an n-type transistor having a drain electrically connected to the control node, a source electrically connected to the first node, and a gate electrically connected to a ground voltage, and wherein the biasing circuit further includes: a first resistor having a first end connected to the drain of the n-type transistor and a second end connected to an output of the driver circuit; and a second resistor having a first end connected to the source of the n-type transistor and a second end connected to the first node; and a driver circuit configured to drive the control node, the driver circuit comprising a plurality of driver sub-circuits (312, 314), wherein each sub-driver circuit is configured to provide said mode select signal to a gate of a respective one of the transistors of the switching circuit. a switching circuit comprising a plurality of NMOS transistors (332, 334) connected in series between a first node and a second node to enable, responsive to a mode select signal, a current path between the first node and the second node in a first mode and disable the current path in a second mode, wherein the switching circuit includes a first transistor having a source and a drain electrically connected in the current path and a gate electrically connected to a control node, wherein the transistor is configured to enable the current path in response to a gate-source voltage exceeding the threshold voltage and disable the current path in response to the gate-source voltage being less than the threshold voltage; a biasing circuit configured to, in the second mode, prevent a voltage surge at the first node from enabling the current path to the second node by biasing a voltage of the control node of the switching circuit, wherein the biasing circuit is configured to reduce the voltage of the gate, in response to the first node having a voltage below an operating voltage range of the switching circuit, by an amount sufficient to prevent the gate-source voltage from exceeding the threshold voltage, wherein the biasing circuit includes an n-type transistor having a drain electrically connected to the control node, a source electrically connected to the first node, and a gate electrically connected to a ground voltage, and wherein the biasing circuit further includes: a first resistor having a first end connected to the drain of the n-type transistor and a second end connected to an output of the driver circuit; and a second resistor having a first end connected to the source of the n-type transistor and a second end connected to the first node; and a first resistor having a first end connected to the drain of the n-type transistor and a second end connected to an output of the driver circuit; and a second resistor having a first end connected to the source of the n-type transistor and a second end connected to the first node; and a driver circuit configured to drive the control node, the driver circuit comprising a plurality of driver sub-circuits (312, 314), wherein each sub-driver circuit is configured to provide said mode select signal to a gate of a respective one of the transistors of the switching circuit.