A shift register, comprising a charging unit, a pull-up unit, a pull-down circuit, a gate signal input terminal (INPUT), a DC low level signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a fourth clock signal input terminal and a gate signal output terminal (OUTPUT), wherein the charging unit is coupled to the gate signal input terminal (INPUT), the first clock signal input terminal, the pull-up unit and the pull-down circuit respectively so as to control a potential of a pull-up node to a high level in response to a first clock signal provided on the first clock signal input terminal during a charging phase; the pull-up unit is coupled to the charging unit, the pull-down circuit, the second clock signal input terminal and the gate signal output terminal (OUTPUT) respectively so as to output the high level signal input by the second clock signal input terminal to the gate signal output terminal (OUTPUT) under control of potentials on the pull-up node during an output phase; and the pull-down circuit is coupled to the charging unit, the pull-up unit, the DC low level signal input terminal, the third clock signal input terminal and the fourth clock signal input terminal respectively so as to control potentials of the pull-up node and the gate signal output terminal (OUTPUT) to a low level during a reset phase and a reset maintaining phase, the pull-down circuit comprises a first pull-down unit and a second pull-down unit, the first pull-down unit is coupled to the third clock signal input terminal and the DC low level signal input terminal respectively so as to control potentials of the pull-up node and the gate signal output terminal (OUTPUT) to the low level during the reset phase; and the second pull-down unit is coupled to the fourth clock signal input terminal and the DC low level signal input terminal respectively so as to control potentials of the pull-up node and the gate signal output terminal (OUTPUT) to the low level during the reset maintaining phase, the shift register further comprises a DC high level signal input terminal; characterized in that the first pull-down unit comprises a fourth thin film transistor, a fifth thin film transistor, an eighth thin film transistor and a tenth thin film transistor, wherein the source of the fourth thin film transistor is coupled to the charging unit, the pull-up unit and the gate of the tenth thin film transistor respectively via the pull-up node, the gate of the fourth thin film transistor is coupled to the drain of the eighth thin film transistor and the source of the tenth thin film transistor respectively, and the drain of the fourth thin film transistor is coupled to the DC low level signal input terminal; the source of the fifth thin film transistor is coupled to the pull-up unit and the gate signal output terminal (OUTPUT) respectively, the gate of the fifth thin film transistor is coupled to the drain of the eighth thin film transistor and the source of the tenth thin film transistor respectively, and the drain of the fifth thin film transistor is coupled to the DC low level signal input terminal; the source of the eighth thin film transistor is coupled to the DC high level signal input terminal, the gate of the eighth thin film transistor is coupled to the third clock signal input terminal, and the drain of the eighth thin film transistor is coupled to the gate of the fourth thin film transistor, the gate of the fifth thin film transistor and the source of the tenth thin film transistor respectively; and the drain of the tenth thin film transistor is coupled to the DC low level signal input terminal; and the second pull-down unit comprises a sixth thin film transistor, a seventh thin film transistor, a ninth thin film transistor and an eleventh thin film transistor, wherein the source of the sixth thin film transistor is coupled to the pull-up unit and the gate signal output terminal (OUTPUT) respectively, the gate of the sixth thin film transistor is coupled to the drain of the ninth thin film transistor and the source of the eleventh thin film transistor respectively, the drain of the sixth thin film transistor is coupled to the DC low level signal input terminal; the source of the seventh thin film transistor is coupled to the charging unit, the pull-up unit and the gate of the eleventh thin film transistor respectively via the pull-up node, the gate of the seventh thin film transistor is coupled to the drain of the ninth thin film transistor and the source of the eleventh thin film transistor respectively, the drain of the seventh thin film transistor is coupled to the DC low level signal input terminal; the source of the ninth thin film transistor is coupled to the DC high level signal input terminal, the gate of the ninth thin film transistor is coupled to the fourth clock signal input terminal, the drain of the ninth thin film transistor is coupled to the gate of the sixth thin film transistor, the gate of the seventh thin film transistor and the source of the eleventh thin film transistor respectively; and the drain of the eleventh thin film transistor is coupled to the DC low level signal input terminal.