A memory device comprising: a memory cell array comprising a plurality of memory cells connected to bit lines, each bit line extending in a first horizontal direction; and a page buffer circuit connected to the bit lines, wherein the page buffer circuit comprises: page buffer units comprising a first set of page buffer units (PBUO to PBU3) arranged in the first horizontal direction and a second set of page buffer units (PBU4 to PBU7) arranged in the first horizontal direction; and cache units arranged, in the first horizontal direction, between the first set of page buffer units (PBUO to PBU3) and the second set of page buffer units (PBU4 to PBU7), the cache units comprising first cache units (CUO to CU3) respectively corresponding to the first set of page buffer units (PBUO to PBU3) and second cache units (CU4 to CU7) respectively corresponding to the second set of page buffer units (PBU4 to PBU7), wherein each of the page buffer units comprises a sensing node and a pass transistor connected to the sensing node and configured to be selectively turned on during a data transmission period, the first cache units (CUO to CU3) share a first combined sensing node, and the first combined sensing node is connected to a pass transistor included in a first page buffer unit (PBUO) adjacent to the first cache units (CUO to CU3) from among the first set of page buffer units (PBUO to PBU3), the second cache units (CU4 to CU7) share a second combined sensing node (SOC1'), and the second combined sensing node (SOC1') is connected to a pass transistor included in a second page buffer unit adjacent to the second cache units (CU4 to CU7) from among the second set of page buffer units (PBU4 to PBU7), and, the sensing nodes respectively corresponding to the page buffer units are configured to, during the data transmission period, be electrically connected to one another through serial connections of pass transistors respectively included in the page buffer units. a memory cell array comprising a plurality of memory cells connected to bit lines, each bit line extending in a first horizontal direction; and a page buffer circuit connected to the bit lines, wherein the page buffer circuit comprises: page buffer units comprising a first set of page buffer units (PBUO to PBU3) arranged in the first horizontal direction and a second set of page buffer units (PBU4 to PBU7) arranged in the first horizontal direction; and cache units arranged, in the first horizontal direction, between the first set of page buffer units (PBUO to PBU3) and the second set of page buffer units (PBU4 to PBU7), the cache units comprising first cache units (CUO to CU3) respectively corresponding to the first set of page buffer units (PBUO to PBU3) and second cache units (CU4 to CU7) respectively corresponding to the second set of page buffer units (PBU4 to PBU7), wherein each of the page buffer units comprises a sensing node and a pass transistor connected to the sensing node and configured to be selectively turned on during a data transmission period, the first cache units (CUO to CU3) share a first combined sensing node, and the first combined sensing node is connected to a pass transistor included in a first page buffer unit (PBUO) adjacent to the first cache units (CUO to CU3) from among the first set of page buffer units (PBUO to PBU3), the second cache units (CU4 to CU7) share a second combined sensing node (SOC1'), and the second combined sensing node (SOC1') is connected to a pass transistor included in a second page buffer unit adjacent to the second cache units (CU4 to CU7) from among the second set of page buffer units (PBU4 to PBU7), and, the sensing nodes respectively corresponding to the page buffer units are configured to, during the data transmission period, be electrically connected to one another through serial connections of pass transistors respectively included in the page buffer units. page buffer units comprising a first set of page buffer units (PBUO to PBU3) arranged in the first horizontal direction and a second set of page buffer units (PBU4 to PBU7) arranged in the first horizontal direction; and cache units arranged, in the first horizontal direction, between the first set of page buffer units (PBUO to PBU3) and the second set of page buffer units (PBU4 to PBU7), the cache units comprising first cache units (CUO to CU3) respectively corresponding to the first set of page buffer units (PBUO to PBU3) and second cache units (CU4 to CU7) respectively corresponding to the second set of page buffer units (PBU4 to PBU7), wherein each of the page buffer units comprises a sensing node and a pass transistor connected to the sensing node and configured to be selectively turned on during a data transmission period, the first cache units (CUO to CU3) share a first combined sensing node, and the first combined sensing node is connected to a pass transistor included in a first page buffer unit (PBUO) adjacent to the first cache units (CUO to CU3) from among the first set of page buffer units (PBUO to PBU3), the second cache units (CU4 to CU7) share a second combined sensing node (SOC1'), and the second combined sensing node (SOC1') is connected to a pass transistor included in a second page buffer unit adjacent to the second cache units (CU4 to CU7) from among the second set of page buffer units (PBU4 to PBU7), and, the sensing nodes respectively corresponding to the page buffer units are configured to, during the data transmission period, be electrically connected to one another through serial connections of pass transistors respectively included in the page buffer units.