A phase-locked loop, comprising: a voltage-controlled oscillator having: a control input; and a clock output; and a phase frequency detector having: a reference clock input (CK ref); a feedback clock input(CK fb); an up output configured to be either in a set state or a reset state; and a down output configured to be either in a set state or a reset state, the up output and the down output of the phase frequency detector being operably connected to the control input of the voltage-controlled oscillator, the clock output of the voltage-controlled oscillator being operably connected to the feedback clock input of the phase frequency detector, the phase frequency detector comprising an adjustable delay block configured to adjust an output frequency of the phase-locked loop by delaying, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state; and a delay controller, having an output operably connected to a control input of the adjustable delay block, wherein the delay controller has a first input operably connected to the reference clock input, and a second input operably connected to the feedback clock input, characterized in that the delay controller is configured to count edges of respective signals at the reference clock input and at the feedback clock input and adjust a variable delay line in the phase frequency detector based on the edge count. a voltage-controlled oscillator having: a control input; and a clock output; and a control input; and a clock output; and a phase frequency detector having: a reference clock input (CK ref); a feedback clock input(CK fb); an up output configured to be either in a set state or a reset state; and a down output configured to be either in a set state or a reset state, a reference clock input (CK ref); a feedback clock input(CK fb); an up output configured to be either in a set state or a reset state; and a down output configured to be either in a set state or a reset state, the up output and the down output of the phase frequency detector being operably connected to the control input of the voltage-controlled oscillator, the clock output of the voltage-controlled oscillator being operably connected to the feedback clock input of the phase frequency detector, the phase frequency detector comprising an adjustable delay block configured to adjust an output frequency of the phase-locked loop by delaying, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state; and a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state; and a delay controller, having an output operably connected to a control input of the adjustable delay block, wherein the delay controller has a first input operably connected to the reference clock input, and a second input operably connected to the feedback clock input, characterized in that the delay controller is configured to count edges of respective signals at the reference clock input and at the feedback clock input and adjust a variable delay line in the phase frequency detector based on the edge count.