An apparatus, comprising: a NAND string (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n) comprising a drain-end select gate transistor (717, 737, 757, 777) at a drain-end of the NAND string, a selected data memory cell (704, 724, 744, 764), unselected data memory cells (705-714, 725-734, 745-754, 765-774), and a first dummy memory cell (716, 736, 756, 776) adjacent to the drain-end select gate transistor, wherein each memory cell is connected to a respective word line; a bit line connected (BL0-BL3) to the drain-end; and a control circuit (110, 122, 132) configured to, in a program loop for the selected data memory cell: perform a pre-charge phase in which the bit line has a positive voltage and the drain-end select gate transistor is in a conductive state; the apparatus characterised by the control circuit being configured to: after the pre-charge phase, perform a program phase in which, before a program pulse is applied to the word line of the selected data memory cell, a start of a ramp up of a voltage (1560c, 1560d, 1570c, 1570g) applied to the word line of the first dummy memory cell is after a start of a ramp up of a voltage applied to the word lines of the unselected data memory cells when a position of the selected data memory cell in the NAND string is among a subset of memory cells adjacent to a source-end of the NAND string. a NAND string (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n) comprising a drain-end select gate transistor (717, 737, 757, 777) at a drain-end of the NAND string, a selected data memory cell (704, 724, 744, 764), unselected data memory cells (705-714, 725-734, 745-754, 765-774), and a first dummy memory cell (716, 736, 756, 776) adjacent to the drain-end select gate transistor, wherein each memory cell is connected to a respective word line; a bit line connected (BL0-BL3) to the drain-end; and a control circuit (110, 122, 132) configured to, in a program loop for the selected data memory cell: perform a pre-charge phase in which the bit line has a positive voltage and the drain-end select gate transistor is in a conductive state; the apparatus characterised by the control circuit being configured to: after the pre-charge phase, perform a program phase in which, before a program pulse is applied to the word line of the selected data memory cell, a start of a ramp up of a voltage (1560c, 1560d, 1570c, 1570g) applied to the word line of the first dummy memory cell is after a start of a ramp up of a voltage applied to the word lines of the unselected data memory cells when a position of the selected data memory cell in the NAND string is among a subset of memory cells adjacent to a source-end of the NAND string. perform a pre-charge phase in which the bit line has a positive voltage and the drain-end select gate transistor is in a conductive state; the apparatus characterised by the control circuit being configured to: after the pre-charge phase, perform a program phase in which, before a program pulse is applied to the word line of the selected data memory cell, a start of a ramp up of a voltage (1560c, 1560d, 1570c, 1570g) applied to the word line of the first dummy memory cell is after a start of a ramp up of a voltage applied to the word lines of the unselected data memory cells when a position of the selected data memory cell in the NAND string is among a subset of memory cells adjacent to a source-end of the NAND string.