A wafer-level chip-size package, comprising: a semiconductor structure; a bonding pad formed over the semiconductor structure, comprising two conductive segments; a conductive component formed over the semiconductor structure, being adjacent to the bonding pad; a passivation layer formed over the semiconductor structure, the first bonding pad and the conductive component, wherein openings in the passivation layer expose portions of the conductive segments of the first bonding pad; a conductive redistribution layer formed over the passivation layer and the portion of the conductive segments of the first bonding pad exposed by the openings in the passivation layer; a planarization layer formed over the passivation layer and the conductive redistribution layer, wherein an opening in the planarization layer exposes a portion of the conductive redistribution layer; an under-bump-metallurgy layer formed over the planarization layer and the portion of the conductive redistribution layer exposed by the opening in the planarization layer; and a conductive bump formed over the UBM layer; characterised in that the conductive component has a strip-like configuration from a top view and the conductive segments have a maximum size that is less than a maximum size of the conductive component, wherein the conductive component and the conductive segments comprise the same conductive materials; wherein the conductive component is isolated from each of the conductive segments by a trench formed therebetween, and wherein the passivation layer fills each of the trenches; wherein the conductive component is disposed between the two conductive segments of the bonding pad and is adjacent to the two conductive segments of the bonding pad; and wherein the UBM layer is formed over the portion of the conductive redistribution layer at a place that is not over the portions of the conductive segments of the bonding pad exposed by the openings in the passivation layer. a semiconductor structure; a bonding pad formed over the semiconductor structure, comprising two conductive segments; a conductive component formed over the semiconductor structure, being adjacent to the bonding pad; a passivation layer formed over the semiconductor structure, the first bonding pad and the conductive component, wherein openings in the passivation layer expose portions of the conductive segments of the first bonding pad; a conductive redistribution layer formed over the passivation layer and the portion of the conductive segments of the first bonding pad exposed by the openings in the passivation layer; a planarization layer formed over the passivation layer and the conductive redistribution layer, wherein an opening in the planarization layer exposes a portion of the conductive redistribution layer; an under-bump-metallurgy layer formed over the planarization layer and the portion of the conductive redistribution layer exposed by the opening in the planarization layer; and a conductive bump formed over the UBM layer; characterised in that the conductive component has a strip-like configuration from a top view and the conductive segments have a maximum size that is less than a maximum size of the conductive component, wherein the conductive component and the conductive segments comprise the same conductive materials; wherein the conductive component is isolated from each of the conductive segments by a trench formed therebetween, and wherein the passivation layer fills each of the trenches; wherein the conductive component is disposed between the two conductive segments of the bonding pad and is adjacent to the two conductive segments of the bonding pad; and wherein the UBM layer is formed over the portion of the conductive redistribution layer at a place that is not over the portions of the conductive segments of the bonding pad exposed by the openings in the passivation layer.