A computer-aided method for configuring a hardware verification system comprising a plurality of programmable devices, the method comprising: receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system; and transforming, using the computer, the first data into a second data representative of a second design that includes: the functionality of the first design; and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design; configuring the plurality of programmable devices of the hardware verification system with the second data; and running the second data, wherein the first circuit comprises: a program instruction memory; a program control and decoder decoding instructions; a weight X toggle count computing the power consumption of the first portion of the first design, wherein the first portion is selected in accordance with instructions received from the program control and decoder, wherein the weight X toggle count computes the power in accordance with a plurality of toggle counts of sequential logic elements disposed in the first portion of the first design as well as a plurality of coefficients defined by fanouts of these sequential logic elements. receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system; and transforming, using the computer, the first data into a second data representative of a second design that includes: the functionality of the first design; and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design; the functionality of the first design; and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design; configuring the plurality of programmable devices of the hardware verification system with the second data; and running the second data, wherein the first circuit comprises: a program instruction memory; a program control and decoder decoding instructions; a weight X toggle count computing the power consumption of the first portion of the first design, wherein the first portion is selected in accordance with instructions received from the program control and decoder, wherein the weight X toggle count computes the power in accordance with a plurality of toggle counts of sequential logic elements disposed in the first portion of the first design as well as a plurality of coefficients defined by fanouts of these sequential logic elements. a program instruction memory; a program control and decoder decoding instructions; a weight X toggle count computing the power consumption of the first portion of the first design, wherein the first portion is selected in accordance with instructions received from the program control and decoder, wherein the weight X toggle count computes the power in accordance with a plurality of toggle counts of sequential logic elements disposed in the first portion of the first design as well as a plurality of coefficients defined by fanouts of these sequential logic elements.