A semiconductor storage device (1, 3) comprising: a plurality of unit memory arrays (10_0: 10_m) each including a first and second memory blocks (BLK_0, BLK_1: BLK_2n, BLK_2n+1) each including a plurality of electrically erasable/writable nonvolatile memory cells (MC_0, MC_1: MC_2n, MC_2n+1), a sense amplifier block (12_0: 12_m) including a sense amplifier (HSA_0: HSA_m) for reading data stored in each memory cell and a verify circuit (VF_0: VF_m) for verifying data stored in each memory cell; and a verify control circuit (28, for controlling verify processing in each verify circuit, wherein the verify control circuit is configured to apply a pulse corresponding to verify data to each memory cell of the first and the second memory blocks, and to set an expectation value (vctrl) corresponding to the verify data to each verify circuit, wherein each verify circuit is configured to perform the verify processing by comparing the data stored in the memory cell and read by the sense amplifier (out_0: out_m) with the expectation value (vctrl), the semiconductor storage device being characterised in that the sense amplifier and the verify circuit are disposed between the first memory block and the second memory block; the verify circuits are sequentially coupled to each other, each verify circuit except for the last one (VF_m) is configured to transmit a result signal of the verify processing to the next one, and the last one (VF_m) is configured to transmit an output signal (vrslt_m) of the verify processing to the verify control circuit; and each verify circuit includes: a first logic circuit (XNOR_0: XNOR_m) which is configured to compare the data stored in the memory cell and read by the sense amplifier (out_0: out_m) with the expectationvalue (vctrl), and to output a comparison result as the result of the verify processing; and a second logic circuit (AND_0: AND_m) which is configured to input an output of the first logic circuit and the result of the verify processing in a preceding stage, and to output a signal indicating normality when the output of the first logic circuit and the result of the verify processing in the preceding stage are both normal. a plurality of unit memory arrays (10_0: 10_m) each including a first and second memory blocks (BLK_0, BLK_1: BLK_2n, BLK_2n+1) each including a plurality of electrically erasable/writable nonvolatile memory cells (MC_0, MC_1: MC_2n, MC_2n+1), a sense amplifier block (12_0: 12_m) including a sense amplifier (HSA_0: HSA_m) for reading data stored in each memory cell and a verify circuit (VF_0: VF_m) for verifying data stored in each memory cell; and a verify control circuit (28, for controlling verify processing in each verify circuit, wherein the verify control circuit is configured to apply a pulse corresponding to verify data to each memory cell of the first and the second memory blocks, and to set an expectation value (vctrl) corresponding to the verify data to each verify circuit, wherein each verify circuit is configured to perform the verify processing by comparing the data stored in the memory cell and read by the sense amplifier (out_0: out_m) with the expectation value (vctrl), the semiconductor storage device being characterised in that the sense amplifier and the verify circuit are disposed between the first memory block and the second memory block; the verify circuits are sequentially coupled to each other, each verify circuit except for the last one (VF_m) is configured to transmit a result signal of the verify processing to the next one, and the last one (VF_m) is configured to transmit an output signal (vrslt_m) of the verify processing to the verify control circuit; and each verify circuit includes: a first logic circuit (XNOR_0: XNOR_m) which is configured to compare the data stored in the memory cell and read by the sense amplifier (out_0: out_m) with the expectationvalue (vctrl), and to output a comparison result as the result of the verify processing; and a second logic circuit (AND_0: AND_m) which is configured to input an output of the first logic circuit and the result of the verify processing in a preceding stage, and to output a signal indicating normality when the output of the first logic circuit and the result of the verify processing in the preceding stage are both normal. a first logic circuit (XNOR_0: XNOR_m) which is configured to compare the data stored in the memory cell and read by the sense amplifier (out_0: out_m) with the expectationvalue (vctrl), and to output a comparison result as the result of the verify processing; and a second logic circuit (AND_0: AND_m) which is configured to input an output of the first logic circuit and the result of the verify processing in a preceding stage, and to output a signal indicating normality when the output of the first logic circuit and the result of the verify processing in the preceding stage are both normal.