A vector-by-matrix multiplication system, comprising: an array (3301a, 3301b, 3301c, 3301d, 3301e, 3301f, 3301g, 3301h) of non-volatile memory cells arranged into rows and columns; an input block (3303a, 3303b, 3303c, 3303d, 3303e, 3303f, 3303g, 3303h) coupled to the array to receive one or more input pulses, convert the one or more input pulses into an analog voltage, and apply the analog voltage to a word line or a control gate line coupled to a row of non-volatile memory cells in the array during a vector matrix multiplier operation; and an output block (3302a, 3302b, 3302c, 3302d, 3302e, 3302f, 3302g, 3302h) coupled to the array to generate a digital pulse of varying width in response to a neuron current drawn by the array during the vector matrix multiplier operation, wherein a width of the digital pulse varies in proportion to the neuron current; the output block comprising: a first operational amplifier comprising an inverting input terminal, a non-inverting input terminal, and an output terminal; a reference current source to generate a reference current at an output thereof; a first switch to selectively couple the output of the reference current source to the inverting input terminal of the first operational amplifier; a second switch to selectively couple the neuron current to the inverting input terminal of the first operational amplifier; a capacitor coupled between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; a third switch to selectively couple the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; and a second operational amplifier comprising a non-inverting input terminal coupled to the output of the first operational amplifier, an inverting input terminal, and an output terminal to generate a digital pulse in response to the neuron current. an array (3301a, 3301b, 3301c, 3301d, 3301e, 3301f, 3301g, 3301h) of non-volatile memory cells arranged into rows and columns; an input block (3303a, 3303b, 3303c, 3303d, 3303e, 3303f, 3303g, 3303h) coupled to the array to receive one or more input pulses, convert the one or more input pulses into an analog voltage, and apply the analog voltage to a word line or a control gate line coupled to a row of non-volatile memory cells in the array during a vector matrix multiplier operation; and an output block (3302a, 3302b, 3302c, 3302d, 3302e, 3302f, 3302g, 3302h) coupled to the array to generate a digital pulse of varying width in response to a neuron current drawn by the array during the vector matrix multiplier operation, wherein a width of the digital pulse varies in proportion to the neuron current; the output block comprising: a first operational amplifier comprising an inverting input terminal, a non-inverting input terminal, and an output terminal; a reference current source to generate a reference current at an output thereof; a first switch to selectively couple the output of the reference current source to the inverting input terminal of the first operational amplifier; a second switch to selectively couple the neuron current to the inverting input terminal of the first operational amplifier; a capacitor coupled between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; a third switch to selectively couple the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; and a second operational amplifier comprising a non-inverting input terminal coupled to the output of the first operational amplifier, an inverting input terminal, and an output terminal to generate a digital pulse in response to the neuron current. a first operational amplifier comprising an inverting input terminal, a non-inverting input terminal, and an output terminal; a reference current source to generate a reference current at an output thereof; a first switch to selectively couple the output of the reference current source to the inverting input terminal of the first operational amplifier; a second switch to selectively couple the neuron current to the inverting input terminal of the first operational amplifier; a capacitor coupled between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; a third switch to selectively couple the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; and a second operational amplifier comprising a non-inverting input terminal coupled to the output of the first operational amplifier, an inverting input terminal, and an output terminal to generate a digital pulse in response to the neuron current.