A clock signal generator comprising: an input pin for receiving an oscillating signal; an output pin for providing an output clock signal; a frequency divider connected between the input pin and the output pin, the frequency divider having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the output clock signal; a counter configured to count the number of pulses in the output clock signal and/or in the received oscillating signal; a shift register configured to store a component of the plurality of frequency division factors and provide the component of a frequency division factor at an output of the shift register; a divider configured to divide the component of a frequency division factor that is output by the shift register in accordance with a jitter range input signal in order to provide a variable component of a frequency division factor; and a controller configured to: replace the in-use frequency division factor with another of the plurality of frequency division factors when a count of the counter reaches a predetermined value; and shift the components of the plurality of frequency division factors through the shift register, such that a next component of the plurality of frequency division factors stored in the shift register contributes to the in-use frequency division factor for the frequency divider when replacing the in-use frequency division factor. an input pin for receiving an oscillating signal; an output pin for providing an output clock signal; a frequency divider connected between the input pin and the output pin, the frequency divider having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the output clock signal; a counter configured to count the number of pulses in the output clock signal and/or in the received oscillating signal; a shift register configured to store a component of the plurality of frequency division factors and provide the component of a frequency division factor at an output of the shift register; a divider configured to divide the component of a frequency division factor that is output by the shift register in accordance with a jitter range input signal in order to provide a variable component of a frequency division factor; and a controller configured to: replace the in-use frequency division factor with another of the plurality of frequency division factors when a count of the counter reaches a predetermined value; and shift the components of the plurality of frequency division factors through the shift register, such that a next component of the plurality of frequency division factors stored in the shift register contributes to the in-use frequency division factor for the frequency divider when replacing the in-use frequency division factor. replace the in-use frequency division factor with another of the plurality of frequency division factors when a count of the counter reaches a predetermined value; and shift the components of the plurality of frequency division factors through the shift register, such that a next component of the plurality of frequency division factors stored in the shift register contributes to the in-use frequency division factor for the frequency divider when replacing the in-use frequency division factor.