An apparatus comprising: a synchronous rectification circuit coupled to a synchronous rectifier and configured to generate a synchronous rectification signal to control synchronous rectification of said synchronous rectifier, wherein during a period (t2-t3) of synchronous rectification, a gate voltage of said synchronous rectifier decreases gradually; and a light load control circuit (62, 102) coupled to said synchronous rectifier, said light load control circuit (62, 102) receiving the gate voltage to said synchronous rectifier, and said light load control circuit (62, 102) selectively latching off synchronous rectification of said synchronous rectifier into non-synchronous rectification based upon at least said gate voltage; wherein the light load control circuit (62, 102) comprises: a gate voltage comparator comparing the gate voltage (VG, PGND) with a first reference voltage (VREF); a latching circuit (621, 700, 1021, 1100) connected to an output terminal of said gate voltage comparator, the latching circuit (621, 700, 1021, 1100) outputting a light load control signal to selectively latch off synchronous rectification into non-synchronous rectification, the latching circuit (621, 700, 1021, 1100) comprising a light load logic circuit (71, 110) coupled to said comparator and generating a load indication signal (VLLG); and a blanking time circuit (622, 1022) outputting a blanking time signal (VBLANK, VBLANK1), wherein said load indication signal (VLLG) presents a pulse if the gate voltage is higher than said first reference signal (VREF, VREF1) at a falling edge of said blanking time signal (VBLANK, VBLANK1), or said load indication signal (VLLG) presents logic LOW if the gate voltage is lower than said first reference voltage (VREF, VREF1) at the falling edge of said blanking time signal (VBLANK, VBLANK1); wherein during synchronous rectification operation of said rectifier, if said load indication signal (VLLG) is a pattern for a predetermined time, latching off synchronous rectification into non-synchronous rectification of said rectifier. a synchronous rectification circuit coupled to a synchronous rectifier and configured to generate a synchronous rectification signal to control synchronous rectification of said synchronous rectifier, wherein during a period (t2-t3) of synchronous rectification, a gate voltage of said synchronous rectifier decreases gradually; and a light load control circuit (62, 102) coupled to said synchronous rectifier, said light load control circuit (62, 102) receiving the gate voltage to said synchronous rectifier, and said light load control circuit (62, 102) selectively latching off synchronous rectification of said synchronous rectifier into non-synchronous rectification based upon at least said gate voltage; wherein the light load control circuit (62, 102) comprises: a gate voltage comparator comparing the gate voltage (VG, PGND) with a first reference voltage (VREF); a latching circuit (621, 700, 1021, 1100) connected to an output terminal of said gate voltage comparator, the latching circuit (621, 700, 1021, 1100) outputting a light load control signal to selectively latch off synchronous rectification into non-synchronous rectification, the latching circuit (621, 700, 1021, 1100) comprising a light load logic circuit (71, 110) coupled to said comparator and generating a load indication signal (VLLG); and a blanking time circuit (622, 1022) outputting a blanking time signal (VBLANK, VBLANK1), wherein a gate voltage comparator comparing the gate voltage (VG, PGND) with a first reference voltage (VREF); a latching circuit (621, 700, 1021, 1100) connected to an output terminal of said gate voltage comparator, the latching circuit (621, 700, 1021, 1100) outputting a light load control signal to selectively latch off synchronous rectification into non-synchronous rectification, the latching circuit (621, 700, 1021, 1100) comprising a light load logic circuit (71, 110) coupled to said comparator and generating a load indication signal (VLLG); and a blanking time circuit (622, 1022) outputting a blanking time signal (VBLANK, VBLANK1), wherein said load indication signal (VLLG) presents a pulse if the gate voltage is higher than said first reference signal (VREF, VREF1) at a falling edge of said blanking time signal (VBLANK, VBLANK1), or said load indication signal (VLLG) presents logic LOW if the gate voltage is lower than said first reference voltage (VREF, VREF1) at the falling edge of said blanking time signal (VBLANK, VBLANK1); wherein during synchronous rectification operation of said rectifier, if said load indication signal (VLLG) is a pattern for a predetermined time, latching off synchronous rectification into non-synchronous rectification of said rectifier.