A column buffer for use with at least one pixel cell, the column buffer comprising: an amplifier coupled to an output of the pixel cell; a signal read-out circuit comprising: a first transistor coupled to an output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; a reset read-out circuit comprising: a first transistor coupled to the output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; and a pedestal read-out circuit comprising: a first transistor coupled to the output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; wherein each of the first transistors (601 611, 621) is controlled to sample the output of the amplifier at a different time during a row select clock cycle and all the second transistors are controlled to simultaneously output the read-out signals. an amplifier coupled to an output of the pixel cell; a signal read-out circuit comprising: a first transistor coupled to an output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; a first transistor coupled to an output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; a reset read-out circuit comprising: a first transistor coupled to the output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; and a first transistor coupled to the output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; and a pedestal read-out circuit comprising: a first transistor coupled to the output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier; wherein each of the first transistors (601 611, 621) is controlled to sample the output of the amplifier at a different time during a row select clock cycle and all the second transistors are controlled to simultaneously output the read-out signals. a first transistor coupled to the output of the amplifier; a driver amplifier coupled to the first transistor; a capacitor having a first node coupled between the first transistor and the driver amplifier and a second node coupled to ground; and a second transistor coupled to an output of the driver amplifier;