An analog to digital converter, comprising: an input circuit for receiving an analog signal; a computation circuit coupled to the input circuit, and an output circuit coupled to the computation circuit and providing a digital signal; wherein the computation circuit includes an amplifier and initialization circuit, wherein the amplifier and initialization circuit comprises: an amplifier having a pair of inputs (Imp, Imn), a pair of complementary outputs (Outp, Outn), a terminal for receiving a power supply voltage, an initialization circuit (333, 335, 337), a common mode feedback circuit, and a clock generation circuit configured to produce a Reset signal and a clock signal; wherein during a startup initialization mode, the clock generation circuit is configured to assert the Reset signal, and in a conversion mode, after the startup initialization mode, the clock generation circuit is configured to assert a conversion signal, deassert the Reset signal and initiate a series of pulses on the clock signal; wherein the pair of complementary outputs and the clock signal are coupled to inputs of the common mode feedback circuit, wherein the common mode feedback circuit has an output for providing a feedback signal (CMFB) to a signal line for controlling the common mode voltage of the amplifier during the conversion mode, wherein in the conversion mode, a switched capacitor circuit, located in the common mode feedback circuit, whose switches open and close with the clock pulses, is configured to generate the feedback signal, and during the startup initialization mode the common mode feedback circuit is configured not to drive the signal line; wherein during the startup initialization mode the initialization circuit is configured to connect the pair of complementary outputs together and to the signal line and the pair of complementary outputs is configured to drive the signal line such that the voltage on the signal line equals a known first voltage less than the power supply voltage. an input circuit for receiving an analog signal; a computation circuit coupled to the input circuit, and an output circuit coupled to the computation circuit and providing a digital signal; wherein the computation circuit includes an amplifier and initialization circuit, wherein the amplifier and initialization circuit comprises: an amplifier having a pair of inputs (Imp, Imn), a pair of complementary outputs (Outp, Outn), a terminal for receiving a power supply voltage, an initialization circuit (333, 335, 337), a common mode feedback circuit, and a clock generation circuit configured to produce a Reset signal and a clock signal; wherein during a startup initialization mode, the clock generation circuit is configured to assert the Reset signal, and in a conversion mode, after the startup initialization mode, the clock generation circuit is configured to assert a conversion signal, deassert the Reset signal and initiate a series of pulses on the clock signal; wherein the pair of complementary outputs and the clock signal are coupled to inputs of the common mode feedback circuit, wherein the common mode feedback circuit has an output for providing a feedback signal (CMFB) to a signal line for controlling the common mode voltage of the amplifier during the conversion mode, wherein in the conversion mode, a switched capacitor circuit, located in the common mode feedback circuit, whose switches open and close with the clock pulses, is configured to generate the feedback signal, and during the startup initialization mode the common mode feedback circuit is configured not to drive the signal line; wherein during the startup initialization mode the initialization circuit is configured to connect the pair of complementary outputs together and to the signal line and the pair of complementary outputs is configured to drive the signal line such that the voltage on the signal line equals a known first voltage less than the power supply voltage. an amplifier having a pair of inputs (Imp, Imn), a pair of complementary outputs (Outp, Outn), a terminal for receiving a power supply voltage, an initialization circuit (333, 335, 337), a common mode feedback circuit, and a clock generation circuit configured to produce a Reset signal and a clock signal; wherein during a startup initialization mode, the clock generation circuit is configured to assert the Reset signal, and in a conversion mode, after the startup initialization mode, the clock generation circuit is configured to assert a conversion signal, deassert the Reset signal and initiate a series of pulses on the clock signal; wherein the pair of complementary outputs and the clock signal are coupled to inputs of the common mode feedback circuit, wherein the common mode feedback circuit has an output for providing a feedback signal (CMFB) to a signal line for controlling the common mode voltage of the amplifier during the conversion mode, wherein in the conversion mode, a switched capacitor circuit, located in the common mode feedback circuit, whose switches open and close with the clock pulses, is configured to generate the feedback signal, and during the startup initialization mode the common mode feedback circuit is configured not to drive the signal line; wherein during the startup initialization mode the initialization circuit is configured to connect the pair of complementary outputs together and to the signal line and the pair of complementary outputs is configured to drive the signal line such that the voltage on the signal line equals a known first voltage less than the power supply voltage.