A system comprising: a plurality of block-based processor cores, wherein a processor core includes one or more instruction windows, each of which can be configured to execute an instruction block of a program, wherein an instruction block is an atomic collection of block-based-processor instructions that includes an instruction block header and a plurality of one or more instructions; and an instruction block scheduler that is configured to allocate instruction blocks to the processor cores, wherein the allocating includes mapping an instruction block to an instruction window of a processor core, characterized in that the instruction block scheduler is further configured to: identify a recurrence comprising multiple instruction blocks that are resident on one or more of the processor cores and are to be executed again; and refresh at least one of the instruction blocks of the recurrence so that the at least one of the instruction blocks is not re-fetched during at least one iteration of the recurrence, wherein the refreshing further includes: adjusting a mapping of the identified multiple instruction blocks of the recurrence so that the identified multiple instruction blocks are re-executed on one or more of the processor cores without re-fetching the identified multiple instruction blocks of the recurrence, wherein adjusting the mapping of the identified multiple instruction blocks of the recurrence further includes remapping an instruction block of the recurrence to a different processor core and aligning the identified multiple instruction blocks of the recurrence to a particular instruction window of the one or more of the processor cores. a plurality of block-based processor cores, wherein a processor core includes one or more instruction windows, each of which can be configured to execute an instruction block of a program, wherein an instruction block is an atomic collection of block-based-processor instructions that includes an instruction block header and a plurality of one or more instructions; and an instruction block scheduler that is configured to allocate instruction blocks to the processor cores, wherein the allocating includes mapping an instruction block to an instruction window of a processor core, characterized in that the instruction block scheduler is further configured to: identify a recurrence comprising multiple instruction blocks that are resident on one or more of the processor cores and are to be executed again; and refresh at least one of the instruction blocks of the recurrence so that the at least one of the instruction blocks is not re-fetched during at least one iteration of the recurrence, wherein the refreshing further includes: adjusting a mapping of the identified multiple instruction blocks of the recurrence so that the identified multiple instruction blocks are re-executed on one or more of the processor cores without re-fetching the identified multiple instruction blocks of the recurrence, wherein adjusting the mapping of the identified multiple instruction blocks of the recurrence further includes remapping an instruction block of the recurrence to a different processor core and aligning the identified multiple instruction blocks of the recurrence to a particular instruction window of the one or more of the processor cores. identify a recurrence comprising multiple instruction blocks that are resident on one or more of the processor cores and are to be executed again; and refresh at least one of the instruction blocks of the recurrence so that the at least one of the instruction blocks is not re-fetched during at least one iteration of the recurrence, wherein the refreshing further includes: adjusting a mapping of the identified multiple instruction blocks of the recurrence so that the identified multiple instruction blocks are re-executed on one or more of the processor cores without re-fetching the identified multiple instruction blocks of the recurrence, wherein adjusting the mapping of the identified multiple instruction blocks of the recurrence further includes remapping an instruction block of the recurrence to a different processor core and aligning the identified multiple instruction blocks of the recurrence to a particular instruction window of the one or more of the processor cores. adjusting a mapping of the identified multiple instruction blocks of the recurrence so that the identified multiple instruction blocks are re-executed on one or more of the processor cores without re-fetching the identified multiple instruction blocks of the recurrence, wherein adjusting the mapping of the identified multiple instruction blocks of the recurrence further includes remapping an instruction block of the recurrence to a different processor core and aligning the identified multiple instruction blocks of the recurrence to a particular instruction window of the one or more of the processor cores.