A method comprising: receiving configuration data associated with a programmable logic device, wherein the PLD comprises an array of configuration memory cells comprising a plurality of logic block memory cells associated with a logic fabric of the PLD and a plurality of input/output (I/O) block memory cells associated with an I/O fabric (205, 210, 215, 220) of the PLD; programming a first subset of the I/O block memory cells with a first portion of the configuration data; providing a first wakeup signal to wake up functionality associated with a first portion (205, 210) of the I/O fabric associated with the first subset of the I/O block memory cells; in response to the first wakeup signal, transitioning the first portion of the I/O fabric from a configuration mode to a fast boot operation mode; programming remaining configuration memory cells of the array with a second portion of the configuration data, wherein the remaining configuration memory cells comprise a second subset of any remaining portion of the I/O block memory cells and at least a subset of the logic block memory cells; operating the first portion of the I/O fabric while the programming the remaining configuration memory cells is performed; providing a second wakeup signal to wake up functionality associated with a second portion (215, 220) of the I/O fabric associated with the second subset of the I/O block memory cells and at least a portion of the logic fabric associated with the subset of the logic block memory cells; and in response to the second wakeup signal, transitioning the first portion of the I/O fabric from the fast boot operation mode to a system operation mode and transitioning the second portion of the I/O fabric and the portion of the logic fabric from the configuration mode to the system operation mode. receiving configuration data associated with a programmable logic device, wherein the PLD comprises an array of configuration memory cells comprising a plurality of logic block memory cells associated with a logic fabric of the PLD and a plurality of input/output (I/O) block memory cells associated with an I/O fabric (205, 210, 215, 220) of the PLD; programming a first subset of the I/O block memory cells with a first portion of the configuration data; providing a first wakeup signal to wake up functionality associated with a first portion (205, 210) of the I/O fabric associated with the first subset of the I/O block memory cells; in response to the first wakeup signal, transitioning the first portion of the I/O fabric from a configuration mode to a fast boot operation mode; programming remaining configuration memory cells of the array with a second portion of the configuration data, wherein the remaining configuration memory cells comprise a second subset of any remaining portion of the I/O block memory cells and at least a subset of the logic block memory cells; operating the first portion of the I/O fabric while the programming the remaining configuration memory cells is performed; providing a second wakeup signal to wake up functionality associated with a second portion (215, 220) of the I/O fabric associated with the second subset of the I/O block memory cells and at least a portion of the logic fabric associated with the subset of the logic block memory cells; and in response to the second wakeup signal, transitioning the first portion of the I/O fabric from the fast boot operation mode to a system operation mode and transitioning the second portion of the I/O fabric and the portion of the logic fabric from the configuration mode to the system operation mode.