A memory array (100, 218, 219, 318) comprising: a plurality of planes (220, 221, 222, 223, 320, 322) each having a plurality of memory cells (202, 302) arranged in a cross point architecture of rows and columns and a plurality of plane select devices (236, 238, 336, 338), groups of the plurality of memory cells (202, 302) being coupled to a respective one of the plurality of plane select devices (236, 238, 336, 338), wherein each of the plurality of planes is formed over a substrate material and wherein a first plane is associated with a first number of access lines and a second plane is associated with a second number of access lines wherein each plane select device is a three-terminal ovonic threshold switch, OTS, that is configured to remain in an "on" state subsequent to application of a control pulse as long as a minimum holding voltage is present across the three-terminal OTS; and a decode logic (224, 226) having elements formed in the substrate material and coupled to the plurality of plane select devices (236, 238, 336, 338), wherein the first number of access lines and the second number of access lines are respectively coupled in parallel to a number of common access lines that are coupled to the decode logic (224, 226), and wherein the plurality of memory cells (202, 302) and the respective plurality of plane select devices (236, 238, 336, 338) are formed on a same plane of the plurality of planes (220, 221, 222, 223, 320, 322); and wherein respective resistors are coupled to the first number of access lines to limit a current through the respective plurality of plane select devices of the first plane; and wherein respective resistors are coupled to the second number of access lines to limit a current through the respective plurality of plane select devices of the second plane. a plurality of planes (220, 221, 222, 223, 320, 322) each having a plurality of memory cells (202, 302) arranged in a cross point architecture of rows and columns and a plurality of plane select devices (236, 238, 336, 338), groups of the plurality of memory cells (202, 302) being coupled to a respective one of the plurality of plane select devices (236, 238, 336, 338), wherein each of the plurality of planes is formed over a substrate material and wherein a first plane is associated with a first number of access lines and a second plane is associated with a second number of access lines wherein each plane select device is a three-terminal ovonic threshold switch, OTS, that is configured to remain in an "on" state subsequent to application of a control pulse as long as a minimum holding voltage is present across the three-terminal OTS; and a decode logic (224, 226) having elements formed in the substrate material and coupled to the plurality of plane select devices (236, 238, 336, 338), wherein the first number of access lines and the second number of access lines are respectively coupled in parallel to a number of common access lines that are coupled to the decode logic (224, 226), and wherein the plurality of memory cells (202, 302) and the respective plurality of plane select devices (236, 238, 336, 338) are formed on a same plane of the plurality of planes (220, 221, 222, 223, 320, 322); and wherein respective resistors are coupled to the first number of access lines to limit a current through the respective plurality of plane select devices of the first plane; and wherein respective resistors are coupled to the second number of access lines to limit a current through the respective plurality of plane select devices of the second plane.