A method for performing an erase iteration (860, 862 and 864) of an erase operation for a set (200, 300) of non-volatile storage elements which is formed on a substrate (140, 600, 900), the set of non-volatile storage elements comprises a string (201, 301) of series-connected non-volatile storage elements between first and second select transistors (202, 216, 302, 318), the series-connected non-volatile storage elements comprise a first non-user data non-volatile storage element (204, 214, 304, 316) adjacent to the first select transistor (202, 302) and a second non-user data non-volatile storage element (306, 314) adjacent to the first non-user data non-volatile storage element (304, 316), the method comprising: increasing an erase voltage (Vp-well) of the substrate to provide a first source of capacitive coupling up to a control gate (941, 949) of the first select gate transistor, while floating a voltage (Vsgs/sgd_array) of the control gate of the first select gate transistor and driving at 0 V or more a voltage (Vwldd0/wlds0_array) of a control gate (942, 948) of the first non-user data non-volatile storage element and a voltage (Vwldd1/wlds1_array) of a control gate (943, 947) of the second non-user data non-volatile storage element; increasing the erase voltage of the substrate to provide a second source of capacitive coupling up to the control gate of the first select gate transistor and to the control gate of the first non-user data non-volatile storage element, while floating the voltage of the control gate of the first select gate transistor and the voltage of the control gate of the first non-user data non-volatile storage element and driving at 0 V or more the voltage of the control gate of the second non-user data non-volatile storage element; and increasing the erase voltage of the substrate to provide a third source of capacitive coupling up to the control gates of the first select gate transistor, the first non-user data non-volatile storage element and the second non-user data non-volatile storage element, wherein the increasing of the erase voltage to provide the first source of capacitive coupling occurs before the increasing of the erase voltage to provide the second source of capacitive coupling, and the increasing of the erase voltage of the substrate to provide the second source of capacitive coupling occurs before the increasing of the erase voltage of the substrate to provide the third source of capacitive coupling. increasing an erase voltage (Vp-well) of the substrate to provide a first source of capacitive coupling up to a control gate (941, 949) of the first select gate transistor, while floating a voltage (Vsgs/sgd_array) of the control gate of the first select gate transistor and driving at 0 V or more a voltage (Vwldd0/wlds0_array) of a control gate (942, 948) of the first non-user data non-volatile storage element and a voltage (Vwldd1/wlds1_array) of a control gate (943, 947) of the second non-user data non-volatile storage element; increasing the erase voltage of the substrate to provide a second source of capacitive coupling up to the control gate of the first select gate transistor and to the control gate of the first non-user data non-volatile storage element, while floating the voltage of the control gate of the first select gate transistor and the voltage of the control gate of the first non-user data non-volatile storage element and driving at 0 V or more the voltage of the control gate of the second non-user data non-volatile storage element; and increasing the erase voltage of the substrate to provide a third source of capacitive coupling up to the control gates of the first select gate transistor, the first non-user data non-volatile storage element and the second non-user data non-volatile storage element, wherein the increasing of the erase voltage to provide the first source of capacitive coupling occurs before the increasing of the erase voltage to provide the second source of capacitive coupling, and the increasing of the erase voltage of the substrate to provide the second source of capacitive coupling occurs before the increasing of the erase voltage of the substrate to provide the third source of capacitive coupling.