A cross-coupled differential activated latch circuit, comprising: first and second inputs for receiving digital input values; first and second outputs for outputting digital latched values; first and second n-FETs connected in a cross-coupled arrangement, with a gate of each of same first and second n-FETs electrically connected to a drain of the other one of the first and second n-FETs, wherein the drain of the first n-FET is connected to the first output, and the drain of the second n-FET is connected to the second output; first and second resistors connected between a voltage source (V ddF) and the first and second outputs, respectively, for pulling up the voltage at the first and second outputs, respectively, when the first and second n-FETs, respectively, are turned off; a node SW having a changing voltage; in that circuitry comprising a plurality of n-FETs (76, 78, 80, 82) and inverters (72, 74) connected to the first and second inputs, the first and second outputs, the first and second cross-coupled n-FETs and the node SW, for preventing common mode signals appearing as the same logic signal at the latch inputs caused by the changing voltage on the node SW from affecting the digital latched values of the first and second outputs, wherein the plurality of inverters (74, 72) comprise first and second inverters having inputs connected, respectively, to the first and second inputs, and having outputs connected, respectively, to sixth and third n-FETs, and wherein the third and fifth n-FETs are connected, respectively, to the second and first n-FETs, such that the digital latched values on the first and second outputs only change if the digital input values on the first and second inputs are opposite to each other. first and second inputs for receiving digital input values; first and second outputs for outputting digital latched values; first and second n-FETs connected in a cross-coupled arrangement, with a gate of each of same first and second n-FETs electrically connected to a drain of the other one of the first and second n-FETs, wherein the drain of the first n-FET is connected to the first output, and the drain of the second n-FET is connected to the second output; first and second resistors connected between a voltage source (V ddF) and the first and second outputs, respectively, for pulling up the voltage at the first and second outputs, respectively, when the first and second n-FETs, respectively, are turned off; a node SW having a changing voltage; in that circuitry comprising a plurality of n-FETs (76, 78, 80, 82) and inverters (72, 74) connected to the first and second inputs, the first and second outputs, the first and second cross-coupled n-FETs and the node SW, for preventing common mode signals appearing as the same logic signal at the latch inputs caused by the changing voltage on the node SW from affecting the digital latched values of the first and second outputs, wherein the plurality of inverters (74, 72) comprise first and second inverters having inputs connected, respectively, to the first and second inputs, and having outputs connected, respectively, to sixth and third n-FETs, and wherein the third and fifth n-FETs are connected, respectively, to the second and first n-FETs, such that the digital latched values on the first and second outputs only change if the digital input values on the first and second inputs are opposite to each other.