A communication chip, characterized by comprising: a plurality of synchronization modules; a set of buffer modules; and a plurality of alignment modules, wherein each of the plurality of synchronization modules is configured to receive data of a corresponding channel, synchronize received data, and store synchronized data into a corresponding buffer module; the set of buffer modules comprise a plurality of first-in-first-out queues FIFOs, and each FIFO is configured to buffer the synchronized data output by a corresponding synchronization module; and each of the plurality of alignment modules is configured to align the synchronized data of corresponding channels in corresponding buffer modules, combine aligned data and output combined data, a number of the plurality of synchronization modules is 8, a number of the plurality of alignment modules is 7, and a number of the plurality of FIFOs is 8, characterized in that, the plurality of alignment modules comprise four first alignment modules, two second alignment modules and one third alignment module; each first alignment module is configured to align the synchronized data of two channels corresponding to buffers of two FIFOs, and combine aligned data and output combined data of the two channels; each second alignment module is configured to align the synchronized data of four channels corresponding to buffers of four FIFOs, and combine aligned data and output combined data of the four channels; and the third alignment module is configured to align the synchronized data of eight channels corresponding to buffers of eight FIFOs, and combine aligned data and output combined data of the eight channels. a plurality of synchronization modules; a set of buffer modules; and a plurality of alignment modules, wherein each of the plurality of synchronization modules is configured to receive data of a corresponding channel, synchronize received data, and store synchronized data into a corresponding buffer module; the set of buffer modules comprise a plurality of first-in-first-out queues FIFOs, and each FIFO is configured to buffer the synchronized data output by a corresponding synchronization module; and each of the plurality of alignment modules is configured to align the synchronized data of corresponding channels in corresponding buffer modules, combine aligned data and output combined data, a number of the plurality of synchronization modules is 8, a number of the plurality of alignment modules is 7, and a number of the plurality of FIFOs is 8, characterized in that, the plurality of alignment modules comprise four first alignment modules, two second alignment modules and one third alignment module; each first alignment module is configured to align the synchronized data of two channels corresponding to buffers of two FIFOs, and combine aligned data and output combined data of the two channels; each second alignment module is configured to align the synchronized data of four channels corresponding to buffers of four FIFOs, and combine aligned data and output combined data of the four channels; and the third alignment module is configured to align the synchronized data of eight channels corresponding to buffers of eight FIFOs, and combine aligned data and output combined data of the eight channels.