An optical transceiver comprising: a decoder configured to decode an 8B10B line-coded signal into a decoded signal having sixty-four bits, wherein the decoded signal includes a data code; a data mapper configured to: separate the decoded signal from the decoder into block units by combining eight 8-bit signals; identify control codes in the block units using a K signal and sequentially map the control codes from a starting point in the block; and secure extra memory space by subtracting the number of bits of the decoded signal and the number of bits of a block information code from the number of bits of a corresponding group of eight 8B10B line-coded signals; and map a block information code including a flag bit onto a corresponding block, the flag bit configured to indicate whether or not the corresponding block contains a control code, wherein a flag bit value of 1 indicates that the control code exists in the corresponding block; a demultiplexer configured to split the 8B10B line-coded signal into a plurality of parallel signals and transfer the split signals to the decoder for decoding; a Forward Error Correction, FEC, encoding unit configured to create FEC data and map the FEC data onto the extra memory space; and a framer configured to form a frame by mapping a plurality of blocks, onto which the FEC data, the decoded signal and the block information codes are mapped, to a generic Framing Procedure, GFP, frame; wherein the decoder is configured to decode the 8B10B line-coded signal into an original 8-bit value if an input signal is a code word or decode the 8B 10B line-coded signal into a 4-bit Control Code Indicator, CCI, 3-bit position information and an extra one bit if the input signal is a control code word, wherein the extra one bit of the control code is a Last Control Character, LCC, which is configured to indicate whether or not a subsequent 8-bit symbol is a control code, wherein when LCC=1, a next 8-bit symbol is a control code and when LCC=0, a corresponding symbol is the last control code in the block, wherein the 3-bit position information indicates an original position of the control code within a sequence of eight 8-bit symbols contained in the block. a decoder configured to decode an 8B10B line-coded signal into a decoded signal having sixty-four bits, wherein the decoded signal includes a data code; a data mapper configured to: separate the decoded signal from the decoder into block units by combining eight 8-bit signals; identify control codes in the block units using a K signal and sequentially map the control codes from a starting point in the block; and secure extra memory space by subtracting the number of bits of the decoded signal and the number of bits of a block information code from the number of bits of a corresponding group of eight 8B10B line-coded signals; and map a block information code including a flag bit onto a corresponding block, the flag bit configured to indicate whether or not the corresponding block contains a control code, wherein a flag bit value of 1 indicates that the control code exists in the corresponding block; separate the decoded signal from the decoder into block units by combining eight 8-bit signals; identify control codes in the block units using a K signal and sequentially map the control codes from a starting point in the block; and secure extra memory space by subtracting the number of bits of the decoded signal and the number of bits of a block information code from the number of bits of a corresponding group of eight 8B10B line-coded signals; and map a block information code including a flag bit onto a corresponding block, the flag bit configured to indicate whether or not the corresponding block contains a control code, wherein a flag bit value of 1 indicates that the control code exists in the corresponding block; a demultiplexer configured to split the 8B10B line-coded signal into a plurality of parallel signals and transfer the split signals to the decoder for decoding; a Forward Error Correction, FEC, encoding unit configured to create FEC data and map the FEC data onto the extra memory space; and a framer configured to form a frame by mapping a plurality of blocks, onto which the FEC data, the decoded signal and the block information codes are mapped, to a generic Framing Procedure, GFP, frame; wherein the decoder is configured to decode the 8B10B line-coded signal into an original 8-bit value if an input signal is a code word or decode the 8B 10B line-coded signal into a 4-bit Control Code Indicator, CCI, 3-bit position information and an extra one bit if the input signal is a control code word, wherein the extra one bit of the control code is a Last Control Character, LCC, which is configured to indicate whether or not a subsequent 8-bit symbol is a control code, wherein when LCC=1, a next 8-bit symbol is a control code and when LCC=0, a corresponding symbol is the last control code in the block, wherein the 3-bit position information indicates an original position of the control code within a sequence of eight 8-bit symbols contained in the block.