Method for operating a drive circuit for driving an electronically commutated motor, wherein the drive circuit has a power factor correction circuit for feeding sinusoidal currents to a DC link from an AC terminal which is connectable to a power supply grid, wherein the power supply grid feeds the drive circuit with a positive grid half-cycle and a negative grid half-cycle, the DC link feeds the motor via an inverter having polyphase bridge circuits (S7-S12), and the drive circuit also has a control device for controlling the power switches (S7-S12) of the inverter and the switches (S1-S6, S13-S16) of the power factor correction circuit, which control device controls the switches (S1-S6, S13-S16) of the power factor correction circuit in such a way that the two poles (14m, 14p) of the DC link are connected alternately to a neutral conductor of the power supply grid via the power factor correction circuit, characterized in that the drive circuit also has a polarity reversal circuit between the AC terminal and the power factor correction circuit, which polarity reversal circuit contains switches (S17-S20) for selectively connecting a phase line (L') and a neutral line (N') of the power factor correction circuit to the two poles of the AC terminal, and a polarity of the conductors (L, N) of the power supply grid which are connected to the AC terminal is checked by means of the control device, and then, by way of controlling the polarity reversal circuit, a phase line (L') of the power factor correction circuit is connected to that pole of the AC terminal which is connected to the phase conductor of the power supply grid, and a neutral line (N') of the power factor correction circuit is connected to that pole of the AC terminal which is connected to the neutral conductor of the power supply grid; and the frequency for the alternating connection of the two poles (14m, 14p) of the DC link to the neutral conductor of the power supply grid corresponds to the line frequency of the line voltage (U LN) of the power supply grid, wherein, in the positive grid half-cycle, substantially only those power switches (S2, S3, S13, S14) of the power factor correction circuit which are connected to the negative pole of the DC link are clocked, and in the negative grid half-cycle, substantially only those power switches (S1, S4, S15, S16) of the power factor correction circuit which are connected to the positive pole of the DC link are clocked. the drive circuit also has a polarity reversal circuit between the AC terminal and the power factor correction circuit, which polarity reversal circuit contains switches (S17-S20) for selectively connecting a phase line (L') and a neutral line (N') of the power factor correction circuit to the two poles of the AC terminal, and a polarity of the conductors (L, N) of the power supply grid which are connected to the AC terminal is checked by means of the control device, and then, by way of controlling the polarity reversal circuit, a phase line (L') of the power factor correction circuit is connected to that pole of the AC terminal which is connected to the phase conductor of the power supply grid, and a neutral line (N') of the power factor correction circuit is connected to that pole of the AC terminal which is connected to the neutral conductor of the power supply grid; and the frequency for the alternating connection of the two poles (14m, 14p) of the DC link to the neutral conductor of the power supply grid corresponds to the line frequency of the line voltage (U LN) of the power supply grid, wherein, in the positive grid half-cycle, substantially only those power switches (S2, S3, S13, S14) of the power factor correction circuit which are connected to the negative pole of the DC link are clocked, and in the negative grid half-cycle, substantially only those power switches (S1, S4, S15, S16) of the power factor correction circuit which are connected to the positive pole of the DC link are clocked.