A display device comprising: a storage electrode pattern (SC, 120, 320) on a substrate (110, 200, 310, 400, 500, 600); a dielectric layer (FD, 130, 330) on the substrate (110, 200, 310, 400, 500, 600), the dielectric layer (FD, 130, 330) covering the storage electrode pattern (SC, 120, 320); a thin film transistor; a data line on the dielectric layer (FD, 130, 330), a source electrode electrically connected to the data line and a drain electrode on the dielectric layer (FD, 130, 330), wherein the drain electrode is arranged as an output terminal (DE, 140, 340) of the thin film transistor that outputs a data signal based on a timing signal; a dielectric pattern (DP, 150, 350) on the dielectric layer (FD, 130, 330), the dielectric pattern (DP, 150, 350) having a first contact hole (152, 352) through which the output terminal (DE, 140, 340) is exposed; an insulating pattern (IP, 160, 360) on the dielectric pattern (DP, 150, 350), the insulating pattern (IP, 160, 360) having a second contact hole (162, 362) corresponding to the first contact hole (152,352) and a third contact hole (164, 364) through which a portion of the dielectric pattern (DP, 150, 350) corresponding to the storage electrode pattern (SC, 120, 320) is exposed, wherein the first contact hole extends through the whole thickness of the insulating pattern and the dielectric pattern to expose the output terminal; and a pixel electrode (PE, 170, 370) electrically connected to the output terminal (DE, 140, 340) on the insulating pattern (IP, 160, 360), the pixel electrode (PE, 170, 370) comprising a storage electrode portion (172, 372) corresponding to the storage electrode pattern (SC, 120, 320), and the storage electrode pattern (SC, 120, 320), the dielectric layer (FD, 130, 330) and the storage electrode portion (172, 372) of the pixel electrode (PE, 170, 370) form a storage capacitor; characterised in that the second contact hole (162, 362) has a first opening (162a, 362a) of a first area (A 1) and a second opening (162b, 362b) having a second area (A 2) that is larger than the first area (A 1), and the second opening (162b, 362b) is connected to the first opening (162a, 362a), and in that the dielectric pattern (DP, 150, 350) has a surface increasing part (355, 357, SI) corresponding to the storage electrode pattern (SC, 120, 320), wherein the surface increasing part (355, 357, SI) is exposed through the third contact hole (164, 364). a storage electrode pattern (SC, 120, 320) on a substrate (110, 200, 310, 400, 500, 600); a dielectric layer (FD, 130, 330) on the substrate (110, 200, 310, 400, 500, 600), the dielectric layer (FD, 130, 330) covering the storage electrode pattern (SC, 120, 320); a thin film transistor; a data line on the dielectric layer (FD, 130, 330), a source electrode electrically connected to the data line and a drain electrode on the dielectric layer (FD, 130, 330), wherein the drain electrode is arranged as an output terminal (DE, 140, 340) of the thin film transistor that outputs a data signal based on a timing signal; a dielectric pattern (DP, 150, 350) on the dielectric layer (FD, 130, 330), the dielectric pattern (DP, 150, 350) having a first contact hole (152, 352) through which the output terminal (DE, 140, 340) is exposed; an insulating pattern (IP, 160, 360) on the dielectric pattern (DP, 150, 350), the insulating pattern (IP, 160, 360) having a second contact hole (162, 362) corresponding to the first contact hole (152,352) and a third contact hole (164, 364) through which a portion of the dielectric pattern (DP, 150, 350) corresponding to the storage electrode pattern (SC, 120, 320) is exposed, wherein the first contact hole extends through the whole thickness of the insulating pattern and the dielectric pattern to expose the output terminal; and a pixel electrode (PE, 170, 370) electrically connected to the output terminal (DE, 140, 340) on the insulating pattern (IP, 160, 360), the pixel electrode (PE, 170, 370) comprising a storage electrode portion (172, 372) corresponding to the storage electrode pattern (SC, 120, 320), and the storage electrode pattern (SC, 120, 320), the dielectric layer (FD, 130, 330) and the storage electrode portion (172, 372) of the pixel electrode (PE, 170, 370) form a storage capacitor; characterised in that the second contact hole (162, 362) has a first opening (162a, 362a) of a first area (A 1) and a second opening (162b, 362b) having a second area (A 2) that is larger than the first area (A 1), and the second opening (162b, 362b) is connected to the first opening (162a, 362a), and in that the dielectric pattern (DP, 150, 350) has a surface increasing part (355, 357, SI) corresponding to the storage electrode pattern (SC, 120, 320), wherein the surface increasing part (355, 357, SI) is exposed through the third contact hole (164, 364).