A circuit comprising: a memory array comprising: a plurality of bit lines; a plurality of word lines; a plurality of select lines, the plurality of bit lines and the plurality of select lines intersect the plurality of word lines; and a plurality of memory cells each comprising: a first transistor, a second transistor, a first memory element, and a second memory element, the first and second memory elements are connected to the plurality of word lines by way of the first and second transistors, the first and second memory elements are connected to the plurality of bit lines and the plurality of select lines, and characterised by, wherein: the first transistor and the second transistor are a complementary pair of bipolar junction pass transistors, the complementary pair of bipolar junction pass transistors comprising an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor, or the first transistor and the second transistor are a complementary pair of junction field-effect transistors, the complementary pair of junction field-effect transistors comprising an n-channel junction field-effect transistor and a p-channel junction field effect-transistor; and wherein the first memory element is connected between one of the plurality of bit lines and a first shared collector emitter or source drain terminal of the complementary pair, and the second memory element is connected between one of the plurality of select lines and a second shared collector emitter or source drain terminal of the complementary pair. a memory array comprising: a plurality of bit lines; a plurality of word lines; a plurality of select lines, the plurality of bit lines and the plurality of select lines intersect the plurality of word lines; and a plurality of memory cells each comprising: a first transistor, a second transistor, a first memory element, and a second memory element, the first and second memory elements are connected to the plurality of word lines by way of the first and second transistors, the first and second memory elements are connected to the plurality of bit lines and the plurality of select lines, and characterised by, wherein: a plurality of bit lines; a plurality of word lines; a plurality of select lines, the plurality of bit lines and the plurality of select lines intersect the plurality of word lines; and a plurality of memory cells each comprising: a first transistor, a second transistor, a first memory element, and a second memory element, the first and second memory elements are connected to the plurality of word lines by way of the first and second transistors, the first and second memory elements are connected to the plurality of bit lines and the plurality of select lines, and characterised by, wherein: a first transistor, a second transistor, a first memory element, and a second memory element, the first and second memory elements are connected to the plurality of word lines by way of the first and second transistors, the first and second memory elements are connected to the plurality of bit lines and the plurality of select lines, and characterised by, wherein: the first transistor and the second transistor are a complementary pair of bipolar junction pass transistors, the complementary pair of bipolar junction pass transistors comprising an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor, or the first transistor and the second transistor are a complementary pair of junction field-effect transistors, the complementary pair of junction field-effect transistors comprising an n-channel junction field-effect transistor and a p-channel junction field effect-transistor; and wherein the first memory element is connected between one of the plurality of bit lines and a first shared collector emitter or source drain terminal of the complementary pair, and the second memory element is connected between one of the plurality of select lines and a second shared collector emitter or source drain terminal of the complementary pair.