An apparatus, comprising: a non-volatile memory cell including: a memory element comprising a first chalcogenide material, wherein the memory element is configured to exhibit a first threshold voltage based on the magnitude of a voltage applied across the memory cell; and a selector device electrically coupled to the memory element comprising a second chalcogenide material, wherein the selector device is configured to exhibit a second threshold voltage based on the relative voltage polarities of read and write pulses applied across the memory cell; a first memory access line coupled to the memory cell; a second memory access line coupled to the memory cell; a first access line driver coupled to the first memory access line; and a second access line driver coupled to the second memory access line, wherein the first and second access line drivers are configured to: provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell, provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell, provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell, and provide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell, wherein the first, second, third, and fourth logic states correspond to values of a first bit and a second bit of data stored in the memory cell, wherein the first bit is stored in the memory element and is represented by the first threshold voltage, and the second bit is stored in the selector device and is represented by the second threshold voltage. a non-volatile memory cell including: a memory element comprising a first chalcogenide material, wherein the memory element is configured to exhibit a first threshold voltage based on the magnitude of a voltage applied across the memory cell; and a selector device electrically coupled to the memory element comprising a second chalcogenide material, wherein the selector device is configured to exhibit a second threshold voltage based on the relative voltage polarities of read and write pulses applied across the memory cell; a memory element comprising a first chalcogenide material, wherein the memory element is configured to exhibit a first threshold voltage based on the magnitude of a voltage applied across the memory cell; and a selector device electrically coupled to the memory element comprising a second chalcogenide material, wherein the selector device is configured to exhibit a second threshold voltage based on the relative voltage polarities of read and write pulses applied across the memory cell; a first memory access line coupled to the memory cell; a second memory access line coupled to the memory cell; a first access line driver coupled to the first memory access line; and a second access line driver coupled to the second memory access line, wherein the first and second access line drivers are configured to: provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell, provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell, provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell, and provide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell, wherein the first, second, third, and fourth logic states correspond to values of a first bit and a second bit of data stored in the memory cell, wherein the first bit is stored in the memory element and is represented by the first threshold voltage, and the second bit is stored in the selector device and is represented by the second threshold voltage. provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell, provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell, provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell, and provide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell, wherein the first, second, third, and fourth logic states correspond to values of a first bit and a second bit of data stored in the memory cell, wherein the first bit is stored in the memory element and is represented by the first threshold voltage, and the second bit is stored in the selector device and is represented by the second threshold voltage.