A circuit comprising: a multi-stage amplifier chain (Eq1, Eq2, Eq3, Eq4), including a first amplifier stage and a last amplifier stage in the chain; an offset cancellation loop configured to receive an output (V OFF_OUT) of the last amplifier stage and to provide an offset correction voltage signal (V CORR, VOFP, VOFN) to the first amplifier stage; an input transistor (M1,M2) in the first amplifier stage, the input transistor (M1,M2) having a gate, source and drain, wherein the gate of the input transistor (M1,M2) is configured to receive an input signal (INN,INP); and an offset compensation transistor (Mofcp, Mofcn) in the first amplifier stage, the offset compensation transistor (Mofcp, Mofcn) having a gate, source, and drain, wherein the drain of the offset compensation transistor (Mofcp, Mofcn) is electrically connected to the source of the input transistor (M1,M2) and a voltage on the gate of the offset compensation transistor (Mofcp, Mofcn) is determined by the offset correction voltage signal (V CORR; VOFN, VOFN); characterized by an impedance (Z1, Z2) which is electrically connected to the source of the offset compensation transistor (Mofcp, Mofcn); and a tail current source (I 1, I 2) which is electrically connected to the source of the offset compensation transistor (Mofcp, Mofcn), and a resistor (Rfxp, Rfxn) configured in parallel with a channel of the offset compensation transistor (Mofcp, Mofcn), wherein one end of the resistor is electrically coupled to the source of the offset compensation transistor (Mofcp, Mofcn), and another end of the resistor is electrically coupled to the drain of the offset compensation transistor (Mofcp, Mofcn). a multi-stage amplifier chain (Eq1, Eq2, Eq3, Eq4), including a first amplifier stage and a last amplifier stage in the chain; an offset cancellation loop configured to receive an output (V OFF_OUT) of the last amplifier stage and to provide an offset correction voltage signal (V CORR, VOFP, VOFN) to the first amplifier stage; an input transistor (M1,M2) in the first amplifier stage, the input transistor (M1,M2) having a gate, source and drain, wherein the gate of the input transistor (M1,M2) is configured to receive an input signal (INN,INP); and an offset compensation transistor (Mofcp, Mofcn) in the first amplifier stage, the offset compensation transistor (Mofcp, Mofcn) having a gate, source, and drain, wherein the drain of the offset compensation transistor (Mofcp, Mofcn) is electrically connected to the source of the input transistor (M1,M2) and a voltage on the gate of the offset compensation transistor (Mofcp, Mofcn) is determined by the offset correction voltage signal (V CORR; VOFN, VOFN); characterized by an impedance (Z1, Z2) which is electrically connected to the source of the offset compensation transistor (Mofcp, Mofcn); and a tail current source (I 1, I 2) which is electrically connected to the source of the offset compensation transistor (Mofcp, Mofcn), and a resistor (Rfxp, Rfxn) configured in parallel with a channel of the offset compensation transistor (Mofcp, Mofcn), wherein one end of the resistor is electrically coupled to the source of the offset compensation transistor (Mofcp, Mofcn), and another end of the resistor is electrically coupled to the drain of the offset compensation transistor (Mofcp, Mofcn).