A display panel, comprising a plurality of subpixels, a respective subpixel comprising a respective light emitting element and a respective pixel driving circuit; wherein the display panel comprises: a base substrate; a plurality of light emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements; wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area; the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer; the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer; and the plurality of first signal lines are electrically connected to the plurality of second signal lines, characterized in that, the display panel further comprises: a gate-on-array circuit in the peripheral area of the display panel; an anode metal layer on a side of a first peripheral first voltage line (pvss1) of the interconnected first voltage supply network away from the gate-on-array circuit; and a cathode layer on a side of the anode metal layer away from the first peripheral first voltage line (pvss1); wherein the first peripheral first voltage line (pvss1) is in the peripheral area on a first side of the display panel; and an orthographic projection of the first peripheral first voltage line (pvss1) on the base substrate at least partially overlaps with an orthographic projection of the gate-on-array circuit on the base substrate, and wherein the cathode layer is connected to the anode metal layer through one or more first peripheral vias in the peripheral area and extending through a third planarization layer, and the anode metal layer is connected to the first peripheral first voltage line (pvss1) through one or more second peripheral vias in the peripheral area and extending through a second planarization layer, thereby providing the first voltage signal to the cathodes of the plurality of light emitting elements; the one or more first peripheral vias connecting the cathode layer and the anode metal layer, and the one or more second peripheral vias connecting the anode metal layer and the interconnected first voltage supply network are limited in the peripheral area, and absent in the display area; and the first peripheral first voltage line (pvss1) and the anode metal layer connected to the first peripheral first voltage line (pvss1) respectively partially surround the display area. a base substrate; a plurality of light emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements; wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area; the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer; the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer; and the plurality of first signal lines are electrically connected to the plurality of second signal lines, characterized in that, the display panel further comprises: a gate-on-array circuit in the peripheral area of the display panel; an anode metal layer on a side of a first peripheral first voltage line (pvss1) of the interconnected first voltage supply network away from the gate-on-array circuit; and a cathode layer on a side of the anode metal layer away from the first peripheral first voltage line (pvss1); wherein the first peripheral first voltage line (pvss1) is in the peripheral area on a first side of the display panel; and an orthographic projection of the first peripheral first voltage line (pvss1) on the base substrate at least partially overlaps with an orthographic projection of the gate-on-array circuit on the base substrate, and wherein the cathode layer is connected to the anode metal layer through one or more first peripheral vias in the peripheral area and extending through a third planarization layer, and the anode metal layer is connected to the first peripheral first voltage line (pvss1) through one or more second peripheral vias in the peripheral area and extending through a second planarization layer, thereby providing the first voltage signal to the cathodes of the plurality of light emitting elements; the one or more first peripheral vias connecting the cathode layer and the anode metal layer, and the one or more second peripheral vias connecting the anode metal layer and the interconnected first voltage supply network are limited in the peripheral area, and absent in the display area; and the first peripheral first voltage line (pvss1) and the anode metal layer connected to the first peripheral first voltage line (pvss1) respectively partially surround the display area.