A static random access memory, SRAM,cache memory comprising: a memory access logic circuit provided in a first data access path, the memory access logic circuit comprising a tag array, the memory access logic circuit configured to: receive a data entry address of a memory access request for addressing a data entry in a SRAM data array in the first data access path; access the tag array to determine if the data entry address is accessible in the SRAM data array; in response to the data entry address being accessible in the SRAM data array, generate a data index based on the received data entry address in the first data access path to index the SRAM data array for accessing the data entry in the SRAM data array corresponding to the received data entry address; and a pre-charge circuit provided in a second data access path separate from the first data access path, the pre-charge circuit configured to, prior to accessing the data entry in the SRAM data array: receive the data entry address in the second data access path; and generate a pre-charge enable to at least a portion of the SRAM data array based on the received data entry address in the second data access path to pre-charge the at least a portion of the SRAM data array. a memory access logic circuit provided in a first data access path, the memory access logic circuit comprising a tag array, the memory access logic circuit configured to: receive a data entry address of a memory access request for addressing a data entry in a SRAM data array in the first data access path; access the tag array to determine if the data entry address is accessible in the SRAM data array; in response to the data entry address being accessible in the SRAM data array, generate a data index based on the received data entry address in the first data access path to index the SRAM data array for accessing the data entry in the SRAM data array corresponding to the received data entry address; and receive a data entry address of a memory access request for addressing a data entry in a SRAM data array in the first data access path; access the tag array to determine if the data entry address is accessible in the SRAM data array; in response to the data entry address being accessible in the SRAM data array, generate a data index based on the received data entry address in the first data access path to index the SRAM data array for accessing the data entry in the SRAM data array corresponding to the received data entry address; and a pre-charge circuit provided in a second data access path separate from the first data access path, the pre-charge circuit configured to, prior to accessing the data entry in the SRAM data array: receive the data entry address in the second data access path; and generate a pre-charge enable to at least a portion of the SRAM data array based on the received data entry address in the second data access path to pre-charge the at least a portion of the SRAM data array. receive the data entry address in the second data access path; and generate a pre-charge enable to at least a portion of the SRAM data array based on the received data entry address in the second data access path to pre-charge the at least a portion of the SRAM data array.