A power electronics circuit (10; 20; 30; 40) comprising: an electrical first gate (12; 12a-b) comprising a first (14; 14a-d) and a second terminal (16; 16a-d); a magnetic second gate comprising a first (22; 22a-d) and a second terminal (24; 24a-d); a first parallel branch (26; 26'; 26'a-b) comprising a first series connection of at least a first switch (S 11; S 31), a second switch (S 1; S 12; S 32) and a third switch (S 22; S 42); and a second parallel branch (34; 34'; 34'a-b) connected in parallel to the first parallel branch (26; 26; 26'a-b) and comprising a second series connection of at least a first switch (S 13; S 33), a second switch (S 2; S 14; S 34) and a third switch (S 24; S 44); wherein the first terminal (14; 14a-d) of the electrical first gate (12; 12a-b) is connected to a first node (28, 36) between the first (S 11, S 13, S 31) S 33) and the second switch (S 12, S 14; S 1, S 2, S 32, S 34) in the first (26; 26'; 26'a-b) and the second parallel branch (34; 34'; 34'a-b) via a respective coil (L 1a, L 1b; L 31, L 3b); wherein the second terminal (16; 16a-d) of the electrical first gate (12; 12a-b) is connected to a second node (32, 38) between the second (S 12, S 14; S 1, S 2, S 32, S 34) and the third switch (S 22, S 42, S 24; S 44) in the first (26; 26'; 26'a-b) and the second parallel branch (34; 34'; 34'a-b) via a respective coil (L 2a, L 2b; L 4a, L 4b); wherein the first nodes (28, 36) are coupled magnetically to the first terminal (22; 22a-d) of the magnetic second gate by means of magnetically coupled repeating coils (L 1; L 1P, L 1S); and wherein the second nodes (32, 38) are coupled magnetically to the second terminal (24; 24a-d) of the magnetic second gate by means of magnetically coupled repeating coils (L 2; L 2P, L 2S). an electrical first gate (12; 12a-b) comprising a first (14; 14a-d) and a second terminal (16; 16a-d); a magnetic second gate comprising a first (22; 22a-d) and a second terminal (24; 24a-d); a first parallel branch (26; 26'; 26'a-b) comprising a first series connection of at least a first switch (S 11; S 31), a second switch (S 1; S 12; S 32) and a third switch (S 22; S 42); and a second parallel branch (34; 34'; 34'a-b) connected in parallel to the first parallel branch (26; 26; 26'a-b) and comprising a second series connection of at least a first switch (S 13; S 33), a second switch (S 2; S 14; S 34) and a third switch (S 24; S 44); wherein the first terminal (14; 14a-d) of the electrical first gate (12; 12a-b) is connected to a first node (28, 36) between the first (S 11, S 13, S 31) S 33) and the second switch (S 12, S 14; S 1, S 2, S 32, S 34) in the first (26; 26'; 26'a-b) and the second parallel branch (34; 34'; 34'a-b) via a respective coil (L 1a, L 1b; L 31, L 3b); wherein the second terminal (16; 16a-d) of the electrical first gate (12; 12a-b) is connected to a second node (32, 38) between the second (S 12, S 14; S 1, S 2, S 32, S 34) and the third switch (S 22, S 42, S 24; S 44) in the first (26; 26'; 26'a-b) and the second parallel branch (34; 34'; 34'a-b) via a respective coil (L 2a, L 2b; L 4a, L 4b); wherein the first nodes (28, 36) are coupled magnetically to the first terminal (22; 22a-d) of the magnetic second gate by means of magnetically coupled repeating coils (L 1; L 1P, L 1S); and wherein the second nodes (32, 38) are coupled magnetically to the second terminal (24; 24a-d) of the magnetic second gate by means of magnetically coupled repeating coils (L 2; L 2P, L 2S).