A fingerprint identification system (10, 30, 50, 70), comprising: a pixel array circuit (12, 52), wherein the pixel array circuit (12, 52) is switched to a normal operation mode in response to a control signal (ctrl); a first peripheral top electrode (14, 34a, 54, 74a), arranged at a first side of the pixel array circuit (12, 52), wherein the first peripheral top electrode (14, 34a, 54, 74a) is formed in a same integrated circuit as the pixel array circuit (12, 52), and is located at an uppermost metal layer of a circuit layout of the integrated circuit; a peripheral circuit arranged below the first peripheral top electrode (14, 34a, 54, 74a), wherein the peripheral circuit includes a serial peripheral interface bus circuit or a low dropout regulator circuit; a first capacitive sensing circuit (16, 36, 56, 76a), coupled to the first peripheral top electrode (14, 34a, 54, 74a), the first capacitive sensing circuit (16, 36, 56, 76a) being used for sensing capacitance associated with the first peripheral top electrode (14, 34a, 54, 74a) in a sleep mode and generating a sensing result (Rst); and a logic control circuit, coupled to the first capacitive sensing circuit (16, 36, 56, 76a), the logic control circuit being used for generating the control signal (ctrl) according to the sensing result (Rst); wherein when the sensing result (Rst) indicates that the first peripheral top electrode (14, 34a, 54, 74a) is coupled by a finger when the user presses the finger on the pixel array circuit (12, 52), the logic control circuit generates the control signal (ctrl), and the pixel array circuit (12, 52) is switched from the sleep mode into the normal operation mode accordingly; wherein in the normal operation mode, the pixel array circuit (12, 52) performs fingerprint identification with respect to a finger, the fingerprint identification system (10, 30, 50, 70) further comprising: a first driving circuit, arranged for generating a first driving signal to the first peripheral top electrode (14, 34a, 54, 74a) in the sleep mode, wherein the first capacitive sensing circuit (16, 36, 56, 76a) senses capacitance between the first peripheral top electrode (14, 34a, 54, 74a) and a ground terminal in the sleep mode. a pixel array circuit (12, 52), wherein the pixel array circuit (12, 52) is switched to a normal operation mode in response to a control signal (ctrl); a first peripheral top electrode (14, 34a, 54, 74a), arranged at a first side of the pixel array circuit (12, 52), wherein the first peripheral top electrode (14, 34a, 54, 74a) is formed in a same integrated circuit as the pixel array circuit (12, 52), and is located at an uppermost metal layer of a circuit layout of the integrated circuit; a peripheral circuit arranged below the first peripheral top electrode (14, 34a, 54, 74a), wherein the peripheral circuit includes a serial peripheral interface bus circuit or a low dropout regulator circuit; a first capacitive sensing circuit (16, 36, 56, 76a), coupled to the first peripheral top electrode (14, 34a, 54, 74a), the first capacitive sensing circuit (16, 36, 56, 76a) being used for sensing capacitance associated with the first peripheral top electrode (14, 34a, 54, 74a) in a sleep mode and generating a sensing result (Rst); and a logic control circuit, coupled to the first capacitive sensing circuit (16, 36, 56, 76a), the logic control circuit being used for generating the control signal (ctrl) according to the sensing result (Rst); wherein when the sensing result (Rst) indicates that the first peripheral top electrode (14, 34a, 54, 74a) is coupled by a finger when the user presses the finger on the pixel array circuit (12, 52), the logic control circuit generates the control signal (ctrl), and the pixel array circuit (12, 52) is switched from the sleep mode into the normal operation mode accordingly; wherein in the normal operation mode, the pixel array circuit (12, 52) performs fingerprint identification with respect to a finger, the fingerprint identification system (10, 30, 50, 70) further comprising: a first driving circuit, arranged for generating a first driving signal to the first peripheral top electrode (14, 34a, 54, 74a) in the sleep mode, wherein the first capacitive sensing circuit (16, 36, 56, 76a) senses capacitance between the first peripheral top electrode (14, 34a, 54, 74a) and a ground terminal in the sleep mode. a first driving circuit, arranged for generating a first driving signal to the first peripheral top electrode (14, 34a, 54, 74a) in the sleep mode, wherein the first capacitive sensing circuit (16, 36, 56, 76a) senses capacitance between the first peripheral top electrode (14, 34a, 54, 74a) and a ground terminal in the sleep mode.