A multi-stage analog-to-digital converter, ADC, having calibration and coupled to convert an input signal into a digital conversion output comprising: a multiplying digital-to-analog converter, MDAC, coupled to receive the input signal and to output N-bit digital values and a residue current as output signal based upon the input signal and the N-bit digital values, the MDAC comprising an initial analog-to-digital converter, ADC, coupled to receive the input signal and to provide the N-bit digital value as output; an additional analog-to-digital converter, ADC, coupled to receive a plurality of time-interleaved currents generated on the basis of the residue current from the MDAC and having an M-bit digital value as output signal; and wherein the additional ADC comprises: an array of sub analog-to-digital converters, sub-ADC, each sub-ADC (430,432,434) of the array of sub-ADCs comprising a current-controlled ring oscillator coupled to receive a current from the plurality of time-interleaved currents and convert it into a digital value; a combiner coupled to receive the digital value from each of the sub-ADCs (430,432,434) and provide the M-bit digital value; calibration logic coupled to receive the N-bit digital values from the MDAC and M-bit digital values from the additional ADC as inputs to provide correction values as outputs, wherein the correction values for each operational region (562, 564) determined by the N-bit digital values are calculated based upon differences between expected range values of each operational region and actual range values of each operational region, the actual range values being determined from the differences between recorded maximum values and minimum values of the M-bit digital values, wherein the expected range values are predetermined values; wherein the digital conversion output comprises combinations of the N-bit digital values and the M-bit digital values corrected with the correction values. a multiplying digital-to-analog converter, MDAC, coupled to receive the input signal and to output N-bit digital values and a residue current as output signal based upon the input signal and the N-bit digital values, the MDAC comprising an initial analog-to-digital converter, ADC, coupled to receive the input signal and to provide the N-bit digital value as output; an additional analog-to-digital converter, ADC, coupled to receive a plurality of time-interleaved currents generated on the basis of the residue current from the MDAC and having an M-bit digital value as output signal; and wherein the additional ADC comprises: an array of sub analog-to-digital converters, sub-ADC, each sub-ADC (430,432,434) of the array of sub-ADCs comprising a current-controlled ring oscillator coupled to receive a current from the plurality of time-interleaved currents and convert it into a digital value; a combiner coupled to receive the digital value from each of the sub-ADCs (430,432,434) and provide the M-bit digital value; calibration logic coupled to receive the N-bit digital values from the MDAC and M-bit digital values from the additional ADC as inputs to provide correction values as outputs, wherein the correction values for each operational region (562, 564) determined by the N-bit digital values are calculated based upon differences between expected range values of each operational region and actual range values of each operational region, the actual range values being determined from the differences between recorded maximum values and minimum values of the M-bit digital values, wherein the expected range values are predetermined values; an array of sub analog-to-digital converters, sub-ADC, each sub-ADC (430,432,434) of the array of sub-ADCs comprising a current-controlled ring oscillator coupled to receive a current from the plurality of time-interleaved currents and convert it into a digital value; a combiner coupled to receive the digital value from each of the sub-ADCs (430,432,434) and provide the M-bit digital value; calibration logic coupled to receive the N-bit digital values from the MDAC and M-bit digital values from the additional ADC as inputs to provide correction values as outputs, wherein the correction values for each operational region (562, 564) determined by the N-bit digital values are calculated based upon differences between expected range values of each operational region and actual range values of each operational region, the actual range values being determined from the differences between recorded maximum values and minimum values of the M-bit digital values, wherein the expected range values are predetermined values;