A method for combining instructions, performed by a compiler, the method comprising: obtaining a plurality of first instructions, wherein each first instruction performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST, Load/Store, operation, a SMP, sampling, operation and a complicated mathematics operation; combining the first instructions as a combined result according to data dependencies between the first instructions; obtaining a second instruction, wherein the second instruction is used for sending data from a CR, Common Register, or a CB, Constant Buffer, to another CR or a post-processing unit; and combining the combined result for the first instructions with the second instruction as the combined instruction, and sending the combined instruction to a SP, Stream Processor, wherein the SP comprises: a DF, Data Fetch, unit; a bypass-pipe, coupled to a CR, Common Register, a CB, Constant Buffer, and the DF unit; and a main-pipe, coupled to the DF unit and the bypass-pipe, comprising an ALG, Algorithm, unit, a comparison/logic unit and a post-PROC, Process, unit, wherein the ALG, comparison/logic and post-PROC units (140, 150, 160) are coupled in series and each of the ALG, comparison/logic and post-PROC units (140, 150, 160) is coupled to the bypass-pipe; a first computation unit of the ALG unit is coupled to the bypass-pipe and the DF unit for obtaining operands from the bypass-pipe and/or the DF unit; a second computation unit of the comparison/logic unit is coupled to the bypass-pipe and a first output of the first computation unit for obtaining operands from the bypass-pipe and/or the first output; a third computation unit of the post-PROC unit is coupled to the bypass-pipe, the first output of the first computation unit and a second output of the second computation unit for obtaining operands from the bypass-pipe, the first output and/or the second output; and a determination unit of the post-PROC unit writes the data to the CR or outputs an operation result to the post-processing unit according to a result generated by the comparison/logic unit. obtaining a plurality of first instructions, wherein each first instruction performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST, Load/Store, operation, a SMP, sampling, operation and a complicated mathematics operation; combining the first instructions as a combined result according to data dependencies between the first instructions; obtaining a second instruction, wherein the second instruction is used for sending data from a CR, Common Register, or a CB, Constant Buffer, to another CR or a post-processing unit; and combining the combined result for the first instructions with the second instruction as the combined instruction, and sending the combined instruction to a SP, Stream Processor, wherein the SP comprises: a DF, Data Fetch, unit; a bypass-pipe, coupled to a CR, Common Register, a CB, Constant Buffer, and the DF unit; and a main-pipe, coupled to the DF unit and the bypass-pipe, comprising an ALG, Algorithm, unit, a comparison/logic unit and a post-PROC, Process, unit, wherein the ALG, comparison/logic and post-PROC units (140, 150, 160) are coupled in series and each of the ALG, comparison/logic and post-PROC units (140, 150, 160) is coupled to the bypass-pipe; a first computation unit of the ALG unit is coupled to the bypass-pipe and the DF unit for obtaining operands from the bypass-pipe and/or the DF unit; a second computation unit of the comparison/logic unit is coupled to the bypass-pipe and a first output of the first computation unit for obtaining operands from the bypass-pipe and/or the first output; a third computation unit of the post-PROC unit is coupled to the bypass-pipe, the first output of the first computation unit and a second output of the second computation unit for obtaining operands from the bypass-pipe, the first output and/or the second output; and a determination unit of the post-PROC unit writes the data to the CR or outputs an operation result to the post-processing unit according to a result generated by the comparison/logic unit. a DF, Data Fetch, unit; a bypass-pipe, coupled to a CR, Common Register, a CB, Constant Buffer, and the DF unit; and a main-pipe, coupled to the DF unit and the bypass-pipe, comprising an ALG, Algorithm, unit, a comparison/logic unit and a post-PROC, Process, unit, wherein the ALG, comparison/logic and post-PROC units (140, 150, 160) are coupled in series and each of the ALG, comparison/logic and post-PROC units (140, 150, 160) is coupled to the bypass-pipe; a first computation unit of the ALG unit is coupled to the bypass-pipe and the DF unit for obtaining operands from the bypass-pipe and/or the DF unit; a second computation unit of the comparison/logic unit is coupled to the bypass-pipe and a first output of the first computation unit for obtaining operands from the bypass-pipe and/or the first output; a third computation unit of the post-PROC unit is coupled to the bypass-pipe, the first output of the first computation unit and a second output of the second computation unit for obtaining operands from the bypass-pipe, the first output and/or the second output; and a determination unit of the post-PROC unit writes the data to the CR or outputs an operation result to the post-processing unit according to a result generated by the comparison/logic unit.