An apparatus for data transmission, comprising: a front-end processor, a transmission controller and a back-end processor; the front-end processor is connected, through the transmission controller, with the back-end processor; the front-end processor comprises a direct memory access, DMA, controller, a transmission scheduler, a memory controller and a plurality of transmission buffers (1014, 1015); wherein the DMA controller is respectively connected with the transmission controller, the memory controller, respective transmission buffers (1014, 1015) and the transmission scheduler, the transmission controller and the transmission scheduler are respectively connected with the respective transmission buffers (1014, 1015); the DMA controller is configured to: receive a request for data transmission sent by the back-end processor; send, according to the request for data transmission, a data reading instruction to the memory controller; and receive read data and send the read data to a respective one of the transmission buffers (1014, 1015); the memory controller is configured to: control, according to the data reading instruction, a memory to read data; and send the read data to the DMA controller; the transmission scheduler is configured to: control the plurality of the transmission buffers (1014, 1015) to write data sent by the DMA controller, and control the plurality of the transmission buffers (1014, 1015) to read data and transmit, through the transmission controller, the data to the back-end processor; characterized in that: the transmission scheduler comprises an entry scheduler and an exit scheduler; the entry scheduler is configured to control, according to an entry scheduling state and writing token information, the transmission buffer with writing authority to write data; the exit scheduler is configured to control, according to an exit scheduling state and reading token information, the transmission buffer with reading authority to read data. the front-end processor is connected, through the transmission controller, with the back-end processor; the front-end processor comprises a direct memory access, DMA, controller, a transmission scheduler, a memory controller and a plurality of transmission buffers (1014, 1015); wherein the DMA controller is respectively connected with the transmission controller, the memory controller, respective transmission buffers (1014, 1015) and the transmission scheduler, the transmission controller and the transmission scheduler are respectively connected with the respective transmission buffers (1014, 1015); the DMA controller is configured to: receive a request for data transmission sent by the back-end processor; send, according to the request for data transmission, a data reading instruction to the memory controller; and receive read data and send the read data to a respective one of the transmission buffers (1014, 1015); the memory controller is configured to: control, according to the data reading instruction, a memory to read data; and send the read data to the DMA controller; the transmission scheduler is configured to: control the plurality of the transmission buffers (1014, 1015) to write data sent by the DMA controller, and control the plurality of the transmission buffers (1014, 1015) to read data and transmit, through the transmission controller, the data to the back-end processor; characterized in that: the transmission scheduler comprises an entry scheduler and an exit scheduler; the entry scheduler is configured to control, according to an entry scheduling state and writing token information, the transmission buffer with writing authority to write data; the exit scheduler is configured to control, according to an exit scheduling state and reading token information, the transmission buffer with reading authority to read data. the transmission scheduler comprises an entry scheduler and an exit scheduler; the entry scheduler is configured to control, according to an entry scheduling state and writing token information, the transmission buffer with writing authority to write data; the exit scheduler is configured to control, according to an exit scheduling state and reading token information, the transmission buffer with reading authority to read data.