An apparatus comprising: processing circuitry to execute instructions, the processing circuitry being operable at a plurality of exception levels (ELO, EL1, EL2, EL3) in which exceptions are taken, each exception level having different software execution privilege; a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain access ranges of pointers used in operations performed by the processing circuitry when executing said instructions; and capability configuration storage to identify capability configuration information for each of said plurality of exception levels, for each exception level the capability configuration information identifying at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by said capabilities, wherein: during a switch operation from a source exception level to a destination exception level, the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing circuitry is managed during the switch operation; and the processing circuitry is arranged to use an exception mechanism to transition between said plurality of exception levels, and when exception entry causes the switch operation from the source exception level to the destination exception level, the processing circuitry is arranged to determine return address information to be preserved for the source exception level with reference to the capability configuration information pertaining to the source exception level. processing circuitry to execute instructions, the processing circuitry being operable at a plurality of exception levels (ELO, EL1, EL2, EL3) in which exceptions are taken, each exception level having different software execution privilege; a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain access ranges of pointers used in operations performed by the processing circuitry when executing said instructions; and capability configuration storage to identify capability configuration information for each of said plurality of exception levels, for each exception level the capability configuration information identifying at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by said capabilities, wherein: during a switch operation from a source exception level to a destination exception level, the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing circuitry is managed during the switch operation; and the processing circuitry is arranged to use an exception mechanism to transition between said plurality of exception levels, and when exception entry causes the switch operation from the source exception level to the destination exception level, the processing circuitry is arranged to determine return address information to be preserved for the source exception level with reference to the capability configuration information pertaining to the source exception level. during a switch operation from a source exception level to a destination exception level, the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing circuitry is managed during the switch operation; and the processing circuitry is arranged to use an exception mechanism to transition between said plurality of exception levels, and when exception entry causes the switch operation from the source exception level to the destination exception level, the processing circuitry is arranged to determine return address information to be preserved for the source exception level with reference to the capability configuration information pertaining to the source exception level.