An electronic device comprising: a semiconductor device including a substrate having: a circuit portion provided on a face and configured to use high frequency waves within a range of 60 GHz to 80 GHz and a metal bump provided on this face which electrically couples to the circuit portion, and a conductive layer provided directly on another face of the substrate that is an opposite side of the substrate to the face; and a package including a package substrate having a wiring pattern and a chassis covered with metal, the package substrate having the semiconductor device mounted face down thereon, the metal bump being coupled to the wiring pattern of the package substrate and the chassis facing the conductive layer, wherein: the substrate is one of a GaAs substrate, a Si substrate, a SiC substrate, a sapphire substrate and a GaN substrate; the conductive layer is one of a NiCr layer with a thickness of 4 nm to 70 nm, a TaN layer with a thickness of 10 nm to 200 nm, an ITO layer with a thickness of 10 nm to 160 nm, in a case where the substrate is the GaAs substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 65 nm, a TaN layer with a thickness of 10 nm to 180 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the Si substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 63 nm, a TaN layer with a thickness of 7 nm to 160 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the SiC substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 63 nm, a TaN layer with a thickness of 7 nm to 160 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the sapphire substrate; and the conductive layer is one of a NiCr layer with a thickness of 3 nm to 68 nm, a TaN layer with a thickness of 10 nm to 180 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the GaN substrate, and wherein the conductive layer has a resistivity of 1.0 X 10 -6 Ωm to 2.5 X 10 -6 Ωm. a semiconductor device including a substrate having: a circuit portion provided on a face and configured to use high frequency waves within a range of 60 GHz to 80 GHz and a metal bump provided on this face which electrically couples to the circuit portion, and a conductive layer provided directly on another face of the substrate that is an opposite side of the substrate to the face; and a package including a package substrate having a wiring pattern and a chassis covered with metal, the package substrate having the semiconductor device mounted face down thereon, the metal bump being coupled to the wiring pattern of the package substrate and the chassis facing the conductive layer, wherein: the substrate is one of a GaAs substrate, a Si substrate, a SiC substrate, a sapphire substrate and a GaN substrate; the conductive layer is one of a NiCr layer with a thickness of 4 nm to 70 nm, a TaN layer with a thickness of 10 nm to 200 nm, an ITO layer with a thickness of 10 nm to 160 nm, in a case where the substrate is the GaAs substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 65 nm, a TaN layer with a thickness of 10 nm to 180 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the Si substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 63 nm, a TaN layer with a thickness of 7 nm to 160 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the SiC substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 63 nm, a TaN layer with a thickness of 7 nm to 160 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the sapphire substrate; and the conductive layer is one of a NiCr layer with a thickness of 3 nm to 68 nm, a TaN layer with a thickness of 10 nm to 180 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the GaN substrate, and wherein the conductive layer has a resistivity of 1.0 X 10 -6 Ωm to 2.5 X 10 -6 Ωm. the substrate is one of a GaAs substrate, a Si substrate, a SiC substrate, a sapphire substrate and a GaN substrate; the conductive layer is one of a NiCr layer with a thickness of 4 nm to 70 nm, a TaN layer with a thickness of 10 nm to 200 nm, an ITO layer with a thickness of 10 nm to 160 nm, in a case where the substrate is the GaAs substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 65 nm, a TaN layer with a thickness of 10 nm to 180 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the Si substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 63 nm, a TaN layer with a thickness of 7 nm to 160 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the SiC substrate; the conductive layer is one of a NiCr layer with a thickness of 3 nm to 63 nm, a TaN layer with a thickness of 7 nm to 160 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the sapphire substrate; and the conductive layer is one of a NiCr layer with a thickness of 3 nm to 68 nm, a TaN layer with a thickness of 10 nm to 180 nm, an ITO layer with a thickness of 5 nm to 140 nm, in a case where the substrate is the GaN substrate, and wherein the conductive layer has a resistivity of 1.0 X 10 -6 Ωm to 2.5 X 10 -6 Ωm.