A frequency drift detector comprising: a frequency-to-voltage converter, FVC, arranged to receive a reference frequency signal from a crystal oscillator and configured to generate an FVC output voltage; a voltage regulator arranged to output at least one regulated voltage, wherein the at least one regulated voltage is representative of a known frequency drift level of the crystal oscillator; and a voltage comparator coupled to an output of the FVC and an output of the voltage regulator and arranged to compare the FVC output voltage and the at least one regulated voltage and generate an error signal in response to determining that the FVC output voltage exceeds the known frequency drift level indicated by the at least one regulated voltage such that the error signal corresponds to an excessive frequency drift of the crystal oscillator, wherein the FVC comprises a phase locked loop, PLL, arranged to receive the reference frequency signal; wherein the PLL comprises a phase detector (510, 610) configured to compare the reference frequency signal (407, 507, 607) to a feedback signal (545, 645) and output a control signal (515, 615) based on the comparison; a loop filter (520, 620) configured to filter the control signal (515, 615); a voltage controlled oscillator, VCO (530, 630), configured to generate an output radio frequency signal in response to the filtered control signal (525, 625); a feedback path configured to generate the feedback signal (545, 645) based on the output radio frequency signal; and a low pass filter (550, 650) arranged to filter the filtered control signal (525, 625) in order to generate the FVC output voltage (455, 555, 655), wherein the PLL is operably coupled to a temperature compensation circuit (580, 680, 685), such that the temperature compensation circuit (580, 680, 685) is coupled to one or more of: the VCO (530, 630), and the temperature compensation circuit (580, 680) is arranged to apply a temperature compensation signal to the VCO such that, in response thereto, the filtered control signal (525, 625) is constant over temperature; and a programmable divider in the feedback path of the PLL, and the temperature compensation circuit is arranged to apply a temperature compensation signal to the programmable divider such that, in response thereto, the filtered control signal (525, 625) is constant over temperature. a frequency-to-voltage converter, FVC, arranged to receive a reference frequency signal from a crystal oscillator and configured to generate an FVC output voltage; a voltage regulator arranged to output at least one regulated voltage, wherein the at least one regulated voltage is representative of a known frequency drift level of the crystal oscillator; and a voltage comparator coupled to an output of the FVC and an output of the voltage regulator and arranged to compare the FVC output voltage and the at least one regulated voltage and generate an error signal in response to determining that the FVC output voltage exceeds the known frequency drift level indicated by the at least one regulated voltage such that the error signal corresponds to an excessive frequency drift of the crystal oscillator, wherein the FVC comprises a phase locked loop, PLL, arranged to receive the reference frequency signal; wherein the PLL comprises a phase detector (510, 610) configured to compare the reference frequency signal (407, 507, 607) to a feedback signal (545, 645) and output a control signal (515, 615) based on the comparison; a loop filter (520, 620) configured to filter the control signal (515, 615); a voltage controlled oscillator, VCO (530, 630), configured to generate an output radio frequency signal in response to the filtered control signal (525, 625); a feedback path configured to generate the feedback signal (545, 645) based on the output radio frequency signal; and a low pass filter (550, 650) arranged to filter the filtered control signal (525, 625) in order to generate the FVC output voltage (455, 555, 655), wherein the PLL is operably coupled to a temperature compensation circuit (580, 680, 685), such that the temperature compensation circuit (580, 680, 685) is coupled to one or more of: the VCO (530, 630), and the temperature compensation circuit (580, 680) is arranged to apply a temperature compensation signal to the VCO such that, in response thereto, the filtered control signal (525, 625) is constant over temperature; and a programmable divider in the feedback path of the PLL, and the temperature compensation circuit is arranged to apply a temperature compensation signal to the programmable divider such that, in response thereto, the filtered control signal (525, 625) is constant over temperature. the VCO (530, 630), and the temperature compensation circuit (580, 680) is arranged to apply a temperature compensation signal to the VCO such that, in response thereto, the filtered control signal (525, 625) is constant over temperature; and a programmable divider in the feedback path of the PLL, and the temperature compensation circuit is arranged to apply a temperature compensation signal to the programmable divider such that, in response thereto, the filtered control signal (525, 625) is constant over temperature.