A random access memory cache memory controller, comprising: a first interface for receiving memory access requests; a second interface for sending cache access requests to a RAM cache memory device; and control logic; wherein in response to receiving a memory access request, the control logic is configured to: generate a cache tag access request based on the memory access request; generate a cache data access request different from the cache tag access request based on the memory access request; store a unique identifier in each of the cache tag access request and the cache data access request, wherein the unique identifier specifies each of the cache tag access request and the cache data access request is generated from a same memory access request; send the cache data access request to the RAM cache memory device after information generated by processing the cache tag request is available; send the cache tag access request to the RAM cache memory device via the second interface, wherein the cache tag access request is sent to the memory device before the data access request is sent; and schedule sending the cache data access request to the RAM cache memory device based on information generated by processing the cache tag access request, wherein scheduling sending the cache data access request comprises canceling sending of the cache data access request to the RAM cache memory device responsive to determining a tag miss. a first interface for receiving memory access requests; a second interface for sending cache access requests to a RAM cache memory device; and control logic; wherein in response to receiving a memory access request, the control logic is configured to: generate a cache tag access request based on the memory access request; generate a cache data access request different from the cache tag access request based on the memory access request; store a unique identifier in each of the cache tag access request and the cache data access request, wherein the unique identifier specifies each of the cache tag access request and the cache data access request is generated from a same memory access request; send the cache data access request to the RAM cache memory device after information generated by processing the cache tag request is available; send the cache tag access request to the RAM cache memory device via the second interface, wherein the cache tag access request is sent to the memory device before the data access request is sent; and schedule sending the cache data access request to the RAM cache memory device based on information generated by processing the cache tag access request, wherein scheduling sending the cache data access request comprises canceling sending of the cache data access request to the RAM cache memory device responsive to determining a tag miss. generate a cache tag access request based on the memory access request; generate a cache data access request different from the cache tag access request based on the memory access request; store a unique identifier in each of the cache tag access request and the cache data access request, wherein the unique identifier specifies each of the cache tag access request and the cache data access request is generated from a same memory access request; send the cache data access request to the RAM cache memory device after information generated by processing the cache tag request is available; send the cache tag access request to the RAM cache memory device via the second interface, wherein the cache tag access request is sent to the memory device before the data access request is sent; and schedule sending the cache data access request to the RAM cache memory device based on information generated by processing the cache tag access request, wherein scheduling sending the cache data access request comprises canceling sending of the cache data access request to the RAM cache memory device responsive to determining a tag miss.