An apparatus for recovering clock and data from an M-level signal of a receiver in a transmission system, M being a positive integer and a power of two and at least 4, the apparatus comprising: - an M-level log 2 -bit analog-to-digital converter, ADC, connected at an input of the apparatus, the M-level log 2 -bit ADC being adapted to output an outer level bit, OLB, corresponding to a polarity (+, -) of an amplitude difference between an analog data of the M-level signal and a closest value in the range of voltage threshold from 2-M to M-2 and adapted to output the most significant bit, MSB, corresponding to a polarity (+, -) of an amplitude difference between the analog data of the M-level signal and a voltage threshold equal to zero; - a first voltage comparator connected at the input of the apparatus, the first voltage comparator being adapted to compare a first amplitude difference corresponding to an amplitude difference between the analog data and a first controllable threshold value (X up), wherein the first controllable threshold value (X up) has an amplitude equal to a sum of M-1 and a first quantization value (Δ 1); - a second voltage comparator connected at the input of the apparatus, the second comparator being adapted to compare a second amplitude difference corresponding to an amplitude difference between the analog data and a second controllable threshold value (X down), wherein the second controllable threshold value (X down) has an amplitude equal to a sum of 1-M and a second quantization value (Δ 2); and - a three-valued logic unit adapted to generate a phase detection output, through a truth table, which outputs a truth value amongst -1, 0 and +1, based on a polarity (+, -) of the MSB, a polarity of the OLB, and a polarity of an amplitude difference to be selected amongst the first and second amplitude differences, - a filter adapted to filter the truth value (0, ±1) output from the three-value logic unit; and - an oscillator adapted to receive the filtered truth value (0, ±1) and generate a clock signal to be provided to the M-level log 2 -bit ADC, wherein: - two consecutive analog data (X 1, X 2) of the M-level signal are sampled at a distance of one symbol period with respect to each other. - an M-level log 2 -bit analog-to-digital converter, ADC, connected at an input of the apparatus, the M-level log 2 -bit ADC being adapted to output an outer level bit, OLB, corresponding to a polarity (+, -) of an amplitude difference between an analog data of the M-level signal and a closest value in the range of voltage threshold from 2-M to M-2 and adapted to output the most significant bit, MSB, corresponding to a polarity (+, -) of an amplitude difference between the analog data of the M-level signal and a voltage threshold equal to zero; - a first voltage comparator connected at the input of the apparatus, the first voltage comparator being adapted to compare a first amplitude difference corresponding to an amplitude difference between the analog data and a first controllable threshold value (X up), wherein the first controllable threshold value (X up) has an amplitude equal to a sum of M-1 and a first quantization value (Δ 1); - a second voltage comparator connected at the input of the apparatus, the second comparator being adapted to compare a second amplitude difference corresponding to an amplitude difference between the analog data and a second controllable threshold value (X down), wherein the second controllable threshold value (X down) has an amplitude equal to a sum of 1-M and a second quantization value (Δ 2); and - a three-valued logic unit adapted to generate a phase detection output, through a truth table, which outputs a truth value amongst -1, 0 and +1, based on a polarity (+, -) of the MSB, a polarity of the OLB, and a polarity of an amplitude difference to be selected amongst the first and second amplitude differences, - a filter adapted to filter the truth value (0, ±1) output from the three-value logic unit; and - an oscillator adapted to receive the filtered truth value (0, ±1) and generate a clock signal to be provided to the M-level log 2 -bit ADC, - two consecutive analog data (X 1, X 2) of the M-level signal are sampled at a distance of one symbol period with respect to each other.