An active cable comprising: a cable (507, 607); a first plug (500, 600) connected to a first end of the cable (507, 607) and comprising: a first clock and data recovery circuit (510, 610, 615) to retime signals received at an input of the first plug (500, 600); a second clock and data recovery circuit (530, 630, 635) to retime signals received from the cable (507, 607); and a first microcontroller (520, 620) to configure the first clock and data recovery circuit (510, 610, 615) and the second clock and data recovery circuit (530, 630, 635); and a second plug (505, 605) connected to a second end of the cable (507, 607) and comprising: a third clock and data recovery circuit (540, 640, 645) to retime signals received at an input of the second plug (505, 605); a fourth clock and data recovery circuit (560, 660, 665) to retime signals received from the cable (507, 607); and a second microcontroller (550, 650) to configure the third clock and data recovery circuit (540, 640, 645) and the fourth clock and data recovery circuit (560, 660, 665), wherein the cable is configured to connect an output of the first clock and data recovery circuit (510, 610, 615) to an input of the fourth clock and data recovery circuit (560, 660, 665) and an output of the third clock and data recovery circuit (540, 640, 645) to an input of the second clock and data recovery circuit (530, 630, 635), characterised in that the first microcontroller (520, 620) is adapted to configure an output of the first clock and data recovery circuit (510, 610, 615) to couple to an input of the second clock and data recovery circuit (530, 630, 635), and to configure an output of the second clock and data recovery circuit (530, 630, 635) to couple to an input of the first clock and data recovery circuit (510, 610, 615). a cable (507, 607); a first plug (500, 600) connected to a first end of the cable (507, 607) and comprising: a first clock and data recovery circuit (510, 610, 615) to retime signals received at an input of the first plug (500, 600); a second clock and data recovery circuit (530, 630, 635) to retime signals received from the cable (507, 607); and a first microcontroller (520, 620) to configure the first clock and data recovery circuit (510, 610, 615) and the second clock and data recovery circuit (530, 630, 635); and a first clock and data recovery circuit (510, 610, 615) to retime signals received at an input of the first plug (500, 600); a second clock and data recovery circuit (530, 630, 635) to retime signals received from the cable (507, 607); and a first microcontroller (520, 620) to configure the first clock and data recovery circuit (510, 610, 615) and the second clock and data recovery circuit (530, 630, 635); and a second plug (505, 605) connected to a second end of the cable (507, 607) and comprising: a third clock and data recovery circuit (540, 640, 645) to retime signals received at an input of the second plug (505, 605); a fourth clock and data recovery circuit (560, 660, 665) to retime signals received from the cable (507, 607); and a second microcontroller (550, 650) to configure the third clock and data recovery circuit (540, 640, 645) and the fourth clock and data recovery circuit (560, 660, 665), wherein the cable is configured to connect an output of the first clock and data recovery circuit (510, 610, 615) to an input of the fourth clock and data recovery circuit (560, 660, 665) and an output of the third clock and data recovery circuit (540, 640, 645) to an input of the second clock and data recovery circuit (530, 630, 635), characterised in that the first microcontroller (520, 620) is adapted to configure an output of the first clock and data recovery circuit (510, 610, 615) to couple to an input of the second clock and data recovery circuit (530, 630, 635), and to configure an output of the second clock and data recovery circuit (530, 630, 635) to couple to an input of the first clock and data recovery circuit (510, 610, 615). a third clock and data recovery circuit (540, 640, 645) to retime signals received at an input of the second plug (505, 605); a fourth clock and data recovery circuit (560, 660, 665) to retime signals received from the cable (507, 607); and a second microcontroller (550, 650) to configure the third clock and data recovery circuit (540, 640, 645) and the fourth clock and data recovery circuit (560, 660, 665), wherein the cable is configured to connect an output of the first clock and data recovery circuit (510, 610, 615) to an input of the fourth clock and data recovery circuit (560, 660, 665) and an output of the third clock and data recovery circuit (540, 640, 645) to an input of the second clock and data recovery circuit (530, 630, 635), characterised in that the first microcontroller (520, 620) is adapted to configure an output of the first clock and data recovery circuit (510, 610, 615) to couple to an input of the second clock and data recovery circuit (530, 630, 635), and to configure an output of the second clock and data recovery circuit (530, 630, 635) to couple to an input of the first clock and data recovery circuit (510, 610, 615).