Data processing apparatus comprising: processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry(60, 80) to execute instructions decoded by the instruction decoder circuitry; wherein: the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive; and the instruction decoder circuitry is responsive to the propagation instruction to control the instruction processing circuitry to respond to initial states of the set of predicate flags applicable to the current data vector, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are active, the derived predicate flags in the set applicable to the current data vector are derived from their respective initial states. instruction decoder circuitry to decode program instructions; and instruction processing circuitry(60, 80) to execute instructions decoded by the instruction decoder circuitry; wherein: the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive; and the instruction decoder circuitry is responsive to the propagation instruction to control the instruction processing circuitry to respond to initial states of the set of predicate flags applicable to the current data vector, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are active, the derived predicate flags in the set applicable to the current data vector are derived from their respective initial states. the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive; and the instruction decoder circuitry is responsive to the propagation instruction to control the instruction processing circuitry to respond to initial states of the set of predicate flags applicable to the current data vector, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are active, the derived predicate flags in the set applicable to the current data vector are derived from their respective initial states.