A power semiconductor device comprising a semiconductor wafer having a first main side and a second main side opposite to the first main side, the semiconductor wafer comprising a plurality of parallel thyristor cells, wherein each thyristor cell comprises in an order from the first main side to the second main side: (a) a cathode electrode and a gate electrode arranged on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the first base layer and forms a first p-n junction between the first base layer and the cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer; wherein the gate electrode forms an ohmic contact with the first base layer; and an anode electrode is arranged on the second main side and forms an ohmic contact with the anode layer; wherein the gate electrodes of the plurality of thyristor cells form a honeycombed gate design comprising multiple hexagons each comprising six struts, wherein the cathode regions are of hexagonal shape, and the cathode layers comprise cathode short areas of the second conductivity type connecting the cathode electrodes with the first base layers, wherein the cathode short areas are of polygonal shape or circular shape or stripe shape and the cathode short areas are placed along a hexagonal gate-cathode boundary within the hexagonal cathode region. a plurality of parallel thyristor cells, wherein each thyristor cell comprises in an order from the first main side to the second main side: (a) a cathode electrode and a gate electrode arranged on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the first base layer and forms a first p-n junction between the first base layer and the cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer; (a) a cathode electrode and a gate electrode arranged on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the first base layer and forms a first p-n junction between the first base layer and the cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer; wherein the gate electrode forms an ohmic contact with the first base layer; and an anode electrode is arranged on the second main side and forms an ohmic contact with the anode layer; wherein the gate electrodes of the plurality of thyristor cells form a honeycombed gate design comprising multiple hexagons each comprising six struts, wherein the cathode regions are of hexagonal shape, and the cathode layers comprise cathode short areas of the second conductivity type connecting the cathode electrodes with the first base layers, wherein the cathode short areas are of polygonal shape or circular shape or stripe shape and the cathode short areas are placed along a hexagonal gate-cathode boundary within the hexagonal cathode region.