A semiconductor device comprising: first and second sets of transistors (100, 200) arranged on a substrate, each set comprising a pass transistor (110, 210) and a stacked complementary transistor pair (120, 220) of a lower transistor (122, 222) and an upper transistor (124, 224), wherein each transistor of the first set comprises a semiconductor channel (110c, 122c, 124c) extending between respective source and drain regions along a horizontal first fin track, and each transistor of the second set comprises a semiconductor channel (210c, 222c, 224c) extending between respective source and drain regions along a second fin track parallel to the first fin track, and wherein the semiconductor channels (110c, 210c) of said pass transistors (110, 210) and the semiconductor channels (122c, 222c) of said lower transistors (122, 222) are arranged at a first level above the substrate and the semiconductor channels (124c, 224c) of said upper transistors (124, 224) are arranged at a second level above the first level, a first tall gate electrode forming a common gate for the semiconductor channels (122c, 124c) of the first complementary transistor pair and arranged along a horizontal first gate track transverse to said fin tracks (FT1, FT2), and a first short gate electrode forming a gate for the semiconductor channel of the first pass transistor and arranged along a second gate track parallel to the first gate track, a second tall gate electrode forming a common gate for the semiconductor channels (222c, 224c) of the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the semiconductor channel of the second pass transistor and arranged along the first gate track, first and second contact arrangements (150, 250) arranged between the first and second gate tracks (GT1, GT2) and forming a common drain contact for the transistors of the first set and the second set, respectively, a first cross-couple contact extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, the first cross-couple contact comprising a first end arranged in contact with the first tall gate electrode at a first interface, a second end arranged in contact with the second contact arrangement at a second interface, and a body extending from the first interface to the second interface in a horizontal path running above the second short gate electrode, and a second cross-couple contact extending horizontally between and interconnecting the second tall gate electrode and the first contact arrangement. first and second sets of transistors (100, 200) arranged on a substrate, each set comprising a pass transistor (110, 210) and a stacked complementary transistor pair (120, 220) of a lower transistor (122, 222) and an upper transistor (124, 224), wherein each transistor of the first set comprises a semiconductor channel (110c, 122c, 124c) extending between respective source and drain regions along a horizontal first fin track, and each transistor of the second set comprises a semiconductor channel (210c, 222c, 224c) extending between respective source and drain regions along a second fin track parallel to the first fin track, and wherein the semiconductor channels (110c, 210c) of said pass transistors (110, 210) and the semiconductor channels (122c, 222c) of said lower transistors (122, 222) are arranged at a first level above the substrate and the semiconductor channels (124c, 224c) of said upper transistors (124, 224) are arranged at a second level above the first level, a first tall gate electrode forming a common gate for the semiconductor channels (122c, 124c) of the first complementary transistor pair and arranged along a horizontal first gate track transverse to said fin tracks (FT1, FT2), and a first short gate electrode forming a gate for the semiconductor channel of the first pass transistor and arranged along a second gate track parallel to the first gate track, a second tall gate electrode forming a common gate for the semiconductor channels (222c, 224c) of the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the semiconductor channel of the second pass transistor and arranged along the first gate track, first and second contact arrangements (150, 250) arranged between the first and second gate tracks (GT1, GT2) and forming a common drain contact for the transistors of the first set and the second set, respectively, a first cross-couple contact extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, the first cross-couple contact comprising a first end arranged in contact with the first tall gate electrode at a first interface, a second end arranged in contact with the second contact arrangement at a second interface, and a body extending from the first interface to the second interface in a horizontal path running above the second short gate electrode, and a second cross-couple contact extending horizontally between and interconnecting the second tall gate electrode and the first contact arrangement.