A light-emitting device package comprising: a substrate having a chip-mounting region; first and second wiring layers disposed on the substrate around the chip-mounting region so as to be spaced apart from each other; and a plurality of light-emitting chips (10-1 to 10-6) disposed on the chip-mounting region, wherein the first wiring layer includes a first wiring pattern disposed at one region with respect to a reference line and having a first concave portion, and a first extension pattern extending from the first wiring pattern to an opposite region with respect to the reference line, the second wiring layer includes a second wiring pattern disposed at the opposite region with respect to the reference line and having a second concave portion, and a second extension pattern extending from the second wiring pattern to the one region with respect to the reference line, wherein the reference line is a straight line passing through a center of the chip-mounting region, characterised in that, the first extension pattern includes a first connection portion connected to one end of the first concave portion, and a first extension portion connected to the first connection portion and having a shape of a curved line, the curved line being concave in a direction opposite the first concave portion, and the second extension pattern includes a second connection portion connected to one end of the second concave portion, and a second extension portion connected to the second connection portion and having a shape of a curved line, the curved line being concave in a direction opposite the second concave portion. a substrate having a chip-mounting region; first and second wiring layers disposed on the substrate around the chip-mounting region so as to be spaced apart from each other; and a plurality of light-emitting chips (10-1 to 10-6) disposed on the chip-mounting region, wherein the first wiring layer includes a first wiring pattern disposed at one region with respect to a reference line and having a first concave portion, and a first extension pattern extending from the first wiring pattern to an opposite region with respect to the reference line, the second wiring layer includes a second wiring pattern disposed at the opposite region with respect to the reference line and having a second concave portion, and a second extension pattern extending from the second wiring pattern to the one region with respect to the reference line, wherein the reference line is a straight line passing through a center of the chip-mounting region, characterised in that, the first extension pattern includes a first connection portion connected to one end of the first concave portion, and a first extension portion connected to the first connection portion and having a shape of a curved line, the curved line being concave in a direction opposite the first concave portion, and the second extension pattern includes a second connection portion connected to one end of the second concave portion, and a second extension portion connected to the second connection portion and having a shape of a curved line, the curved line being concave in a direction opposite the second concave portion.