A method for detecting one or more errors in at least one of a global reference clock signal (Sample Clock Pulse), a pulse width modulated test signal generation source and a data transport system which sends controlling signals for use with an analogue to digital converter circuit, wherein the analogue to digital converter circuit receives a first analogue input signal, the global reference clock signal and a first unique pulse width modulated test signal and includes cooperating analogue circuit elements, the method comprising the steps of: digitally simulating said analogue to digital converter circuit using a digitally simulated circuit, the digitally simulated circuit comprising digital circuit components (2303 - 2309) which provide digital equivalents of the cooperating analogue circuit elements, wherein the digitally simulated circuit is arranged to mimic the behaviour of the analogue to digital converter circuit and to be uninfluenced by external analogue circuitry or connections, wherein the digitally simulated circuit is arranged to simulate reception of a second analogue input signal, and is further arranged to be connected to the data transport system to receive a second uniquely phased pulse width modulated test signal (Dtest) and to receive the global reference clock signal (Sample Clock Pulse) and generate an output (Data Out) functionally dependent on the global reference clock signal (Sample Clock Pulse) and the second uniquely phased pulse width modulated test signal (Dtest); driving the digitally simulated circuit with the global reference clock signal (Sample Clock Pulse) and the second uniquely phased pulse width modulated test signal (Dtest) to provide the output (Data Out); and comparing the output (Data Out) of said digitally simulated circuit with stored reference data; and generating an error condition when the output (Data Out) of said digitally simulated circuit and said stored reference data differ by more than a predetermined threshold. digitally simulating said analogue to digital converter circuit using a digitally simulated circuit, the digitally simulated circuit comprising digital circuit components (2303 - 2309) which provide digital equivalents of the cooperating analogue circuit elements, wherein the digitally simulated circuit is arranged to mimic the behaviour of the analogue to digital converter circuit and to be uninfluenced by external analogue circuitry or connections, wherein the digitally simulated circuit is arranged to simulate reception of a second analogue input signal, and is further arranged to be connected to the data transport system to receive a second uniquely phased pulse width modulated test signal (Dtest) and to receive the global reference clock signal (Sample Clock Pulse) and generate an output (Data Out) functionally dependent on the global reference clock signal (Sample Clock Pulse) and the second uniquely phased pulse width modulated test signal (Dtest); driving the digitally simulated circuit with the global reference clock signal (Sample Clock Pulse) and the second uniquely phased pulse width modulated test signal (Dtest) to provide the output (Data Out); and comparing the output (Data Out) of said digitally simulated circuit with stored reference data; and generating an error condition when the output (Data Out) of said digitally simulated circuit and said stored reference data differ by more than a predetermined threshold.