Half-bridge electronic device, comprising in series a high level switch and a low level switch, connected at a midpoint, the half-bridge electronic device further comprising a delay generation device, the delay generation device being capable to form, from a digital input signal, - a first digital control signal (PWM-LS) the edge of which for triggering from a state 0 to a state 1 is shifted by one time out with respect to an edge for triggering from a state 0 to a state 1 of the input signal and the edge of which for triggering from a state 1 to a state 0 is not shifted with respect to the edge for triggering from a state 1 to a state 0 of the input signal, - and a second digital control signal (PWM-HS) the edge of which for triggering from a state 0 to a state 1 is shifted by the time out with respect to an edge for triggering from a state 1 to a state 0 of the input signal and the edge of which for triggering from a state 1 to a state 0 is not shifted with respect to the edge for triggering from a state 0 to a state 1 of the input signal, the low level switch and the high level being respectively controlled by a first (S LS) and a second (S HS) activation/deactivation signal, the device being characterized in that it comprises: • a first synchronization system comprising a first detection circuit configured to interpret a change, following a falling edge, of the voltage (Vm) at the midpoint, the first system being configured to generate a first digital synchronization signal (ATON-LS), activated at a state 1 by the falling edge of the voltage (Vm) at the midpoint and reset at a state 0 as the first control signal (PWM-LS) goes to a state 1; • a second synchronization system comprising a second detection circuit configured to interpret a change, following a rising edge, of the voltage (Vm) at the midpoint, the second system being configured to generate a second digital synchronization signal (ATON-HS), activated at a state 1 by the rising edge of the voltage (Vm) at the midpoint and reset at a state 0 as the second control signal (PWM-HS) goes to a state 1; • a logic gate of the OR type combining the first synchronization signal (ATON-LS) with the first control signal (PWM-LS), to form the first activation/deactivation signal (S LS); • a further logic gate of the OR type combining the second synchronization signal (ATON-HS) with the second control signal (PWM-HS), to form the second activation/deactivation signal (S HS). - a first digital control signal (PWM-LS) the edge of which for triggering from a state 0 to a state 1 is shifted by one time out with respect to an edge for triggering from a state 0 to a state 1 of the input signal and the edge of which for triggering from a state 1 to a state 0 is not shifted with respect to the edge for triggering from a state 1 to a state 0 of the input signal, - and a second digital control signal (PWM-HS) the edge of which for triggering from a state 0 to a state 1 is shifted by the time out with respect to an edge for triggering from a state 1 to a state 0 of the input signal and the edge of which for triggering from a state 1 to a state 0 is not shifted with respect to the edge for triggering from a state 0 to a state 1 of the input signal, • a first synchronization system comprising a first detection circuit configured to interpret a change, following a falling edge, of the voltage (Vm) at the midpoint, the first system being configured to generate a first digital synchronization signal (ATON-LS), activated at a state 1 by the falling edge of the voltage (Vm) at the midpoint and reset at a state 0 as the first control signal (PWM-LS) goes to a state 1; • a second synchronization system comprising a second detection circuit configured to interpret a change, following a rising edge, of the voltage (Vm) at the midpoint, the second system being configured to generate a second digital synchronization signal (ATON-HS), activated at a state 1 by the rising edge of the voltage (Vm) at the midpoint and reset at a state 0 as the second control signal (PWM-HS) goes to a state 1; • a logic gate of the OR type combining the first synchronization signal (ATON-LS) with the first control signal (PWM-LS), to form the first activation/deactivation signal (S LS); • a further logic gate of the OR type combining the second synchronization signal (ATON-HS) with the second control signal (PWM-HS), to form the second activation/deactivation signal (S HS).