A switching regulator comprising: a capacitor; a charge control circuit coupled to the capacitor, the charge control circuit for charging and discharging the capacitor; a discharge detector including an input coupled to the capacitor, the discharge detector for asserting a limiting signal in response to detecting when charge on the capacitor has discharged to a predetermined level; a power switch circuit (139, 141) coupled to receive current from a power input of the switching regulator, the power switch circuit (139, 141) coupled to receive a switching signal to control the conductivity of the power switch circuit (139, 141) for supplying an output voltage at a voltage level dependent upon a duty cycle of the switching signal, wherein an on-time of the duty cycle of the switching signal is gated by the limiting signal indicating that the capacitor has discharged to the predetermined level to reduce current flowing from the power input through the power switch circuit (139, 141) and to stop discharging of the capacitor; and a feedback circuit (151, 143) providing a current signal indicative of an amount of current from the power input through the power switch circuit (139, 141), wherein the charge control circuit discharges the capacitor by a sense current based upon the current signal, wherein the sense current is proportional to the amount of current through the power switch circuit (139, 141), wherein the charge control circuit comprises: a current source including a first terminal coupled to receive a reference voltage and a second terminal; a first transistor including a first current terminal coupled to the second terminal of the current source, a control terminal for receiving a clocking signal, and a second current terminal coupled to both a terminal of the capacitor and the input of the discharge detector; a second transistor including a first current terminal coupled to the second current terminal of the first transistor, a control terminal for receiving the clocking signal, and a second current terminal; and a current sink including a first terminal coupled to the second current terminal of the second transistor, a control terminal coupled to the feedback circuit (151, 143) to receive the current signal, and a second terminal coupled to a supply voltage terminal. a capacitor; a charge control circuit coupled to the capacitor, the charge control circuit for charging and discharging the capacitor; a discharge detector including an input coupled to the capacitor, the discharge detector for asserting a limiting signal in response to detecting when charge on the capacitor has discharged to a predetermined level; a power switch circuit (139, 141) coupled to receive current from a power input of the switching regulator, the power switch circuit (139, 141) coupled to receive a switching signal to control the conductivity of the power switch circuit (139, 141) for supplying an output voltage at a voltage level dependent upon a duty cycle of the switching signal, wherein an on-time of the duty cycle of the switching signal is gated by the limiting signal indicating that the capacitor has discharged to the predetermined level to reduce current flowing from the power input through the power switch circuit (139, 141) and to stop discharging of the capacitor; and a feedback circuit (151, 143) providing a current signal indicative of an amount of current from the power input through the power switch circuit (139, 141), wherein the charge control circuit discharges the capacitor by a sense current based upon the current signal, wherein the sense current is proportional to the amount of current through the power switch circuit (139, 141), a current source including a first terminal coupled to receive a reference voltage and a second terminal; a first transistor including a first current terminal coupled to the second terminal of the current source, a control terminal for receiving a clocking signal, and a second current terminal coupled to both a terminal of the capacitor and the input of the discharge detector; a second transistor including a first current terminal coupled to the second current terminal of the first transistor, a control terminal for receiving the clocking signal, and a second current terminal; and a current sink including a first terminal coupled to the second current terminal of the second transistor, a control terminal coupled to the feedback circuit (151, 143) to receive the current signal, and a second terminal coupled to a supply voltage terminal.