An imaging device including a plurality of pixels, each pixel (Pi,j) being formed by a photodetector associated and connected to a reading circuit, comprising: - an integration capacitance (C INT), connected to a first node (N 1) and intended to store charges originating from the photodetector, - a first reset transistor configured, when it is made conducting, to reset the integration capacitance (C INT), - at least one so-called "coupling" transistor (Mc), arranged between the photodetector and the integration capacitance (C INT) and able to, alternately, couple the photodetector to the first node (N 1) when it is made conducting, and decouple the photodetector off the first node (N 1) when it is made non-conducting, - a memorisation capacitance (C MEM) connected to a second node (N 2), - a second reset transistor configured, when it is made conducting, to reset the memorisation capacitance (C MEM), - a so-called "memorisation" switch between the integration capacitance (C INT) and the memorisation capacitance (C MEM), when it is made conducting, to connect the integration capacitance (C INT) and the memorisation capacitance (C MEM), and when it is made non-conducting, to disconnect the integration capacitance (C INT) from the memorisation capacitance (C MEM), the device further comprising: a circuit for controlling the reading circuit configured, during a measurement cycle including a phase of estimating a ratio (R = Cint/Cmem) between an estimated value of the integration capacitance and an estimated value Cmem of the memorisation capacitance: - according to a first part of said phase of estimating said ratio to make the first reset transistor and the second reset transistor conducting so as to respectively reset the integration capacitance (CINT) and the memorisation capacitance (CMEM) and to make said memorisation switch non-conducting so as to disconnect the integration capacitance (CINT) from the memorisation capacitance (CMEM) and during the first phase and during the first part, to decouple the photodetector off said first node, then, - according to a second part of said estimation phase to make the first reset transistor and the second reset transistor non-conducting and to make said memorisation switch conducting so as to connect the first node and the second node, and thus be able to assess a potential (Vf) at said second node representative of said ratio (R= Cint/Cmem). - an integration capacitance (C INT), connected to a first node (N 1) and intended to store charges originating from the photodetector, - a first reset transistor configured, when it is made conducting, to reset the integration capacitance (C INT), - at least one so-called "coupling" transistor (Mc), arranged between the photodetector and the integration capacitance (C INT) and able to, alternately, couple the photodetector to the first node (N 1) when it is made conducting, and decouple the photodetector off the first node (N 1) when it is made non-conducting, - a memorisation capacitance (C MEM) connected to a second node (N 2), - a second reset transistor configured, when it is made conducting, to reset the memorisation capacitance (C MEM), - a so-called "memorisation" switch between the integration capacitance (C INT) and the memorisation capacitance (C MEM), when it is made conducting, to connect the integration capacitance (C INT) and the memorisation capacitance (C MEM), and when it is made non-conducting, to disconnect the integration capacitance (C INT) from the memorisation capacitance (C MEM), - according to a first part of said phase of estimating said ratio to make the first reset transistor and the second reset transistor conducting so as to respectively reset the integration capacitance (CINT) and the memorisation capacitance (CMEM) and to make said memorisation switch non-conducting so as to disconnect the integration capacitance (CINT) from the memorisation capacitance (CMEM) and during the first phase and during the first part, to decouple the photodetector off said first node, then, - according to a second part of said estimation phase to make the first reset transistor and the second reset transistor non-conducting and to make said memorisation switch conducting so as to connect the first node and the second node, and thus be able to assess a potential (Vf) at said second node representative of said ratio (R= Cint/Cmem).