An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transactional memory support circuitry comprising conflict detection circuitry to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; in which: in response to a transactional compare-and-discard instruction executed within a given transaction, the transactional compare-and-discard instruction specifying a target address and a compare value, the processing circuitry is configured to: load a target data value from a memory location corresponding to the target address; set at least one condition status indication depending on a result of comparing the target data value and the compare value; and discard the target data value without adding the target address to the working set of addresses for the given transaction; and in response to a conditional branch instruction specifying a test condition, the processing circuitry is configured to perform a branch operation conditional on said at least one condition status indication meeting said test condition. processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transactional memory support circuitry comprising conflict detection circuitry to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; in which: in response to a transactional compare-and-discard instruction executed within a given transaction, the transactional compare-and-discard instruction specifying a target address and a compare value, the processing circuitry is configured to: load a target data value from a memory location corresponding to the target address; set at least one condition status indication depending on a result of comparing the target data value and the compare value; and discard the target data value without adding the target address to the working set of addresses for the given transaction; and in response to a conditional branch instruction specifying a test condition, the processing circuitry is configured to perform a branch operation conditional on said at least one condition status indication meeting said test condition. in response to a transactional compare-and-discard instruction executed within a given transaction, the transactional compare-and-discard instruction specifying a target address and a compare value, the processing circuitry is configured to: load a target data value from a memory location corresponding to the target address; set at least one condition status indication depending on a result of comparing the target data value and the compare value; and discard the target data value without adding the target address to the working set of addresses for the given transaction; and load a target data value from a memory location corresponding to the target address; set at least one condition status indication depending on a result of comparing the target data value and the compare value; and discard the target data value without adding the target address to the working set of addresses for the given transaction; in response to a conditional branch instruction specifying a test condition, the processing circuitry is configured to perform a branch operation conditional on said at least one condition status indication meeting said test condition.