A radio receiver device (2, 2') arranged to receive a radio signal (38, 38') modulated with a plurality of data symbols from an incoming bitstream, said radio receiver device (2, 2') comprising: an analogue circuit portion (4, 4') for connection to an antenna (10, 10'), said analogue circuit portion (4, 4') comprising an analogue-to-digital converter (32, 34, 32', 34') clocked by a first clock signal (54, 54'), wherein the analogue-to-digital converter (32, 34, 32', 34') is arranged to receive the radio signal (38, 38') and produce a digital signal (56, 58, 56', 58') therefrom; a digital circuit portion (6, 6') arranged to receive the digital signal (56, 58, 56', 58') produced by the analogue-to-digital converter (32, 34, 32', 34'), said digital circuit portion (6, 6') comprising: one or more digital processing units, clocked by a second clock (84, 84') derived from the first clock (54, 54'), said one or more digital processing units being arranged to process the digital signal (56, 58, 56', 58') and produce an output signal (90, 92, 90', 92') therefrom at an output sample rate; and characterised by a sample counter (72, 72') clocked by the second clock (84, 84') such that the sample counter (72, 72') counts a number of samples at the output sample rate, said sample counter (72, 72') being arranged to set a trigger flag (98, 98') when the number of samples exceeds a predetermined threshold value; wherein the radio receiver (2, 2') further comprises a buffer (100, 100') arranged to receive the output signal (90, 92, 90', 92') from the one or more digital processing units, wherein said buffer (100, 100') is enabled only when the trigger flag (98, 98') is set. an analogue circuit portion (4, 4') for connection to an antenna (10, 10'), said analogue circuit portion (4, 4') comprising an analogue-to-digital converter (32, 34, 32', 34') clocked by a first clock signal (54, 54'), wherein the analogue-to-digital converter (32, 34, 32', 34') is arranged to receive the radio signal (38, 38') and produce a digital signal (56, 58, 56', 58') therefrom; a digital circuit portion (6, 6') arranged to receive the digital signal (56, 58, 56', 58') produced by the analogue-to-digital converter (32, 34, 32', 34'), said digital circuit portion (6, 6') comprising: one or more digital processing units, clocked by a second clock (84, 84') derived from the first clock (54, 54'), said one or more digital processing units being arranged to process the digital signal (56, 58, 56', 58') and produce an output signal (90, 92, 90', 92') therefrom at an output sample rate; and characterised by a sample counter (72, 72') clocked by the second clock (84, 84') such that the sample counter (72, 72') counts a number of samples at the output sample rate, said sample counter (72, 72') being arranged to set a trigger flag (98, 98') when the number of samples exceeds a predetermined threshold value; one or more digital processing units, clocked by a second clock (84, 84') derived from the first clock (54, 54'), said one or more digital processing units being arranged to process the digital signal (56, 58, 56', 58') and produce an output signal (90, 92, 90', 92') therefrom at an output sample rate; and characterised by a sample counter (72, 72') clocked by the second clock (84, 84') such that the sample counter (72, 72') counts a number of samples at the output sample rate, said sample counter (72, 72') being arranged to set a trigger flag (98, 98') when the number of samples exceeds a predetermined threshold value;