A memory device, comprising: a memory bank; a memory side interface configured to receive a WRITE command from a host over a link, receive Write Data and a write protection code from the host over the link, the write protection code being a code for protection of the Write Data, store the Write Data to the memory bank in response to the WRITE command, receive a READ command from the host over the link, retrieve Read Data from the memory bank in response to the READ command, and send the Read Data and a read protection code to the host over the link, the read protection code being a code for protection of the Read Data; a memory side decoder configured to detect whether the Write Data has an error based on the write protection code; and a memory side encoder configured to generate the read protection code based on the Read Data retrieved from the memory bank, wherein the link comprises a plurality of data, DQ, lines, a data mask, DM, line for use by the host in mask write operations, and a Read Strobe clock line for use by the memory device to provide timing in read operations, and wherein the memory side interface is configured to receive the Write Data during a write operation and send the Read Data during a read operation over the plurality of DQ lines, receive the write protection code over the Read Strobe clock line during the write operation, and send the read protection code over the DM line during the read operation. a memory bank; a memory side interface configured to receive a WRITE command from a host over a link, receive Write Data and a write protection code from the host over the link, the write protection code being a code for protection of the Write Data, store the Write Data to the memory bank in response to the WRITE command, receive a READ command from the host over the link, retrieve Read Data from the memory bank in response to the READ command, and send the Read Data and a read protection code to the host over the link, the read protection code being a code for protection of the Read Data; receive a WRITE command from a host over a link, receive Write Data and a write protection code from the host over the link, the write protection code being a code for protection of the Write Data, store the Write Data to the memory bank in response to the WRITE command, receive a READ command from the host over the link, retrieve Read Data from the memory bank in response to the READ command, and send the Read Data and a read protection code to the host over the link, the read protection code being a code for protection of the Read Data; a memory side decoder configured to detect whether the Write Data has an error based on the write protection code; and a memory side encoder configured to generate the read protection code based on the Read Data retrieved from the memory bank, wherein the link comprises a plurality of data, DQ, lines, a data mask, DM, line for use by the host in mask write operations, and a Read Strobe clock line for use by the memory device to provide timing in read operations, and wherein the memory side interface is configured to receive the Write Data during a write operation and send the Read Data during a read operation over the plurality of DQ lines, receive the write protection code over the Read Strobe clock line during the write operation, and send the read protection code over the DM line during the read operation. receive the Write Data during a write operation and send the Read Data during a read operation over the plurality of DQ lines, receive the write protection code over the Read Strobe clock line during the write operation, and send the read protection code over the DM line during the read operation.