A method of forming a semiconductor device, comprising: providing a substrate that includes silicon, a first insulation layer directly over the silicon of the substrate, and a layer of silicon directly over the first insulation layer; performing an etch process to remove the layer of silicon and the insulation layer from a second area of the substrate, while maintaining the first insulation layer and the silicon layer in a first area of the substrate; forming a second layer of insulation over the layer of silicon in the first area of the substrate and over the silicon of the substrate in the second area of the substrate; forming a first plurality of trenches in the first area of the substrate that each extends through the second layer of insulation, the layer of silicon, and the first insulation layer, and extends into the silicon of the substrate; forming a second plurality of trenches in the second area of the substrate that each extends through the second layer of insulation, and extends into the silicon of the substrate; forming insulation material in the first and second pluralities of trenches; forming logic devices in the first area of the substrate, wherein the forming of each of the logic devices includes: forming spaced apart source and drain regions (60 and 62) the silicon layer, and forming a conductive gate over and insulated from a portion of the silicon layer and between the source and drain regions (60 and 62); forming memory cells in the second area of the substrate, wherein the forming of each of the memory cells includes: forming spaced apart second source and second drain regions (46 and 58) in the silicon of the substrate and defining a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, and forming a select gate over and insulated from a second portion of the channel region. providing a substrate that includes silicon, a first insulation layer directly over the silicon of the substrate, and a layer of silicon directly over the first insulation layer; performing an etch process to remove the layer of silicon and the insulation layer from a second area of the substrate, while maintaining the first insulation layer and the silicon layer in a first area of the substrate; forming a second layer of insulation over the layer of silicon in the first area of the substrate and over the silicon of the substrate in the second area of the substrate; forming a first plurality of trenches in the first area of the substrate that each extends through the second layer of insulation, the layer of silicon, and the first insulation layer, and extends into the silicon of the substrate; forming a second plurality of trenches in the second area of the substrate that each extends through the second layer of insulation, and extends into the silicon of the substrate; forming insulation material in the first and second pluralities of trenches; forming logic devices in the first area of the substrate, wherein the forming of each of the logic devices includes: forming spaced apart source and drain regions (60 and 62) the silicon layer, and forming a conductive gate over and insulated from a portion of the silicon layer and between the source and drain regions (60 and 62); forming spaced apart source and drain regions (60 and 62) the silicon layer, and forming a conductive gate over and insulated from a portion of the silicon layer and between the source and drain regions (60 and 62); forming memory cells in the second area of the substrate, wherein the forming of each of the memory cells includes: forming spaced apart second source and second drain regions (46 and 58) in the silicon of the substrate and defining a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, and forming a select gate over and insulated from a second portion of the channel region. forming spaced apart second source and second drain regions (46 and 58) in the silicon of the substrate and defining a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, and forming a select gate over and insulated from a second portion of the channel region.