An interposer-chip-arrangement, comprising: - an interposer with a main surface and a further main surface opposite the main surface, - metal layers arranged above the main surface, - a further metal layer arranged above the further main surface, - an electrically conductive interconnection through the interposer, the interconnection connecting one of the metal layers and the further metal layer, - a chip arranged at the main surface or at the further main surface, - a contact pad on the chip, - a dielectric layer arranged above the main surface with the metal layers embedded in the dielectric layer, - a further dielectric layer arranged above the further main surface with the further metal layer arranged in or on the further dielectric layer, and - the interposer being provided with an integrated circuit, which is connected with at least one of the metal layers, characterized in that - a cavity and a further cavity are present in the main surface or in the further main surface of the interposer, - the cavities (22, 23) have different depths, - the chip is arranged in the cavity, - a further chip with contact pad is arranged in the further cavity, the chips (12, 13) having different sizes, - the contact pads of the chip and the further chip are arranged at the same level at surfaces of the chips (12, 13) facing away from the interposer, - a planarizing cover layer with openings above the contact pads and with openings above the metal layers or above the further metal layer is applied on the chips (12, 13) and on the dielectric or further dielectric layer (2, 3), and wherein, when the cavity and the further cavity are present in the main surface, the contact pad of the chip is electrically conductively connected with the interconnection by a structured metallization on the planarizing cover layer via one of the metal layers or wherein, when the cavity and the further cavity are present in the further main surface, the contact pad of the chip is electrically conductively connected with the interconnection by a structured metallization on the planarizing cover layer via the further metal layer. - an interposer with a main surface and a further main surface opposite the main surface, - metal layers arranged above the main surface, - a further metal layer arranged above the further main surface, - an electrically conductive interconnection through the interposer, the interconnection connecting one of the metal layers and the further metal layer, - a chip arranged at the main surface or at the further main surface, - a contact pad on the chip, - a dielectric layer arranged above the main surface with the metal layers embedded in the dielectric layer, - a further dielectric layer arranged above the further main surface with the further metal layer arranged in or on the further dielectric layer, and - the interposer being provided with an integrated circuit, which is connected with at least one of the metal layers, characterized in that - a cavity and a further cavity are present in the main surface or in the further main surface of the interposer, - the cavities (22, 23) have different depths, - the chip is arranged in the cavity, - a further chip with contact pad is arranged in the further cavity, the chips (12, 13) having different sizes, - the contact pads of the chip and the further chip are arranged at the same level at surfaces of the chips (12, 13) facing away from the interposer, - a planarizing cover layer with openings above the contact pads and with openings above the metal layers or above the further metal layer is applied on the chips (12, 13) and on the dielectric or further dielectric layer (2, 3), and wherein, when the cavity and the further cavity are present in the main surface, the contact pad of the chip is electrically conductively connected with the interconnection by a structured metallization on the planarizing cover layer via one of the metal layers or wherein, when the cavity and the further cavity are present in the further main surface, the contact pad of the chip is electrically conductively connected with the interconnection by a structured metallization on the planarizing cover layer via the further metal layer.