A display device comprising: a display panel; a timing controller configured to generate image data corresponding to an input image, and generate and output a first start signal (TVST), an on clock (ON CLK), and an off clock (OFF_CLK); a level shifter configured to generate a second start signal (GVST) in synchronization with the first start signal (TVST), generate gate clocks (GCLKs) that swing to a predetermined voltage and have multiple phases distinguishable by phase numbers, by using the on clock (ON_CLK) and the off clock (OFF_CLK), and output the generated gate clocks (GCLKs); a shift register including multiple stages connected to gate lines of the display panel, respectively, and configured to output a scan signal (SCAN) sequentially to the gate lines by using the second start signal (GVST) and the gate clocks (GCLKs); and a data driving circuit configured to supply a data voltage (Vdata) corresponding to the image data to data lines of the display panel in synchronization with the scan signal (SCAN), wherein the level shifter is configured to generate the gate clocks (GCLKs) according to an order determined by the level shifter, said order being the sequential temporal schedule according to which the gate clocks (GCLKs) with their multiple phases are output to the shift register; wherein said order is determined on a basis of a number of pulses of one of the on clock (ON_CLK) and the off clock (OFF_CLK) included in a vertical blank period, and the level shifter is configured to detect a timing at which a pulse of the other one of the on clock (ON_CLK) and the off clock (OFF_CLK) is not output for a predetermined time and to use the detected timing as start timing of the vertical blank period, and is configured to determine the number of pulses of the one of the on clock (ON_CLK) and the off clock (OFF_CLK) included in a vertical blank period by counting the pulses from the start timing to a first edge of the first start signal (TVST) of a subsequent frame; wherein the level shifter is further configured to generate the gate clocks (GCLKs) in forward order of the phase numbers when the determined number of pulses is zero, and otherwise to generate the gate clocks (GCLK) in reverse order of the phase numbers by using as a start clock among the gate clocks (GCLKs), a clock having a phase number corresponding to the determined number of pulses of said one of the on clock (ON_CLK) and the off clock (OFF_CLK) included in the vertical blank period. a display panel; a timing controller configured to generate image data corresponding to an input image, and generate and output a first start signal (TVST), an on clock (ON CLK), and an off clock (OFF_CLK); a level shifter configured to generate a second start signal (GVST) in synchronization with the first start signal (TVST), generate gate clocks (GCLKs) that swing to a predetermined voltage and have multiple phases distinguishable by phase numbers, by using the on clock (ON_CLK) and the off clock (OFF_CLK), and output the generated gate clocks (GCLKs); a shift register including multiple stages connected to gate lines of the display panel, respectively, and configured to output a scan signal (SCAN) sequentially to the gate lines by using the second start signal (GVST) and the gate clocks (GCLKs); and a data driving circuit configured to supply a data voltage (Vdata) corresponding to the image data to data lines of the display panel in synchronization with the scan signal (SCAN), wherein the level shifter is configured to generate the gate clocks (GCLKs) according to an order determined by the level shifter, said order being the sequential temporal schedule according to which the gate clocks (GCLKs) with their multiple phases are output to the shift register; wherein said order is determined on a basis of a number of pulses of one of the on clock (ON_CLK) and the off clock (OFF_CLK) included in a vertical blank period, and the level shifter is configured to detect a timing at which a pulse of the other one of the on clock (ON_CLK) and the off clock (OFF_CLK) is not output for a predetermined time and to use the detected timing as start timing of the vertical blank period, and is configured to determine the number of pulses of the one of the on clock (ON_CLK) and the off clock (OFF_CLK) included in a vertical blank period by counting the pulses from the start timing to a first edge of the first start signal (TVST) of a subsequent frame; wherein the level shifter is further configured to generate the gate clocks (GCLKs) in forward order of the phase numbers when the determined number of pulses is zero, and otherwise to generate the gate clocks (GCLK) in reverse order of the phase numbers by using as a start clock among the gate clocks (GCLKs), a clock having a phase number corresponding to the determined number of pulses of said one of the on clock (ON_CLK) and the off clock (OFF_CLK) included in the vertical blank period.