A processor including: a memory port for accessing a physical memory under control of an address; at least one processing unit for executing instructions stored in the memory and/or operating on data stored in the memory; at least one address generation unit for generating an address for controlling access to the memory; the address generation unit being associated with at least a first set of a plurality of N registers, where the set of registers enables the address generation unit to generate the address under control of an address generation mechanism; characterised in that: a memory unit operative to save/load k of the N registers that are used for address generation, where 2<=k<= N, triggered by one operation, where the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers; wherein the processor is operative to operate on operands with a smallest size of one processor word and the memory word has a width of a multiple of the processor word size; and the concatenator is operative to map the registers to boundaries in the memory that correspond to the processor word. a memory port for accessing a physical memory under control of an address; at least one processing unit for executing instructions stored in the memory and/or operating on data stored in the memory; at least one address generation unit for generating an address for controlling access to the memory; the address generation unit being associated with at least a first set of a plurality of N registers, where the set of registers enables the address generation unit to generate the address under control of an address generation mechanism; characterised in that: a memory unit operative to save/load k of the N registers that are used for address generation, where 2<=k<= N, triggered by one operation, where the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers; wherein the processor is operative to operate on operands with a smallest size of one processor word and the memory word has a width of a multiple of the processor word size; and the concatenator is operative to map the registers to boundaries in the memory that correspond to the processor word. a memory unit operative to save/load k of the N registers that are used for address generation, where 2<=k<= N, triggered by one operation, where the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers; wherein the processor is operative to operate on operands with a smallest size of one processor word and the memory word has a width of a multiple of the processor word size; and the concatenator is operative to map the registers to boundaries in the memory that correspond to the processor word.