A row decoder, for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines (WL<i>) and array bitlines, said row decoder having a hierarchical architecture and comprising: at least one global decoder (8; 8') configured to receive block address signals (GP, D) and to select and bias a first global wordline (MWL_LV; MWL') and a second global wordline (MWL; MWL_WR) according to the block address signals (GP, D), the first global wordline being active both during a reading and during a programming operation, and the second global wordline being active during a programming operation and inactive during a reading operation; and a plurality of local decoders (9; 9'), operatively coupled to said at least one global decoder (8; 8'), each local decoder being connected at its input to said first (MWL_LV; MWL') and second (MWL; MWL_WR)_global wordlines and at its output to a single respective array wordline (WL<i>), and being configured to receive respective first (WLSELN_LV; WLSEL_SW) and second (WLSEL) selection signals and to select and bias the respective array wordline (WL<i>) according to values of said first and second global wordlines and of said respective first and second selection signals, wherein each local decoder (9; 9') comprises: a first circuit branch (25, 26, 31; 40, 41) configured to provide, based on the value of said first global wordline (MWL_LV; MWL') and said respective first selection signal (WLSELN_LV; WLSEL_SW), a first current path between the respective array wordline (WL<i>) and a first biasing source (V DD) during a reading operation; and a second circuit branch (32; 42) configured to provide, based on the value of said second global wordline (MWL; MWL_WR) and said respective second selection signal (WLSEL), a second current path, distinct from said first current path, between the respective array wordline (WL<i>) and a second biasing source (V CC) during a programming operation, wherein voltage levels of said first (MWL_LV; MWL') and second (MWL; MWL_WR) global wordlines and of said respective first (WLSELN_LV; WLSEL_SW) and second (WLSEL) selection signals do not exceed a highest value of the first (V DD) and second (V CC) biasing sources, during both reading and programming operations. at least one global decoder (8; 8') configured to receive block address signals (GP, D) and to select and bias a first global wordline (MWL_LV; MWL') and a second global wordline (MWL; MWL_WR) according to the block address signals (GP, D), the first global wordline being active both during a reading and during a programming operation, and the second global wordline being active during a programming operation and inactive during a reading operation; and a plurality of local decoders (9; 9'), operatively coupled to said at least one global decoder (8; 8'), each local decoder being connected at its input to said first (MWL_LV; MWL') and second (MWL; MWL_WR)_global wordlines and at its output to a single respective array wordline (WL<i>), and being configured to receive respective first (WLSELN_LV; WLSEL_SW) and second (WLSEL) selection signals and to select and bias the respective array wordline (WL<i>) according to values of said first and second global wordlines and of said respective first and second selection signals, wherein each local decoder (9; 9') comprises: a first circuit branch (25, 26, 31; 40, 41) configured to provide, based on the value of said first global wordline (MWL_LV; MWL') and said respective first selection signal (WLSELN_LV; WLSEL_SW), a first current path between the respective array wordline (WL<i>) and a first biasing source (V DD) during a reading operation; and a second circuit branch (32; 42) configured to provide, based on the value of said second global wordline (MWL; MWL_WR) and said respective second selection signal (WLSEL), a second current path, distinct from said first current path, between the respective array wordline (WL<i>) and a second biasing source (V CC) during a programming operation, wherein voltage levels of said first (MWL_LV; MWL') and second (MWL; MWL_WR) global wordlines and of said respective first (WLSELN_LV; WLSEL_SW) and second (WLSEL) selection signals do not exceed a highest value of the first (V DD) and second (V CC) biasing sources, during both reading and programming operations.