An SOI-based electro-optic arrangement, comprising: a silicon substrate; a buried dielectric layer; a single crystal silicon "SOI" layer disposed over the buried dielectric layer; at least one optical component area (110, 112) disposed for waveguiding electromagnetic radiation, including: a thin dielectric layer (118, 120) disposed over a portion (106-A, 106-P) of the SOI layer; and, a silicon layer (124, 126) disposed over the thin dielectric layer (118, 120) so as to overlap, at least in part, the portion (106-A, 106-P) of the SOI layer; at least one electrical component area, including: a thin dielectric layer disposed over a separate portion (106-E) of the SOI layer; and, a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer; wherein one or more optical devices are formed in each of the optical component areas (110, 112), and one or more electrical devices are formed in each of the electrical component areas; and, a common electrical interconnect arrangement (152... 160, 162... 170, 174... 180, 182... 186), including one or more layers (162... 170, 182... 186) of metallization. a silicon substrate; a buried dielectric layer; a single crystal silicon "SOI" layer disposed over the buried dielectric layer; at least one optical component area (110, 112) disposed for waveguiding electromagnetic radiation, including: a thin dielectric layer (118, 120) disposed over a portion (106-A, 106-P) of the SOI layer; and, a silicon layer (124, 126) disposed over the thin dielectric layer (118, 120) so as to overlap, at least in part, the portion (106-A, 106-P) of the SOI layer; at least one electrical component area, including: a thin dielectric layer disposed over a separate portion (106-E) of the SOI layer; and, a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer; wherein one or more optical devices are formed in each of the optical component areas (110, 112), and one or more electrical devices are formed in each of the electrical component areas; and, a common electrical interconnect arrangement (152... 160, 162... 170, 174... 180, 182... 186), including one or more layers (162... 170, 182... 186) of metallization. a thin dielectric layer (118, 120) disposed over a portion (106-A, 106-P) of the SOI layer; and, a silicon layer (124, 126) disposed over the thin dielectric layer (118, 120) so as to overlap, at least in part, the portion (106-A, 106-P) of the SOI layer; at least one electrical component area, including: a thin dielectric layer disposed over a separate portion (106-E) of the SOI layer; and, a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer; wherein one or more optical devices are formed in each of the optical component areas (110, 112), and one or more electrical devices are formed in each of the electrical component areas; and, a common electrical interconnect arrangement (152... 160, 162... 170, 174... 180, 182... 186), including one or more layers (162... 170, 182... 186) of metallization. a thin dielectric layer disposed over a separate portion (106-E) of the SOI layer; and, a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer; wherein one or more optical devices are formed in each of the optical component areas (110, 112), and one or more electrical devices are formed in each of the electrical component areas; and, a common electrical interconnect arrangement (152... 160, 162... 170, 174... 180, 182... 186), including one or more layers (162... 170, 182... 186) of metallization.