A power up test system comprising: a first row (Row 1) of skewed ROM memory cells storing a first predetermined data word, each memory cell of the first row (Row 1) of skewed ROM memory cells (630, 632, 634) being connected to corresponding bitlines and configured as long channel transistors; a second row (Row 2) of skewed ROM memory cells (636, 638, 640) storing a second predetermined data word, each memory cell of the second row (Row 2) of skewed ROM memory cells being connected to the corresponding bitlines nd configured as long channel transistors, and the second predetermined data word being the single bit shifted in a preset direction first predetermined data word, where a last bit of the first row occupies a first bit position of the second row; sense amplifiers coupled to the corresponding bitlines and adapted to sense the first predetermined data word from the first row (Row 1) of skewed ROM memory cells in a first read operation and adapted to sense the second predetermined data word from the second row (Row 2) of skewed ROM memory cells in a second read operation; a dual function data register adapted to receive the first predetermined data word into slave latches and to shift the first predetermined data word into master latches in the first read operation in the preset direction such that a bit of the first predetermined data word stored in a last slave latch is shifted to a first master latch, the dual function data register adapted to receive the second predetermined data word into the slave latches in the second read operation; and a data comparison logic adapted to compare data between the master latches and the slave latches, and to provide a signal indicating matching data between the master latches and the slave latches. a first row (Row 1) of skewed ROM memory cells storing a first predetermined data word, each memory cell of the first row (Row 1) of skewed ROM memory cells (630, 632, 634) being connected to corresponding bitlines and configured as long channel transistors; a second row (Row 2) of skewed ROM memory cells (636, 638, 640) storing a second predetermined data word, each memory cell of the second row (Row 2) of skewed ROM memory cells being connected to the corresponding bitlines nd configured as long channel transistors, and the second predetermined data word being the single bit shifted in a preset direction first predetermined data word, where a last bit of the first row occupies a first bit position of the second row; sense amplifiers coupled to the corresponding bitlines and adapted to sense the first predetermined data word from the first row (Row 1) of skewed ROM memory cells in a first read operation and adapted to sense the second predetermined data word from the second row (Row 2) of skewed ROM memory cells in a second read operation; a dual function data register adapted to receive the first predetermined data word into slave latches and to shift the first predetermined data word into master latches in the first read operation in the preset direction such that a bit of the first predetermined data word stored in a last slave latch is shifted to a first master latch, the dual function data register adapted to receive the second predetermined data word into the slave latches in the second read operation; and a data comparison logic adapted to compare data between the master latches and the slave latches, and to provide a signal indicating matching data between the master latches and the slave latches.