A method of fabricating a graphene device (100, 200), comprising: forming a graphene layer (120, 220) on first and second regions (110A, 210A, 110B, 210B) of a semiconductor substrate (110, 210) to form a Schottky barrier at the junction of the graphene layer (120, 220) and the semiconductor substrate (110, 210); forming a metal layer on the graphene layer (120, 220); forming a third electrode (150, 250) on a third region (110C, 210C) of the semiconductor substrate (110, 210) without an intervening graphene layer (120, 220) between the third electrode (150, 250) and the third region (110C, 210C) of the semiconductor substrate (110, 210); forming a first electrode (130, 230) on the first region of the semiconductor substrate by removing the metal layer from the second region (110B, 210B) of the semiconductor substrate (110, 210) to expose the graphene layer (120, 220) on the second region (110B, 210B) of the semiconductor substrate (110, 210); forming a gate insulating layer (160, 260) on the semiconductor substrate (110, 210) the graphene layer (120, 220), the first electrode (130, 230), and the third electrode (150, 250); forming a second electrode (140, 240) on the second region of the semiconductor substrate, on the gate insulating layer (160, 260) between the first electrode (130, 230) and the third electrode (150, 250); and forming holes through the gate insulating layer to expose upper portions of the first electrode (130, 230) and the third electrode (150, 250); and characterized in that on the first and second regions of the semiconductor substrate the graphene layer is disposed on the semiconductor substrate without an intervening insulating layer such that the graphene layer directly contacts the semiconductor substrate in the first and second regions of the semiconductor substrate. forming a graphene layer (120, 220) on first and second regions (110A, 210A, 110B, 210B) of a semiconductor substrate (110, 210) to form a Schottky barrier at the junction of the graphene layer (120, 220) and the semiconductor substrate (110, 210); forming a metal layer on the graphene layer (120, 220); forming a third electrode (150, 250) on a third region (110C, 210C) of the semiconductor substrate (110, 210) without an intervening graphene layer (120, 220) between the third electrode (150, 250) and the third region (110C, 210C) of the semiconductor substrate (110, 210); forming a first electrode (130, 230) on the first region of the semiconductor substrate by removing the metal layer from the second region (110B, 210B) of the semiconductor substrate (110, 210) to expose the graphene layer (120, 220) on the second region (110B, 210B) of the semiconductor substrate (110, 210); forming a gate insulating layer (160, 260) on the semiconductor substrate (110, 210) the graphene layer (120, 220), the first electrode (130, 230), and the third electrode (150, 250); forming a second electrode (140, 240) on the second region of the semiconductor substrate, on the gate insulating layer (160, 260) between the first electrode (130, 230) and the third electrode (150, 250); and forming holes through the gate insulating layer to expose upper portions of the first electrode (130, 230) and the third electrode (150, 250); and characterized in that on the first and second regions of the semiconductor substrate the graphene layer is disposed on the semiconductor substrate without an intervening insulating layer such that the graphene layer directly contacts the semiconductor substrate in the first and second regions of the semiconductor substrate.