A logic gateway circuit for an ISA standard bus of a computer system, the ISA standard bus supporting a plurality of interrupt request signals generated from a plurality of target devices (D1, D2,..., Dn) connected to the ISA standard bus, the logic gateway circuit comprising: an output OR gate having a plurality of input terminals and an interrupt request signal output terminal; and a plurality of gateway circuits (3a, 3b,..., 3n) respectively connected between the interrupt request signal output terminal of the output OR gate and the target devices (D1, D2,..., Dn), each gateway circuit (3a, 3b,..., 3n) having an interrupt request signal input terminal (31a, 31b,..., 31m) electrically connected to one of the target devices (D1, D2,..., Dn) for receiving the interrupt request signal generated by the target device (D1, D2,..., Dn); characterised in that each gateway circuit (3a, 3b,.... 3n) includes an inverter, the input terminal of which is connected to said interrupt request signal output terminal, and in that each gateway circuit generates a gateway signal according to a signal state of the interrupt request signal output terminal of the output OR gate and a signal state of the interrupt request signal of the target device (D1, D2,..., Dn) so as to allow the interrupt request signal of the target device (D1, D2,..., Dn) to transmit through the gateway circuit (3a, 3b,.., 3n) to the output OR gate or to selectively queue the interrupt request signal in the gateway circuit (3a, 3b,..., 3n), characterized in that the gateway circuit (3a, 3b,..., 3n) further comprises: an AND gate, which has an input terminal served as the interrupt request signal input terminal, a gateway signal input terminal, and an output terminal, and characterized in that the interrupt request signal input terminal is connected to an associated target device (D1, D2,..., Dn) to receive the interrupt request signal from said target device (D1, D2,..., Dn), and the output terminal is connected to an input terminal of the output OR gate; and an OR gate, which has first and second input terminals(32a, 32b) and an output terminal, characterized in that the first input terminal is connected to the output terminal of the AND gate, the second input terminal is connected to the output terminal of the inverter, and the output terminal is connected to the gateway signal input terminal of the AND gate, the OR gate basing on states of the output terminal of the AND gate and the interrupt request signal output terminal of the output OR gate to generate a gateway signal to the gateway signal input terminal (31 b) of the AND gate. an output OR gate having a plurality of input terminals and an interrupt request signal output terminal; and a plurality of gateway circuits (3a, 3b,..., 3n) respectively connected between the interrupt request signal output terminal of the output OR gate and the target devices (D1, D2,..., Dn), each gateway circuit (3a, 3b,..., 3n) having an interrupt request signal input terminal (31a, 31b,..., 31m) electrically connected to one of the target devices (D1, D2,..., Dn) for receiving the interrupt request signal generated by the target device (D1, D2,..., Dn); characterised in that each gateway circuit (3a, 3b,.... 3n) includes an inverter, the input terminal of which is connected to said interrupt request signal output terminal, and in that each gateway circuit generates a gateway signal according to a signal state of the interrupt request signal output terminal of the output OR gate and a signal state of the interrupt request signal of the target device (D1, D2,..., Dn) so as to allow the interrupt request signal of the target device (D1, D2,..., Dn) to transmit through the gateway circuit (3a, 3b,.., 3n) to the output OR gate or to selectively queue the interrupt request signal in the gateway circuit (3a, 3b,..., 3n), an AND gate, which has an input terminal served as the interrupt request signal input terminal, a gateway signal input terminal, and an output terminal, and characterized in that the interrupt request signal input terminal is connected to an associated target device (D1, D2,..., Dn) to receive the interrupt request signal from said target device (D1, D2,..., Dn), and the output terminal is connected to an input terminal of the output OR gate; and an OR gate, which has first and second input terminals(32a, 32b) and an output terminal, characterized in that the first input terminal is connected to the output terminal of the AND gate, the second input terminal is connected to the output terminal of the inverter, and the output terminal is connected to the gateway signal input terminal of the AND gate, the OR gate basing on states of the output terminal of the AND gate and the interrupt request signal output terminal of the output OR gate to generate a gateway signal to the gateway signal input terminal (31 b) of the AND gate.