A class-AB amplifier comprising: - an output stage that comprises a first half-bridge (120, 122) and a second half-bridge (124, 126) configured to be coupled to a load; and - a current sensing circuit coupled to said first half-bridge (120, 122) and configured to sense a load current, wherein the current sensing circuit comprises: - a first resistive element; - a first sense transistor having a gate terminal coupled to a gate terminal of a first transistor of said first half-bridge (120, 122), wherein a drain terminal of said first sense transistor is biased (402, 404, 408) with a voltage equal to the voltage at an output (OUTM) of the first half-bridge (120, 122), whereby, since the gate voltages of said first transistor and said first sense transistor are equal and the drain voltages of said first transistor and said first sense transistor are equal, said first sense transistor generates a first current being a scaled copy of the current flowing through said first transistor; and - a current mirror (416, 624, 626) configured to generate a first mirrored current (i 414) by mirroring the first current, and flowing the mirrored current (i 414) through the first resistive element; characterized in that the current sensing circuit is coupled to said second half-bridge (124, 126) and comprises further: - a second resistive element; - a second sense transistor having a gate terminal coupled to a gate terminal of a second transistor of said second half-bridge (124, 126), wherein a drain terminal of said second sense transistor is biased (422, 424, 428) with a voltage equal to the voltage at an output (OUTP) of the second half-bridge (124, 126), whereby, since the gate voltages of said second transistor and said second sense transistor are equal and the drain voltages of said second transistor and said second sense transistor are equal, said second sense transistor generates a second current being a scaled copy of the current flowing through said second transistor; - a further current mirror (436, 644, 646) configured to generate a second mirrored current (i 434) by mirroring the second current, and flowing the second mirrored current (i 434) through the second resistive element; - a fully-differential buffer receiving a first voltage (V senseM) of the first resistive element and a second voltage (V senseP) of the second resistive element, and producing a differential voltage (ΔV) with a gain; wherein each of said current mirror (416, 624, 626) and said further current mirror (436, 644, 646) comprises respectively a first current mirror (626; 646) comprising two transistors (618, 620; 638, 640) and a first current mirror transistor (622; 642) configured to adjust a mirroring ratio of the first current mirror (626; 646) by selectively connecting a gate terminal of said first current mirror transistor (622; 642) to a gate terminal of said two transistors (618, 620; 638, 640) based on a first control signal. - an output stage that comprises a first half-bridge (120, 122) and a second half-bridge (124, 126) configured to be coupled to a load; and - a current sensing circuit coupled to said first half-bridge (120, 122) and configured to sense a load current, - a first resistive element; - a first sense transistor having a gate terminal coupled to a gate terminal of a first transistor of said first half-bridge (120, 122), wherein a drain terminal of said first sense transistor is biased (402, 404, 408) with a voltage equal to the voltage at an output (OUTM) of the first half-bridge (120, 122), whereby, since the gate voltages of said first transistor and said first sense transistor are equal and the drain voltages of said first transistor and said first sense transistor are equal, said first sense transistor generates a first current being a scaled copy of the current flowing through said first transistor; and - a current mirror (416, 624, 626) configured to generate a first mirrored current (i 414) by mirroring the first current, and flowing the mirrored current (i 414) through the first resistive element; - a second resistive element; - a second sense transistor having a gate terminal coupled to a gate terminal of a second transistor of said second half-bridge (124, 126), wherein a drain terminal of said second sense transistor is biased (422, 424, 428) with a voltage equal to the voltage at an output (OUTP) of the second half-bridge (124, 126), whereby, since the gate voltages of said second transistor and said second sense transistor are equal and the drain voltages of said second transistor and said second sense transistor are equal, said second sense transistor generates a second current being a scaled copy of the current flowing through said second transistor; - a further current mirror (436, 644, 646) configured to generate a second mirrored current (i 434) by mirroring the second current, and flowing the second mirrored current (i 434) through the second resistive element; - a fully-differential buffer receiving a first voltage (V senseM) of the first resistive element and a second voltage (V senseP) of the second resistive element, and producing a differential voltage (ΔV) with a gain;