A processor-based device, comprising: a plurality of processing elements, PEs, (102 -102), each comprising a plurality of repeat-read indicators (138 -138) each corresponding to a coherence granule (110) read by the processing element, PE, and indicating whether the coherence granule was repeatedly read by the PE; a central ordering point circuit, COP,; a master PE (102) among the plurality of PEs configured to send a cache coherence bus command to the COP as part of a memory store operation; and a PE (102) of the plurality of PEs configured to: generate a first protocol preference indicator based on a repeat-read indicator (138) of the plurality of repeat-read indicators; and send the first protocol preference indicator to the COP; the COP configured to: responsive to receiving the cache coherence bus command, dynamically select, on a store-by-store basis, one of a write invalidate protocol and a write update protocol as a cache coherence protocol to use for maintaining cache coherency, based on one or more protocol preference indicators provided by one or more of the master PE, at least one snooper PE among the plurality of PEs (102, 102), and the COP, the one or more protocol preference indicators comprising the first protocol preference indicator; and send a response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooper PE. a plurality of processing elements, PEs, (102 -102), each comprising a plurality of repeat-read indicators (138 -138) each corresponding to a coherence granule (110) read by the processing element, PE, and indicating whether the coherence granule was repeatedly read by the PE; a central ordering point circuit, COP,; a master PE (102) among the plurality of PEs configured to send a cache coherence bus command to the COP as part of a memory store operation; and a PE (102) of the plurality of PEs configured to: generate a first protocol preference indicator based on a repeat-read indicator (138) of the plurality of repeat-read indicators; and send the first protocol preference indicator to the COP; generate a first protocol preference indicator based on a repeat-read indicator (138) of the plurality of repeat-read indicators; and send the first protocol preference indicator to the COP; the COP configured to: responsive to receiving the cache coherence bus command, dynamically select, on a store-by-store basis, one of a write invalidate protocol and a write update protocol as a cache coherence protocol to use for maintaining cache coherency, based on one or more protocol preference indicators provided by one or more of the master PE, at least one snooper PE among the plurality of PEs (102, 102), and the COP, the one or more protocol preference indicators comprising the first protocol preference indicator; and send a response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooper PE. responsive to receiving the cache coherence bus command, dynamically select, on a store-by-store basis, one of a write invalidate protocol and a write update protocol as a cache coherence protocol to use for maintaining cache coherency, based on one or more protocol preference indicators provided by one or more of the master PE, at least one snooper PE among the plurality of PEs (102, 102), and the COP, the one or more protocol preference indicators comprising the first protocol preference indicator; and send a response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooper PE.