A display device comprising: a display panel having gate lines; and a shift register comprising a plurality of dependently connected stages (ST1 to STn), the shift register configured to supply gate pulses (Gout) to the gate lines, wherein each stage of the shift register comprises: a node control circuit (NCON) configured to control potentials of a Q node and a QB node in response to a gate start pulse or an output from a previous stage; a reset circuit connected to the Q node and configured to receive an output control signal at a first voltage level during a non-display period of a frame period, to receive the output control signal at a second voltage level during a display period of the frame period, and to output the output control signal to an output terminal (Qout) of the reset circuit according to the potential of the Q node or discharge the output terminal (Qout) at a low potential voltage based on the Q node potential; a gate pulse output unit connected to the output terminal (Qout); and the reset circuit further configured to control the gate pulse output unit to prevent outputting of the gate pulse (Gout) in response to the output control signal at the first voltage level and to output the gate pulse (Gout) to the output terminal (Qout) in response to the output control signal at the second voltage level; wherein the gate pulse output unit comprises: a first output unit configured to provide a first output signal (Vgout1) to an output terminal (Nout) connected a respective gate line, by inverting the respective voltage level received from the output terminal (Qout) of the reset circuit; and a second output unit configured to invert the respective voltage level received from the output terminal (Qout) of the reset circuit and provide a second output signal (Vgout2) having a phase different from a phase of the first output signal (Vgout1) to the output terminal (Nout). a display panel having gate lines; and a shift register comprising a plurality of dependently connected stages (ST1 to STn), the shift register configured to supply gate pulses (Gout) to the gate lines, wherein each stage of the shift register comprises: a node control circuit (NCON) configured to control potentials of a Q node and a QB node in response to a gate start pulse or an output from a previous stage; a reset circuit connected to the Q node and configured to receive an output control signal at a first voltage level during a non-display period of a frame period, to receive the output control signal at a second voltage level during a display period of the frame period, and to output the output control signal to an output terminal (Qout) of the reset circuit according to the potential of the Q node or discharge the output terminal (Qout) at a low potential voltage based on the Q node potential; a gate pulse output unit connected to the output terminal (Qout); and the reset circuit further configured to control the gate pulse output unit to prevent outputting of the gate pulse (Gout) in response to the output control signal at the first voltage level and to output the gate pulse (Gout) to the output terminal (Qout) in response to the output control signal at the second voltage level; a node control circuit (NCON) configured to control potentials of a Q node and a QB node in response to a gate start pulse or an output from a previous stage; a reset circuit connected to the Q node and configured to receive an output control signal at a first voltage level during a non-display period of a frame period, to receive the output control signal at a second voltage level during a display period of the frame period, and to output the output control signal to an output terminal (Qout) of the reset circuit according to the potential of the Q node or discharge the output terminal (Qout) at a low potential voltage based on the Q node potential; a gate pulse output unit connected to the output terminal (Qout); and the reset circuit further configured to control the gate pulse output unit to prevent outputting of the gate pulse (Gout) in response to the output control signal at the first voltage level and to output the gate pulse (Gout) to the output terminal (Qout) in response to the output control signal at the second voltage level; wherein the gate pulse output unit comprises: a first output unit configured to provide a first output signal (Vgout1) to an output terminal (Nout) connected a respective gate line, by inverting the respective voltage level received from the output terminal (Qout) of the reset circuit; and a second output unit configured to invert the respective voltage level received from the output terminal (Qout) of the reset circuit and provide a second output signal (Vgout2) having a phase different from a phase of the first output signal (Vgout1) to the output terminal (Nout). a first output unit configured to provide a first output signal (Vgout1) to an output terminal (Nout) connected a respective gate line, by inverting the respective voltage level received from the output terminal (Qout) of the reset circuit; and a second output unit configured to invert the respective voltage level received from the output terminal (Qout) of the reset circuit and provide a second output signal (Vgout2) having a phase different from a phase of the first output signal (Vgout1) to the output terminal (Nout).