A data processing circuit or a channel setting determination circuit, the circuit comprising: a main data processing circuit receiving a series of data samples and including: a first equalizer circuit receiving the series of data samples and providing an equalized output, wherein the equalizer circuit is controlled at least in part by a coefficient; and a data detector circuit, wherein the data detector circuit receives the equalizer output and provides a main data output based at least in part on a partial response target; an adaptive setting determination circuit receiving the series of data samples and the main data output, and operating in parallel with the main data processing circuit to adaptively determine the coefficient and the target, wherein the adaptive setting determination circuit includes a second equalizer circuit receiving the series of data samples and equalizing the series of data samples to provide a second equalized output; wherein the first equalizer circuit is a first finite impulse response filter having at least a first tap, wherein the second equalizer circuit is a second finite impulse response filter having at least a second tap; wherein the adaptive setting determination circuit includes: a first multiplier circuit multiplying the series of data samples by an error value and providing a coefficient value; a second multiplier circuit multiplying the main data output by the error value and providing a target value; a convolution circuit, wherein the convolution circuit provides a convolved output based at least in part on a current partial response target derived from the target value; and an adder circuit, wherein the adder circuit compares the convolved output with the second equalized output and provides the difference as the error; wherein operation of the second equalizer circuit is at least in part governed by a current coefficient derived from the coefficient value; and wherein the current coefficient is provided as the coefficient to the first tap when the error value is a minimum. a main data processing circuit receiving a series of data samples and including: a first equalizer circuit receiving the series of data samples and providing an equalized output, wherein the equalizer circuit is controlled at least in part by a coefficient; and a data detector circuit, wherein the data detector circuit receives the equalizer output and provides a main data output based at least in part on a partial response target; a first equalizer circuit receiving the series of data samples and providing an equalized output, wherein the equalizer circuit is controlled at least in part by a coefficient; and a data detector circuit, wherein the data detector circuit receives the equalizer output and provides a main data output based at least in part on a partial response target; an adaptive setting determination circuit receiving the series of data samples and the main data output, and operating in parallel with the main data processing circuit to adaptively determine the coefficient and the target, wherein the adaptive setting determination circuit includes a second equalizer circuit receiving the series of data samples and equalizing the series of data samples to provide a second equalized output; wherein the first equalizer circuit is a first finite impulse response filter having at least a first tap, wherein the second equalizer circuit is a second finite impulse response filter having at least a second tap; wherein the adaptive setting determination circuit includes: a first multiplier circuit multiplying the series of data samples by an error value and providing a coefficient value; a second multiplier circuit multiplying the main data output by the error value and providing a target value; a convolution circuit, wherein the convolution circuit provides a convolved output based at least in part on a current partial response target derived from the target value; and an adder circuit, wherein the adder circuit compares the convolved output with the second equalized output and provides the difference as the error; wherein operation of the second equalizer circuit is at least in part governed by a current coefficient derived from the coefficient value; and wherein the current coefficient is provided as the coefficient to the first tap when the error value is a minimum. a first multiplier circuit multiplying the series of data samples by an error value and providing a coefficient value; a second multiplier circuit multiplying the main data output by the error value and providing a target value; a convolution circuit, wherein the convolution circuit provides a convolved output based at least in part on a current partial response target derived from the target value; and an adder circuit, wherein the adder circuit compares the convolved output with the second equalized output and provides the difference as the error; wherein operation of the second equalizer circuit is at least in part governed by a current coefficient derived from the coefficient value; and wherein the current coefficient is provided as the coefficient to the first tap when the error value is a minimum.