A feedback-loop frequency synthesis device (100; 200; 300) comprising: - an input intended to receive an electrical signal oscillating at a reference frequency (F ref); - an output intended to supply an electrical signal oscillating at an output frequency (F c); - a servo circuit for the control of the output frequency (F c) by the reference frequency (F ref), connecting the input to the output of the device and comprising a first phase accumulator clocked at a frequency linked to the reference frequency (F ref), a phase comparison block, a loop filter and a frequency controlled oscillator providing the electrical signal oscillating at the output frequency (F c), the phase comparison block being linked to the loop filter for controlling said frequency controlled oscillator; and - a feedback loop connecting the output to the phase comparison block, comprising a second phase accumulator clocked at a frequency linked to the output frequency (F c), the first and second phase accumulators (106, 122) being adapted to provide the same number T of possible phase accumulation discrete values; characterized in that: - the servo circuit is configured to provide, to the phase comparison block, T first distinct logic signals the logic levels of which depend continuously on the phase accumulation values (φ ref) supplied by the first phase accumulator according to a first multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T first signals; - the feedback loop is configured to provide, to the phase comparison block, T second distinct logic signals the logic levels of which depend continuously on the phase accumulation values (φ c) supplied by second phase accumulator according to a second multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T second signals; and - the phase comparison block comprises T phase comparators with logic gates receiving respectively in continuous time the T first logic signals on T first comparison inputs and the T second logic signals on T second comparison inputs. - an input intended to receive an electrical signal oscillating at a reference frequency (F ref); - an output intended to supply an electrical signal oscillating at an output frequency (F c); - a servo circuit for the control of the output frequency (F c) by the reference frequency (F ref), connecting the input to the output of the device and comprising a first phase accumulator clocked at a frequency linked to the reference frequency (F ref), a phase comparison block, a loop filter and a frequency controlled oscillator providing the electrical signal oscillating at the output frequency (F c), the phase comparison block being linked to the loop filter for controlling said frequency controlled oscillator; and - a feedback loop connecting the output to the phase comparison block, comprising a second phase accumulator clocked at a frequency linked to the output frequency (F c), the first and second phase accumulators (106, 122) being adapted to provide the same number T of possible phase accumulation discrete values; - the servo circuit is configured to provide, to the phase comparison block, T first distinct logic signals the logic levels of which depend continuously on the phase accumulation values (φ ref) supplied by the first phase accumulator according to a first multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T first signals; - the feedback loop is configured to provide, to the phase comparison block, T second distinct logic signals the logic levels of which depend continuously on the phase accumulation values (φ c) supplied by second phase accumulator according to a second multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T second signals; and - the phase comparison block comprises T phase comparators with logic gates receiving respectively in continuous time the T first logic signals on T first comparison inputs and the T second logic signals on T second comparison inputs.