A display substrate, comprising: a plurality of gate lines, a plurality of data lines, a plurality of gate lead wires, and a plurality of touch electrode lead wires, the plurality of gate lead wires and the plurality of touch electrode lead wires form a one-to-one correspondence, the plurality of gate lead wires being connected to a gate integrated circuit and the plurality of touch electrode lead wires being connected to a touch IC, each one of the plurality of gate lead wires configured for providing a gate signal to at least one of the plurality of gate lines, at least one of the plurality of touch electrode lead wires configured for transmitting a touch signal to a touch electrode, wherein: at least one of the plurality of gate lead wires and at least one of the plurality of touch electrode lead wires are aligned along a direction that one of the plurality of data lines is aligned, wherein the end of the at least one of the plurality of touch electrode lead wires and the end of the at least one of the plurality of gate lead wires are facing each other, the at least one of the plurality of gate lead wires is connected to a corresponding gate line through a first via, and the at least one of the plurality of touch electrode lead wires is connected to a corresponding touch electrode through a second via, and the at least one of the plurality of gate lead wires, the at least one of the plurality of touch electrode lead wires, a source electrode, and a drain electrode are arranged in a same layer, the at least one of the plurality of gate lead wires and the at least one of the plurality of touch electrode lead wires are aligned with one another, and the at least one of the plurality of touch electrode lead wires is arranged to be separated from a connection point between the at least one of the plurality of gate lead wires and the corresponding gate line by a distance, such that the at least one of the plurality of touch electrode lead wires and the at least one of the plurality of gate lead wires are insulated from each other, wherein the gate IC is located at one side of the plurality of data lines and the touch IC is located at another side of the plurality of data lines, the at least one of the plurality of touch electrode lead wires is separated from the connection point between the at least one of the plurality of gate lead wires and the corresponding gate line along the direction that one of the plurality of data lines is aligned. at least one of the plurality of gate lead wires and at least one of the plurality of touch electrode lead wires are aligned along a direction that one of the plurality of data lines is aligned, wherein the end of the at least one of the plurality of touch electrode lead wires and the end of the at least one of the plurality of gate lead wires are facing each other, the at least one of the plurality of gate lead wires is connected to a corresponding gate line through a first via, and the at least one of the plurality of touch electrode lead wires is connected to a corresponding touch electrode through a second via, and the at least one of the plurality of gate lead wires, the at least one of the plurality of touch electrode lead wires, a source electrode, and a drain electrode are arranged in a same layer, the at least one of the plurality of gate lead wires and the at least one of the plurality of touch electrode lead wires are aligned with one another, and the at least one of the plurality of touch electrode lead wires is arranged to be separated from a connection point between the at least one of the plurality of gate lead wires and the corresponding gate line by a distance, such that the at least one of the plurality of touch electrode lead wires and the at least one of the plurality of gate lead wires are insulated from each other, wherein the gate IC is located at one side of the plurality of data lines and the touch IC is located at another side of the plurality of data lines, the at least one of the plurality of touch electrode lead wires is separated from the connection point between the at least one of the plurality of gate lead wires and the corresponding gate line along the direction that one of the plurality of data lines is aligned.