A digital-to-analog converter, DAC for converting an N bit digital value to an analog signal, said DAC comprising: a first capacitive DAC that comprises: N first capacitances (C 4, C 3, C 2, C 1) that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one; and N first switches (SW MSB) that first, during a sampling phase, connect a selected one of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) to a common node at a same time that remaining ones of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) are connected to one of a voltage reference and a ground, and that second, during an integrating phase subsequent to said sampling phase, connect said selected one of said second ends of said N first capacitances to said ground at a same time that said remaining ones of said second ends of said N first capacitances are connected to said ground; a first amplifier having an input and an output, wherein capacitance values of said N first capacitances (C 4, C 3, C 2, C 1) are substantially equal; and wherein said first ends are connected to said input of said first amplifier and disconnected from said ground during said integrating phase, and wherein said first ends are connected to said ground and disconnected from said input of said first amplifier during said sampling phase; and a second DAC (120, 150) connected to said common node, wherein the second DAC is one of a second capacitive DAC comprising N second switches (SW LSB) and and a second amplifier, whereby the output of the second amplifier is connected to the common node, OR a resistive DAC comprising N resistances (R 4, R 3, R 2, R 1) connected in series between said voltage reference and said ground, N nodes between said N resistances and said ground, and N second switches (SW LSB) that selectively connect said common node to one of said N nodes; a control module for controlling said first and second switches (SW MSB, SW LSB), wherein the MSB bits of the the N bit digital value are allocated to the N first switches (SW MSB) and the LSB bits of the N bit digital value are allocated to the N second switches (SW LSB). a first capacitive DAC that comprises: N first capacitances (C 4, C 3, C 2, C 1) that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one; and N first switches (SW MSB) that first, during a sampling phase, connect a selected one of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) to a common node at a same time that remaining ones of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) are connected to one of a voltage reference and a ground, and that second, during an integrating phase subsequent to said sampling phase, connect said selected one of said second ends of said N first capacitances to said ground at a same time that said remaining ones of said second ends of said N first capacitances are connected to said ground; N first capacitances (C 4, C 3, C 2, C 1) that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one; and N first switches (SW MSB) that first, during a sampling phase, connect a selected one of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) to a common node at a same time that remaining ones of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) are connected to one of a voltage reference and a ground, and that second, during an integrating phase subsequent to said sampling phase, connect said selected one of said second ends of said N first capacitances to said ground at a same time that said remaining ones of said second ends of said N first capacitances are connected to said ground; a first amplifier having an input and an output, wherein capacitance values of said N first capacitances (C 4, C 3, C 2, C 1) are substantially equal; and wherein said first ends are connected to said input of said first amplifier and disconnected from said ground during said integrating phase, and wherein said first ends are connected to said ground and disconnected from said input of said first amplifier during said sampling phase; and a second DAC (120, 150) connected to said common node, wherein the second DAC is one of a second capacitive DAC comprising N second switches (SW LSB) and and a second amplifier, whereby the output of the second amplifier is connected to the common node, OR a resistive DAC comprising N resistances (R 4, R 3, R 2, R 1) connected in series between said voltage reference and said ground, N nodes between said N resistances and said ground, and N second switches (SW LSB) that selectively connect said common node to one of said N nodes; a control module for controlling said first and second switches (SW MSB, SW LSB), wherein the MSB bits of the the N bit digital value are allocated to the N first switches (SW MSB) and the LSB bits of the N bit digital value are allocated to the N second switches (SW LSB).