A dual input, low drop-out, LDO, voltage regulator (100; 220; 450) for providing a regulated voltage (VDDC) at an output port (112; 225; 453), the voltage regulator (100; 220; 450) comprising: - power amplification circuitry (106; 226, 224; 456, 454) having a first input port (102; 223; 452) couplable to a first power source (VDDCIN) and a first power stage (226; 456) coupled to the first input port (102; 223; 452), a second input port (104; 221; 451) couplable to a second power source (VBAT) and a second power stage (224; 454) coupled to the second input port (102; 221), wherein an output of the first power stage (226; 456) and an output of the second power stage (224; 454) are coupled to the output port (112; 225; 453), wherein the first power stage (226; 456) has at least a first intermediate power stage and a first power field-effect transistor, FET, and the second power stage (224; 454) has at least a second intermediate power stage and a second power FET, wherein at least the first power FET and the second power FET form a FET circuitry to operate in a saturation mode while drawing power provided at the first input port (102; 223; 452) from the first power source (VDDCIN); and - current-level switch circuitry (110; 229, 233; 462, 465) capable to sense a change in a current-level used to maintain the FET circuitry in the saturation mode, wherein the sensed change in the current-level is indicative for the first power FET being out of saturation and/or at a threshold of a saturation range, wherein, in response to a sensed change in the current-level, the FET circuity is capable to maintain the saturation mode by switching from the first power stage (226; 456) coupled to the first input port (223; 452) to the second power stage (224; 454) coupled to the second input port (221; 451), and further by, in response to the switch, the second power stage (224; 454) drawing power provided at the second input port from the second power source (VBAT) and the second power FET transitioning to saturation, so that in result, the FET circuity, which includes both the first and the second power stages (226, 224; 456, 454), as such maintains the saturation mode. - power amplification circuitry (106; 226, 224; 456, 454) having a first input port (102; 223; 452) couplable to a first power source (VDDCIN) and a first power stage (226; 456) coupled to the first input port (102; 223; 452), a second input port (104; 221; 451) couplable to a second power source (VBAT) and a second power stage (224; 454) coupled to the second input port (102; 221), wherein an output of the first power stage (226; 456) and an output of the second power stage (224; 454) are coupled to the output port (112; 225; 453), wherein the first power stage (226; 456) has at least a first intermediate power stage and a first power field-effect transistor, FET, and the second power stage (224; 454) has at least a second intermediate power stage and a second power FET, wherein at least the first power FET and the second power FET form a FET circuitry to operate in a saturation mode while drawing power provided at the first input port (102; 223; 452) from the first power source (VDDCIN); and - current-level switch circuitry (110; 229, 233; 462, 465) capable to sense a change in a current-level used to maintain the FET circuitry in the saturation mode, wherein the sensed change in the current-level is indicative for the first power FET being out of saturation and/or at a threshold of a saturation range, wherein, in response to a sensed change in the current-level, the FET circuity is capable to maintain the saturation mode by switching from the first power stage (226; 456) coupled to the first input port (223; 452) to the second power stage (224; 454) coupled to the second input port (221; 451), and further by, in response to the switch, the second power stage (224; 454) drawing power provided at the second input port from the second power source (VBAT) and the second power FET transitioning to saturation, so that in result, the FET circuity, which includes both the first and the second power stages (226, 224; 456, 454), as such maintains the saturation mode.