A five Transistor Static Random Access Memory, 5T SRAM, comprising a plurality of 5T SRAM cells, wherein a 5T SRAM cell of the plurality of 5T SRAM cells comprises: storage means configured to store data, the storage means coupled to a variable cell voltage (Vcell) and a ground voltage, wherein the storage means comprises a first inverter (M1, M2), comprising a first p-channel transistor and a first n-channel transistor, cross coupled to a second inverter (M3, M4), comprising a second p-channel transistor and a second n-channel transistor; a single access transistor as access means, coupled to a word line and a bit line, for controlling access operations on the storage means; and the 5T SRAM further comprising: control means (M6, M6') to generate a value of the variable cell voltage (V cell) for a write operation that is lower than the value of the variable cell voltage (V cell) for a read operation, the 5T SRAM being characterised in that the single access transistor is larger in size than each of the transistors (M1, M2, M3, M4) of the inverters; the first inverter and the second inverter of the 5T SRAM cell are balanced in size, a size of the first p-channel transistor is equal to a size of the second p-channel transistor, and a size of the first n-channel transistor is equal to a size of the second n-channel transistor; the 5T SRAM comprising means configured to: drive the word line to a supply voltage, float the bit line, and drive the variable cell voltage (Vcell) to the supply voltage during the read operation, wherein, drive the variable cell voltage (V cell) to an intermediate voltage (V H) that lies between the ground voltage and the supply voltage during a write operation to the 5T SRAM cell, when the 5T SRAM cell is selected, float the bit line and drive the variable cell voltage (V cell) to the supply voltage during a write operation to another 5T SRAM cell, when the 5T SRAM cell is half selected, and turn off the access means, couple the access means to the intermediate voltage (V H) and drive the variable cell voltage (V cell) to the intermediate voltage (V H) during a standby mode of operation. storage means configured to store data, the storage means coupled to a variable cell voltage (Vcell) and a ground voltage, wherein the storage means comprises a first inverter (M1, M2), comprising a first p-channel transistor and a first n-channel transistor, cross coupled to a second inverter (M3, M4), comprising a second p-channel transistor and a second n-channel transistor; a single access transistor as access means, coupled to a word line and a bit line, for controlling access operations on the storage means; and control means (M6, M6') to generate a value of the variable cell voltage (V cell) for a write operation that is lower than the value of the variable cell voltage (V cell) for a read operation, the 5T SRAM being characterised in that the single access transistor is larger in size than each of the transistors (M1, M2, M3, M4) of the inverters; the first inverter and the second inverter of the 5T SRAM cell are balanced in size, a size of the first p-channel transistor is equal to a size of the second p-channel transistor, and a size of the first n-channel transistor is equal to a size of the second n-channel transistor; the 5T SRAM comprising means configured to: drive the word line to a supply voltage, float the bit line, and drive the variable cell voltage (Vcell) to the supply voltage during the read operation, wherein, drive the variable cell voltage (V cell) to an intermediate voltage (V H) that lies between the ground voltage and the supply voltage during a write operation to the 5T SRAM cell, when the 5T SRAM cell is selected, float the bit line and drive the variable cell voltage (V cell) to the supply voltage during a write operation to another 5T SRAM cell, when the 5T SRAM cell is half selected, and turn off the access means, couple the access means to the intermediate voltage (V H) and drive the variable cell voltage (V cell) to the intermediate voltage (V H) during a standby mode of operation. drive the word line to a supply voltage, float the bit line, and drive the variable cell voltage (Vcell) to the supply voltage during the read operation, wherein, drive the variable cell voltage (V cell) to an intermediate voltage (V H) that lies between the ground voltage and the supply voltage during a write operation to the 5T SRAM cell, when the 5T SRAM cell is selected, float the bit line and drive the variable cell voltage (V cell) to the supply voltage during a write operation to another 5T SRAM cell, when the 5T SRAM cell is half selected, and turn off the access means, couple the access means to the intermediate voltage (V H) and drive the variable cell voltage (V cell) to the intermediate voltage (V H) during a standby mode of operation.