A ring oscillator in an FPGA, comprising: a plurality of LUT circuits as delay elements connected annularly, a selector circuit (11, 13, 15, 17) configured to apply input logic values to each of the LUT circuits; each of the LUT circuits including: a memory part having a plurality of individual memory cells respectively storing logic values, an output terminal connected to the next-stage LUT circuit, a first input terminal connected to an output terminal of the pre-stage LUT circuit, and a plurality of first gate circuits, each of the first gate circuits including: at least one p-type transistor and at least one n-type transistor, each of the first gate circuits being brought into an on state or an off state according to the logic value inputted to the first input terminal by the selector circuit (11, 13, 15, 17), and each of the first gate circuits entering a state of allowing the logic value in one of the individual memory cells or the inverted logic value of the logic value in one of the individual memory cells to pass to the output terminal side in the on state, and a state of not allowing the passage of the logic values stored in the individual memory cells to the output terminal side in the off state, the LUT circuits including first and second and third LUT circuits connected in order from the input side to the output side, the second LUT circuit and the third LUT circuit respectively having the same plurality of first gate circuits, characterized in that said selector circuit (11, 13, 15, 17) is configured to operate the LUT circuits in an oscillating mode by applying a first set of logic values and to operate the LUT circuits in a non-oscillating mode by applying a second set of logic values, wherein said second set of logic values is selected depending on whether the degradation of the p-type transistor or the degradation of the n-type transistor shall be suppressed and such that the logic value inputted to the first input terminal of the second LUT circuit and the logic value outputted from the output terminal of the second LUT circuit are the same in order to bring the same part of the first gate circuits into an off state in the second LUT circuit and the third LUT circuit respectively when the LUT circuits are operated in the non-oscillating mode. a plurality of LUT circuits as delay elements connected annularly, a selector circuit (11, 13, 15, 17) configured to apply input logic values to each of the LUT circuits; each of the LUT circuits including: a memory part having a plurality of individual memory cells respectively storing logic values, an output terminal connected to the next-stage LUT circuit, a first input terminal connected to an output terminal of the pre-stage LUT circuit, and a plurality of first gate circuits, a memory part having a plurality of individual memory cells respectively storing logic values, an output terminal connected to the next-stage LUT circuit, a first input terminal connected to an output terminal of the pre-stage LUT circuit, and a plurality of first gate circuits, each of the first gate circuits including: at least one p-type transistor and at least one n-type transistor, each of the first gate circuits being brought into an on state or an off state according to the logic value inputted to the first input terminal by the selector circuit (11, 13, 15, 17), and at least one p-type transistor and at least one n-type transistor, each of the first gate circuits being brought into an on state or an off state according to the logic value inputted to the first input terminal by the selector circuit (11, 13, 15, 17), and each of the first gate circuits entering a state of allowing the logic value in one of the individual memory cells or the inverted logic value of the logic value in one of the individual memory cells to pass to the output terminal side in the on state, and a state of not allowing the passage of the logic values stored in the individual memory cells to the output terminal side in the off state, the LUT circuits including first and second and third LUT circuits connected in order from the input side to the output side, the second LUT circuit and the third LUT circuit respectively having the same plurality of first gate circuits, characterized in that said selector circuit (11, 13, 15, 17) is configured to operate the LUT circuits in an oscillating mode by applying a first set of logic values and to operate the LUT circuits in a non-oscillating mode by applying a second set of logic values,