A space-efficient signal filter comprising: first mechanism (50, 58) for receiving a first signal being a narrowband signal and a second signal being a wideband signal and for separating the narrowband signal into even and odd samples, second mechanism (60, 62) for selectively filtering said first signal during a first mode of operation and filtering said second signal during a second mode of operation; third mechanism for generating control signals; and fourth mechanism (64, 68) for automatically configuring said second mechanism (60, 62) to operate in said first mode of operation or said second mode of operation based an said control signals, wherein said first signal has a first rate, and wherein said second signal has a second rate, and wherein said first signal and said second signal are ADC outputs, characterized in that said second mechanism (60, 62) includes plural filter banks (82, 86, 90, 94), each of said plural filter banks (82, 86, 90, 94) including one or more Multiply-Accumulate pipes (130, 142, 152, 144, 154, 146, 156), each of said MAC pipes (130, 142, 152, 144, 154, 146, 156) including one or more MAC blocks (200, 212, 214, 216), each of said one or more MAC blocks (200, 212, 214, 216) being associated with one or more corresponding coefficient memory data structures, said third mechanism includes a controller that further includes a fifth mechanism (68, 64, 230, 232) for selecting coefficients from each of said one or more memory data structures to apply to each of said one or more MAC blocks (200, 212, 214, 216), thereby selectively affecting a signal response of the filter, said coefficients are user-definable via a user interface to the controller; wherein said controller is user-configurable via said user interface; wherein said memory data structure is a stack; and wherein said fifth mechanism (68, 64. 230, 232) is responsive to coefficient-control signals from said controller, said coefficient-control signals indicating start addresses and end addresses for sets of coefficients to be applied to said one or more MAC blocks (200, 212, 214, 216), the second mechanism further includes a first filter block and a second filter block, each having two of the filter banks (82, 86, 90, 94), one filter bank (82, 90) of each of the filter blocks is connected to the first mechanism for receiving the even samples and for producing I signals, and another filter bank (86, 94) of each of the filter blocks is connected to the first mechanism for receiving the odd samples and for producing Q signals, and the filter includes an I/Q output configuration module for selectively combining I and Q output by said first filter block and said second filter block into desired filter outputs. first mechanism (50, 58) for receiving a first signal being a narrowband signal and a second signal being a wideband signal and for separating the narrowband signal into even and odd samples, second mechanism (60, 62) for selectively filtering said first signal during a first mode of operation and filtering said second signal during a second mode of operation; third mechanism for generating control signals; and fourth mechanism (64, 68) for automatically configuring said second mechanism (60, 62) to operate in said first mode of operation or said second mode of operation based an said control signals, wherein said first signal has a first rate, and wherein said second signal has a second rate, and wherein said first signal and said second signal are ADC outputs, characterized in that said second mechanism (60, 62) includes plural filter banks (82, 86, 90, 94), each of said plural filter banks (82, 86, 90, 94) including one or more Multiply-Accumulate pipes (130, 142, 152, 144, 154, 146, 156), each of said MAC pipes (130, 142, 152, 144, 154, 146, 156) including one or more MAC blocks (200, 212, 214, 216), each of said one or more MAC blocks (200, 212, 214, 216) being associated with one or more corresponding coefficient memory data structures, said third mechanism includes a controller that further includes a fifth mechanism (68, 64, 230, 232) for selecting coefficients from each of said one or more memory data structures to apply to each of said one or more MAC blocks (200, 212, 214, 216), thereby selectively affecting a signal response of the filter, said coefficients are user-definable via a user interface to the controller; wherein said controller is user-configurable via said user interface; wherein said memory data structure is a stack; and wherein said fifth mechanism (68, 64. 230, 232) is responsive to coefficient-control signals from said controller, said coefficient-control signals indicating start addresses and end addresses for sets of coefficients to be applied to said one or more MAC blocks (200, 212, 214, 216), the second mechanism further includes a first filter block and a second filter block, each having two of the filter banks (82, 86, 90, 94), one filter bank (82, 90) of each of the filter blocks is connected to the first mechanism for receiving the even samples and for producing I signals, and another filter bank (86, 94) of each of the filter blocks is connected to the first mechanism for receiving the odd samples and for producing Q signals, and the filter includes an I/Q output configuration module for selectively combining I and Q output by said first filter block and said second filter block into desired filter outputs.