A resistive memory storage apparatus, comprising: a memory array, comprising a plurality of memory cells, wherein each of the plurality of memory cells outputs a writing current (Id, 300) during a writing pulse width period (T_WPW); a first selecting transistor, coupled to the plurality of memory cells, wherein the first selecting transistor comprises a control end; and a memory controller, coupled to the first selecting transistor and the plurality of memory cells, configured to apply a first control voltage gradually changing to a first voltage level according to the writing current (Id, 300) to the control end of the first selecting transistor during a first resistance transition phase of the writing pulse width period (T_WPW), and set the first control voltage to the first voltage level during a first filament stabilization phase after the first resistance transition phase, so as to limit the writing current (Id, 300) to a first predetermined current value (Iref1), wherein the resistive memory storage apparatus is characterized in that the writing pulse width period (T_WPW) comprises a plurality of resistance transition phases (P0, P2, P4) and a plurality of filament stabilization phases (P1, P3, P5), and the writing current (Id, 300) is limited to the corresponding predetermined current value (Irefl, Iref2, Iref3) during each of the plurality of filament stabilization phases (P1, P3, P5), the plurality of resistance transition phases (P0, P2, P4) comprise the first resistance transition phase and a second resistance transition phase after the first filament stabilization phase, the plurality of filament stabilization phases (P1, P3, P5) comprise the first filament stabilization phase and a second filament stabilization phase after the second resistance transition phase, the memory controller is configured to gradually change the first control voltage to the first voltage level during the first resistance transition phase, and to gradually change the first control voltage (V1') to a second voltage level during the second resistance transition phase, and is configured to set the first control voltage (V1') to the second voltage level during the second filament stabilization phase, wherein the second voltage level is greater than the first voltage level, the writing current (Id, 300) is limited to a second predetermined current value (Iref2) greater than the first predetermined current value (Iref1) during the second filament stabilization phase. a memory array, comprising a plurality of memory cells, wherein each of the plurality of memory cells outputs a writing current (Id, 300) during a writing pulse width period (T_WPW); a first selecting transistor, coupled to the plurality of memory cells, wherein the first selecting transistor comprises a control end; and a memory controller, coupled to the first selecting transistor and the plurality of memory cells, configured to apply a first control voltage gradually changing to a first voltage level according to the writing current (Id, 300) to the control end of the first selecting transistor during a first resistance transition phase of the writing pulse width period (T_WPW), and set the first control voltage to the first voltage level during a first filament stabilization phase after the first resistance transition phase, so as to limit the writing current (Id, 300) to a first predetermined current value (Iref1), wherein the resistive memory storage apparatus is characterized in that the writing pulse width period (T_WPW) comprises a plurality of resistance transition phases (P0, P2, P4) and a plurality of filament stabilization phases (P1, P3, P5), and the writing current (Id, 300) is limited to the corresponding predetermined current value (Irefl, Iref2, Iref3) during each of the plurality of filament stabilization phases (P1, P3, P5), the plurality of resistance transition phases (P0, P2, P4) comprise the first resistance transition phase and a second resistance transition phase after the first filament stabilization phase, the plurality of filament stabilization phases (P1, P3, P5) comprise the first filament stabilization phase and a second filament stabilization phase after the second resistance transition phase, the memory controller is configured to gradually change the first control voltage to the first voltage level during the first resistance transition phase, and to gradually change the first control voltage (V1') to a second voltage level during the second resistance transition phase, and is configured to set the first control voltage (V1') to the second voltage level during the second filament stabilization phase, wherein the second voltage level is greater than the first voltage level, the writing current (Id, 300) is limited to a second predetermined current value (Iref2) greater than the first predetermined current value (Iref1) during the second filament stabilization phase.