A hearing instrument comprising: a control and processing circuit comprising: a first audio input channel for receipt of a first audio signal, a signal processor for receipt and processing of the first audio signal for generating a compensated microphone signal according to a hearing loss of a user; a class D output amplifier for receipt of the compensated microphone signal and generation of an amplified or buffered output signal for application to a miniature receiver or loudspeaker of the hearing instrument; wherein the class D output amplifier comprises an integrated circuit output driver for driving an audio transducer; said integrated circuit output driver comprising: a positive supply voltage rail (Vdd) and a negative supply voltage rail, a first half-bridge driver comprising a first PMOS transistor and a first NMOS transistor connected in series between the positive and negative supply voltage rails to form a first driver output at interconnected drain terminals of the first PMOS and NMOS transistors (16,18), - a first body terminal connected to a body of the first PMOS transistor for receipt of a first back bias voltage, - a second body terminal connected to a body of the first NMOS transistor for receipt of a second back bias voltage, - a bias voltage generator configured to adjust at least one of the first back bias voltage and the second back bias voltage to control on-resistance of at least one of the first PMOS transistor and first NMOS transistor. a first audio input channel for receipt of a first audio signal, a signal processor for receipt and processing of the first audio signal for generating a compensated microphone signal according to a hearing loss of a user; a class D output amplifier for receipt of the compensated microphone signal and generation of an amplified or buffered output signal for application to a miniature receiver or loudspeaker of the hearing instrument; wherein the class D output amplifier comprises an integrated circuit output driver for driving an audio transducer; said integrated circuit output driver comprising: a positive supply voltage rail (Vdd) and a negative supply voltage rail, a first half-bridge driver comprising a first PMOS transistor and a first NMOS transistor connected in series between the positive and negative supply voltage rails to form a first driver output at interconnected drain terminals of the first PMOS and NMOS transistors (16,18), - a first body terminal connected to a body of the first PMOS transistor for receipt of a first back bias voltage, - a second body terminal connected to a body of the first NMOS transistor for receipt of a second back bias voltage, - a bias voltage generator configured to adjust at least one of the first back bias voltage and the second back bias voltage to control on-resistance of at least one of the first PMOS transistor and first NMOS transistor. a positive supply voltage rail (Vdd) and a negative supply voltage rail, a first half-bridge driver comprising a first PMOS transistor and a first NMOS transistor connected in series between the positive and negative supply voltage rails to form a first driver output at interconnected drain terminals of the first PMOS and NMOS transistors (16,18), - a first body terminal connected to a body of the first PMOS transistor for receipt of a first back bias voltage, - a second body terminal connected to a body of the first NMOS transistor for receipt of a second back bias voltage, - a bias voltage generator configured to adjust at least one of the first back bias voltage and the second back bias voltage to control on-resistance of at least one of the first PMOS transistor and first NMOS transistor. - a first body terminal connected to a body of the first PMOS transistor for receipt of a first back bias voltage, - a second body terminal connected to a body of the first NMOS transistor for receipt of a second back bias voltage, - a bias voltage generator configured to adjust at least one of the first back bias voltage and the second back bias voltage to control on-resistance of at least one of the first PMOS transistor and first NMOS transistor.