A memory device, comprising: a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface; a memory cell formed on a first fin of the plurality of fins, comprising: spaced apart source and drain regions (36, 38) in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions, a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, a control gate that extends along and is insulated from the floating gate, characterized by an erase gate that extends along and is insulated from the source region, wherein the erase gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, and extends along and is insulated from an upper edge of the floating gate, and wherein the erase gate includes a notch facing the upper edge of the floating gate; a logic device formed on a second fin of the plurality of fins, wherein the first and second fins are formed as a single continuous fin, comprising: spaced apart logic source and logic drain regions (94, 96) in the second fin, with a logic channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the logic source and drain regions, and a logic gate that extends along the logic channel region, wherein the logic gate extends along and is insulated from the first and second side surfaces and the top surface of the second fin. a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface; a memory cell formed on a first fin of the plurality of fins, comprising: spaced apart source and drain regions (36, 38) in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions, a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, a control gate that extends along and is insulated from the floating gate, characterized by an erase gate that extends along and is insulated from the source region, wherein the erase gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, and extends along and is insulated from an upper edge of the floating gate, and wherein the erase gate includes a notch facing the upper edge of the floating gate; spaced apart source and drain regions (36, 38) in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions, a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, a control gate that extends along and is insulated from the floating gate, characterized by an erase gate that extends along and is insulated from the source region, wherein the erase gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, and extends along and is insulated from an upper edge of the floating gate, and wherein the erase gate includes a notch facing the upper edge of the floating gate; a logic device formed on a second fin of the plurality of fins, wherein the first and second fins are formed as a single continuous fin, comprising: spaced apart logic source and logic drain regions (94, 96) in the second fin, with a logic channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the logic source and drain regions, and a logic gate that extends along the logic channel region, wherein the logic gate extends along and is insulated from the first and second side surfaces and the top surface of the second fin. spaced apart logic source and logic drain regions (94, 96) in the second fin, with a logic channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the logic source and drain regions, and a logic gate that extends along the logic channel region, wherein the logic gate extends along and is insulated from the first and second side surfaces and the top surface of the second fin.