Circuit arrangement (74, 76) with a series circuit comprising at least two semiconductor switches (44, 78), each of which is connected via its control input to a respective actuation circuit (42, 82), which is configured such as to switch the semiconductor switches (44, 78) as a function of a predeterminable switching signal (S1, Sn), wherein, during a switching process, a switching behaviour of at least one of the actuation circuits (42, 82) is determined by at least one digital switching parameter, the value of which (K1*Uzk, K2*Uzk, K1 *Uzk, K2 *Uzk, K1(n)*Uzk, K2(n)*Uzk, dt1, dtn) can be changed, such that the switching behaviour can be set during operation, characterised in that the circuit arrangement is configured to switch all semiconductor switches (44, 78) in the series circuit into a blocking state, in order to interrupt a current, and a) at least one of the actuation circuits (42, 82) has a voltage monitoring facility, which is embodied so as to monitor a voltage (Ud, Uce, U1max, Un,max) falling over the semiconductor switch (44, 78) actuated by the actuation circuit (42, 82) and, if the voltage (Ud, Uce, U1max, Un,max) is greater than a limit value (K1*Uzk, K1 *Uzk, K1(n)*Uzk), to reduce the voltage (Ud, Uce, U1max, Un,max) by taking effect on the switching process, wherein the limit value (K1*Uzk, K1 *Uzk, K1(n)*Uzk) can be adjusted as a switching parameter of the actuation circuit (42, 82) for the control behaviour of said circuit, wherein the actuation circuit (42, 82) is embodied to limit the voltage over the semiconductor switch (44, 78) to a maximum value by the control behaviour, and/or b) at at least one of the actuation circuits (42, 82), a voltage end value (K2*Uzk, K2 *Uzk, K2(n)*Uzk) can be set as a switching parameter, which is intended to have a voltage (Ud, Uce, U1 Un) falling over the semiconductor switch (44, 78) actuated by the actuation circuit (42, 82) at the end of a switching process, wherein the actuation circuit (42, 82) is configured such as to produce at least one symmetry balancing pulse at the control input of the semiconductor switch (44, 78), for the adjustment of the voltage end value (K2*Uzk, K2 *Uzk, K2(n)*Uzk) at the end of the switching process. a) at least one of the actuation circuits (42, 82) has a voltage monitoring facility, which is embodied so as to monitor a voltage (Ud, Uce, U1max, Un,max) falling over the semiconductor switch (44, 78) actuated by the actuation circuit (42, 82) and, if the voltage (Ud, Uce, U1max, Un,max) is greater than a limit value (K1*Uzk, K1 *Uzk, K1(n)*Uzk), to reduce the voltage (Ud, Uce, U1max, Un,max) by taking effect on the switching process, wherein the limit value (K1*Uzk, K1 *Uzk, K1(n)*Uzk) can be adjusted as a switching parameter of the actuation circuit (42, 82) for the control behaviour of said circuit, wherein the actuation circuit (42, 82) is embodied to limit the voltage over the semiconductor switch (44, 78) to a maximum value by the control behaviour, b) at at least one of the actuation circuits (42, 82), a voltage end value (K2*Uzk, K2 *Uzk, K2(n)*Uzk) can be set as a switching parameter, which is intended to have a voltage (Ud, Uce, U1 Un) falling over the semiconductor switch (44, 78) actuated by the actuation circuit (42, 82) at the end of a switching process, wherein the actuation circuit (42, 82) is configured such as to produce at least one symmetry balancing pulse at the control input of the semiconductor switch (44, 78), for the adjustment of the voltage end value (K2*Uzk, K2 *Uzk, K2(n)*Uzk) at the end of the switching process.