An image sensor arrangement for determining a three-dimensional image, comprising: - an image sensor comprising an array of global shutter pixels, - a control unit (CTRL) configured to drive the image sensor in an imaging mode and in a time-of-flight mode, wherein: - each pixel from the array of global shutter pixels comprises a p-type epitaxial layer, denoted p-epi, a p-well region, a pinned photodiode formed by a p+ surface implant and a deeper n implant, an n+ implant region, and a p++ substrate, - the n+ and p+ implant regions are isolated also by shallow trench isolation STI, - the pinned photodiode comprises a surface pinned at ground potential by the p+ surface implant layer, said p+ implant layer being connected to the ground potential, - the pinned photodiode is formed by the deeper n-type implant n under this pinning implant layer, which forms a junction with the p+ surface implant and the p-epitaxial layer p-epi, and wherein: - the pinned photodiode comprises charge transfer gates, including a transfer gate øt, a memory gate øm and a reset gate ør, as well as a floating diffusion fd, a reset transistor RST, and an anti-blooming charge drain AB, and - the pixel comprises an in-pixel charge storage m under a storage or memory gate øm; - the pixels of the array of global shutter pixels are operable in both the imaging mode and the time-of-flight mode, - in the imaging mode, the control unit (CTRL) drives at least some of the pixels according to an imaging timing sequence, - in the time-of-flight mode, the control unit (CTRL) drives at least some of the pixels according to a time-of-flight, TOF, timing sequence, and - at least a first subset of pixels are operated with a phase delay with respect to at least a second subset of pixels according to a first phase and a second phase (01, Ø2), respectively. - an image sensor comprising an array of global shutter pixels, - a control unit (CTRL) configured to drive the image sensor in an imaging mode and in a time-of-flight mode, - each pixel from the array of global shutter pixels comprises a p-type epitaxial layer, denoted p-epi, a p-well region, a pinned photodiode formed by a p+ surface implant and a deeper n implant, an n+ implant region, and a p++ substrate, a p-type epitaxial layer, denoted p-epi, a p-well region, a pinned photodiode formed by a p+ surface implant and a deeper n implant, an n+ implant region, and a p++ substrate, - the n+ and p+ implant regions are isolated also by shallow trench isolation STI, - the pinned photodiode comprises a surface pinned at ground potential by the p+ surface implant layer, said p+ implant layer being connected to the ground potential, - the pinned photodiode is formed by the deeper n-type implant n under this pinning implant layer, which forms a junction with the p+ surface implant and the p-epitaxial layer p-epi, and wherein: - the pinned photodiode comprises charge transfer gates, including a transfer gate øt, a memory gate øm and a reset gate ør, as well as a floating diffusion fd, a reset transistor RST, and an anti-blooming charge drain AB, and - the pixel comprises an in-pixel charge storage m under a storage or memory gate øm; - the pixels of the array of global shutter pixels are operable in both the imaging mode and the time-of-flight mode, - in the imaging mode, the control unit (CTRL) drives at least some of the pixels according to an imaging timing sequence, - in the time-of-flight mode, the control unit (CTRL) drives at least some of the pixels according to a time-of-flight, TOF, timing sequence, and - at least a first subset of pixels are operated with a phase delay with respect to at least a second subset of pixels according to a first phase and a second phase (01, Ø2), respectively.