An apparatus, comprising: a driver circuit mounted on a circuit board and having at least one gate drive terminal, said driver circuit being configured to produce a gate drive signal on said at least one gate drive terminal; a first semiconductor switch mounted on said circuit board and having a first gate, a first drain, and a first source; a second semiconductor switch mounted on said circuit board and having a second gate, a second drain, and a second source, said first and second semiconductor switches being connected in a paralleled arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected; a first electrical connection between said gate drive terminal of said driver circuit and said first gate of said first semiconductor switch wherein said first electrical connection has a first length and comprises electrically conductive material with a first inductance associated therewith; a second electrical connection, different from said first electrical connection, between said gate drive terminal and said second gate of said second semiconductor switch wherein said second electrical connection has a second length and comprises electrically conductive material with a second inductance associated therewith, said second length being longer than said first length such that said second inductance is larger than said first inductance; and an impedance element associated with said first semiconductor switch selected from a group comprising (i) a resistor that is electrically connected in series in said first electrical connection and (ii) a capacitor that is electrically connected across said first gate and said first source of said first semiconductor switch, said impedance element having an impedance value configured to delay a first turn-off time of said first semiconductor switch relative to a second turn-off time of said second semiconductor switch. a driver circuit mounted on a circuit board and having at least one gate drive terminal, said driver circuit being configured to produce a gate drive signal on said at least one gate drive terminal; a first semiconductor switch mounted on said circuit board and having a first gate, a first drain, and a first source; a second semiconductor switch mounted on said circuit board and having a second gate, a second drain, and a second source, said first and second semiconductor switches being connected in a paralleled arrangement wherein (i) said first drain and said second drain are electrically connected and (ii) said first source and said second source are electrically connected; a first electrical connection between said gate drive terminal of said driver circuit and said first gate of said first semiconductor switch wherein said first electrical connection has a first length and comprises electrically conductive material with a first inductance associated therewith; a second electrical connection, different from said first electrical connection, between said gate drive terminal and said second gate of said second semiconductor switch wherein said second electrical connection has a second length and comprises electrically conductive material with a second inductance associated therewith, said second length being longer than said first length such that said second inductance is larger than said first inductance; and an impedance element associated with said first semiconductor switch selected from a group comprising (i) a resistor that is electrically connected in series in said first electrical connection and (ii) a capacitor that is electrically connected across said first gate and said first source of said first semiconductor switch, said impedance element having an impedance value configured to delay a first turn-off time of said first semiconductor switch relative to a second turn-off time of said second semiconductor switch.