An interface for mitigating electromagnetic interference, EMI, the interface comprising: a printed circuit board having: first and second sides laterally separated from one another by an interface region; one or more circuit components attached to the second side; one or more pairs of input pads and output pads, each of the one or more pairs straddling the interface region with the input pads located on the first side of the printed circuit board and the output pads located on the second side of the printed circuit board; one or more EMI line filters connected between each of the one or more pairs of input and output pads; signal planes comprising first and second metallization layers (42A-42D) patterned with traces for conducting filterable signals and non-filterable signals, respectively, the first metallization layers (42A; 42B) sandwiched between first and second ground planes (40A-40C), the second metallization layers (42C; 42D) sandwiched between third and fourth ground planes (40D-40F), wherein the first and second metallization layers extend throughout both first and second sides of the printed circuit board, wherein the filterable signals are filtered by an associated one of the one or more EMI line filters while passing from the first side to the second side of the printed circuit board, so as to provide the one or more circuit components on the second side of the printed circuit board access to both filtered and non-filterable signals; a ground barrier disposed in the printed circuit board proximate the interface region; a clamshell housing containing the printed circuit board within, the clamshell housing having: a partition wall aligned with the interface region so as to form first side and second side EMI cages within the clamshell house, the first side of the printed circuit board residing in the first EMI cage and the second side of the printed circuit board residing in the second EMI cage. first and second sides laterally separated from one another by an interface region; one or more circuit components attached to the second side; one or more pairs of input pads and output pads, each of the one or more pairs straddling the interface region with the input pads located on the first side of the printed circuit board and the output pads located on the second side of the printed circuit board; one or more EMI line filters connected between each of the one or more pairs of input and output pads; signal planes comprising first and second metallization layers (42A-42D) patterned with traces for conducting filterable signals and non-filterable signals, respectively, the first metallization layers (42A; 42B) sandwiched between first and second ground planes (40A-40C), the second metallization layers (42C; 42D) sandwiched between third and fourth ground planes (40D-40F), wherein the first and second metallization layers extend throughout both first and second sides of the printed circuit board, wherein the filterable signals are filtered by an associated one of the one or more EMI line filters while passing from the first side to the second side of the printed circuit board, so as to provide the one or more circuit components on the second side of the printed circuit board access to both filtered and non-filterable signals; a ground barrier disposed in the printed circuit board proximate the interface region; a clamshell housing containing the printed circuit board within, the clamshell housing having: a partition wall aligned with the interface region so as to form first side and second side EMI cages within the clamshell house, the first side of the printed circuit board residing in the first EMI cage and the second side of the printed circuit board residing in the second EMI cage.