A power management integrated circuit, PMIC, comprising: a first pin, arranged to receive a first reference voltage; a second pin, arranged to receive a second reference voltage that is different from the first reference voltage; a third pin, arranged to output a pulsed voltage (V LX); a controller; a fourth pin, arranged to receive an auxiliary reference voltage that is to be supplied to the controller of the PMIC; and a switching regulator (102, 200, 600, 700, 900), arranged to generate the pulsed voltage, wherein the switching regulator (102,200, 600, 700, 900) comprises: a first switch circuit, having a first connection node coupled to the first pin, and a second connection node coupled to the third pin; a second switch circuit, having a first connection node coupled to the second pin, and a second connection node coupled to the third pin; and a protection circuit(108, 206, 606, 706, 906), arranged to sense a voltage level at the first connection node of the first switch circuit, and selectively enable an auxiliary current path (208, 608) in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path (208, 608) and at least the first switch circuit are arranged in a parallel connection fashion, characterized in that the protection circuit (108, 206, 606, 706, 906) comprises an auxiliary transistor having a gate coupled to the fourth pin, a source coupled to the first pin, and a drain coupled either to the second pin or to the third pin, to automatically enable the auxiliary current path (208, 608) according to a difference between the auxiliary reference voltage and the voltage level at the first connection node of the first switch circuit. a first pin, arranged to receive a first reference voltage; a second pin, arranged to receive a second reference voltage that is different from the first reference voltage; a third pin, arranged to output a pulsed voltage (V LX); a controller; a fourth pin, arranged to receive an auxiliary reference voltage that is to be supplied to the controller of the PMIC; and a switching regulator (102, 200, 600, 700, 900), arranged to generate the pulsed voltage, wherein the switching regulator (102,200, 600, 700, 900) comprises: a first switch circuit, having a first connection node coupled to the first pin, and a second connection node coupled to the third pin; a second switch circuit, having a first connection node coupled to the second pin, and a second connection node coupled to the third pin; and a protection circuit(108, 206, 606, 706, 906), arranged to sense a voltage level at the first connection node of the first switch circuit, and selectively enable an auxiliary current path (208, 608) in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path (208, 608) and at least the first switch circuit are arranged in a parallel connection fashion, characterized in that the protection circuit (108, 206, 606, 706, 906) comprises an auxiliary transistor having a gate coupled to the fourth pin, a source coupled to the first pin, and a drain coupled either to the second pin or to the third pin, to automatically enable the auxiliary current path (208, 608) according to a difference between the auxiliary reference voltage and the voltage level at the first connection node of the first switch circuit. a first switch circuit, having a first connection node coupled to the first pin, and a second connection node coupled to the third pin; a second switch circuit, having a first connection node coupled to the second pin, and a second connection node coupled to the third pin; and a protection circuit(108, 206, 606, 706, 906), arranged to sense a voltage level at the first connection node of the first switch circuit, and selectively enable an auxiliary current path (208, 608) in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path (208, 608) and at least the first switch circuit are arranged in a parallel connection fashion, characterized in that the protection circuit (108, 206, 606, 706, 906) comprises an auxiliary transistor having a gate coupled to the fourth pin, a source coupled to the first pin, and a drain coupled either to the second pin or to the third pin, to automatically enable the auxiliary current path (208, 608) according to a difference between the auxiliary reference voltage and the voltage level at the first connection node of the first switch circuit.