A method of secure key generation for a semiconductor device in a trust and secure mode, the method comprising: writing a predetermined write pattern to a particular address of a volatile memory of the semiconductor device, wherein the volatile memory comprises a plurality of bit lines; reading data from the particular address while applying a first set of operating variables to the volatile memory, subsequent to the writing, wherein the first set of operating variables comprises at least one of a first operating voltage and a first operating temperature; and sensing a first plurality of mismatches during the reading, wherein the semiconductor device comprises a plurality of latches and a plurality of sense amplifiers coupled to the plurality of bit lines, characterized in that the predetermined write pattern comprises the same data values, the particular address of a volatile memory is a particular row address, the first plurality of mismatches is a first plurality of timing mismatches, each latch of the plurality of latches is coupled between a respective pair of the plurality of sense amplifiers, and each latch of the plurality of latches is configured to output one of a first data value and a second data value to indicate a respective timing mismatch between outputs of the respective pair of the plurality of sense amplifiers; and wherein the method further comprises determining an entropy ratio for the particular address, wherein the entropy ratio is associated with the first set of operating variables, and the entropy ratio is equivalent to a ratio of a first number of latches that output the first data value to a second number of latches that output the second data value during the sensing. writing a predetermined write pattern to a particular address of a volatile memory of the semiconductor device, wherein the volatile memory comprises a plurality of bit lines; reading data from the particular address while applying a first set of operating variables to the volatile memory, subsequent to the writing, wherein the first set of operating variables comprises at least one of a first operating voltage and a first operating temperature; and sensing a first plurality of mismatches during the reading, wherein the semiconductor device comprises a plurality of latches and a plurality of sense amplifiers coupled to the plurality of bit lines, characterized in that the predetermined write pattern comprises the same data values, the particular address of a volatile memory is a particular row address, the first plurality of mismatches is a first plurality of timing mismatches, each latch of the plurality of latches is coupled between a respective pair of the plurality of sense amplifiers, and each latch of the plurality of latches is configured to output one of a first data value and a second data value to indicate a respective timing mismatch between outputs of the respective pair of the plurality of sense amplifiers; and wherein the method further comprises determining an entropy ratio for the particular address, wherein the entropy ratio is associated with the first set of operating variables, and the entropy ratio is equivalent to a ratio of a first number of latches that output the first data value to a second number of latches that output the second data value during the sensing.