An image sensor comprising an array of pixels and control logic which is arranged to control operation of the pixels, each of the pixels comprising: a pinned photodiode; a first sense node having a capacitance (Cs); a second sense node which is connected to a parasitic capacitance or an explicit capacitive device; a transfer gate connected between the pinned photodiode and the first sense node; a first reset transistor connected between a voltage reference line and the second sense node; a second reset transistor connected between the first sense node and the second sense node; and a buffer amplifier having an input connected to the first sense node; the image sensor further comprising: a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array; a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array; and wherein an operational cycle of the pixels comprises a readout period and a non-readout period and the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in the low gain conversion gain mode the control logic is arranged to operate the second reset control line to continuously switch on the second reset transistor during the readout period of the operational cycle of the pixels, characterised in that the control logic is arranged, in the high conversion gain mode, to operate the first reset control line to continuously switch on the first reset transistor during the readout period of the operational cycle of the pixels. a pinned photodiode; a first sense node having a capacitance (Cs); a second sense node which is connected to a parasitic capacitance or an explicit capacitive device; a transfer gate connected between the pinned photodiode and the first sense node; a first reset transistor connected between a voltage reference line and the second sense node; a second reset transistor connected between the first sense node and the second sense node; and a buffer amplifier having an input connected to the first sense node; the image sensor further comprising: a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array; a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array; and wherein an operational cycle of the pixels comprises a readout period and a non-readout period and the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in the low gain conversion gain mode the control logic is arranged to operate the second reset control line to continuously switch on the second reset transistor during the readout period of the operational cycle of the pixels, characterised in that the control logic is arranged, in the high conversion gain mode, to operate the first reset control line to continuously switch on the first reset transistor during the readout period of the operational cycle of the pixels. a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array; a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array; and wherein an operational cycle of the pixels comprises a readout period and a non-readout period and the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in the low gain conversion gain mode the control logic is arranged to operate the second reset control line to continuously switch on the second reset transistor during the readout period of the operational cycle of the pixels, characterised in that the control logic is arranged, in the high conversion gain mode, to operate the first reset control line to continuously switch on the first reset transistor during the readout period of the operational cycle of the pixels.