A memory array circuit comprising: a plurality of memory rows, each comprising: a plurality of memory bit cell circuits; and a word line coupled to each of the plurality of memory bit cell circuits; an inverted delay clock circuit configured to: receive a latch clock signal (CLK LAT) comprising one of a first clock state and a second clock state; generate an inverted delay clock signal (CLK DLY) comprising the second clock state in response to receiving the latch clock signal (CLK LAT) comprising the first clock state; and generate the inverted delay clock signal (CLK DLY) comprising the first clock state in response to receiving the latch clock signal (CLK LAT) comprising the second clock state; and a plurality of word line latch circuits each coupled to the word line of one of the plurality of memory rows and configured to: receive the latch clock signal (CLK LAT) and the inverted delay clock signal (CLK DLY); receive an address decode signal comprising a decode state comprising one of an active state and an inactive state; in response to the latch clock signal (CLK LAT) comprising the first clock state and the inverted delay clock signal (CLK DLY) comprising the first clock state, store the decode state of the received address decode signal and generate a word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows; hold the word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal (CLK LAT) comprising the first clock state and the inverted delay clock signal (CLK DLY) comprising the second clock state; and generate the word line signal comprising the inactive state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal (CLK LAT) comprising the second clock state. a plurality of memory rows, each comprising: a plurality of memory bit cell circuits; and a word line coupled to each of the plurality of memory bit cell circuits; a plurality of memory bit cell circuits; and a word line coupled to each of the plurality of memory bit cell circuits; an inverted delay clock circuit configured to: receive a latch clock signal (CLK LAT) comprising one of a first clock state and a second clock state; generate an inverted delay clock signal (CLK DLY) comprising the second clock state in response to receiving the latch clock signal (CLK LAT) comprising the first clock state; and generate the inverted delay clock signal (CLK DLY) comprising the first clock state in response to receiving the latch clock signal (CLK LAT) comprising the second clock state; and receive a latch clock signal (CLK LAT) comprising one of a first clock state and a second clock state; generate an inverted delay clock signal (CLK DLY) comprising the second clock state in response to receiving the latch clock signal (CLK LAT) comprising the first clock state; and generate the inverted delay clock signal (CLK DLY) comprising the first clock state in response to receiving the latch clock signal (CLK LAT) comprising the second clock state; and a plurality of word line latch circuits each coupled to the word line of one of the plurality of memory rows and configured to: receive the latch clock signal (CLK LAT) and the inverted delay clock signal (CLK DLY); receive an address decode signal comprising a decode state comprising one of an active state and an inactive state; in response to the latch clock signal (CLK LAT) comprising the first clock state and the inverted delay clock signal (CLK DLY) comprising the first clock state, store the decode state of the received address decode signal and generate a word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows; hold the word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal (CLK LAT) comprising the first clock state and the inverted delay clock signal (CLK DLY) comprising the second clock state; and generate the word line signal comprising the inactive state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal (CLK LAT) comprising the second clock state. receive the latch clock signal (CLK LAT) and the inverted delay clock signal (CLK DLY); receive an address decode signal comprising a decode state comprising one of an active state and an inactive state; in response to the latch clock signal (CLK LAT) comprising the first clock state and the inverted delay clock signal (CLK DLY) comprising the first clock state, store the decode state of the received address decode signal and generate a word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows; hold the word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal (CLK LAT) comprising the first clock state and the inverted delay clock signal (CLK DLY) comprising the second clock state; and generate the word line signal comprising the inactive state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal (CLK LAT) comprising the second clock state.