An apparatus for encoding with Low-Density Parity Check codes comprising means to receive an information bit sequence to encode and a sparse matrix multiplier (1, 2, 3, 4, 10, 13) that includes ✔ splitter means configured to split the information bit sequence into packets of bits of size γ·δ·ε, where γ, δ, ε are non-zero, positive integers; and ✔ a chain of components (16, 17, 18, 19, 20), whereby the components include: • memory means configured to store sets with equal number of δ·ε bits, which sets form a packet; • four cascaded processing means (17, 18, 19, 20) configured to perform binary operations over the packets, and configured to base the binary operations on circulant blocks, with each circulant block being established by cyclic permutation of a diagonal or anti-diagonal matrix and defined by a single shift parameter, including ▪ level-1 shifter means configured to shift sets of δ·ε bits within a packet followed by ▪ level-2 shifter means configured to shifts sets of ε bits within a set of δ·ε bits followed by ▪ sign shifter means between the level-2 shifter means and level-3 shifter means configured to flip sets of ε bits within a set of δ·ε bits followed by ▪ the level-3 shifter means configured to shift bits within a set of ε bits whereby the level-2 shifter means and the level-3 shifter means are configured to base the binary operations on circulant blocks defined by the single shift parameter and the sign shifter means is configured to base the binary operations on the sign of the single shift parameter ✔ a controller that is configured to provide the shift parameters to the processing means (17, 18, 20) and the memory means; the encoding apparatus further including means to receive the packets after the packets have been processed by the sparse matrix multiplier and to provide a codeword that corresponds to the information bit sequence. ✔ splitter means configured to split the information bit sequence into packets of bits of size γ·δ·ε, where γ, δ, ε are non-zero, positive integers; and ✔ a chain of components (16, 17, 18, 19, 20), whereby the components include: • memory means configured to store sets with equal number of δ·ε bits, which sets form a packet; • four cascaded processing means (17, 18, 19, 20) configured to perform binary operations over the packets, and configured to base the binary operations on circulant blocks, with each circulant block being established by cyclic permutation of a diagonal or anti-diagonal matrix and defined by a single shift parameter, including ▪ level-1 shifter means configured to shift sets of δ·ε bits within a packet followed by ▪ level-2 shifter means configured to shifts sets of ε bits within a set of δ·ε bits followed by ▪ sign shifter means between the level-2 shifter means and level-3 shifter means configured to flip sets of ε bits within a set of δ·ε bits followed by ▪ the level-3 shifter means configured to shift bits within a set of ε bits whereby the level-2 shifter means and the level-3 shifter means are configured to base the binary operations on circulant blocks defined by the single shift parameter and the sign shifter means is configured to base the binary operations on the sign of the single shift parameter • memory means configured to store sets with equal number of δ·ε bits, which sets form a packet; • four cascaded processing means (17, 18, 19, 20) configured to perform binary operations over the packets, and configured to base the binary operations on circulant blocks, with each circulant block being established by cyclic permutation of a diagonal or anti-diagonal matrix and defined by a single shift parameter, including ▪ level-1 shifter means configured to shift sets of δ·ε bits within a packet followed by ▪ level-2 shifter means configured to shifts sets of ε bits within a set of δ·ε bits followed by ▪ sign shifter means between the level-2 shifter means and level-3 shifter means configured to flip sets of ε bits within a set of δ·ε bits followed by ▪ the level-3 shifter means configured to shift bits within a set of ε bits whereby the level-2 shifter means and the level-3 shifter means are configured to base the binary operations on circulant blocks defined by the single shift parameter and the sign shifter means is configured to base the binary operations on the sign of the single shift parameter ▪ level-1 shifter means configured to shift sets of δ·ε bits within a packet followed by ▪ level-2 shifter means configured to shifts sets of ε bits within a set of δ·ε bits followed by ▪ sign shifter means between the level-2 shifter means and level-3 shifter means configured to flip sets of ε bits within a set of δ·ε bits followed by ▪ the level-3 shifter means configured to shift bits within a set of ε bits whereby the level-2 shifter means and the level-3 shifter means are configured to base the binary operations on circulant blocks defined by the single shift parameter and the sign shifter means is configured to base the binary operations on the sign of the single shift parameter ✔ a controller that is configured to provide the shift parameters to the processing means (17, 18, 20) and the memory means;