A wireless device (104 1, 104 2, 104 3...104 n) configured with a discontinuous reception cycle which comprises a reachability cycle, a sleep cycle, and a synchronization cycle, the wireless device comprising: a processor (118 1, 118 2, 118 3...118 n); and a memory (120 1, 120 2, 120 3...120 n) that stores processor-executable instructions, wherein the processor interfaces with the memory to execute the processor-executable instructions, whereby said wireless device is operable to: compute (202, 504), during the reachability cycle, a time (T W) for the synchronization cycle during which a synchronization procedure is to be performed; and set (204, 504) a timer with a time (T d) based on the computed time (T W) to wake up from the sleep cycle and perform the synchronization procedure, wherein the reachability cycle occurs before the sleep cycle, and the sleep cycle occurs before the synchronization cycle; and the wireless device is characterized to compute the time (T W) for the synchronization cycle as follows: estimate (202a, 504a) a total accumulated frequency drift of the sleep cycle, wherein the total accumulated frequency drift is equal to Δf*T S, wherein Δf is a frequency drift per unit time of a local oscillator in the wireless device, and wherein T S is an estimated duration of the sleep cycle; compute (202b, 504b) a number of Frequency Correction Bursts (FBs), Synchronization Bursts (SBs), and Normal Bursts (NBs) to be received to enable a correction of the estimated total accumulated frequency drift; and compute (202c, 504c) the time (T W) for the synchronization cycle based on (i) a known frame structure which indicates how many FBs, SBs, and NBs are expected during a certain period of time, (ii) a known amount of frequency drift that can be corrected from each reception of FB, SB, and NB, and (iii) the computed number of FBs, SBs, and NBs to be received to enable the correction of the estimated total accumulated frequency drift. a processor (118 1, 118 2, 118 3...118 n); and a memory (120 1, 120 2, 120 3...120 n) that stores processor-executable instructions, wherein the processor interfaces with the memory to execute the processor-executable instructions, whereby said wireless device is operable to: compute (202, 504), during the reachability cycle, a time (T W) for the synchronization cycle during which a synchronization procedure is to be performed; and set (204, 504) a timer with a time (T d) based on the computed time (T W) to wake up from the sleep cycle and perform the synchronization procedure, compute (202, 504), during the reachability cycle, a time (T W) for the synchronization cycle during which a synchronization procedure is to be performed; and set (204, 504) a timer with a time (T d) based on the computed time (T W) to wake up from the sleep cycle and perform the synchronization procedure, wherein the reachability cycle occurs before the sleep cycle, and the sleep cycle occurs before the synchronization cycle; and the wireless device is characterized to compute the time (T W) for the synchronization cycle as follows: estimate (202a, 504a) a total accumulated frequency drift of the sleep cycle, wherein the total accumulated frequency drift is equal to Δf*T S, wherein Δf is a frequency drift per unit time of a local oscillator in the wireless device, and wherein T S is an estimated duration of the sleep cycle; compute (202b, 504b) a number of Frequency Correction Bursts (FBs), Synchronization Bursts (SBs), and Normal Bursts (NBs) to be received to enable a correction of the estimated total accumulated frequency drift; and compute (202c, 504c) the time (T W) for the synchronization cycle based on (i) a known frame structure which indicates how many FBs, SBs, and NBs are expected during a certain period of time, (ii) a known amount of frequency drift that can be corrected from each reception of FB, SB, and NB, and (iii) the computed number of FBs, SBs, and NBs to be received to enable the correction of the estimated total accumulated frequency drift. estimate (202a, 504a) a total accumulated frequency drift of the sleep cycle, wherein the total accumulated frequency drift is equal to Δf*T S, wherein Δf is a frequency drift per unit time of a local oscillator in the wireless device, and wherein T S is an estimated duration of the sleep cycle; compute (202b, 504b) a number of Frequency Correction Bursts (FBs), Synchronization Bursts (SBs), and Normal Bursts (NBs) to be received to enable a correction of the estimated total accumulated frequency drift; and compute (202c, 504c) the time (T W) for the synchronization cycle based on (i) a known frame structure which indicates how many FBs, SBs, and NBs are expected during a certain period of time, (ii) a known amount of frequency drift that can be corrected from each reception of FB, SB, and NB, and (iii) the computed number of FBs, SBs, and NBs to be received to enable the correction of the estimated total accumulated frequency drift.