A method for writing a shift register comprising a plurality of the register cells, each register cell comprising a differential amplifying portion comprising a first inverter coupled to a second inverter such as to form an unbalanced flip-flop circuit, wherein the first inverter comprises a first PMOS transistor connected in series with a first NMOS transistor forming an input node, and the second inverter comprises a second PMOS transistor connected in series with a second NMOS transistor forming an output node, the gates of the first PMOS transistor and the first NMOS transistor being coupled to the drain of the second PMOS transistor and to the source of the second NMOS transistor, and the sources of the first and second PMOS transistors (P1, P2) being connected to a first bit line and a second bit line, respectively; a first magnetic tunnel junction having its first terminal electrically connected to the drain of the first NMOS transistor, and a second magnetic tunnel junction having its first terminal electrically connected to the drain of the second NMOS transistor; a first source line (S L0) connected to the second terminal of the first magnetic tunnel junction and a second source line (S L1) connected to the second terminal of the second magnetic tunnel junction; each register cell being connected in series to the adjacent register cell via a shift transistor which is connected between an output node of one register cell and input node of an adjacent register cell, so as to chain together the two inverters (3, 3') of the adjacent register cells and to shift data from the output node of one register cell to the input node of the adjacent register cell; the method comprising: selecting, in the shift register, the first or second magnetic tunnel junctions (6, 6') having the same magnetic state, by shifting an information sequence data such as to provide a high voltage V DD at the input node or the output node (Qn) of the register cell; heating the selected magnetic tunnel junctions (6, 6') by passing a heating current through the selected magnetic tunnel junctions (6, 6') via the source line (S L0, S L1); once the selected magnetic tunnel junctions (6, 6') have reached the predetermined high threshold temperature, changing the magnetic state of the selected magnetic tunnel junctions (6, 6') by applying an external magnetic field to the selected magnetic tunnel junctions (6, 6') or by passing a current through the selected magnetic tunnel junctions (6, 6'); characterized in that the signal of the first or second source line (S L0, S L1) connected to the second terminal of the selected first or second magnetic tunnel junctions (6, 6') is set to a low signal, such as to have enough voltage across the selected first or second NMOS transistor (N1, N2) and the magnetic tunnel junction (6, 6') connected thereto, such that the heating current passing through the selected magnetic tunnel junctions (6, 6') is high enough to heat the selected magnetic tunnel junctions (6, 6') to a predetermined high threshold temperature. selecting, in the shift register, the first or second magnetic tunnel junctions (6, 6') having the same magnetic state, by shifting an information sequence data such as to provide a high voltage V DD at the input node or the output node (Qn) of the register cell; heating the selected magnetic tunnel junctions (6, 6') by passing a heating current through the selected magnetic tunnel junctions (6, 6') via the source line (S L0, S L1); once the selected magnetic tunnel junctions (6, 6') have reached the predetermined high threshold temperature, changing the magnetic state of the selected magnetic tunnel junctions (6, 6') by applying an external magnetic field to the selected magnetic tunnel junctions (6, 6') or by passing a current through the selected magnetic tunnel junctions (6, 6'); characterized in that the signal of the first or second source line (S L0, S L1) connected to the second terminal of the selected first or second magnetic tunnel junctions (6, 6') is set to a low signal, such as to have enough voltage across the selected first or second NMOS transistor (N1, N2) and the magnetic tunnel junction (6, 6') connected thereto, such that the heating current passing through the selected magnetic tunnel junctions (6, 6') is high enough to heat the selected magnetic tunnel junctions (6, 6') to a predetermined high threshold temperature.