A system for collecting tissue images comprising: a patient interface module and a catheter having a sensing head near the distal end, the sensing head comprising an array of transducer elements, wherein the transducer elements are configured to convert echo signals received from tissue into electrical signals to be processed by the PIM, wherein the PIM comprises: a pulse transmitter circuit; a receive amplifier configured to amplify the electrical signals into an amplified signal; an analog to digital converter circuit configured to receive the amplified signal and to provide a digital signal; a reconstruction field programmable gate array circuit (FPGA) circuit configured to provide image-reconstructed data from the digital signal provided by the ADC; and a communication protocol circuit which is provided with the image-reconstructed data from the FPGA circuit and configured to transfer the image-reconstructed data to an IVUS control system; wherein digitization points are provided by the ADC and interleaved into sampling points (401, 402) by the FPGA circuit such that the FPGA circuit operates at approximately 1/2 the frequency of the ADC; and wherein the FPGA circuit comprises: a quadrature internal conditioning circuit; a buffer circuit; and a reconstruction circuit comprising: a circuit to measure a phase of a signal; and a flavor interpolation circuit, wherein the circuit to measure the phase of the signal is configured to form two complex numbers from the digitization points for each cycle of the center frequency of the amplified signal. a patient interface module and a catheter having a sensing head near the distal end, the sensing head comprising an array of transducer elements, wherein the transducer elements are configured to convert echo signals received from tissue into electrical signals to be processed by the PIM, wherein the PIM comprises: a pulse transmitter circuit; a receive amplifier configured to amplify the electrical signals into an amplified signal; an analog to digital converter circuit configured to receive the amplified signal and to provide a digital signal; a reconstruction field programmable gate array circuit (FPGA) circuit configured to provide image-reconstructed data from the digital signal provided by the ADC; and a communication protocol circuit which is provided with the image-reconstructed data from the FPGA circuit and configured to transfer the image-reconstructed data to an IVUS control system; wherein digitization points are provided by the ADC and interleaved into sampling points (401, 402) by the FPGA circuit such that the FPGA circuit operates at approximately 1/2 the frequency of the ADC; and wherein the FPGA circuit comprises: a quadrature internal conditioning circuit; a buffer circuit; and a reconstruction circuit comprising: a circuit to measure a phase of a signal; and a flavor interpolation circuit, wherein the circuit to measure the phase of the signal is configured to form two complex numbers from the digitization points for each cycle of the center frequency of the amplified signal. a pulse transmitter circuit; a receive amplifier configured to amplify the electrical signals into an amplified signal; an analog to digital converter circuit configured to receive the amplified signal and to provide a digital signal; a reconstruction field programmable gate array circuit (FPGA) circuit configured to provide image-reconstructed data from the digital signal provided by the ADC; and a communication protocol circuit which is provided with the image-reconstructed data from the FPGA circuit and configured to transfer the image-reconstructed data to an IVUS control system; wherein digitization points are provided by the ADC and interleaved into sampling points (401, 402) by the FPGA circuit such that the FPGA circuit operates at approximately 1/2 the frequency of the ADC; and wherein the FPGA circuit comprises: a quadrature internal conditioning circuit; a buffer circuit; and a reconstruction circuit comprising: a circuit to measure a phase of a signal; and a flavor interpolation circuit, wherein the circuit to measure the phase of the signal is configured to form two complex numbers from the digitization points for each cycle of the center frequency of the amplified signal. a quadrature internal conditioning circuit; a buffer circuit; and a reconstruction circuit comprising: a circuit to measure a phase of a signal; and a flavor interpolation circuit, wherein the circuit to measure the phase of the signal is configured to form two complex numbers from the digitization points for each cycle of the center frequency of the amplified signal. a circuit to measure a phase of a signal; and a flavor interpolation circuit, wherein the circuit to measure the phase of the signal is configured to form two complex numbers from the digitization points for each cycle of the center frequency of the amplified signal.