A system to manage interrupts, comprising: a processor; a virtual machine, VM, including a guest operating system, OS,; and a non-transitory computer readable medium to store a set of instructions for execution by the processor, the set of instructions to cause the processor to: receive an interrupt for the guest operating system, OS; determine whether the guest OS is in a first, real time, mode of operation or a second, non-real time, mode of operation; route the interrupt to a processor core for the guest OS when the guest OS is in the first mode of operation; and invoke a hypervisor to handle the interrupt for the guest OS when the guest OS is in the second mode of operation; characterised in that the set of instructions are further to cause the processor to: route the interrupt directly to the processor core without invoking the hypervisor when the guest OS is in the first mode of operation; generate, by the guest OS, an end of interrupt, EOI, to indicate completion of the processing of the interrupt while the guest OS is operating in the first mode; send the EOI to a virtual advance programmable interrupt controller, APIC,; determine, by the APIC, based on a setting in a data structure, whether a VM exit is to occur; and signal, by the APIC, completion of the interrupt associated with the EOI without causing a VM exit. a processor; a virtual machine, VM, including a guest operating system, OS,; and a non-transitory computer readable medium to store a set of instructions for execution by the processor, the set of instructions to cause the processor to: receive an interrupt for the guest operating system, OS; determine whether the guest OS is in a first, real time, mode of operation or a second, non-real time, mode of operation; route the interrupt to a processor core for the guest OS when the guest OS is in the first mode of operation; and invoke a hypervisor to handle the interrupt for the guest OS when the guest OS is in the second mode of operation; characterised in that the set of instructions are further to cause the processor to: route the interrupt directly to the processor core without invoking the hypervisor when the guest OS is in the first mode of operation; generate, by the guest OS, an end of interrupt, EOI, to indicate completion of the processing of the interrupt while the guest OS is operating in the first mode; send the EOI to a virtual advance programmable interrupt controller, APIC,; determine, by the APIC, based on a setting in a data structure, whether a VM exit is to occur; and signal, by the APIC, completion of the interrupt associated with the EOI without causing a VM exit. receive an interrupt for the guest operating system, OS; determine whether the guest OS is in a first, real time, mode of operation or a second, non-real time, mode of operation; route the interrupt to a processor core for the guest OS when the guest OS is in the first mode of operation; and invoke a hypervisor to handle the interrupt for the guest OS when the guest OS is in the second mode of operation; characterised in that the set of instructions are further to cause the processor to: route the interrupt directly to the processor core without invoking the hypervisor when the guest OS is in the first mode of operation; generate, by the guest OS, an end of interrupt, EOI, to indicate completion of the processing of the interrupt while the guest OS is operating in the first mode; send the EOI to a virtual advance programmable interrupt controller, APIC,; determine, by the APIC, based on a setting in a data structure, whether a VM exit is to occur; and signal, by the APIC, completion of the interrupt associated with the EOI without causing a VM exit. route the interrupt directly to the processor core without invoking the hypervisor when the guest OS is in the first mode of operation; generate, by the guest OS, an end of interrupt, EOI, to indicate completion of the processing of the interrupt while the guest OS is operating in the first mode; send the EOI to a virtual advance programmable interrupt controller, APIC,; determine, by the APIC, based on a setting in a data structure, whether a VM exit is to occur; and signal, by the APIC, completion of the interrupt associated with the EOI without causing a VM exit.