An apparatus for providing configuration data to an integrated circuit, the apparatus comprising: a device programmer, coupled to a semiconductor fuse array disposed on a die, configured to program said semiconductor fuse array with compressed configuration data; and a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array, and wherein one of said plurality of cores is configured to access said semiconductor fuse array upon power-up/reset to read and decompress said compressed configuration data, and to store decompressed configuration data sets for one or more cache memories within said each of said plurality of cores in a stores that is disposed on the same die as the plurality of cores but not within any of said plurality of cores and coupled to said plurality of cores, said each of said plurality of cores comprising: reset logic, configured to employ said decompressed configuration data sets to initialize said one or more cache memories upon power-up/reset, wherein the reset logic is also configured to read a configuration data register to determine if one of the plurality of cores is a master core or a slave core; and sleep logic, configured to determine that power is restored following a power gating event, and configured to subsequently access said stores to retrieve and employ said decompressed configuration data sets to initialize said one or more caches following said power gating event. a device programmer, coupled to a semiconductor fuse array disposed on a die, configured to program said semiconductor fuse array with compressed configuration data; and a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array, and wherein one of said plurality of cores is configured to access said semiconductor fuse array upon power-up/reset to read and decompress said compressed configuration data, and to store decompressed configuration data sets for one or more cache memories within said each of said plurality of cores in a stores that is disposed on the same die as the plurality of cores but not within any of said plurality of cores and coupled to said plurality of cores, said each of said plurality of cores comprising: reset logic, configured to employ said decompressed configuration data sets to initialize said one or more cache memories upon power-up/reset, wherein the reset logic is also configured to read a configuration data register to determine if one of the plurality of cores is a master core or a slave core; and sleep logic, configured to determine that power is restored following a power gating event, and configured to subsequently access said stores to retrieve and employ said decompressed configuration data sets to initialize said one or more caches following said power gating event. reset logic, configured to employ said decompressed configuration data sets to initialize said one or more cache memories upon power-up/reset, wherein the reset logic is also configured to read a configuration data register to determine if one of the plurality of cores is a master core or a slave core; and sleep logic, configured to determine that power is restored following a power gating event, and configured to subsequently access said stores to retrieve and employ said decompressed configuration data sets to initialize said one or more caches following said power gating event.