A signal output circuit comprising: an input buffer, a generation control circuit, a control voltage generation circuit, and an output circuit, each using only npn transistors as transistors, wherein the input buffer externally receives a single-phase switching instruction signal for instructing to switch a state of the output circuit to one of a shutdown disable state and a shutdown enable state, and converts and outputs the single-phase switching instruction signal into differential switching instruction signals (1 IS) formed from two signals having phases opposite to each other, the generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signals, the control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal based on the generation control signal, and the output circuit externally receives differential input signals, outputs differential output signals upon impedance-converting the differential input signals, and switches between the shutdown disable state and the shutdown enable state of the differential input signals based on the control voltage, and characterized in that the output circuit comprises a ninth npn transistor having a base connected to a first differential input terminal to which a first phase input signal of the differential input signals is input, and a collector connected to the first power supply potential on the high-potential side via a 15th resistor, with a second phase output signal of the differential output signals being output from the collector, a 10th npn transistor having a base connected to a second differential input terminal to which a second phase input signal of the differential input signals is input, and a collector connected to the first power supply potential via a 16th resistor, with a first phase output signal of the differential output signals being output from the collector, a 17th resistor having one port connected to an emitter of the ninth npn transistor, and the other port connected to an emitter of the 10th npn transistor, a 11th npn transistor having a base receiving the control voltage, a collector connected to the emitter of the ninth npn transistor, and an emitter connected to the second power supply potential on the low-potential side via an 18th resistor, and a 12th npn transistor having a base receiving the control voltage, a collector connected to the emitter of the 10th npn transistor, and an emitter connected to the second power supply potential via a 19th resistor. an input buffer, a generation control circuit, a control voltage generation circuit, and an output circuit, each using only npn transistors as transistors, wherein the input buffer externally receives a single-phase switching instruction signal for instructing to switch a state of the output circuit to one of a shutdown disable state and a shutdown enable state, and converts and outputs the single-phase switching instruction signal into differential switching instruction signals (1 IS) formed from two signals having phases opposite to each other, the generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signals, the control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal based on the generation control signal, and the output circuit externally receives differential input signals, outputs differential output signals upon impedance-converting the differential input signals, and switches between the shutdown disable state and the shutdown enable state of the differential input signals based on the control voltage, and characterized in that the output circuit comprises a ninth npn transistor having a base connected to a first differential input terminal to which a first phase input signal of the differential input signals is input, and a collector connected to the first power supply potential on the high-potential side via a 15th resistor, with a second phase output signal of the differential output signals being output from the collector, a 10th npn transistor having a base connected to a second differential input terminal to which a second phase input signal of the differential input signals is input, and a collector connected to the first power supply potential via a 16th resistor, with a first phase output signal of the differential output signals being output from the collector, a 17th resistor having one port connected to an emitter of the ninth npn transistor, and the other port connected to an emitter of the 10th npn transistor, a 11th npn transistor having a base receiving the control voltage, a collector connected to the emitter of the ninth npn transistor, and an emitter connected to the second power supply potential on the low-potential side via an 18th resistor, and a 12th npn transistor having a base receiving the control voltage, a collector connected to the emitter of the 10th npn transistor, and an emitter connected to the second power supply potential via a 19th resistor.