A method of manufacturing an image sensor device comprising: providing a metalized thin film transistor layer (204, 206, 208, 210) formed on a glass substrate; forming a first inter-layer dielectric layer on the metalized thin film transistor layer; forming a via through the first inter-layer dielectric layer; forming a metal layer (220, 222, 224, 226) on an upper surface of the first inter-layer dielectric and within the first inter-layer dielectric layer via for contacting the metalized thin film transistor layer; forming a second inter-layer dielectric layer on an upper surface of the metal layer and the first inter-layer dielectric layer; forming a via through the second inter-layer dielectric layer; forming a conductive oxide layer on an upper surface of the second inter-layer dielectric layer and within the second inter-layer dielectric layer via for contacting an upper surface of the metal layer; i) forming an electron transport layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer; forming a bulk heterojunction layer on an upper surface of the electron transport layer; forming a hole transport layer on an upper surface of the bulk heterojunction layer; and forming a top contact layer on an upper surface of the hole transport layer; or ii) forming a bank layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer; forming a via through the bank layer; forming an electron transport layer on an upper surface of the bank layer and within the bank layer via to contact an upper surface of the conductive oxide layer; forming a bulk heterojunction layer on an upper surface of the electron transport layer; forming a hole transport layer on an upper surface of the bulk heterojunction layer; and forming a top contact layer on an upper surface of the hole transport layer. providing a metalized thin film transistor layer (204, 206, 208, 210) formed on a glass substrate; forming a first inter-layer dielectric layer on the metalized thin film transistor layer; forming a via through the first inter-layer dielectric layer; forming a metal layer (220, 222, 224, 226) on an upper surface of the first inter-layer dielectric and within the first inter-layer dielectric layer via for contacting the metalized thin film transistor layer; forming a second inter-layer dielectric layer on an upper surface of the metal layer and the first inter-layer dielectric layer; forming a via through the second inter-layer dielectric layer; forming a conductive oxide layer on an upper surface of the second inter-layer dielectric layer and within the second inter-layer dielectric layer via for contacting an upper surface of the metal layer; i) forming an electron transport layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer; forming a bulk heterojunction layer on an upper surface of the electron transport layer; forming a hole transport layer on an upper surface of the bulk heterojunction layer; and forming a top contact layer on an upper surface of the hole transport layer; or forming a bulk heterojunction layer on an upper surface of the electron transport layer; forming a hole transport layer on an upper surface of the bulk heterojunction layer; and forming a top contact layer on an upper surface of the hole transport layer; or ii) forming a bank layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer; forming a via through the bank layer; forming an electron transport layer on an upper surface of the bank layer and within the bank layer via to contact an upper surface of the conductive oxide layer; forming a bulk heterojunction layer on an upper surface of the electron transport layer; forming a hole transport layer on an upper surface of the bulk heterojunction layer; and forming a top contact layer on an upper surface of the hole transport layer. forming a via through the bank layer; forming an electron transport layer on an upper surface of the bank layer and within the bank layer via to contact an upper surface of the conductive oxide layer; forming a bulk heterojunction layer on an upper surface of the electron transport layer; forming a hole transport layer on an upper surface of the bulk heterojunction layer; and forming a top contact layer on an upper surface of the hole transport layer.