A multilayered printed circuit board comprising: a first stripline board having first and second opposing surfaces, the first stripline board having a first conductor formed as a first signal path within the multilayered printed circuit board; a second stripline board having first and second opposing surfaces, the second stripline board having a second conductor formed as a second signal path within the multilayered printed circuit board; a vertical interconnect disposed along portions of an outer surface (202c, 204c) of the first and second stripline boards, said vertical interconnect having a first end electrically coupled to the first conductor and a second end electrically coupled to the second conductor, wherein the outer surface of the first and second stripline boards comprises a side portion of the first stripline board and the second stripline board; an electrically conductive wall formed over the outer surface of the first and second stripline boards to form a cavity, wherein said electrically conductive wall encloses said vertical interconnect and the outer surface of the first and second stripline boards, wherein the electrically conductive wall encloses the outer surface such that the cavity is formed between the outer surface of the first and second stripline boards and an inner surface of the electrically conductive wall; a conductive layer, wherein the conductive layer is disposed between the first stripline board and the second stripline board and serves as a ground plane for the first stripline board and the second stripline board; and a ramp provided from a dielectric material provided on one end of the conductive layer such that the dielectric material is disposed between the end and the vertical interconnect, wherein the ramp is configured to insulate the vertical interconnect from the conductive layer. a first stripline board having first and second opposing surfaces, the first stripline board having a first conductor formed as a first signal path within the multilayered printed circuit board; a second stripline board having first and second opposing surfaces, the second stripline board having a second conductor formed as a second signal path within the multilayered printed circuit board; a vertical interconnect disposed along portions of an outer surface (202c, 204c) of the first and second stripline boards, said vertical interconnect having a first end electrically coupled to the first conductor and a second end electrically coupled to the second conductor, wherein the outer surface of the first and second stripline boards comprises a side portion of the first stripline board and the second stripline board; an electrically conductive wall formed over the outer surface of the first and second stripline boards to form a cavity, wherein said electrically conductive wall encloses said vertical interconnect and the outer surface of the first and second stripline boards, wherein the electrically conductive wall encloses the outer surface such that the cavity is formed between the outer surface of the first and second stripline boards and an inner surface of the electrically conductive wall; a conductive layer, wherein the conductive layer is disposed between the first stripline board and the second stripline board and serves as a ground plane for the first stripline board and the second stripline board; and a ramp provided from a dielectric material provided on one end of the conductive layer such that the dielectric material is disposed between the end and the vertical interconnect, wherein the ramp is configured to insulate the vertical interconnect from the conductive layer.