An amplifier, comprising: a high gain stage having input terminals (inputp, inputn) configured to receive incoming signals and output terminals configured to output driving signals (pdrive, ndrive) generated in response to the incoming signals, to an output driver stage; the output driver stage coupled to the high gain stage, comprising: a first driver circuit (105, 106) having a first terminal receiving a first driving signal (pdrive, ndrive) from the high gain stage, a second terminal coupled to a first power rail (VDD, VSS) through a first voltage drop device (201, 202) that is configured to provide a first voltage drop (Vdrop), and a third terminal coupled to an output terminal (107, output) of the amplifier, wherein the first driver (105, 106) circuit comprises a common source transistor; and a first sense circuit (301, 302) comprising a first terminal coupled to the first power rail (VDD, VSS), a second terminal arranged to receive the first driving signal (pdrive, ndrive), and a output terminal coupled to a first side auxiliary driver (303, 304), the first sense circuit (301, 302) being arranged to detect if an amplifier output signal is driven to within the first voltage drop (Vdrop) of the first power rail; and the first side auxiliary driver (303, 304) comprising a first terminal coupled to the output terminal of the first sense circuit (301, 302), a second terminal coupled to the output terminal (107, output) of the amplifier and a third terminal coupled to the first power rail (VDD, VSS), wherein the first side auxiliary driver (303, 304) is arranged to be selectively activated by the output signal level of the first sense circuit to connect the output terminal of the amplifier to the first power rail (VDD, VSS) to bypass the first voltage drop device (201, 202) and allow the output of the amplifier to go all the way to the first power rail (VDD, VSS) if the amplifier output signal is driven to within the first voltage drop (Vdrop) of the first power rail (VDD, VSS). a high gain stage having input terminals (inputp, inputn) configured to receive incoming signals and output terminals configured to output driving signals (pdrive, ndrive) generated in response to the incoming signals, to an output driver stage; the output driver stage coupled to the high gain stage, comprising: a first driver circuit (105, 106) having a first terminal receiving a first driving signal (pdrive, ndrive) from the high gain stage, a second terminal coupled to a first power rail (VDD, VSS) through a first voltage drop device (201, 202) that is configured to provide a first voltage drop (Vdrop), and a third terminal coupled to an output terminal (107, output) of the amplifier, wherein the first driver (105, 106) circuit comprises a common source transistor; and a first sense circuit (301, 302) comprising a first terminal coupled to the first power rail (VDD, VSS), a second terminal arranged to receive the first driving signal (pdrive, ndrive), and a output terminal coupled to a first side auxiliary driver (303, 304), the first sense circuit (301, 302) being arranged to detect if an amplifier output signal is driven to within the first voltage drop (Vdrop) of the first power rail; and the first side auxiliary driver (303, 304) comprising a first terminal coupled to the output terminal of the first sense circuit (301, 302), a second terminal coupled to the output terminal (107, output) of the amplifier and a third terminal coupled to the first power rail (VDD, VSS), wherein the first side auxiliary driver (303, 304) is arranged to be selectively activated by the output signal level of the first sense circuit to connect the output terminal of the amplifier to the first power rail (VDD, VSS) to bypass the first voltage drop device (201, 202) and allow the output of the amplifier to go all the way to the first power rail (VDD, VSS) if the amplifier output signal is driven to within the first voltage drop (Vdrop) of the first power rail (VDD, VSS).