A computing apparatus comprising: a processor configured to execute instructions in an instruction format, wherein the instruction format includes a plurality of fields including a data element width field, a vector length field, and a write mask field, wherein the instruction format supports specification of a plurality of different vector operations, wherein each of the plurality of vector operations requires an operation to be independently performed on each of a plurality of different data element positions of at least one source vector operand to generate at least one destination vector operand, wherein the instruction format supports through different values in the data element width field specification of different data element widths, wherein the instruction format supports through different values in the vector length field specification of a plurality of different vector lengths, wherein the instruction format supports through different values in the write mask field specification of different write masks, wherein only one of the different values may be placed in each of the data element width field and the write mask field on each occurrence of an instruction in the instruction format, and wherein the data element width and the vector length for the occurrence distinguishes which data element positions correspond with which bits of the occurrence's write mask, and wherein the write mask for the occurrence specifies on a per data element position basis whether results of the occurrence's vector operation are or are not to be reflected in the destination vector operand's corresponding data element positions. a processor configured to execute instructions in an instruction format, wherein the instruction format includes a plurality of fields including a data element width field, a vector length field, and a write mask field, wherein the instruction format supports specification of a plurality of different vector operations, wherein each of the plurality of vector operations requires an operation to be independently performed on each of a plurality of different data element positions of at least one source vector operand to generate at least one destination vector operand, wherein the instruction format supports through different values in the data element width field specification of different data element widths, wherein the instruction format supports through different values in the vector length field specification of a plurality of different vector lengths, wherein the instruction format supports through different values in the write mask field specification of different write masks, wherein only one of the different values may be placed in each of the data element width field and the write mask field on each occurrence of an instruction in the instruction format, and wherein the data element width and the vector length for the occurrence distinguishes which data element positions correspond with which bits of the occurrence's write mask, and wherein the write mask for the occurrence specifies on a per data element position basis whether results of the occurrence's vector operation are or are not to be reflected in the destination vector operand's corresponding data element positions.