A dual mode low dropout voltage regulator comprising: - a pass transistor ( P PASS) configured for providing an output voltage ( V OUT) at an output terminal of the dual mode low dropout voltage regulator and comprising a gate; - a low dropout regulation control circuit for controlling regulation of a voltage level ( V OUT) at an output terminal of the dual mode low dropout regulator connected to a load when a bypass signal indicates that the dual mode low dropout voltage regulator is in a low dropout regulation mode, comprising - an error amplifier configured for generating a error signal ( V ERR) indicating a difference between an input reference signal ( V REF) and the output voltage ( V OUT) at the output terminal of the dual mode low dropout voltage regulator and transferring the error signal ( V ERR) to an output terminal of the error amplifier, a pass gate driver circuit configured for receiving the error signal ( V ERR), amplifying the error signal ( V ERR), and transferring the amplified error signal to the gate of the pass transistor ( P PASS), and - a mode transition circuit configured for smoothing a transition between the low dropout regulation mode and the bypass mode of the dual mode low dropout voltage regulator comprising: - a switched error voltage clamp connected for receiving the bypass signal to clamp the output terminal of the error amplifier to approximately its operating voltage level to prevent the output voltage level at the output terminal from decreasing; - a bypass control circuit configured for forcing the voltage level at the output terminal of the dual mode voltage regulator connected to the load to be a voltage level of an unregulated input voltage source (VBAT) as applied to an input terminal of the dual mode low dropout voltage regulator in a bypass mode; - wherein, when the low dropout regulation control circuit receives the bypass signal, the switched error voltage clamp clamps the output terminal of the error amplifier to approximately its operating voltage level, and the bypass control circuit connects the gate of the pass transistor ( P PASS) to a ground reference voltage level to turn on the pass transistor ( P PASS) and forces the voltage level at the output terminal to the voltage level of the unregulated input voltage source ( VBAT). - a pass transistor ( P PASS) configured for providing an output voltage ( V OUT) at an output terminal of the dual mode low dropout voltage regulator and comprising a gate; - a low dropout regulation control circuit for controlling regulation of a voltage level ( V OUT) at an output terminal of the dual mode low dropout regulator connected to a load when a bypass signal indicates that the dual mode low dropout voltage regulator is in a low dropout regulation mode, comprising - an error amplifier configured for generating a error signal ( V ERR) indicating a difference between an input reference signal ( V REF) and the output voltage ( V OUT) at the output terminal of the dual mode low dropout voltage regulator and transferring the error signal ( V ERR) to an output terminal of the error amplifier, a pass gate driver circuit configured for receiving the error signal ( V ERR), amplifying the error signal ( V ERR), and transferring the amplified error signal to the gate of the pass transistor ( P PASS), and - an error amplifier configured for generating a error signal ( V ERR) indicating a difference between an input reference signal ( V REF) and the output voltage ( V OUT) at the output terminal of the dual mode low dropout voltage regulator and transferring the error signal ( V ERR) to an output terminal of the error amplifier, a pass gate driver circuit configured for receiving the error signal ( V ERR), amplifying the error signal ( V ERR), and transferring the amplified error signal to the gate of the pass transistor ( P PASS), and - a mode transition circuit configured for smoothing a transition between the low dropout regulation mode and the bypass mode of the dual mode low dropout voltage regulator comprising: - a switched error voltage clamp connected for receiving the bypass signal to clamp the output terminal of the error amplifier to approximately its operating voltage level to prevent the output voltage level at the output terminal from decreasing; - a bypass control circuit configured for forcing the voltage level at the output terminal of the dual mode voltage regulator connected to the load to be a voltage level of an unregulated input voltage source (VBAT) as applied to an input terminal of the dual mode low dropout voltage regulator in a bypass mode; - a switched error voltage clamp connected for receiving the bypass signal to clamp the output terminal of the error amplifier to approximately its operating voltage level to prevent the output voltage level at the output terminal from decreasing; - a bypass control circuit configured for forcing the voltage level at the output terminal of the dual mode voltage regulator connected to the load to be a voltage level of an unregulated input voltage source (VBAT) as applied to an input terminal of the dual mode low dropout voltage regulator in a bypass mode; - wherein, when the low dropout regulation control circuit receives the bypass signal, the switched error voltage clamp clamps the output terminal of the error amplifier to approximately its operating voltage level, and the bypass control circuit connects the gate of the pass transistor ( P PASS) to a ground reference voltage level to turn on the pass transistor ( P PASS) and forces the voltage level at the output terminal to the voltage level of the unregulated input voltage source ( VBAT).