A method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of active areas; forming a plurality of bit lines arranged at intervals on the substrate, a plurality of first mask layers being arranged on the plurality of bit lines; forming a first dielectric layer on the substrate positioned between adjacent two of the plurality of bit lines, the first dielectric layer covering the plurality of bit lines and the substrate; patterning the first dielectric layer to form a plurality of first notches arranged at intervals on the first dielectric layer; forming a second mask layer on the first dielectric layer, the second mask layer encircling in each of the plurality of first notches to form a second notch, the second mask layer being formed on an inner wall of each of the plurality of first notches, and the second mask layer extending to outside of each of the plurality of first notches and covering the first dielectric layer; removing the first dielectric layer positioned under the second notch to form a plurality of contact holes arranged at intervals in the first dielectric layer, each of the plurality of contact holes extending into the substrate to expose a part of the plurality of active areas; and forming a conductive plunger in each of the plurality of contact holes, the conductive plunger being in contact with each of the plurality of active areas. providing a substrate, the substrate comprising a plurality of active areas; forming a plurality of bit lines arranged at intervals on the substrate, a plurality of first mask layers being arranged on the plurality of bit lines; forming a first dielectric layer on the substrate positioned between adjacent two of the plurality of bit lines, the first dielectric layer covering the plurality of bit lines and the substrate; patterning the first dielectric layer to form a plurality of first notches arranged at intervals on the first dielectric layer; forming a second mask layer on the first dielectric layer, the second mask layer encircling in each of the plurality of first notches to form a second notch, the second mask layer being formed on an inner wall of each of the plurality of first notches, and the second mask layer extending to outside of each of the plurality of first notches and covering the first dielectric layer; removing the first dielectric layer positioned under the second notch to form a plurality of contact holes arranged at intervals in the first dielectric layer, each of the plurality of contact holes extending into the substrate to expose a part of the plurality of active areas; and forming a conductive plunger in each of the plurality of contact holes, the conductive plunger being in contact with each of the plurality of active areas. forming a plurality of bit lines arranged at intervals on the substrate, a plurality of first mask layers being arranged on the plurality of bit lines; forming a first dielectric layer on the substrate positioned between adjacent two of the plurality of bit lines, the first dielectric layer covering the plurality of bit lines and the substrate; patterning the first dielectric layer to form a plurality of first notches arranged at intervals on the first dielectric layer; forming a second mask layer on the first dielectric layer, the second mask layer encircling in each of the plurality of first notches to form a second notch, the second mask layer being formed on an inner wall of each of the plurality of first notches, and the second mask layer extending to outside of each of the plurality of first notches and covering the first dielectric layer; removing the first dielectric layer positioned under the second notch to form a plurality of contact holes arranged at intervals in the first dielectric layer, each of the plurality of contact holes extending into the substrate to expose a part of the plurality of active areas; and forming a conductive plunger in each of the plurality of contact holes, the conductive plunger being in contact with each of the plurality of active areas.