An integrated circuit comprising: a memory for outputting N-bit data; a memory test circuit for testing the memory; an input/output port; and a PLL for generating a first clock signal having a high speed substantially the same as a clock speed in a normal operation based on a test clock signal slower than the first clock signal and for supplying the first clock signal to the memory, wherein the memory test circuit includes: a latch circuit that includes 2N flip-flops and is for latching the N-bit data output from the memory; a counter for counting the first clock signal and for outputting a latch signal having a cycle of an integer multiple of the first clock signal for latching the N-bit data to the latch circuit based on a count value counted by the counter; a control circuit (61, 62, 63) for outputting a control signal indicating a read based on a read signal and the count value; and a mask circuit for starting outputting a FF clock signal after a latch signal is generated synchronized with the test clock signal to the latch circuit based on the count value and the control signal to shift and output the N-bit data of the latch circuit to the input/output port, the integrated circuit is configured such that: an address corresponding to a cell of the memory to be accessed is changed in accordance with the first clock signal, and the N-bit data output from the memory corresponding to the changed address is latched by the latch circuit in accordance with the latch signal, the N-bit data of the latch circuit is output via the input/output port in a cycle of the latch signal, the address corresponding to the cell of the memory to be accessed is changed, and the latch and the output is repeated for the N-bit data output from the memory corresponding to the changed address. a memory for outputting N-bit data; a memory test circuit for testing the memory; an input/output port; and a PLL for generating a first clock signal having a high speed substantially the same as a clock speed in a normal operation based on a test clock signal slower than the first clock signal and for supplying the first clock signal to the memory, wherein the memory test circuit includes: a latch circuit that includes 2N flip-flops and is for latching the N-bit data output from the memory; a counter for counting the first clock signal and for outputting a latch signal having a cycle of an integer multiple of the first clock signal for latching the N-bit data to the latch circuit based on a count value counted by the counter; a control circuit (61, 62, 63) for outputting a control signal indicating a read based on a read signal and the count value; and a mask circuit for starting outputting a FF clock signal after a latch signal is generated synchronized with the test clock signal to the latch circuit based on the count value and the control signal to shift and output the N-bit data of the latch circuit to the input/output port, the integrated circuit is configured such that: an address corresponding to a cell of the memory to be accessed is changed in accordance with the first clock signal, and the N-bit data output from the memory corresponding to the changed address is latched by the latch circuit in accordance with the latch signal, the N-bit data of the latch circuit is output via the input/output port in a cycle of the latch signal, the address corresponding to the cell of the memory to be accessed is changed, and the latch and the output is repeated for the N-bit data output from the memory corresponding to the changed address. a latch circuit that includes 2N flip-flops and is for latching the N-bit data output from the memory; a counter for counting the first clock signal and for outputting a latch signal having a cycle of an integer multiple of the first clock signal for latching the N-bit data to the latch circuit based on a count value counted by the counter; a control circuit (61, 62, 63) for outputting a control signal indicating a read based on a read signal and the count value; and a mask circuit for starting outputting a FF clock signal after a latch signal is generated synchronized with the test clock signal to the latch circuit based on the count value and the control signal to shift and output the N-bit data of the latch circuit to the input/output port, the integrated circuit is configured such that: an address corresponding to a cell of the memory to be accessed is changed in accordance with the first clock signal, and the N-bit data output from the memory corresponding to the changed address is latched by the latch circuit in accordance with the latch signal, the N-bit data of the latch circuit is output via the input/output port in a cycle of the latch signal, the address corresponding to the cell of the memory to be accessed is changed, and the latch and the output is repeated for the N-bit data output from the memory corresponding to the changed address. an address corresponding to a cell of the memory to be accessed is changed in accordance with the first clock signal, and the N-bit data output from the memory corresponding to the changed address is latched by the latch circuit in accordance with the latch signal, the N-bit data of the latch circuit is output via the input/output port in a cycle of the latch signal, the address corresponding to the cell of the memory to be accessed is changed, and the latch and the output is repeated for the N-bit data output from the memory corresponding to the changed address.