An integrated circuit comprising: a plurality of connected digital signal processing elements, wherein each DSP element of the plurality of connected DSP elements includes: a first output port for outputting an output value; a second output port for outputting a cascaded input value as input from an adjacent DSP element; a first input port coupled to receive the cascaded input value by way of a first dedicated signal line from a second output port of the adjacent DSP element, wherein the first dedicated signal line provides a direct connection to the first input port; a second input port coupled to receive an output value byway of a second dedicated signal line from a first output port of the adjacent DSP element, wherein the second dedicated signal line provides a direct connection to the second input port; multiplexing circuitry (370, 372, 374) having: a first multiplexer input; a second multiplexer input coupled to the first input port; a third multiplexer input coupled to the second input port; a fourth multiplexer input coupled to receive the output value; first and second multiplexer outputs; and a select input; a hardwired adder having a first addend input connected to the first multiplexer output, a second addend input, and a third addend input connected to the second multiplexer output, the adder configured to provide the output value; and a register connected to the select input of the multiplexing circuitry, the register configurable to connect either the first multiplexer input or the second multiplexer input to the first multiplexer output, and connect either the third multiplexer input or the fourth multiplexer input to the second multiplexer output; and a control circuit coupled to the registers in the plurality of DSP elements, wherein the control circuit is configured to control contents of each register for determining function and connectivity of the plurality of DSP elements. a plurality of connected digital signal processing elements, wherein each DSP element of the plurality of connected DSP elements includes: a first output port for outputting an output value; a second output port for outputting a cascaded input value as input from an adjacent DSP element; a first input port coupled to receive the cascaded input value by way of a first dedicated signal line from a second output port of the adjacent DSP element, wherein the first dedicated signal line provides a direct connection to the first input port; a first output port for outputting an output value; a second output port for outputting a cascaded input value as input from an adjacent DSP element; a first input port coupled to receive the cascaded input value by way of a first dedicated signal line from a second output port of the adjacent DSP element, wherein the first dedicated signal line provides a direct connection to the first input port; a second input port coupled to receive an output value byway of a second dedicated signal line from a first output port of the adjacent DSP element, wherein the second dedicated signal line provides a direct connection to the second input port; multiplexing circuitry (370, 372, 374) having: a first multiplexer input; a second multiplexer input coupled to the first input port; a third multiplexer input coupled to the second input port; a fourth multiplexer input coupled to receive the output value; first and second multiplexer outputs; and a select input; a hardwired adder having a first addend input connected to the first multiplexer output, a second addend input, and a third addend input connected to the second multiplexer output, the adder configured to provide the output value; and a register connected to the select input of the multiplexing circuitry, the register configurable to connect either the first multiplexer input or the second multiplexer input to the first multiplexer output, and connect either the third multiplexer input or the fourth multiplexer input to the second multiplexer output; and multiplexing circuitry (370, 372, 374) having: a first multiplexer input; a second multiplexer input coupled to the first input port; a third multiplexer input coupled to the second input port; a fourth multiplexer input coupled to receive the output value; first and second multiplexer outputs; and a select input; a first multiplexer input; a second multiplexer input coupled to the first input port; a third multiplexer input coupled to the second input port; a fourth multiplexer input coupled to receive the output value; first and second multiplexer outputs; and a select input; a hardwired adder having a first addend input connected to the first multiplexer output, a second addend input, and a third addend input connected to the second multiplexer output, the adder configured to provide the output value; and a register connected to the select input of the multiplexing circuitry, the register configurable to connect either the first multiplexer input or the second multiplexer input to the first multiplexer output, and connect either the third multiplexer input or the fourth multiplexer input to the second multiplexer output; and a control circuit coupled to the registers in the plurality of DSP elements, wherein the control circuit is configured to control contents of each register for determining function and connectivity of the plurality of DSP elements.