A machine-readable medium storing instructions that, when executed on a computing device, cause the computing device to perform a method for compiling a plurality of virtual programmable devices from descriptions in OpenCL for configuring a programmable integrated circuit device, said method comprising: compiling configurations of configurable routing resources (201, 211) of the virtual programmable devices from programmable resources of said programmable integrated circuit device; and compiling configurations of a plurality of complex function blocks of the virtual programmable devices from programmable resources of said programmable integrated circuit device; and configuring input registers for at least one complex function block of said plurality of complex function blocks for balancing said configurable routing resources (201, 211), wherein said configuring input registers comprises configuring a respective FIFO having a depth equal to a respective maximum expected pipeline imbalance on at least one input of said at least one complex function block of said plurality of complex function blocks; wherein said compiling configurations of configurable routing resources (201, 211) comprises compiling a pipelined stall signal network; and wherein said compiling a pipelined stall signal network comprises compiling a network including a plurality of routing switches, each of said routing switches having: an input and at least one output; a respective register for a stall signal on each of said input and said at least one output; an output data stall register for storing output data during a stall of any of said at least one output; a first input data stall register for storing data received at said input prior to a stall of said input; and a second input data stall register for storing data present at said input when said input stalls. compiling configurations of configurable routing resources (201, 211) of the virtual programmable devices from programmable resources of said programmable integrated circuit device; and compiling configurations of a plurality of complex function blocks of the virtual programmable devices from programmable resources of said programmable integrated circuit device; and configuring input registers for at least one complex function block of said plurality of complex function blocks for balancing said configurable routing resources (201, 211), wherein said configuring input registers comprises configuring a respective FIFO having a depth equal to a respective maximum expected pipeline imbalance on at least one input of said at least one complex function block of said plurality of complex function blocks; wherein said compiling configurations of configurable routing resources (201, 211) comprises compiling a pipelined stall signal network; and wherein said compiling a pipelined stall signal network comprises compiling a network including a plurality of routing switches, each of said routing switches having: an input and at least one output; a respective register for a stall signal on each of said input and said at least one output; an output data stall register for storing output data during a stall of any of said at least one output; a first input data stall register for storing data received at said input prior to a stall of said input; and a second input data stall register for storing data present at said input when said input stalls. an input and at least one output; a respective register for a stall signal on each of said input and said at least one output; an output data stall register for storing output data during a stall of any of said at least one output; a first input data stall register for storing data received at said input prior to a stall of said input; and a second input data stall register for storing data present at said input when said input stalls.