A semiconductor device, comprising: a silicon substrate with a device region defined by a device isolation region and including a channel region in said device region; a gate electrode formed on said silicon substrate opposite said channel region with a gate insulation film in between, said gate electrode carrying a pair of sidewall insulation films (13A, 13B,13C, 13D) respectively on each of two mutually opposing sidewall surfaces thereof; source and drain extension regions (10a, 10b) of p-type formed in said silicon substrate opposite respective lateral sides of said gate electrode, at opposite sides of said channel region; source and drain regions (10c, 10d) of p-type formed in said silicon substrate opposite respective outer sides of said pairs of sidewall insulation films (13A, 13B, 13C, 13D) and in continuation of said source extension region and said drain extension region respectively; a pair of p-type SiGe mixed crystal regions (11SGA, 11SGB) formed in said silicon substrate at respective outer sides of said sidewall insulation films (13A, 13B, 13C, 13D) epitaxially to said silicon substrate so as to constitute a part of said source region and said drain region respectively, each of said SiGe mixed crystal regions (11SGA, 11SGB) being formed to project beyond an interface between said gate insulation film and said silicon substrate, wherein there is provided a compressive stress accumulating film at respective top surfaces and on respective sidewall surfaces of said pair of SiGe mixed crystal regions (11SGA, 11SGB), wherein each of said SiGe mixed crystal regions (11SGA, 11SGB) carries a tensile stress accumulating film on a sidewall surface thereof so that the compressive stress acting to each SiGe mixed crystal layer perpendicularly to the substrate surface is reduced. a silicon substrate with a device region defined by a device isolation region and including a channel region in said device region; a gate electrode formed on said silicon substrate opposite said channel region with a gate insulation film in between, said gate electrode carrying a pair of sidewall insulation films (13A, 13B,13C, 13D) respectively on each of two mutually opposing sidewall surfaces thereof; source and drain extension regions (10a, 10b) of p-type formed in said silicon substrate opposite respective lateral sides of said gate electrode, at opposite sides of said channel region; source and drain regions (10c, 10d) of p-type formed in said silicon substrate opposite respective outer sides of said pairs of sidewall insulation films (13A, 13B, 13C, 13D) and in continuation of said source extension region and said drain extension region respectively; a pair of p-type SiGe mixed crystal regions (11SGA, 11SGB) formed in said silicon substrate at respective outer sides of said sidewall insulation films (13A, 13B, 13C, 13D) epitaxially to said silicon substrate so as to constitute a part of said source region and said drain region respectively, each of said SiGe mixed crystal regions (11SGA, 11SGB) being formed to project beyond an interface between said gate insulation film and said silicon substrate, wherein there is provided a compressive stress accumulating film at respective top surfaces and on respective sidewall surfaces of said pair of SiGe mixed crystal regions (11SGA, 11SGB), wherein each of said SiGe mixed crystal regions (11SGA, 11SGB) carries a tensile stress accumulating film on a sidewall surface thereof so that the compressive stress acting to each SiGe mixed crystal layer perpendicularly to the substrate surface is reduced.