A digital pixel comprising: one or more capacitors configured to collect charge corresponding to an amount of light received at the digital pixel; a threshold detector configured to generate a first signal that transitions logically based on an amount of charge in said one or each of said more capacitors, respectively; and an N bit accumulator configured to store a value that indicates a count of a particular type of logical transition of the first signal, the N bit accumulator including: a toggle flip flop configured to receive the first signal and generate a second signal having a logical value that toggles in response to a particular type of logical transition of the first signal; a first clock generator configured to generate a first clock signal by performing a logical AND of the first signal and the second signal; a second clock generator configured to generate a second clock signal by performing a logical AND of the first signal and an inverted version of the second signal; and a linear feedback shift register (LFSR) comprising N-1 bits, each bit comprising a master latch and a slave latch, each master latch of the plurality of N-1 bits configured to latch a feedback value received at the input of said each master latch in response to a particular type of logical transition of the second clock signal, each slave latch of the plurality of bits configured to latch an output value of the master latch of the respective bit in response to a particular type of logical transition of the first clock signal. one or more capacitors configured to collect charge corresponding to an amount of light received at the digital pixel; a threshold detector configured to generate a first signal that transitions logically based on an amount of charge in said one or each of said more capacitors, respectively; and an N bit accumulator configured to store a value that indicates a count of a particular type of logical transition of the first signal, the N bit accumulator including: a toggle flip flop configured to receive the first signal and generate a second signal having a logical value that toggles in response to a particular type of logical transition of the first signal; a first clock generator configured to generate a first clock signal by performing a logical AND of the first signal and the second signal; a second clock generator configured to generate a second clock signal by performing a logical AND of the first signal and an inverted version of the second signal; and a linear feedback shift register (LFSR) comprising N-1 bits, each bit comprising a master latch and a slave latch, each master latch of the plurality of N-1 bits configured to latch a feedback value received at the input of said each master latch in response to a particular type of logical transition of the second clock signal, each slave latch of the plurality of bits configured to latch an output value of the master latch of the respective bit in response to a particular type of logical transition of the first clock signal. a toggle flip flop configured to receive the first signal and generate a second signal having a logical value that toggles in response to a particular type of logical transition of the first signal; a first clock generator configured to generate a first clock signal by performing a logical AND of the first signal and the second signal; a second clock generator configured to generate a second clock signal by performing a logical AND of the first signal and an inverted version of the second signal; and a linear feedback shift register (LFSR) comprising N-1 bits, each bit comprising a master latch and a slave latch, each master latch of the plurality of N-1 bits configured to latch a feedback value received at the input of said each master latch in response to a particular type of logical transition of the second clock signal, each slave latch of the plurality of bits configured to latch an output value of the master latch of the respective bit in response to a particular type of logical transition of the first clock signal.