A memory apparatus comprising: a register to hold width selection information; an interface (DQs) to exchange data with a remote device; the interface comprising first and second data lines (D0, D1); a plurality of memory subsections (PB0,..., PB3), each subsection (PB0,..., PB3) representing an array of plural memory cells of generally fixed size; and routing (310, 315) coupling the memory subsections (PBO,..., PB3) with the interface (DQs), the routing (310, 315) supporting first and second width configurations responsive to the width selection information; wherein in the first width configuration, a first integer number of the memory subsections is accessed and the routing (310, 315) conveys data of a first data width between the first integer number of the memory subsections (PBO,..., PB3) and the interface (DQs), whereby data is conveyed to the remote device on the first and the second data lines (D0, D1); and the plurality of memory subsections (PBO,..., PB3) collectively provide a first memory depth, and in the second width configuration, a second integer number of the memory subsections is accessed and the routing (310, 315) conveys data of a second data width between the second integer number of the memory subsections (PBO,..., PB3) and the interface (DQs), whereby data is conveyed to the remote device on the first data line but not the second data line; and the plurality of memory subsections (PBO,..., PB3) collectively provide a second memory depth; wherein the first data width is different from the second data width, and the second data width is less than the first data width, and the second integer number is less than the first integer number. a register to hold width selection information; an interface (DQs) to exchange data with a remote device; the interface comprising first and second data lines (D0, D1); a plurality of memory subsections (PB0,..., PB3), each subsection (PB0,..., PB3) representing an array of plural memory cells of generally fixed size; and routing (310, 315) coupling the memory subsections (PBO,..., PB3) with the interface (DQs), the routing (310, 315) supporting first and second width configurations responsive to the width selection information; wherein in the first width configuration, a first integer number of the memory subsections is accessed and the routing (310, 315) conveys data of a first data width between the first integer number of the memory subsections (PBO,..., PB3) and the interface (DQs), whereby data is conveyed to the remote device on the first and the second data lines (D0, D1); and the plurality of memory subsections (PBO,..., PB3) collectively provide a first memory depth, and in the second width configuration, a second integer number of the memory subsections is accessed and the routing (310, 315) conveys data of a second data width between the second integer number of the memory subsections (PBO,..., PB3) and the interface (DQs), whereby data is conveyed to the remote device on the first data line but not the second data line; and the plurality of memory subsections (PBO,..., PB3) collectively provide a second memory depth; wherein the first data width is different from the second data width, and