A differential amplifier circuit comprising: a differential stage comprising: a differential transistor pair (101, 102) for differentially receiving signal voltage supplied to an input pair (11a, 11b) thereof; a load element transistor pair (103, 104) connected between an output pair of the differential transistor pair (101, 102) and a power supply; and a current source for supplying a current to said differential transistor pair (101, 102); said differential transistor pair (101, 102) and/or said load element transistor pair (103, 104) being comprised of transistors each having a first threshold voltage; said differential amplifier circuit including a switch circuit (108, 109) for controlling activation and deactivation, characterized in that said switch circuit (108, 109) includes at least one transistor having a second threshold voltage higher than said first threshold voltage and including a control terminal for receiving a control signal (S1, S1B) to be controlled to be on and off; said load element transistor pair (103, 104) comprises a pair of transistors (103, 104) having control terminals coupled; said switch circuit (108, 109) comprises a first switch comprised of a transistor having said second threshold voltage, connected between said power supply and said coupled control terminals of said load element transistor pair (103, 104), and a second switch comprised of a transistor having said second threshold voltage, connected between an output end of one transistor of said load element transistor pair (103, 104) and said coupled control terminals; and said first and second switches (109 and 108) are controlled in common to be on and off respectively by the control signal (S1, S1B) supplied to control terminals of said transistors constituting said first and second switches (109 and 108). a differential stage comprising: a differential transistor pair (101, 102) for differentially receiving signal voltage supplied to an input pair (11a, 11b) thereof; a load element transistor pair (103, 104) connected between an output pair of the differential transistor pair (101, 102) and a power supply; and a current source for supplying a current to said differential transistor pair (101, 102); said differential transistor pair (101, 102) and/or said load element transistor pair (103, 104) being comprised of transistors each having a first threshold voltage; a differential transistor pair (101, 102) for differentially receiving signal voltage supplied to an input pair (11a, 11b) thereof; a load element transistor pair (103, 104) connected between an output pair of the differential transistor pair (101, 102) and a power supply; and a current source for supplying a current to said differential transistor pair (101, 102); said differential transistor pair (101, 102) and/or said load element transistor pair (103, 104) being comprised of transistors each having a first threshold voltage; said differential amplifier circuit including a switch circuit (108, 109) for controlling activation and deactivation, characterized in that said switch circuit (108, 109) includes at least one transistor having a second threshold voltage higher than said first threshold voltage and including a control terminal for receiving a control signal (S1, S1B) to be controlled to be on and off; said load element transistor pair (103, 104) comprises a pair of transistors (103, 104) having control terminals coupled; said switch circuit (108, 109) comprises a first switch comprised of a transistor having said second threshold voltage, connected between said power supply and said coupled control terminals of said load element transistor pair (103, 104), and a second switch comprised of a transistor having said second threshold voltage, connected between an output end of one transistor of said load element transistor pair (103, 104) and said coupled control terminals; and said first and second switches (109 and 108) are controlled in common to be on and off respectively by the control signal (S1, S1B) supplied to control terminals of said transistors constituting said first and second switches (109 and 108).