A method for manufacturing a gate-all-around, GAA, semiconductor device, the method comprising: - providing a semiconductor substrate of a first crystalline semiconductor material; - forming shallow trench isolation, STI, regions in the semiconductor substrate; - after forming the STI regions creating recesses in between the STI regions; - forming a plurality of semiconductor fins on the semiconductor substrate by epitaxial growing a second crystalline semiconductor material in between the STI regions using aspect ratio trapping; the second crystalline semiconductor material being lattice mismatched to the first crystalline semiconductor material, each one of the plurality of semiconductor fins being formed between a respective pair of STI regions wherein the plurality of semiconductor fins are isolated from each other by the STI regions, and the semiconductor fins abutting on a common planar top surface of the second crystalline semiconductor material and the STI regions; - providing at least one nanowire of a third crystalline semiconductor material, different from the second crystalline semiconductor material, above the common planar top surface on the second crystalline semiconductor material of each one of the plurality of semiconductor fins; - providing a dummy gate stack on the at least one nanowire; - providing on the at least one nanowire a source and a drain region at respective sides of the dummy gate; - removing the dummy gate and thereafter removing the second crystalline semiconductor material thereby suspending the at least one nanowire being anchored by the source and drain region; - providing a final gate stack around the at least one nanowire after removing the second crystalline semiconductor material. - providing a semiconductor substrate of a first crystalline semiconductor material; - forming shallow trench isolation, STI, regions in the semiconductor substrate; - after forming the STI regions creating recesses in between the STI regions; - forming a plurality of semiconductor fins on the semiconductor substrate by epitaxial growing a second crystalline semiconductor material in between the STI regions using aspect ratio trapping; the second crystalline semiconductor material being lattice mismatched to the first crystalline semiconductor material, each one of the plurality of semiconductor fins being formed between a respective pair of STI regions wherein the plurality of semiconductor fins are isolated from each other by the STI regions, and the semiconductor fins abutting on a common planar top surface of the second crystalline semiconductor material and the STI regions; - providing at least one nanowire of a third crystalline semiconductor material, different from the second crystalline semiconductor material, above the common planar top surface on the second crystalline semiconductor material of each one of the plurality of semiconductor fins; - providing a dummy gate stack on the at least one nanowire; - providing on the at least one nanowire a source and a drain region at respective sides of the dummy gate; - removing the dummy gate and thereafter removing the second crystalline semiconductor material thereby suspending the at least one nanowire being anchored by the source and drain region; - providing a final gate stack around the at least one nanowire after removing the second crystalline semiconductor material.