An integrated circuit package comprising: an integrated circuit die (101A, 101B) comprising first and second circuit regions (130, 131) and a surface, wherein the first circuit region generates a higher heat density than the second circuit region when the integrated circuit die (101A, 101B) is operating; and a cooling structure (102A, 102B) on the surface of the integrated circuit die (101A, 101B), wherein the cooling structure (102A, 102B) comprises a plurality of different sized micropipe interconnects (115, 315A, 315B) to form a cooling channel that allows for the flow of coolant through the cooling structure (102A, 102B) wherein each of the micropipe interconnects (115, 315A, 315B) comprises conductors that electrically connect to through-silicon-vias in the integrated circuit die (101A, 101B); characterized in that the cooling channel comprises: a first heat removal region provided next to the first circuit region and comprising a first subset of the micropipe interconnects (115, 315A) having a first diameter, wherein first sub-fluidic channels are formed between the first subset of the micropipe interconnects (115, 315A) having a first dimension, and second heat removal region provided next to the second circuit region and comprising a second subset of the micropipe interconnects (115, 315B) having a second diameter that is larger than the first diameter (Di), wherein second sub-fluidic channels are formed between the second subset of the micropipe interconnects (115, 315B) having a second dimension that is smaller than the first dimension, so that the first sub-fluidic channels have a higher volume of coolant to cool the first circuit region and the second sub-fluidic channels have a lower volume of coolant to cool the second circuit region. an integrated circuit die (101A, 101B) comprising first and second circuit regions (130, 131) and a surface, wherein the first circuit region generates a higher heat density than the second circuit region when the integrated circuit die (101A, 101B) is operating; and a cooling structure (102A, 102B) on the surface of the integrated circuit die (101A, 101B), wherein the cooling structure (102A, 102B) comprises a plurality of different sized micropipe interconnects (115, 315A, 315B) to form a cooling channel that allows for the flow of coolant through the cooling structure (102A, 102B) wherein each of the micropipe interconnects (115, 315A, 315B) comprises conductors that electrically connect to through-silicon-vias in the integrated circuit die (101A, 101B); characterized in that the cooling channel comprises: a first heat removal region provided next to the first circuit region and comprising a first subset of the micropipe interconnects (115, 315A) having a first diameter, wherein first sub-fluidic channels are formed between the first subset of the micropipe interconnects (115, 315A) having a first dimension, and second heat removal region provided next to the second circuit region and comprising a second subset of the micropipe interconnects (115, 315B) having a second diameter that is larger than the first diameter (Di), wherein second sub-fluidic channels are formed between the second subset of the micropipe interconnects (115, 315B) having a second dimension that is smaller than the first dimension, so that the first sub-fluidic channels have a higher volume of coolant to cool the first circuit region and the second sub-fluidic channels have a lower volume of coolant to cool the second circuit region. a first heat removal region provided next to the first circuit region and comprising a first subset of the micropipe interconnects (115, 315A) having a first diameter, wherein first sub-fluidic channels are formed between the first subset of the micropipe interconnects (115, 315A) having a first dimension, and second heat removal region provided next to the second circuit region and comprising a second subset of the micropipe interconnects (115, 315B) having a second diameter that is larger than the first diameter (Di), wherein second sub-fluidic channels are formed between the second subset of the micropipe interconnects (115, 315B) having a second dimension that is smaller than the first dimension, so that the first sub-fluidic channels have a higher volume of coolant to cool the first circuit region and the second sub-fluidic channels have a lower volume of coolant to cool the second circuit region.