A cyclic redundancy check, CRC, decoder circuit comprising: an input for receiving an input stream that has a K-bit, CRC-encoded input bit sequence, s, comprising information bits and L CRC bits being generated using a predefined CRC generator polynomial and a number, P, of at least two processors configured to perform a CRC decode computation of the K-bit input bit sequence, s; a Look Up Table, LUT, operably coupled to the at least two processors and comprising a plurality of addresses; wherein the CRC decoder circuit is characterized in that the at least two processors are configured to: firstly combine LUT data with the input stream to generate P intermediate parity bit sequences using multiple, ⌈ K / P ⌉, first Z steps; and secondly combine the P mare intermediate parity bit sequences multiple, ⌈ log 2 P ⌉, times to generate a single parity bit sequence representing a CRC syndrome; determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error; wherein each address of the LUT is configured to store Z P rows of a CRC generator matrix generated from Z an inverse of the predefined CRC generator polynomial, wherein the inverse of the CRC generator polynomial is obtained from the CRC generator polynomial by subtracting each of its exponents from L; wherein a set of mod(-K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, s, and wherein an order of the rows in the CRC generator matrix^ is reversed and aligned with the input bits of the i extended input stream;and wherein the at least two processors are further configured to firstly combine LUT data with the input stream by using Z P bits of the extended, aligned input stream to mask the corresponding P rows of the CRC generator matrix stored in the LUT under one address. an input for receiving an input stream that has a K-bit, CRC-encoded input bit sequence, s, comprising information bits and L CRC bits being generated using a predefined CRC generator polynomial and a number, P, of at least two processors configured to perform a CRC decode computation of the K-bit input bit sequence, s; a Look Up Table, LUT, operably coupled to the at least two processors and comprising a plurality of addresses; wherein the CRC decoder circuit is characterized in that the at least two processors are configured to: firstly combine LUT data with the input stream to generate P intermediate parity bit sequences using multiple, ⌈ K / P ⌉, first Z steps; and secondly combine the P mare intermediate parity bit sequences multiple, ⌈ log 2 P ⌉, times to generate a single parity bit sequence representing a CRC syndrome; determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error; wherein each address of the LUT is configured to store Z P rows of a CRC generator matrix generated from Z an inverse of the predefined CRC generator polynomial, wherein the inverse of the CRC generator polynomial is obtained from the CRC generator polynomial by subtracting each of its exponents from L; wherein a set of mod(-K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, s, and wherein an order of the rows in the CRC generator matrix^ is reversed and aligned with the input bits of the i extended input stream;and wherein the at least two processors are further configured to firstly combine LUT data with the input stream by using Z P bits of the extended, aligned input stream to mask the corresponding P rows of the CRC generator matrix stored in the LUT under one address. firstly combine LUT data with the input stream to generate P intermediate parity bit sequences using multiple, ⌈ K / P ⌉, first Z steps; and secondly combine the P mare intermediate parity bit sequences multiple, ⌈ log 2 P ⌉, times to generate a single parity bit sequence representing a CRC syndrome; determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error; wherein each address of the LUT is configured to store Z P rows of a CRC generator matrix generated from Z an inverse of the predefined CRC generator polynomial, wherein the inverse of the CRC generator polynomial is obtained from the CRC generator polynomial by subtracting each of its exponents from L; wherein a set of mod(-K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, s, and wherein an order of the rows in the CRC generator matrix^ is reversed and aligned with the input bits of the i extended input stream;and wherein the at least two processors are further configured to firstly combine LUT data with the input stream by using Z P bits of the extended, aligned input stream to mask the corresponding P rows of the CRC generator matrix stored in the LUT under one address.