A system, comprising: a dual in-line memory module, wherein the dual in-line memory module comprises non-volatile random access memory, NVRAM, the non-volatile random access memory to be allocated system memory address space as byte addressable system memory, and wherein the dual in-line memory module comprises a far memory controller; the system further comprising a memory side cache communicatively coupled to the dual in-line memory module, the memory side cache comprising: a DRAM memory to act as a cache for the non-volatile random access memory, the non-volatile random access memory having a greater storage capacity than the DRAM memory; and a cache control unit, wherein the cache control unit is configured to: receive a memory access request, wherein the memory access request requests data at a system memory address; determine whether the requested data is in the DRAM memory; if the requested data is not in the DRAM memory, send the memory access request to the far memory controller along with the system memory address; wherein the far memory controller is configured, in a read operation, to: translate the system memory address, being a logical block address, to a physical address of the NVRAM at block granularity using an address indirection table (520, 563), and direct the read operation to the translated address of the NVRAM; receive the requested data from the non-volatile random access memory; and send the requested data to the cache control unit; wherein the far memory controller is further configured to update the address indirection table (520, 563) whenever a NVRAM block is moved due to wear levelling. a dual in-line memory module, wherein the dual in-line memory module comprises non-volatile random access memory, NVRAM, the non-volatile random access memory to be allocated system memory address space as byte addressable system memory, and wherein the dual in-line memory module comprises a far memory controller; the system further comprising a memory side cache communicatively coupled to the dual in-line memory module, the memory side cache comprising: a DRAM memory to act as a cache for the non-volatile random access memory, the non-volatile random access memory having a greater storage capacity than the DRAM memory; and a cache control unit, wherein the cache control unit is configured to: receive a memory access request, wherein the memory access request requests data at a system memory address; determine whether the requested data is in the DRAM memory; if the requested data is not in the DRAM memory, send the memory access request to the far memory controller along with the system memory address; wherein the far memory controller is configured, in a read operation, to: translate the system memory address, being a logical block address, to a physical address of the NVRAM at block granularity using an address indirection table (520, 563), and direct the read operation to the translated address of the NVRAM; receive the requested data from the non-volatile random access memory; and send the requested data to the cache control unit; wherein the far memory controller is further configured to update the address indirection table (520, 563) whenever a NVRAM block is moved due to wear levelling. a DRAM memory to act as a cache for the non-volatile random access memory, the non-volatile random access memory having a greater storage capacity than the DRAM memory; and a cache control unit, wherein the cache control unit is configured to: receive a memory access request, wherein the memory access request requests data at a system memory address; determine whether the requested data is in the DRAM memory; if the requested data is not in the DRAM memory, send the memory access request to the far memory controller along with the system memory address; receive a memory access request, wherein the memory access request requests data at a system memory address; determine whether the requested data is in the DRAM memory; if the requested data is not in the DRAM memory, send the memory access request to the far memory controller along with the system memory address; wherein the far memory controller is configured, in a read operation, to: translate the system memory address, being a logical block address, to a physical address of the NVRAM at block granularity using an address indirection table (520, 563), and direct the read operation to the translated address of the NVRAM; receive the requested data from the non-volatile random access memory; and send the requested data to the cache control unit; translate the system memory address, being a logical block address, to a physical address of the NVRAM at block granularity using an address indirection table (520, 563), and direct the read operation to the translated address of the NVRAM; receive the requested data from the non-volatile random access memory; and send the requested data to the cache control unit; wherein the far memory controller is further configured to update the address indirection table (520, 563) whenever a NVRAM block is moved due to wear levelling.