A flash memory device (4400, 4500, 4600), comprising: an array of flash memory cells organized into rows and columns, each column of flash memory cells coupled to a bit line; a programming circuit (4100, 4200) for applying a programming current to a selected bit line coupled to a column of flash memory cells in the array during a programming operation; and a multiplexor (4402, 4502, 4602) comprising a programming inhibit circuit (4406, 4506, 4606) for applying an inhibit bias current to unselected bit lines coupled to columns of flash memory cells in the array during a programming operation and a read circuit (4408, 4508, 4608) for coupling a selected bit line coupled to a column of flash memory cells in the array to a sense amplifier during a read operation; wherein during a programming operation a selected cell coupled to the selected bit line is programmed but all cells coupled to the unselected bit lines are not programmed; wherein the programming inhibit circuit comprises: a first set of PMOS transistors (4406, 4506), wherein each bit line is coupled to a PMOS transistor in the first set of PMOS transistors to receive the inhibit bias current; and a second set of PMOS transistors, wherein each PMOS transistor in the second set of PMOS transistors is coupled to a plurality of PMOS transistors in the first set of PMOS transistors to provide the inhibit bias current; and wherein the programming circuit comprises a circuit (4102, 4104, 4106, 4202) for sampling a leakage current drawn by the selected bit line and during a programming operation injecting a current into the selected bit line to compensate for the leakage current. an array of flash memory cells organized into rows and columns, each column of flash memory cells coupled to a bit line; a programming circuit (4100, 4200) for applying a programming current to a selected bit line coupled to a column of flash memory cells in the array during a programming operation; and a multiplexor (4402, 4502, 4602) comprising a programming inhibit circuit (4406, 4506, 4606) for applying an inhibit bias current to unselected bit lines coupled to columns of flash memory cells in the array during a programming operation and a read circuit (4408, 4508, 4608) for coupling a selected bit line coupled to a column of flash memory cells in the array to a sense amplifier during a read operation; wherein during a programming operation a selected cell coupled to the selected bit line is programmed but all cells coupled to the unselected bit lines are not programmed; wherein the programming inhibit circuit comprises: a first set of PMOS transistors (4406, 4506), wherein each bit line is coupled to a PMOS transistor in the first set of PMOS transistors to receive the inhibit bias current; and a second set of PMOS transistors, wherein each PMOS transistor in the second set of PMOS transistors is coupled to a plurality of PMOS transistors in the first set of PMOS transistors to provide the inhibit bias current; and wherein the programming circuit comprises a circuit (4102, 4104, 4106, 4202) for sampling a leakage current drawn by the selected bit line and during a programming operation injecting a current into the selected bit line to compensate for the leakage current. a first set of PMOS transistors (4406, 4506), wherein each bit line is coupled to a PMOS transistor in the first set of PMOS transistors to receive the inhibit bias current; and a second set of PMOS transistors, wherein each PMOS transistor in the second set of PMOS transistors is coupled to a plurality of PMOS transistors in the first set of PMOS transistors to provide the inhibit bias current; and wherein the programming circuit comprises a circuit (4102, 4104, 4106, 4202) for sampling a leakage current drawn by the selected bit line and during a programming operation injecting a current into the selected bit line to compensate for the leakage current.