A packaged leadless semiconductor device comprising: a heat sink flange having an upper surface and a lower surface spaced apart by a flange thickness; a semiconductor die physically coupled to said upper surface of said heat sink flange; a frame structure having a perimeter that defines a cavity and terminal pads surrounding said cavity, each of said terminal pads including a first surface and a second surface, said first surface being spaced apart from said second surface by a distance that is at greater than said flange thickness, each of said terminal pads comprises a folded arrangement having a first section and a second section, and said first surface being formed on a top side of said first section, and said second surface being formed on an underside of said second section and said heat sink flange is positioned in said cavity such that said lower surface of said heat sink flange and said second surface of each of said terminal pads are in coplanar alignment, and at least a portion of said first surface of said each of said terminal pads overlies said upper surface of said heat sink flange; interconnects electrically connecting said semiconductor die with said first surface of said terminal pads; and a molding compound encapsulant encasing said frame structure, said flange, said semiconductor die, and said interconnects with at least said lower surface of said flange and said second surface of said each of said terminal pads remaining exposed from said molding compound encapsulant, wherein said first surface is spaced apart from said upper surface of said heat sink flange by a first gap with, a dielectric material residing in said first gap, wherein said dielectric material is provided to increase the capacitance between said heat sink flange and said frame structure; said terminal pads further comprise a connector section interconnecting said first and second sections (46, 48), wherein said second section is outwardly laterally displaced away from said heat sink flange relative to said first section said connector section is spaced apart from a lateral sidewall of said heat sink flange by a gap, characterized in that said semiconductor device further comprises a dielectric material residing in said gap. a heat sink flange having an upper surface and a lower surface spaced apart by a flange thickness; a semiconductor die physically coupled to said upper surface of said heat sink flange; a frame structure having a perimeter that defines a cavity and terminal pads surrounding said cavity, each of said terminal pads including a first surface and a second surface, said first surface being spaced apart from said second surface by a distance that is at greater than said flange thickness, each of said terminal pads comprises a folded arrangement having a first section and a second section, and said first surface being formed on a top side of said first section, and said second surface being formed on an underside of said second section and said heat sink flange is positioned in said cavity such that said lower surface of said heat sink flange and said second surface of each of said terminal pads are in coplanar alignment, and at least a portion of said first surface of said each of said terminal pads overlies said upper surface of said heat sink flange; interconnects electrically connecting said semiconductor die with said first surface of said terminal pads; and a molding compound encapsulant encasing said frame structure, said flange, said semiconductor die, and said interconnects with at least said lower surface of said flange and said second surface of said each of said terminal pads remaining exposed from said molding compound encapsulant, wherein said first surface is spaced apart from said upper surface of said heat sink flange by a first gap with, a dielectric material residing in said first gap, wherein said dielectric material is provided to increase the capacitance between said heat sink flange and said frame structure; said terminal pads further comprise a connector section interconnecting said first and second sections (46, 48), wherein said second section is outwardly laterally displaced away from said heat sink flange relative to said first section said connector section is spaced apart from a lateral sidewall of said heat sink flange by a gap, characterized in that said semiconductor device further comprises a dielectric material residing in said gap.