A system comprising: a memory containing instructions; a main processor unit coupled to the memory and executing instructions obtained from the memory; a stack machine, separate from the main processor unit, coupled to the memory and executing instruction bytecodes obtained from the memory, the stack machine characterised by: a program counter containing an address of a first instruction bytecode to be decoded, wherein the first instruction bytecode (Bytecode A) may comprise all or a portion of a current instruction; a program counter calculator coupled to the program counter; a register containing instruction bytecodes including the first instruction bytecode (Bytecode A) and at least one subsequent bytecode (Bytecode B-F) following the first bytecode (Bytecode A), wherein the at least one subsequent instruction bytecode may comprise a portion of the current instruction or of one or more subsequent instructions; decode logic coupled to the register (140 and to the program counter calculator and arranged to decode the first instruction bytecode (Bytecode A) from the register; pre-decode logic coupled to the program counter calculator the pre-decode logic arranged to decode the at least one subsequent instruction bytecodes (Bytecode B-F), while the decode logic is decoding the first instruction bytecode (Bytecode A), wherein the pre-decode logic includes a plurality of comparators, multiplexer circuitry coupled to the plurality of the comparators and an output connected to the program counter calculator and wherein each comparator is arranged to compare one of the at least one subsequent instruction bytecodes to a predetermined set of prefixes, wherein when at least one subsequent instruction bytecode (Bytecode B-F) is found to match one from the set of predetermined prefixes, the pre-decode logic is arranged to selectively provide a signal to the program counter to skip the prefix and point to a next one of the at least one subsequent instruction bytecode (Bytecode B-F) and to provide a signal to switch the instruction set mode for the instruction following a detected matching bytecode. a memory containing instructions; a main processor unit coupled to the memory and executing instructions obtained from the memory; a stack machine, separate from the main processor unit, coupled to the memory and executing instruction bytecodes obtained from the memory, the stack machine characterised by: a program counter containing an address of a first instruction bytecode to be decoded, wherein the first instruction bytecode (Bytecode A) may comprise all or a portion of a current instruction; a program counter calculator coupled to the program counter; a register containing instruction bytecodes including the first instruction bytecode (Bytecode A) and at least one subsequent bytecode (Bytecode B-F) following the first bytecode (Bytecode A), wherein the at least one subsequent instruction bytecode may comprise a portion of the current instruction or of one or more subsequent instructions; decode logic coupled to the register (140 and to the program counter calculator and arranged to decode the first instruction bytecode (Bytecode A) from the register; pre-decode logic coupled to the program counter calculator the pre-decode logic arranged to decode the at least one subsequent instruction bytecodes (Bytecode B-F), while the decode logic is decoding the first instruction bytecode (Bytecode A), wherein the pre-decode logic includes a plurality of comparators, multiplexer circuitry coupled to the plurality of the comparators and an output connected to the program counter calculator and wherein each comparator is arranged to compare one of the at least one subsequent instruction bytecodes to a predetermined set of prefixes, wherein a program counter containing an address of a first instruction bytecode to be decoded, wherein the first instruction bytecode (Bytecode A) may comprise all or a portion of a current instruction; a program counter calculator coupled to the program counter; a register containing instruction bytecodes including the first instruction bytecode (Bytecode A) and at least one subsequent bytecode (Bytecode B-F) following the first bytecode (Bytecode A), wherein the at least one subsequent instruction bytecode may comprise a portion of the current instruction or of one or more subsequent instructions; decode logic coupled to the register (140 and to the program counter calculator and arranged to decode the first instruction bytecode (Bytecode A) from the register; pre-decode logic coupled to the program counter calculator the pre-decode logic arranged to decode the at least one subsequent instruction bytecodes (Bytecode B-F), while the decode logic is decoding the first instruction bytecode (Bytecode A), wherein the pre-decode logic includes a plurality of comparators, multiplexer circuitry coupled to the plurality of the comparators and an output connected to the program counter calculator and wherein each comparator is arranged to compare one of the at least one subsequent instruction bytecodes to a predetermined set of prefixes, wherein when at least one subsequent instruction bytecode (Bytecode B-F) is found to match one from the set of predetermined prefixes, the pre-decode logic is arranged to selectively provide a signal to the program counter to skip the prefix and point to a next one of the at least one subsequent instruction bytecode (Bytecode B-F) and to provide a signal to switch the instruction set mode for the instruction following a detected matching bytecode.