An electronic device (EA; EA-A) comprising: an electronic module (EM; EM2; EM-A) comprising at least one of, a light emitting module, a light receiving module, or a camera module; the electronic device further comprising a display panel (DP; DP-A) comprising: a first display area (AA; RA1; RA1-A); and a second display area (HA; RA2; RA2-A) adjacent to the first display area (AA; RA1; RA1-A), the second display area (HA; RA2; RA1-A) comprising a hole area which comprises a module hole, the hole area being surrounded by an active area, the second display area overlapping with the electronic module (EM; EM2; EM-A), and comprising: a circuit layer comprising driving elements comprising thin film transistors; and a display element layer comprising one or more light emitting elements and a deposition preventing pattern (PD; PD-A), wherein the deposition preventing pattern (PD; PD-A) is configured to prevent the deposition of conductive material at the deposition preventing pattern (PD; PD-A), wherein the light emitting elements comprise: first electrodes (E1, E1') connected to the thin film transistors; emission patterns on the first electrodes (E1, E1'); and a second electrode on the emission patterns, wherein the deposition preventing pattern (PD; PD-A) is arranged on a same layer on which the second electrode is arranged, wherein the second electrode overlaps with the first display area (AA; RA1; RA1-A) and the second display area (HA; RA2; RA2-A), and wherein the deposition preventing pattern (PD; PD-A) overlaps with the hole area in the second display area (HA; RA2; RA2-A) wherein a first side of the deposition preventing pattern adjoins the second electrode at the limit between the active area and the hole area and a second side of the deposition preventing pattern, opposite to the first side, is exposed by the module hole. an electronic module (EM; EM2; EM-A) comprising at least one of, a light emitting module, a light receiving module, or a camera module; the electronic device further comprising a display panel (DP; DP-A) comprising: a first display area (AA; RA1; RA1-A); and a second display area (HA; RA2; RA2-A) adjacent to the first display area (AA; RA1; RA1-A), the second display area (HA; RA2; RA1-A) comprising a hole area which comprises a module hole, the hole area being surrounded by an active area, the second display area overlapping with the electronic module (EM; EM2; EM-A), and comprising: a circuit layer comprising driving elements comprising thin film transistors; and a display element layer comprising one or more light emitting elements and a deposition preventing pattern (PD; PD-A), wherein the deposition preventing pattern (PD; PD-A) is configured to prevent the deposition of conductive material at the deposition preventing pattern (PD; PD-A), a first display area (AA; RA1; RA1-A); and a second display area (HA; RA2; RA2-A) adjacent to the first display area (AA; RA1; RA1-A), the second display area (HA; RA2; RA1-A) comprising a hole area which comprises a module hole, the hole area being surrounded by an active area, the second display area overlapping with the electronic module (EM; EM2; EM-A), and comprising: a circuit layer comprising driving elements comprising thin film transistors; and a display element layer comprising one or more light emitting elements and a deposition preventing pattern (PD; PD-A), wherein the deposition preventing pattern (PD; PD-A) is configured to prevent the deposition of conductive material at the deposition preventing pattern (PD; PD-A), a circuit layer comprising driving elements comprising thin film transistors; and a display element layer comprising one or more light emitting elements and a deposition preventing pattern (PD; PD-A), wherein the deposition preventing pattern (PD; PD-A) is configured to prevent the deposition of conductive material at the deposition preventing pattern (PD; PD-A), wherein the light emitting elements comprise: first electrodes (E1, E1') connected to the thin film transistors; emission patterns on the first electrodes (E1, E1'); and a second electrode on the emission patterns, first electrodes (E1, E1') connected to the thin film transistors; emission patterns on the first electrodes (E1, E1'); and a second electrode on the emission patterns, wherein the deposition preventing pattern (PD; PD-A) is arranged on a same layer on which the second electrode is arranged, wherein the second electrode overlaps with the first display area (AA; RA1; RA1-A) and the second display area (HA; RA2; RA2-A), and wherein the deposition preventing pattern (PD; PD-A) overlaps with the hole area in the second display area (HA; RA2; RA2-A) wherein a first side of the deposition preventing pattern adjoins the second electrode at the limit between the active area and the hole area and a second side of the deposition preventing pattern, opposite to the first side, is exposed by the module hole.