A decoder circuit (1625, 1700) comprising an output node coupled to a coupling gate of a split-gate flash memory cell located in a P-well located in a deep N-well, comprising: a first circuit (1705, 1710) for providing a first positive voltage to the coupling gate through the output node when the flash memory cell is selected for a read operation, the first circuit comprising a first PMOS transistor comprising a drain terminal connected to a positive voltage source, and a source terminal and a second PMOS transistor comprising a drain terminal connected to the source terminal of the first PMOS transistor and a source terminal; a third PMOS transistor comprising a drain terminal connected to the source terminal of the second PMOS transistor and a source terminal connected to the coupling gate of the split-gate flash memory cell; a second circuit (1715, 1720) for providing a second positive voltage to the coupling gate through the output node when the flash memory cell is selected for a program operation, the second circuit comprising a fourth PMOS transistor comprising a drain terminal and a source terminal, and a fifth PMOS transistor comprising a drain terminal connected to the source terminal of the fourth PMOS transistor and a source terminal connected to the source terminal of the second PMOS transistor and the drain terminal of the third PMOS transistor; a third circuit (1750, 1755) for providing a negative voltage to the coupling gate through the output node when the flash memory cell is selected for an erase operation, the third circuit comprising a first NMOS transistor comprising a drain terminal and a source terminal, and a second NMOS transistor comprising a drain terminal directly connected to the source terminal of the first NMOS transistor and a source terminal connected to a negative voltage source; and a fourth circuit (1730, 1735, 1740, 1745) for providing a third positive voltage to the coupling gate through the output node when the flash memory cell is unselected for a read, program, or erase operation, the fourth circuit comprising a third NMOS transistor comprising a drain terminal directly connected to the source terminal of the third PMOS transistor and a source terminal directly connected to the drain terminal of the first NMOS transistor, a fourth NMOS transistor comprising a drain terminal directly connected to the source terminal of the third NMOS transistor and the drain terminal of the first NMOS transistor and a source terminal, a fifth NMOS transistor comprising a drain terminal connected to the source terminal of the fourth NMOS transistor and a source terminal, and a sixth NMOS transistor comprising a drain terminal connected to the source terminal of the fifth NMOS transistor and a source terminal connected to ground. a first circuit (1705, 1710) for providing a first positive voltage to the coupling gate through the output node when the flash memory cell is selected for a read operation, the first circuit comprising a first PMOS transistor comprising a drain terminal connected to a positive voltage source, and a source terminal and a second PMOS transistor comprising a drain terminal connected to the source terminal of the first PMOS transistor and a source terminal; a third PMOS transistor comprising a drain terminal connected to the source terminal of the second PMOS transistor and a source terminal connected to the coupling gate of the split-gate flash memory cell; a second circuit (1715, 1720) for providing a second positive voltage to the coupling gate through the output node when the flash memory cell is selected for a program operation, the second circuit comprising a fourth PMOS transistor comprising a drain terminal and a source terminal, and a fifth PMOS transistor comprising a drain terminal connected to the source terminal of the fourth PMOS transistor and a source terminal connected to the source terminal of the second PMOS transistor and the drain terminal of the third PMOS transistor; a third circuit (1750, 1755) for providing a negative voltage to the coupling gate through the output node when the flash memory cell is selected for an erase operation, the third circuit comprising a first NMOS transistor comprising a drain terminal and a source terminal, and a second NMOS transistor comprising a drain terminal directly connected to the source terminal of the first NMOS transistor and a source terminal connected to a negative voltage source; and a fourth circuit (1730, 1735, 1740, 1745) for providing a third positive voltage to the coupling gate through the output node when the flash memory cell is unselected for a read, program, or erase operation, the fourth circuit comprising a third NMOS transistor comprising a drain terminal directly connected to the source terminal of the third PMOS transistor and a source terminal directly connected to the drain terminal of the first NMOS transistor, a fourth NMOS transistor comprising a drain terminal directly connected to the source terminal of the third NMOS transistor and the drain terminal of the first NMOS transistor and a source terminal, a fifth NMOS transistor comprising a drain terminal connected to the source terminal of the fourth NMOS transistor and a source terminal, and a sixth NMOS transistor comprising a drain terminal connected to the source terminal of the fifth NMOS transistor and a source terminal connected to ground.