Memory comprising: - a matrix of resistive memory cells with: ∘ line electrical tracks (L 1, L i, L n), ∘ column electrical tracks (C 1, C j, C m), and o resistive memory cells located at the crossings between the line electrical tracks (L 1, L i, L n) and the column electrical tracks (C 1, C j, C m), each memory cell being connected between, on the one hand, one of the line electrical tracks and, on the other hand, one of the column electrical tracks, - the memory comprising an interfacing device for interfacing said matrix, the interfacing device comprising at least one conversion capacitor, a voltage measuring device connected to the terminals of the conversion capacitor, an electrical source, a first switch, a second switch and a control module, the interfacing device being configured to execute the following steps: o step a): connecting the conversion capacitor to the source by means of the second switch to charge the conversion capacitor, then o step b): - disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the line electrical tracks (L i) and one of the column electrical tracks (C j), by means of the first switch, then - acquiring a read result voltage (V R), at the terminals (11, 12) of the conversion capacitor, by means of the voltage measuring device, then - determining a resistive state of said cellule, by the control module, based on said read result voltage (V R). - a matrix of resistive memory cells with: ∘ line electrical tracks (L 1, L i, L n), ∘ column electrical tracks (C 1, C j, C m), and o resistive memory cells located at the crossings between the line electrical tracks (L 1, L i, L n) and the column electrical tracks (C 1, C j, C m), each memory cell being connected between, on the one hand, one of the line electrical tracks and, on the other hand, one of the column electrical tracks, ∘ line electrical tracks (L 1, L i, L n), ∘ column electrical tracks (C 1, C j, C m), and o resistive memory cells located at the crossings between the line electrical tracks (L 1, L i, L n) and the column electrical tracks (C 1, C j, C m), each memory cell being connected between, on the one hand, one of the line electrical tracks and, on the other hand, one of the column electrical tracks, - the memory comprising an interfacing device for interfacing said matrix, the interfacing device comprising at least one conversion capacitor, a voltage measuring device connected to the terminals of the conversion capacitor, an electrical source, a first switch, a second switch and a control module, the interfacing device being configured to execute the following steps: o step a): connecting the conversion capacitor to the source by means of the second switch to charge the conversion capacitor, then o step b): - disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the line electrical tracks (L i) and one of the column electrical tracks (C j), by means of the first switch, then - acquiring a read result voltage (V R), at the terminals (11, 12) of the conversion capacitor, by means of the voltage measuring device, then - determining a resistive state of said cellule, by the control module, based on said read result voltage (V R). o step a): connecting the conversion capacitor to the source by means of the second switch to charge the conversion capacitor, then o step b): - disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the line electrical tracks (L i) and one of the column electrical tracks (C j), by means of the first switch, then - acquiring a read result voltage (V R), at the terminals (11, 12) of the conversion capacitor, by means of the voltage measuring device, then - determining a resistive state of said cellule, by the control module, based on said read result voltage (V R). - disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the line electrical tracks (L i) and one of the column electrical tracks (C j), by means of the first switch, then - acquiring a read result voltage (V R), at the terminals (11, 12) of the conversion capacitor, by means of the voltage measuring device, then - determining a resistive state of said cellule, by the control module, based on said read result voltage (V R).