An electronic circuit for a memory device, comprising: means for determining a cell condition for a resistive random access memory, RRAM, cell based on a measured indication of a resistance of the RRAM cell of a state previously written to the RRAM cell, wherein the means for determining the cell condition comprises a measurement circuit to determine the measured indication of the resistance of the RRAM cell, and wherein the measured indication of the resistance comprises a digital value having a higher bit resolution than a data read value of the RRAM cell, the data read value comprising a number of bits for the RRAM cell, and the digital value having a number of bits greater than the number of bits for the data read value of the RRAM cell; and write circuitry comprising an adjustable write driver to write the state to the RRAM cell using a write condition based on the determined cell condition, wherein the write circuitry is configured to adjust a strength of the write condition when the resistance of the RRAM cell is above or below a threshold resistance for the state, wherein the write driver is to: write to the RRAM cell using weaker set conditions when the RRAM cell is a high resistance RRAM cell with lower resistance, wherein the weaker set conditions comprise one or more of: a shorter set pulse; a lesser number of set pulses; a lower voltage; and a lower current; write to the RRAM cell using stronger set conditions when the RRAM cell is a high resistance state RRAM cell with higher resistance, wherein the stronger set conditions comprise one or more of: a longer set pulse; a greater number of set pulses; a greater voltage; and a greater current; write to the RRAM cell using stronger reset conditions when the RRAM cell is a low resistance state RRAM cell with lower resistance, wherein the stronger reset conditions comprise one or more of: a longer reset pulse; a greater number of set pulses; a greater voltage; and a greater current; and write to the RRAM cell using weaker reset conditions when the RRAM cell is a low resistance state RRAM cell with higher resistance, wherein the weaker reset conditions comprise one or more of: a shorter reset pulse; a lesser number of set pulses; a lower voltage; and a lower current. means for determining a cell condition for a resistive random access memory, RRAM, cell based on a measured indication of a resistance of the RRAM cell of a state previously written to the RRAM cell, wherein the means for determining the cell condition comprises a measurement circuit to determine the measured indication of the resistance of the RRAM cell, and wherein the measured indication of the resistance comprises a digital value having a higher bit resolution than a data read value of the RRAM cell, the data read value comprising a number of bits for the RRAM cell, and the digital value having a number of bits greater than the number of bits for the data read value of the RRAM cell; and write circuitry comprising an adjustable write driver to write the state to the RRAM cell using a write condition based on the determined cell condition, wherein the write circuitry is configured to adjust a strength of the write condition when the resistance of the RRAM cell is above or below a threshold resistance for the state, wherein the write driver is to: write to the RRAM cell using weaker set conditions when the RRAM cell is a high resistance RRAM cell with lower resistance, wherein the weaker set conditions comprise one or more of: a shorter set pulse; a lesser number of set pulses; a lower voltage; and a lower current; write to the RRAM cell using stronger set conditions when the RRAM cell is a high resistance state RRAM cell with higher resistance, wherein the stronger set conditions comprise one or more of: a longer set pulse; a greater number of set pulses; a greater voltage; and a greater current; write to the RRAM cell using stronger reset conditions when the RRAM cell is a low resistance state RRAM cell with lower resistance, wherein the stronger reset conditions comprise one or more of: a longer reset pulse; a greater number of set pulses; a greater voltage; and a greater current; and write to the RRAM cell using weaker reset conditions when the RRAM cell is a low resistance state RRAM cell with higher resistance, wherein the weaker reset conditions comprise one or more of: a shorter reset pulse; a lesser number of set pulses; a lower voltage; and a lower current. write to the RRAM cell using weaker set conditions when the RRAM cell is a high resistance RRAM cell with lower resistance, wherein the weaker set conditions comprise one or more of: a shorter set pulse; a lesser number of set pulses; a lower voltage; and a lower current; write to the RRAM cell using stronger set conditions when the RRAM cell is a high resistance state RRAM cell with higher resistance, wherein the stronger set conditions comprise one or more of: a longer set pulse; a greater number of set pulses; a greater voltage; and a greater current; write to the RRAM cell using stronger reset conditions when the RRAM cell is a low resistance state RRAM cell with lower resistance, wherein the stronger reset conditions comprise one or more of: a longer reset pulse; a greater number of set pulses; a greater voltage; and a greater current; and write to the RRAM cell using weaker reset conditions when the RRAM cell is a low resistance state RRAM cell with higher resistance, wherein the weaker reset conditions comprise one or more of: a shorter reset pulse; a lesser number of set pulses; a lower voltage; and a lower current.