A level translator that receives an input signal at an input terminal A, and generates an output signal at an output terminal B, the level translator comprising: first, second, third and fourth one-shot circuits, wherein the first and third one-shot circuits each has an input connected to the output terminal B and the second and fourth one-shot circuits each has an input connected to the input terminal A; a first transistor having a source connected to a first voltage source (VCCA), a drain connected to the input terminal A, and a gate connected to an output of the first one-shot circuit; a second transistor having a source connected to a second voltage source (VCCB) that is different from the first voltage source, a drain connected to the output terminal B, and a gate connected to an output of the second one-shot circuit; a third transistor having a drain connected to the input terminal A, a source connected to ground, and a gate connected to an output of the third one-shot circuit; a fourth transistor having a source connected to ground, a drain connected to the output terminal B, and a gate connected to an output of the fourth one-shot circuit; a first switch connected in series to a first resistor where the series of the first switch and the first resistor is connected in parallel with the first transistor, wherein the first switch has a first terminal connected to the first voltage source and a second terminal connected to a first terminal of the first resistor and wherein a second terminal of the first resistor is connected to the input terminal A; and a second switch connected is series to a second resistor where the series of the second switch and the second resistor is connected in parallel with the second transistor, wherein the second switch has a first terminal connected to the second voltage source and a second terminal connected to a first terminal of the second resistor and wherein a second terminal of the second resistor is connected to the output terminal B wherein the first switch is configured to be on during a rise time of the input signal at the input terminal A and off at other times and the second switch is configured to be on during a rise time of an input signal at the output terminal B and off at other times, thereby respectively preventing current leakage from the input terminal A to the output terminal B, and from the output terminal B to the input terminal A first, second, third and fourth one-shot circuits, wherein the first and third one-shot circuits each has an input connected to the output terminal B and the second and fourth one-shot circuits each has an input connected to the input terminal A; a first transistor having a source connected to a first voltage source (VCCA), a drain connected to the input terminal A, and a gate connected to an output of the first one-shot circuit; a second transistor having a source connected to a second voltage source (VCCB) that is different from the first voltage source, a drain connected to the output terminal B, and a gate connected to an output of the second one-shot circuit; a third transistor having a drain connected to the input terminal A, a source connected to ground, and a gate connected to an output of the third one-shot circuit; a fourth transistor having a source connected to ground, a drain connected to the output terminal B, and a gate connected to an output of the fourth one-shot circuit; a first switch connected in series to a first resistor where the series of the first switch and the first resistor is connected in parallel with the first transistor, wherein the first switch has a first terminal connected to the first voltage source and a second terminal connected to a first terminal of the first resistor and wherein a second terminal of the first resistor is connected to the input terminal A; and a second switch connected is series to a second resistor where the series of the second switch and the second resistor is connected in parallel with the second transistor, wherein the second switch has a first terminal connected to the second voltage source and a second terminal connected to a first terminal of the second resistor and wherein a second terminal of the second resistor is connected to the output terminal B wherein the first switch is configured to be on during a rise time of the input signal at the input terminal A and off at other times and the second switch is configured to be on during a rise time of an input signal at the output terminal B and off at other times, thereby respectively preventing current leakage from the input terminal A to the output terminal B, and from the output terminal B to the input terminal A