An apparatus comprising: an instruction decoder to decode instructions; and processing circuitry to perform data processing in response to instructions decoded by the instruction decoder; in which: in response to a branch instruction, the instruction decoder is configured to control the processing circuitry to trigger a non-sequential change of program flow to an instruction at a target address; when the non-sequential change of program flow is triggered in response to a branch-with-link instruction, the instruction decoder is configured to control the processing circuitry to set a return address for a subsequent return of program flow; when the non-sequential change of program flow is triggered in response to at least one target-checking type of branch instruction, the instruction decoder is configured to control the processing circuitry to trigger an error handling response when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction; and for at least a subset of said at least one target-checking type of branch instruction, said at least one permitted type of branch target instruction includes a branch target variant of the branch-with-link instruction; in response to the branch target variant of the branch-with-link instruction, the processing circuitry is configured to set the return address to an address of the branch target variant of the branch-with-link instruction; and the processing circuitry is configured to suppress a non-sequential change of program flow associated with the branch target variant of the branch-with-link instruction, when program flow passes non-sequentially from a branch instruction of said at least one target-checking type to the branch target variant of the branch-with-link instruction. an instruction decoder to decode instructions; and processing circuitry to perform data processing in response to instructions decoded by the instruction decoder; in which: in response to a branch instruction, the instruction decoder is configured to control the processing circuitry to trigger a non-sequential change of program flow to an instruction at a target address; when the non-sequential change of program flow is triggered in response to a branch-with-link instruction, the instruction decoder is configured to control the processing circuitry to set a return address for a subsequent return of program flow; when the non-sequential change of program flow is triggered in response to at least one target-checking type of branch instruction, the instruction decoder is configured to control the processing circuitry to trigger an error handling response when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction; and for at least a subset of said at least one target-checking type of branch instruction, said at least one permitted type of branch target instruction includes a branch target variant of the branch-with-link instruction; in response to the branch target variant of the branch-with-link instruction, the processing circuitry is configured to set the return address to an address of the branch target variant of the branch-with-link instruction; and the processing circuitry is configured to suppress a non-sequential change of program flow associated with the branch target variant of the branch-with-link instruction, when program flow passes non-sequentially from a branch instruction of said at least one target-checking type to the branch target variant of the branch-with-link instruction. in response to a branch instruction, the instruction decoder is configured to control the processing circuitry to trigger a non-sequential change of program flow to an instruction at a target address; when the non-sequential change of program flow is triggered in response to a branch-with-link instruction, the instruction decoder is configured to control the processing circuitry to set a return address for a subsequent return of program flow; when the non-sequential change of program flow is triggered in response to at least one target-checking type of branch instruction, the instruction decoder is configured to control the processing circuitry to trigger an error handling response when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction; and for at least a subset of said at least one target-checking type of branch instruction, said at least one permitted type of branch target instruction includes a branch target variant of the branch-with-link instruction; in response to the branch target variant of the branch-with-link instruction, the processing circuitry is configured to set the return address to an address of the branch target variant of the branch-with-link instruction; and the processing circuitry is configured to suppress a non-sequential change of program flow associated with the branch target variant of the branch-with-link instruction, when program flow passes non-sequentially from a branch instruction of said at least one target-checking type to the branch target variant of the branch-with-link instruction.