A digital-to-analog conversion circuit for converting a first digital input into a first analog output (AA_OUT), comprising: a segmentation circuit (112, 700, 900), arranged to apply segmentation to the first digital input (A, D_IN) to generate a plurality of code segments; a plurality of multi-bit dynamic element matching digital-to-analog converters, DEM DACs, (114_1-114_N) arranged to convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs (114_1-114_N) comprise at least a first multi-bit DEM DAC and a second multi-bit DEM DAC; and a combination circuit, arranged to combine the DAC outputs to generate the first analog output (AA_OUT); wherein the first multi-bit DEM DAC employs a first DEM technique that uses a rotated pulse width modulation, PWM, algorithm; wherein the second multi-bit DEM DAC employs a second DEM technique that uses a data weighted averaging, DWA, algorithm or a scrambling algorithm; wherein complexity of the second DEM technique is lower than complexity of the first DEM technique and wherein the segmentation circuit (112, 700, 900) is a noise shaped segmentation circuit, arranged to reduce a bit length of the first digital input to generate a first code segment and subtract the first code segment from the first digital input to generate a code segment from which a second code segment (C, C1, C2) is derived, wherein the code segments comprise the first code segment that is associated with a most significant bit, MSB, part of the first digital input and the second code segment (C,C1,C2) that is associated with a least significant bit, LSB, part of the first digital input, the DAC outputs comprise a first DAC output and a second DAC output, the first multi-bit DEM DAC is arranged to convert the first code segment into the first DAC output, and the second multi-bit DEM DAC is arranged to convert the second code segment (C, C1, C2) into the second DAC output. a segmentation circuit (112, 700, 900), arranged to apply segmentation to the first digital input (A, D_IN) to generate a plurality of code segments; a plurality of multi-bit dynamic element matching digital-to-analog converters, DEM DACs, (114_1-114_N) arranged to convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs (114_1-114_N) comprise at least a first multi-bit DEM DAC and a second multi-bit DEM DAC; and a combination circuit, arranged to combine the DAC outputs to generate the first analog output (AA_OUT); wherein the first multi-bit DEM DAC employs a first DEM technique that uses a rotated pulse width modulation, PWM, algorithm; wherein the second multi-bit DEM DAC employs a second DEM technique that uses a data weighted averaging, DWA, algorithm or a scrambling algorithm; wherein complexity of the second DEM technique is lower than complexity of the first DEM technique and wherein the segmentation circuit (112, 700, 900) is a noise shaped segmentation circuit, arranged to reduce a bit length of the first digital input to generate a first code segment and subtract the first code segment from the first digital input to generate a code segment from which a second code segment (C, C1, C2) is derived, wherein the code segments comprise the first code segment that is associated with a most significant bit, MSB, part of the first digital input and the second code segment (C,C1,C2) that is associated with a least significant bit, LSB, part of the first digital input, the DAC outputs comprise a first DAC output and a second DAC output, the first multi-bit DEM DAC is arranged to convert the first code segment into the first DAC output, and the second multi-bit DEM DAC is arranged to convert the second code segment (C, C1, C2) into the second DAC output.