A data processing apparatus comprising: data processing circuitry for performing data processing operations in response to execution of program instructions; debug circuitry for performing debug operations controlled by debug software executing on said data processing circuitry; said data processing apparatus comprising a data store for storing a current debug exception mask value; said data processing circuitry being configured to set said current debug exception mask value to a first value in said data store in response to executing critical code and on termination of execution of said critical code to reset said current debug exception mask value to not store said first value; wherein said data processing circuitry is configured to execute program instructions corresponding to a plurality of different software hierarchical levels, a higher software hierarchical level being a level with greater privileges than a lower software hierarchical level such that there are at least some data storage locations that can be accessed from said higher hierarchical level and cannot be accessed from said lower hierarchical level; and said data processing circuitry is configured to allow a debug exception to be taken when said debug software is to be executed at a same hierarchical level as a level software is currently operating at if said current debug exception mask value is not set to said first value, and not to allow said debug exception to be taken if said current debug exception mask value is set to said first value, and to allow a debug exception when said debug software is to be executed at a higher predetermined software hierarchical level to be taken, wherein said critical code comprises at least one of: a plurality of instructions interruption of which may generate a software malfunction; code for storing a state of a processor to a data store; code for restoring a state of a processor from state stored in a data store; code for accessing a memory region that might generate a synchronous exception; code for saving or restoring register values configuring the apparatus; code acknowledging, disabling or re-enabling interrupt system registers; and operating system code. data processing circuitry for performing data processing operations in response to execution of program instructions; debug circuitry for performing debug operations controlled by debug software executing on said data processing circuitry; said data processing apparatus comprising a data store for storing a current debug exception mask value; said data processing circuitry being configured to set said current debug exception mask value to a first value in said data store in response to executing critical code and on termination of execution of said critical code to reset said current debug exception mask value to not store said first value; wherein said data processing circuitry is configured to execute program instructions corresponding to a plurality of different software hierarchical levels, a higher software hierarchical level being a level with greater privileges than a lower software hierarchical level such that there are at least some data storage locations that can be accessed from said higher hierarchical level and cannot be accessed from said lower hierarchical level; and said data processing circuitry is configured to allow a debug exception to be taken when said debug software is to be executed at a same hierarchical level as a level software is currently operating at if said current debug exception mask value is not set to said first value, and not to allow said debug exception to be taken if said current debug exception mask value is set to said first value, and to allow a debug exception when said debug software is to be executed at a higher predetermined software hierarchical level to be taken, wherein said critical code comprises at least one of: a plurality of instructions interruption of which may generate a software malfunction; code for storing a state of a processor to a data store; code for restoring a state of a processor from state stored in a data store; code for accessing a memory region that might generate a synchronous exception; code for saving or restoring register values configuring the apparatus; code acknowledging, disabling or re-enabling interrupt system registers; and operating system code. a plurality of instructions interruption of which may generate a software malfunction; code for storing a state of a processor to a data store; code for restoring a state of a processor from state stored in a data store; code for accessing a memory region that might generate a synchronous exception; code for saving or restoring register values configuring the apparatus; code acknowledging, disabling or re-enabling interrupt system registers; and operating system code.