A non-volatile, ternary content addressable memory device utilizing resistive random access memory, RRAM, technology, wherein the non-volatile, ternary content addressable memory device comprises an array of memory cells including: a first memory cell (133, 321, 625), including: a first programmable resistive element (104, 302, 604) including a first terminal and a second terminal; a second programmable resistive element (105, 303, 605) including a first terminal and a second terminal; and a third programmable resistive element (106, 304, 606) including a first terminal and a second terminal, characterized in that the first terminals of the first, second, and third programmable resistive elements (104, 302, 604, 105, 303, 605, 106, 304, 606) are directly coupled to a first node, the second terminal of the first programmable resistive element (104, 302, 604) is coupled to a first source line voltage, the second terminal of the second programmable resistive element (105, 303, 605) is coupled to a second source line voltage, and the second terminal of the third programmable resistive element (106, 304, 606) is coupled to a first supply voltage; wherein the first memory cell (133, 321, 625) further includes: a first access transistor (101, 301, 601) including a first current electrode coupled to a bit line, a second current electrode coupled to the first node, and a control electrode coupled to a first word line; and a match line transistor (108, 305, 603) including a first current electrode coupled to a first match line, a second current electrode coupled to a second supply voltage, and a control electrode coupled to the first node. a first memory cell (133, 321, 625), including: a first programmable resistive element (104, 302, 604) including a first terminal and a second terminal; a second programmable resistive element (105, 303, 605) including a first terminal and a second terminal; and a third programmable resistive element (106, 304, 606) including a first terminal and a second terminal, a first programmable resistive element (104, 302, 604) including a first terminal and a second terminal; a second programmable resistive element (105, 303, 605) including a first terminal and a second terminal; and a third programmable resistive element (106, 304, 606) including a first terminal and a second terminal, characterized in that the first terminals of the first, second, and third programmable resistive elements (104, 302, 604, 105, 303, 605, 106, 304, 606) are directly coupled to a first node, the second terminal of the first programmable resistive element (104, 302, 604) is coupled to a first source line voltage, the second terminal of the second programmable resistive element (105, 303, 605) is coupled to a second source line voltage, and the second terminal of the third programmable resistive element (106, 304, 606) is coupled to a first supply voltage; the first terminals of the first, second, and third programmable resistive elements (104, 302, 604, 105, 303, 605, 106, 304, 606) are directly coupled to a first node, the second terminal of the first programmable resistive element (104, 302, 604) is coupled to a first source line voltage, the second terminal of the second programmable resistive element (105, 303, 605) is coupled to a second source line voltage, and the second terminal of the third programmable resistive element (106, 304, 606) is coupled to a first supply voltage; wherein the first memory cell (133, 321, 625) further includes: a first access transistor (101, 301, 601) including a first current electrode coupled to a bit line, a second current electrode coupled to the first node, and a control electrode coupled to a first word line; and a match line transistor (108, 305, 603) including a first current electrode coupled to a first match line, a second current electrode coupled to a second supply voltage, and a control electrode coupled to the first node. a first access transistor (101, 301, 601) including a first current electrode coupled to a bit line, a second current electrode coupled to the first node, and a control electrode coupled to a first word line; and a match line transistor (108, 305, 603) including a first current electrode coupled to a first match line, a second current electrode coupled to a second supply voltage, and a control electrode coupled to the first node.