An electrostatic protection circuit, wherein the electrostatic protection circuit comprises: at least one first transistor and at least one second transistor, wherein a gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line; a gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line; wherein the first signal line and the second signal line are any two adjacent signal lines on an array substrate, and the first electrode and the second electrode are one of a source electrode and a drain electrode, respectively; an orthographic projection of an end, close to a channel, of at least one of the first electrode (12, 22) and the second electrode (13, 23) of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the channel, and an upper base of the trapezoid is close to the channel relative to a lower base thereof; and the channel of each of the transistors (M1, M2) meets at least one of the following requirements: an orthographic projection of an end, close to the first electrode (12, 22), of the channel of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the first electrode (12, 22), and an upper base of the trapezoid is close to the first electrode (12, 22) relative to a lower base thereof; and an orthographic projection of an end, close to the second electrode (13, 23), of the channel of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the second electrode (13, 23), and an upper base of the trapezoid is close to the second electrode (13, 23) relative to a lower base thereof. a gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line; a gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line; wherein the first signal line and the second signal line are any two adjacent signal lines on an array substrate, and the first electrode and the second electrode are one of a source electrode and a drain electrode, respectively; an orthographic projection of an end, close to a channel, of at least one of the first electrode (12, 22) and the second electrode (13, 23) of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the channel, and an upper base of the trapezoid is close to the channel relative to a lower base thereof; and the channel of each of the transistors (M1, M2) meets at least one of the following requirements: an orthographic projection of an end, close to the first electrode (12, 22), of the channel of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the first electrode (12, 22), and an upper base of the trapezoid is close to the first electrode (12, 22) relative to a lower base thereof; and an orthographic projection of an end, close to the second electrode (13, 23), of the channel of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the second electrode (13, 23), and an upper base of the trapezoid is close to the second electrode (13, 23) relative to a lower base thereof. an orthographic projection of an end, close to the first electrode (12, 22), of the channel of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the first electrode (12, 22), and an upper base of the trapezoid is close to the first electrode (12, 22) relative to a lower base thereof; and an orthographic projection of an end, close to the second electrode (13, 23), of the channel of each of the transistors (M1, M2) on the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the second electrode (13, 23), and an upper base of the trapezoid is close to the second electrode (13, 23) relative to a lower base thereof.