A monostable circuit, comprising: a delay cell (20'; 20"), comprising: a reference inverter having its input coupled to its output and configured to generate a threshold voltage (Vth); an adjustable resistance being a process, voltage and temperature, PVT, invariant resistance, a reference current generator configured to generate a reference current (Iref) as a ratio of the threshold voltage and the PVT invariant resistance; and a delay block (22; 22') comprising: an output capacitor (C2; C2'); and an output circuit configured to alter an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal (INB; IN); an output inverter (27; 27') having an input coupled to the output circuit of the delay block and having an output; and a logic circuit (42; 42') configured to logically combine the output of the output inverter and the input signal to generate a monostable trigger pulse, wherein the output circuit of the delay block (22; 22') comprises: a first p-channel transistor having a source coupled to receive the reference current (Iref), a drain, and a gate coupled to receive the input signal (INB; IN); a second p-channel transistor having a source coupled to the source of the first p-channel transistor, a drain coupled to ground, and a gate coupled to receive a complement of the input signal (INB; IN); and an n-channel transistor having a drain coupled to the drain of the first p-channel transistor, a source coupled to ground, and a gate coupled to receive the input signal (INB; IN); and wherein the output capacitor (C2; C2') is coupled between the drain of the n-channel transistor and ground. a delay cell (20'; 20"), comprising: a reference inverter having its input coupled to its output and configured to generate a threshold voltage (Vth); an adjustable resistance being a process, voltage and temperature, PVT, invariant resistance, a reference current generator configured to generate a reference current (Iref) as a ratio of the threshold voltage and the PVT invariant resistance; and a delay block (22; 22') comprising: an output capacitor (C2; C2'); and an output circuit configured to alter an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal (INB; IN); a reference inverter having its input coupled to its output and configured to generate a threshold voltage (Vth); an adjustable resistance being a process, voltage and temperature, PVT, invariant resistance, a reference current generator configured to generate a reference current (Iref) as a ratio of the threshold voltage and the PVT invariant resistance; and a delay block (22; 22') comprising: an output capacitor (C2; C2'); and an output circuit configured to alter an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal (INB; IN); an output capacitor (C2; C2'); and an output circuit configured to alter an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal (INB; IN); an output inverter (27; 27') having an input coupled to the output circuit of the delay block and having an output; and a logic circuit (42; 42') configured to logically combine the output of the output inverter and the input signal to generate a monostable trigger pulse, wherein the output circuit of the delay block (22; 22') comprises: a first p-channel transistor having a source coupled to receive the reference current (Iref), a drain, and a gate coupled to receive the input signal (INB; IN); a second p-channel transistor having a source coupled to the source of the first p-channel transistor, a drain coupled to ground, and a gate coupled to receive a complement of the input signal (INB; IN); and an n-channel transistor having a drain coupled to the drain of the first p-channel transistor, a source coupled to ground, and a gate coupled to receive the input signal (INB; IN); and a first p-channel transistor having a source coupled to receive the reference current (Iref), a drain, and a gate coupled to receive the input signal (INB; IN); a second p-channel transistor having a source coupled to the source of the first p-channel transistor, a drain coupled to ground, and a gate coupled to receive a complement of the input signal (INB; IN); and an n-channel transistor having a drain coupled to the drain of the first p-channel transistor, a source coupled to ground, and a gate coupled to receive the input signal (INB; IN); and wherein the output capacitor (C2; C2') is coupled between the drain of the n-channel transistor and ground.