A method of operating a multiple execution unit processor having an instruction pipeline and a loop cache memory capable of storing N execute packets of instructions, each execute packet corresponding to a set of one or more instructions that will be dispatched to the execution units of the processor during the same clock cycle, wherein N is an integer greater than one and the N execute packets of instructions form a loop prolog, a loop kernel and a loop epilog, said method comprising the steps of: (a) providing a loop cache memory for storing N execute packets; (b) fetching a fetch packet comprising N execute packets of instructions; (c) during a loop prolog: (i) issuing said N execute packets to particular decode units corresponding to associated execution units (D1, D2, L1, L2, S1, S2, M1, M2), and (ii) building, in said loop cache memory, n built execute packets out of the N execute packets fetched and stored in memory by regrouping those instructions which can be executed in parallel since they are to be executed on different execution units of the processor, wherein n is an integer greater than one; (d) stalling the dispatch stage of the pipeline until all of said execute packets of the fetch packet have been issued and stored as built execute packets in the loop cache memory; (e) repeating steps (b) to (d) until all fetch packets of the loop are executed from the instruction pipeline; (f) wherein for each iteration of the loop kernel, issuing said built execute packets in said loop cache memory to said particular decode units corresponding to associated execution units (D1, D2, L1, L2, S1, S2, M1, M2); (g) stalling said dispatch stage of the instruction pipeline until all iterations of the loop are executed; and (h) executing the loop epilog. (a) providing a loop cache memory for storing N execute packets; (b) fetching a fetch packet comprising N execute packets of instructions; (c) during a loop prolog: (i) issuing said N execute packets to particular decode units corresponding to associated execution units (D1, D2, L1, L2, S1, S2, M1, M2), and (ii) building, in said loop cache memory, n built execute packets out of the N execute packets fetched and stored in memory by regrouping those instructions which can be executed in parallel since they are to be executed on different execution units of the processor, wherein n is an integer greater than one; (i) issuing said N execute packets to particular decode units corresponding to associated execution units (D1, D2, L1, L2, S1, S2, M1, M2), and (ii) building, in said loop cache memory, n built execute packets out of the N execute packets fetched and stored in memory by regrouping those instructions which can be executed in parallel since they are to be executed on different execution units of the processor, wherein n is an integer greater than one; (d) stalling the dispatch stage of the pipeline until all of said execute packets of the fetch packet have been issued and stored as built execute packets in the loop cache memory; (e) repeating steps (b) to (d) until all fetch packets of the loop are executed from the instruction pipeline; (f) wherein for each iteration of the loop kernel, issuing said built execute packets in said loop cache memory to said particular decode units corresponding to associated execution units (D1, D2, L1, L2, S1, S2, M1, M2); (g) stalling said dispatch stage of the instruction pipeline until all iterations of the loop are executed; and (h) executing the loop epilog.