A processor system adapted to execute instructions from multiple instruction threads in interleaved fashion, the processor system comprising: a plurality of pipelines (135A-C) each including an execution unit (145 A-B); an instruction cache; a context unit including a plurality of rows (310 A-L), each of the plurality of rows: - being assigned to an independent thread, - including at least one program counter, - including instruction block storage configured to store one or more instructions, - including logic configured to fetch the one or more instructions from the instruction cache, and - including logic configured to determine when an instruction is ready to be issued to the pipeline (135A-C) from the respective row (310 A-L); and a logical register file set comprised of a plurality of register files (125 A-C) that are mapped to a plurality of physical memory arrays, each of the memory arrays having an access time and a plurality of access ports, each register file (125 A-C) of the register file set being assigned to a different hardware context; wherein each of the plurality of said hardware contexts being hardware dedicated to executing an independent thread and comprises: one of the logical register files (125 A-C) and a row (310 A-L) of said context unit, wherein the rows (310 A-L) are associated with different hardware contexts; and issue logic configured to: select a row (310 A-L) from among the plurality of rows (310 A-L), wherein the selection of the row (310 A-L) is based on a selected row (310 A-L) being in a ready state, and issue an instruction from the selected row (310 A-L) to one of the plurality of pipelines (135 A-B); wherein the issue logic is configured to alternatively select different rows (310 A-L) of the plurality of rows (310 A-L), such that a row (310 A-L) of the same hardware context is not selected more than once within a time required to access one of the memory arrays. a plurality of pipelines (135A-C) each including an execution unit (145 A-B); an instruction cache; a context unit including a plurality of rows (310 A-L), each of the plurality of rows: - being assigned to an independent thread, - including at least one program counter, - including instruction block storage configured to store one or more instructions, - including logic configured to fetch the one or more instructions from the instruction cache, and - including logic configured to determine when an instruction is ready to be issued to the pipeline (135A-C) from the respective row (310 A-L); and - being assigned to an independent thread, - including at least one program counter, - including instruction block storage configured to store one or more instructions, - including logic configured to fetch the one or more instructions from the instruction cache, and - including logic configured to determine when an instruction is ready to be issued to the pipeline (135A-C) from the respective row (310 A-L); and a logical register file set comprised of a plurality of register files (125 A-C) that are mapped to a plurality of physical memory arrays, each of the memory arrays having an access time and a plurality of access ports, each register file (125 A-C) of the register file set being assigned to a different hardware context; wherein each of the plurality of said hardware contexts being hardware dedicated to executing an independent thread and comprises: one of the logical register files (125 A-C) and a row (310 A-L) of said context unit, wherein the rows (310 A-L) are associated with different hardware contexts; and one of the logical register files (125 A-C) and a row (310 A-L) of said context unit, wherein the rows (310 A-L) are associated with different hardware contexts; and issue logic configured to: select a row (310 A-L) from among the plurality of rows (310 A-L), wherein the selection of the row (310 A-L) is based on a selected row (310 A-L) being in a ready state, and issue an instruction from the selected row (310 A-L) to one of the plurality of pipelines (135 A-B); select a row (310 A-L) from among the plurality of rows (310 A-L), wherein the selection of the row (310 A-L) is based on a selected row (310 A-L) being in a ready state, and issue an instruction from the selected row (310 A-L) to one of the plurality of pipelines (135 A-B); wherein the issue logic is configured to alternatively select different rows (310 A-L) of the plurality of rows (310 A-L), such that a row (310 A-L) of the same hardware context is not selected more than once within a time required to access one of the memory arrays.