A microprocessor apparatus, for performing a block memory copy operation, the apparatus comprising: translation logic, configured to translate a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to locally allocate a first block of cache lines in an exclusive state without fetching said first block of cache lines and to copy the contents of a second block of cache lines to said first block of cache lines, wherein said block allocate and rename instruction comprises a modification to an existing prefetch instruction within an existing instruction set, and wherein said existing prefetch instruction does not otherwise provide for allocation and rename of said first block of cache lines, and wherein said block allocate and rename instruction comprises a prefetch opcode field within an extended address specifier entity, and wherein a specific value of said prefetch opcode field directs said microprocessor to allocate said first block of cache lines in said exclusive state and to copy said contents of said second block of cache lines to said first block of cache lines, and wherein other values of said prefetch opcode field direct said microprocessor to execute other types of prefetch operations according to said existing instruction set, and wherein said prefetch opcode field comprises bits 5:3 within the ModR/M byte of an x86 prefetch instruction; and execution logic, coupled to said translation logic, configured to receive said micro instruction sequence, and configured to issue transactions over a memory bus to obtain exclusive ownership of said first block of cache lines without transferring said first block of cache lines from memory, and configured to copy said contents of said second block of cache lines to said first block of cache lines. translation logic, configured to translate a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to locally allocate a first block of cache lines in an exclusive state without fetching said first block of cache lines and to copy the contents of a second block of cache lines to said first block of cache lines, wherein said block allocate and rename instruction comprises a modification to an existing prefetch instruction within an existing instruction set, and wherein said existing prefetch instruction does not otherwise provide for allocation and rename of said first block of cache lines, and wherein said block allocate and rename instruction comprises a prefetch opcode field within an extended address specifier entity, and wherein a specific value of said prefetch opcode field directs said microprocessor to allocate said first block of cache lines in said exclusive state and to copy said contents of said second block of cache lines to said first block of cache lines, and wherein other values of said prefetch opcode field direct said microprocessor to execute other types of prefetch operations according to said existing instruction set, and wherein said prefetch opcode field comprises bits 5:3 within the ModR/M byte of an x86 prefetch instruction; and execution logic, coupled to said translation logic, configured to receive said micro instruction sequence, and configured to issue transactions over a memory bus to obtain exclusive ownership of said first block of cache lines without transferring said first block of cache lines from memory, and configured to copy said contents of said second block of cache lines to said first block of cache lines.