A three-dimensional memory device (100, 200, 300, 400, 500, 600), comprising: a plurality of memory stacks comprising a first memory stack and a second memory stack arranged along a first direction, each memory stack comprising: a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction; and a channel structure extending through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction; a dummy structure disposed between the first memory stack and the second memory stack, the dummy structure extending along a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction; a first isolation structure disposed between the dummy structure and the first memory stack, the first isolation structure extending along the second direction and the third direction; a second isolation structure disposed between the dummy structure and the second memory stack, the second isolation structure extending along the second direction and the third direction; a semiconductor layer disposed under the plurality of memory stacks, the dummy structure, the first isolation structure, and the second isolation structure; and a trench isolation structure disposed in the semiconductor layer extending along the second direction and the third direction, wherein the trench isolation structure electrically isolates the semiconductor layer under each memory stack and wherein the trench isolation structure is disposed under the first and the second isolation structures and aligns to the first and the second isolation structures. a plurality of memory stacks comprising a first memory stack and a second memory stack arranged along a first direction, each memory stack comprising: a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction; and a channel structure extending through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction; a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction; and a channel structure extending through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction; a dummy structure disposed between the first memory stack and the second memory stack, the dummy structure extending along a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction; a first isolation structure disposed between the dummy structure and the first memory stack, the first isolation structure extending along the second direction and the third direction; a second isolation structure disposed between the dummy structure and the second memory stack, the second isolation structure extending along the second direction and the third direction; a semiconductor layer disposed under the plurality of memory stacks, the dummy structure, the first isolation structure, and the second isolation structure; and a trench isolation structure disposed in the semiconductor layer extending along the second direction and the third direction, wherein the trench isolation structure electrically isolates the semiconductor layer under each memory stack and wherein the trench isolation structure is disposed under the first and the second isolation structures and aligns to the first and the second isolation structures.