A pulse-width modulation control circuit (242, 3502) comprising: a first transistor (336, 2822) including a first terminal coupled to a power source and a second terminal coupled to a first input of a controlled component; and a signal generator (334, 2842, 3522, 3524) coupled to a gate of the first transistor (336, 2822), the signal generator (334, 2842, 3522, 3524) being configured to: receive a comparison value (3322, 3422) and two comparison criteria (3324, 3326, 3424, 3426); compare the comparison value (3322, 3422) to a counter value based on one of the comparison criteria (3324, 3326, 3424, 3426); and in response to the comparison value (3322, 3422) satisfying the comparison criterion (3324, 3326, 3424, 3426) with respect to the counter value, send a control signal (3532, 3534) to the gate of the first transistor (336, 2822) to generate a pulse edge of a pulse of a pulse-width modulated signal, wherein the comparison value (3322, 3422) and the comparison criteria (3324, 3326, 3424, 3426) are included in a set point signal (3312-3320, 3412-3420), and wherein the comparison criteria (3324, 3326, 3424, 3426) are adjustable and comprise a greater than condition, a greater than or equal to condition, a less than condition, or a less than or equal to condition and wherein the signal generator (334, 2842, 3522, 3524) is further configured to determine the comparison value (3322, 3422) based on a shift operation of the set point signal (3312-3320, 3412-3420) and to determine the comparison criterion (3324, 3326, 3424, 3426) based on one or more bits of the set point signal (3312-3320, 3412-3420). a first transistor (336, 2822) including a first terminal coupled to a power source and a second terminal coupled to a first input of a controlled component; and a signal generator (334, 2842, 3522, 3524) coupled to a gate of the first transistor (336, 2822), the signal generator (334, 2842, 3522, 3524) being configured to: receive a comparison value (3322, 3422) and two comparison criteria (3324, 3326, 3424, 3426); compare the comparison value (3322, 3422) to a counter value based on one of the comparison criteria (3324, 3326, 3424, 3426); and in response to the comparison value (3322, 3422) satisfying the comparison criterion (3324, 3326, 3424, 3426) with respect to the counter value, send a control signal (3532, 3534) to the gate of the first transistor (336, 2822) to generate a pulse edge of a pulse of a pulse-width modulated signal, receive a comparison value (3322, 3422) and two comparison criteria (3324, 3326, 3424, 3426); compare the comparison value (3322, 3422) to a counter value based on one of the comparison criteria (3324, 3326, 3424, 3426); and in response to the comparison value (3322, 3422) satisfying the comparison criterion (3324, 3326, 3424, 3426) with respect to the counter value, send a control signal (3532, 3534) to the gate of the first transistor (336, 2822) to generate a pulse edge of a pulse of a pulse-width modulated signal, wherein the comparison value (3322, 3422) and the comparison criteria (3324, 3326, 3424, 3426) are included in a set point signal (3312-3320, 3412-3420), and wherein the comparison criteria (3324, 3326, 3424, 3426) are adjustable and comprise a greater than condition, a greater than or equal to condition, a less than condition, or a less than or equal to condition and wherein the signal generator (334, 2842, 3522, 3524) is further configured to determine the comparison value (3322, 3422) based on a shift operation of the set point signal (3312-3320, 3412-3420) and to determine the comparison criterion (3324, 3326, 3424, 3426) based on one or more bits of the set point signal (3312-3320, 3412-3420).