A high-voltage integrated circuit device, comprising: a p-type semiconductor substrate; an n-type low-side circuit portion, disposed on the p-type semiconductor substrate and electrically connectable to a low-voltage power supply which takes a GND potential as reference; an n-type high-side circuit portion, disposed on the p-type semiconductor substrate at a distance from the n-type low-side circuit portion and electrically connectable to a low-voltage power supply which takes, as reference, an intermediate potential higher than the GND potential; a p-type region which is electrically connectable to the GND potential, is disposed surrounding the n-type high-side circuit portion, and forms a high-voltage junction terminating region together with an outer peripheral portion of the n-type high-side circuit portion; a first pickup electrode, disposed in the p-type region; a second pickup electrode, electrically connectable to a high-potential side of the low-voltage power supply taking the intermediate potential as reference, and disposed on an outer peripheral portion of the n-type high-side circuit portion; a first p-type high-concentration contact region that is in Ohmic contact with the first pickup electrode; and a second n-type high-concentration contact region that is in Ohmic contact with the second pickup electrode, characterized in that the first p-type high-concentration contact region is a universal contact region, in which a p + -type region and a plurality of n + -type regions are present such that the plurality of n + -type regions and subregions of the p + -type region are disposed in mutual alternating contact along a surface of the semiconductor substrate, wherein among the p + -type region and the plurality of n + -type regions forming the universal contact region, reach n + -type region of the plurality of n + -type regions is disposed in island form surrounded by the p + -type region so that all the periphery of each n + -type region is in contact with the p + -type region in planar direction. a p-type semiconductor substrate; an n-type low-side circuit portion, disposed on the p-type semiconductor substrate and electrically connectable to a low-voltage power supply which takes a GND potential as reference; an n-type high-side circuit portion, disposed on the p-type semiconductor substrate at a distance from the n-type low-side circuit portion and electrically connectable to a low-voltage power supply which takes, as reference, an intermediate potential higher than the GND potential; a p-type region which is electrically connectable to the GND potential, is disposed surrounding the n-type high-side circuit portion, and forms a high-voltage junction terminating region together with an outer peripheral portion of the n-type high-side circuit portion; a first pickup electrode, disposed in the p-type region; a second pickup electrode, electrically connectable to a high-potential side of the low-voltage power supply taking the intermediate potential as reference, and disposed on an outer peripheral portion of the n-type high-side circuit portion; a first p-type high-concentration contact region that is in Ohmic contact with the first pickup electrode; and a second n-type high-concentration contact region that is in Ohmic contact with the second pickup electrode, characterized in that the first p-type high-concentration contact region is a universal contact region, in which a p + -type region and a plurality of n + -type regions are present such that the plurality of n + -type regions and subregions of the p + -type region are disposed in mutual alternating contact along a surface of the semiconductor substrate, wherein among the p + -type region and the plurality of n + -type regions forming the universal contact region, reach n + -type region of the plurality of n + -type regions is disposed in island form surrounded by the p + -type region so that all the periphery of each n + -type region is in contact with the p + -type region in planar direction.