A memory cell comprising: a semiconductor substrate covered by an insulating layer; a fin disposed on the semiconductor substrate and protruding from the insulating layer; a memory gate structure including a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked, and being disposed on the insulating layer so as to extend over the fin; a first select gate structure including a first select gate electrode stacked on a first select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along a first sidewall spacer disposed on one sidewall of the memory gate structure; a second select gate structure including a second select gate electrode stacked on a second select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along a second sidewall spacer disposed on the other sidewall of the memory gate structure; a drain region provided adjacent to the first select gate structure on a surface of the fin, insulated from the first select gate electrode, and electrically connected with a bit line; and a source region provided adjacent to the second select gate structure on the surface of the fin, insulated from the second select gate electrode, and electrically connected with a source line, wherein the first select gate structure, the memory gate structure, and the second select gate structure are provided between the drain region and the source region, and in the insulating layer: a distance between the semiconductor substrate and a lower surface of the lower memory gate insulating film is longer than distances between the semiconductor substrate and lower surfaces of the first select gate insulating film and the second select gate insulating film; and positions of the lower surfaces of the first select gate electrode and the second select gate electrode with respect to the semiconductor substrate are closer than the lower surface of the memory gate electrode with respect to the semiconductor substrate. a semiconductor substrate covered by an insulating layer; a fin disposed on the semiconductor substrate and protruding from the insulating layer; a memory gate structure including a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked, and being disposed on the insulating layer so as to extend over the fin; a first select gate structure including a first select gate electrode stacked on a first select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along a first sidewall spacer disposed on one sidewall of the memory gate structure; a second select gate structure including a second select gate electrode stacked on a second select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along a second sidewall spacer disposed on the other sidewall of the memory gate structure; a drain region provided adjacent to the first select gate structure on a surface of the fin, insulated from the first select gate electrode, and electrically connected with a bit line; and a source region provided adjacent to the second select gate structure on the surface of the fin, insulated from the second select gate electrode, and electrically connected with a source line, wherein the first select gate structure, the memory gate structure, and the second select gate structure are provided between the drain region and the source region, and in the insulating layer: a distance between the semiconductor substrate and a lower surface of the lower memory gate insulating film is longer than distances between the semiconductor substrate and lower surfaces of the first select gate insulating film and the second select gate insulating film; and positions of the lower surfaces of the first select gate electrode and the second select gate electrode with respect to the semiconductor substrate are closer than the lower surface of the memory gate electrode with respect to the semiconductor substrate. a distance between the semiconductor substrate and a lower surface of the lower memory gate insulating film is longer than distances between the semiconductor substrate and lower surfaces of the first select gate insulating film and the second select gate insulating film; and positions of the lower surfaces of the first select gate electrode and the second select gate electrode with respect to the semiconductor substrate are closer than the lower surface of the memory gate electrode with respect to the semiconductor substrate.