A data transmitting circuit, comprising: a serializer circuit configured to serialize a high-speed parallel bit stream corresponding to a high-speed bitrate based on a high-speed reference frequency to generate a high-speed serial bit stream for transmission over a high-speed serial bus, wherein the high-speed parallel bit stream comprises a plurality of binary bit periods, each of the plurality of binary bit periods comprising a first number of parallel binary bits; and a data processing circuit configured to: receive a low-speed parallel bit stream corresponding to a low-speed bitrate slower than the high-speed bitrate, wherein the low-speed parallel bit stream is a pulse width modulated, PWM, parallel bitstream and comprises a plurality of PWM bit periods, each of the plurality of PWM bit periods comprising a second number of parallel PWM bits; wherein each PWM bit is configured to be digitally represented by a first number of binary zeros and a second number of binary ones; determine a bit multiplier value by dividing the high-speed bitrate by the low-speed bitrate; and for each of the second number of parallel PWM bits in each of the plurality of PWM bit periods: encode the PWM bit into a calculated number of binary bit periods among the plurality of binary bit periods in the high-speed parallel bit stream based on the bit multiplier value by converting the PWM bit into the first number of binary zeros and the second number of binary ones according to a predetermined ratio, wherein the calculated number of binary bit periods is determined by dividing the bit multiplier value by the first number of parallel binary bits; and output the calculated number of binary bit periods to the serializer circuit. a serializer circuit configured to serialize a high-speed parallel bit stream corresponding to a high-speed bitrate based on a high-speed reference frequency to generate a high-speed serial bit stream for transmission over a high-speed serial bus, wherein the high-speed parallel bit stream comprises a plurality of binary bit periods, each of the plurality of binary bit periods comprising a first number of parallel binary bits; and a data processing circuit configured to: receive a low-speed parallel bit stream corresponding to a low-speed bitrate slower than the high-speed bitrate, wherein the low-speed parallel bit stream is a pulse width modulated, PWM, parallel bitstream and comprises a plurality of PWM bit periods, each of the plurality of PWM bit periods comprising a second number of parallel PWM bits; wherein each PWM bit is configured to be digitally represented by a first number of binary zeros and a second number of binary ones; determine a bit multiplier value by dividing the high-speed bitrate by the low-speed bitrate; and for each of the second number of parallel PWM bits in each of the plurality of PWM bit periods: encode the PWM bit into a calculated number of binary bit periods among the plurality of binary bit periods in the high-speed parallel bit stream based on the bit multiplier value by converting the PWM bit into the first number of binary zeros and the second number of binary ones according to a predetermined ratio, wherein the calculated number of binary bit periods is determined by dividing the bit multiplier value by the first number of parallel binary bits; and output the calculated number of binary bit periods to the serializer circuit. receive a low-speed parallel bit stream corresponding to a low-speed bitrate slower than the high-speed bitrate, wherein the low-speed parallel bit stream is a pulse width modulated, PWM, parallel bitstream and comprises a plurality of PWM bit periods, each of the plurality of PWM bit periods comprising a second number of parallel PWM bits; wherein each PWM bit is configured to be digitally represented by a first number of binary zeros and a second number of binary ones; determine a bit multiplier value by dividing the high-speed bitrate by the low-speed bitrate; and for each of the second number of parallel PWM bits in each of the plurality of PWM bit periods: encode the PWM bit into a calculated number of binary bit periods among the plurality of binary bit periods in the high-speed parallel bit stream based on the bit multiplier value by converting the PWM bit into the first number of binary zeros and the second number of binary ones according to a predetermined ratio, wherein the calculated number of binary bit periods is determined by dividing the bit multiplier value by the first number of parallel binary bits; and output the calculated number of binary bit periods to the serializer circuit. encode the PWM bit into a calculated number of binary bit periods among the plurality of binary bit periods in the high-speed parallel bit stream based on the bit multiplier value by converting the PWM bit into the first number of binary zeros and the second number of binary ones according to a predetermined ratio, wherein the calculated number of binary bit periods is determined by dividing the bit multiplier value by the first number of parallel binary bits; and output the calculated number of binary bit periods to the serializer circuit.