A digital receiver (10, 10A, 10B) for recovering data from a FEC-encoded signal having a stream of N bits mapped into M transmitted symbols, comprising: a one-dimensional hard demapper for generating a set of K demapped bits for each arriving symbol, where K=ceil(N/M); and a FEC decoder (12, 12A, 12B) for producing a stream of decoded data bits from the output of the one-dimensional hard demapper, the FEC decoder including: an apparatus responsive to a set of M*K demapped bits and configured to convert the set of M*K demapped bits into a plurality of N log-likelihood ratios, abbreviated LLRs associated with the stream of N bits in a one-to-one relationship, the apparatus comprising: at least one processor, and at least one memory including computer program code, wherein the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to generate the plurality of N LLRs, each LLR defined by a magnitude and a sign, the magnitude selected from a plurality of predefined, different LLR magnitudes; and a decoding engine responsive to the LLRs generated by the apparatus and producing therefrom an output stream of decoded data bits. a one-dimensional hard demapper for generating a set of K demapped bits for each arriving symbol, where K=ceil(N/M); and a FEC decoder (12, 12A, 12B) for producing a stream of decoded data bits from the output of the one-dimensional hard demapper, the FEC decoder including: an apparatus responsive to a set of M*K demapped bits and configured to convert the set of M*K demapped bits into a plurality of N log-likelihood ratios, abbreviated LLRs associated with the stream of N bits in a one-to-one relationship, the apparatus comprising: at least one processor, and at least one memory including computer program code, wherein the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to generate the plurality of N LLRs, each LLR defined by a magnitude and a sign, the magnitude selected from a plurality of predefined, different LLR magnitudes; and a decoding engine responsive to the LLRs generated by the apparatus and producing therefrom an output stream of decoded data bits. an apparatus responsive to a set of M*K demapped bits and configured to convert the set of M*K demapped bits into a plurality of N log-likelihood ratios, abbreviated LLRs associated with the stream of N bits in a one-to-one relationship, the apparatus comprising: at least one processor, and at least one memory including computer program code, wherein the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to generate the plurality of N LLRs, each LLR defined by a magnitude and a sign, the magnitude selected from a plurality of predefined, different LLR magnitudes; and at least one processor, and at least one memory including computer program code, wherein the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to generate the plurality of N LLRs, each LLR defined by a magnitude and a sign, the magnitude selected from a plurality of predefined, different LLR magnitudes; and a decoding engine responsive to the LLRs generated by the apparatus and producing therefrom an output stream of decoded data bits.