A multilevel converter comprising: a plurality of phase legs each having at least two inner switching devices (44, 46), at least two outer switching devices (42, 48), at least two clamping diodes (50, 52) and a split DC link; and a switching device failure detection circuit characterized by: a logic module for each of the switching devices which is configured to generate a blocking state logic signal (Vcl, Vc2, Vc3, Vc4) to compare a switching device voltage (Vswl, Vsw2, Vsw3, Vsw4) and a threshold reference voltage (Vth), said logic modules comprising a respective comparator (72,74,76,78) to determine whether a respective switching device (42,44,46,48) is actually blocking or not; a voltage calculation module configured to determine an expected voltage blocking state (Vsl, Vs2, Vs3, Vs4) for each of the switching devices based on the gate drive signals (G1, G2, G3, G4) of the switching devices and an output current (Io) direction; a failure detection algorithm operable to detect a failure condition in any of the switching devices (42,44,46,48) based on the blocking state logic signals (Vcl, Vc2, Vc3, Vc4) and the expected voltage blocking states (Vsl, Vs2, Vs3, Vs4) of the switching devices (42,44,46,48), said failure condition being either a short circuit or an open circuit failure. a plurality of phase legs each having at least two inner switching devices (44, 46), at least two outer switching devices (42, 48), at least two clamping diodes (50, 52) and a split DC link; and a switching device failure detection circuit characterized by: a logic module for each of the switching devices which is configured to generate a blocking state logic signal (Vcl, Vc2, Vc3, Vc4) to compare a switching device voltage (Vswl, Vsw2, Vsw3, Vsw4) and a threshold reference voltage (Vth), said logic modules comprising a respective comparator (72,74,76,78) to determine whether a respective switching device (42,44,46,48) is actually blocking or not; a voltage calculation module configured to determine an expected voltage blocking state (Vsl, Vs2, Vs3, Vs4) for each of the switching devices based on the gate drive signals (G1, G2, G3, G4) of the switching devices and an output current (Io) direction; a failure detection algorithm operable to detect a failure condition in any of the switching devices (42,44,46,48) based on the blocking state logic signals (Vcl, Vc2, Vc3, Vc4) and the expected voltage blocking states (Vsl, Vs2, Vs3, Vs4) of the switching devices (42,44,46,48), said failure condition being either a short circuit or an open circuit failure. a logic module for each of the switching devices which is configured to generate a blocking state logic signal (Vcl, Vc2, Vc3, Vc4) to compare a switching device voltage (Vswl, Vsw2, Vsw3, Vsw4) and a threshold reference voltage (Vth), said logic modules comprising a respective comparator (72,74,76,78) to determine whether a respective switching device (42,44,46,48) is actually blocking or not; a voltage calculation module configured to determine an expected voltage blocking state (Vsl, Vs2, Vs3, Vs4) for each of the switching devices based on the gate drive signals (G1, G2, G3, G4) of the switching devices and an output current (Io) direction; a failure detection algorithm operable to detect a failure condition in any of the switching devices (42,44,46,48) based on the blocking state logic signals (Vcl, Vc2, Vc3, Vc4) and the expected voltage blocking states (Vsl, Vs2, Vs3, Vs4) of the switching devices (42,44,46,48), said failure condition being either a short circuit or an open circuit failure.