A sensor circuit comprising: a first subcircuit comprising: a first sense capacitor; a first integration capacitor, and a first clock input for receiving a first digital clock signal, the first subcircuit being configured to initiate discharge of the first integration capacitor at time T, wherein a rate of discharge of the first integration capacitor is at least partly determined by a capacitance of the first sense capacitor; a second subcircuit comprising: a second sense capacitor; a second integration capacitor, and a second clock input (CLKD) for receiving a second digital clock signal, the second subcircuit being configured to initiate discharge of the second integration capacitor at time T+T d, wherein a rate of discharge of the second integration capacitor is at least partly determined by a capacitance of the second sense capacitor, wherein the circuit is configured: at time T eval, after initiation of discharge of the first and second integration capacitors, to compare the extent to which the first and second integration capacitors have discharged, thereby to compare the capacitance of the first sense capacitor to the capacitance of the second sense capacitor; and to output a digital signal indicating the result of the comparison, wherein the sensor circuit further comprises a delay generator for varying T d in a plurality of measurements for comparing the capacitance of the first sense capacitor to the capacitance of the second sense capacitor. a first subcircuit comprising: a first sense capacitor; a first integration capacitor, and a first clock input for receiving a first digital clock signal, the first subcircuit being configured to initiate discharge of the first integration capacitor at time T, wherein a rate of discharge of the first integration capacitor is at least partly determined by a capacitance of the first sense capacitor; a first sense capacitor; a first integration capacitor, and a first clock input for receiving a first digital clock signal, the first subcircuit being configured to initiate discharge of the first integration capacitor at time T, wherein a rate of discharge of the first integration capacitor is at least partly determined by a capacitance of the first sense capacitor; a second subcircuit comprising: a second sense capacitor; a second integration capacitor, and a second clock input (CLKD) for receiving a second digital clock signal, the second subcircuit being configured to initiate discharge of the second integration capacitor at time T+T d, a second sense capacitor; a second integration capacitor, and a second clock input (CLKD) for receiving a second digital clock signal, the second subcircuit being configured to initiate discharge of the second integration capacitor at time T+T d, wherein a rate of discharge of the second integration capacitor is at least partly determined by a capacitance of the second sense capacitor, at time T eval, after initiation of discharge of the first and second integration capacitors, to compare the extent to which the first and second integration capacitors have discharged, thereby to compare the capacitance of the first sense capacitor to the capacitance of the second sense capacitor; and to output a digital signal indicating the result of the comparison, wherein the sensor circuit further comprises a delay generator for varying T d in a plurality of measurements for comparing the capacitance of the first sense capacitor to the capacitance of the second sense capacitor.