A complementary field effect transistor, CFET, structure, comprising: a lower source contact and a lower drain contact in an intermetal dielectric, IMD, layer; a lower gate-all-around, GAA, gate region in the IMD layer between the lower source and drain contacts (132, 134), the lower GAA gate region being a first conductivity type and comprising one or more lower channel structures, each lower channel structure comprising: a lower transition metal dichalcogenide, TMD, channel electrically coupled with the lower source contact and with the lower drain contact; and first and second lower gate oxide layers respectively on lower and upper surfaces of the lower TMD channel; an upper source contact and an upper drain contact in the IMD layer above the lower source and drain contacts (132, 134); an upper GAA gate region in the IMD layer above the lower GAA gate region and between the upper source and drain contacts (142, 144), the upper GAA gate region being a second conductivity type opposite the first conductivity type and comprising one or more upper channel structures, each upper channel structure comprising: an upper TMD channel electrically coupled with the upper source contact and with the upper drain contact (142, 144); and first and second upper gate oxide layers respectively on lower and upper surfaces of the upper TMD channel; and a common gate in the IMD layer between the lower source and drain contacts (132, 234) and between the upper source and drain contacts (142, 144), the common gate being configured to apply a common voltage to the lower and upper channel structures (240, 250). a lower source contact and a lower drain contact in an intermetal dielectric, IMD, layer; a lower gate-all-around, GAA, gate region in the IMD layer between the lower source and drain contacts (132, 134), the lower GAA gate region being a first conductivity type and comprising one or more lower channel structures, each lower channel structure comprising: a lower transition metal dichalcogenide, TMD, channel electrically coupled with the lower source contact and with the lower drain contact; and first and second lower gate oxide layers respectively on lower and upper surfaces of the lower TMD channel; a lower transition metal dichalcogenide, TMD, channel electrically coupled with the lower source contact and with the lower drain contact; and first and second lower gate oxide layers respectively on lower and upper surfaces of the lower TMD channel; an upper source contact and an upper drain contact in the IMD layer above the lower source and drain contacts (132, 134); an upper GAA gate region in the IMD layer above the lower GAA gate region and between the upper source and drain contacts (142, 144), the upper GAA gate region being a second conductivity type opposite the first conductivity type and comprising one or more upper channel structures, each upper channel structure comprising: an upper TMD channel electrically coupled with the upper source contact and with the upper drain contact (142, 144); and first and second upper gate oxide layers respectively on lower and upper surfaces of the upper TMD channel; and an upper TMD channel electrically coupled with the upper source contact and with the upper drain contact (142, 144); and first and second upper gate oxide layers respectively on lower and upper surfaces of the upper TMD channel; and a common gate in the IMD layer between the lower source and drain contacts (132, 234) and between the upper source and drain contacts (142, 144), the common gate being configured to apply a common voltage to the lower and upper channel structures (240, 250).