An apparatus comprising: a differential cascode amplifier (302, 412) comprising a first cascode transistor (304, 422) and a second cascode transistor (306, 424); a transistor (320, 420) including: a source terminal coupled to a gate terminal (312, 436) of the first cascode transistor of the differential cascode amplifier; and a drain terminal coupled to a gate terminal (314, 438) of the second cascode transistor of the differential cascode amplifier; a first high impedance element (322, 414) coupled to the gate terminal of the first cascode transistor and to the source terminal of the transistor; and a second high impedance element (324, 416) coupled to the gate terminal of the second cascode transistor and to the drain terminal; wherein the transistor is configured to be activated in a first mode to selectively couple the source terminal to the gate terminal of the first cascode transistor of the differential cascode amplifier and to selectively couple the drain terminal to the gate terminal of the second cascode transistor of the differential cascode amplifier; and the transistor is configured to be deactivated in a second mode so that the gate terminal of the first cascode transistor of the differential cascode amplifier is coupled to the gate terminal of the second cascode transistor of the differential cascode amplifier via the first high impedance element and the second high impedance element, wherein the first high impedance element and the second high impedance element include resistors, inductors, or a combination thereof, and are coupled together to a common control node, so that the drain-to-gate voltages of the first and second cascode transistors are reduced during the second mode. a differential cascode amplifier (302, 412) comprising a first cascode transistor (304, 422) and a second cascode transistor (306, 424); a transistor (320, 420) including: a source terminal coupled to a gate terminal (312, 436) of the first cascode transistor of the differential cascode amplifier; and a drain terminal coupled to a gate terminal (314, 438) of the second cascode transistor of the differential cascode amplifier; a source terminal coupled to a gate terminal (312, 436) of the first cascode transistor of the differential cascode amplifier; and a drain terminal coupled to a gate terminal (314, 438) of the second cascode transistor of the differential cascode amplifier; a first high impedance element (322, 414) coupled to the gate terminal of the first cascode transistor and to the source terminal of the transistor; and a second high impedance element (324, 416) coupled to the gate terminal of the second cascode transistor and to the drain terminal; wherein the transistor is configured to be activated in a first mode to selectively couple the source terminal to the gate terminal of the first cascode transistor of the differential cascode amplifier and to selectively couple the drain terminal to the gate terminal of the second cascode transistor of the differential cascode amplifier; and the transistor is configured to be deactivated in a second mode so that the gate terminal of the first cascode transistor of the differential cascode amplifier is coupled to the gate terminal of the second cascode transistor of the differential cascode amplifier via the first high impedance element and the second high impedance element, wherein the first high impedance element and the second high impedance element include resistors, inductors, or a combination thereof, and are coupled together to a common control node, so that the drain-to-gate voltages of the first and second cascode transistors are reduced during the second mode.