A data processing apparatus comprising: at least one memory (7, 8, 9, 10) configured to store data; processing circuitry configured to issue memory transactions for accessing data in the at least one memory; a memory built-in self-test (MBIST) interface configured to receive a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location of the at least one memory; control circuitry (17, 18, 19) configured to detect the MBIST request received by the MBIST interface, and in response to detecting the MBIST request, to reserve for testing at least one reserved memory location including said at least one target memory location; wherein during the test procedure, the at least one memory is configured to continue servicing memory transactions issued by the processing circuitry which target a memory location other than the at least one reserved memory location reserved by the control circuitry; wherein the control circuitry is configured to prevent servicing of memory transactions from the processing circuitry which target one of said at least one reserved memory location; characterised by: the test procedure being an in-field MBIST procedure; the apparatus comprising an MBIST controller configured to control testing of a given range of memory locations by issuing a plurality of separate MBIST requests to the MBIST interface, each MBIST request corresponding to a burst of test transactions for testing a different subset of memory locations within said given range of memory locations; and wherein in response to each of said separate MBIST requests, the control circuitry is configured to issue an MBIST acknowledgement signal over the MBIST interface to trigger the MBIST controller to start the test procedure for the corresponding subset of memory locations. at least one memory (7, 8, 9, 10) configured to store data; processing circuitry configured to issue memory transactions for accessing data in the at least one memory; a memory built-in self-test (MBIST) interface configured to receive a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location of the at least one memory; control circuitry (17, 18, 19) configured to detect the MBIST request received by the MBIST interface, and in response to detecting the MBIST request, to reserve for testing at least one reserved memory location including said at least one target memory location; wherein during the test procedure, the at least one memory is configured to continue servicing memory transactions issued by the processing circuitry which target a memory location other than the at least one reserved memory location reserved by the control circuitry; wherein the control circuitry is configured to prevent servicing of memory transactions from the processing circuitry which target one of said at least one reserved memory location; characterised by: the test procedure being an in-field MBIST procedure; the apparatus comprising an MBIST controller configured to control testing of a given range of memory locations by issuing a plurality of separate MBIST requests to the MBIST interface, each MBIST request corresponding to a burst of test transactions for testing a different subset of memory locations within said given range of memory locations; and wherein in response to each of said separate MBIST requests, the control circuitry is configured to issue an MBIST acknowledgement signal over the MBIST interface to trigger the MBIST controller to start the test procedure for the corresponding subset of memory locations.