An integrated circuit for voltage regulation, comprising: (a) a first differential opamp configured to receive a reference voltage and a feedback voltage and generate an amplified signal; (b) a second circuit comprising: a first P-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor having corresponding source terminals coupled to a supply bus, and corresponding gate terminals commonly coupled to a first connection node; a first N-type metal-oxide-semiconductor (NMOS) transistor having a first gate terminal, a first source terminal and a first drain terminal, wherein the first gate terminal is coupled to receive the feedback voltage, the first drain terminal is coupled to a drain node of the first PMOS transistor, and the first source terminal is coupled to a tail current node; a second NMOS transistor having a second gate terminal, a second source terminal and a second drain terminal, wherein the second gate terminal is coupled to receive the reference voltage, the second drain terminal is coupled to a drain node of the second PMOS transistor; and the second source terminal is coupled to the tail current node; a first resistor coupled between the first connection node and the first drain node; a second resistor coupled between the first connection node and the second drain node; and, a current source transistor having a third drain terminal coupled to the tail current node and a third gate terminal configured to receive the amplified signal; (c) a driver transistor configured to provide an output voltage at an output voltage node and to receive a gating voltage output from the first connection node; and, (d) a first capacitor connected between the first connection node and the tail current node. (a) a first differential opamp configured to receive a reference voltage and a feedback voltage and generate an amplified signal; (b) a second circuit comprising: a first P-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor having corresponding source terminals coupled to a supply bus, and corresponding gate terminals commonly coupled to a first connection node; a first N-type metal-oxide-semiconductor (NMOS) transistor having a first gate terminal, a first source terminal and a first drain terminal, wherein the first gate terminal is coupled to receive the feedback voltage, the first drain terminal is coupled to a drain node of the first PMOS transistor, and the first source terminal is coupled to a tail current node; a second NMOS transistor having a second gate terminal, a second source terminal and a second drain terminal, wherein the second gate terminal is coupled to receive the reference voltage, the second drain terminal is coupled to a drain node of the second PMOS transistor; and the second source terminal is coupled to the tail current node; a first resistor coupled between the first connection node and the first drain node; a second resistor coupled between the first connection node and the second drain node; and, a current source transistor having a third drain terminal coupled to the tail current node and a third gate terminal configured to receive the amplified signal; a first P-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor having corresponding source terminals coupled to a supply bus, and corresponding gate terminals commonly coupled to a first connection node; a first N-type metal-oxide-semiconductor (NMOS) transistor having a first gate terminal, a first source terminal and a first drain terminal, wherein the first gate terminal is coupled to receive the feedback voltage, the first drain terminal is coupled to a drain node of the first PMOS transistor, and the first source terminal is coupled to a tail current node; a second NMOS transistor having a second gate terminal, a second source terminal and a second drain terminal, wherein the second gate terminal is coupled to receive the reference voltage, the second drain terminal is coupled to a drain node of the second PMOS transistor; and the second source terminal is coupled to the tail current node; a first resistor coupled between the first connection node and the first drain node; a second resistor coupled between the first connection node and the second drain node; and, a current source transistor having a third drain terminal coupled to the tail current node and a third gate terminal configured to receive the amplified signal; (c) a driver transistor configured to provide an output voltage at an output voltage node and to receive a gating voltage output from the first connection node; and, (d) a first capacitor connected between the first connection node and the tail current node.