An in-memory computation circuit, comprising: a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column; a word line drive circuit for each row having an output connected to drive the word line of the row; a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation; a column processing circuit connected to the at least one bit lines for each column and configured to process analog voltages developed on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory compute operation; a voltage generator circuit (112, 212) configured to generate, during the simultaneous actuation of the plurality of word lines for the in-memory compute operation, a first voltage having a level which is dependent on integrated circuit process and/or temperature conditions, said voltage generator circuit comprising: a current source configured to generate a current applied to a first node; and a replica circuit comprising a series connection of a first and second transistor between the first node and a reference node; wherein said first voltage is generated at said first node; wherein the first transistor is a replica of a passgate transistor within the SRAM cells; wherein the second transistor is a replica of a pull down transistor within the SRAM cells; and an amplifier circuit having an input coupled to said first node and an output coupled to power the word line drive circuits, wherein the current generated by the current source has a magnitude set as a function of a reference current representative of current flowing through the passgate transistor and the pull down transistor for an applicable integrated circuit process corner. a memory array including a plurality of static random access memory (SRAM) cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the SRAM cells of the row, and each column including at least one bit line connected to the SRAM cells of the column; a word line drive circuit for each row having an output connected to drive the word line of the row; a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation; a column processing circuit connected to the at least one bit lines for each column and configured to process analog voltages developed on the bit lines in response to the simultaneous actuation of the plurality of word lines to generate a decision output for the in-memory compute operation; a voltage generator circuit (112, 212) configured to generate, during the simultaneous actuation of the plurality of word lines for the in-memory compute operation, a first voltage having a level which is dependent on integrated circuit process and/or temperature conditions, said voltage generator circuit comprising: a current source configured to generate a current applied to a first node; and a replica circuit comprising a series connection of a first and second transistor between the first node and a reference node; wherein said first voltage is generated at said first node; wherein the first transistor is a replica of a passgate transistor within the SRAM cells; wherein the second transistor is a replica of a pull down transistor within the SRAM cells; and an amplifier circuit having an input coupled to said first node and an output coupled to power the word line drive circuits, wherein the current generated by the current source has a magnitude set as a function of a reference current representative of current flowing through the passgate transistor and the pull down transistor for an applicable integrated circuit process corner. a current source configured to generate a current applied to a first node; and a replica circuit comprising a series connection of a first and second transistor between the first node and a reference node; wherein said first voltage is generated at said first node; wherein the first transistor is a replica of a passgate transistor within the SRAM cells; wherein the second transistor is a replica of a pull down transistor within the SRAM cells; and an amplifier circuit having an input coupled to said first node and an output coupled to power the word line drive circuits, wherein the current generated by the current source has a magnitude set as a function of a reference current representative of current flowing through the passgate transistor and the pull down transistor for an applicable integrated circuit process corner.