A monolithic three-dimensional semiconductor memory device, said memory device comprising: a plurality of horizontally separated pillar structures disposed above a silicon substrate wherein each of said pillar structures includes two or more memory cells vertically disposed relative to the silicon substrate and vertically separated from each other, to thereby form a plurality of vertically separated levels of memory cells, each of said memory cells comprising: a vertical semiconductor film stack comprising three regions (1312, 1314, 1316) located between a first input/output conductor and a second input/output conductor; a charge storage medium comprising one or more layers, wherein said charge storage medium is laterally disposed relative to the vertical semiconductor film stack and comprises a charge trapping layer in a dielectric stack; and a control gate laterally disposed relative to the charge storage medium; the memory device further comprising: driver circuitry associated with operation of each of the levels of memory cells; wherein: said pillar structures are arranged in two or more horizontally separated rows, each of said horizontally separated rows having two or more said pillar structures; the control gate of the memory cells in a first level of memory cells formed by the horizontally separated pillar structures is common among all the memory cells in the first level of memory cells, and fills the gaps between the memory cells in the first level of memory cells formed by the horizontally separated pillar structures and is recessed below the top surface of the memory cells in the first level of memory cells; and the memory cells in the pillar structures are vertically separated from each other by the second input/output conductor. a plurality of horizontally separated pillar structures disposed above a silicon substrate wherein each of said pillar structures includes two or more memory cells vertically disposed relative to the silicon substrate and vertically separated from each other, to thereby form a plurality of vertically separated levels of memory cells, each of said memory cells comprising: a vertical semiconductor film stack comprising three regions (1312, 1314, 1316) located between a first input/output conductor and a second input/output conductor; a charge storage medium comprising one or more layers, wherein said charge storage medium is laterally disposed relative to the vertical semiconductor film stack and comprises a charge trapping layer in a dielectric stack; and a control gate laterally disposed relative to the charge storage medium; the memory device further comprising: driver circuitry associated with operation of each of the levels of memory cells; wherein: said pillar structures are arranged in two or more horizontally separated rows, each of said horizontally separated rows having two or more said pillar structures; the control gate of the memory cells in a first level of memory cells formed by the horizontally separated pillar structures is common among all the memory cells in the first level of memory cells, and fills the gaps between the memory cells in the first level of memory cells formed by the horizontally separated pillar structures and is recessed below the top surface of the memory cells in the first level of memory cells; and the memory cells in the pillar structures are vertically separated from each other by the second input/output conductor. driver circuitry associated with operation of each of the levels of memory cells; wherein: said pillar structures are arranged in two or more horizontally separated rows, each of said horizontally separated rows having two or more said pillar structures; the control gate of the memory cells in a first level of memory cells formed by the horizontally separated pillar structures is common among all the memory cells in the first level of memory cells, and fills the gaps between the memory cells in the first level of memory cells formed by the horizontally separated pillar structures and is recessed below the top surface of the memory cells in the first level of memory cells; and the memory cells in the pillar structures are vertically separated from each other by the second input/output conductor. said pillar structures are arranged in two or more horizontally separated rows, each of said horizontally separated rows having two or more said pillar structures; the control gate of the memory cells in a first level of memory cells formed by the horizontally separated pillar structures is common among all the memory cells in the first level of memory cells, and fills the gaps between the memory cells in the first level of memory cells formed by the horizontally separated pillar structures and is recessed below the top surface of the memory cells in the first level of memory cells; and the memory cells in the pillar structures are vertically separated from each other by the second input/output conductor.