A radio frequency to digital receiver comprising: a modulator sampling a signal at a first rate; a plurality of processing units comprising: a plurality of digital bandpass filters separating the sampled signal and recombining the separated signal at a rate less than the first rate; and a digital down converter adjusting frequency offset or centering the recombined signal at the rate less than the first rate; and at least one rate control buffer coupled between adjacent processing units of the plurality of processing units wherein the radio frequency to digital receiver is arranged to: bypass a digital down converter in a processing unit by adjusting the first rate as a multiple of a processing rate of a current processing unit of the plurality of processing units and a carrier frequency as a multiple of the processing rate of the current processing unit when the current processing unit is coupled to the modulator otherwise, adjusting a processing rate of a previous processing unit of the plurality of processing units as a multiple of the processing rate of the current processing unit and adjusting an intermediate frequency as a multiple of the processing rate of the current processing unit. a modulator sampling a signal at a first rate; a plurality of processing units comprising: a plurality of digital bandpass filters separating the sampled signal and recombining the separated signal at a rate less than the first rate; and a digital down converter adjusting frequency offset or centering the recombined signal at the rate less than the first rate; and a plurality of digital bandpass filters separating the sampled signal and recombining the separated signal at a rate less than the first rate; and a digital down converter adjusting frequency offset or centering the recombined signal at the rate less than the first rate; and at least one rate control buffer coupled between adjacent processing units of the plurality of processing units wherein the radio frequency to digital receiver is arranged to: bypass a digital down converter in a processing unit by adjusting the first rate as a multiple of a processing rate of a current processing unit of the plurality of processing units and a carrier frequency as a multiple of the processing rate of the current processing unit when the current processing unit is coupled to the modulator otherwise, adjusting a processing rate of a previous processing unit of the plurality of processing units as a multiple of the processing rate of the current processing unit and adjusting an intermediate frequency as a multiple of the processing rate of the current processing unit. bypass a digital down converter in a processing unit by adjusting the first rate as a multiple of a processing rate of a current processing unit of the plurality of processing units and a carrier frequency as a multiple of the processing rate of the current processing unit when the current processing unit is coupled to the modulator otherwise, adjusting a processing rate of a previous processing unit of the plurality of processing units as a multiple of the processing rate of the current processing unit and adjusting an intermediate frequency as a multiple of the processing rate of the current processing unit.