A storage device comprising: a nonvolatile memory device including a memory cell array that includes a plurality of word-lines (WLs) stacked on a substrate, wherein a plurality of memory cells that are provided in a plurality of channel holes extend in a vertical direction with respect to the substrate, and word-line cut regions extend in a first horizontal direction and divide the plurality of word-lines (WLs) into a plurality of memory blocks (BLK1~BLKz); and a storage controller configured to control the nonvolatile memory device, wherein the storage controller includes an error correction code, ECC, engine (500; 500a) and a memory interface, wherein the ECC engine (500; 500a) includes an ECC encoder (520; 520a), the ECC encoder (520; 520a), in a write operation on target memory cells in a target page (PAG_T) coupled to a target word-line from among the plurality of word-lines (WLs), is configured to: perform a first ECC encoding operation on each of a plurality of sub data units (SDUi) in user data to generate parity bits (PRTi) associated with each of the plurality of sub data units (SDUi) and to generate a plurality of ECC sectors (ECCSi) based on the plurality of sub data units (SDUi) and the parity bits (PRTi), select, from among the plurality of ECC sectors (ECCSi), outer cell bits to be stored in outer cells from among the target memory cells, to constitute an outer ECC sector (OECCS) that includes the outer cell bits, the selection being based on an error correction mode signal, and perform a second ECC encoding operation on the outer ECC sector (OECCS) to generate outer parity bits (OPRT); wherein the memory interface is configured to transmit, to the nonvolatile memory device, a codeword set including the plurality of ECC sectors (ECCSi) and the outer parity bits (OPRT); and wherein the storage controller is configured to group the target memory cells coupled to the target word-line into the outer cells and into inner cells based on a location index (LIDX) of each of the target memory cells, a distance (Do) between each outer cell and a word-line cut region being less than a distance (Di) between each inner cell and the word-line cut region. a nonvolatile memory device including a memory cell array that includes a plurality of word-lines (WLs) stacked on a substrate, wherein a plurality of memory cells that are provided in a plurality of channel holes extend in a vertical direction with respect to the substrate, and word-line cut regions extend in a first horizontal direction and divide the plurality of word-lines (WLs) into a plurality of memory blocks (BLK1~BLKz); and a storage controller configured to control the nonvolatile memory device, wherein the storage controller includes an error correction code, ECC, engine (500; 500a) and a memory interface, wherein the ECC engine (500; 500a) includes an ECC encoder (520; 520a), the ECC encoder (520; 520a), in a write operation on target memory cells in a target page (PAG_T) coupled to a target word-line from among the plurality of word-lines (WLs), is configured to: perform a first ECC encoding operation on each of a plurality of sub data units (SDUi) in user data to generate parity bits (PRTi) associated with each of the plurality of sub data units (SDUi) and to generate a plurality of ECC sectors (ECCSi) based on the plurality of sub data units (SDUi) and the parity bits (PRTi), select, from among the plurality of ECC sectors (ECCSi), outer cell bits to be stored in outer cells from among the target memory cells, to constitute an outer ECC sector (OECCS) that includes the outer cell bits, the selection being based on an error correction mode signal, and perform a second ECC encoding operation on the outer ECC sector (OECCS) to generate outer parity bits (OPRT); perform a first ECC encoding operation on each of a plurality of sub data units (SDUi) in user data to generate parity bits (PRTi) associated with each of the plurality of sub data units (SDUi) and to generate a plurality of ECC sectors (ECCSi) based on the plurality of sub data units (SDUi) and the parity bits (PRTi), select, from among the plurality of ECC sectors (ECCSi), outer cell bits to be stored in outer cells from among the target memory cells, to constitute an outer ECC sector (OECCS) that includes the outer cell bits, the selection being based on an error correction mode signal, and perform a second ECC encoding operation on the outer ECC sector (OECCS) to generate outer parity bits (OPRT); wherein the memory interface is configured to transmit, to the nonvolatile memory device, a codeword set including the plurality of ECC sectors (ECCSi) and the outer parity bits (OPRT); and wherein the storage controller is configured to group the target memory cells coupled to the target word-line into the outer cells and into inner cells based on a location index (LIDX) of each of the target memory cells, a distance (Do) between each outer cell and a word-line cut region being less than a distance (Di) between each inner cell and the word-line cut region.