A successive approximation analog-to-digital converter, comprising: an input for receiving an input analog voltage; a first capacitor including a first plate and a second plate, the first plate coupled to the output of an input switch and the second plate coupled to a first switch; and the first switch; a comparator including: a third switch that includes: an input coupled to receive a bias voltage (Vbias); and an output coupled to a latch of the comparator; a third capacitor including a first plate and a second plate, the first plate coupled to an output of an amplifier and the second plate coupled to the third switch; wherein the latch is coupled to the third capacitor; and the amplifier that includes: a transconductor coupled to the first capacitor; a buffer coupled to the transconductor; a second capacitor; and a second switch including a first and a second terminal, the first terminal being coupled to the buffer and to the transconductor and the second terminal being coupled to the second capacitor; sample phase circuitry comprising the amplifier and for providing the bias voltage (Vbias) to the second plate of the first capacitor through the first switch and to the second plate of the third capacitor through the third switch in a sample phase and for providing the amplifier with a first set of electrical attributes and for sampling the input analog voltage in the sample phase, the amplifier configured to close the second switch to connect the second capacitor to the transconductor in the sample phase; and conversion phase circuitry comprising the amplifier, and for providing the amplifier with a second set of electrical attributes differing from the first set of electrical attributes and for converting a comparison, of the sampling of the input analog voltage relative to a reference voltage (Varef), to a digital value (CODE) in a conversion phase, the amplifier configured to open the second switch to disconnect the second capacitor from the transconductor in the conversion phase. an input for receiving an input analog voltage; a first capacitor including a first plate and a second plate, the first plate coupled to the output of an input switch and the second plate coupled to a first switch; and the first switch; a comparator including: a third switch that includes: an input coupled to receive a bias voltage (Vbias); and an output coupled to a latch of the comparator; a third capacitor including a first plate and a second plate, the first plate coupled to an output of an amplifier and the second plate coupled to the third switch; wherein the latch is coupled to the third capacitor; and the amplifier that includes: a transconductor coupled to the first capacitor; a buffer coupled to the transconductor; a second capacitor; and a second switch including a first and a second terminal, the first terminal being coupled to the buffer and to the transconductor and the second terminal being coupled to the second capacitor; a third switch that includes: an input coupled to receive a bias voltage (Vbias); and an output coupled to a latch of the comparator; an input coupled to receive a bias voltage (Vbias); and an output coupled to a latch of the comparator; a third capacitor including a first plate and a second plate, the first plate coupled to an output of an amplifier and the second plate coupled to the third switch; wherein the latch is coupled to the third capacitor; and the amplifier that includes: a transconductor coupled to the first capacitor; a buffer coupled to the transconductor; a second capacitor; and a second switch including a first and a second terminal, the first terminal being coupled to the buffer and to the transconductor and the second terminal being coupled to the second capacitor; a transconductor coupled to the first capacitor; a buffer coupled to the transconductor; a second capacitor; and a second switch including a first and a second terminal, the first terminal being coupled to the buffer and to the transconductor and the second terminal being coupled to the second capacitor; sample phase circuitry comprising the amplifier and for providing the bias voltage (Vbias) to the second plate of the first capacitor through the first switch and to the second plate of the third capacitor through the third switch in a sample phase and for providing the amplifier with a first set of electrical attributes and for sampling the input analog voltage in the sample phase, the amplifier configured to close the second switch to connect the second capacitor to the transconductor in the sample phase; and conversion phase circuitry comprising the amplifier, and for providing the amplifier with a second set of electrical attributes differing from the first set of electrical attributes and for converting a comparison, of the sampling of the input analog voltage relative to a reference voltage (Varef), to a digital value (CODE) in a conversion phase, the amplifier configured to open the second switch to disconnect the second capacitor from the transconductor in the conversion phase.