A bit generation apparatus comprising: a glitch generation section that generates a glitch signal including a plurality of pulses; a filter section configured to include series-connected N semiconductor devices, N being an integer of two or more, a first semiconductor device to an N-th semiconductor device, the filter section inputting via the first semiconductor device the glitch signal generated by the glitch generation section, removing a pulse whose width is less than a predetermined pulse width, by allowing the inputted glitch signal to pass through the first semiconductor device to the N-th semiconductor device, and outputting via the N-th semiconductor device the glitch signal from which the pulse whose width is less than the predetermined pulse width has been removed; and a bit value generation section that inputs the glitch signal outputted by the filter section, and generates a bit value of 0 or 1 based on rising edges or falling edges of the plurality of pulses included in the inputted glitch signal, wherein the bit value generation section inputs the glitch signal outputted by the filter section, and generates the bit value of 0 or 1 based on a parity of the number of rising edges of the plurality of pulses included in the inputted glitch signal, the bit generation apparatus comprising: a toggle flip-flop circuit as the bit generation section, which outputs the bit value of 0 or 1 based on the parity of the number of rising edges of the plurality of pulses included in the inputted glitch signal. a glitch generation section that generates a glitch signal including a plurality of pulses; a filter section configured to include series-connected N semiconductor devices, N being an integer of two or more, a first semiconductor device to an N-th semiconductor device, the filter section inputting via the first semiconductor device the glitch signal generated by the glitch generation section, removing a pulse whose width is less than a predetermined pulse width, by allowing the inputted glitch signal to pass through the first semiconductor device to the N-th semiconductor device, and outputting via the N-th semiconductor device the glitch signal from which the pulse whose width is less than the predetermined pulse width has been removed; and a bit value generation section that inputs the glitch signal outputted by the filter section, and generates a bit value of 0 or 1 based on rising edges or falling edges of the plurality of pulses included in the inputted glitch signal, wherein the bit value generation section inputs the glitch signal outputted by the filter section, and generates the bit value of 0 or 1 based on a parity of the number of rising edges of the plurality of pulses included in the inputted glitch signal, the bit generation apparatus comprising: a toggle flip-flop circuit as the bit generation section, which outputs the bit value of 0 or 1 based on the parity of the number of rising edges of the plurality of pulses included in the inputted glitch signal. a toggle flip-flop circuit as the bit generation section, which outputs the bit value of 0 or 1 based on the parity of the number of rising edges of the plurality of pulses included in the inputted glitch signal.