A parallel associative memory for searching all the addresses at the same time and determining whether or not the same data as input data is stored, comprising: parity generation means for generating a parity of n-bit data inputted at write time and search time; and a plurality of memory locations corresponding to a plurality of addresses; in which each of said memory locations comprises n Content Addressable Memory, hereinafter termed CAM, memory cells for storing n-bit data inputted at the write time and comparing the n-bit data inputted at the search time and the stored n-bit data; a plurality of parity memory cells, each memory cell corresponding to a memory location and configured to store a parity generated by said parity generation means at the write time of n-bit data in said corresponding memory location; and parity check means comprising a plurality of parity check circuits, each parity check circuit corresponding to a parity memory cell and configured to judge whether or not a parity generated by said parity generation means at the search time and the parity stored in said parity memory cell are matched, wherein each parity check circuit is configured to activate a parity match signal (/PM) if there is a match between the parity generated by said parity generation means at the search time and the parity stored in said corresponding parity memory cell, and each of said memory locations further comprises a word match detection circuit for activating a word data match signal to a first logic level if the n-bit data inputted at the search time and the n-bit data stored in the CAM memory cells of said memory location are matched, and parity validation means comprising a plurality of parity validation circuits, each parity validation circuit corresponding to a parity memory cell and a memory location and configured to validate a corresponding parity match signal (/PM) outputted from a corresponding parity check circuit in response to the corresponding word data match signal being activated by said corresponding word match detection circuit; characterized in that the activation of each parity match signal (/PM) is made at a second logic level different from the first logic level by the correspond parity check circuit and in that the parallel associative memory further comprising parity error detection means for activating a parity error signal at the first logic level if any one of a plurality of parity match signals validated by said parity validation means and outputted from said plurality of memory locations is inactive. parity generation means for generating a parity of n-bit data inputted at write time and search time; and a plurality of memory locations corresponding to a plurality of addresses; in which each of said memory locations comprises n Content Addressable Memory, hereinafter termed CAM, memory cells for storing n-bit data inputted at the write time and comparing the n-bit data inputted at the search time and the stored n-bit data; a plurality of parity memory cells, each memory cell corresponding to a memory location and configured to store a parity generated by said parity generation means at the write time of n-bit data in said corresponding memory location; and parity check means comprising a plurality of parity check circuits, each parity check circuit corresponding to a parity memory cell and configured to judge whether or not a parity generated by said parity generation means at the search time and the parity stored in said parity memory cell are matched, wherein each parity check circuit is configured to activate a parity match signal (/PM) if there is a match between the parity generated by said parity generation means at the search time and the parity stored in said corresponding parity memory cell, and each of said memory locations further comprises a word match detection circuit for activating a word data match signal to a first logic level if the n-bit data inputted at the search time and the n-bit data stored in the CAM memory cells of said memory location are matched, and parity validation means comprising a plurality of parity validation circuits, each parity validation circuit corresponding to a parity memory cell and a memory location and configured to validate a corresponding parity match signal (/PM) outputted from a corresponding parity check circuit in response to the corresponding word data match signal being activated by said corresponding word match detection circuit; characterized in that the activation of each parity match signal (/PM) is made at a second logic level different from the first logic level by the correspond parity check circuit and in that the parallel associative memory further comprising parity error detection means for activating a parity error signal at the first logic level if any one of a plurality of parity match signals validated by said parity validation means and outputted from said plurality of memory locations is inactive.