A microprocessor having architectural condition flags and which performs an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the microprocessor comprising: a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions, wherein if the architectural instruction specifies that the architectural condition flags are to be updated, then the first microinstruction indicates to write the architectural condition flags and the second microinstruction is of a first type; and if the architectural instruction specifies that the architectural condition flags are not to be updated, then the first microinstruction indicates not to write the architectural condition flags and the second microinstruction is of a second type; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the operation on the source operands to generate the result; and if the first microinstruction indicates to write the architectural condition flags, generates a non-architectural indicator that indicates whether the architectural condition flags satisfy the condition; wherein in response to the second microinstruction, the execution pipeline: determines whether the condition is met based on the non-architectural indicator if the second microinstruction is of the first type and based on the architectural condition flags if the second microinstruction is of the second type; writes the destination register with the result generated by the first microinstruction, if the condition is met; and writes the destination register with the current value of the destination register, if the condition is not met. a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions, wherein if the architectural instruction specifies that the architectural condition flags are to be updated, then the first microinstruction indicates to write the architectural condition flags and the second microinstruction is of a first type; and if the architectural instruction specifies that the architectural condition flags are not to be updated, then the first microinstruction indicates not to write the architectural condition flags and the second microinstruction is of a second type; and if the architectural instruction specifies that the architectural condition flags are to be updated, then the first microinstruction indicates to write the architectural condition flags and the second microinstruction is of a first type; and if the architectural instruction specifies that the architectural condition flags are not to be updated, then the first microinstruction indicates not to write the architectural condition flags and the second microinstruction is of a second type; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline: performs the operation on the source operands to generate the result; and if the first microinstruction indicates to write the architectural condition flags, generates a non-architectural indicator that indicates whether the architectural condition flags satisfy the condition; performs the operation on the source operands to generate the result; and if the first microinstruction indicates to write the architectural condition flags, generates a non-architectural indicator that indicates whether the architectural condition flags satisfy the condition; wherein in response to the second microinstruction, the execution pipeline: determines whether the condition is met based on the non-architectural indicator if the second microinstruction is of the first type and based on the architectural condition flags if the second microinstruction is of the second type; writes the destination register with the result generated by the first microinstruction, if the condition is met; and writes the destination register with the current value of the destination register, if the condition is not met. determines whether the condition is met based on the non-architectural indicator if the second microinstruction is of the first type and based on the architectural condition flags if the second microinstruction is of the second type; writes the destination register with the result generated by the first microinstruction, if the condition is met; and writes the destination register with the current value of the destination register, if the condition is not met.