A method for forming a three-dimensional memory device (200, 300), comprising: forming a dielectric deck (304A, 304B) comprising interleaved sacrificial layers and dielectric layers (206, 306) on a substrate (202, 302), wherein the dielectric deck comprises an upper deck (207N, 304B) and a lower deck (207A, 304A) separated by a joint oxide layer (203, 303); forming an opening (222, 224, 320, 322, 324) extending vertically through the dielectric deck (304A, 304B); etching a side of the sacrificial layers that abuts a sidewall of the opening (222, 224, 320, 322, 324); forming a discontinuous blocking layer (212, 312, 2121, 2122) at the locations where the sacrificial layers are etched, wherein the discontinuous blocking layer (212, 312) extends through the upper and lower decks (304B, 304A), and wherein the sidewall of the discontinuous blocking layer (112, 312) is completely flush with the sidewall of the joint oxide layer (103, 203, 303) or the sidewalls of the two layers have a shift between each other of no more than 1 nm; wherein a memory stack (307A, 307B) having interleaved conductor layers (209, 309) and the dielectric layers (206, 306) is formed by replacing, with the conductor layers, the sacrificial layers in the dielectric stack (304A, 304B), wherein the conductor layers (209, 309) are formed from tungsten, cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof, wherein the discontinuous blocking layer (112, 312, 2121, 2122) includes multiple small sections, with adjacent sections along the vertical direction being separated by dielectric layers (206, 306), wherein each small section abuts the storage layer (214, 314) on one end and abuts a side of one layer of the conductor layer (209, 309) on the other end, and is located in a recess of that conductor layer (209, 309) surrounded by two adjacent dielectric layers (206, 306) and one side of that conductor layer (209, 309) and subsequently (410, 412) forming a storage layer (214, 314), a tunneling layer (216, 316), and a semiconductor channel (218, 318) over the discontinuous blocking layer (212, 312) and the interposed dielectric layers (206, 306), wherein the dielectric layers (206, 306) include dielectric materials similar to that of the discontinuous blocking layer (212, 312, 2121, 2122), so that the discontinuous blocking layer (212, 312, 2121, 2122) and dielectric layers (206, 306) collectively form a continuous blocking layer along the sidewall of the memory string, characterised in that forming the discontinuous blocking layer (212, 312, 2121, 2122) comprises oxidizing the etched side of the sacrificial layers. forming an opening (222, 224, 320, 322, 324) extending vertically through the dielectric deck (304A, 304B); etching a side of the sacrificial layers that abuts a sidewall of the opening (222, 224, 320, 322, 324); forming a discontinuous blocking layer (212, 312, 2121, 2122) at the locations where the sacrificial layers are etched, wherein the discontinuous blocking layer (212, 312) extends through the upper and lower decks (304B, 304A), and wherein the sidewall of the discontinuous blocking layer (112, 312) is completely flush with the sidewall of the joint oxide layer (103, 203, 303) or the sidewalls of the two layers have a shift between each other of no more than 1 nm; wherein a memory stack (307A, 307B) having interleaved conductor layers (209, 309) and the dielectric layers (206, 306) is formed by replacing, with the conductor layers, the sacrificial layers in the dielectric stack (304A, 304B), wherein the conductor layers (209, 309) are formed from tungsten, cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof, wherein the discontinuous blocking layer (112, 312, 2121, 2122) includes multiple small sections, with adjacent sections along the vertical direction being separated by dielectric layers (206, 306), wherein each small section abuts the storage layer (214, 314) on one end and abuts a side of one layer of the conductor layer (209, 309) on the other end, and is located in a recess of that conductor layer (209, 309) surrounded by two adjacent dielectric layers (206, 306) and one side of that conductor layer (209, 309) and subsequently (410, 412) forming a storage layer (214, 314), a tunneling layer (216, 316), and a semiconductor channel (218, 318) over the discontinuous blocking layer (212, 312) and the interposed dielectric layers (206, 306), wherein the dielectric layers (206, 306) include dielectric materials similar to that of the discontinuous blocking layer (212, 312, 2121, 2122), so that the discontinuous blocking layer (212, 312, 2121, 2122) and dielectric layers (206, 306) collectively form a continuous blocking layer along the sidewall of the memory string, characterised in that forming the discontinuous blocking layer (212, 312, 2121, 2122) comprises oxidizing the etched side of the sacrificial layers.