A memory circuit comprising: a volatile memory; a write circuit; a first non-volatile memory and a second non-volatile memory; a read circuit; and at least one selector circuit; wherein: - the memory circuit is configured to receive alternatively one of a first level clock signal and a second level clock signal; - the memory circuit is configured such that during each first level clock signal: -- the write circuit is configured to write new data stored in the volatile memory as current data into the first non-volatile memory and the second non-volatile memory; and -- the volatile memory is configured to transmit the new data as the current data to the at least one selector circuit; - the memory circuit is configured such that during each second level clock signal: -- the read circuit is configured to read the current data stored in the first non-volatile memory and in the second non-volatile memory and transmit the current data to the at least one selector circuit; and -- the volatile memory is configured to store new data; and - the at least one selector circuit is configured to output the current data transmitted either by the volatile memory or by the read circuit, depending on whether the memory circuit is receiving the first level clock signal or the second level clock signal. a volatile memory; a write circuit; a first non-volatile memory and a second non-volatile memory; a read circuit; and at least one selector circuit; wherein: - the memory circuit is configured to receive alternatively one of a first level clock signal and a second level clock signal; - the memory circuit is configured such that during each first level clock signal: -- the write circuit is configured to write new data stored in the volatile memory as current data into the first non-volatile memory and the second non-volatile memory; and -- the volatile memory is configured to transmit the new data as the current data to the at least one selector circuit; - the memory circuit is configured such that during each second level clock signal: -- the read circuit is configured to read the current data stored in the first non-volatile memory and in the second non-volatile memory and transmit the current data to the at least one selector circuit; and -- the volatile memory is configured to store new data; and - the at least one selector circuit is configured to output the current data transmitted either by the volatile memory or by the read circuit, depending on whether the memory circuit is receiving the first level clock signal or the second level clock signal. - the memory circuit is configured to receive alternatively one of a first level clock signal and a second level clock signal; - the memory circuit is configured such that during each first level clock signal: -- the write circuit is configured to write new data stored in the volatile memory as current data into the first non-volatile memory and the second non-volatile memory; and -- the volatile memory is configured to transmit the new data as the current data to the at least one selector circuit; -- the write circuit is configured to write new data stored in the volatile memory as current data into the first non-volatile memory and the second non-volatile memory; and -- the volatile memory is configured to transmit the new data as the current data to the at least one selector circuit; - the memory circuit is configured such that during each second level clock signal: -- the read circuit is configured to read the current data stored in the first non-volatile memory and in the second non-volatile memory and transmit the current data to the at least one selector circuit; and -- the volatile memory is configured to store new data; and -- the read circuit is configured to read the current data stored in the first non-volatile memory and in the second non-volatile memory and transmit the current data to the at least one selector circuit; and -- the volatile memory is configured to store new data; and - the at least one selector circuit is configured to output the current data transmitted either by the volatile memory or by the read circuit, depending on whether the memory circuit is receiving the first level clock signal or the second level clock signal.