A method for encapsulating a semiconductor device comprising the steps of: a) providing a mold having top (110, 201) and bottom (120, 202) portions to form a cavity (130, 210) for creating a package having planar top and side areas, the top mold portion (110, 201) having a center die (111, 203) to define the planar top area of the package, and side dies (112, 113, 204, 205) to define the planar side areas of the package, the center die (111, 203) separated from the side dies (112, 113, 204, 205) by a gap (170, 206) having a width (170a, 206a) and further having protruding members (180, 207) along the die perimeter, the members (180, 207) extending toward the cavity (130, 210) and having a height (180a, 207a) equal to the width of the gap (170a, 206a); b) lining the top mold portion (110, 201) facing the cavity (130, 210) with a protective plastic tape; c) pulling the plastic tape tight to the contours of the top mold portion (110, 201) by applying vacuum to the gap (170, 206), thereby causing the tape to line the center die members (180, 207) and to bridge the gap (170, 206); d) providing a semiconductor chip (801, 230) on a substrate (802, 240); e) positioning the substrate (802, 240) on the bottom mold portion (120, 202, 250), so that the chip faces away from the bottom mold (120, 202, 250); f) dispensing a pre-determined amount of encapsulation compound (260, 810) over the chips (230, 801) to cover the chips and portions of the substrate (240, 802) near the chips; and g) closing the mold portions (110, 120, 201, 202) by clamping the top portion (110, 201) onto the bottom portion (120, 202), thereby forming a seal of the tape surrounding the substrate (240, 802); and h) shaping the encapsulation compound (260, 810) to follow the contours of the tape to form a recess along edge lines formed where the planar top and side areas intersect, thereby preserving the planarity of the top package area by preventing any compound (260, 810) to reach over the top area plane. a) providing a mold having top (110, 201) and bottom (120, 202) portions to form a cavity (130, 210) for creating a package having planar top and side areas, the top mold portion (110, 201) having a center die (111, 203) to define the planar top area of the package, and side dies (112, 113, 204, 205) to define the planar side areas of the package, the center die (111, 203) separated from the side dies (112, 113, 204, 205) by a gap (170, 206) having a width (170a, 206a) and further having protruding members (180, 207) along the die perimeter, the members (180, 207) extending toward the cavity (130, 210) and having a height (180a, 207a) equal to the width of the gap (170a, 206a); b) lining the top mold portion (110, 201) facing the cavity (130, 210) with a protective plastic tape; c) pulling the plastic tape tight to the contours of the top mold portion (110, 201) by applying vacuum to the gap (170, 206), thereby causing the tape to line the center die members (180, 207) and to bridge the gap (170, 206); d) providing a semiconductor chip (801, 230) on a substrate (802, 240); e) positioning the substrate (802, 240) on the bottom mold portion (120, 202, 250), so that the chip faces away from the bottom mold (120, 202, 250); f) dispensing a pre-determined amount of encapsulation compound (260, 810) over the chips (230, 801) to cover the chips and portions of the substrate (240, 802) near the chips; and g) closing the mold portions (110, 120, 201, 202) by clamping the top portion (110, 201) onto the bottom portion (120, 202), thereby forming a seal of the tape surrounding the substrate (240, 802); and h) shaping the encapsulation compound (260, 810) to follow the contours of the tape to form a recess along edge lines formed where the planar top and side areas intersect, thereby preserving the planarity of the top package area by preventing any compound (260, 810) to reach over the top area plane.