A double phase-locked loop, comprising: a first narrowband phase-locked loop (160, 360) including a first phase detector (120, 304a), and a first loop filter (122, 322) configured to receive a first input clock (Ref !n) at a first input of the first phase detector (120, 304a) and to reduce phase noise having frequencies of less than 10 Hz in the first input clock; a second phase-locked loop (150, 350) including a second phase detector (104, 304), and a second loop filter (105, 305) configured to receive a second input clock from a stable clock source (103, 300) at a first input of the second phase detector (104, 304), the second input clock having a frequency close to a frequency of the first input clock such that there is a fractional offset in frequencies of not more than 200ppm, wherein a ratio between a bandwidth of the second loop filter (105, 305) and a bandwidth of the first loop filter (122, 322) is at least 10:1; a common controlled oscillator (109, 309) driven by a local oscillator (108, 308), the common controlled oscillator (109, 309) being shared by the first and second phase-locked loops, the output of the common controlled oscillator (109, 309) providing a common output which is coupled to second inputs of the first (120, 304a) and second (104, 304) phase detectors; and an adder (112, 312) configured to add an output of the first loop filter (122, 322) to an output of the second phase detector (104, 304) to couple the first and second phase-locked loops, wherein the second loop filter (105, 305) is coupled between the adder (112, 312) and the common controlled oscillator (109, 309) to provide a control signal to the common controlled oscillator (109, 309). a first narrowband phase-locked loop (160, 360) including a first phase detector (120, 304a), and a first loop filter (122, 322) configured to receive a first input clock (Ref !n) at a first input of the first phase detector (120, 304a) and to reduce phase noise having frequencies of less than 10 Hz in the first input clock; a second phase-locked loop (150, 350) including a second phase detector (104, 304), and a second loop filter (105, 305) configured to receive a second input clock from a stable clock source (103, 300) at a first input of the second phase detector (104, 304), the second input clock having a frequency close to a frequency of the first input clock such that there is a fractional offset in frequencies of not more than 200ppm, wherein a ratio between a bandwidth of the second loop filter (105, 305) and a bandwidth of the first loop filter (122, 322) is at least 10:1; a common controlled oscillator (109, 309) driven by a local oscillator (108, 308), the common controlled oscillator (109, 309) being shared by the first and second phase-locked loops, the output of the common controlled oscillator (109, 309) providing a common output which is coupled to second inputs of the first (120, 304a) and second (104, 304) phase detectors; and an adder (112, 312) configured to add an output of the first loop filter (122, 322) to an output of the second phase detector (104, 304) to couple the first and second phase-locked loops, wherein the second loop filter (105, 305) is coupled between the adder (112, 312) and the common controlled oscillator (109, 309) to provide a control signal to the common controlled oscillator (109, 309).