An image processor comprising: an array of execution lanes; and a two-dimensional shift register array, characterized in that the two-dimensional shift register array comprises: a plurality of cells arranged in a physical ordering that is different from a logical ordering of the plurality of cells, wherein each execution lane corresponds to a respective one of the plurality of cells, wherein each cell of one or more of the plurality of cells comprises: a plurality of N first input ports, each first input port corresponding to a particular input shift amount from an immediately preceding logically ordered cell, a plurality of N first output ports, each first output port corresponding to a particular output shift amount and coupled to a first input port of an immediately following logically ordered cell, a shifting unit cell configured to receive input shift data on a particular first input port, to write the input shift data to a local register space of the shifting unit cell, to read data from the local register space, and to provide output shift data to a particular first output port, and a straight-through cell configured to not perform any logical shift, said straight-through cell having a plurality of N second input ports and a plurality of N second output ports, wherein each second input port is coupled to a corresponding second output port, and wherein the straight-through cell is configured to receive input shift data on a particular second input port and to provide output shift data to a particular second output port. an array of execution lanes; and a two-dimensional shift register array, characterized in that the two-dimensional shift register array comprises: a plurality of cells arranged in a physical ordering that is different from a logical ordering of the plurality of cells, wherein each execution lane corresponds to a respective one of the plurality of cells, wherein each cell of one or more of the plurality of cells comprises: a plurality of N first input ports, each first input port corresponding to a particular input shift amount from an immediately preceding logically ordered cell, a plurality of N first output ports, each first output port corresponding to a particular output shift amount and coupled to a first input port of an immediately following logically ordered cell, a shifting unit cell configured to receive input shift data on a particular first input port, to write the input shift data to a local register space of the shifting unit cell, to read data from the local register space, and to provide output shift data to a particular first output port, and a straight-through cell configured to not perform any logical shift, said straight-through cell having a plurality of N second input ports and a plurality of N second output ports, wherein each second input port is coupled to a corresponding second output port, and wherein the straight-through cell is configured to receive input shift data on a particular second input port and to provide output shift data to a particular second output port. a plurality of cells arranged in a physical ordering that is different from a logical ordering of the plurality of cells, wherein each execution lane corresponds to a respective one of the plurality of cells, wherein each cell of one or more of the plurality of cells comprises: a plurality of N first input ports, each first input port corresponding to a particular input shift amount from an immediately preceding logically ordered cell, a plurality of N first output ports, each first output port corresponding to a particular output shift amount and coupled to a first input port of an immediately following logically ordered cell, a shifting unit cell configured to receive input shift data on a particular first input port, to write the input shift data to a local register space of the shifting unit cell, to read data from the local register space, and to provide output shift data to a particular first output port, and a straight-through cell configured to not perform any logical shift, said straight-through cell having a plurality of N second input ports and a plurality of N second output ports, wherein each second input port is coupled to a corresponding second output port, and wherein the straight-through cell is configured to receive input shift data on a particular second input port and to provide output shift data to a particular second output port. a plurality of N first input ports, each first input port corresponding to a particular input shift amount from an immediately preceding logically ordered cell, a plurality of N first output ports, each first output port corresponding to a particular output shift amount and coupled to a first input port of an immediately following logically ordered cell, a shifting unit cell configured to receive input shift data on a particular first input port, to write the input shift data to a local register space of the shifting unit cell, to read data from the local register space, and to provide output shift data to a particular first output port, and a straight-through cell configured to not perform any logical shift, said straight-through cell having a plurality of N second input ports and a plurality of N second output ports, wherein each second input port is coupled to a corresponding second output port, and wherein the straight-through cell is configured to receive input shift data on a particular second input port and to provide output shift data to a particular second output port.