A switching power supply circuit, comprising: a low power supply line; a master power supply line and a slave power supply line, the switching circuit being configured such that a potential applied to each of the master power supply line and the slave power supply line is higher than another potential applied to said low power supply line is applied; characterized by a master reactor and a slave reactor provided in said master power supply line and said slave power supply line respectively, the master reactor and the slave reactor having the same inductance; a first master diode and a first slave diode connected in series to said master reactor and to said slave reactor in said master power supply line and said slave power supply line respectively, the first master diode and said first slave diode having anodes pointing to said master reactor and said slave reactor respectively; a master insulated gate bipolar transistor provided between a node between said master reactor and said master diode, and said low power supply line, the master insulated gate bipolar transistor having an emitter pointing to said low power supply line; a slave insulated gate bipolar transistor provided between a node between said slave reactor and said first slave diode, and said low power supply line, the slave insulated gate bipolar transistor having an emitter pointing to said low power supply line; and a second slave diode connected in parallel to said slave insulated gate bipolar transistor, the second slave diode having an anode pointing to said low power supply line, wherein the switching supply circuit is further configured such that the master insulated gate bipolar transistor is brought into conduction if a current flowing in said master reactor becomes zero; the master insulated gate bipolar transistor is brought into nonconduction after elapse of a first period; the slave insulated gate bipolar transistor is brought into conduction subject to satisfaction of a first condition, said first condition being elapse of a second period after said master insulated gate bipolar transistor is brought into conduction, the second period being shorter than a third period from when said master insulated gate bipolar transistor is brought into conduction until when said master insulated gate bipolar transistor is brought into conduction again; and the slave insulated gate bipolar transistor is brought into nonconduction after elapse of a fourth period shorter than said first period. a low power supply line; a master power supply line and a slave power supply line, the switching circuit being configured such that a potential applied to each of the master power supply line and the slave power supply line is higher than another potential applied to said low power supply line is applied; characterized by a master reactor and a slave reactor provided in said master power supply line and said slave power supply line respectively, the master reactor and the slave reactor having the same inductance; a first master diode and a first slave diode connected in series to said master reactor and to said slave reactor in said master power supply line and said slave power supply line respectively, the first master diode and said first slave diode having anodes pointing to said master reactor and said slave reactor respectively; a master insulated gate bipolar transistor provided between a node between said master reactor and said master diode, and said low power supply line, the master insulated gate bipolar transistor having an emitter pointing to said low power supply line; a slave insulated gate bipolar transistor provided between a node between said slave reactor and said first slave diode, and said low power supply line, the slave insulated gate bipolar transistor having an emitter pointing to said low power supply line; and a second slave diode connected in parallel to said slave insulated gate bipolar transistor, the second slave diode having an anode pointing to said low power supply line, wherein the switching supply circuit is further configured such that the master insulated gate bipolar transistor is brought into conduction if a current flowing in said master reactor becomes zero; the master insulated gate bipolar transistor is brought into nonconduction after elapse of a first period; the slave insulated gate bipolar transistor is brought into conduction subject to satisfaction of a first condition, said first condition being elapse of a second period after said master insulated gate bipolar transistor is brought into conduction, the second period being shorter than a third period from when said master insulated gate bipolar transistor is brought into conduction until when said master insulated gate bipolar transistor is brought into conduction again; and the slave insulated gate bipolar transistor is brought into nonconduction after elapse of a fourth period shorter than said first period.