Apparatus comprising: register storage circuitry having a plurality of registers, each register to store at least four data elements; decoder circuitry responsive to a matrix multiply instruction to generate control signals, wherein the matrix multiply instruction specifies in the plurality of registers: a first source register, and second source register, and a destination register; and data processing circuitry responsive to the control signals to perform a matrix multiply operation comprising: extracting a first matrix of data elements from the first source register; extracting a second matrix of data elements from the second source register; performing plural dot product operations to generate a square matrix of result data elements, wherein each dot product operation acts on a respective row of the first matrix of data elements and a respective column of the second matrix of data elements to generate a respective result data element of the square matrix of result data elements; and applying the square matrix of result data elements to the destination register, wherein the matrix multiply instruction further specifies at least one of: a third source register, and wherein the matrix multiply operation comprises extracting the first matrix of data elements from the first source register and the third source register; a fourth source register, and wherein the matrix multiply operation comprises extracting the second matrix of data elements from the second source register and the fourth source register; and a further destination register, and wherein the matrix multiply operation comprises applying the square matrix of result data elements split between the destination register and the further destination register. register storage circuitry having a plurality of registers, each register to store at least four data elements; decoder circuitry responsive to a matrix multiply instruction to generate control signals, wherein the matrix multiply instruction specifies in the plurality of registers: a first source register, and second source register, and a destination register; and data processing circuitry responsive to the control signals to perform a matrix multiply operation comprising: extracting a first matrix of data elements from the first source register; extracting a second matrix of data elements from the second source register; performing plural dot product operations to generate a square matrix of result data elements, wherein each dot product operation acts on a respective row of the first matrix of data elements and a respective column of the second matrix of data elements to generate a respective result data element of the square matrix of result data elements; and applying the square matrix of result data elements to the destination register, wherein the matrix multiply instruction further specifies at least one of: a third source register, and wherein the matrix multiply operation comprises extracting the first matrix of data elements from the first source register and the third source register; a fourth source register, and wherein the matrix multiply operation comprises extracting the second matrix of data elements from the second source register and the fourth source register; and a further destination register, and wherein the matrix multiply operation comprises applying the square matrix of result data elements split between the destination register and the further destination register. extracting a first matrix of data elements from the first source register; extracting a second matrix of data elements from the second source register; performing plural dot product operations to generate a square matrix of result data elements, wherein each dot product operation acts on a respective row of the first matrix of data elements and a respective column of the second matrix of data elements to generate a respective result data element of the square matrix of result data elements; and applying the square matrix of result data elements to the destination register, wherein the matrix multiply instruction further specifies at least one of: a third source register, and wherein the matrix multiply operation comprises extracting the first matrix of data elements from the first source register and the third source register; a fourth source register, and wherein the matrix multiply operation comprises extracting the second matrix of data elements from the second source register and the fourth source register; and a further destination register, and wherein the matrix multiply operation comprises applying the square matrix of result data elements split between the destination register and the further destination register. a third source register, and wherein the matrix multiply operation comprises extracting the first matrix of data elements from the first source register and the third source register; a fourth source register, and wherein the matrix multiply operation comprises extracting the second matrix of data elements from the second source register and the fourth source register; and a further destination register, and wherein the matrix multiply operation comprises applying the square matrix of result data elements split between the destination register and the further destination register.