A solid-state imaging device comprising: a light receiving unit that includes M x N, M and N are integers equal to or greater than 2, pixels which are two-dimensionally arranged in a matrix of M rows and N columns and each of which includes a photodiode; a plurality of signal output units that are provided in association with a plurality of column groups, respectively, wherein each of the column groups includes two or more columns among the N columns; and a vertical shift register that controls charge outputs from the pixels on row by row basis, wherein each of the plurality of signal output units includes: two or more integrating circuits that are provided in association with the two or more columns included in a corresponding column group, respectively, and each of which accumulates charge output from the pixels included in a corresponding column and converts the charge into a voltage signal; two or more holding circuits that are connected to output ends of the two or more integrating circuits, respectively; a horizontal shift register that causes the two or more holding circuits to sequentially output voltage signals; an input terminal electrode group including a plurality of terminal electrodes for inputting a reset signal that resets the integrating circuits, a hold signal that controls input of voltage signals to the two or more holding circuits, a horizontal start signal that starts operation of the horizontal shift register, a horizontal clock signal that regulates clock of the horizontal shift register, a vertical start signal that starts operation of the vertical shift register, and a vertical clock signal that regulates clock of the vertical shift register; and an output terminal electrode that provides output signals sequentially output from the two or more holding circuits, a reset common line (Lcr) for providing the reset signal to the integrating circuits of each of the signal output units, a holding common line for providing the hold signal to the two or more holding circuits of each of the signal output units, a vertical start common line for providing the vertical start signal to the vertical shift register, and a vertical clock common line for providing the vertical clock signal to the vertical shift register are provided across the plurality of signal output units, among the plurality of terminal electrodes of the input terminal electrode group of each of the signal output unit, a terminal electrode for the reset signal, a terminal electrode for the hold signal, a terminal electrode for the vertical start signal, and a terminal electrode for the vertical clock signal are connected to the reset common line, the holding common line, the vertical start common line, and the vertical clock common line through switches, respectively, and each of the signal output units further includes a control terminal electrode for inputting a switch control signal that controls connection/disconnection of the switches. a light receiving unit that includes M x N, M and N are integers equal to or greater than 2, pixels which are two-dimensionally arranged in a matrix of M rows and N columns and each of which includes a photodiode; a plurality of signal output units that are provided in association with a plurality of column groups, respectively, wherein each of the column groups includes two or more columns among the N columns; and a vertical shift register that controls charge outputs from the pixels on row by row basis, two or more integrating circuits that are provided in association with the two or more columns included in a corresponding column group, respectively, and each of which accumulates charge output from the pixels included in a corresponding column and converts the charge into a voltage signal; two or more holding circuits that are connected to output ends of the two or more integrating circuits, respectively;