A semiconductor device comprising: a first drive control circuit (21, 21_1) which drives a gate terminal of a first IGBT (12_1), a second drive control circuit (21, 21_2) which drives a gate terminal of a second IGBT (12_2) coupled in parallel with the first IGBT (12_1), and a state machine control circuit which controls an operation mode of the semiconductor device, the operation mode including a normal mode and a test mode, wherein each of the first and second drive control circuits (21, 21_1, 21_2) includes a base data memory which stores driving current information for rising and driving current information for falling, a current drive circuit which drives the corresponding IGBT based on a PWM signal and has a drive capability determined by the driving current information stored in the base data memory, and an output terminal (OT, OT1, OT2) to which an output terminal of the current drive circuit is coupled, and wherein, in the test mode, the first drive control circuit (21, 21_1) detects a first transition time from a start of charging a gate circuit capacity of the first IGBT (12_1) to an ON-state of the first IGBT (12_1) and a second transition time from a start of discharging the gate circuit capacity of the first IGBT (12_1) to an OFF-state of the first IGBT (12_1), wherein, in the test mode, the second drive control circuit (21, 21_2) detects a third transition time from a start of charging a gate circuit capacity of the second IGBT (12_2) to the ON-state of the second IGBT (12_2) and a fourth transition time from a start of discharging the gate circuit capacity of the second IGBT (12_2) to the OFF-state of the second IGBT (12_2), wherein the driving current information for rising stored in the base data memory is changed so that a turn-on time of the first IGBT (12_1) equals to a turn-on time of the second IGBT (12_2) based on the first and third transition times, and wherein the driving current information for falling stored in the base data memory is changed so that a turn-off time (TOFF1) of the first IGBT (12_1) equals to a turn-off time (TOFF2) of the second IGBT (12_2) based on the second and fourth transition times. a first drive control circuit (21, 21_1) which drives a gate terminal of a first IGBT (12_1), a second drive control circuit (21, 21_2) which drives a gate terminal of a second IGBT (12_2) coupled in parallel with the first IGBT (12_1), and a state machine control circuit which controls an operation mode of the semiconductor device, the operation mode including a normal mode and a test mode, wherein each of the first and second drive control circuits (21, 21_1, 21_2) includes a base data memory which stores driving current information for rising and driving current information for falling, a current drive circuit which drives the corresponding IGBT based on a PWM signal and has a drive capability determined by the driving current information stored in the base data memory, and an output terminal (OT, OT1, OT2) to which an output terminal of the current drive circuit is coupled, and wherein, in the test mode, the first drive control circuit (21, 21_1) detects a first transition time from a start of charging a gate circuit capacity of the first IGBT (12_1) to an ON-state of the first IGBT (12_1) and a second transition time from a start of discharging the gate circuit capacity of the first IGBT (12_1) to an OFF-state of the first IGBT (12_1), wherein, in the test mode, the second drive control circuit (21, 21_2) detects a third transition time from a start of charging a gate circuit capacity of the second IGBT (12_2) to the ON-state of the second IGBT (12_2) and a fourth transition time from a start of discharging the gate circuit capacity of the second IGBT (12_2) to the OFF-state of the second IGBT (12_2), wherein the driving current information for rising stored in the base data memory is changed so that a turn-on time of the first IGBT (12_1) equals to a turn-on time of the second IGBT (12_2) based on the first and third transition times, and wherein the driving current information for falling stored in the base data memory is changed so that a turn-off time (TOFF1) of the first IGBT (12_1) equals to a turn-off time (TOFF2) of the second IGBT (12_2) based on the second and fourth transition times.