Redundantly designed automation system, which has at least a first subsystem, at least a second subsystem and at least a third subsystem, wherein a sequence program is implemented in the subsystems (2, 3, 4) of the automation system in each case, which can be executed in a runtime environment (15, 17, 19) in order to fulfil automation tasks, and wherein a data memory is implemented in the subsystems (2, 3, 4) of the automation system in each case, wherein the sequence program has at least a first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) and a second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c), and wherein the data memory in each case has at least one first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) and a second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c), wherein the first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) is assigned to the first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) and the second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) is assigned to the second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c), and wherein the automation system is designed to synchronise the first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the first subsystem with the first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the second subsystem with a first synchronisation clock and to synchronise the first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the first subsystem with the first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the second subsystem with the first synchronisation clock, and to synchronise the second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the first subsystem with the second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the third subsystem with a second synchronisation clock, and to synchronise the second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the first subsystem with the second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the third subsystem with the second synchronisation clock, wherein the first synchronisation clock and the second synchronisation clock differ from one another. wherein a sequence program is implemented in the subsystems (2, 3, 4) of the automation system in each case, which can be executed in a runtime environment (15, 17, 19) in order to fulfil automation tasks, and wherein a data memory is implemented in the subsystems (2, 3, 4) of the automation system in each case, wherein the sequence program has at least a first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) and a second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c), and wherein the data memory in each case has at least one first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) and a second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c), wherein the first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) is assigned to the first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) and the second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) is assigned to the second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c), and wherein the automation system is designed to synchronise the first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the first subsystem with the first subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the second subsystem with a first synchronisation clock and to synchronise the first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the first subsystem with the first submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the second subsystem with the first synchronisation clock, and to synchronise the second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the first subsystem with the second subprogram (16a, 16b, 16c, 18a, 18b, 18c, 20a, 20b, 20c) of the third subsystem with a second synchronisation clock, and to synchronise the second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the first subsystem with the second submemory (21a, 21b, 21c, 22a, 22b, 22c, 23a, 23b, 23c) of the third subsystem with the second synchronisation clock, wherein the first synchronisation clock and the second synchronisation clock differ from one another.