A row decoder, for a non-volatile memory device, provided with a memory array, having memory cells arranged in a plurality of wordlines and receiving a supply voltage (Vdd), comprising: an input and pre-decoding module (10, 12), configured to receive address signals (AS r) and generate pre-decoded address signals ( PAS LV) at low voltage, in the range of the supply voltage (Vdd); a driving module, configured to generate biasing signals (S_WL) for biasing the wordlines of said memory array starting from decoded address signals (DAS HV), which are a function of the pre-decoded address signals ( PAS LV), at high voltage and in the range of a boosted voltage (Vx) higher than the supply voltage (Vdd); and a processing module, configured to receive said pre-decoded address signals ( PAS LV) and to jointly execute an operation of logic combination and an operation of voltage boosting of said pre-decoded address signals ( PAS LV) for generation of the decoded address signals (DAS HV), wherein said processing module comprises a plurality of processing units, each including: a decoding stage, which operates at low voltage and is configured to execute said operation of logic combination of said pre-decoded address signals ( PAS LV); a boosting stage, which operates at high voltage, configured to execute the voltage-boosting operation on the results of said logic combination, for generation on an output terminal (out) of a respective one of said decoded address signals (DAS HV); and a protection stage, set between said logic-combination stage and said boosting stage, for protecting said logic-combination stage from the high voltage present in said boosting stage; characterized in that said operation of logic combination is an OR logic operation between a respective first pre-decoded address signal (psx) and a respective second pre-decoded address signal (sxy); and wherein said decoding stage comprises: a first pair of combination transistors (38a, 38b), connected in parallel between a reference-potential terminal and a first combination node (N 1), a first combination transistor of the pair receiving on its own gate terminal the first pre-decoded address signal (psx), and the second combination transistor of the pair receiving on its own gate terminal the second pre-decoded address signal (sxy); and a second pair of combination transistors (39a, 39b), connected in series between the reference-potential terminal and a second combination node (N 2) that is designed to be coupled to said output terminal (out), a first combination transistor of the pair receiving on its own gate terminal the first pre-decoded address signal negated (psx_n), and the second combination transistor of the pair receiving on its own gate terminal the second pre-decoded address signal negated (sxy_n). an input and pre-decoding module (10, 12), configured to receive address signals (AS r) and generate pre-decoded address signals ( PAS LV) at low voltage, in the range of the supply voltage (Vdd); a driving module, configured to generate biasing signals (S_WL) for biasing the wordlines of said memory array starting from decoded address signals (DAS HV), which are a function of the pre-decoded address signals ( PAS LV), at high voltage and in the range of a boosted voltage (Vx) higher than the supply voltage (Vdd); and a processing module, configured to receive said pre-decoded address signals ( PAS LV) and to jointly execute an operation of logic combination and an operation of voltage boosting of said pre-decoded address signals ( PAS LV) for generation of the decoded address signals (DAS HV), wherein said processing module comprises a plurality of processing units, each including: a decoding stage, which operates at low voltage and is configured to execute said operation of logic combination of said pre-decoded address signals ( PAS LV); a boosting stage, which operates at high voltage, configured to execute the voltage-boosting operation on the results of said logic combination, for generation on an output terminal (out) of a respective one of said decoded address signals (DAS HV); and a protection stage, set between said logic-combination stage and said boosting stage, for protecting said logic-combination stage from the high voltage present in said boosting stage; characterized in that said operation of logic combination is an OR logic operation between a respective first pre-decoded address signal (psx) and a respective second pre-decoded address signal (sxy); and wherein said decoding stage comprises: a first pair of combination transistors (38a, 38b), connected in parallel between a reference-potential terminal and a first combination node (N 1), a first combination transistor of the pair receiving on its own gate terminal the first pre-decoded address signal (psx), and the second combination transistor of the pair receiving on its own gate terminal the second pre-decoded address signal (sxy); and a second pair of combination transistors (39a, 39b), connected in series between the reference-potential terminal and a second combination node (N 2) that is designed to be coupled to said output terminal (out), a first combination transistor of the pair receiving on its own gate terminal the first pre-decoded address signal negated (psx_n), and the second combination transistor of the pair receiving on its own gate terminal the second pre-decoded address signal negated (sxy_n).