A stacked device comprising: a lower chip including a plurality of wiring lands (55a, 55b, 55c, 55d) and a plurality of wall-block patterns (53a, 53b), each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of an array of the plurality of the wiring lands is higher than the wiring lands; and an upper chip including a plurality of wiring bumps (35a, 35b, 35c, 35d) assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of pyramidal or conical cone bumps (33a, 33b) assigned correspondingly to the positions of the wall-block patterns, respectively; the stacked device being characterized in that a first hydrophobic film is delineated in a periphery of the lower chip configured to surround the array of the wiring lands and the wall-block patterns, and a second hydrophobic film is delineated in a periphery of the upper chip configured to surround an array of the plurality of the wiring bumps and the plurality of cone bumps; and in that a wall-block pattern has a pyramidal concave with a cross-section apex angle α 1 greater than a cross-section apex angle α 2 of a cone bump (33p 1, 33p 2) assigned to the position of this wall-block pattern; or a wall-block pattern has a truncated pyramidal concave with a cross-section slant angle of the side wall β 1 /2 and a cone bump (33q 1, 33q 2) assigned to the position of this wall-block pattern has a cross-section apex angle β 2 and β 1 ≤ β 2. a lower chip including a plurality of wiring lands (55a, 55b, 55c, 55d) and a plurality of wall-block patterns (53a, 53b), each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of an array of the plurality of the wiring lands is higher than the wiring lands; and an upper chip including a plurality of wiring bumps (35a, 35b, 35c, 35d) assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of pyramidal or conical cone bumps (33a, 33b) assigned correspondingly to the positions of the wall-block patterns, respectively; the stacked device being characterized in that a first hydrophobic film is delineated in a periphery of the lower chip configured to surround the array of the wiring lands and the wall-block patterns, and a second hydrophobic film is delineated in a periphery of the upper chip configured to surround an array of the plurality of the wiring bumps and the plurality of cone bumps; and in that a wall-block pattern has a pyramidal concave with a cross-section apex angle α 1 greater than a cross-section apex angle α 2 of a cone bump (33p 1, 33p 2) assigned to the position of this wall-block pattern; or a wall-block pattern has a truncated pyramidal concave with a cross-section slant angle of the side wall β 1 /2 and a cone bump (33q 1, 33q 2) assigned to the position of this wall-block pattern has a cross-section apex angle β 2 and β 1 ≤ β 2.