A method of verifying values programmed into a plurality of non-volatile memory cells in a vector-by-matrix multiplication array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder in response to control signals from test control logic, all word lines in the array simultaneously; asserting, by the column decoder in response to control signals from the test control logic, a bit line in the array; sensing, by a sense amplifier, a current received from the bit line; and generating, by a reference current source a reference current (IREF 2607), the generating comprising: (i) receiving a reference current bias (Ibiasunit); (ii) receiving a digital input; (iii) mirroring the reference current bias into a plurality of devices, each of the plurality of devices comprising a first NMOS transistor comprising a first terminal providing an output current, a second terminal, and a gate receiving an enable signal; and a second NMOS transistor comprising a first terminal coupled to the second terminal of the first NMOS transistor, a second terminal coupled to ground, and a gate receiving the reference current bias; (iv) enabling one or more of the plurality of devices in response to the digital input by asserting the enable signal for the enabled devices; (v) mirroring the enabled devices by a buffer mirror to generate the reference current equal to the sum of the output currents generated by the enabled devices; comparing, by the test control logic, the current to the reference current to determine if the non-volatile memory cells coupled to the bit line contain the desired neuron value. asserting, by the row decoder in response to control signals from test control logic, all word lines in the array simultaneously; asserting, by the column decoder in response to control signals from the test control logic, a bit line in the array; sensing, by a sense amplifier, a current received from the bit line; and generating, by a reference current source a reference current (IREF 2607), the generating comprising: (i) receiving a reference current bias (Ibiasunit); (ii) receiving a digital input; (iii) mirroring the reference current bias into a plurality of devices, each of the plurality of devices comprising a first NMOS transistor comprising a first terminal providing an output current, a second terminal, and a gate receiving an enable signal; and a second NMOS transistor comprising a first terminal coupled to the second terminal of the first NMOS transistor, a second terminal coupled to ground, and a gate receiving the reference current bias; (iv) enabling one or more of the plurality of devices in response to the digital input by asserting the enable signal for the enabled devices; (v) mirroring the enabled devices by a buffer mirror to generate the reference current equal to the sum of the output currents generated by the enabled devices; comparing, by the test control logic, the current to the reference current to determine if the non-volatile memory cells coupled to the bit line contain the desired neuron value.