A method for operating a three-dimensional, 3D, memory device (100, 300, 301, 400, 500, 600), wherein the 3D memory device (100, 300, 301, 400, 500, 600) comprises a plurality of memory decks (204A, 204B) each comprising a plurality of memory layers in a vertical direction, a plurality of dummy memory layers between a first and second memory decks (204A and 204B) in the vertical direction, wherein the dummy memory layers have the same physical structure, but different electrical configuration, as the memory layer, and a plurality of NAND memory strings (308, 310) each extending vertically through the plurality of memory decks (204A, 204B) and each comprising a drain select transistor, the method comprising: first programming each memory layer in the first memory deck of the plurality of memory decks, the first programming comprises applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck; and second programming each memory layer in the second memory deck of the plurality of memory decks (204A, 204B) above the first memory deck, the second programming comprises (i) applying the program voltage to the memory layer and the first channel pass voltage to each of the rest of the memory layers in the second memory deck; and (ii) applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck; the second programming further comprising applying the second channel pass voltage to the dummy memory layers; the second programming further yet comprising applying a cut-off voltage smaller than a threshold voltage of a control gate to the control gate of at least one of the dummy memory layers to turn off the control gate, wherein preferably the second programming further comprises applying a set of voltages to a set of the dummy memory layers above the at least one dummy memory layer, and wherein preferably the set of voltages gradually decrease from the first channel pass voltage to the cut-off voltage. wherein the 3D memory device (100, 300, 301, 400, 500, 600) comprises a plurality of memory decks (204A, 204B) each comprising a plurality of memory layers in a vertical direction, a plurality of dummy memory layers between a first and second memory decks (204A and 204B) in the vertical direction, wherein the dummy memory layers have the same physical structure, but different electrical configuration, as the memory layer, and a plurality of NAND memory strings (308, 310) each extending vertically through the plurality of memory decks (204A, 204B) and each comprising a drain select transistor, the method comprising: first programming each memory layer in the first memory deck of the plurality of memory decks, the first programming comprises applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck; and second programming each memory layer in the second memory deck of the plurality of memory decks (204A, 204B) above the first memory deck, the second programming comprises (i) applying the program voltage to the memory layer and the first channel pass voltage to each of the rest of the memory layers in the second memory deck; and (ii) applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck; the second programming further comprising applying the second channel pass voltage to the dummy memory layers; the second programming further yet comprising applying a cut-off voltage smaller than a threshold voltage of a control gate to the control gate of at least one of the dummy memory layers to turn off the control gate, wherein preferably the second programming further comprises applying a set of voltages to a set of the dummy memory layers above the at least one dummy memory layer, and first programming each memory layer in the first memory deck of the plurality of memory decks, the first programming comprises applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck; and second programming each memory layer in the second memory deck of the plurality of memory decks (204A, 204B) above the first memory deck, the second programming comprises (i) applying the program voltage to the memory layer and the first channel pass voltage to each of the rest of the memory layers in the second memory deck; and (ii) applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck; (i) applying the program voltage to the memory layer and the first channel pass voltage to each of the rest of the memory layers in the second memory deck; and (ii) applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck; the second programming further comprising applying the second channel pass voltage to the dummy memory layers; the second programming further yet comprising applying a cut-off voltage smaller than a threshold voltage of a control gate to the control gate of at least one of the dummy memory layers to turn off the control gate, wherein preferably the second programming further comprises applying a set of voltages to a set of the dummy memory layers above the at least one dummy memory layer, and wherein preferably the set of voltages gradually decrease from the first channel pass voltage to the cut-off voltage.