A neural network accelerator, comprising: a multiplication unit and an adder tree unit configured to perform lattice-multiplication operations; and an accumulator unit (104, 104b) coupled to an output of the adder tree unit to form dot-product values from the lattice-multiplication operations performed by the multiplication unit and the adder tree unit, wherein the multiplication unit comprises n multiplier units (101, 201, 310) that perform lattice-multiplication-based operations and output product values, wherein each multiplier unit (101, 201, 310) comprises an N x N multiplier unit (101, 201, 310), and each multiplier unit (101, 201, 310) comprises four N/2 x N/2 multipliers, wherein n and N comprise 8, and each multiplier unit (101, 201, 310) receives a first multiplicand and a second multiplicand, the first multiplicand comprising a most significant nibble and a least significant nibble and the second multiplicand comprising a most significant nibble and a least significant nibble, and wherein each multiplier unit (101, 201, 310) comprises a first multiplier that receives the least significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, a second multiplier that receives the least significant nibble of the first multiplicand and the most significant nibble of the second multiplicand, a third multiplier that receives a most significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, and a fourth multiplier that receives the most significant nibble of the first multiplicand and the most significant nibble of the second multiplicand. a multiplication unit and an adder tree unit configured to perform lattice-multiplication operations; and an accumulator unit (104, 104b) coupled to an output of the adder tree unit to form dot-product values from the lattice-multiplication operations performed by the multiplication unit and the adder tree unit, wherein the multiplication unit comprises n multiplier units (101, 201, 310) that perform lattice-multiplication-based operations and output product values, wherein each multiplier unit (101, 201, 310) comprises an N x N multiplier unit (101, 201, 310), and each multiplier unit (101, 201, 310) comprises four N/2 x N/2 multipliers, wherein n and N comprise 8, and each multiplier unit (101, 201, 310) receives a first multiplicand and a second multiplicand, the first multiplicand comprising a most significant nibble and a least significant nibble and the second multiplicand comprising a most significant nibble and a least significant nibble, and wherein each multiplier unit (101, 201, 310) comprises a first multiplier that receives the least significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, a second multiplier that receives the least significant nibble of the first multiplicand and the most significant nibble of the second multiplicand, a third multiplier that receives a most significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, and a fourth multiplier that receives the most significant nibble of the first multiplicand and the most significant nibble of the second multiplicand.