A memory device, comprising: two calibration resistor interfaces, the two calibration resistor interfaces being connected to a same ZQ calibration resistor; and a first master chip, a plurality of cascaded first slave chips, a second master chip, and a plurality of cascaded second slave chips, which are commonly connected to the ZQ calibration resistor; wherein the first master chip, the first slave chips, the second master chip, and the second slave chips are provided with first transmission terminals and second transmission terminals, and the first transmission terminals and the second transmission terminals are used to transmit a ZQ flag signal; and wherein a second transmission terminal of the first master chip is connected to a first transmission terminal of a first slave chip of a first stage, a second transmission terminal of a first slave chip of each stage is connected to a first transmission terminal of a first slave chip of a next stage, a second transmission terminal of a second master chip is connected to a first transmission terminal of a second slave chip of a first stage, and a second transmission terminal of a second slave chip of each stage is connected to a first transmission terminal of a second slave chip of a next stage; the first master chip is provided with a first signal receiver, the second master chip is provided with a second signal receiver, and the first slave chips and the second slave chips are provided with third signal receivers; in a command mode, the first signal receiver is used to receive, through a ZQ signal terminal, a ZQ calibration command provided by a memory, the second signal receiver is used to receive and delay the ZQ calibration command by a ZQ signal terminal, the first master chip and the second master chip start to calibrate based on the ZQ calibration command, and the first master chip and the second master chip send the ZQ flag signal by the second transmission terminals after the calibration is completed, the ZQ flag signal indicating that a current chip has been calibrated with the calibration resistor; and the third signal receiver is used to receive the ZQ flag signal by the first transmission terminal, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and the first slave chips and the second slave chips send the ZQ flag signal by the second transmission terminals after the calibration is completed until all the first or second slave chips have been calibrated. two calibration resistor interfaces, the two calibration resistor interfaces being connected to a same ZQ calibration resistor; and a first master chip, a plurality of cascaded first slave chips, a second master chip, and a plurality of cascaded second slave chips, which are commonly connected to the ZQ calibration resistor; wherein the first master chip, the first slave chips, the second master chip, and the second slave chips are provided with first transmission terminals and second transmission terminals, and the first transmission terminals and the second transmission terminals are used to transmit a ZQ flag signal; and wherein a second transmission terminal of the first master chip is connected to a first transmission terminal of a first slave chip of a first stage, a second transmission terminal of a first slave chip of each stage is connected to a first transmission terminal of a first slave chip of a next stage, a second transmission terminal of a second master chip is connected to a first transmission terminal of a second slave chip of a first stage, and a second transmission terminal of a second slave chip of each stage is connected to a first transmission terminal of a second slave chip of a next stage; the first master chip is provided with a first signal receiver, the second master chip is provided with a second signal receiver, and the first slave chips and the second slave chips are provided with third signal receivers; in a command mode, the first signal receiver is used to receive, through a ZQ signal terminal, a ZQ calibration command provided by a memory, the second signal receiver is used to receive and delay the ZQ calibration command by a ZQ signal terminal, the first master chip and the second master chip start to calibrate based on the ZQ calibration command, and the first master chip and the second master chip send the ZQ flag signal by the second transmission terminals after the calibration is completed, the ZQ flag signal indicating that a current chip has been calibrated with the calibration resistor; and the third signal receiver is used to receive the ZQ flag signal by the first transmission terminal, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and the first slave chips and the second slave chips send the ZQ flag signal by the second transmission terminals after the calibration is completed until all the first or second slave chips have been calibrated.