A data processing apparatus configured to process a low density parity check, LDPC, code as prescribed in the DVB-S.2 standard ETSI EN 302 307 V1.1.2, said data processing apparatus comprising: a store configured to store code bits of the LDPC code in a row direction and a column direction, a re-arrangement unit configured to re-arrange code bits of the LDPC code, the LDPC code being generated in accordance with a parity check matrix comprising an information matrix and a parity matrix, the information matrix which corresponds to information bits of the LDPC code having a cyclic structure and the parity matrix which corresponds to parity bits of the LDPC code has a staircase structure, the LDPC code bits being transmitted as symbols each formed from m code bits of the LDPC code, where m is equal to 4, 6, 8, 10, or 12, to write in the column direction into the store and read out in the row direction from said store, wherein the store stores mb bits in the row direction and stores N/(mb) bits in the column direction, where b is a positive integer and N is the LDPC code length, the LDPC code having an information length of K bits, and to column twist interleave by changing the writing starting position of a column when the code bits of the LDPC code are to be written in the column direction into said store as a re-arrangement process for re-arranging the code bits of the LDPC code, and a parity interleaver configured to parity interleave the K+qx+y+1th code bit from among the parity bits which are K+1th to K+Mth code bits of the LDPC code to the position of the K+Py+x+1th code bit, K + M = N, x being an integer higher than 0 but lower than P and y being an integer higher than 0 but lower than q, where P = 360 and q = M/360. a store configured to store code bits of the LDPC code in a row direction and a column direction, a re-arrangement unit configured to re-arrange code bits of the LDPC code, the LDPC code being generated in accordance with a parity check matrix comprising an information matrix and a parity matrix, the information matrix which corresponds to information bits of the LDPC code having a cyclic structure and the parity matrix which corresponds to parity bits of the LDPC code has a staircase structure, the LDPC code bits being transmitted as symbols each formed from m code bits of the LDPC code, where m is equal to 4, 6, 8, 10, or 12, to write in the column direction into the store and read out in the row direction from said store, wherein the store stores mb bits in the row direction and stores N/(mb) bits in the column direction, where b is a positive integer and N is the LDPC code length, the LDPC code having an information length of K bits, and to column twist interleave by changing the writing starting position of a column when the code bits of the LDPC code are to be written in the column direction into said store as a re-arrangement process for re-arranging the code bits of the LDPC code, and a parity interleaver configured to parity interleave the K+qx+y+1th code bit from among the parity bits which are K+1th to K+Mth code bits of the LDPC code to the position of the K+Py+x+1th code bit, K + M = N, x being an integer higher than 0 but lower than P and y being an integer higher than 0 but lower than q, where P = 360 and q = M/360.