An integrated circuit comprising: a plurality of logic tiles, wherein each logic tile includes: a plurality of computing elements; a plurality of switches i) electrically coupled to at least one computing element and ii) electrically interconnected and arranged in a plurality of switch matrices (1.N), wherein each switch matrix of the plurality of switch matrices is associated with at least one computing element and include a plurality of the switches; and wherein the plurality of switch matrices are arranged in a plurality of stages (Stage N) of switch matrices, including: a first stage (Stage 2) of switch matrices configured in a hierarchical network a second stage of switch matrices configured in a hierarchical network and a third stage of switch matrices, wherein each matrix of the third stage of switch matrices includes a plurality of inputs and a plurality of outputs and is i) configured in a mesh network wherein the plurality of outputs of each switch matrix of the third stage of switch matrices are routed tc selected other switch matrices of the third stage and ii) electrically coupled to one or more switches of the switch matrices of the first stage of switch matrices and/or one or more switches of the switch matrices of the second stage of switch matrices, and wherein the third stage of switch matrices is the highest stage of the plurality of stages wherein each switch matrix of the third stage of switch matrices is directly connected to only one switch matrix of the second stage of switch matrices. a plurality of logic tiles, wherein each logic tile includes: a plurality of computing elements; a plurality of switches i) electrically coupled to at least one computing element and ii) electrically interconnected and arranged in a plurality of switch matrices (1.N), wherein each switch matrix of the plurality of switch matrices is associated with at least one computing element and include a plurality of the switches; and a plurality of computing elements; a plurality of switches i) electrically coupled to at least one computing element and ii) electrically interconnected and arranged in a plurality of switch matrices (1.N), wherein each switch matrix of the plurality of switch matrices is associated with at least one computing element and include a plurality of the switches; and wherein the plurality of switch matrices are arranged in a plurality of stages (Stage N) of switch matrices, including: a first stage (Stage 2) of switch matrices configured in a hierarchical network a second stage of switch matrices configured in a hierarchical network and a third stage of switch matrices, wherein each matrix of the third stage of switch matrices includes a plurality of inputs and a plurality of outputs and is i) configured in a mesh network wherein the plurality of outputs of each switch matrix of the third stage of switch matrices are routed tc selected other switch matrices of the third stage and ii) electrically coupled to one or more switches of the switch matrices of the first stage of switch matrices and/or one or more switches of the switch matrices of the second stage of switch matrices, and wherein the third stage of switch matrices is the highest stage of the plurality of stages a first stage (Stage 2) of switch matrices configured in a hierarchical network a second stage of switch matrices configured in a hierarchical network and a third stage of switch matrices, wherein each matrix of the third stage of switch matrices includes a plurality of inputs and a plurality of outputs and is i) configured in a mesh network wherein the plurality of outputs of each switch matrix of the third stage of switch matrices are routed tc selected other switch matrices of the third stage and ii) electrically coupled to one or more switches of the switch matrices of the first stage of switch matrices and/or one or more switches of the switch matrices of the second stage of switch matrices, and wherein the third stage of switch matrices is the highest stage of the plurality of stages wherein each switch matrix of the third stage of switch matrices is directly connected to only one switch matrix of the second stage of switch matrices.