An organic light emitting diode OLED display comprising: a display unit comprising a plurality of data lines (DL[n]), a plurality of scan lines (SL[n]), and a plurality of pixels coupled to corresponding data lines and corresponding scan lines; a scan driver configured to supply a plurality of scan signals (S[n], Sr[n], Sg[n], Sb[n]) to the scan lines; a data driver configured to: output a plurality of first data signals through a plurality of first output lines (DO[s-1]), output a plurality of second data signals through the first output lines, and output a plurality of third data signals through a plurality of second output lines (DO[s]), wherein the first data signals represent a first colour, the second data signals represent a second colour, and the third data signals represent a third colour; a data distribution unit configured to: transmit the first data signals to a plurality of corresponding first data lines (DL[m-2]) according to a first clock signal, transmit the second data signals to a plurality of corresponding second data lines (DL[m]) according to a second clock signal, and transmit the third data signals to a plurality of corresponding third data lines (DL[m-1]) according to a third clock signal, wherein a horizontal period comprises: a writing period (Tw) in which a corresponding voltage of the first to third data signals are respectively stored in first to third capacitive elements (Cr, Cg, Cb), and a scan period (Ts) in which the corresponding voltage of the first to third data signals stored in the first to third capacitive elements are transmitted to the corresponding data lines, and wherein the data driver is further configured to: sequentially output the first data signal and the second data signal during the writing period, and wherein the data driver outputs the third data signal to overlap with at least one of the first data signal or the second data signal; and a signal controller configured to output the first and second clock signals having sequential activation periods (P1, P2), respectively, during the writing period, wherein the signal controller is configured to output the third clock signal having an activation period overlapping an activation period of at least one of the first clock signal and the second clock signal during the writing period. a display unit comprising a plurality of data lines (DL[n]), a plurality of scan lines (SL[n]), and a plurality of pixels coupled to corresponding data lines and corresponding scan lines; a scan driver configured to supply a plurality of scan signals (S[n], Sr[n], Sg[n], Sb[n]) to the scan lines; output a plurality of first data signals through a plurality of first output lines (DO[s-1]), output a plurality of second data signals through the first output lines, and output a plurality of third data signals through a plurality of second output lines (DO[s]), wherein the first data signals represent a first colour, the second data signals represent a second colour, and the third data signals represent a third colour; transmit the first data signals to a plurality of corresponding first data lines (DL[m-2]) according to a first clock signal, transmit the second data signals to a plurality of corresponding second data lines (DL[m]) according to a second clock signal, and transmit the third data signals to a plurality of corresponding third data lines (DL[m-1]) according to a third clock signal, wherein a writing period (Tw) in which a corresponding voltage of the first to third data signals are respectively stored in first to third capacitive elements (Cr, Cg, Cb), and a scan period (Ts) in which the corresponding voltage of the first to third data signals stored in the first to third capacitive elements are transmitted to the corresponding data lines, and wherein the data driver is further configured to: sequentially output the first data signal and the second data signal during the writing period, and wherein the data driver outputs the third data signal to overlap with at least one of the first data signal or the second data signal; and a signal controller configured to output the first and second clock signals having sequential activation periods (P1, P2), respectively, during the writing period, wherein the signal controller is configured to output the third clock signal having an activation period overlapping an activation period of at least one of the first clock signal and the second clock signal during the writing period. sequentially output the first data signal and the second data signal during the writing period, and wherein the data driver outputs the third data signal to overlap with at least one of the first data signal or the second data signal; and a signal controller configured to output the first and second clock signals having sequential activation periods (P1, P2), respectively, during the writing period, wherein the signal controller is configured to output the third clock signal having an activation period overlapping an activation period of at least one of the first clock signal and the second clock signal during the writing period.