A memory circuit, comprising: a plurality of memory tiles (210 - 226) arranged as an array having L+1 rows and N+1 columns, each memory tile in the plurality of memory tiles comprising a plurality of resistive non-volatile memory, NVM, bit cells arranged as an array having P+1 rows and Q+1 columns, and a read and write control circuit coupled to the plurality of bit cells, the read and write control circuit configured to provide latched data to the plurality of resistive NVM bit cells during write operations; a row circuit configured to receive a row address (ROW_ADDR) signal identifying the row of a bit cell of the plurality of bit cells in a memory tile of the plurality of memory tiles, and a read-write control signal; a column circuit configured to a) receive a column address (COL_ADDR) signal identifying the column of a bit cell of the plurality of bit cells in a memory tile of the plurality of memory tiles, and the read-write control signal, b) receive and send data signals (DATA) from a controller, c) provide column access signals (CA'[0..Q]) and tile data signals (TDATA[0..N]) to the plurality of memory tiles, and d) receive global bit-line signals (GBLR[0..N]) from the plurality of memory tiles; a respective write control line (RWR,..RWR) coupled between the row circuit and each read and write control circuit in the respective row of tiles, each configured to receive a write control signal to initiate a write operation in a memory tile in the respective row of tiles; wherein the row circuit is configured to provide a first write control signal to a first of the write control lines to initiate a first write operation in a first memory tile, and a second write control signal to a second write control line to initiate a second write operation in a second memory tile, the second write operation being initiated before the first write operation is completed. a plurality of memory tiles (210 - 226) arranged as an array having L+1 rows and N+1 columns, each memory tile in the plurality of memory tiles comprising a plurality of resistive non-volatile memory, NVM, bit cells arranged as an array having P+1 rows and Q+1 columns, and a read and write control circuit coupled to the plurality of bit cells, the read and write control circuit configured to provide latched data to the plurality of resistive NVM bit cells during write operations; a plurality of resistive non-volatile memory, NVM, bit cells arranged as an array having P+1 rows and Q+1 columns, and a read and write control circuit coupled to the plurality of bit cells, the read and write control circuit configured to provide latched data to the plurality of resistive NVM bit cells during write operations; a row circuit configured to receive a row address (ROW_ADDR) signal identifying the row of a bit cell of the plurality of bit cells in a memory tile of the plurality of memory tiles, and a read-write control signal; a column circuit configured to a) receive a column address (COL_ADDR) signal identifying the column of a bit cell of the plurality of bit cells in a memory tile of the plurality of memory tiles, and the read-write control signal, b) receive and send data signals (DATA) from a controller, c) provide column access signals (CA'[0..Q]) and tile data signals (TDATA[0..N]) to the plurality of memory tiles, and d) receive global bit-line signals (GBLR[0..N]) from the plurality of memory tiles; a) receive a column address (COL_ADDR) signal identifying the column of a bit cell of the plurality of bit cells in a memory tile of the plurality of memory tiles, and the read-write control signal, b) receive and send data signals (DATA) from a controller, c) provide column access signals (CA'[0..Q]) and tile data signals (TDATA[0..N]) to the plurality of memory tiles, and d) receive global bit-line signals (GBLR[0..N]) from the plurality of memory tiles; a respective write control line (RWR,..RWR) coupled between the row circuit and each read and write control circuit in the respective row of tiles, each configured to receive a write control signal to initiate a write operation in a memory tile in the respective row of tiles; wherein the row circuit is configured to provide a first write control signal to a first of the write control lines to initiate a first write operation in a first memory tile, and a second write control signal to a second write control line to initiate a second write operation in a second memory tile, the second write operation being initiated before the first write operation is completed. a first write control signal to a first of the write control lines to initiate a first write operation in a first memory tile, and a second write control signal to a second write control line to initiate a second write operation in a second memory tile, the second write operation being initiated before the first write operation is completed.