A hardware accelerator engine (400, 500, 600) that supports efficient mapping of convolutional stages of deep neural network algorithms, the hardware accelerator engine (400, 500, 600) comprising: a set of control registers; a stream switch having a plurality of input bus ports and a plurality of output bus ports; a plurality of convolution accelerators (600, 600A, 600B), each one convolution accelerator of the plurality of convolution accelerators (600, 600A, 600B) including: a kernel buffer; a feature line buffer; wherein the feature line buffer is configured to receive and store a plurality of lines of feature data arranged as at least one image frame, wherein each line of feature data has a first tag and a last tag, and the at least one image frame also has a first line tag on its first line and a second line tag on its last line; validation logic configured to check and verify that tag information included in the feature data has a correct format; a plurality of multiply-accumulate, MAC, units arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer; and at least one input bus (602, 604, 606) coupled to an output bus port of the plurality of output bus ports of the stream switch; at least one output bus coupled to an input bus port of the plurality of input bus ports of the stream switch; or at least one input bus (602, 604, 606) and at least one output bus hard wired to respective output bus and input bus ports of the stream switch. a set of control registers; a stream switch having a plurality of input bus ports and a plurality of output bus ports; a plurality of convolution accelerators (600, 600A, 600B), each one convolution accelerator of the plurality of convolution accelerators (600, 600A, 600B) including: a kernel buffer; a feature line buffer; wherein the feature line buffer is configured to receive and store a plurality of lines of feature data arranged as at least one image frame, wherein each line of feature data has a first tag and a last tag, and the at least one image frame also has a first line tag on its first line and a second line tag on its last line; validation logic configured to check and verify that tag information included in the feature data has a correct format; a plurality of multiply-accumulate, MAC, units arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer; and at least one input bus (602, 604, 606) coupled to an output bus port of the plurality of output bus ports of the stream switch; at least one output bus coupled to an input bus port of the plurality of input bus ports of the stream switch; or at least one input bus (602, 604, 606) and at least one output bus hard wired to respective output bus and input bus ports of the stream switch. a kernel buffer; a feature line buffer; wherein the feature line buffer is configured to receive and store a plurality of lines of feature data arranged as at least one image frame, wherein each line of feature data has a first tag and a last tag, and the at least one image frame also has a first line tag on its first line and a second line tag on its last line; validation logic configured to check and verify that tag information included in the feature data has a correct format; a plurality of multiply-accumulate, MAC, units arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer; and at least one input bus (602, 604, 606) coupled to an output bus port of the plurality of output bus ports of the stream switch; at least one output bus coupled to an input bus port of the plurality of input bus ports of the stream switch; or at least one input bus (602, 604, 606) and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.