An amplifier comprising: an input stage comprising a first NMOS transistor for receiving a first input signal (V in) inputted into the gate of the first NMOS transistor, and a second NMOS transistor for receiving the second input signal (V ip) inputted into the gate of the second NMOS transistor; a load stage (24, 32) coupled between the input stage and a predetermined voltage (V dd), the load stage (24, 32) is an active load of electrically coupled in cascade transistors (M31, M41, M51, M61, M71, M81) comprising a plurality of electrically coupled third transistors (M31, M51, M71) coupled to the first NMOS transistor of the input stage for generating the first output signal (V op) and a plurality of electrically coupled fourth transistors (M41, M61, M81) coupled to the second NMOS transistor of the input stage for generating the second output signal (V on), a first current source coupled to the input stage for allowing a predetermined current I Q to flow; a second current source (26, 28) coupled to the first NMOS transistor of the input stage and the predetermined voltage (V dd), wherein the second current source (26, 28) is adapted to inject a first current into the input stage, a third current source (26, 28) coupled to the second NMOS transistor of the input stage and the predetermined voltage (V dd), the third current source (26, 28) is adapted to inject a second current into the input stage, wherein the second and third current sources (26, 28) are coupled in parallel to the load stage (24, 32) between the predetermined voltage (V dd) and the input stage, wherein the input stage, the load stage (24, 32), and the first current source are configured in a telescopic topology, wherein the second current source (26, 28) is a p-type current source comprising a first series of electrically connected transistors (M72; M52; M32), a drain of one transistor of said series being directly coupled to the drain of the first NMOS transistor of the input stage for injecting the first current into the drain of the first NMOS transistor, and wherein the third current source (26, 28) is a p-type current source comprising a series of electrically connected transistors (M82; M62; M42), a drain of one transistor of said series being directly coupled to the drain of the second NMOS transistor of the input stage for injecting the second current into the drain of the second NMOS transistor, so that transistors (M71, M81) of the load stage (24, 32) have a reduced size and reduced parasitic capacitance for achieving an increased unity-gain bandwidth for the amplifier. an input stage comprising a first NMOS transistor for receiving a first input signal (V in) inputted into the gate of the first NMOS transistor, and a second NMOS transistor for receiving the second input signal (V ip) inputted into the gate of the second NMOS transistor; a load stage (24, 32) coupled between the input stage and a predetermined voltage (V dd), the load stage (24, 32) is an active load of electrically coupled in cascade transistors (M31, M41, M51, M61, M71, M81) comprising a plurality of electrically coupled third transistors (M31, M51, M71) coupled to the first NMOS transistor of the input stage for generating the first output signal (V op) and a plurality of electrically coupled fourth transistors (M41, M61, M81) coupled to the second NMOS transistor of the input stage for generating the second output signal (V on), a first current source coupled to the input stage for allowing a predetermined current I Q to flow; a second current source (26, 28) coupled to the first NMOS transistor of the input stage and the predetermined voltage (V dd), wherein the second current source (26, 28) is adapted to inject a first current into the input stage, a third current source (26, 28) coupled to the second NMOS transistor of the input stage and the predetermined voltage (V dd), the third current source (26, 28) is adapted to inject a second current into the input stage, wherein the second and third current sources (26, 28) are coupled in parallel to the load stage (24, 32) between the predetermined voltage (V dd) and the input stage, wherein the input stage, the load stage (24, 32), and the first current source are configured in a telescopic topology, wherein the second current source (26, 28) is a p-type current source comprising a first series of electrically connected transistors (M72; M52; M32), a drain of one transistor of said series being directly coupled to the drain of the first NMOS transistor of the input stage for injecting the first current into the drain of the first NMOS transistor, and wherein the third current source (26, 28) is a p-type current source comprising a series of electrically connected transistors (M82; M62; M42), a drain of one transistor of said series being directly coupled to the drain of the second NMOS transistor of the input stage for injecting the second current into the drain of the second NMOS transistor, so that transistors (M71, M81) of the load stage (24, 32) have a reduced size and reduced parasitic capacitance for achieving an increased unity-gain bandwidth for the amplifier.