An apparatus comprising: a plurality of matrix processing chips (220a,..., 220d) integrated on a package and configured in a cyclical arrangement, each matrix processing chip (220a,..., 220d) to process matrix instructions; inter-chip links, ICLs, to connect two or more of the plurality of matrix processing chips (220a,..., 220d), the ICLs to enable bi-directional communication between neighboring ones of the two or more matrix processing chips of the plurality of matrix processing chips (220a,..., 220d); a plurality of high bandwidth memory, HBM, modules (240a,...240d), an HBM module (240a,...240d) of the plurality of HBM modules (240a,...240d) to store matrix data for processing by a matrix processing chip of the plurality of matrix processing chips (220a,..., 220d); each of the plurality of matrix processing chips (220a,..., 220d) comprising: a host interface to couple the respective matrix processing chip to a host processor, a controller to control and/or manage matrix operations of a programmed matrix routine comprising a series of instructions and/or commands supported by the respective matrix processing chip, a plurality of programmable matrix processing units coupled to the controller configured to perform a matrix multiplication operation based on a matrix multiplication instruction from the programmed matrix routine, the matrix multiplication instruction specifying matrix operands, including a first input matrix, A, and a second input matrix, B, the matrix processing units to produce an output matrix, C, by multiplying the first input matrix, A, and the second input matrix, B, and a slicing engine configured to slice the matrix operands of particular matrix operations into smaller partial matrices, the slicing engine comprising a convolution slicing engine, CSE, which slices matrix operands in a manner that enables a convolution operation to be cast as the matrix multiplication operation comprising to perform dimension shuffle operations to reorder the dimensions of the matrix operands. a plurality of matrix processing chips (220a,..., 220d) integrated on a package and configured in a cyclical arrangement, each matrix processing chip (220a,..., 220d) to process matrix instructions; inter-chip links, ICLs, to connect two or more of the plurality of matrix processing chips (220a,..., 220d), the ICLs to enable bi-directional communication between neighboring ones of the two or more matrix processing chips of the plurality of matrix processing chips (220a,..., 220d); a plurality of high bandwidth memory, HBM, modules (240a,...240d), an HBM module (240a,...240d) of the plurality of HBM modules (240a,...240d) to store matrix data for processing by a matrix processing chip of the plurality of matrix processing chips (220a,..., 220d); each of the plurality of matrix processing chips (220a,..., 220d) comprising: a host interface to couple the respective matrix processing chip to a host processor, a controller to control and/or manage matrix operations of a programmed matrix routine comprising a series of instructions and/or commands supported by the respective matrix processing chip, a plurality of programmable matrix processing units coupled to the controller configured to perform a matrix multiplication operation based on a matrix multiplication instruction from the programmed matrix routine, the matrix multiplication instruction specifying matrix operands, including a first input matrix, A, and a second input matrix, B, the matrix processing units to produce an output matrix, C, by multiplying the first input matrix, A, and the second input matrix, B, and a slicing engine configured to slice the matrix operands of particular matrix operations into smaller partial matrices, the slicing engine comprising a convolution slicing engine, CSE, which slices matrix operands in a manner that enables a convolution operation to be cast as the matrix multiplication operation comprising to perform dimension shuffle operations to reorder the dimensions of the matrix operands. a host interface to couple the respective matrix processing chip to a host processor, a controller to control and/or manage matrix operations of a programmed matrix routine comprising a series of instructions and/or commands supported by the respective matrix processing chip, a plurality of programmable matrix processing units coupled to the controller configured to perform a matrix multiplication operation based on a matrix multiplication instruction from the programmed matrix routine, the matrix multiplication instruction specifying matrix operands, including a first input matrix, A, and a second input matrix, B, the matrix processing units to produce an output matrix, C, by multiplying the first input matrix, A, and the second input matrix, B, and a slicing engine configured to slice the matrix operands of particular matrix operations into smaller partial matrices, the slicing engine comprising a convolution slicing engine, CSE, which slices matrix operands in a manner that enables a convolution operation to be cast as the matrix multiplication operation comprising to perform dimension shuffle operations to reorder the dimensions of the matrix operands.