A voltage clamp circuit (10; 50; 100) comprising: a first (14; 54; 104) and a second (14; 56; 106) comparator loop circuits, each comprising: a comparator (16; 58; 62; 108; 112) configured to compare an input voltage (V IN) provided at an input node (12; 52; 102) with a corresponding clamping voltage (V CL; V CH) and a transistor network (N 1, P 1, P 2; N 2, N 3, P 3) interconnecting a corresponding voltage rail (V DD; Ground) and the input node (12; 52; 102), the comparato (16; 58; 62; 108; 112) being configured to activate the transistor network (N 1, P 2, P 2; N 2, N 3, P 3) to set the input voltage (V IN) to be approximately equal to the corresponding clamping voltage (V CL; V CH) in response to the input voltage (V IN) exceeding the corresponding clamping voltage (V CL; V CH); wherein the comparator (16; 58; 62; 108; 112) comprises: a first pair of transistors (N 4, N 5; P 6, P 7) comprising common-coupled control terminals corresponding to an output (CL1; CL2) of the comparator (16; 58; 62; 108; 112); wherein one of (N 4; P 6) the first pair of transistors (N 4, N 5; P 6, P 7) comprises a terminal coupled to the input node (12; 52; 102) and the other (N 5; P 7) of the first pair of transistors (N 4, N 5; P 6, P 7) comprises a terminal coupled to the corresponding clamping voltage (V CL; V CH); and a second pair of transistors (P 4, P 5; N 6, N 7) arranged as a current-mirror controlled by a static current source (110; 114), wherein each of the second pair of transistors (P 4, P 5; N 6, N 7) comprises a first terminal coupled to the corresponding voltage rail (V DD; Ground) and a second terminal coupled to a second terminal of a respective one of the first pair of transistors (N 4, N 5; P 6, P 7); wherein the corresponding clamping voltages of the first (14; 54; 104) and second (14; 56; 106) comparator loop circuits comprise a low clamping voltage (V CL) and a high clamping voltage (V CH); wherein the comparator (16; 58; 108) of the first comparator loop circuit (14; 54; 106) is configured to compare the input voltage (V IN) with the low clamping voltage (V CL) and to assert its output in response to the input voltage (V IN) decreasing less than the low clamping voltage (V CL); and wherein the comparator (16; 62; 112) of the second comparator loop circuit (14; 56; 106) is configured to compare the input voltage (V IN) with the high clamping voltage (V CH) and to assert its output in response to the input voltage (V IN) increasing greater than the high clamping voltage (V CH). a comparator (16; 58; 62; 108; 112) configured to compare an input voltage (V IN) provided at an input node (12; 52; 102) with a corresponding clamping voltage (V CL; V CH) and a transistor network (N 1, P 1, P 2; N 2, N 3, P 3) interconnecting a corresponding voltage rail (V DD; Ground) and the input node (12; 52; 102), the comparato (16; 58; 62; 108; 112) being configured to activate the transistor network (N 1, P 2, P 2; N 2, N 3, P 3) to set the input voltage (V IN) to be approximately equal to the corresponding clamping voltage (V CL; V CH) in response to the input voltage (V IN) exceeding the corresponding clamping voltage (V CL; V CH); a first pair of transistors (N 4, N 5; P 6, P 7) comprising common-coupled control terminals corresponding to an output (CL1; CL2) of the comparator (16; 58; 62; 108; 112); wherein one of (N 4; P 6) the first pair of transistors (N 4, N 5; P 6, P 7) comprises a terminal coupled to the input node (12; 52; 102) and the other (N 5; P 7) of the first pair of transistors (N 4, N 5; P 6, P 7) comprises a terminal coupled to the corresponding clamping voltage (V CL; V CH); and a second pair of transistors (P 4, P 5; N 6, N 7) arranged as a current-mirror controlled by a static current source (110; 114), wherein each of the second pair of transistors (P 4, P 5; N 6, N 7) comprises a first terminal coupled to the corresponding voltage rail (V DD; Ground) and a second terminal coupled to a second terminal of a respective one of the first pair of transistors (N 4, N 5; P 6, P 7); wherein the corresponding clamping voltages of the first (14; 54; 104) and second (14; 56; 106) comparator loop circuits comprise a low clamping voltage (V CL) and a high clamping voltage (V CH); wherein the comparator (16; 58; 108) of the first comparator loop circuit (14; 54; 106) is configured to compare the input voltage (V IN) with the low clamping voltage (V CL) and to assert its output in response to the input voltage (V IN) decreasing less than the low clamping voltage (V CL); and wherein the comparator (16; 62; 112) of the second comparator loop circuit (14; 56; 106) is configured to compare the input voltage (V IN) with the high clamping voltage (V CH) and to assert its output in response to the input voltage (V IN) increasing greater than the high clamping voltage (V CH).