A sensing circuit comprising: a first path (180, 280) comprising the first resistive memory device, wherein the first path (180, 280) is coupled to a first split path (140,240) comprising a first clamping transistor (124, 224) and a first load transistor (150, 250) and to a second split path (142, 242) comprising a second clamping transistor (126, 226) and a second load transistor (154, 254); and a second path (182, 282) comprising a reference resistive memory device, wherein the second path (182, 282) is coupled to a third split path comprising a third clamping transistor and a third load transistor (156, 256) and to a fourth split path comprising a fourth clamping transistor (128, 228) and a fourth load transistor (152, 252), wherein the first load transistor (150, 250) is coupled to the fourth load transistor (152, 252) via a first common gate bias and the second load transistor (154, 254) is coupled to the third load transistor (156, 256) via a second common gate bias, the common gate of the first and fourth load transistors being connected to a node between the first load and clamp transistors and the common gate of the second and third load transistors being connected to a node between the third load and clamp transistors, wherein the second load transistor (154, 254) is coupled to a data node (160, 260) that in turn is coupled to the second clamping transistor (126, 226) and the fourth load transistor (152, 252) is coupled to a reference node (162, 262) that in turn is coupled to the fourth clamping transistor (128, 228), wherein characteristics of the load transistors are such that the voltage difference between the data node (160, 260) and the reference node (162, 262) when the first resistive memory device is in logic state 1 is balanced with the voltage difference between the reference node (162,262) and the data node (160, 260) when the first resistive memory device is in logic state 0, and the sensing circuit being characterized in that the characteristic of the second load transistor is different from the corresponding characteristic of the fourth load transistor or the characteristic of the first load transistor is different from the corresponding characteristic of the third load transistor. a first path (180, 280) comprising the first resistive memory device, wherein the first path (180, 280) is coupled to a first split path (140,240) comprising a first clamping transistor (124, 224) and a first load transistor (150, 250) and to a second split path (142, 242) comprising a second clamping transistor (126, 226) and a second load transistor (154, 254); and a second path (182, 282) comprising a reference resistive memory device, wherein the second path (182, 282) is coupled to a third split path comprising a third clamping transistor and a third load transistor (156, 256) and to a fourth split path comprising a fourth clamping transistor (128, 228) and a fourth load transistor (152, 252), wherein the first load transistor (150, 250) is coupled to the fourth load transistor (152, 252) via a first common gate bias and the second load transistor (154, 254) is coupled to the third load transistor (156, 256) via a second common gate bias, the common gate of the first and fourth load transistors being connected to a node between the first load and clamp transistors and the common gate of the second and third load transistors being connected to a node between the third load and clamp transistors, wherein the second load transistor (154, 254) is coupled to a data node (160, 260) that in turn is coupled to the second clamping transistor (126, 226) and the fourth load transistor (152, 252) is coupled to a reference node (162, 262) that in turn is coupled to the fourth clamping transistor (128, 228), wherein characteristics of the load transistors are such that the voltage difference between the data node (160, 260) and the reference node (162, 262) when the first resistive memory device is in logic state 1 is balanced with the voltage difference between the reference node (162,262) and the data node (160, 260) when the first resistive memory device is in logic state 0, and the sensing circuit being characterized in that the characteristic of the second load transistor is different from the corresponding characteristic of the fourth load transistor or the characteristic of the first load transistor is different from the corresponding characteristic of the third load transistor.