A fractional divider system (505, 300), comprising: a plurality of input nodes to receive a dividing value signal, a shift input signal, and a data signal, the dividing value signal indicating a base dividing value having a base integer component and a base fractional component; a fractional shifting modulator coupled with at least some of the plurality of input nodes to generate a shifted fractional component value as a function of the base fractional component, the data signal, and a shift value set by the shift input signal, wherein the shifted fractional component value represents the base fractional component, as modulated by the data signal, and as shifted by the shift value, and the shift input signal is applied to shift the base fractional component of the dividing value signal away from an N-boundary; a fractionalizer coupled with the fractional shifting modulator to generate a first stream of integers responsive to receiving the shifted fractional component value, such that the first stream of integers time-averages to the shifted fractional component value; an integer de-shifter coupled with the fractionalizer to generate a second stream of integers by de-shifting a sum of the first stream of integers and the base integer component, such that the second stream of integers time-averages to a modulated dividing value, the modulated dividing value corresponding to the base dividing value as modulated by the data signal; and a divider coupled with the integer de-shifter to generate a feedback signal as a function of sequentially dividing a frequency of a clock output signal by the second stream of integers. a plurality of input nodes to receive a dividing value signal, a shift input signal, and a data signal, the dividing value signal indicating a base dividing value having a base integer component and a base fractional component; a fractional shifting modulator coupled with at least some of the plurality of input nodes to generate a shifted fractional component value as a function of the base fractional component, the data signal, and a shift value set by the shift input signal, wherein the shifted fractional component value represents the base fractional component, as modulated by the data signal, and as shifted by the shift value, and the shift input signal is applied to shift the base fractional component of the dividing value signal away from an N-boundary; a fractionalizer coupled with the fractional shifting modulator to generate a first stream of integers responsive to receiving the shifted fractional component value, such that the first stream of integers time-averages to the shifted fractional component value; an integer de-shifter coupled with the fractionalizer to generate a second stream of integers by de-shifting a sum of the first stream of integers and the base integer component, such that the second stream of integers time-averages to a modulated dividing value, the modulated dividing value corresponding to the base dividing value as modulated by the data signal; and a divider coupled with the integer de-shifter to generate a feedback signal as a function of sequentially dividing a frequency of a clock output signal by the second stream of integers.