A method for data transmission on a data bus system, comprising - a reference potential line, and - a single-wire data bus (b1, b2, b3) having a single signal line for transmitting data between a bus master and between at least two bus nodes (BS1, BS2, BS3), - wherein the single-wire data bus (b1, b2, b3) is divided by the bus nodes (BS1, BS2, BS3) into at least two single wire data bus sections (b1, b2, b3) and is terminated by a bus node, the terminating bus node, and - wherein each of the bus nodes (BS1, BS2, BS3), except for a first bus node, is connected by a preceding single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3), and the one first bus node is connected by a preceding single-wire data bus section of the single-wire data bus sections (b1, b2, b3) to the bus master, and - wherein each bus node (BS1, BS2, BS3), except for a terminated bus node, is connected by a subsequent single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a subsequent bus node (BS2, BS3) of the bus nodes (BS1, BS2, BS3), characterized by - bidirectionally transmitting and receiving data via the single-wire data bus (b1, b2, b3) or at least one single-wire data bus section (b1, b2, b3) of the single-wire data bus sections (b1, b2, b3), in the following referred to as the considered single-wire data bus section (b1, b2, b3), by a master single-wire data bus interface of the bus master with the aid of a data bus protocol with more than two physical voltage and/or current levels; - receiving data from the considered single-wire data bus section (b1, b2, b3) by a single-wire data bus interface (OWS1, OWS2, OWS3) of a considered bus node of the bus nodes (BS1, BS2, BS3) with the aid of a data bus protocol with more than two physical voltage and/or current levels; - transmitting data via the considered single-wire data bus section (b1, b2, b3) by the single-wire data bus interface (OWS1, OWS2, OWS3) of a considered bus node of the bus nodes (BS1, BS2, BS3) with the aid of a data bus protocol with more than two physical voltage and/or current levels; - bidirectionally transmitting and receiving data via at least one subsequent single-wire data bus section (b2, b3) of the single-wire data bus sections (b2, b3) by a master single-wire data bus interface (OWM1, OWM2, OWM3) of the considered bus nodes with the aid of a data bus protocol with more than two physical voltage and/or current levels to a subsequent bus node (BS2, BS3); - controlling the master single-wire data bus interface (OWM1, OWM2, OWM3) of the considered bus node via a bus master control register (OWMCR) of the considered bus node being adapted to be writable by the bus master via the single-wire data bus (b1, b2, b3). - a reference potential line, and - a single-wire data bus (b1, b2, b3) having a single signal line for transmitting data between a bus master and between at least two bus nodes (BS1, BS2, BS3), - wherein the single-wire data bus (b1, b2, b3) is divided by the bus nodes (BS1, BS2, BS3) into at least two single wire data bus sections (b1, b2, b3) and is terminated by a bus node, the terminating bus node, and - wherein each of the bus nodes (BS1, BS2, BS3), except for a first bus node, is connected by a preceding single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3), and the one first bus node is connected by a preceding single-wire data bus section of the single-wire data bus sections (b1, b2, b3) to the bus master, and - wherein each bus node (BS1, BS2, BS3), except for a terminated bus node, is connected by a subsequent single-wire data bus section (b2, b3) of the single-wire data bus sections (b1, b2, b3) to a subsequent bus node (BS2, BS3) of the bus nodes (BS1, BS2, BS3), - bidirectionally transmitting and receiving data via the single-wire data bus (b1, b2, b3) or at least one single-wire data bus section (b1, b2, b3) of the single-wire data bus sections (b1, b2, b3), in the following referred to as the considered single-wire data bus section (b1, b2, b3), by a master single-wire data bus interface of the bus master with the aid of a data bus protocol with more than two physical voltage and/or current levels; - receiving data from the considered single-wire data bus section (b1, b2, b3) by a single-wire data bus interface (OWS1, OWS2, OWS3) of a considered bus node of the bus nodes (BS1, BS2, BS3) with the aid of a data bus protocol with more than two physical voltage and/or current levels; - transmitting data via the considered single-wire data bus section (b1, b2, b3) by the single-wire data bus interface (OWS1, OWS2, OWS3) of a considered bus node of the bus nodes (BS1, BS2, BS3) with the aid of a data bus protocol with more than two physical voltage and/or current levels; - bidirectionally transmitting and receiving data via at least one subsequent single-wire data bus section (b2, b3) of the single-wire data bus sections (b2, b3) by a master single-wire data bus interface (OWM1, OWM2, OWM3) of the considered bus nodes with the aid of a data bus protocol with more than two physical voltage and/or current levels to a subsequent bus node (BS2, BS3); - controlling the master single-wire data bus interface (OWM1, OWM2, OWM3) of the considered bus node via a bus master control register (OWMCR) of the considered bus node being adapted to be writable by the bus master via the single-wire data bus (b1, b2, b3).