A parallel processing device, comprising: a first processing execution unit configured to execute a command; a first address management unit configured to instruct the first processing execution unit to execute a command; a second processing execution unit configured to execute a command different from the command that the first processing execution unit executes, in parallel with the execution by the first processing execution unit; a second address management unit configured to instruct the second processing execution unit to execute a command; a sequence command storage memory configured to store a sequence command in each address, wherein a sequence command for the first processing execution unit is different from a sequence command for the second processing execution unit, and configured to store together with the sequence command for a first address a command for parallel processing start in a manner to correspond to a parallel processing start bit, and configured to store together with the sequence command for a second address a command for parallel processing completion in a manner to correspond to a parallel processing completion bit; and a processing sequence management unit configured to control the sequence command storage memory so that the sequence command storage memory outputs the sequence commands from the first address, including the command corresponding to the parallel processing start bit, to the second address, including the command corresponding to the parallel processing completion bit, in sequence to both the first address management unit and the second address management unit, wherein the first address management unit, when referring to the sequence commands outputted from the sequence command storage memory in order from the first address, is configured to find a command that is to be executed by the first processing execution unit, and to instruct the first processing execution unit to execute the found command, and the second address management unit, when referring to the sequence commands outputted from the sequence command storage memory in order from the first address, is configured to find a command that is to be executed by the second processing execution unit, and to instruct the second processing execution unit to execute the found command. a first processing execution unit configured to execute a command; a first address management unit configured to instruct the first processing execution unit to execute a command; a second processing execution unit configured to execute a command different from the command that the first processing execution unit executes, in parallel with the execution by the first processing execution unit; a second address management unit configured to instruct the second processing execution unit to execute a command; a sequence command storage memory configured to store a sequence command in each address, wherein a sequence command for the first processing execution unit is different from a sequence command for the second processing execution unit, and configured to store together with the sequence command for a first address a command for parallel processing start in a manner to correspond to a parallel processing start bit, and configured to store together with the sequence command for a second address a command for parallel processing completion in a manner to correspond to a parallel processing completion bit; and a processing sequence management unit configured to control the sequence command storage memory so that the sequence command storage memory outputs the sequence commands from the first address, including the command corresponding to the parallel processing start bit, to the second address, including the command corresponding to the parallel processing completion bit, in sequence to both the first address management unit and the second address management unit, wherein the first address management unit, when referring to the sequence commands outputted from the sequence command storage memory in order from the first address, is configured to find a command that is to be executed by the first processing execution unit, and to instruct the first processing execution unit to execute the found command, and the second address management unit, when referring to the sequence commands outputted from the sequence command storage memory in order from the first address, is configured to find a command that is to be executed by the second processing execution unit, and to instruct the second processing execution unit to execute the found command.