A semiconductor package assembly, comprising: a substrate having a first pad and a second pad thereon; a logic die (100a, 100b) mounted on the substrate, wherein a logic die (100a, 100b) is one of a logic die comprising a logic die pad coupled to the second pad only through a bond wire and a logic die which is flip-chip mounted on the substrate and which comprises a logic die pad coupled to the second pad through a conductive bump structure and an interconnect in the substrate; and a memory die stacked and mounted on the first logic die (100a, 100b), wherein the memory die comprises: a memory I/O die pad and a redistribution layer, RDL, structure, including a first RDL trace on the memory I/O die pad, and a first memory die pad on the first RDL trace; the first RDL trace having a first terminal close to a first side of the memory die and a second terminal close to a second side of the memory die, wherein the first terminal is coupled to the first pad through a first wire bond and through the first memory die pad, and wherein the second terminal is coupled to the second pad through a second wire bond without using the first memory die pad and the first pad; wherein the first memory die pad and the first pad are both disposed close to the first side of the memory die; wherein the first logic die pad (150a, 150b) and the second pad are disposed close to the second side of the memory die, wherein the first side is different from the second side; and wherein the RDL trace is a ground trace and the first pad and the second pad are discrete ground pads; wherein the RDL structure further comprises a second RDL trace close to and parallel to the first RDL trace and a second memory die pad coupled to a first terminal of the second RDL trace for input/output connections to signals of a second memory I/O die pad, wherein the second RDL trace extends between the first and second sides (220, 222) of the memory die, wherein the RDL trace is disposed at a single layered level. a substrate having a first pad and a second pad thereon; a logic die (100a, 100b) mounted on the substrate, wherein a logic die (100a, 100b) is one of a logic die comprising a logic die pad coupled to the second pad only through a bond wire and a logic die which is flip-chip mounted on the substrate and which comprises a logic die pad coupled to the second pad through a conductive bump structure and an interconnect in the substrate; and a memory die stacked and mounted on the first logic die (100a, 100b), wherein the memory die comprises: a memory I/O die pad and a redistribution layer, RDL, structure, including a first RDL trace on the memory I/O die pad, and a first memory die pad on the first RDL trace; the first RDL trace having a first terminal close to a first side of the memory die and a second terminal close to a second side of the memory die, wherein the first terminal is coupled to the first pad through a first wire bond and through the first memory die pad, and wherein the second terminal is coupled to the second pad through a second wire bond without using the first memory die pad and the first pad; wherein the first memory die pad and the first pad are both disposed close to the first side of the memory die; wherein the first logic die pad (150a, 150b) and the second pad are disposed close to the second side of the memory die, wherein the first side is different from the second side; and wherein the RDL trace is a ground trace and the first pad and the second pad are discrete ground pads; wherein the RDL structure further comprises a second RDL trace close to and parallel to the first RDL trace and a second memory die pad coupled to a first terminal of the second RDL trace for input/output connections to signals of a second memory I/O die pad, wherein the second RDL trace extends between the first and second sides (220, 222) of the memory die, wherein the RDL trace is disposed at a single layered level. a memory I/O die pad and a redistribution layer, RDL, structure, including a first RDL trace on the memory I/O die pad, and a first memory die pad on the first RDL trace; the first RDL trace having a first terminal close to a first side of the memory die and a second terminal close to a second side of the memory die, wherein the first terminal is coupled to the first pad through a first wire bond and through the first memory die pad, and wherein the second terminal is coupled to the second pad through a second wire bond without using the first memory die pad and the first pad; wherein the first memory die pad and the first pad are both disposed close to the first side of the memory die; wherein the first logic die pad (150a, 150b) and the second pad are disposed close to the second side of the memory die, wherein the first side is different from the second side; and wherein the RDL trace is a ground trace and the first pad and the second pad are discrete ground pads; wherein the RDL structure further comprises a second RDL trace close to and parallel to the first RDL trace and a second memory die pad coupled to a first terminal of the second RDL trace for input/output connections to signals of a second memory I/O die pad, wherein the second RDL trace extends between the first and second sides (220, 222) of the memory die, wherein the RDL trace is disposed at a single layered level.