A regulator (100, 200) comprising - a first amplification stage configured to provide a stage output voltage at a stage output node; wherein the first amplification stage comprises a differential amplification stage configured to provide the stage output voltage at the stage output node, based on a first input voltage at a first stage input node and a second input voltage at a second stage input node; - an intermediate amplification stage comprising - an amplifier current source configured to provide an amplifier current; and - an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the stage output node of the first amplification stage; wherein the intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor; wherein a drain of the amplifier transistor is coupled to the midpoint; - a gain control circuit configured to reduce an effective output impedance of the amplifier transistor by providing a current feedback to the midpoint; wherein the gain control circuit comprises a control transistor; wherein a gate of the control transistor is coupled to the stage output node of the first amplification stage; wherein a source of the control transistor is coupled to a source of the amplifier transistor; wherein the gain control circuit comprises current mapping means (302, 303) configured to map a current at a drain of the control transistor to the midpoint; wherein the current mapping means (302, 303) comprise a current mirror; - an output amplification stage configured to provide a load current at an amplifier output voltage to a load; wherein an input of the output amplification stage is coupled to an output of the intermediate amplification stage; and - voltage sensing means configured to provide an indication of the amplifier output voltage; wherein the indication of the amplifier output voltage is fed back as the first input voltage to the first stage input node of the first amplification stage. - a first amplification stage configured to provide a stage output voltage at a stage output node; wherein the first amplification stage comprises a differential amplification stage configured to provide the stage output voltage at the stage output node, based on a first input voltage at a first stage input node and a second input voltage at a second stage input node; - an intermediate amplification stage comprising - an amplifier current source configured to provide an amplifier current; and - an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the stage output node of the first amplification stage; wherein the intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor; wherein a drain of the amplifier transistor is coupled to the midpoint; - an amplifier current source configured to provide an amplifier current; and - an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the stage output node of the first amplification stage; wherein the intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor; wherein a drain of the amplifier transistor is coupled to the midpoint; - a gain control circuit configured to reduce an effective output impedance of the amplifier transistor by providing a current feedback to the midpoint; wherein the gain control circuit comprises a control transistor; wherein a gate of the control transistor is coupled to the stage output node of the first amplification stage; wherein a source of the control transistor is coupled to a source of the amplifier transistor; wherein the gain control circuit comprises current mapping means (302, 303) configured to map a current at a drain of the control transistor to the midpoint; wherein the current mapping means (302, 303) comprise a current mirror; - an output amplification stage configured to provide a load current at an amplifier output voltage to a load; wherein an input of the output amplification stage is coupled to an output of the intermediate amplification stage; and - voltage sensing means configured to provide an indication of the amplifier output voltage; wherein the indication of the amplifier output voltage is fed back as the first input voltage to the first stage input node of the first amplification stage.