A circuit comprising: an autonomous ferroelectric memory latch, AML (176', 54, 92), having an autonomous memory circuit and a feedback loop, wherein the autonomous memory circuit includes a ferroelectric capacitor, a conductive load and a switch having a current actuated control input that connects an output node to a first power rail, the conductive load connecting a second power rail to the output node, the ferroelectric capacitor being connected between the switch control input and the output node, said AML comprising an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state wherein the feedback loop comprises: a first power contact coupled to the first power rail, a second power contact coupled to the second power rail, a feedback control input node coupled to the output node and a feedback output node coupled to the current actuated control input, the AML input is coupled to the current actuated control input, the AML output is directly coupled to the output node, the first AML power contact is directly coupled to the first power rail, and the second AML power contact is directly coupled to the second power rail; characterised by: a first switch (178, 58, 95) in series with one of said AML input or said AML output; a second switch (177, 57, 94) in series with the other of said AML input or said AML output; a latch (179, 52, 93) in series with said AML input or said AML output, said latch being positioned such that a direct path does not exist between said AML output and said AML input; and a switch controller configured to open said first and second switches prior to power being removed from said first and second AML power contacts. an autonomous ferroelectric memory latch, AML (176', 54, 92), having an autonomous memory circuit and a feedback loop, wherein the autonomous memory circuit includes a ferroelectric capacitor, a conductive load and a switch having a current actuated control input that connects an output node to a first power rail, the conductive load connecting a second power rail to the output node, the ferroelectric capacitor being connected between the switch control input and the output node, said AML comprising an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state wherein the feedback loop comprises: a first power contact coupled to the first power rail, a second power contact coupled to the second power rail, a feedback control input node coupled to the output node and a feedback output node coupled to the current actuated control input, the AML input is coupled to the current actuated control input, the AML output is directly coupled to the output node, the first AML power contact is directly coupled to the first power rail, and the second AML power contact is directly coupled to the second power rail; characterised by: a first switch (178, 58, 95) in series with one of said AML input or said AML output; a second switch (177, 57, 94) in series with the other of said AML input or said AML output; a latch (179, 52, 93) in series with said AML input or said AML output, said latch being positioned such that a direct path does not exist between said AML output and said AML input; and a switch controller configured to open said first and second switches prior to power being removed from said first and second AML power contacts.