A system, comprising: a plurality of sequencers (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) each configured to provide a number of sequenced output signals (257-1, 257-2, 258-1, 258-2, 357-1, 357-2, 357-3, 358-1, 358-2, 358-3) responsive to assertion of a respective sequencer enable signal provided thereto; and chaining circuitry (152, 252, 352) coupled to the plurality of sequencers and comprising logic configured to: responsive to assertion of a primary enable signal (251, 351) received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; the system being characterised in that the logic is configured to responsive to deassertion of the primary enable signal, deassert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence, and in that the chaining circuitry comprises: a first logic gate (255-1, 255-2, 255-3, 256-1, 256-2, 256-3, 355-1, 355-2, 355-N-1, 356-1, 356-2, 356-3) configured to receive the primary enable signal as a first input and output a first sequencer enable signal to a first sequencer (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) of the plurality of sequencers; and a second logic gate (255-1, 255-2, 255-3, 256-1, 256-2, 256-3, 355-1, 355-2, 355-N-1, 356-1, 356-2, 356-3) configured to receive an output signal of the first sequencer as a first input and output a second sequencer enable signal to a second sequencer (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) of the plurality of sequencers. a plurality of sequencers (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) each configured to provide a number of sequenced output signals (257-1, 257-2, 258-1, 258-2, 357-1, 357-2, 357-3, 358-1, 358-2, 358-3) responsive to assertion of a respective sequencer enable signal provided thereto; and chaining circuitry (152, 252, 352) coupled to the plurality of sequencers and comprising logic configured to: responsive to assertion of a primary enable signal (251, 351) received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; the system being characterised in that the logic is configured to responsive to deassertion of the primary enable signal, deassert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence, and in that the chaining circuitry comprises: a first logic gate (255-1, 255-2, 255-3, 256-1, 256-2, 256-3, 355-1, 355-2, 355-N-1, 356-1, 356-2, 356-3) configured to receive the primary enable signal as a first input and output a first sequencer enable signal to a first sequencer (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) of the plurality of sequencers; and a second logic gate (255-1, 255-2, 255-3, 256-1, 256-2, 256-3, 355-1, 355-2, 355-N-1, 356-1, 356-2, 356-3) configured to receive an output signal of the first sequencer as a first input and output a second sequencer enable signal to a second sequencer (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) of the plurality of sequencers. responsive to assertion of a primary enable signal (251, 351) received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; the system being characterised in that the logic is configured to responsive to deassertion of the primary enable signal, deassert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence, and in that the chaining circuitry comprises: a first logic gate (255-1, 255-2, 255-3, 256-1, 256-2, 256-3, 355-1, 355-2, 355-N-1, 356-1, 356-2, 356-3) configured to receive the primary enable signal as a first input and output a first sequencer enable signal to a first sequencer (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) of the plurality of sequencers; and a second logic gate (255-1, 255-2, 255-3, 256-1, 256-2, 256-3, 355-1, 355-2, 355-N-1, 356-1, 356-2, 356-3) configured to receive an output signal of the first sequencer as a first input and output a second sequencer enable signal to a second sequencer (153, 253-1, 253-2, 253-3, 353-1, 353-2, 353-3, 353-N) of the plurality of sequencers.