A memory array, comprising: a plurality of memory columns, each memory column having a plurality of flash memory cells, the memory columns being divided into at least two blocks, wherein: at least one source pull down column is disposed between two adjacent blocks, and each source pull down column has a plurality of flash memory cells; a select gate of each flash memory cell in the source pull down column and select gates of corresponding flash memory cells of the plurality of memory columns in a same row are coupled to a same word line; a control gate of each flash memory cell in the source pull down column and control gates of corresponding flash memory cells of the plurality of memory columns in a same row are coupled to a same control gate line; an erasing gate of each flash memory cell in the source pull down column and erasing gates of corresponding flash memory cells of the plurality memory columns in a same row are coupled to a same erasing gate line; a source of each flash memory cell in the source pull down column is coupled to sources of corresponding flash memory cells of the plurality of memory columns in a same row; and a drain of each flash memory cell in the source pull down column is configured to receive a source pull down control signal. a plurality of memory columns, each memory column having a plurality of flash memory cells, the memory columns being divided into at least two blocks, wherein: at least one source pull down column is disposed between two adjacent blocks, and each source pull down column has a plurality of flash memory cells; a select gate of each flash memory cell in the source pull down column and select gates of corresponding flash memory cells of the plurality of memory columns in a same row are coupled to a same word line; a control gate of each flash memory cell in the source pull down column and control gates of corresponding flash memory cells of the plurality of memory columns in a same row are coupled to a same control gate line; an erasing gate of each flash memory cell in the source pull down column and erasing gates of corresponding flash memory cells of the plurality memory columns in a same row are coupled to a same erasing gate line; a source of each flash memory cell in the source pull down column is coupled to sources of corresponding flash memory cells of the plurality of memory columns in a same row; and a drain of each flash memory cell in the source pull down column is configured to receive a source pull down control signal. at least one source pull down column is disposed between two adjacent blocks, and each source pull down column has a plurality of flash memory cells; a select gate of each flash memory cell in the source pull down column and select gates of corresponding flash memory cells of the plurality of memory columns in a same row are coupled to a same word line; a control gate of each flash memory cell in the source pull down column and control gates of corresponding flash memory cells of the plurality of memory columns in a same row are coupled to a same control gate line; an erasing gate of each flash memory cell in the source pull down column and erasing gates of corresponding flash memory cells of the plurality memory columns in a same row are coupled to a same erasing gate line; a source of each flash memory cell in the source pull down column is coupled to sources of corresponding flash memory cells of the plurality of memory columns in a same row; and a drain of each flash memory cell in the source pull down column is configured to receive a source pull down control signal.