A data processing device configured to perform a DCT or iDCT computation, comprising: an operand storage circuit comprising at least one source register for storing operands and at least one result register for storing a result, each register being notionally subdivided into a plurality of segments at respective positions in the register, a functional unit for executing an instruction including an opcode and referring to one source register and to one result register in the operand storage circuit, said instruction causing the functional unit to execute at least two operations in parallel and independently of one another, each of the at least two operations adding or subtracting segments from the referred one source register, half of the operations are addition operations and half of the operations are subtraction operations, the segments having mutually different positions in the referred one source register, each of the one source register and the one result register comprises a first segment, a second segment, a third segment and a fourth segment, said at least two operations comprise summing numbers stored in the first segment of the one source register and the fourth segment of the one source register yielding a first result, summing numbers stored in the second segment of the one source register and the third segment of the one source register yielding a second result, subtracting the number stored in the third segment of the one source register from the number stored in the second segment of the one source register yielding a third result, subtracting the number stored in the fourth segment of the one source register from the number stored in the first segment of the one source register yielding a fourth result, and to store the first result in the first segment of the one result register, the second result in the second segment of the one result register, the third result in the third segment of the one result register and the fourth result in the fourth segment of the one result register. an operand storage circuit comprising at least one source register for storing operands and at least one result register for storing a result, each register being notionally subdivided into a plurality of segments at respective positions in the register, a functional unit for executing an instruction including an opcode and referring to one source register and to one result register in the operand storage circuit, said instruction causing the functional unit to execute at least two operations in parallel and independently of one another, each of the at least two operations adding or subtracting segments from the referred one source register, half of the operations are addition operations and half of the operations are subtraction operations, the segments having mutually different positions in the referred one source register, each of the one source register and the one result register comprises a first segment, a second segment, a third segment and a fourth segment, said at least two operations comprise summing numbers stored in the first segment of the one source register and the fourth segment of the one source register yielding a first result, summing numbers stored in the second segment of the one source register and the third segment of the one source register yielding a second result, subtracting the number stored in the third segment of the one source register from the number stored in the second segment of the one source register yielding a third result, subtracting the number stored in the fourth segment of the one source register from the number stored in the first segment of the one source register yielding a fourth result, summing numbers stored in the first segment of the one source register and the fourth segment of the one source register yielding a first result, summing numbers stored in the second segment of the one source register and the third segment of the one source register yielding a second result, subtracting the number stored in the third segment of the one source register from the number stored in the second segment of the one source register yielding a third result, subtracting the number stored in the fourth segment of the one source register from the number stored in the first segment of the one source register yielding a fourth result, and to store the first result in the first segment of the one result register, the second result in the second segment of the one result register, the third result in the third segment of the one result register and the fourth result in the fourth segment of the one result register.