An interleaved multiphase switching power converter comprising: a plurality of subconverters including: a first subconverter having a power switch; and a second subconverter having a power switch, the second subconverter phase shifted relative to the first subconverter; and a control circuit coupled to the first subconverter and the second subconverter for controlling the power switch of the first subconverter and the power switch of the second subconverter to balance currents in the first subconverter and the second subconverter over multiple periods, the control circuit including: a current compensator (112, 612) configured to: determine a first duty cycle multiple times over the multiple periods based on a first reference signal (Iref) and a sensed current (Isense) in the switching power converter; generate a first PWM control signal having a present value (u(t)) of the first duty cycle for controlling the power switch of the first subconverter during one period of the multiple periods; determine a second duty cycle based on the present value (u(t)) of the first duty cycle and a previous value (u(t-1)) of the first duty cycle; and generate a second PWM control signal having a present value (u(t)') of the second duty cycle for controlling the power switch of the second subconverter during the one period; wherein the control circuit is configured to generate an error signal (err) based on a comparison between the present value of the first duty cycle and the previous value of the first duty cycle for determining the second duty cycle; and characterized in that the control circuit is configured to determine the present value (u(t)') of the second duty cycle based on the equation: u t ′ = u t − u t − 1 * C 1 + u t, wherein u(t) - u(t-1) represents the error signal (err); wherein C1 represents a second reference signal; and wherein u(t)' represents the present value of the second duty cycle. a plurality of subconverters including: a first subconverter having a power switch; and a second subconverter having a power switch, the second subconverter phase shifted relative to the first subconverter; and a control circuit coupled to the first subconverter and the second subconverter for controlling the power switch of the first subconverter and the power switch of the second subconverter to balance currents in the first subconverter and the second subconverter over multiple periods, the control circuit including: a current compensator (112, 612) configured to: determine a first duty cycle multiple times over the multiple periods based on a first reference signal (Iref) and a sensed current (Isense) in the switching power converter; generate a first PWM control signal having a present value (u(t)) of the first duty cycle for controlling the power switch of the first subconverter during one period of the multiple periods; determine a second duty cycle based on the present value (u(t)) of the first duty cycle and a previous value (u(t-1)) of the first duty cycle; and generate a second PWM control signal having a present value (u(t)') of the second duty cycle for controlling the power switch of the second subconverter during the one period; determine a first duty cycle multiple times over the multiple periods based on a first reference signal (Iref) and a sensed current (Isense) in the switching power converter; generate a first PWM control signal having a present value (u(t)) of the first duty cycle for controlling the power switch of the first subconverter during one period of the multiple periods; determine a second duty cycle based on the present value (u(t)) of the first duty cycle and a previous value (u(t-1)) of the first duty cycle; and generate a second PWM control signal having a present value (u(t)') of the second duty cycle for controlling the power switch of the second subconverter during the one period; wherein the control circuit is configured to generate an error signal (err) based on a comparison between the present value of the first duty cycle and the previous value of the first duty cycle for determining the second duty cycle; and characterized in that the control circuit is configured to determine the present value (u(t)') of the second duty cycle based on the equation: u t ′ = u t − u t − 1 * C 1 + u t, wherein u(t) - u(t-1) represents the error signal (err); wherein C1 represents a second reference signal; and wherein u(t)' represents the present value of the second duty cycle. wherein u(t) - u(t-1) represents the error signal (err); wherein C1 represents a second reference signal; and wherein u(t)' represents the present value of the second duty cycle.