An apparatus, comprising: a central processing circuit, wherein the central processing circuit includes: a plurality of memory devices including a first group of memory devices (310a1) and a second group of memory devices (310a2), wherein the plurality of memory devices are grouped based on a timing criticality of each of the plurality of memory devices, wherein the first group of memory devices (310a1) includes memory devices that have a timing criticality of less than or equal to a timing threshold and the second group of memory devices (310a2) includes memory devices that have a timing criticality of greater than the timing threshold; a memory core, MX, voltage supply (VDD_MX) configured to provide the plurality of memory devices with an MX voltage; an application processor core, APC, voltage supply (VDD_APC) configured to provide the plurality of memory devices with an APC voltage; and a voltage switching circuit (310b1, 310b2) operated in accordance with the APC voltage and configured to: detect an operating mode of the central processing circuit, and switch a voltage provided to at least one of the first group of memory devices or the second group of memory devices (310a2) between the MX voltage and the APC voltage based on a type of the operating mode detected, wherein the voltage switching circuit (310b1, 310b2) is configured to switch the first group of memory devices (310a1) from the MX voltage to the APC voltage when the operating mode is faster than a nominal operating mode, wherein the operating mode faster than a nominal operating mode is slower than a turbo operating mode, wherein the voltage switching circuit (310b1, 310b2) is configured to switch the second group of memory devices (310a2) from the MX voltage to the APC voltage when the operating mode is at least the turbo operating mode. a central processing circuit, wherein the central processing circuit includes: a plurality of memory devices including a first group of memory devices (310a1) and a second group of memory devices (310a2), wherein the plurality of memory devices are grouped based on a timing criticality of each of the plurality of memory devices, wherein the first group of memory devices (310a1) includes memory devices that have a timing criticality of less than or equal to a timing threshold and the second group of memory devices (310a2) includes memory devices that have a timing criticality of greater than the timing threshold; a memory core, MX, voltage supply (VDD_MX) configured to provide the plurality of memory devices with an MX voltage; an application processor core, APC, voltage supply (VDD_APC) configured to provide the plurality of memory devices with an APC voltage; and a voltage switching circuit (310b1, 310b2) operated in accordance with the APC voltage and configured to: detect an operating mode of the central processing circuit, and switch a voltage provided to at least one of the first group of memory devices or the second group of memory devices (310a2) between the MX voltage and the APC voltage based on a type of the operating mode detected, a plurality of memory devices including a first group of memory devices (310a1) and a second group of memory devices (310a2), wherein the plurality of memory devices are grouped based on a timing criticality of each of the plurality of memory devices, wherein the first group of memory devices (310a1) includes memory devices that have a timing criticality of less than or equal to a timing threshold and the second group of memory devices (310a2) includes memory devices that have a timing criticality of greater than the timing threshold; a memory core, MX, voltage supply (VDD_MX) configured to provide the plurality of memory devices with an MX voltage; an application processor core, APC, voltage supply (VDD_APC) configured to provide the plurality of memory devices with an APC voltage; and a voltage switching circuit (310b1, 310b2) operated in accordance with the APC voltage and configured to: detect an operating mode of the central processing circuit, and switch a voltage provided to at least one of the first group of memory devices or the second group of memory devices (310a2) between the MX voltage and the APC voltage based on a type of the operating mode detected, detect an operating mode of the central processing circuit, and switch a voltage provided to at least one of the first group of memory devices or the second group of memory devices (310a2) between the MX voltage and the APC voltage based on a type of the operating mode detected, wherein the voltage switching circuit (310b1, 310b2) is configured to switch the first group of memory devices (310a1) from the MX voltage to the APC voltage when the operating mode is faster than a nominal operating mode, wherein the operating mode faster than a nominal operating mode is slower than a turbo operating mode, wherein the voltage switching circuit (310b1, 310b2) is configured to switch the second group of memory devices (310a2) from the MX voltage to the APC voltage when the operating mode is at least the turbo operating mode.