A device in a first node for wireless communication, characterized in that said device comprises: a first processor, to generate a first bit block and to perform channel coding; a first transmitter, to transmit a first radio signal; wherein bits in the first bit block are used to generate bits in a second bit block, a third bit block comprises the bits in the second bit block and the bits in the first bit block, the third bit block is used to generate the first radio signal; the first bit block and the second bit block comprise multiple second-type bits and P2 first-type bits, respectively, the third bit block comprise P3 binary bits, any one of the multiple second-type bits or the P2 first-type bits is a binary bit, the P2 is 24, and the P3 is a positive integer; the P3 is equal to a sum of a number of bits in the multiple second-type bits and the P2; the second bit block is used for CRC check of the first bit block; for an arbitrary bit of the first bit block, the arbitrary bit is used to determine at least one bit in the second bit block; the third bit block is used as an input to the channel coding, an output of the channel coding is used to generate the first radio signal, the channel coding is based on a polar code; among first-type bits associated with a first target bit and independent of a second target bit, a first bit is arranged foremost in the third bit block, among first-type bits associated with the second target bit and independent of the first target bit, a second bit is arranged foremost in the third bit block, the first bit is prior to the second bit, a position of the first target bit in the third bit block is prior to a position of the second target bit in the third bit block, and the first target bit and the second target bit are any two of the multiple second-type bits; at least two of the multiple second-type bits have front and rear positions in the first bit block opposite to front and rear positions in the third bit block; all of second-type bits associated with a given first-type bit are arranged prior to the given first-type bit in the third bit block, and the given first-type bit is any one bit of the P2 first-type bits; at least two bits of the second bit block are discontinuous in the third bit block, and at least two bits of the first bit block are discontinuous in the third bit block; the first node is a base station. a first processor, to generate a first bit block and to perform channel coding; a first transmitter, to transmit a first radio signal; wherein bits in the first bit block are used to generate bits in a second bit block, a third bit block comprises the bits in the second bit block and the bits in the first bit block, the third bit block is used to generate the first radio signal; the first bit block and the second bit block comprise multiple second-type bits and P2 first-type bits, respectively, the third bit block comprise P3 binary bits, any one of the multiple second-type bits or the P2 first-type bits is a binary bit, the P2 is 24, and the P3 is a positive integer; the P3 is equal to a sum of a number of bits in the multiple second-type bits and the P2; the second bit block is used for CRC check of the first bit block; for an arbitrary bit of the first bit block, the arbitrary bit is used to determine at least one bit in the second bit block; the third bit block is used as an input to the channel coding, an output of the channel coding is used to generate the first radio signal, the channel coding is based on a polar code; among first-type bits associated with a first target bit and independent of a second target bit, a first bit is arranged foremost in the third bit block, among first-type bits associated with the second target bit and independent of the first target bit, a second bit is arranged foremost in the third bit block, the first bit is prior to the second bit, a position of the first target bit in the third bit block is prior to a position of the second target bit in the third bit block, and the first target bit and the second target bit are any two of the multiple second-type bits; at least two of the multiple second-type bits have front and rear positions in the first bit block opposite to front and rear positions in the third bit block; all of second-type bits associated with a given first-type bit are arranged prior to the given first-type bit in the third bit block, and the given first-type bit is any one bit of the P2 first-type bits; at least two bits of the second bit block are discontinuous in the third bit block, and at least two bits of the first bit block are discontinuous in the third bit block; the first node is a base station.