An RF buffer circuit for coupling to an output of a voltage controlled oscillator, VCO, core circuit, the RF buffer circuit including two buffer circuit portions (102a, 102b), each buffer circuit portion comprising: means for detecting a high swing mode condition and a low swing mode condition at plural input terminals thereof; and means for responding to the detected swing mode condition by controlling the biasing voltage of the RF buffer circuit in order to phase align a voltage at an output terminal to a voltage at an input terminal of a first or a second transistor (M1, M2), wherein the means for responding include: a first switching circuit and a second switching circuit connected to the first transistor and to the second transistor, respectively, wherein the first switching circuit is connected to the source of the first transistor and the second switching circuit is connected to the source of the second transistor, wherein the first switching circuit is switched to a point of ground potential during a high swing mode condition and is switched to a first source of biasing potential during a low swing mode condition, wherein the second switching circuit is switched to the first source of biasing potential during a high swing mode condition and is switched to ground during a low swing mode condition, means for varying the biasing potential applied at the gates of the first and second transistors (M1, M2), respectively, wherein the means for varying comprise a first switch block (SWa') and a second switch block (SWb'), wherein the first switch block (SWa') is switched to ground during a high swing mode condition and is switched to half the voltage of the first source of bias potential during a low swing mode condition, wherein the second switch block (SWb') is switched to the voltage of the first source of bias potential during a high swing mode condition and is switched to half the voltage of the first source of bias potential during a low swing mode condition. means for detecting a high swing mode condition and a low swing mode condition at plural input terminals thereof; and means for responding to the detected swing mode condition by controlling the biasing voltage of the RF buffer circuit in order to phase align a voltage at an output terminal to a voltage at an input terminal of a first or a second transistor (M1, M2), wherein the means for responding include: a first switching circuit and a second switching circuit connected to the first transistor and to the second transistor, respectively, wherein the first switching circuit is connected to the source of the first transistor and the second switching circuit is connected to the source of the second transistor, wherein the first switching circuit is switched to a point of ground potential during a high swing mode condition and is switched to a first source of biasing potential during a low swing mode condition, wherein the second switching circuit is switched to the first source of biasing potential during a high swing mode condition and is switched to ground during a low swing mode condition, means for varying the biasing potential applied at the gates of the first and second transistors (M1, M2), respectively, wherein the means for varying comprise a first switch block (SWa') and a second switch block (SWb'), wherein the first switch block (SWa') is switched to ground during a high swing mode condition and is switched to half the voltage of the first source of bias potential during a low swing mode condition, wherein the second switch block (SWb') is switched to the voltage of the first source of bias potential during a high swing mode condition and is switched to half the voltage of the first source of bias potential during a low swing mode condition. a first switching circuit and a second switching circuit connected to the first transistor and to the second transistor, respectively, wherein the first switching circuit is connected to the source of the first transistor and the second switching circuit is connected to the source of the second transistor, wherein the first switching circuit is switched to a point of ground potential during a high swing mode condition and is switched to a first source of biasing potential during a low swing mode condition, wherein the second switching circuit is switched to the first source of biasing potential during a high swing mode condition and is switched to ground during a low swing mode condition, means for varying the biasing potential applied at the gates of the first and second transistors (M1, M2), respectively, wherein the means for varying comprise a first switch block (SWa') and a second switch block (SWb'), wherein the first switch block (SWa') is switched to ground during a high swing mode condition and is switched to half the voltage of the first source of bias potential during a low swing mode condition, wherein the second switch block (SWb') is switched to the voltage of the first source of bias potential during a high swing mode condition and is switched to half the voltage of the first source of bias potential during a low swing mode condition.