An error correction code, ECC, decoder, comprising: a buffer configured to store a plurality of read pages (PG1 - PG3) read from a plurality of multi-level cells (MC1-MCn) connected to a same wordline, wherein the read pages (PG1-PG3) comprise read bits (RB1-RB3) and corresponding reliability parameters (ST, WK) each indicating a reliability of the corresponding read bits (RB1-RB3), wherein the read bits (RB1-RB3) are derived from data read using a first voltage, and the reliability parameters (ST, WK) are derived from data read using a second voltage and a third voltage, the second voltage and the third voltage being proximate to and different from the first voltage, wherein the reliability parameters are derived by performing a logical operation on or encoding data read using the second voltage and the third voltage, and wherein each of the plurality of multi-level cells (MC1-MCn) is programmable into one of a plurality of states (S1-S8), and each of the plurality of multi-level cells (MC1-MCn) stores bits pertaining to different read pages (PG1-PG3), the bits stored in each of the plurality of multi-level cells (MC1-MCn) corresponding to one state; a data converter configured to adjust reliability parameters (ST, WK) of read bits (RB1-RB3) of the plurality of read pages (PG1 - PG3), based on state-bit mapping information (MINF) and the plurality of read pages (PG1 - PG3), to generate a plurality of ECC input data (EID1 - EID3) respectively corresponding to the plurality of read pages (PG1-PG3) based on the plurality of read pages (PG1-PG3) and the reliability parameters (ST, WK), the state-bit mapping information indicating mapping relationships between states (S1-S8) and bits stored in the plurality of multi-level cells (MC1-MCn); and a decoding circuit configured to perform an ECC decoding operation on the plurality of read pages (PG1-PG3) based on the plurality of ECC input data (EID1-EID3). a buffer configured to store a plurality of read pages (PG1 - PG3) read from a plurality of multi-level cells (MC1-MCn) connected to a same wordline, wherein the read pages (PG1-PG3) comprise read bits (RB1-RB3) and corresponding reliability parameters (ST, WK) each indicating a reliability of the corresponding read bits (RB1-RB3), wherein the read bits (RB1-RB3) are derived from data read using a first voltage, and the reliability parameters (ST, WK) are derived from data read using a second voltage and a third voltage, the second voltage and the third voltage being proximate to and different from the first voltage, wherein the reliability parameters are derived by performing a logical operation on or encoding data read using the second voltage and the third voltage, and wherein each of the plurality of multi-level cells (MC1-MCn) is programmable into one of a plurality of states (S1-S8), and each of the plurality of multi-level cells (MC1-MCn) stores bits pertaining to different read pages (PG1-PG3), the bits stored in each of the plurality of multi-level cells (MC1-MCn) corresponding to one state; the read pages (PG1-PG3) comprise read bits (RB1-RB3) and corresponding reliability parameters (ST, WK) each indicating a reliability of the corresponding read bits (RB1-RB3), wherein the read bits (RB1-RB3) are derived from data read using a first voltage, and the reliability parameters (ST, WK) are derived from data read using a second voltage and a third voltage, the second voltage and the third voltage being proximate to and different from the first voltage, wherein the reliability parameters are derived by performing a logical operation on or encoding data read using the second voltage and the third voltage, and wherein each of the plurality of multi-level cells (MC1-MCn) is programmable into one of a plurality of states (S1-S8), and each of the plurality of multi-level cells (MC1-MCn) stores bits pertaining to different read pages (PG1-PG3), the bits stored in each of the plurality of multi-level cells (MC1-MCn) corresponding to one state; a data converter configured to adjust reliability parameters (ST, WK) of read bits (RB1-RB3) of the plurality of read pages (PG1 - PG3), based on state-bit mapping information (MINF) and the plurality of read pages (PG1 - PG3), to generate a plurality of ECC input data (EID1 - EID3) respectively corresponding to the plurality of read pages (PG1-PG3) based on the plurality of read pages (PG1-PG3) and the reliability parameters (ST, WK), the state-bit mapping information indicating mapping relationships between states (S1-S8) and bits stored in the plurality of multi-level cells (MC1-MCn); and a decoding circuit configured to perform an ECC decoding operation on the plurality of read pages (PG1-PG3) based on the plurality of ECC input data (EID1-EID3).