A circuit configured to receive a reference signal and a target signal comprising: first circuitry (610,602,604) operative to output first levels (Q 602,Q 604) representative of the reference signal when triggered by the target signal, the first circuitry comprising a first circuit operative to output a first detected level (Q 602) representative of the reference signal detected in synchrony with the rising edge of the target signal and a second circuit configured to output a second detected level (Q 604) representative of the reference signal detected in synchrony with the falling of the target signal, wherein the first levels comprise the first detected level and the second detected level; and second circuitry (612,606,608) operative to output second levels (Q 606,Q 608) representative of the target signal when triggered by the reference signal, the second circuitry comprising a third circuit configured to output a third detected level (Q 606) representative of the target signal detected in synchrony with the rising edge of the reference output signal and a fourth circuit configured to output a fourth detected level (Q 608) representative of the target signal detected in synchrony with the falling edge of the reference output signal, wherein the second levels comprise the third detected level and the fourth detected level; characterized in that the circuit further comprises third circuitry (614,616) configured to receive the first levels and the second levels, respectively, from the first and second circuitry, and operative to output a third level when the first levels and the second levels indicate that the target signal is not in phase with the reference signal, the third circuitry comprising a NAND gate configured to receive the second detected level (Q 604) and the fourth detected level (Q 608) and an AND gate configured to receive the output of the NAND gate, the first detected level (Q 602) and the third detected level (Q 606) and to output the third level; and fourth circuitry connected to the third circuitry and operative to output a fourth level after an amount of time has passed, wherein the fourth circuitry is further operative to reset when the third circuitry outputs the third level. first circuitry (610,602,604) operative to output first levels (Q 602,Q 604) representative of the reference signal when triggered by the target signal, the first circuitry comprising a first circuit operative to output a first detected level (Q 602) representative of the reference signal detected in synchrony with the rising edge of the target signal and a second circuit configured to output a second detected level (Q 604) representative of the reference signal detected in synchrony with the falling of the target signal, wherein the first levels comprise the first detected level and the second detected level; and second circuitry (612,606,608) operative to output second levels (Q 606,Q 608) representative of the target signal when triggered by the reference signal, the second circuitry comprising a third circuit configured to output a third detected level (Q 606) representative of the target signal detected in synchrony with the rising edge of the reference output signal and a fourth circuit configured to output a fourth detected level (Q 608) representative of the target signal detected in synchrony with the falling edge of the reference output signal, wherein the second levels comprise the third detected level and the fourth detected level; characterized in that the circuit further comprises third circuitry (614,616) configured to receive the first levels and the second levels, respectively, from the first and second circuitry, and operative to output a third level when the first levels and the second levels indicate that the target signal is not in phase with the reference signal, the third circuitry comprising a NAND gate configured to receive the second detected level (Q 604) and the fourth detected level (Q 608) and an AND gate configured to receive the output of the NAND gate, the first detected level (Q 602) and the third detected level (Q 606) and to output the third level; and fourth circuitry connected to the third circuitry and operative to output a fourth level after an amount of time has passed, wherein the fourth circuitry is further operative to reset when the third circuitry outputs the third level.