A user equipment, UE, unit capable of conducting an initial cell search and establishing a communication link with a base station in a communication network, the UE comprising: a first module configured to process a communication signal and assign an index value to a peak sample of said communication signal, said index value being used to calculate a chip offset of a primary scrambling code; and a second module configured to utilize the calculated chip offset to detect a scrambling code group number, a slot offset, and a secondary synchronization code of the communication signal; a third module configured to receive the chip offset calculated by the first module, and the scrambling code group number and the slot offset detected by the second module, the third module being configured to retrieve a primary scrambling code from said communication signal based on the chip offset, scrambling code group number and slot offset; a controller coupled to said first module, second module and third module, said UE being characterized in that: said controller is configured to control an adjustment of a search frequency in said UE to enable the third module to retrieve the primary scrambling code in said communication signal; the controller including: a first buffer configured to store rejected primary scrambling codes; a second buffer configured to store rejected chip offset vectors; and a decision logic circuit configured to determine whether the detected scrambling code is correct; wherein the first module further includes a mask generator, the mask generator of the first module being configured to determine which chips in each slot are to be excluded from detection by the decision logic circuit, the excluded chips being determined based on chip offsets stored in the second buffer. a first module configured to process a communication signal and assign an index value to a peak sample of said communication signal, said index value being used to calculate a chip offset of a primary scrambling code; and a second module configured to utilize the calculated chip offset to detect a scrambling code group number, a slot offset, and a secondary synchronization code of the communication signal; a third module configured to receive the chip offset calculated by the first module, and the scrambling code group number and the slot offset detected by the second module, the third module being configured to retrieve a primary scrambling code from said communication signal based on the chip offset, scrambling code group number and slot offset; a controller coupled to said first module, second module and third module, said UE being characterized in that: said controller is configured to control an adjustment of a search frequency in said UE to enable the third module to retrieve the primary scrambling code in said communication signal; the controller including: a first buffer configured to store rejected primary scrambling codes; a second buffer configured to store rejected chip offset vectors; and a decision logic circuit configured to determine whether the detected scrambling code is correct; wherein the first module further includes a mask generator, the mask generator of the first module being configured to determine which chips in each slot are to be excluded from detection by the decision logic circuit, the excluded chips being determined based on chip offsets stored in the second buffer. said controller is configured to control an adjustment of a search frequency in said UE to enable the third module to retrieve the primary scrambling code in said communication signal; the controller including: a first buffer configured to store rejected primary scrambling codes; a second buffer configured to store rejected chip offset vectors; and a decision logic circuit configured to determine whether the detected scrambling code is correct; wherein the first module further includes a mask generator, the mask generator of the first module being configured to determine which chips in each slot are to be excluded from detection by the decision logic circuit, the excluded chips being determined based on chip offsets stored in the second buffer.