A device, comprising: at least one processor circuit having means configured to: receive portions of a data burst, line encode the portions into blocks, and add the blocks to a buffer; generate a first FEC codeword from at least some of the blocks of the buffer when a number of blocks in the buffer satisfies a threshold, remove the at least some of the blocks from the buffer, and provide the first FEC codeword for transmission; generate a set of FEC codewords from remaining blocks of the buffer when a marker indicating an end of the data burst is detected, wherein the set of FEC codewords is determined based at least in part on a number of the remaining blocks in the buffer when the marker is detected; and provide the set of FEC codewords for transmission, wherein the at least one processor circuit is further configured to: identify a bin among a plurality of bins based on the number of remaining blocks contained in the buffer when the marker indicating the end of the data burst is detected, wherein: each of the plurality of bins has a respective lower block number threshold and a respective upper block number threshold, and a number of FEC codewords in the set of FEC codewords is determined based at least on the identified bin. at least one processor circuit having means configured to: receive portions of a data burst, line encode the portions into blocks, and add the blocks to a buffer; generate a first FEC codeword from at least some of the blocks of the buffer when a number of blocks in the buffer satisfies a threshold, remove the at least some of the blocks from the buffer, and provide the first FEC codeword for transmission; generate a set of FEC codewords from remaining blocks of the buffer when a marker indicating an end of the data burst is detected, wherein the set of FEC codewords is determined based at least in part on a number of the remaining blocks in the buffer when the marker is detected; and provide the set of FEC codewords for transmission, wherein receive portions of a data burst, line encode the portions into blocks, and add the blocks to a buffer; generate a first FEC codeword from at least some of the blocks of the buffer when a number of blocks in the buffer satisfies a threshold, remove the at least some of the blocks from the buffer, and provide the first FEC codeword for transmission; generate a set of FEC codewords from remaining blocks of the buffer when a marker indicating an end of the data burst is detected, wherein the set of FEC codewords is determined based at least in part on a number of the remaining blocks in the buffer when the marker is detected; and provide the set of FEC codewords for transmission, wherein the at least one processor circuit is further configured to: identify a bin among a plurality of bins based on the number of remaining blocks contained in the buffer when the marker indicating the end of the data burst is detected, wherein: each of the plurality of bins has a respective lower block number threshold and a respective upper block number threshold, and a number of FEC codewords in the set of FEC codewords is determined based at least on the identified bin. identify a bin among a plurality of bins based on the number of remaining blocks contained in the buffer when the marker indicating the end of the data burst is detected, wherein: each of the plurality of bins has a respective lower block number threshold and a respective upper block number threshold, and a number of FEC codewords in the set of FEC codewords is determined based at least on the identified bin. each of the plurality of bins has a respective lower block number threshold and a respective upper block number threshold, and a number of FEC codewords in the set of FEC codewords is determined based at least on the identified bin.