A digital pixel circuit comprising: a detector including a photodiode coupled to a well capacitor, the well capacitor configured to accumulate charge generated by an input light signal incident on the photodiode and the detector configured to discharge the well capacitor each time a voltage across the well capacitor exceeds a well capacitor threshold value, characterized by: a Digital Readout Integrated Circuit - DROIC - coupled to the detector and configured, in a first mode of operation, to increment a value of a reset counter each time the well capacitor is discharged, and in a second mode of operation, not to increment the reset counter when the well capacitor is discharged; and an image processing unit coupled to the DROIC, the image processing unit configured to monitor a count rate at which the DROIC is incrementing the reset counter, transmit a count enable signal at a first level to the DROIC in response to a determination that the count rate of the DROIC is less than a count rate threshold, and transmit a count enable signal at a second level to the DROIC in response to a determination that the count rate of the DROIC is greater than the count rate threshold, wherein, the DROIC is further configured, in response to receiving the count enable signal at the first level, to operate in the first mode of operation, and in response to receiving the count enable signal at the second level, to operate in the second mode of operation. a detector including a photodiode coupled to a well capacitor, the well capacitor configured to accumulate charge generated by an input light signal incident on the photodiode and the detector configured to discharge the well capacitor each time a voltage across the well capacitor exceeds a well capacitor threshold value, characterized by: a Digital Readout Integrated Circuit - DROIC - coupled to the detector and configured, in a first mode of operation, to increment a value of a reset counter each time the well capacitor is discharged, and in a second mode of operation, not to increment the reset counter when the well capacitor is discharged; and an image processing unit coupled to the DROIC, the image processing unit configured to monitor a count rate at which the DROIC is incrementing the reset counter, transmit a count enable signal at a first level to the DROIC in response to a determination that the count rate of the DROIC is less than a count rate threshold, and transmit a count enable signal at a second level to the DROIC in response to a determination that the count rate of the DROIC is greater than the count rate threshold, a Digital Readout Integrated Circuit - DROIC - coupled to the detector and configured, in a first mode of operation, to increment a value of a reset counter each time the well capacitor is discharged, and in a second mode of operation, not to increment the reset counter when the well capacitor is discharged; and an image processing unit coupled to the DROIC, the image processing unit configured to monitor a count rate at which the DROIC is incrementing the reset counter, transmit a count enable signal at a first level to the DROIC in response to a determination that the count rate of the DROIC is less than a count rate threshold, and transmit a count enable signal at a second level to the DROIC in response to a determination that the count rate of the DROIC is greater than the count rate threshold, wherein, the DROIC is further configured, in response to receiving the count enable signal at the first level, to operate in the first mode of operation, and in response to receiving the count enable signal at the second level, to operate in the second mode of operation.