A data transmitter comprising: a plurality of parallel driver slices (301, 302, 303), a first driver slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor and in series with a second transistor coupled to a first bias signal (Vpres) and with a third transistor in parallel to the second transistor; wherein a gate of the first transistor is coupled to a p portion (inp) of a differential data signal received at the plurality of parallel driver slices; and a first bias circuit configured to maintain an output resistance of the first signal generator circuit to a first resistance value, and including a fourth transistor and a fifth transistor in series with a first current source and a sixth transistor in parallel with the fourth transistor, wherein the fourth transistor comprises a replica of the second transistor, the fifth transistor comprises a replica of the first transistor and the sixth transistor comprises a replica of the third transistor, the first bias circuit further including a first operational amplifier, op amp, having a first inverting input coupled to a first reference voltage (vref1) and a second non-inverting input coupled between the fifth transistor and the first current source, an output of the first op amp configured to provide the first bias signal (Vpres) to a gate of the second transistor and to a gate of the fourth transistor, wherein a gate of the sixth transistor is coupled to a second current source and to a gate of the third transistor, wherein said maintaining the output resistance of the first signal generator circuit comprises adjusting gate voltage (Vpcorner) of the third transistor and the sixth transistor, to operate in a triode region. a plurality of parallel driver slices (301, 302, 303), a first driver slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor and in series with a second transistor coupled to a first bias signal (Vpres) and with a third transistor in parallel to the second transistor; wherein a gate of the first transistor is coupled to a p portion (inp) of a differential data signal received at the plurality of parallel driver slices; and a first bias circuit configured to maintain an output resistance of the first signal generator circuit to a first resistance value, and including a fourth transistor and a fifth transistor in series with a first current source and a sixth transistor in parallel with the fourth transistor, wherein the fourth transistor comprises a replica of the second transistor, the fifth transistor comprises a replica of the first transistor and the sixth transistor comprises a replica of the third transistor, the first bias circuit further including a first operational amplifier, op amp, having a first inverting input coupled to a first reference voltage (vref1) and a second non-inverting input coupled between the fifth transistor and the first current source, an output of the first op amp configured to provide the first bias signal (Vpres) to a gate of the second transistor and to a gate of the fourth transistor, wherein a gate of the sixth transistor is coupled to a second current source and to a gate of the third transistor, wherein said maintaining the output resistance of the first signal generator circuit comprises adjusting gate voltage (Vpcorner) of the third transistor and the sixth transistor, to operate in a triode region.