An array substrate comprising a Gate Driver on Array, GOA, circuit structure having a plurality of GOA units forming a shift register and a GOA reset circuit configured to reset the last GOA unit for a last row, wherein each of said GOA units has a normal phase clock signal input terminal, a reverse phase clock signal input terminal (CLKB), a low voltage signal input terminal, an input terminal (INPUT), an output terminal (OUTPUT), and a reset terminal (RESET), and wherein said GOA reset circuit comprises: a first electronic switch circuit connected to the input terminal (INPUT) of the last GOA unit; and a second electronic switch circuit connected to the output terminal (OUTPUT) of the last GOA unit, wherein the first electronic switch circuit is connected to the low voltage signal input terminal of the last GOA unit, which is a low level signal terminal, and is switched on to connect the low voltage signal input terminal to the reset terminal (RESET) of the last GOA unit when the input terminal (INPUT) of the last GOA unit is at a high level; and the second electronic switch circuit is connected to the reverse phase clock signal input terminal (CLKB) of the last GOA unit and is switched on to connect the reverse phase clock signal input terminal (CLKB) to the reset terminal (RESET) of the last GOA unit when the output terminal (OUTPUT) of the last GOA unit is at a high level, the first electronic switch circuit includes a first switching element which is one of a Field-Effect Transistor, FET, and a Thin Film Transistor, TFT; and the second electronic switch circuit includes a second switching element which is one of a FET and a TFT; a delay element having a first terminal connected to the output terminal (OUTPUT) of the last GOA unit and a second terminal connected to a control terminal of the second electronic switch circuit, wherein the delay element is a coupling capacitor; a control electrode of the first electronic switch circuit is connected to the input terminal (INPUT) of the last GOA unit, a first terminal electrode of the first electronic switch circuit is connected to the low voltage signal input terminal, and a second terminal electrode of the first electronic switch circuit is connected to the reset terminal (RESET) of the last GOA unit; and a control electrode of the second electronic switch circuit is connected to the output terminal (OUTPUT) of the last GOA unit via the delay element, a first terminal electrode of the second electronic switch circuit is connected to the reverse phase clock signal input terminal (CLKB), and a second terminal electrode of the second electronic switch circuit is connected to the reset terminal (RESET) of the last GOA unit. a first electronic switch circuit connected to the input terminal (INPUT) of the last GOA unit; and a second electronic switch circuit connected to the output terminal (OUTPUT) of the last GOA unit, wherein the first electronic switch circuit is connected to the low voltage signal input terminal of the last GOA unit, which is a low level signal terminal, and is switched on to connect the low voltage signal input terminal to the reset terminal (RESET) of the last GOA unit when the input terminal (INPUT) of the last GOA unit is at a high level; and the second electronic switch circuit is connected to the reverse phase clock signal input terminal (CLKB) of the last GOA unit and is switched on to connect the reverse phase clock signal input terminal (CLKB) to the reset terminal (RESET) of the last GOA unit when the output terminal (OUTPUT) of the last GOA unit is at a high level, the first electronic switch circuit includes a first switching element which is one of a Field-Effect Transistor, FET, and a Thin Film Transistor, TFT; and the second electronic switch circuit includes a second switching element which is one of a FET and a TFT; a delay element having a first terminal connected to the output terminal (OUTPUT) of the last GOA unit and a second terminal connected to a control terminal of the second electronic switch circuit, wherein the delay element is a coupling capacitor; a control electrode of the first electronic switch circuit is connected to the input terminal (INPUT) of the last GOA unit, a first terminal electrode of the first electronic switch circuit is connected to the low voltage signal input terminal, and a second terminal electrode of the first electronic switch circuit is connected to the reset terminal (RESET) of the last GOA unit; and a control electrode of the second electronic switch circuit is connected to the output terminal (OUTPUT) of the last GOA unit via the delay element, a first terminal electrode of the second electronic switch circuit is connected to the reverse phase clock signal input terminal (CLKB), and a second terminal electrode of the second electronic switch circuit is connected to the reset terminal (RESET) of the last GOA unit.