An encryption device including a data processing unit configured to convert 2n-bit data L and an exclusive OR calculator configured to calculate an exclusive OR of a process result of the data processing unit and 2n-bit data R, the device comprising: a first register (Reg-FO) configured to store n-bit data; a first multiplexer configured to selectively output one of n-bit data stored in the first register (Reg-FO), higher-order n bits LL of the data L and lower-order n bits LR of the data L; a first exclusive OR calculator configured to calculate an exclusive OR of an output of the first multiplexer and a round key KOij, where j is a natural number; a first data processing unit configured to convert an output of the first exclusive OR calculator to n-bit data, using an extended key KIik, where k is a natural number; a second multiplexer configured to selectively output one of lower-order n bits LR of the data L and n-bit "0" data; a second exclusive OR calculator configured to calculate an exclusive OR of an output of the second multiplexer and an output of the first data processing unit; a third multiplexer configured to selectively output one of an output of the second exclusive OR calculator and a round key KOim, where m is a natural number; a second register (Reg-R) configured to store the data R; a third exclusive OR calculator configured to calculate an exclusive OR of higher-order n bits RL of data R stored in the second register (Reg-R) and an output of the third multiplexer; and a fourth exclusive OR calculator configured to calculate an exclusive OR of an output of the second exclusive OR calculator and lower-order n bits RR of the data R stored in the second register (Reg-R), wherein the first multiplexer, second multiplexer and third multiplexer are externally controlled, the first register (Reg-FO) is configured to input and store an output of the second exclusive OR calculator, and the second register (Reg-R) is configured to store an output of the third exclusive OR calculator and an output of the fourth exclusive OR calculator as higher-order n bits RL and lower-order n bits RR of the data R, respectively. a first register (Reg-FO) configured to store n-bit data; a first multiplexer configured to selectively output one of n-bit data stored in the first register (Reg-FO), higher-order n bits LL of the data L and lower-order n bits LR of the data L; a first exclusive OR calculator configured to calculate an exclusive OR of an output of the first multiplexer and a round key KOij, where j is a natural number; a first data processing unit configured to convert an output of the first exclusive OR calculator to n-bit data, using an extended key KIik, where k is a natural number; a second multiplexer configured to selectively output one of lower-order n bits LR of the data L and n-bit "0" data; a second exclusive OR calculator configured to calculate an exclusive OR of an output of the second multiplexer and an output of the first data processing unit; a third multiplexer configured to selectively output one of an output of the second exclusive OR calculator and a round key KOim, where m is a natural number; a second register (Reg-R) configured to store the data R; a third exclusive OR calculator configured to calculate an exclusive OR of higher-order n bits RL of data R stored in the second register (Reg-R) and an output of the third multiplexer; and a fourth exclusive OR calculator configured to calculate an exclusive OR of an output of the second exclusive OR calculator and lower-order n bits RR of the data R stored in the second register (Reg-R), wherein the first multiplexer, second multiplexer and third multiplexer are externally controlled, the first register (Reg-FO) is configured to input and store an output of the second exclusive OR calculator, and the second register (Reg-R) is configured to store an output of the third exclusive OR calculator and an output of the fourth exclusive OR calculator as higher-order n bits RL and lower-order n bits RR of the data R, respectively.