A method for migration from a first addressing scheme to a second addressing scheme, comprising: receiving, by a coherence ordering unit, "COU", a first request to access a first memory address and a second request to access a second memory address; comparing, by the COU, the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; the method being characterised by: tagging, by the COU, the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging, by the COU, the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending, by the COU, the first request to a first memory controller unit, "MCU", and the second request to a second MCU, wherein the first MCU interprets the first memory address according to the first addressing scheme in response to the first tag, and wherein the second MCU interprets the second memory address according to the second addressing scheme in response to the second tag; and establishing, by a scrubber connected to the COU, a time window in response to the barrier pointer being modified; issuing, by the scrubber, a read request tagged with the first tag, directed towards the barrier address in response expiration of the time window; receiving, by the scrubber, a value in response to the read request; issuing, by the scrubber, a write request tagged with the second tag, comprising the value and directed toward the barrier address; updating by the COU the barrier pointer to reference the next un-migrated address in response to issuing the write request tagged with the second tag by the scrubber. receiving, by a coherence ordering unit, "COU", a first request to access a first memory address and a second request to access a second memory address; comparing, by the COU, the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; the method being characterised by: tagging, by the COU, the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging, by the COU, the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending, by the COU, the first request to a first memory controller unit, "MCU", and the second request to a second MCU, wherein the first MCU interprets the first memory address according to the first addressing scheme in response to the first tag, and wherein the second MCU interprets the second memory address according to the second addressing scheme in response to the second tag; and establishing, by a scrubber connected to the COU, a time window in response to the barrier pointer being modified; issuing, by the scrubber, a read request tagged with the first tag, directed towards the barrier address in response expiration of the time window; receiving, by the scrubber, a value in response to the read request; issuing, by the scrubber, a write request tagged with the second tag, comprising the value and directed toward the barrier address; updating by the COU the barrier pointer to reference the next un-migrated address in response to issuing the write request tagged with the second tag by the scrubber. tagging, by the COU, the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging, by the COU, the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending, by the COU, the first request to a first memory controller unit, "MCU", and the second request to a second MCU, wherein the first MCU interprets the first memory address according to the first addressing scheme in response to the first tag, and wherein the second MCU interprets the second memory address according to the second addressing scheme in response to the second tag; and establishing, by a scrubber connected to the COU, a time window in response to the barrier pointer being modified; issuing, by the scrubber, a read request tagged with the first tag, directed towards the barrier address in response expiration of the time window; receiving, by the scrubber, a value in response to the read request; issuing, by the scrubber, a write request tagged with the second tag, comprising the value and directed toward the barrier address; updating by the COU the barrier pointer to reference the next un-migrated address in response to issuing the write request tagged with the second tag by the scrubber.