A semiconductor structure, comprising: a substrate comprising an active region and an isolation region; a plurality of gate structures (308A-308E), each having a portion disposed above the active region and a portion disposed above the isolation region of the substrate, wherein one or more of the plurality of gate structures (308A-308E) comprises a gate cap dielectric layer on a top surface of the gate structure, the gate cap dielectric layer having a top surface, and wherein the gate cap dielectric layer comprises a first material; a plurality of source or drain regions disposed in the active region of the substrate, between the portions of the gate structures (308A-308E) disposed above the active region; a plurality of source or drain contacts (311A-311C), a source or drain contact disposed on each of the source or drain regions, one or more of the plurality of source or drain contacts (311A-311C) comprising a trench cap dielectric layer on a top surface of the source or drain contact, the source or drain contacts (311A-311C) having a top surface below the top surface of the gate structures (308A-308E), and the trench cap dielectric layer having a top surface co-planar with the top surface of the gate cap dielectric layer, wherein the trench cap dielectric layer comprises a second material with a different etch characteristic than the first material; a gate contact via disposed on one of the gate structures (308A-308E) only partially covered by the gate cap dielectric layer, on the portion of the gate structure disposed above the active region of the substrate; and a source or drain contact via disposed on one of the source or drain contacts (311A-311C) only partially covered by the trench cap dielectric layer; wherein each of the gate structures (308A-308E) further comprises a pair of sidewall spacers, wherein the source or drain contacts (311A-311C) are disposed directly adjacent to the sidewall spacers of a corresponding gate structure, and wherein the sidewall spacers have a same height as the gate structures (308A-308E) and are covered by the gate cap dielectric layer. a substrate comprising an active region and an isolation region; a plurality of gate structures (308A-308E), each having a portion disposed above the active region and a portion disposed above the isolation region of the substrate, wherein one or more of the plurality of gate structures (308A-308E) comprises a gate cap dielectric layer on a top surface of the gate structure, the gate cap dielectric layer having a top surface, and wherein the gate cap dielectric layer comprises a first material; a plurality of source or drain regions disposed in the active region of the substrate, between the portions of the gate structures (308A-308E) disposed above the active region; a plurality of source or drain contacts (311A-311C), a source or drain contact disposed on each of the source or drain regions, one or more of the plurality of source or drain contacts (311A-311C) comprising a trench cap dielectric layer on a top surface of the source or drain contact, the source or drain contacts (311A-311C) having a top surface below the top surface of the gate structures (308A-308E), and the trench cap dielectric layer having a top surface co-planar with the top surface of the gate cap dielectric layer, wherein the trench cap dielectric layer comprises a second material with a different etch characteristic than the first material; a gate contact via disposed on one of the gate structures (308A-308E) only partially covered by the gate cap dielectric layer, on the portion of the gate structure disposed above the active region of the substrate; and a source or drain contact via disposed on one of the source or drain contacts (311A-311C) only partially covered by the trench cap dielectric layer; wherein each of the gate structures (308A-308E) further comprises a pair of sidewall spacers, wherein the source or drain contacts (311A-311C) are disposed directly adjacent to the sidewall spacers of a corresponding gate structure, and wherein the sidewall spacers have a same height as the gate structures (308A-308E) and are covered by the gate cap dielectric layer.