A NAND flash controller comprising a status circuit configured to determine a number of program and erase cycles for a block of a NAND device, wherein the block is an open block from a time of a first write to the block until a time that all pages of the block have been programmed, wherein the block is a closed block from the time that all pages of the block have been programmed until a subsequent erase, wherein an endurance event is determined to occur each time that the determined number of program and erase cycles reaches a threshold number of program and erase cycles, wherein the status circuit is operable to determine a number of reads performed on the block after the block is closed and a read disturb event is determined to have occurred each time that the determined number of reads reaches a read disturb threshold, wherein the status circuit is operable to determine a closed block retention time to be the amount of time that has elapsed since the time that the block is closed and a retention timer event is determined to have occurred when the closed block retention time reaches a threshold retention time; and a background reference positioning circuit coupled to the status circuit, the background reference positioning circuit configured to perform, when the block is closed and upon the occurrence of one or more of the endurance event, the retention timer event and the read disturb event, background reads of representative pages of each page group of the block by sending to the NAND device threshold voltage shift read instructions representative of offsets to each threshold voltage that is required for reading the representative pages of each page group of the block to identify a set of updated threshold voltage offset values for each page group of the block, wherein each time that a set of updated threshold voltage offset values is identified in response to the endurance event, the set of updated threshold voltage offset values are saved as a set of endurance threshold voltage offset values and as a set of retention-read threshold voltage offset values, wherein each time that a set of updated threshold voltage offset values is identified in response to the retention timer event or the read disturb event, the set of updated threshold voltage offset values are saved as the set of retention-read threshold voltage offset values, a read circuit coupled to the status circuit and to the background reference positioning circuit, characterized in that: when the block is open, the read circuit is configured to perform host-requested reads by sending threshold voltage shift read instructions to the NAND device using a set of the endurance threshold voltage offset values corresponding to the page group of the page being read, and when the block is closed the read circuit is configured to perform host-requested reads by sending threshold voltage shift read instructions to the NAND device using the set of retention-read threshold voltage offset values corresponding to the page group of the page being read. when the block is open, the read circuit is configured to perform host-requested reads by sending threshold voltage shift read instructions to the NAND device using a set of the endurance threshold voltage offset values corresponding to the page group of the page being read, and when the block is closed the read circuit is configured to perform host-requested reads by sending threshold voltage shift read instructions to the NAND device using the set of retention-read threshold voltage offset values corresponding to the page group of the page being read.