A computer-implemented method for configuring a hardware system, the hardware system comprising a plurality of configurable hardware logic, called CHL, circuits (CHL1A, CHL2A, CHL3, CHL4) which are connected by a plurality of physical connections (S1, S2, S3), wherein each CHL circuit comprises multiplexer circuits for time-multiplexing the physical connections, the method comprising: providing, in the computer, a first data representative of a first assignment of a plurality of wires (p1A, p2, p3, p4A) to the plurality of physical connections (S1, S2, S3) between the plurality of CHL circuits (CHL1A, CHL2A, CHL3, CHL4) of the hardware system, wherein each wire represents a segment of a plurality of paths of a circuit design to be mapped to the hardware system and wherein multiple wires are mapped to a single physical connection of the plurality of physical connections; and transforming, using the computer, the first data into a second data representative of a second assignment of the plurality of wires (p1A, p2, p3, p4A) to the plurality of physical connections (S1, S2, S3), wherein the transforming includes: calculating a plurality of latencies each associated with a selected one of the plurality of wires (plA, p2, p3, p4A), wherein a latency of a wire is determined by a latency of the path that includes the segment that is represented by the wire; and assigning a first subset of the plurality of wires (plA, p2, p3, p4A) to a reduced number of the plurality of physical connections (S1, S2, S3) in accordance with a first improvement goal, thereby leaving as many as possible empty physical connections, and responsive to assigning the first subset, assigning a second subset of the plurality of wires (p1A, p2, p3, p4A) to at least one of the empty physical connections (S1, S2, S3), wherein the latencies associated with the wires of the first subset are less critical than latencies associated with the wires of the second subset, and wherein transforming causes the value of each one of the plurality of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system. providing, in the computer, a first data representative of a first assignment of a plurality of wires (p1A, p2, p3, p4A) to the plurality of physical connections (S1, S2, S3) between the plurality of CHL circuits (CHL1A, CHL2A, CHL3, CHL4) of the hardware system, wherein each wire represents a segment of a plurality of paths of a circuit design to be mapped to the hardware system and wherein multiple wires are mapped to a single physical connection of the plurality of physical connections; and transforming, using the computer, the first data into a second data representative of a second assignment of the plurality of wires (p1A, p2, p3, p4A) to the plurality of physical connections (S1, S2, S3), wherein the transforming includes: calculating a plurality of latencies each associated with a selected one of the plurality of wires (plA, p2, p3, p4A), wherein a latency of a wire is determined by a latency of the path that includes the segment that is represented by the wire; and assigning a first subset of the plurality of wires (plA, p2, p3, p4A) to a reduced number of the plurality of physical connections (S1, S2, S3) in accordance with a first improvement goal, thereby leaving as many as possible empty physical connections, and responsive to assigning the first subset, assigning a second subset of the plurality of wires (p1A, p2, p3, p4A) to at least one of the empty physical connections (S1, S2, S3), wherein the latencies associated with the wires of the first subset are less critical than latencies associated with the wires of the second subset, and wherein transforming causes the value of each one of the plurality of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system. calculating a plurality of latencies each associated with a selected one of the plurality of wires (plA, p2, p3, p4A), wherein a latency of a wire is determined by a latency of the path that includes the segment that is represented by the wire; and assigning a first subset of the plurality of wires (plA, p2, p3, p4A) to a reduced number of the plurality of physical connections (S1, S2, S3) in accordance with a first improvement goal, thereby leaving as many as possible empty physical connections, and responsive to assigning the first subset, assigning a second subset of the plurality of wires (p1A, p2, p3, p4A) to at least one of the empty physical connections (S1, S2, S3), wherein the latencies associated with the wires of the first subset are less critical than latencies associated with the wires of the second subset, and wherein transforming causes the value of each one of the plurality of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.