A bandpass analog-to-digital converter, ADC, for use in RF receiver circuitry of a wireless communication device, the bandpass ADC comprising: first noise-shaping successive approximation register, NS-SAR, circuitry arranged in a first path; and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate, Fs/2, wherein at least one of the first and second NS-SAR circuitry includes: a capacitor digital to analog converter, DAC, configured to sample the analog input voltage; and a feedback path from the output of a SAR comparator to the capacitor digital to analog converter, DAC,; and wherein the capacitor digital to analog converter, DAC, is configured to provide two outputs including a main SAR output voltage and a residue voltage, which represents the quantization error after a SAR conversion cycle is complete; and wherein the at least one of the first and second NS-SAR circuitry further includes: noise-shaping circuitry arranged to process a residue voltage output from the capacitor DAC, wherein the noise-shaping circuitry comprises a low-noise amplifier and loop filter circuitry comprising low-pass loop filter circuitry, wherein the low-noise amplifier is arranged to amplify the residue voltage output from the capacitor DAC, and wherein the loop filter circuitry is arranged between the output of the low-noise amplifier and a first input of the SAR comparator; and a first mixer configured to invert a voltage provided by the low-noise amplifier at the particular sampling rate F s /2 and a second mixer configured to invert an output of the low-pass loop filter circuitry at the particular sampling rate, Fs/2; and wherein the SAR comparator includes the first input and a second input, and wherein the SAR comparator is arranged to receive the main SAR output voltage at the second input; and wherein the bandpass ADC further comprises: a first switch arranged at the output of the first NS-SAR circuitry and a second switch arranged at the output of the second NS-SAR circuitry, wherein the first switch and the second switch are configured to alternately sample the output of the first and second NS-SAR circuitries at the particular sampling rate, Fs/2, to generate digital output. first noise-shaping successive approximation register, NS-SAR, circuitry arranged in a first path; and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate, Fs/2, wherein at least one of the first and second NS-SAR circuitry includes: a capacitor digital to analog converter, DAC, configured to sample the analog input voltage; and a feedback path from the output of a SAR comparator to the capacitor digital to analog converter, DAC,; and a capacitor digital to analog converter, DAC, configured to sample the analog input voltage; and a feedback path from the output of a SAR comparator to the capacitor digital to analog converter, DAC,; and wherein the capacitor digital to analog converter, DAC, is configured to provide two outputs including a main SAR output voltage and a residue voltage, which represents the quantization error after a SAR conversion cycle is complete; and wherein the at least one of the first and second NS-SAR circuitry further includes: noise-shaping circuitry arranged to process a residue voltage output from the capacitor DAC, wherein the noise-shaping circuitry comprises a low-noise amplifier and loop filter circuitry comprising low-pass loop filter circuitry, wherein the low-noise amplifier is arranged to amplify the residue voltage output from the capacitor DAC, and wherein the loop filter circuitry is arranged between the output of the low-noise amplifier and a first input of the SAR comparator; and a first mixer configured to invert a voltage provided by the low-noise amplifier at the particular sampling rate F s /2 and a second mixer configured to invert an output of the low-pass loop filter circuitry at the particular sampling rate, Fs/2; and noise-shaping circuitry arranged to process a residue voltage output from the capacitor DAC, wherein the noise-shaping circuitry comprises a low-noise amplifier and loop filter circuitry comprising low-pass loop filter circuitry, wherein the low-noise amplifier is arranged to amplify the residue voltage output from the capacitor DAC, and wherein the loop filter circuitry is arranged between the output of the low-noise amplifier and a first input of the SAR comparator; and a first mixer configured to invert a voltage provided by the low-noise amplifier at the particular sampling rate F s /2 and a second mixer configured to invert an output of the low-pass loop filter circuitry at the particular sampling rate, Fs/2; and wherein the SAR comparator includes the first input and a second input, and wherein the SAR comparator is arranged to receive the main SAR output voltage at the second input; and wherein the bandpass ADC further comprises: a first switch arranged at the output of the first NS-SAR circuitry and a second switch arranged at the output of the second NS-SAR circuitry, a first switch arranged at the output of the first NS-SAR circuitry and a second switch arranged at the output of the second NS-SAR circuitry, wherein the first switch and the second switch are configured to alternately sample the output of the first and second NS-SAR circuitries at the particular sampling rate, Fs/2, to generate digital output.