An apparatus comprising: an instruction decoder to decode instructions; processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder; and memory attribute checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a plurality of memory attribute entries, each memory attribute entry specifying access permissions for a corresponding address region of variable size within an address space; in which: in response to a single range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder is configured to control the processing circuitry to set, in at least one software-accessible storage location (12, 13) accessible to at least one type of instruction supported by the instruction decoder, a status value indicative of whether the first address and the second address correspond to the same memory attribute entry; the memory attribute checking circuitry comprises at least one set of comparators, each set of comparators comprising: a lower bound comparator to compare a target address of a memory access request against a lower bound address of a given memory attribute entry; and an upper bound comparator to compare the target address of a memory access request against an upper bound address of the given memory attribute entry; and in response to the range checking instruction, the instruction decoder is configured to control the processing circuitry to supply the first address as the target address to the lower bound comparator of each set of comparators and to supply the second address as the target address to the upper bound comparator of each set of comparators. an instruction decoder to decode instructions; processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder; and memory attribute checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a plurality of memory attribute entries, each memory attribute entry specifying access permissions for a corresponding address region of variable size within an address space; in which: in response to a single range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder is configured to control the processing circuitry to set, in at least one software-accessible storage location (12, 13) accessible to at least one type of instruction supported by the instruction decoder, a status value indicative of whether the first address and the second address correspond to the same memory attribute entry; the memory attribute checking circuitry comprises at least one set of comparators, each set of comparators comprising: a lower bound comparator to compare a target address of a memory access request against a lower bound address of a given memory attribute entry; and an upper bound comparator to compare the target address of a memory access request against an upper bound address of the given memory attribute entry; and in response to the range checking instruction, the instruction decoder is configured to control the processing circuitry to supply the first address as the target address to the lower bound comparator of each set of comparators and to supply the second address as the target address to the upper bound comparator of each set of comparators. in response to a single range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder is configured to control the processing circuitry to set, in at least one software-accessible storage location (12, 13) accessible to at least one type of instruction supported by the instruction decoder, a status value indicative of whether the first address and the second address correspond to the same memory attribute entry; the memory attribute checking circuitry comprises at least one set of comparators, each set of comparators comprising: a lower bound comparator to compare a target address of a memory access request against a lower bound address of a given memory attribute entry; and an upper bound comparator to compare the target address of a memory access request against an upper bound address of the given memory attribute entry; and a lower bound comparator to compare a target address of a memory access request against a lower bound address of a given memory attribute entry; and an upper bound comparator to compare the target address of a memory access request against an upper bound address of the given memory attribute entry; and in response to the range checking instruction, the instruction decoder is configured to control the processing circuitry to supply the first address as the target address to the lower bound comparator of each set of comparators and to supply the second address as the target address to the upper bound comparator of each set of comparators.