A half-bridge driver circuit comprising: - two output terminals for providing a high side drive signal ( DRV 1) for a high side switch (SW 1) and a low side drive signal ( DRV 2) for a low side switch (SW 2); - a high side driver circuit (200 1) configured to generate said high side drive signal ( DRV 1) as a function of a high side control signal ( IN 1); - a low side driver circuit (200 2) configured to generate said low side drive signal ( DRV 2) as a function of a low side control signal ( IN 2); - an input terminal for receiving a control signal ( CTR 1); and - a circuit (208 1) configured to generate said high side control signal ( IN 1) and said low side control signal ( IN 2) as a function of said control signal ( CTR 1); wherein said circuit (208 1) comprises: - an edge detector (2080, 2082) configured to generate a first signal in response to a first type of edge in said control signal ( CTR 1) and a second signal in response to a second type of edge in said control signal ( CTR 1), said second type of edge being opposed to said first type of edge; and - a state machine comprising: - a first state, where said high side control signal ( IN 1) and said low side control signal ( IN 2) are set to said first logic level, - a second state, where said high side control signal ( IN 1) is set to said second logic level and said low side control signal ( IN 2) is set to said first logic level, - a third state, where said high side control signal ( IN 1) and said low side control signal ( IN 2) are set to said first logic level, and - a fourth state, where said high side control signal ( IN 1) is set to said first logic level and said low side control signal ( IN 2) is set to said second logic level; wherein said state machine is configured to proceed to one of said states in response to a reset signal and: - proceed from said first state to said second state in response to said second signal, - proceed from said second state to said third state in response to said first signal, - proceed from said third state to said fourth state in response to said second signal, and - proceed from said fourth state to said first state in response to said first signal. - two output terminals for providing a high side drive signal ( DRV 1) for a high side switch (SW 1) and a low side drive signal ( DRV 2) for a low side switch (SW 2); - a high side driver circuit (200 1) configured to generate said high side drive signal ( DRV 1) as a function of a high side control signal ( IN 1); - a low side driver circuit (200 2) configured to generate said low side drive signal ( DRV 2) as a function of a low side control signal ( IN 2); - an input terminal for receiving a control signal ( CTR 1); and - a circuit (208 1) configured to generate said high side control signal ( IN 1) and said low side control signal ( IN 2) as a function of said control signal ( CTR 1); - an edge detector (2080, 2082) configured to generate a first signal in response to a first type of edge in said control signal ( CTR 1) and a second signal in response to a second type of edge in said control signal ( CTR 1), said second type of edge being opposed to said first type of edge; and - a state machine comprising: - a first state, where said high side control signal ( IN 1) and said low side control signal ( IN 2) are set to said first logic level, - a second state, where said high side control signal ( IN 1) is set to said second logic level and said low side control signal ( IN 2) is set to said first logic level, - a third state, where said high side control signal ( IN 1) and said low side control signal ( IN 2) are set to said first logic level, and - a fourth state, where said high side control signal ( IN 1) is set to said first logic level and said low side control signal ( IN 2) is set to said second logic level; - a first state, where said high side control signal ( IN 1) and said low side control signal ( IN 2) are set to said first logic level, - a second state, where said high side control signal ( IN 1) is set to said second logic level and said low side control signal ( IN 2) is set to said first logic level, - a third state, where said high side control signal ( IN 1) and said low side control signal ( IN 2) are set to said first logic level, and - a fourth state, where said high side control signal ( IN 1) is set to said first logic level and said low side control signal ( IN 2) is set to said second logic level; - proceed from said first state to said second state in response to said second signal, - proceed from said second state to said third state in response to said first signal, - proceed from said third state to said fourth state in response to said second signal, and - proceed from said fourth state to said first state in response to said first signal.