An optimization apparatus comprising: a pseudo random number generator hardware module configured to operate in synchronization with a clock signal, either in a first operation mode in which to generate a random number sequence after performing an initialization or in a second operation mode in which to generate a random number sequence without performing the initialization, the pseudo random number generator hardware module being initialized by an initialization signal; an annealing calculation hardware module configured to perform an annealing process by use of random numbers generated by the pseudo random number generator, and to suspend the annealing process upon completing an execution of a predetermined number of iterations; and an operation instruct hardware module configured to control the pseudo random number generator hardware module and the annealing calculation hardware module, wherein the operation instruct hardware module is configured to cause the pseudo random number generator hardware module to start operating in the first operation mode by activating the initialization signal to initialize the pseudo random number generator hardware module and by supplying the clock signal to the pseudo random number generator hardware module after deactivating the initialization signal, and is configured to cause the annealing calculation hardware module to perform the annealing process while the pseudo random number generator hardware module generates a random number sequence used in the annealing process, wherein the operation instruct hardware module is configured to stop the clock signal to cause the pseudo random number generator hardware module to stop operating when the annealing calculation hardware module suspends the annealing process, and wherein the operation instruct hardware module is configured to cause the pseudo random number generator hardware module to restart operating in the second operation mode by supplying the clock signal to the pseudo random number generator hardware module without activating the initialization signal, and to cause the annealing calculation hardware module to restart the annealing process. a pseudo random number generator hardware module configured to operate in synchronization with a clock signal, either in a first operation mode in which to generate a random number sequence after performing an initialization or in a second operation mode in which to generate a random number sequence without performing the initialization, the pseudo random number generator hardware module being initialized by an initialization signal; an annealing calculation hardware module configured to perform an annealing process by use of random numbers generated by the pseudo random number generator, and to suspend the annealing process upon completing an execution of a predetermined number of iterations; and an operation instruct hardware module configured to control the pseudo random number generator hardware module and the annealing calculation hardware module, wherein the operation instruct hardware module is configured to cause the pseudo random number generator hardware module to start operating in the first operation mode by activating the initialization signal to initialize the pseudo random number generator hardware module and by supplying the clock signal to the pseudo random number generator hardware module after deactivating the initialization signal, and is configured to cause the annealing calculation hardware module to perform the annealing process while the pseudo random number generator hardware module generates a random number sequence used in the annealing process, wherein the operation instruct hardware module is configured to stop the clock signal to cause the pseudo random number generator hardware module to stop operating when the annealing calculation hardware module suspends the annealing process, and wherein the operation instruct hardware module is configured to cause the pseudo random number generator hardware module to restart operating in the second operation mode by supplying the clock signal to the pseudo random number generator hardware module without activating the initialization signal, and to cause the annealing calculation hardware module to restart the annealing process.