An apparatus comprising: a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, a class field, an alpha field, and a beta field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the class field, the alpha field, and the beta field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the class field, the alpha field, and the beta field on each occurrence of an instruction in the first instruction format in instruction streams, wherein a first value in the class field specifies a first class and a second value specifies a second class, the processor including, a decode unit to decode the occurrences of the instructions in the first instruction format with the class field's content specifying the second class as follows: distinguish the occurrences of instructions in the first instruction format that specify memory access from those that do not based on the modifier field's content in those different occurrences, wherein the beta field is interpreted as a broadcast field and a vector length field when the modifier field's content specifies memory access, wherein part of the beta field is interpreted as an RL field when the modifier field's content do not specify memory access; distinguish, for each of the occurrences that specifies memory access through the modifier field's content, whether to broadcast or not and which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the broadcast field and the vector length field in that occurrence; and distinguish, for each of the occurrences that does not specify memory access through the modifier field's content, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that occurrence, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as the vector length field when the RL field's content indicates the vector length type operation; distinguish, for each of the occurrences that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, which one of a plurality of round operations to apply based on the beta field's content and its interpretation as the round operation field in that occurrence; and distinguish, for each of the occurrences, whether to perform a merging write mask operation or a zeroing write mask operation based on the alpha field's content and its interpretation as a write mask control field in that occurrence. distinguish the occurrences of instructions in the first instruction format that specify memory access from those that do not based on the modifier field's content in those different occurrences, wherein the beta field is interpreted as a broadcast field and a vector length field when the modifier field's content specifies memory access, wherein part of the beta field is interpreted as an RL field when the modifier field's content do not specify memory access; distinguish, for each of the occurrences that specifies memory access through the modifier field's content, whether to broadcast or not and which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the broadcast field and the vector length field in that occurrence; and distinguish, for each of the occurrences that does not specify memory access through the modifier field's content, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that occurrence, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as the vector length field when the RL field's content indicates the vector length type operation; distinguish, for each of the occurrences that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, which one of a plurality of round operations to apply based on the beta field's content and its interpretation as the round operation field in that occurrence; and distinguish, for each of the occurrences, whether to perform a merging write mask operation or a zeroing write mask operation based on the alpha field's content and its interpretation as a write mask control field in that occurrence.