An integrated circuit comprising: a plurality of channels of data communication circuitry, the channels being grouped into a plurality of subpluralities of the channels; respective first and second signal distribution conductors (52, 56; 220a, 220b) associated with a respective one of the subpluralities of the channels, wherein each first signal distribution conductor and each second distribution conductor extends only adjacent the channels in an associated subplurality; circuitry for connecting a first signal distribution conductor associated with a respective subplurality to a second signal distribution conductor of an adjacent subplurality; and characterized in that the circuitry for connecting comprises buffer or driver circuitry; each subplurality of the channels comprises clock multiplier unit configured to provide a clock signal for use by the channels of the respective subplurality; and the first signal distribution conductor is coupled to a first clock multiplier unit a first subplurality of the channels, and the second distribution conductor is coupled via the buffer or driver circuitry to a second clock multiplier unit of another second subplurality of the channels; and by the integrated circuit further comprising multiplexers (60, 120), each multiplexer (60, 120) being associated with a respective one of the subpluralities of channels and adapted to receive a respective clock signal from the first and second signal distribution conductor (52, 56) associated with said respective subplurality of channels and further adapted to allow each channel in said respective subplurality to obtain the clock signal from either the first or second conductor (52, 56). a plurality of channels of data communication circuitry, the channels being grouped into a plurality of subpluralities of the channels; respective first and second signal distribution conductors (52, 56; 220a, 220b) associated with a respective one of the subpluralities of the channels, wherein each first signal distribution conductor and each second distribution conductor extends only adjacent the channels in an associated subplurality; circuitry for connecting a first signal distribution conductor associated with a respective subplurality to a second signal distribution conductor of an adjacent subplurality; and characterized in that the circuitry for connecting comprises buffer or driver circuitry; each subplurality of the channels comprises clock multiplier unit configured to provide a clock signal for use by the channels of the respective subplurality; and the first signal distribution conductor is coupled to a first clock multiplier unit a first subplurality of the channels, and the second distribution conductor is coupled via the buffer or driver circuitry to a second clock multiplier unit of another second subplurality of the channels; and by the integrated circuit further comprising multiplexers (60, 120), each multiplexer (60, 120) being associated with a respective one of the subpluralities of channels and adapted to receive a respective clock signal from the first and second signal distribution conductor (52, 56) associated with said respective subplurality of channels and further adapted to allow each channel in said respective subplurality to obtain the clock signal from either the first or second conductor (52, 56).