Power semiconductor circuit comprising • at least two power semiconductor switches (T1, T2), which are connected electrically in parallel and each have a first and a second load current connection (C, E) and a control connection, wherein the first load current connections of the power semiconductor switches (T1, T2) are electrically conductively connected to one another and the second load current connections of the power semiconductor switches (T1, T2) are electrically conductively connected to one another, • a drive circuit arrangement, wherein the drive circuit arrangement has a first, second, third and fourth electrical connection point (P1, P2, P3, P4), wherein the first and third connection points (P1, P3) are electrically connected to the control connections of the power semiconductor switches (T1, T2), and the second and fourth connection points (P2, P4) are electrically connected to the second load current connections of the power semiconductor switches (T1, T2), wherein in each case a first diode, whose anode faces electrically the first connection point, is connected electrically between the first connection point and the control connections of the power semiconductor switches (T1, T2), wherein in each case a second diode, whose cathode faces electrically the second connection point, is connected electrically between the second connection point and the second load current connections of the power semiconductor switches (T1, T2), wherein in each case a third diode, whose cathode faces electrically the third connection point, is connected electrically between the third connection point and the control connections of the power semiconductor switches (T1, T2), wherein in each case a fourth diode, whose anode faces electrically the fourth connection point, is connected electrically between the fourth connection point and the second load current connections of the power semiconductor switches (T1, T2), and • a drive circuit, wherein the drive circuit is designed in such a way that the drive circuit generates a first electrical potential difference for switching on the power semiconductor switches (T1, T2) between the first and second connection points (P1, P2) and a second electrical potential difference for switching off the power semiconductor switches (T1, T2) between the third and fourth connection points (P3, P4). • at least two power semiconductor switches (T1, T2), which are connected electrically in parallel and each have a first and a second load current connection (C, E) and a control connection, wherein the first load current connections of the power semiconductor switches (T1, T2) are electrically conductively connected to one another and the second load current connections of the power semiconductor switches (T1, T2) are electrically conductively connected to one another, • a drive circuit arrangement, wherein the drive circuit arrangement has a first, second, third and fourth electrical connection point (P1, P2, P3, P4), wherein the first and third connection points (P1, P3) are electrically connected to the control connections of the power semiconductor switches (T1, T2), and the second and fourth connection points (P2, P4) are electrically connected to the second load current connections of the power semiconductor switches (T1, T2), wherein in each case a first diode, whose anode faces electrically the first connection point, is connected electrically between the first connection point and the control connections of the power semiconductor switches (T1, T2), wherein in each case a second diode, whose cathode faces electrically the second connection point, is connected electrically between the second connection point and the second load current connections of the power semiconductor switches (T1, T2), wherein in each case a third diode, whose cathode faces electrically the third connection point, is connected electrically between the third connection point and the control connections of the power semiconductor switches (T1, T2), wherein in each case a fourth diode, whose anode faces electrically the fourth connection point, is connected electrically between the fourth connection point and the second load current connections of the power semiconductor switches (T1, T2), and • a drive circuit, wherein the drive circuit is designed in such a way that the drive circuit generates a first electrical potential difference for switching on the power semiconductor switches (T1, T2) between the first and second connection points (P1, P2) and a second electrical potential difference for switching off the power semiconductor switches (T1, T2) between the third and fourth connection points (P3, P4).