An electronic device, comprising a context setting unit configured to set an interrupt level, in which the electronic device is operated; and a clock circuit comprising: a core-clock postscaler (14; 56) coupled to a clock structure (12; 52, 54) to receive a first signal having a first frequency as a basis for the clock signal and adapted to provide a core-clock signal to a central processing unit of said electronic device, whereby the core clock signal is provided with a core-clock frequency by modifying the first signal; and a bus-clock postscaler (16; 58) coupled to the clock structure (12; 52, 54) to receive the first signal and adapted to provide a bus-clock signal with a bus-clock frequency by modifying the first signal; and a control logic (18; 60, 80, 82) coupled to the core-clock postscaler (14; 56), wherein the control logic is adapted to receive or to poll the current interrupt level communicated by a context setting unit of the electronic device to a status register on change of the interrupt level of the electronic device, the control logic (18; 60, 80, 82) further comprising: a hardware wrapper with a postscale register having a plurality of register entries, wherein each register entry is provided to store a divisor value applicable to the core-clock postscaler (14;56), and wherein said status register is configured to hold the current interrupt level of the electronic device, and wherein the hardware wrapper is configured to select a divisor value based on the interrupt level held in the status register and to pass on the selected divisor value to the core-clock postscaler (14; 56). a core-clock postscaler (14; 56) coupled to a clock structure (12; 52, 54) to receive a first signal having a first frequency as a basis for the clock signal and adapted to provide a core-clock signal to a central processing unit of said electronic device, whereby the core clock signal is provided with a core-clock frequency by modifying the first signal; and a bus-clock postscaler (16; 58) coupled to the clock structure (12; 52, 54) to receive the first signal and adapted to provide a bus-clock signal with a bus-clock frequency by modifying the first signal; and a control logic (18; 60, 80, 82) coupled to the core-clock postscaler (14; 56), wherein the control logic is adapted to receive or to poll the current interrupt level communicated by a context setting unit of the electronic device to a status register on change of the interrupt level of the electronic device, the control logic (18; 60, 80, 82) further comprising: a hardware wrapper with a postscale register having a plurality of register entries, wherein each register entry is provided to store a divisor value applicable to the core-clock postscaler (14;56), and wherein said status register is configured to hold the current interrupt level of the electronic device, and a hardware wrapper with a postscale register having a plurality of register entries, wherein each register entry is provided to store a divisor value applicable to the core-clock postscaler (14;56), and wherein said status register is configured to hold the current interrupt level of the electronic device, and wherein the hardware wrapper is configured to select a divisor value based on the interrupt level held in the status register and to pass on the selected divisor value to the core-clock postscaler (14; 56).