A system, comprising: a volatile storage device; a read-only memory, ROM, configured to store instructions; a memory built-in self-test, BIST, controller; and a central processing unit, CPU, configured to, upon occurrence of an initialization event: execute a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device; execute a second instruction from the ROM to change a value of a program counter to correspond to an address within the volatile storage device at the beginning of the plurality of instructions; execute the plurality of instructions from the volatile storage device using the program counter, the CPU, when executing the plurality of instructions, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM, the instructions including an instruction to change the value of the program counter to correspond to an address within the ROM following the end of the plurality of instructions within the ROM; and execute an instruction from the ROM to determine whether the ROM passed its testing by the memory BIST controller, wherein: the ROM has a first port coupled to the CPU and the ROM has a second port coupled to the memory BIST controller; and when the CPU causes the ROM to enter the test mode, the ROM disables the first port and enables the second port. a volatile storage device; a read-only memory, ROM, configured to store instructions; a memory built-in self-test, BIST, controller; and a central processing unit, CPU, configured to, upon occurrence of an initialization event: execute a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device; execute a second instruction from the ROM to change a value of a program counter to correspond to an address within the volatile storage device at the beginning of the plurality of instructions; execute the plurality of instructions from the volatile storage device using the program counter, the CPU, when executing the plurality of instructions, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM, the instructions including an instruction to change the value of the program counter to correspond to an address within the ROM following the end of the plurality of instructions within the ROM; and execute a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device; execute a second instruction from the ROM to change a value of a program counter to correspond to an address within the volatile storage device at the beginning of the plurality of instructions; execute the plurality of instructions from the volatile storage device using the program counter, the CPU, when executing the plurality of instructions, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM, the instructions including an instruction to change the value of the program counter to correspond to an address within the ROM following the end of the plurality of instructions within the ROM; and the ROM has a first port coupled to the CPU and the ROM has a second port coupled to the memory BIST controller; and when the CPU causes the ROM to enter the test mode, the ROM disables the first port and enables the second port.