A discrete-time analog circuit, comprising: a voltage-current conversion circuit including a first terminal and a second terminal, which is configured to convert a voltage signal that is input to the first terminal into a current signal, and is configured to output the current signal from the second terminal; a history capacitor connected between the second terminal and a ground; and a charge inverting circuit including a third terminal connected to the second terminal, a fourth terminal connected to the ground, and M capacitors (131-1, 131-2, 1431-1, 1434-M), M is an integer greater than or equal to 2, that are provided in parallel between the third terminal and the fourth terminal, wherein the circuit is configured to have each of the M capacitors (131-1, 131-2, 1431-1, 1431-2, 1431-M) repeatedly perform the following operations: - sharing the input charge that is input by the current signal with the history capacitor, by connecting to the third terminal and the fourth terminal in a normal phase manner, - holding at least part of the input charge while not connecting to the third terminal and the fourth terminal, - inverting a polarity of the held charge to share the held charge having the inverted polarity, by connecting to the third terminal and the fourth terminal in a reverse phase manner, and - holding remaining charge while not connecting to the third terminal and the fourth terminal, and wherein during the first and the third operation when one capacitor (131-1, 1431-1) of the M capacitors is connected to the third and fourth terminals, all other capacitors (131-2, 1431-2, 1431-M) of the M capacitors are not connected to the third and fourth terminals such that all the other capacitors (131-2, 1431-2, 1431-M) hold the charge shared in the immediately preceding operation, and wherein during the second and the fourth operation, when the one capacitor (131-1, 1431-1) of the M capacitors is not connected to the third and fourth terminals, all the other capacitors (131-2, 1431-2, 1431-M) of the M capacitors are sequentially connected to the third and fourth terminals such that all the other capacitors (131-2, 1431-2, 1431-M) performs charge sharing by the normal phase connection during the second operation, and invert the polarity of the held charge and performs charge sharing during the fourth operation. a voltage-current conversion circuit including a first terminal and a second terminal, which is configured to convert a voltage signal that is input to the first terminal into a current signal, and is configured to output the current signal from the second terminal; a history capacitor connected between the second terminal and a ground; and a charge inverting circuit including a third terminal connected to the second terminal, a fourth terminal connected to the ground, and M capacitors (131-1, 131-2, 1431-1, 1434-M), M is an integer greater than or equal to 2, that are provided in parallel between the third terminal and the fourth terminal, wherein the circuit is configured to have each of the M capacitors (131-1, 131-2, 1431-1, 1431-2, 1431-M) repeatedly perform the following operations: - sharing the input charge that is input by the current signal with the history capacitor, by connecting to the third terminal and the fourth terminal in a normal phase manner, - holding at least part of the input charge while not connecting to the third terminal and the fourth terminal, - inverting a polarity of the held charge to share the held charge having the inverted polarity, by connecting to the third terminal and the fourth terminal in a reverse phase manner, and - holding remaining charge while not connecting to the third terminal and the fourth terminal, and - sharing the input charge that is input by the current signal with the history capacitor, by connecting to the third terminal and the fourth terminal in a normal phase manner, - holding at least part of the input charge while not connecting to the third terminal and the fourth terminal, - inverting a polarity of the held charge to share the held charge having the inverted polarity, by connecting to the third terminal and the fourth terminal in a reverse phase manner, and - holding remaining charge while not connecting to the third terminal and the fourth terminal, and wherein during the first and the third operation when one capacitor (131-1, 1431-1) of the M capacitors is connected to the third and fourth terminals, all other capacitors (131-2, 1431-2, 1431-M) of the M capacitors are not connected to the third and fourth terminals such that all the other capacitors (131-2, 1431-2, 1431-M) hold the charge shared in the immediately preceding operation, and wherein during the second and the fourth operation, when the one capacitor (131-1, 1431-1) of the M capacitors is not connected to the third and fourth terminals, all the other capacitors (131-2, 1431-2, 1431-M) of the M capacitors are sequentially connected to the third and fourth terminals such that all the other capacitors (131-2, 1431-2, 1431-M) performs charge sharing by the normal phase connection during the second operation, and invert the polarity of the held charge and performs charge sharing during the fourth operation.