A semiconductor device comprising: a logic die have a first surface and an opposed second surface, the logic die extending on a plane; a first via bar and a second via bar, the first and second via bars (608a, 608b) each having a first surface and an opposed second surface, wherein the two via bars (608a, 608b) are on the same plane as the logic die on opposite ends of the logic die, such that the logic die is flanked by each of the first via bar and the second via bar (604a, 604b), the first and second via bars (608a, 608b) comprising glass, wherein one or more through vias, TGVs, are formed within each of the first via bar and the second via bar (608a, 608b) to electrically connect the first surface of the first via bar to the second surface of the first via bar and to electrically connect the first surface of the second via bar to the second surface of the second via bar; a first memory die and a second memory die, the first and second memory dies (606a, 606b) each having a first surface and an opposed second surface; and, a substrate having a first surface, wherein: the second surface of the logic die, the second surface of the first via bar and the second surface of the second via bar are coupled to a first surface of a substrate; the second surface of the first memory die coupled to the first surface of the first via bar and the second surface of the second memory die coupled to the first surface of the second via bar, a portion of the second surface of the first and second memory dies (606a, 606b) extending over the first surface of the logic die, such that both the first and second memory dies (606a, 606b) are vertically staggered over the logic die, such that a portion of the logic die is not overlapped by the first or second memory dies (606a, 606b); the first memory die electrically coupled to the logic die through the first via bar; and the second memory die electrically coupled to the logic die through the second via bar. a logic die have a first surface and an opposed second surface, the logic die extending on a plane; a first via bar and a second via bar, the first and second via bars (608a, 608b) each having a first surface and an opposed second surface, wherein the two via bars (608a, 608b) are on the same plane as the logic die on opposite ends of the logic die, such that the logic die is flanked by each of the first via bar and the second via bar (604a, 604b), the first and second via bars (608a, 608b) comprising glass, wherein one or more through vias, TGVs, are formed within each of the first via bar and the second via bar (608a, 608b) to electrically connect the first surface of the first via bar to the second surface of the first via bar and to electrically connect the first surface of the second via bar to the second surface of the second via bar; a first memory die and a second memory die, the first and second memory dies (606a, 606b) each having a first surface and an opposed second surface; and, a substrate having a first surface, wherein: the second surface of the logic die, the second surface of the first via bar and the second surface of the second via bar are coupled to a first surface of a substrate; the second surface of the first memory die coupled to the first surface of the first via bar and the second surface of the second memory die coupled to the first surface of the second via bar, a portion of the second surface of the first and second memory dies (606a, 606b) extending over the first surface of the logic die, such that both the first and second memory dies (606a, 606b) are vertically staggered over the logic die, such that a portion of the logic die is not overlapped by the first or second memory dies (606a, 606b); the first memory die electrically coupled to the logic die through the first via bar; and the second memory die electrically coupled to the logic die through the second via bar. the second surface of the logic die, the second surface of the first via bar and the second surface of the second via bar are coupled to a first surface of a substrate; the second surface of the first memory die coupled to the first surface of the first via bar and the second surface of the second memory die coupled to the first surface of the second via bar, a portion of the second surface of the first and second memory dies (606a, 606b) extending over the first surface of the logic die, such that both the first and second memory dies (606a, 606b) are vertically staggered over the logic die, such that a portion of the logic die is not overlapped by the first or second memory dies (606a, 606b); the first memory die electrically coupled to the logic die through the first via bar; and the second memory die electrically coupled to the logic die through the second via bar.