A data processing apparatus for segmental processing of input data, the apparatus including: a plurality of data processing sets (32,34,36), each of the plurality of data processing sets comprising a plurality of data processors, a data processor from a data processing set being coupled in series to a corresponding data processor from another data processing set in a manner such that discrete data packets are passed from a data processor from a data processing set to a corresponding data processor in another data processing set; and a central controller configurable to control allocation of the input data to the plurality of data processing sets so as to determine which segment of the input data is to be processed by which data processing set of the plurality of data processing sets, wherein each segment of input data is a portion or section of the input data, the central controller being also for controlling transmission of output data from the apparatus in accordance with either user preferences or predetermined presentation arrangement and being configured to allocate one or more particular data processors to a particular data processing set to bolster a processing power of the particular data processing set; wherein each of the plurality of data processing sets is for processing at least one segment of the input data and wherein each of the plurality of data processing sets includes a set controller which is designated by the central controller, the set controller being one of the plurality of data processors in the data processing set, the set controller being designated for either a permanent or temporary basis and being configured to receive instructions from the central controller for controlling the data processing set of which the set controller is a part; and wherein the discrete data packets are transmitted over a video bus and transmitting discrete data packets over the video bus includes: transmitting data to an output video bus (23(a)) of a first data processor (22(a)); receiving the data at an input video bus (25(b)) of a second data processor (22(b)); transmitting control signals from the first data processor; and receiving the control signals at the second data processor, wherein the control signals determine a flow of data to the second data processor. a plurality of data processing sets (32,34,36), each of the plurality of data processing sets comprising a plurality of data processors, a data processor from a data processing set being coupled in series to a corresponding data processor from another data processing set in a manner such that discrete data packets are passed from a data processor from a data processing set to a corresponding data processor in another data processing set; and a central controller configurable to control allocation of the input data to the plurality of data processing sets so as to determine which segment of the input data is to be processed by which data processing set of the plurality of data processing sets, wherein each segment of input data is a portion or section of the input data, the central controller being also for controlling transmission of output data from the apparatus in accordance with either user preferences or predetermined presentation arrangement and being configured to allocate one or more particular data processors to a particular data processing set to bolster a processing power of the particular data processing set; wherein each of the plurality of data processing sets is for processing at least one segment of the input data and wherein each of the plurality of data processing sets includes a set controller which is designated by the central controller, the set controller being one of the plurality of data processors in the data processing set, the set controller being designated for either a permanent or temporary basis and being configured to receive instructions from the central controller for controlling the data processing set of which the set controller is a part; and wherein the discrete data packets are transmitted over a video bus and transmitting discrete data packets over the video bus includes: transmitting data to an output video bus (23(a)) of a first data processor (22(a)); receiving the data at an input video bus (25(b)) of a second data processor (22(b)); transmitting control signals from the first data processor; and receiving the control signals at the second data processor, wherein the control signals determine a flow of data to the second data processor. transmitting data to an output video bus (23(a)) of a first data processor (22(a)); receiving the data at an input video bus (25(b)) of a second data processor (22(b)); transmitting control signals from the first data processor; and receiving the control signals at the second data processor, wherein the control signals determine a flow of data to the second data processor.