A solid-state imaging device having an imaging area vertically divided into K imaging blocks arranged therein, each imaging block including pixel columns arranged adjacently and all the rows of the imaging device, the device comprising: an image data arithmetic section for specifying a partial readout area of the imaging area in accordance with an input digital video signal, as a rectangular area including the point of maximum brightness; a row selecting circuit for selecting a pixel row corresponding to the partial readout area; a column selecting circuit for selecting a pixel column corresponding to the partial readout area; a timing generating circuit for generating a control signal for selection by the row and column selecting circuits based on an output from the image data arithmetic section; N processing circuits, each connected to a corresponding one of the respective N pixel columns of each of the K imaging blocks via switches that are turned on through the selection by the column selecting circuit, such that each of the N processing circuits is shared among the K imaging blocks (B1, B2, B3); and a plurality of holding circuits, each connected to a respective one of the pixel columns in the imaging area; wherein the n-th processing circuit is connected to the n-th pixel columns in the respective imaging blocks via the switches; the N processing circuits are adapted to generate the digital video signal from a signal for each pixel column selected by the row and column selecting circuits, and the switches are adapted to connect charges accumulated in the holding circuits for the respective pixel columns to the processing circuits corresponding to the selected pixel columns synchronously with the control signal input from the timing generating circuit to the column selecting circuit. an image data arithmetic section for specifying a partial readout area of the imaging area in accordance with an input digital video signal, as a rectangular area including the point of maximum brightness; a row selecting circuit for selecting a pixel row corresponding to the partial readout area; a column selecting circuit for selecting a pixel column corresponding to the partial readout area; a timing generating circuit for generating a control signal for selection by the row and column selecting circuits based on an output from the image data arithmetic section; N processing circuits, each connected to a corresponding one of the respective N pixel columns of each of the K imaging blocks via switches that are turned on through the selection by the column selecting circuit, such that each of the N processing circuits is shared among the K imaging blocks (B1, B2, B3); and a plurality of holding circuits, each connected to a respective one of the pixel columns in the imaging area; wherein the n-th processing circuit is connected to the n-th pixel columns in the respective imaging blocks via the switches; the N processing circuits are adapted to generate the digital video signal from a signal for each pixel column selected by the row and column selecting circuits, and the switches are adapted to connect charges accumulated in the holding circuits for the respective pixel columns to the processing circuits corresponding to the selected pixel columns synchronously with the control signal input from the timing generating circuit to the column selecting circuit.