A method for producing a gate cut in a gate structure (14,15,16) extending transversally with respect to an array of nano-sized semiconductor fins, the method comprising the steps of: - producing said array of semiconductor fins on the front side of a semiconductor substrate, wherein the fins are embedded in a dielectric material (4,4'), and wherein a plurality of rails (5,5') extending parallel to the fins are buried in the substrate and in the dielectric material (4,4'), each rail being present between two adjacent fins, wherein the rails are formed of an electrically conductive material or of a sacrificial material that is to be replaced later by an electrically conductive material, - planarizing the front surface of the dielectric material, followed by recessing the planarized surface of the dielectric material so that top portions of the fins are exposed, the top portions extending outward from the recessed surface, while a portion of said dielectric material remains on top of the rails (5,5'), - producing on the recessed planarized surface at least one gate structure (14,15,16) extending transversally with respect to the fins, and enveloping the top portions of the fins, the gate structure comprising an electrode, a dielectric layer separating the electrode from the top portions of the fins and from the planarized surface, and a gate plug, - from the back side of the substrate, etching at least one trench parallel to and fully overlapping a buried rail (5,5'), - exposing the bottom surface of the rail (5,5') at the bottom of the trench, - from the back side of the substrate, producing an opening in the rail wherein the width of the opening is aligned to the width of the exposed rail, the length of the opening is fully overlapping the width of the gate structure (14,15,16), and wherein a portion of the gate dielectric is exposed at the bottom of the opening, - removing the exposed portion of the gate dielectric at the bottom of the opening, thereby exposing a portion of the gate electrode at the bottom of the opening, followed by: - removing the exposed portion of the gate electrode at the bottom of the opening, to thereby create a gap in the gate electrode, so that the gate electrode is split into a first and second gate electrode portion, and wherein the width of the gap is aligned to the width of the opening, - producing a dielectric layer (24,31) at least on the complete inner surface of the gap, thereby forming a gate cut between said first and second portions of the gate electrode, so that the gate cut is self-aligned to the width of the rail. - producing said array of semiconductor fins on the front side of a semiconductor substrate, wherein the fins are embedded in a dielectric material (4,4'), and wherein a plurality of rails (5,5') extending parallel to the fins are buried in the substrate and in the dielectric material (4,4'), each rail being present between two adjacent fins, wherein the rails are formed of an electrically conductive material or of a sacrificial material that is to be replaced later by an electrically conductive material, - planarizing the front surface of the dielectric material, followed by recessing the planarized surface of the dielectric material so that top portions of the fins are exposed, the top portions extending outward from the recessed surface, while a portion of said dielectric material remains on top of the rails (5,5'), - producing on the recessed planarized surface at least one gate structure (14,15,16) extending transversally with respect to the fins, and enveloping the top portions of the fins, the gate structure comprising an electrode, a dielectric layer separating the electrode from the top portions of the fins and from the planarized surface, and a gate plug, - from the back side of the substrate, etching at least one trench parallel to and fully overlapping a buried rail (5,5'), - exposing the bottom surface of the rail (5,5') at the bottom of the trench, - from the back side of the substrate, producing an opening in the rail wherein the width of the opening is aligned to the width of the exposed rail, the length of the opening is fully overlapping the width of the gate structure (14,15,16), and wherein a portion of the gate dielectric is exposed at the bottom of the opening, - removing the exposed portion of the gate dielectric at the bottom of the opening, thereby exposing a portion of the gate electrode at the bottom of the opening, followed by: - removing the exposed portion of the gate electrode at the bottom of the opening, to thereby create a gap in the gate electrode, so that the gate electrode is split into a first and second gate electrode portion, and wherein the width of the gap is aligned to the width of the opening, - producing a dielectric layer (24,31) at least on the complete inner surface of the gap, thereby forming a gate cut between said first and second portions of the gate electrode, so that the gate cut is self-aligned to the width of the rail.