A branch predictor, comprising: a block address useable to access a block of instruction bytes of an instruction cache of a processor; a first byte offset within the block of instruction bytes; and a second byte offset within the block of instruction bytes; and a conditional branch predictor that comprises a plurality of tables, wherein each table of the plurality of tables has first and second ports and is indexed with its own distinct pair of indexes (164, 166) generated by a hashing logic; wherein the hashing logic hashes a branch pattern and a first address formed from the block address and a first predetermined value to generate a first index and hashes the branch pattern and a second address formed from the block address and a second predetermined value to generate a second index; wherein the first and second predetermined values are different; and wherein the hashing logic hashes a different length of the branch pattern to generate the first/second indexes (164, 166) for each of the plurality of tables; the conditional branch predictor in response generates a corresponding plurality of pairs of direction predictions, and only one of the plurality of pairs of direction predictions is chosen as the respective first and second direction predictions (174, 176) of first and second conditional branch instructions in the block of instruction bytes; and wherein the branch predictor further comprises: a branch target address cache, BTAC, that provides the first and second byte offsets in response to the block address; the BTAC, in response to the block address, also provides first and second branch target address predictions corresponding to the first and second byte offsets; and the branch predictor associates the first direction prediction provided by the conditional branch predictor with the first branch target address prediction provided by the BTAC and associates the second direction prediction provided by the conditional branch predictor with the second branch target address prediction provided by the BTAC. a block address useable to access a block of instruction bytes of an instruction cache of a processor; a first byte offset within the block of instruction bytes; and a second byte offset within the block of instruction bytes; and a conditional branch predictor that comprises a plurality of tables, wherein each table of the plurality of tables has first and second ports and is indexed with its own distinct pair of indexes (164, 166) generated by a hashing logic; wherein the hashing logic hashes a branch pattern and a first address formed from the block address and a first predetermined value to generate a first index and hashes the branch pattern and a second address formed from the block address and a second predetermined value to generate a second index; wherein the first and second predetermined values are different; and wherein the hashing logic hashes a different length of the branch pattern to generate the first/second indexes (164, 166) for each of the plurality of tables; the conditional branch predictor in response generates a corresponding plurality of pairs of direction predictions, and only one of the plurality of pairs of direction predictions is chosen as the respective first and second direction predictions (174, 176) of first and second conditional branch instructions in the block of instruction bytes; and wherein the branch predictor further comprises: a branch target address cache, BTAC, that provides the first and second byte offsets in response to the block address; the BTAC, in response to the block address, also provides first and second branch target address predictions corresponding to the first and second byte offsets; and the branch predictor associates the first direction prediction provided by the conditional branch predictor with the first branch target address prediction provided by the BTAC and associates the second direction prediction provided by the conditional branch predictor with the second branch target address prediction provided by the BTAC. a branch target address cache, BTAC, that provides the first and second byte offsets in response to the block address; the BTAC, in response to the block address, also provides first and second branch target address predictions corresponding to the first and second byte offsets; and the branch predictor associates the first direction prediction provided by the conditional branch predictor with the first branch target address prediction provided by the BTAC and associates the second direction prediction provided by the conditional branch predictor with the second branch target address prediction provided by the BTAC.