A multi-level inverter comprising: - a first bank (S1A-S6A) and a second bank (S1B-S6B) connected in series between an input voltage and a reference voltage; - a third bank (S1C-S6C) and a fourth bank (S1D-S6D) connected in series between the input voltage and the reference voltage; wherein o each bank (S1A-S6A, S1B-S6B, S1C-S6C, S1D-S6D) comprises N MOSFET transistors connected in series, wherein N is equal to or greater than two; - a number of first capacitors (C1-C5), each of the number of first capacitors (C1-C5) connected between two adjacent MOSFET transistors of the first bank (S1A-S6A) and two adjacent MOSFET transistors of the second bank (S1B-S6B); - a number of second capacitors (C6-C10), each of the number of second capacitors (C6-C10) connected between two adj acent MOSFET transistors of the third bank (S1 C-S6C) and two adjacent MOSFET transistors of the fourth bank (S1D-S6D); - a first terminal and a second terminal for providing an AC output voltage there between, wherein ∘ the first terminal is between the first bank (S1A-S6A) and the second bank (S1B-S6B), and ∘ the second terminal is between the third bank (S1C-S6C) and the fourth bank (S1D-S6D); the multi-level inverter being characterised by - a controller configured to selectively couple one or more of the number of first capacitors (C1-C5) to the first terminal and to selectively couple one or more of the number of second capacitors (C6-C10) to the second terminal by: ∘ switching, at staggered times within at least one of a plurality of subsequent switching periods, both the N MOSFET transistors of the first bank (S1AS6A) and the N MOSFET transistors of the fourth bank (S1D-S6D) with N first control signals such that ▪ at each instant of time of the at least one switching period, no more than one of the N MOSFET transistors of the first bank (S1A-S6A) and no more than one of the N MOSFET transistors of the fourth bank (S1D-S6D) is in a respective on-state; ∘ switching both the N MOSFET transistors of the second bank (S1B-S6B) and the N MOSFET transistors of the third bank (S1C-S6C) with N second control signals, the N second control signals corresponding to inverted versions of the N first control signals. - a first bank (S1A-S6A) and a second bank (S1B-S6B) connected in series between an input voltage and a reference voltage; - a third bank (S1C-S6C) and a fourth bank (S1D-S6D) connected in series between the input voltage and the reference voltage; wherein o each bank (S1A-S6A, S1B-S6B, S1C-S6C, S1D-S6D) comprises N MOSFET transistors connected in series, wherein N is equal to or greater than two; - a number of first capacitors (C1-C5), each of the number of first capacitors (C1-C5) connected between two adjacent MOSFET transistors of the first bank (S1A-S6A) and two adjacent MOSFET transistors of the second bank (S1B-S6B); - a number of second capacitors (C6-C10), each of the number of second capacitors (C6-C10) connected between two adj acent MOSFET transistors of the third bank (S1 C-S6C) and two adjacent MOSFET transistors of the fourth bank (S1D-S6D); - a first terminal and a second terminal for providing an AC output voltage there between, wherein ∘ the first terminal is between the first bank (S1A-S6A) and the second bank (S1B-S6B), and ∘ the second terminal is between the third bank (S1C-S6C) and the fourth bank (S1D-S6D); the multi-level inverter being characterised by ∘ the first terminal is between the first bank (S1A-S6A) and the second bank (S1B-S6B), and ∘ the second terminal is between the third bank (S1C-S6C) and the fourth bank (S1D-S6D); the multi-level inverter being characterised by - a controller configured to selectively couple one or more of the number of first capacitors (C1-C5) to the first terminal and to selectively couple one or more of the number of second capacitors (C6-C10) to the second terminal by: ∘ switching, at staggered times within at least one of a plurality of subsequent switching periods, both the N MOSFET transistors of the first bank (S1AS6A) and the N MOSFET transistors of the fourth bank (S1D-S6D) with N first control signals such that ▪ at each instant of time of the at least one switching period, no more than one of the N MOSFET transistors of the first bank (S1A-S6A) and no more than one of the N MOSFET transistors of the fourth bank (S1D-S6D) is in a respective on-state; ∘ switching both the N MOSFET transistors of the second bank (S1B-S6B) and the N MOSFET transistors of the third bank (S1C-S6C) with N second control signals, the N second control signals corresponding to inverted versions of the N first control signals. ∘ switching, at staggered times within at least one of a plurality of subsequent switching periods, both the N MOSFET transistors of the first bank (S1AS6A) and the N MOSFET transistors of the fourth bank (S1D-S6D) with N first control signals such that ▪ at each instant of time of the at least one switching period, no more than one of the N MOSFET transistors of the first bank (S1A-S6A) and no more than one of the N MOSFET transistors of the fourth bank (S1D-S6D) is in a respective on-state; ∘ switching both the N MOSFET transistors of the second bank (S1B-S6B) and the N MOSFET transistors of the third bank (S1C-S6C) with N second control signals, the N second control signals corresponding to inverted versions of the N first control signals.