An insulated gate bipolar transistor comprising at least two first cells (1, 1'), each of which having following layers from a metal emitter electrode on an emitter side to a collector electrode on a collector side opposite to the emitter side: - a source layer of a first conductivity type, - a base layer of a second conductivity type, which is different from the first conductivity type, wherein the source layer and the base layer contact the metal emitter electrode, - an enhancement layer of the first conductivity type having higher doping concentration than a drift layer, wherein the base layer separates the source layer from the enhancement layer, - the drift layer of the first conductivity type, wherein the enhancement layer separates the base layer from the drift layer, - a collector layer of the second conductivity type, which is arranged between the drift layer and the collector electrode and which electrically contacts the collector electrode, - two trench gate electrodes (7, 7'), each of which comprises an electrically conductive gate layer (70, 70'), which is arranged lateral to the base layer, extends deeper into the drift layer than the base layer and has a gate layer thickness, and a gate insulating layer (72, 72'), which separates the gate layer (70, 70') from any doped layer, wherein a channel is formable between the source layer, the base layer, the enhancement layer and the drift layer, wherein the insulated gate bipolar transistor comprises at least one second cell which is arranged between two neighboured first cells (1, 1') and which has following layer on the emitter side: a well of the second conductivity type, which is arranged between two trench gate electrodes (7, 7') of the neighboured first cells (1, 1'), which well extends at least to the gate layer thickness, characterized in that - further enhancement layers (40, 40') of the first conductivity type having higher doping concentration than the drift layer are arranged between the well and the neighboured trench gate electrodes (7, 7') such that the further enhancement layers (40, 40') extend to the emitter side, - an insulator layer stack is arranged on top of the second cell on the emitter side to insulate the second cell and the neighboured trench gate electrodes (7, 7') from the metal emitter electrode, which consists of a first insulating layer and a second insulating layer, wherein the insulator stack has a thickness on top of the well of a first layer thickness plus the second insulating layer thickness and a thickness on top of the gate layer (70, 70') of the second insulating layer thickness, wherein each thickness of the first insulating layer and the second insulating layer is at least 700 nm. - a source layer of a first conductivity type, - a base layer of a second conductivity type, which is different from the first conductivity type, wherein the source layer and the base layer contact the metal emitter electrode, - an enhancement layer of the first conductivity type having higher doping concentration than a drift layer, wherein the base layer separates the source layer from the enhancement layer, - the drift layer of the first conductivity type, wherein the enhancement layer separates the base layer from the drift layer, - a collector layer of the second conductivity type, which is arranged between the drift layer and the collector electrode and which electrically contacts the collector electrode, - two trench gate electrodes (7, 7'), each of which comprises an electrically conductive gate layer (70, 70'), which is arranged lateral to the base layer, extends deeper into the drift layer than the base layer and has a gate layer thickness, and a gate insulating layer (72, 72'), which separates the gate layer (70, 70') from any doped layer, - further enhancement layers (40, 40') of the first conductivity type having higher doping concentration than the drift layer are arranged between the well and the neighboured trench gate electrodes (7, 7') such that the further enhancement layers (40, 40') extend to the emitter side, - an insulator layer stack is arranged on top of the second cell on the emitter side to insulate the second cell and the neighboured trench gate electrodes (7, 7') from the metal emitter electrode, which consists of a first insulating layer and a second insulating layer, wherein the insulator stack has a thickness on top of the well of a first layer thickness plus the second insulating layer thickness and a thickness on top of the gate layer (70, 70') of the second insulating layer thickness, wherein each thickness of the first insulating layer and the second insulating layer is at least 700 nm.