A display panel comprising a pixel circuit array and a driving circuit electrically connected to the pixel circuit array, the pixel circuit array comprising a plurality of pixel circuits, each pixel circuit is configured to control display for a single pixel or sub-pixel of the display panel, wherein each pixel circuit in an N-th row of the pixel circuit array comprises: a capacitor; a capacitor charging transistor for charging the capacitor, a gate of the capacitor charging transistor being electrically connected to a gate line of a (N-1)-th row; a first capacitor discharging transistor, a gate of which is electrically connected to a gate line of the N-th row; and a second capacitor discharging transistor, a gate of which is electrically connected to a data line; wherein the capacitor is charged to a first voltage when the capacitor charging transistor is turned on, the capacitor is connected in series with the first capacitor discharging transistor and the second capacitor discharging transistor to form a discharge circuit, wherein the capacitor is discharged when the first capacitor discharging transistor and the second capacitor discharging transistor are turned on so that a voltage across the capacitor drops from the first voltage to a pixel voltage, wherein N is an integer greater than or equal to 2, wherein the driving circuit comprises a charging power supply for providing a charging voltage for charging the capacitor to the first voltage greater than the pixel voltage; a gate drive module for providing a gate signal to the gate line (110, 120), and a pixel voltage control module configured to provide a data signal (Data) to the data line that turns on the second capacitor discharging transistor to enable the voltage across the capacitor to drop from the first voltage to the pixel voltage, characterized in that, the charging power supply comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor being mutually complementary transistors, a drain of the third transistor and a drain of the fourth transistor being both electrically connected to an output of the charging power supply, a gate of the third transistor and a gate of the fourth transistor being controlled by a polarity reversal control signal, wherein an output of the charging power supply is electrically connected to the capacitor charging transistor to supply the charging voltage. a capacitor; a capacitor charging transistor for charging the capacitor, a gate of the capacitor charging transistor being electrically connected to a gate line of a (N-1)-th row; a first capacitor discharging transistor, a gate of which is electrically connected to a gate line of the N-th row; and a second capacitor discharging transistor, a gate of which is electrically connected to a data line; wherein the capacitor is charged to a first voltage when the capacitor charging transistor is turned on, the capacitor is connected in series with the first capacitor discharging transistor and the second capacitor discharging transistor to form a discharge circuit, wherein the capacitor is discharged when the first capacitor discharging transistor and the second capacitor discharging transistor are turned on so that a voltage across the capacitor drops from the first voltage to a pixel voltage, wherein N is an integer greater than or equal to 2, wherein the driving circuit comprises a charging power supply for providing a charging voltage for charging the capacitor to the first voltage greater than the pixel voltage; a gate drive module for providing a gate signal to the gate line (110, 120), and a pixel voltage control module configured to provide a data signal (Data) to the data line that turns on the second capacitor discharging transistor to enable the voltage across the capacitor to drop from the first voltage to the pixel voltage, characterized in that, the charging power supply comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor being mutually complementary transistors, a drain of the third transistor and a drain of the fourth transistor being both electrically connected to an output of the charging power supply, a gate of the third transistor and a gate of the fourth transistor being controlled by a polarity reversal control signal, wherein an output of the charging power supply is electrically connected to the capacitor charging transistor to supply the charging voltage.