A system comprising: a host processor (102; 202) having a network interface (106; 206) to receive packets for transmission; a plurality of radio devices (130, 132); and a switching interface (116; 216) comprising: a switch (118; 218) having an input coupled to an interface (108; 208) of the host processor and a plurality of outputs, each output being coupled to a respective one of the plurality of radio devices (130, 132); and a memory (124;224) associated with the switch (118; 218); wherein the switch is adapted to receive from the host processor via the input a packet to be forwarded to a destination device comprising the radio device associated with one of the plurality of outputs, wherein the switch is responsive to store the received packet in the associated memory, wherein the host processor has logic for signalling the destination radio device when the packet has been transferred to the memory associated with the switch, wherein the radio device has logic to retrieve the packet from the memory associated with a switch when the radio device is ready to process the packet, and wherein the switch is responsive to a signal from the destination device to forward the packet from the associated memory to the destination device through the one of the plurality of outputs, wherein the switching interface (116; 216) further comprises: a packet encryption engine coupled between the input and the associated memory and the packet encryption engine is responsive to the packet being received from the input to encrypt the packet before storing the packet in the associated memory. a host processor (102; 202) having a network interface (106; 206) to receive packets for transmission; a plurality of radio devices (130, 132); and a switching interface (116; 216) comprising: a switch (118; 218) having an input coupled to an interface (108; 208) of the host processor and a plurality of outputs, each output being coupled to a respective one of the plurality of radio devices (130, 132); and a memory (124;224) associated with the switch (118; 218); wherein the switch is adapted to receive from the host processor via the input a packet to be forwarded to a destination device comprising the radio device associated with one of the plurality of outputs, wherein the switch is responsive to store the received packet in the associated memory, wherein the host processor has logic for signalling the destination radio device when the packet has been transferred to the memory associated with the switch, wherein the radio device has logic to retrieve the packet from the memory associated with a switch when the radio device is ready to process the packet, and wherein the switch is responsive to a signal from the destination device to forward the packet from the associated memory to the destination device through the one of the plurality of outputs, wherein the switching interface (116; 216) further comprises: a packet encryption engine coupled between the input and the associated memory and the packet encryption engine is responsive to the packet being received from the input to encrypt the packet before storing the packet in the associated memory. a switch (118; 218) having an input coupled to an interface (108; 208) of the host processor and a plurality of outputs, each output being coupled to a respective one of the plurality of radio devices (130, 132); and a memory (124;224) associated with the switch (118; 218); wherein the switch is adapted to receive from the host processor via the input a packet to be forwarded to a destination device comprising the radio device associated with one of the plurality of outputs, wherein the switch is responsive to store the received packet in the associated memory, wherein the host processor has logic for signalling the destination radio device when the packet has been transferred to the memory associated with the switch, wherein the radio device has logic to retrieve the packet from the memory associated with a switch when the radio device is ready to process the packet, and wherein the switch is responsive to a signal from the destination device to forward the packet from the associated memory to the destination device through the one of the plurality of outputs, wherein the switching interface (116; 216) further comprises: a packet encryption engine coupled between the input and the associated memory and the packet encryption engine is responsive to the packet being received from the input to encrypt the packet before storing the packet in the associated memory. a packet encryption engine coupled between the input and the associated memory and the packet encryption engine is responsive to the packet being received from the input to encrypt the packet before storing the packet in the associated memory.