A digital signal processor comprising: - a processor core including an integer execution unit configured to execute integer instructions; and - at least a first and a second vector execution unit (203, 205, 520, 530) separate from and coupled to the processor core said vector execution units having a first and a second number of datapaths, respectively, each of said vector execution units being arranged to execute instructions, including vector instructions that are to be performed on multiple complex-valued data words in the form of a vector, and to return a signal when it is finished indicating to the core that it is ready, each instruction being comprised in an instruction word; - at least a first memory unit (230, 231) comprising data to be worked on by the first and second vector execution unit (203, 205, 520, 530) - An on-chip network interconnecting the processor core, the vector execution units (203, 205, 520, 530) and the at least one memory unit (230, 231), - said digital signal processor comprising a program memory arranged to hold instructions for the first and second vector execution unit (203, 205, 520, 530) and issue logic for issuing instructions, including vector instructions, to the first and second vector execution unit, said digital signal processor being characterized in that the processor comprises at least one control unit (705; 213, 223) for controlling, based on an issue signal extracted from an instruction word at least two execution units that are to receive and execute the instruction comprised in the instruction word at the same time, and logic for sending the instruction to said at least two execution units. - a processor core including an integer execution unit configured to execute integer instructions; and - at least a first and a second vector execution unit (203, 205, 520, 530) separate from and coupled to the processor core said vector execution units having a first and a second number of datapaths, respectively, each of said vector execution units being arranged to execute instructions, including vector instructions that are to be performed on multiple complex-valued data words in the form of a vector, and to return a signal when it is finished indicating to the core that it is ready, each instruction being comprised in an instruction word; - at least a first memory unit (230, 231) comprising data to be worked on by the first and second vector execution unit (203, 205, 520, 530) - An on-chip network interconnecting the processor core, the vector execution units (203, 205, 520, 530) and the at least one memory unit (230, 231), - said digital signal processor comprising a program memory arranged to hold instructions for the first and second vector execution unit (203, 205, 520, 530) and issue logic for issuing instructions, including vector instructions, to the first and second vector execution unit, said digital signal processor being characterized in that the processor comprises at least one control unit (705; 213, 223) for controlling, based on an issue signal extracted from an instruction word at least two execution units that are to receive and execute the instruction comprised in the instruction word at the same time, and logic for sending the instruction to said at least two execution units.