A method of programming a FPGA comprising the steps of: a) providing a high-level configuration file b) converting said high-level configuration file into a bitstream file; and c) uploading said bitstream file into the FPGA; characterized in that: said FPGA comprises - an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network (LICN), - each said interconnection network comprising a set of ports (P 0 - P 4W+L-1) connected to respective ports of the interconnection networks and hardware blocks of adjacent macrocells, of hardware blocks or block of the same macrocell and/or to input/output blocks of the FPGA, and wherein - each said interconnection network (LCIN) comprises a set of switches for performing local routing within the interconnection network; - in that said high-level configuration file comprises: ∘ first data defining a set of macrocells and their relative positions; ∘ second data defining a configuration of the hardware blocks of said macrocells; and ∘ third data defining interconnections between said macrocells and a description of the connections between the ports of each said interconnection network, but not of the statuses of said switches; but neither data defining an absolute position of said macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; and in that said step b) comprises: b1) using at least said first data of said high-level configuration file for determining the absolute positions of said macrocells within said FPGA; b2) using at least said third data of said high-level configuration file for determining the local routing information fully defining a configuration of the interconnection networks of said macrocells; and b3) generating said bitstream file, containing information defining said absolute positions, said second data of said high-level configuration file and said local routing information, a format of said bitstream file being dependent on an architecture of said FPGA. a) providing a high-level configuration file b) converting said high-level configuration file into a bitstream file; and c) uploading said bitstream file into the FPGA; - an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network (LICN), - each said interconnection network comprising a set of ports (P 0 - P 4W+L-1) connected to respective ports of the interconnection networks and hardware blocks of adjacent macrocells, of hardware blocks or block of the same macrocell and/or to input/output blocks of the FPGA, and wherein - each said interconnection network (LCIN) comprises a set of switches for performing local routing within the interconnection network; - each said interconnection network comprising a set of ports (P 0 - P 4W+L-1) connected to respective ports of the interconnection networks and hardware blocks of adjacent macrocells, of hardware blocks or block of the same macrocell and/or to input/output blocks of the FPGA, and wherein - each said interconnection network (LCIN) comprises a set of switches for performing local routing within the interconnection network; - in that said high-level configuration file comprises: ∘ first data defining a set of macrocells and their relative positions; ∘ second data defining a configuration of the hardware blocks of said macrocells; and ∘ third data defining interconnections between said macrocells and a description of the connections between the ports of each said interconnection network, but not of the statuses of said switches; ∘ first data defining a set of macrocells and their relative positions; ∘ second data defining a configuration of the hardware blocks of said macrocells; and ∘ third data defining interconnections between said macrocells and a description of the connections between the ports of each said interconnection network, but not of the statuses of said switches; b1) using at least said first data of said high-level configuration file for determining the absolute positions of said macrocells within said FPGA; b2) using at least said third data of said high-level configuration file for determining the local routing information fully defining a configuration of the interconnection networks of said macrocells; and b3) generating said bitstream file, containing information defining said absolute positions, said second data of said high-level configuration file and said local routing information, a format of said bitstream file being dependent on an architecture of said FPGA.