An error correction system, applied to a memory system which is configured to, during a read or write operation, write or read a plurality of data, wherein the plurality of data are divided into M bytes, each having N data with different bits, and the memory system has an encoding stage and a decoding stage, during the decoding stage, the error correction system generates X first operation codes and Y second operation codes based on the memory system, wherein the first operation codes are configured for at least one of error detection or error correction on the N data, and the second operation codes are configured for at least one of error detection or error correction on the M bytes; characterised by the error correction system comprising: M decoding units, each corresponding to a respective one of the bytes, and configured to perform decoding on the X first operation codes and the Y second operation codes to determine whether the respective byte has erroneous data and to locate one or more bits of the erroneous data; wherein each of the decoding units comprises: a decoder, configured to receive the X first operation codes and output N first decoded signals, each of the N first decoded signals corresponding to a respective one bit of the N data, and N being greater than X; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes, the selected operation codes being a subset of the Y second operation codes corresponding to the respective byte; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y-Z) unselected operation codes, the unselected operation codes being second operation codes other than the selected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals, wherein at least one of error detection or error correction is performed on the memory system based on the output of the N second AND gate units, wherein each of X, Y and N is a positive natural number, and Z is an integer which is greater than or equal to (Y-1)/2 and smaller than or equal to (Y+1)/2. M decoding units, each corresponding to a respective one of the bytes, and configured to perform decoding on the X first operation codes and the Y second operation codes to determine whether the respective byte has erroneous data and to locate one or more bits of the erroneous data; wherein each of the decoding units comprises: a decoder, configured to receive the X first operation codes and output N first decoded signals, each of the N first decoded signals corresponding to a respective one bit of the N data, and N being greater than X; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes, the selected operation codes being a subset of the Y second operation codes corresponding to the respective byte; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y-Z) unselected operation codes, the unselected operation codes being second operation codes other than the selected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals, wherein at least one of error detection or error correction is performed on the memory system based on the output of the N second AND gate units, a decoder, configured to receive the X first operation codes and output N first decoded signals, each of the N first decoded signals corresponding to a respective one bit of the N data, and N being greater than X; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes, the selected operation codes being a subset of the Y second operation codes corresponding to the respective byte; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y-Z) unselected operation codes, the unselected operation codes being second operation codes other than the selected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals, wherein at least one of error detection or error correction is performed on the memory system based on the output of the N second AND gate units, wherein each of X, Y and N is a positive natural number, and Z is an integer which is greater than or equal to (Y-1)/2 and smaller than or equal to (Y+1)/2.