A process used in fabricating a metal-insulator-semiconductor field-effect transistor, MISFET, that comprises a first region corresponding to an active region and a second region corresponding to a termination region, said process comprising: forming a gate oxide layer over at least said first region, depositing a polysilicon layer on the gate oxide layer over at least said first region; removing a portion of said gate oxide layer and said polysilicon layer to expose an area of said first region in which a first conductivity-type dopant source region, a second conductivity-type dopant body region, and a second conductivity-type dopant implant region below said first conductivity-type dopant source region are subsequently formed; and after forming said first conductivity-type dopant source region and said second conductivity-type dopant body region, and before forming said second conductivity-type dopant implant region, forming a spacer in contact with a remaining portion of said gate oxide layer and said polysilicon layer and also in contact with said first conductivity-type dopant source region; thereafter depositing a second oxide layer over said first region and said second region, said second region thereby comprising a first oxide layer between said second oxide layer and an epitaxial layer; forming a mask over said first and said second region, said mask comprising a first plurality of mask elements separated by gaps over said second region, said mask further comprising a second plurality of mask elements over said first region, said mask elements in said second plurality separated by a gap; removing parts of said second oxide layer and said first oxide layer in said second region that are exposed through said gaps in said first plurality of mask elements, thereby exposing said epitaxial layer, and removing parts of said second oxide layer and said first conductivity-type dopant source region in said first region that are exposed through said gap in said second plurality of mask elements, thereby exposing said second conductivity-type dopant implant region; implanting said second conductivity-type dopant into said epitaxial layer through openings formed in said second region by said removing parts of said second oxide layer and said first oxide layer in said second region, thereby forming field rings for said MISFET; forming a metal layer in contact with said first conductivity-type dopant source region and said second conductivity-type dopant implant region in said first region; and thereafter forming a passivation layer over said first and second regions, said passivation layer extending into said openings in said second region formed by said removing parts of said second oxide layer and said first oxide layer in said second region. forming a gate oxide layer over at least said first region, depositing a polysilicon layer on the gate oxide layer over at least said first region; removing a portion of said gate oxide layer and said polysilicon layer to expose an area of said first region in which a first conductivity-type dopant source region, a second conductivity-type dopant body region, and a second conductivity-type dopant implant region below said first conductivity-type dopant source region are subsequently formed; and after forming said first conductivity-type dopant source region and said second conductivity-type dopant body region, and before forming said second conductivity-type dopant implant region, forming a spacer in contact with a remaining portion of said gate oxide layer and said polysilicon layer and also in contact with said first conductivity-type dopant source region; thereafter depositing a second oxide layer over said first region and said second region, said second region thereby comprising a first oxide layer between said second oxide layer and an epitaxial layer; forming a mask over said first and said second region, said mask comprising a first plurality of mask elements separated by gaps over said second region, said mask further comprising a second plurality of mask elements over said first region, said mask elements in said second plurality separated by a gap; removing parts of said second oxide layer and said first oxide layer in said second region that are exposed through said gaps in said first plurality of mask elements, thereby exposing said epitaxial layer, and removing parts of said second oxide layer and said first conductivity-type dopant source region in said first region that are exposed through said gap in said second plurality of mask elements, thereby exposing said second conductivity-type dopant implant region; implanting said second conductivity-type dopant into said epitaxial layer through openings formed in said second region by said removing parts of said second oxide layer and said first oxide layer in said second region, thereby forming field rings for said MISFET; forming a metal layer in contact with said first conductivity-type dopant source region and said second conductivity-type dopant implant region in said first region; and thereafter forming a passivation layer over said first and second regions, said passivation layer extending into said openings in said second region formed by said removing parts of said second oxide layer and said first oxide layer in said second region.