A control system to control at least two electric motors driving a vehicle; the control system comprises: a first processing core, which is configured to, in a control cycle N and for a first electric motor, determine a first electric current target (I TRG_R) based on a first torque or speed target (T TRG_R) and, hence, control a first electronic power converter connected to the first electric motor so as to pursue the first electric current target (I TRG_R); a second processing core, which is configured to, in the control cycle N and for a second electric motor, determine a second electric current target (I TRG_L) based on a second torque or speed target (T TRG_L) and, hence, control a second electronic power converter connected to the second electric motor so as to pursue the second electric current target (I TRG_L); and a third processing core operating as master, which is configured to acquire the first and the second torque or speed target (T TRG_R, T TRC_L) and, hence, transmit in a synchronized manner the first and the second torque or speed target (T TRG_R, T TRG_L) to the first and to the second processing core (14, 15) operating as slaves; the control system is characterized in that: the three processing cores (13, 14, 15) are all part of a same and single multi-core microprocessor which uses a single clock signal which is thus common to all three processing cores (13, 14, 15); the third processing core is configured to carry out a monitoring of the presence of operation in the first and in the second processing core (14, 15); and the third processing core is configured to check whether the inputs of the first and of the second processing core (14, 15) are synchronized with one another, to check whether the outputs of the first and of the second processing core (14, 15) are synchronized with one another, and to carry out, if the inputs and/or the outputs of the first and of the second processing core (14, 15) are not synchronized with one another, an emergency recovery procedure wherein the third processing core takes direct control of the electronic power converters, overwriting the outputs of the first and of the second processing core (14, 15). a first processing core, which is configured to, in a control cycle N and for a first electric motor, determine a first electric current target (I TRG_R) based on a first torque or speed target (T TRG_R) and, hence, control a first electronic power converter connected to the first electric motor so as to pursue the first electric current target (I TRG_R); a second processing core, which is configured to, in the control cycle N and for a second electric motor, determine a second electric current target (I TRG_L) based on a second torque or speed target (T TRG_L) and, hence, control a second electronic power converter connected to the second electric motor so as to pursue the second electric current target (I TRG_L); and a third processing core operating as master, which is configured to acquire the first and the second torque or speed target (T TRG_R, T TRC_L) and, hence, transmit in a synchronized manner the first and the second torque or speed target (T TRG_R, T TRG_L) to the first and to the second processing core (14, 15) operating as slaves; the control system is characterized in that: the three processing cores (13, 14, 15) are all part of a same and single multi-core microprocessor which uses a single clock signal which is thus common to all three processing cores (13, 14, 15); the third processing core is configured to carry out a monitoring of the presence of operation in the first and in the second processing core (14, 15); and the third processing core is configured to check whether the inputs of the first and of the second processing core (14, 15) are synchronized with one another, to check whether the outputs of the first and of the second processing core (14, 15) are synchronized with one another, and to carry out, if the inputs and/or the outputs of the first and of the second processing core (14, 15) are not synchronized with one another, an emergency recovery procedure wherein the third processing core takes direct control of the electronic power converters, overwriting the outputs of the first and of the second processing core (14, 15). the three processing cores (13, 14, 15) are all part of a same and single multi-core microprocessor which uses a single clock signal which is thus common to all three processing cores (13, 14, 15); the third processing core is configured to carry out a monitoring of the presence of operation in the first and in the second processing core (14, 15); and the third processing core is configured to check whether the inputs of the first and of the second processing core (14, 15) are synchronized with one another, to check whether the outputs of the first and of the second processing core (14, 15) are synchronized with one another, and to carry out, if the inputs and/or the outputs of the first and of the second processing core (14, 15) are not synchronized with one another, an emergency recovery procedure wherein the third processing core takes direct control of the electronic power converters, overwriting the outputs of the first and of the second processing core (14, 15).