A protection circuit comprising: a power supply terminal; a ground terminal; and first to third transistors (M1, M2, M3), for preventing application of voltage in a reverse direction to a circuit unit having a predetermined function, wherein the first transistor has one of a source and a drain connected to the power supply terminal and a gate connected to the ground terminal and has the other one of the source and drain connected to a first region including a region where a channel is to be formed in the first transistor; the second transistor has one of a source and a drain connected to a second region including a region where a channel is to be formed in the second transistor and the other one of the source and drain of the first transistor, a gate connected to the power supply terminal, the other one of the source and drain connected to the ground terminal; the third transistor has one of a source and a drain connected to the power supply terminal, a gate connected to the ground terminal, the other one of the source and drain connected to the ground terminal through the circuit unit; the first region and the second region are integrally formed in a first N-well and are connected to a third region formed in a second N-well including a region where a channel is formed in the third transistor, wherein the first N-well having the first and second regions and a second N-well having the third region are separated, wherein the first and second N-wells (112, 113) are electrically coupled through a first high concentration N-type region and a second high concentration N-type region and have potentials that are substantially equal. a power supply terminal; a ground terminal; and first to third transistors (M1, M2, M3), for preventing application of voltage in a reverse direction to a circuit unit having a predetermined function, wherein the first transistor has one of a source and a drain connected to the power supply terminal and a gate connected to the ground terminal and has the other one of the source and drain connected to a first region including a region where a channel is to be formed in the first transistor; the second transistor has one of a source and a drain connected to a second region including a region where a channel is to be formed in the second transistor and the other one of the source and drain of the first transistor, a gate connected to the power supply terminal, the other one of the source and drain connected to the ground terminal; the third transistor has one of a source and a drain connected to the power supply terminal, a gate connected to the ground terminal, the other one of the source and drain connected to the ground terminal through the circuit unit; the first region and the second region are integrally formed in a first N-well and are connected to a third region formed in a second N-well including a region where a channel is formed in the third transistor, wherein the first N-well having the first and second regions and a second N-well having the third region are separated, wherein the first and second N-wells (112, 113) are electrically coupled through a first high concentration N-type region and a second high concentration N-type region and have potentials that are substantially equal.