A voltage level shifter, VLS, circuit, comprising: a pre-conditioning circuit configured to: receive an input signal in a first voltage domain; and generate a pre-conditioned input signal on an input node in the first voltage domain at a voltage level on the input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase; a pre-charge circuit coupled to an output node and a first supply rail of a supply voltage relative to a second supply rail in a second voltage domain higher than the first voltage domain, the pre-charge circuit configured to couple the first supply rail to the output node in response to a pre-charge control signal indicating the pre-charge phase; a pull-up circuit coupled to the first supply rail and the output node, the pull-up circuit configured to couple the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state, and in response to the pre-condition control signal, CTRL L, and the pre-charge control signal, CTRL H, having a voltage level of a discharge logical high state indicating an evaluation phase; and a pull-down circuit coupled to the input node and the second supply rail, the pull-down circuit configured to: decouple the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase; and couple the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal, CTRL L, and the pre-charge control signal, CTRL H, having a voltage level of a discharge logical high state indicating the evaluation phase. a pre-conditioning circuit configured to: receive an input signal in a first voltage domain; and generate a pre-conditioned input signal on an input node in the first voltage domain at a voltage level on the input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase; receive an input signal in a first voltage domain; and generate a pre-conditioned input signal on an input node in the first voltage domain at a voltage level on the input node indicating a charge logic state, in response to a pre-condition control signal having a voltage level of the charge logic state indicating a pre-charge phase; a pre-charge circuit coupled to an output node and a first supply rail of a supply voltage relative to a second supply rail in a second voltage domain higher than the first voltage domain, the pre-charge circuit configured to couple the first supply rail to the output node in response to a pre-charge control signal indicating the pre-charge phase; a pull-up circuit coupled to the first supply rail and the output node, the pull-up circuit configured to couple the first supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the charge logic state, and in response to the pre-condition control signal, CTRL L, and the pre-charge control signal, CTRL H, having a voltage level of a discharge logical high state indicating an evaluation phase; and a pull-down circuit coupled to the input node and the second supply rail, the pull-down circuit configured to: decouple the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase; and couple the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal, CTRL L, and the pre-charge control signal, CTRL H, having a voltage level of a discharge logical high state indicating the evaluation phase. decouple the second supply rail from the output node in response to the pre-condition control signal indicating the pre-charge phase; and couple the second supply rail to the output node in response to the pre-conditioned input signal having a voltage level of the discharge logic state, and in response to the pre-condition control signal, CTRL L, and the pre-charge control signal, CTRL H, having a voltage level of a discharge logical high state indicating the evaluation phase.