A method of operating a processor for computing a dot product between a first vector including a plurality of weights and a second vector including a plurality of activations, comprising: arranging the plurality of weights in a first input register of the processor and the plurality of activations in a second input register of the processor, wherein both the first input register and the second input register each have a same number of bits and wherein the number of bits used for the representation of each weight in the first input register and of each activation in the second input register is the same and is smaller than the number of bits of the first and the second input register (710, 720), wherein the weights are arranged in the first input register in a first order, wherein the activations are arranged in the second input register in a second order that is a reverse order of the first order, wherein a same number of bits separates each pair of two weights in the first input register that directly follow each other as well as each pair of two activations in the second input register that directly follow each other, wherein a first and a last of the weights in the first input register and a first and a last of the activations in the second input register are maximally separated from each other in the first input register and in the second input register, respectively; performing, by the processor (1420, 1520), a multiplication between values stored in the first input register and values stored in the second input register; storing a result of the multiplication in an output register of the processor (1420, 1520), wherein the output register has a greater number of bits than the input registers (710, 720); and outputting, from the output register, a value in a preset bit range as a result of the dot product. arranging the plurality of weights in a first input register of the processor and the plurality of activations in a second input register of the processor, wherein both the first input register and the second input register each have a same number of bits and wherein the number of bits used for the representation of each weight in the first input register and of each activation in the second input register is the same and is smaller than the number of bits of the first and the second input register (710, 720), wherein the weights are arranged in the first input register in a first order, wherein the activations are arranged in the second input register in a second order that is a reverse order of the first order, wherein a same number of bits separates each pair of two weights in the first input register that directly follow each other as well as each pair of two activations in the second input register that directly follow each other, wherein a first and a last of the weights in the first input register and a first and a last of the activations in the second input register are maximally separated from each other in the first input register and in the second input register, respectively; performing, by the processor (1420, 1520), a multiplication between values stored in the first input register and values stored in the second input register; storing a result of the multiplication in an output register of the processor (1420, 1520), wherein the output register has a greater number of bits than the input registers (710, 720); and outputting, from the output register, a value in a preset bit range as a result of the dot product.