An apparatus for performing a convolution comprising: a bitcell array to perform a multiply-accumulate operation using a multibit weight and a multibit input, wherein the bitcell array comprises a plurality of bitcells, and wherein each bitcell of the bitcell array comprises a corresponding memory unit to store a corresponding weight bit of the multibit weight, a corresponding multiplication unit to multiply the corresponding weight bit by an input bit of the multibit input, and a corresponding output capacitor to store a result of the multiplication; sample-and-hold circuits (300, 400, 500) coupled to the output capacitors of corresponding columns of bitcells, each sample-and-hold circuit comprising a corresponding holding capacitor (304, 506, 508) to store a charge representing a partial MAC result for the corresponding column; an input buffer to serially send input bits of the multibit input to the bitcell array to be multiplied by the multibit weights in a series of input cycles, wherein each sample-and-hold circuit is configured to, in each input cycle of said series of input cycles: sample a voltage on a corresponding column line coupled to the corresponding output capacitors in order to provide a sampled charge; if the input cycle is after the first occurring input cycle of the series, reduce the charge stored at the end of the previous cycle in the corresponding holding capacitor by half; add half of the sampled charge to the charge of the corresponding holding capacitor; and an analog MAC result circuit comprising the holding capacitors, each holding capacitor associated to a corresponding weight bit significance, the analog MAC result circuit configured to generate, from the charges stored in the holding capacitors at the end of the series of input cycles, an analog MAC result being a summed product of the multibit input and the multibit weight. a bitcell array to perform a multiply-accumulate operation using a multibit weight and a multibit input, wherein the bitcell array comprises a plurality of bitcells, and wherein each bitcell of the bitcell array comprises a corresponding memory unit to store a corresponding weight bit of the multibit weight, a corresponding multiplication unit to multiply the corresponding weight bit by an input bit of the multibit input, and a corresponding output capacitor to store a result of the multiplication; sample-and-hold circuits (300, 400, 500) coupled to the output capacitors of corresponding columns of bitcells, each sample-and-hold circuit comprising a corresponding holding capacitor (304, 506, 508) to store a charge representing a partial MAC result for the corresponding column; an input buffer to serially send input bits of the multibit input to the bitcell array to be multiplied by the multibit weights in a series of input cycles, wherein each sample-and-hold circuit is configured to, in each input cycle of said series of input cycles: sample a voltage on a corresponding column line coupled to the corresponding output capacitors in order to provide a sampled charge; if the input cycle is after the first occurring input cycle of the series, reduce the charge stored at the end of the previous cycle in the corresponding holding capacitor by half; add half of the sampled charge to the charge of the corresponding holding capacitor; and sample a voltage on a corresponding column line coupled to the corresponding output capacitors in order to provide a sampled charge; if the input cycle is after the first occurring input cycle of the series, reduce the charge stored at the end of the previous cycle in the corresponding holding capacitor by half; add half of the sampled charge to the charge of the corresponding holding capacitor; and an analog MAC result circuit comprising the holding capacitors, each holding capacitor associated to a corresponding weight bit significance, the analog MAC result circuit configured to generate, from the charges stored in the holding capacitors at the end of the series of input cycles, an analog MAC result being a summed product of the multibit input and the multibit weight.