A receiving circuit (120_1 - 120_N) applied to a High Definition Multimedia Interface (HDMI), comprising: a decoder, is configured to decode a data stream to generate at least one image frame; a frame key calculating circuit, coupled to the decoder, is configured to calculate a frame key according to the image frame; a line key calculating circuit, coupled to the decoder, is configured to calculate a plurality of line keys according to the image frame; a control circuit, is configured to generate control signals to enable or disable the frame key calculating circuit and the line key calculating circuit according to whether or not the image frame is to be displayed on a display panel coupled to the receiving circuit (120_1 - 120_N); and a timer, coupled to the control circuit, is configured to provide time information of the image frame to the control circuit; characterized in that the frame key calculating circuit is configured to calculate the frame key for the image frame within a period of time defined as when a vertical synchronization signal for the image frame is enabled, and the frame key for the image frame is used to calculate a frame key for a next image frame following the image frame, and when the image frame is not to be displayed on the display panel, the control circuit is configured to generate a control signal to the frame key calculating circuit according to the time information provided by the timer for controlling the frame key calculating circuit to alternately operate in a sleep mode and a normal mode within each image frame, the control circuit is configured to refer to the time information provided by the timer to determine a time point of the vertical synchronization signal, and for each image frame, the control circuit is configured to control the frame key calculating circuit to alternately operate in the sleep mode and the normal mode within each image frame according to the time point of the vertical synchronization signal, wherein the control circuit is configured to control the frame key calculating circuit to operate in the normal mode before a vertical synchronization signal for a next image frame appears according to the time information provided by the timer. a decoder, is configured to decode a data stream to generate at least one image frame; a frame key calculating circuit, coupled to the decoder, is configured to calculate a frame key according to the image frame; a line key calculating circuit, coupled to the decoder, is configured to calculate a plurality of line keys according to the image frame; a control circuit, is configured to generate control signals to enable or disable the frame key calculating circuit and the line key calculating circuit according to whether or not the image frame is to be displayed on a display panel coupled to the receiving circuit (120_1 - 120_N); and a timer, coupled to the control circuit, is configured to provide time information of the image frame to the control circuit; characterized in that the frame key calculating circuit is configured to calculate the frame key for the image frame within a period of time defined as when a vertical synchronization signal for the image frame is enabled, and the frame key for the image frame is used to calculate a frame key for a next image frame following the image frame, and when the image frame is not to be displayed on the display panel, the control circuit is configured to generate a control signal to the frame key calculating circuit according to the time information provided by the timer for controlling the frame key calculating circuit to alternately operate in a sleep mode and a normal mode within each image frame, the control circuit is configured to refer to the time information provided by the timer to determine a time point of the vertical synchronization signal, and for each image frame, the control circuit is configured to control the frame key calculating circuit to alternately operate in the sleep mode and the normal mode within each image frame according to the time point of the vertical synchronization signal, wherein the control circuit is configured to control the frame key calculating circuit to operate in the normal mode before a vertical synchronization signal for a next image frame appears according to the time information provided by the timer.