A method for cache coherency in a reconfigurable cache architecture, comprising: receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address; wherein the reconfigurable cache architecture includes a plurality of cache nodes (225-1...225-n) coupled to the memory, wherein each cache node is partitionable into a plurality of cache bins (310-1...310-8), wherein the target cache bin is one of the plurality of cache bins, and wherein the partitioning of the plurality of cache bins within at least two of the plurality of cache nodes is reconfigurable; and wherein the memory access command includes a unitary identification of any one of: a physical entity, selected from a group consisting of a processing core, and a shared portion of the memory; and a logical entity, selected from a group consisting of: a process, and a thread; wherein: the at least one access parameter including at least one of: a process ID, a processing core ID, a thread ID, and a cache bit; and the determination of the at least one access parameter further comprising at least one of: setting the access parameter as a logical entity identifier, subject to determining that the memory access command is associated with a logical entity; and setting the access parameter as a physical entity identifier subject to determining that the memory access command is associated with a physical entity. receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address; wherein the reconfigurable cache architecture includes a plurality of cache nodes (225-1...225-n) coupled to the memory, wherein each cache node is partitionable into a plurality of cache bins (310-1...310-8), wherein the target cache bin is one of the plurality of cache bins, and wherein the partitioning of the plurality of cache bins within at least two of the plurality of cache nodes is reconfigurable; and wherein the memory access command includes a unitary identification of any one of: a physical entity, selected from a group consisting of a processing core, and a shared portion of the memory; and a logical entity, selected from a group consisting of: a process, and a thread; wherein: the at least one access parameter including at least one of: a process ID, a processing core ID, a thread ID, and a cache bit; and the determination of the at least one access parameter further comprising at least one of: setting the access parameter as a logical entity identifier, subject to determining that the memory access command is associated with a logical entity; and setting the access parameter as a physical entity identifier subject to determining that the memory access command is associated with a physical entity. a physical entity, selected from a group consisting of a processing core, and a shared portion of the memory; and a logical entity, selected from a group consisting of: a process, and a thread; wherein: the at least one access parameter including at least one of: a process ID, a processing core ID, a thread ID, and a cache bit; and the determination of the at least one access parameter further comprising at least one of: setting the access parameter as a logical entity identifier, subject to determining that the memory access command is associated with a logical entity; and setting the access parameter as a physical entity identifier subject to determining that the memory access command is associated with a physical entity. the at least one access parameter including at least one of: a process ID, a processing core ID, a thread ID, and a cache bit; and the determination of the at least one access parameter further comprising at least one of: setting the access parameter as a logical entity identifier, subject to determining that the memory access command is associated with a logical entity; and setting the access parameter as a physical entity identifier subject to determining that the memory access command is associated with a physical entity. setting the access parameter as a logical entity identifier, subject to determining that the memory access command is associated with a logical entity; and setting the access parameter as a physical entity identifier subject to determining that the memory access command is associated with a physical entity.