A wireless communication system, comprising: a first high-frequency integrated circuit, an intermediate-frequency integrated circuit, and an antenna array, wherein the first high-frequency integrated circuit is coupled between the antenna array and the intermediate-frequency integrated circuit; the first high-frequency integrated circuit comprises: a first high-frequency transceiver, a second high-frequency transceiver, a high-frequency phase-locked loop, a high-frequency control unit, a first diplexer, and a second diplexer, wherein the first high-frequency transceiver is coupled to the first diplexer, the second high-frequency transceiver is coupled to the second diplexer, the high-frequency phase-locked loop is separately coupled to the first high-frequency transceiver and the second high-frequency transceiver, and the high-frequency control unit is separately coupled to the first diplexer and the second diplexer; the intermediate-frequency integrated circuit comprises: a first intermediate-frequency transceiver, a second intermediate-frequency transceiver, an intermediate-frequency phase-locked loop, an intermediate-frequency control unit, a third diplexer, and a fourth diplexer, wherein the first intermediate-frequency transceiver is coupled to the third diplexer, the second intermediate-frequency transceiver is coupled to the fourth diplexer, the intermediate-frequency phase-locked loop is separately coupled to the first intermediate-frequency transceiver and the second intermediate-frequency transceiver, and the intermediate-frequency control unit is separately coupled to the third diplexer and the fourth diplexer; and the first diplexer is coupled to the third diplexer, and the second diplexer is coupled to the fourth diplexer, wherein a control signal is transmitted between the high-frequency control unit and the intermediate-frequency control unit, wherein the control signal comprises an instruction data signal and an echo clock signal, a phase of the instruction data signal is synchronized with a phase of the echo clock signal, and a frequency of the instruction data signal and a frequency of the echo clock signal are in a co-frequency relationship or a frequency multiplication relationship; and the echo clock signal is transmitted between the high-frequency control unit and the intermediate-frequency control unit via the first diplexer and the third diplexer, and the instruction data signal is transmitted between the high-frequency control unit and the intermediate-frequency control unit via the second diplexer and the fourth diplexer. the first high-frequency integrated circuit comprises: a first high-frequency transceiver, a second high-frequency transceiver, a high-frequency phase-locked loop, a high-frequency control unit, a first diplexer, and a second diplexer, wherein the first high-frequency transceiver is coupled to the first diplexer, the second high-frequency transceiver is coupled to the second diplexer, the high-frequency phase-locked loop is separately coupled to the first high-frequency transceiver and the second high-frequency transceiver, and the high-frequency control unit is separately coupled to the first diplexer and the second diplexer; the intermediate-frequency integrated circuit comprises: a first intermediate-frequency transceiver, a second intermediate-frequency transceiver, an intermediate-frequency phase-locked loop, an intermediate-frequency control unit, a third diplexer, and a fourth diplexer, wherein the first intermediate-frequency transceiver is coupled to the third diplexer, the second intermediate-frequency transceiver is coupled to the fourth diplexer, the intermediate-frequency phase-locked loop is separately coupled to the first intermediate-frequency transceiver and the second intermediate-frequency transceiver, and the intermediate-frequency control unit is separately coupled to the third diplexer and the fourth diplexer; and the first diplexer is coupled to the third diplexer, and the second diplexer is coupled to the fourth diplexer, wherein a control signal is transmitted between the high-frequency control unit and the intermediate-frequency control unit, wherein the control signal comprises an instruction data signal and an echo clock signal, a phase of the instruction data signal is synchronized with a phase of the echo clock signal, and a frequency of the instruction data signal and a frequency of the echo clock signal are in a co-frequency relationship or a frequency multiplication relationship; and the echo clock signal is transmitted between the high-frequency control unit and the intermediate-frequency control unit via the first diplexer and the third diplexer, and the instruction data signal is transmitted between the high-frequency control unit and the intermediate-frequency control unit via the second diplexer and the fourth diplexer.