A system comprising: a plurality of uninterruptible power supplies (UPSs), each UPS of the plurality of UPSs comprising an inverter; a ring bus, wherein an output of the inverter of each UPS of the plurality of UPSs is coupled to the ring bus; and at least one controller communicatively coupled to the plurality of UPSs, the at least one controller comprising: a processor; and a memory device communicatively coupled to said processor, said memory device storing executable instructions, characterized in that the executable instructions are configured to cause said processor to: determine when a bridge current i s in the inverter of at least one UPS of the plurality of UPSs reaches a predetermined bridge current limit ±I smax; and modify gating signals for switches (405, 407) in the inverter to modify an output capacitor voltage u c in the inverter of the at least one UPS, in response to a determination that the bridge current i s has reached the predetermined bridge current limit ±I smax, to reduce a DC fault current component of a load current in the inverter. a plurality of uninterruptible power supplies (UPSs), each UPS of the plurality of UPSs comprising an inverter; a ring bus, wherein an output of the inverter of each UPS of the plurality of UPSs is coupled to the ring bus; and at least one controller communicatively coupled to the plurality of UPSs, the at least one controller comprising: a processor; and a memory device communicatively coupled to said processor, said memory device storing executable instructions, characterized in that the executable instructions are configured to cause said processor to: determine when a bridge current i s in the inverter of at least one UPS of the plurality of UPSs reaches a predetermined bridge current limit ±I smax; and modify gating signals for switches (405, 407) in the inverter to modify an output capacitor voltage u c in the inverter of the at least one UPS, in response to a determination that the bridge current i s has reached the predetermined bridge current limit ±I smax, to reduce a DC fault current component of a load current in the inverter. a processor; and a memory device communicatively coupled to said processor, said memory device storing executable instructions, characterized in that the executable instructions are configured to cause said processor to: determine when a bridge current i s in the inverter of at least one UPS of the plurality of UPSs reaches a predetermined bridge current limit ±I smax; and modify gating signals for switches (405, 407) in the inverter to modify an output capacitor voltage u c in the inverter of the at least one UPS, in response to a determination that the bridge current i s has reached the predetermined bridge current limit ±I smax, to reduce a DC fault current component of a load current in the inverter. determine when a bridge current i s in the inverter of at least one UPS of the plurality of UPSs reaches a predetermined bridge current limit ±I smax; and modify gating signals for switches (405, 407) in the inverter to modify an output capacitor voltage u c in the inverter of the at least one UPS, in response to a determination that the bridge current i s has reached the predetermined bridge current limit ±I smax, to reduce a DC fault current component of a load current in the inverter.