A printed circuit board comprising: a base insulating layer; an upper insulating layer (120, 140) formed on the base insulating layer and having a plurality of first through holes (121, 122, 123), the upper insulating layer (120, 140) having a plurality of first vias (124, 125, 126) filled in the first through holes (121, 122, 123), respectively; a lower insulating layer (130, 150) formed under the base insulating layer and having one second through hole formed in a region overlapped with the first through holes (121, 122, 123), the lower insulating layer (130, 150) having a second via filled in the sec0ond through hole and commonly connected with the first vias (124, 125, 126); and a plurality of third vias (115, 116, 117) filled in a plurality of third through holes formed through a top surface and a bottom surface of the base insulating layer and connected with the first vias (124, 125, 126) formed in the upper insulating layer (120, 140), respectively, characterized by further comprising: a first circuit pattern interposed between the base insulating layer and the lower insulating layer (130, 150), and having a top surface commonly making contact with bottom surfaces of the third vias (115, 116, 117) and a bottom surface making contact with a top surface of one second via; and a plurality of second circuit patterns (111, 112, 113) interposed between the base insulating layer and the upper insulating layer (120, 140), and having a top surface making contact with one of the first vias (124, 125, 126) and a bottom surface making contact with one of the third vias (115, 116, 117). a base insulating layer; an upper insulating layer (120, 140) formed on the base insulating layer and having a plurality of first through holes (121, 122, 123), the upper insulating layer (120, 140) having a plurality of first vias (124, 125, 126) filled in the first through holes (121, 122, 123), respectively; a lower insulating layer (130, 150) formed under the base insulating layer and having one second through hole formed in a region overlapped with the first through holes (121, 122, 123), the lower insulating layer (130, 150) having a second via filled in the sec0ond through hole and commonly connected with the first vias (124, 125, 126); and a plurality of third vias (115, 116, 117) filled in a plurality of third through holes formed through a top surface and a bottom surface of the base insulating layer and connected with the first vias (124, 125, 126) formed in the upper insulating layer (120, 140), respectively, characterized by further comprising: a first circuit pattern interposed between the base insulating layer and the lower insulating layer (130, 150), and having a top surface commonly making contact with bottom surfaces of the third vias (115, 116, 117) and a bottom surface making contact with a top surface of one second via; and a plurality of second circuit patterns (111, 112, 113) interposed between the base insulating layer and the upper insulating layer (120, 140), and having a top surface making contact with one of the first vias (124, 125, 126) and a bottom surface making contact with one of the third vias (115, 116, 117). a first circuit pattern interposed between the base insulating layer and the lower insulating layer (130, 150), and having a top surface commonly making contact with bottom surfaces of the third vias (115, 116, 117) and a bottom surface making contact with a top surface of one second via; and a plurality of second circuit patterns (111, 112, 113) interposed between the base insulating layer and the upper insulating layer (120, 140), and having a top surface making contact with one of the first vias (124, 125, 126) and a bottom surface making contact with one of the third vias (115, 116, 117).