A mobile Internet-of-Things, IoT, edge device, comprising: a reconfigurable processor unit including a substrate; a die stack coupled to the substrate and having a field-programmable gate array, FPGA, die element and a reconfigurable die element, the reconfigurable die element including memory elements and control circuitry, the control circuitry being configured to control the memory elements to serve as storage memory at one time and as configuration memory at another time, the memory elements when serving as configuration memory storing configuration information for controlling the FPGA die element; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a processor-independent connectivity unit coupled to the reconfigurable processor unit, the processor-independent connectivity unit not including a processor to perform at least a subset of the connectivity unit processing functions, the processor-independent connectivity unit including an antenna; a radio-frequency chip, RFIC, coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; and a system interface configured to transmit the incoming signals or data generated therefrom to the reconfigurable processor unit for processing, and configured to receive outgoing signals or data generated therefrom from the reconfigurable processor unit, the FPGA die element being configured based on the configuration information to operate as analog circuitry for processing the incoming signals or data generated therefrom, the analog circuitry being configured to perform at least the subset of the connectivity unit processing functions on behalf of the processor-independent connectivity unit. a reconfigurable processor unit including a substrate; a die stack coupled to the substrate and having a field-programmable gate array, FPGA, die element and a reconfigurable die element, the reconfigurable die element including memory elements and control circuitry, the control circuitry being configured to control the memory elements to serve as storage memory at one time and as configuration memory at another time, the memory elements when serving as configuration memory storing configuration information for controlling the FPGA die element; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a substrate; a die stack coupled to the substrate and having a field-programmable gate array, FPGA, die element and a reconfigurable die element, the reconfigurable die element including memory elements and control circuitry, the control circuitry being configured to control the memory elements to serve as storage memory at one time and as configuration memory at another time, the memory elements when serving as configuration memory storing configuration information for controlling the FPGA die element; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a processor-independent connectivity unit coupled to the reconfigurable processor unit, the processor-independent connectivity unit not including a processor to perform at least a subset of the connectivity unit processing functions, the processor-independent connectivity unit including an antenna; a radio-frequency chip, RFIC, coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; and a system interface configured to transmit the incoming signals or data generated therefrom to the reconfigurable processor unit for processing, and configured to receive outgoing signals or data generated therefrom from the reconfigurable processor unit, the FPGA die element being configured based on the configuration information to operate as analog circuitry for processing the incoming signals or data generated therefrom, the analog circuitry being configured to perform at least the subset of the connectivity unit processing functions on behalf of the processor-independent connectivity unit. an antenna; a radio-frequency chip, RFIC, coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; and a system interface configured to transmit the incoming signals or data generated therefrom to the reconfigurable processor unit for processing, and configured to receive outgoing signals or data generated therefrom from the reconfigurable processor unit, the FPGA die element being configured based on the configuration information to operate as analog circuitry for processing the incoming signals or data generated therefrom, the analog circuitry being configured to perform at least the subset of the connectivity unit processing functions on behalf of the processor-independent connectivity unit.