A data processing apparatus comprising: processing circuitry for performing data processing operations in response to program code, the processing circuitry comprising exception control circuitry for controlling exception processing; a plurality of registers for storing data, the registers including a first subset of registers and a second subset of registers; and a data store for storing data, the data store comprising a plurality of regions including a secure region and a less secure region, wherein the secure region is for storing data which is accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain; wherein: in response to an initial exception from background processing performed by the processing circuitry, the exception control circuitry is configured to perform state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception, wherein the exception handling routine has responsibility for performing state saving of data from the second subset of registers; in response to a first exception causing a transition from the secure domain to the less secure domain, where the background processing was performed by the processing circuitry in the secure domain, the exception control circuitry is configured to perform additional state saving of the data from the second subset of registers before triggering the processing circuitry to perform the exception handling routine in the less secure domain; and in response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception control circuitry is configured to trigger the processing circuitry to perform the exception handling routine without performing the additional state saving, the tail-chained exception being processed after said first exception has been processed and before returning to the background processing. processing circuitry for performing data processing operations in response to program code, the processing circuitry comprising exception control circuitry for controlling exception processing; a plurality of registers for storing data, the registers including a first subset of registers and a second subset of registers; and a data store for storing data, the data store comprising a plurality of regions including a secure region and a less secure region, wherein the secure region is for storing data which is accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain; wherein: in response to an initial exception from background processing performed by the processing circuitry, the exception control circuitry is configured to perform state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception, wherein the exception handling routine has responsibility for performing state saving of data from the second subset of registers; in response to a first exception causing a transition from the secure domain to the less secure domain, where the background processing was performed by the processing circuitry in the secure domain, the exception control circuitry is configured to perform additional state saving of the data from the second subset of registers before triggering the processing circuitry to perform the exception handling routine in the less secure domain; and in response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception control circuitry is configured to trigger the processing circuitry to perform the exception handling routine without performing the additional state saving, the tail-chained exception being processed after said first exception has been processed and before returning to the background processing.