A light emitting device, comprising: a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface in a region including the light emitting layer; an n-side electrode provided on the second surface in a region not including the light emitting layer; a first insulating layer provided on the second surface side, the first insulating layer having a first via communicating with the p-side electrode and a second via communicating with the n-side electrode; a p-side interconnect layer (21, 23) provided at least inside the first via, the p-side interconnect layer being electrically connected to the p-side electrode; an n-side interconnect layer (22, 24) provided apart from the p-side interconnect layer inside the second via and on an interconnect surface of the first insulating layer, the interconnect surface being opposite to the semiconductor layer, the n-side interconnect layer being electrically connected to the n-side electrode; and a second insulating layer provided at least between the p-side interconnect layer and the n-side interconnect layer, the p-side interconnect layer including a p-side external terminal (21a, 23a) exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface, the n-side interconnect layer including an n-side external terminal (22a, 24a) exposed from the second insulating layer at the third surface, the p-side interconnect layer including a p-side metal plate layer and a p-side metal pillar, the p-side metal plate layer being provided at least inside the first via, the p-side metal pillar being provided on a surface of the p-side metal plate layer opposite to the interconnect surface and opposite to a contacting portion between the first via and the p-side metal plate layer, and the n-side interconnect layer including an n-side metal plate layer and an n-side metal pillar, the n-side metal plate layer being provided inside the second via and on the interconnect surface, the n-side metal pillar being provided on a surface of the n-side metal plate layer opposite to the interconnect surface and opposite to a contacting portion between the second via and the n-side metal plate layer, a distance between the p-side external terminal (21a, 23a) and the n-side external terminal (22a, 24a) exposed at the third surface being greater than a distance between the p-side metal plate layer and the n-side metal plate layer on the interconnect surface. a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface in a region including the light emitting layer; an n-side electrode provided on the second surface in a region not including the light emitting layer; a first insulating layer provided on the second surface side, the first insulating layer having a first via communicating with the p-side electrode and a second via communicating with the n-side electrode; a p-side interconnect layer (21, 23) provided at least inside the first via, the p-side interconnect layer being electrically connected to the p-side electrode; an n-side interconnect layer (22, 24) provided apart from the p-side interconnect layer inside the second via and on an interconnect surface of the first insulating layer, the interconnect surface being opposite to the semiconductor layer, the n-side interconnect layer being electrically connected to the n-side electrode; and a second insulating layer provided at least between the p-side interconnect layer and the n-side interconnect layer, the p-side interconnect layer including a p-side external terminal (21a, 23a) exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface, the n-side interconnect layer including an n-side external terminal (22a, 24a) exposed from the second insulating layer at the third surface, the p-side interconnect layer including a p-side metal plate layer and a p-side metal pillar, the p-side metal plate layer being provided at least inside the first via, the p-side metal pillar being provided on a surface of the p-side metal plate layer opposite to the interconnect surface and opposite to a contacting portion between the first via and the p-side metal plate layer, and the n-side interconnect layer including an n-side metal plate layer and an n-side metal pillar, the n-side metal plate layer being provided inside the second via and on the interconnect surface, the n-side metal pillar being provided on a surface of the n-side metal plate layer opposite to the interconnect surface and opposite to a contacting portion between the second via and the n-side metal plate layer, a distance between the p-side external terminal (21a, 23a) and the n-side external terminal (22a, 24a) exposed at the third surface being greater than a distance between the p-side metal plate layer and the n-side metal plate layer on the interconnect surface.