A memory cell comprising: a source region and a drain region separated by a semiconductor channel region (300, 400, 500, 600), the channel region (300, 400, 500, 600) having a channel surface (301, 401, 501, 601) including a first cylindrical region (1007, 1008); a first dielectric structure (302, 402, 502, 602, 1009) on the channel surface (301, 401, 501, 600); a dielectric charge trapping structure (303, 403, 503, 603, 1010) on the first dielectric structure (202, 302, 402, 502, 602); a second dielectric structure (304, 404, 504, 604, 1011) on the dielectric charge trapping structure (303, 403, 503, 603, 1010); a conductive layer (305, 405, 505, 605) having a conductor surface (306, 406, 506, 606) including a second cylindrical region on the second dielectric structure (304, 404, 504, 604, 1011), the conductor surface (306, 406, 506, 606) overlying the dielectric charge trapping structure (203, 303, 403, 503, 603, 1010) and the channel surface (301, 401, 501, 601); wherein a cross-section of the first cylindrical region (1007, 1008) of the channel surface (201, 301, 401, 501, 601) along the channel width dimension is circular with an arc of less than 360 degrees; wherein a cross-section of the second cylindrical region of the conductor surface (206, 306, 406, 506, 606) along the channel width dimension is circular with an arc of less than 360 degrees; wherein the charge trapping structure (303, 403, 503, 603) has a first bottom surface (309, 409, 509, 609); wherein the channel region (300, 400, 500, 600) has a second bottom surface (307, 407, 507, 607); wherein a cross-section of the first bottom surface (309, 409, 509, 609) along the channel width dimension comprises a first corner (309a, 409a, 509a, 609a) and a second corner (309b, 409b, 509b, 609b) at which the first bottom surface (309, 409, 509, 609) turns away from the channel region (300, 400, 500, 600); and wherein a cross-section of the second bottom surface (307, 407, 507, 607) along the channel width dimension comprises a first line; characterized in that the structures between the channel surface (301, 401, 501, 601) and the conductor surface (306, 406, 506, 606) have an effective oxide thickness and the first cylindrical region of the channel surface (301, 401, 501, 601) has an average radius that is less than the effective oxide thickness. a source region and a drain region separated by a semiconductor channel region (300, 400, 500, 600), the channel region (300, 400, 500, 600) having a channel surface (301, 401, 501, 601) including a first cylindrical region (1007, 1008); a first dielectric structure (302, 402, 502, 602, 1009) on the channel surface (301, 401, 501, 600); a dielectric charge trapping structure (303, 403, 503, 603, 1010) on the first dielectric structure (202, 302, 402, 502, 602); a second dielectric structure (304, 404, 504, 604, 1011) on the dielectric charge trapping structure (303, 403, 503, 603, 1010); a conductive layer (305, 405, 505, 605) having a conductor surface (306, 406, 506, 606) including a second cylindrical region on the second dielectric structure (304, 404, 504, 604, 1011), the conductor surface (306, 406, 506, 606) overlying the dielectric charge trapping structure (203, 303, 403, 503, 603, 1010) and the channel surface (301, 401, 501, 601); wherein a cross-section of the first cylindrical region (1007, 1008) of the channel surface (201, 301, 401, 501, 601) along the channel width dimension is circular with an arc of less than 360 degrees; wherein a cross-section of the second cylindrical region of the conductor surface (206, 306, 406, 506, 606) along the channel width dimension is circular with an arc of less than 360 degrees; wherein the charge trapping structure (303, 403, 503, 603) has a first bottom surface (309, 409, 509, 609); wherein the channel region (300, 400, 500, 600) has a second bottom surface (307, 407, 507, 607); wherein a cross-section of the first bottom surface (309, 409, 509, 609) along the channel width dimension comprises a first corner (309a, 409a, 509a, 609a) and a second corner (309b, 409b, 509b, 609b) at which the first bottom surface (309, 409, 509, 609) turns away from the channel region (300, 400, 500, 600); and wherein a cross-section of the second bottom surface (307, 407, 507, 607) along the channel width dimension comprises a first line; characterized in that the structures between the channel surface (301, 401, 501, 601) and the conductor surface (306, 406, 506, 606) have an effective oxide thickness and the first cylindrical region of the channel surface (301, 401, 501, 601) has an average radius that is less than the effective oxide thickness.