A space vector pulse width modulation control system for a multi-level inverter, comprising: a digital logic circuit comprising: a plurality of digital logic comparators (1402, 1404, 1406, 1408) including a first comparator and a second comparator; a plurality of inverters (1412, 1414, 1416, 1418) coupled to respective outputs of a respective plurality of comparators (1402, 1404, 1406, 1408), the plurality of inverters (1412, 1414, 1416, 1418) including a first inverter; and a plurality of AND gates (1422, 1424, 1426) including a first AND gate, the, first AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator; a digital up/down counter coupled to first inputs of the plurality of comparators (1402, 1404, 1406, 1408), the up/down counter counting from 0 to Ts/2 and then from Ts/2 to 0, where Ts is a sampling period; and a processor and memory configured to: identify a sector location based on an actual angle (θ e *) of a reference voltage vector (V*); convert the actual angle (θ e *) into a converted angle located in a first sector; identify a reference region location based on the magnitude of the reference voltage vector (V*) and the converted angle in the first sector; select a switching sequence and turn-on time values (T1, T2, T3, T4) based on the corresponding actual region location and actual sector, wherein the turn-on time value (T1, T2, T3, T4) is the sum function of weighted duty cycles (T a, T b, Tc); transmit turn-on time values (T1, T2, T3, T4) to second inputs of the plurality of comparators (1402, 1404, 1406, 1408); and provide the output of the first comparator, the outputs of the plurality of AND gates (1422, 1424, 1426), and the output of a last inverter of the plurality of inverters (1412, 1414, 1416, 1418) as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter. a digital logic circuit comprising: a plurality of digital logic comparators (1402, 1404, 1406, 1408) including a first comparator and a second comparator; a plurality of inverters (1412, 1414, 1416, 1418) coupled to respective outputs of a respective plurality of comparators (1402, 1404, 1406, 1408), the plurality of inverters (1412, 1414, 1416, 1418) including a first inverter; and a plurality of AND gates (1422, 1424, 1426) including a first AND gate, the, first AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator; a plurality of digital logic comparators (1402, 1404, 1406, 1408) including a first comparator and a second comparator; a plurality of inverters (1412, 1414, 1416, 1418) coupled to respective outputs of a respective plurality of comparators (1402, 1404, 1406, 1408), the plurality of inverters (1412, 1414, 1416, 1418) including a first inverter; and a plurality of AND gates (1422, 1424, 1426) including a first AND gate, the, first AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator; a digital up/down counter coupled to first inputs of the plurality of comparators (1402, 1404, 1406, 1408), the up/down counter counting from 0 to Ts/2 and then from Ts/2 to 0, where Ts is a sampling period; and a processor and memory configured to: identify a sector location based on an actual angle (θ e *) of a reference voltage vector (V*); convert the actual angle (θ e *) into a converted angle located in a first sector; identify a reference region location based on the magnitude of the reference voltage vector (V*) and the converted angle in the first sector; select a switching sequence and turn-on time values (T1, T2, T3, T4) based on the corresponding actual region location and actual sector, wherein the turn-on time value (T1, T2, T3, T4) is the sum function of weighted duty cycles (T a, T b, Tc); transmit turn-on time values (T1, T2, T3, T4) to second inputs of the plurality of comparators (1402, 1404, 1406, 1408); and provide the output of the first comparator, the outputs of the plurality of AND gates (1422, 1424, 1426), and the output of a last inverter of the plurality of inverters (1412, 1414, 1416, 1418) as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter. identify a sector location based on an actual angle (θ e *) of a reference voltage vector (V*); convert the actual angle (θ e *) into a converted angle located in a first sector; identify a reference region location based on the magnitude of the reference voltage vector (V*) and the converted angle in the first sector; select a switching sequence and turn-on time values (T1, T2, T3, T4) based on the corresponding actual region location and actual sector, wherein the turn-on time value (T1, T2, T3, T4) is the sum function of weighted duty cycles (T a, T b, Tc); transmit turn-on time values (T1, T2, T3, T4) to second inputs of the plurality of comparators (1402, 1404, 1406, 1408); and provide the output of the first comparator, the outputs of the plurality of AND gates (1422, 1424, 1426), and the output of a last inverter of the plurality of inverters (1412, 1414, 1416, 1418) as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter.