An apparatus, comprising: an array of memory cells; and a controller (140, 240) coupled to the array configured to: sense a first memory cell (428-1-1... 428-5-4) using a first sense amp, wherein the first memory cell is coupled to a first digit line and a first access line and the first sense amp is coupled to the first digit line, wherein the first sense amp is configured to sense the first memory cell based upon a first input (432-1-1-1...432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1... 632-2, 634, 636, 634, 636) associated with the first memory cell and a second input (432-1-1-1... 432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1...632-2, 634, 636, 634, 636) and a third input (432-1-1-1...432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1... 632-2, 634, 636, 634, 636) associated with a second memory cell (428-1-1... 428-5-4) wherein the second memory cell is coupled to a second digit line, a third digit line, and the first access line, wherein the first input is received by a gate of a first transistor of the first sense amp and a gate of a second transistor of the first sense amp via the first digit line, the second input is received by a gate of a third transistor of the first sense amp via the second digit line, and the third input is received by a gate of a fourth transistor via the third digit line, wherein a source drain region of the first transistor and a source drain region of the second transistor is coupled to a source drain region of a fifth transistor, wherein a source drain region of the third transistor and a source drain region of the fourth transistor is coupled to a source drain region of a sixth transistor, and wherein the first sense amp includes a cross coupled latch comprising the fifth transistor and the sixth transistor forming a first pair of transistors and a seventh transistor and an eighth transistor forming a second pair of transistors. an array of memory cells; and a controller (140, 240) coupled to the array configured to: sense a first memory cell (428-1-1... 428-5-4) using a first sense amp, wherein the first memory cell is coupled to a first digit line and a first access line and the first sense amp is coupled to the first digit line, wherein the first sense amp is configured to sense the first memory cell based upon a first input (432-1-1-1...432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1... 632-2, 634, 636, 634, 636) associated with the first memory cell and a second input (432-1-1-1... 432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1...632-2, 634, 636, 634, 636) and a third input (432-1-1-1...432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1... 632-2, 634, 636, 634, 636) associated with a second memory cell (428-1-1... 428-5-4) wherein the second memory cell is coupled to a second digit line, a third digit line, and the first access line, wherein the first input is received by a gate of a first transistor of the first sense amp and a gate of a second transistor of the first sense amp via the first digit line, the second input is received by a gate of a third transistor of the first sense amp via the second digit line, and the third input is received by a gate of a fourth transistor via the third digit line, wherein a source drain region of the first transistor and a source drain region of the second transistor is coupled to a source drain region of a fifth transistor, wherein a source drain region of the third transistor and a source drain region of the fourth transistor is coupled to a source drain region of a sixth transistor, and wherein the first sense amp includes a cross coupled latch comprising the fifth transistor and the sixth transistor forming a first pair of transistors and a seventh transistor and an eighth transistor forming a second pair of transistors. sense a first memory cell (428-1-1... 428-5-4) using a first sense amp, wherein the first memory cell is coupled to a first digit line and a first access line and the first sense amp is coupled to the first digit line, wherein the first sense amp is configured to sense the first memory cell based upon a first input (432-1-1-1...432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1... 632-2, 634, 636, 634, 636) associated with the first memory cell and a second input (432-1-1-1... 432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1...632-2, 634, 636, 634, 636) and a third input (432-1-1-1...432-3-2, 434, 436, 532-1... 532-2, 534, 536, 632-1... 632-2, 634, 636, 634, 636) associated with a second memory cell (428-1-1... 428-5-4) wherein the second memory cell is coupled to a second digit line, a third digit line, and the first access line, wherein the first input is received by a gate of a first transistor of the first sense amp and a gate of a second transistor of the first sense amp via the first digit line, the second input is received by a gate of a third transistor of the first sense amp via the second digit line, and the third input is received by a gate of a fourth transistor via the third digit line, wherein a source drain region of the first transistor and a source drain region of the second transistor is coupled to a source drain region of a fifth transistor, wherein a source drain region of the third transistor and a source drain region of the fourth transistor is coupled to a source drain region of a sixth transistor, and wherein the first sense amp includes a cross coupled latch comprising the fifth transistor and the sixth transistor forming a first pair of transistors and a seventh transistor and an eighth transistor forming a second pair of transistors.