A heterostructure field effect transistor comprising: - a semiconductor wire comprising in its longitudinal direction ∘ a source and a drain region ∘ a channel region in between the source and drain region and in its transversal direction for the source region, ∘ a source core region and ∘ a source shell region disposed around the source core region, the source shell region having a thickness (ti) and in its transversal direction for the drain region, ∘ a drain core region and ∘ a drain shell region disposed around the drain core region, the drain shell region having a thickness (t 3) and in its transversal direction for the channel region, ∘ a channel core region and ∘ a channel shell region disposed around the channel core region; the channel shell region having a thickness (t 2) and - a gate structure disposed around the channel region of the semiconductor wire, the gate structure comprising a gate dielectric layer disposed around and in contact with the channel region and a gate layer disposed around and in contact with the gate dielectric layer, wherein - the source shell region, the drain shell region and the channel shell region are quantum well regions, Characterized in that: - the thickness (t 2) of the channel shell region is smaller than the thickness (t 1) of the source shell region and is smaller than the thickness (t 3) of the drain shell region. - a semiconductor wire comprising in its longitudinal direction ∘ a source and a drain region ∘ a channel region in between the source and drain region and in its transversal direction for the source region, ∘ a source core region and ∘ a source shell region disposed around the source core region, the source shell region having a thickness (ti) and in its transversal direction for the drain region, ∘ a drain core region and ∘ a drain shell region disposed around the drain core region, the drain shell region having a thickness (t 3) and in its transversal direction for the channel region, ∘ a channel core region and ∘ a channel shell region disposed around the channel core region; the channel shell region having a thickness (t 2) and ∘ a source and a drain region ∘ a channel region in between the source and drain region ∘ a source core region and ∘ a source shell region disposed around the source core region, the source shell region having a thickness (ti) ∘ a drain core region and ∘ a drain shell region disposed around the drain core region, the drain shell region having a thickness (t 3) ∘ a channel core region and ∘ a channel shell region disposed around the channel core region; the channel shell region having a thickness (t 2) and - a gate structure disposed around the channel region of the semiconductor wire, the gate structure comprising a gate dielectric layer disposed around and in contact with the channel region and a gate layer disposed around and in contact with the gate dielectric layer, - the source shell region, the drain shell region and the channel shell region are quantum well regions, Characterized in that: - the thickness (t 2) of the channel shell region is smaller than the thickness (t 1) of the source shell region and is smaller than the thickness (t 3) of the drain shell region. - the thickness (t 2) of the channel shell region is smaller than the thickness (t 1) of the source shell region and is smaller than the thickness (t 3) of the drain shell region.