Phase error compensation arrangement (300, 400) for compensating a phase error of a receive signal, the phase error compensation arrangement (300, 400) comprising a first phase error compensator and a second phase error compensator arranged downstream of the first phase error compensator, wherein the first phase error compensator is configured to obtain a first estimated phase error (φ PS) of the receive signal based on a value of the receive signal and a predefined pilot value, to shift a phase of the receive signal by the first estimated phase error (φ PS), and to provide the phase shifted receive signal to the second phase error compensator, the first phase error compensator including an interpolator configured to provide a time-varying estimation of the first estimated phase error (φ PS) of the receive signal for the times at which no pilot value is present in the receive signal, wherein the second phase error compensator comprises: - a delay element for delaying the phase shifted receive signal; - a phase error estimator for providing a second estimated phase error (φ FF) of the phase shifted receive signal; - a phase shifter for shifting a phase of the delayed phase shifted receive signal by the second estimated phase error (φ FF); and wherein the phase error estimator comprises: - a slicer for mapping a value of the phase shifted receive signal onto a mapped value; - a conjugator for conjugating one of the mapped value and the value of the phase shifted receive signal to obtain a conjugated output and an unprocessed output; - a multiplier for multiplying the conjugated output and the unprocessed output of the conjugator to obtain a distinction value; - a phase determiner for determining a phase of the distinction value to obtain the second estimated phase error (φ FF); and wherein the phase error compensation arrangement is characterized by further comprising: a further slicer arranged downstream the second phase error compensator for mapping a value of a signal at an input of the further slicer onto a mapped value at an output of the further slicer, and a feedback phase error compensator (420, 430) being configured: - to obtain a feedback phase error (φ PLL) upon the basis of a difference value between the value at the input of the further slicer and the mapped value at the output of the further slicer; and - to shift a phase of the receive signal by the feedback phase error (φ PLL) to obtain the signal at the input of the further slicer. - a delay element for delaying the phase shifted receive signal; - a phase error estimator for providing a second estimated phase error (φ FF) of the phase shifted receive signal; - a phase shifter for shifting a phase of the delayed phase shifted receive signal by the second estimated phase error (φ FF); and wherein the phase error estimator comprises: - a slicer for mapping a value of the phase shifted receive signal onto a mapped value; - a conjugator for conjugating one of the mapped value and the value of the phase shifted receive signal to obtain a conjugated output and an unprocessed output; - a multiplier for multiplying the conjugated output and the unprocessed output of the conjugator to obtain a distinction value; - a phase determiner for determining a phase of the distinction value to obtain the second estimated phase error (φ FF); and wherein the phase error compensation arrangement is characterized by further comprising: a further slicer arranged downstream the second phase error compensator for mapping a value of a signal at an input of the further slicer onto a mapped value at an output of the further slicer, and a feedback phase error compensator (420, 430) being configured: - to obtain a feedback phase error (φ PLL) upon the basis of a difference value between the value at the input of the further slicer and the mapped value at the output of the further slicer; and - to shift a phase of the receive signal by the feedback phase error (φ PLL) to obtain the signal at the input of the further slicer. a further slicer arranged downstream the second phase error compensator for mapping a value of a signal at an input of the further slicer onto a mapped value at an output of the further slicer, and a feedback phase error compensator (420, 430) being configured: - to obtain a feedback phase error (φ PLL) upon the basis of a difference value between the value at the input of the further slicer and the mapped value at the output of the further slicer; and - to shift a phase of the receive signal by the feedback phase error (φ PLL) to obtain the signal at the input of the further slicer. - to obtain a feedback phase error (φ PLL) upon the basis of a difference value between the value at the input of the further slicer and the mapped value at the output of the further slicer; and - to shift a phase of the receive signal by the feedback phase error (φ PLL) to obtain the signal at the input of the further slicer.