A display device, comprising: a gate line; a semiconductor pattern disposed on the gate line and including a first semiconductor region, a second semiconductor region and a third semiconductor region; a data line insulated from the gate line, the data line intersecting the gate line; a voltage division reference line insulated from the gate line, the voltage division reference line intersecting the semiconductor pattern; a first switching element overlapping the first semiconductor region of the semiconductor pattern, the first switching element comprising: a first source electrode electrically connected to the data line, a first drain electrode spaced apart from the first source electrode, and a first gate electrode electrically connected to the gate line; a second switching element overlapping the second semiconductor region of the semiconductor pattern, the second switching element comprising: a second source electrode electrically connected to the data line, a second drain electrode spaced apart from the second source electrode, and a second gate electrode electrically connected to the gate line; a third switching element overlapping the third semiconductor region of the semiconductor pattern, the third switching element comprising: a third source electrode electrically connected to the voltage division reference line, a third drain electrode electrically connected to the second drain electrode, and a third gate electrode electrically connected to the gate line; a first sub-pixel electrode electrically connected to the first drain electrode; and a second sub-pixel electrode electrically connected to the second drain electrode, characterized in that the first semiconductor region, the second semiconductor region and the third semiconductor region are connected to each other, and the sequence of the semiconductor regions is arranged in a first direction; the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are sequentially arranged across the semiconductor pattern and the sequence of electrodes is arranged in the first direction on the semiconductor pattern. a gate line; a semiconductor pattern disposed on the gate line and including a first semiconductor region, a second semiconductor region and a third semiconductor region; a data line insulated from the gate line, the data line intersecting the gate line; a voltage division reference line insulated from the gate line, the voltage division reference line intersecting the semiconductor pattern; a first switching element overlapping the first semiconductor region of the semiconductor pattern, the first switching element comprising: a first source electrode electrically connected to the data line, a first drain electrode spaced apart from the first source electrode, and a first gate electrode electrically connected to the gate line; a first source electrode electrically connected to the data line, a first drain electrode spaced apart from the first source electrode, and a first gate electrode electrically connected to the gate line; a second switching element overlapping the second semiconductor region of the semiconductor pattern, the second switching element comprising: a second source electrode electrically connected to the data line, a second drain electrode spaced apart from the second source electrode, and a second gate electrode electrically connected to the gate line; a second source electrode electrically connected to the data line, a second drain electrode spaced apart from the second source electrode, and a second gate electrode electrically connected to the gate line; a third switching element overlapping the third semiconductor region of the semiconductor pattern, the third switching element comprising: a third source electrode electrically connected to the voltage division reference line, a third drain electrode electrically connected to the second drain electrode, and a third gate electrode electrically connected to the gate line; a third source electrode electrically connected to the voltage division reference line, a third drain electrode electrically connected to the second drain electrode, and a third gate electrode electrically connected to the gate line; a first sub-pixel electrode electrically connected to the first drain electrode; and a second sub-pixel electrode electrically connected to the second drain electrode, characterized in that the first semiconductor region, the second semiconductor region and the third semiconductor region are connected to each other, and the sequence of the semiconductor regions is arranged in a first direction; the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are sequentially arranged across the semiconductor pattern and the sequence of electrodes is arranged in the first direction on the semiconductor pattern.