An apparatus comprising: a physical layer unit, PHY, to be coupled to a serial link, the PHY comprising: a receiver path to process data that is to be received via the serial link, the receiver path including, a differential receiver having a pair of differential input to be coupled to the serial link and a serial output; a clock recovery circuit, having first input to receive a clock signal and a second input coupled to the output of the differential receiver, and having an output comprising a recovered bit clock, a data recovery circuit, having a first input coupled to the serial output of the differential receiver, a second input at which the recovered bit clock is received, and a serial output; a serial to parallel converter, having a first input coupled to the serial output of the data recovery circuit, a second input at which the recovered bit clock is received, a parallel output having 10-bit width, and a symbol clock output; a detection circuit, receiving the symbol clock output and outputting an receiver valid, RxValid, signal and a recovered symbol clock; an elastic buffer, to store a plurality of entries and having a parallel input with a 10-bit width coupled to the parallel output of the serial to parallel converter, an input at which the recovered symbol clock is received, and an input at which a second clock signal is received, and having a parallel output and outputting a buffer overflow/underflow signal; a decoder, having a parallel input coupled to the parallel output of the elastic buffer, and input at which the second clock signal is received, having an 8-bit parallel output, and outputting an error signal; and means for storing a value corresponding to a current depth of the elastic buffer in connection with storage of an incoming entry into the elastic buffer; wherein the apparatus further comprises: a Media Access Channel unit, MAC; a PHY/MAC interface; and means for forwarding the value corresponding to the current depth of the elastic buffer over the PHY/MAC interface to the MAC. a receiver path to process data that is to be received via the serial link, the receiver path including, a differential receiver having a pair of differential input to be coupled to the serial link and a serial output; a clock recovery circuit, having first input to receive a clock signal and a second input coupled to the output of the differential receiver, and having an output comprising a recovered bit clock, a data recovery circuit, having a first input coupled to the serial output of the differential receiver, a second input at which the recovered bit clock is received, and a serial output; a serial to parallel converter, having a first input coupled to the serial output of the data recovery circuit, a second input at which the recovered bit clock is received, a parallel output having 10-bit width, and a symbol clock output; a detection circuit, receiving the symbol clock output and outputting an receiver valid, RxValid, signal and a recovered symbol clock; an elastic buffer, to store a plurality of entries and having a parallel input with a 10-bit width coupled to the parallel output of the serial to parallel converter, an input at which the recovered symbol clock is received, and an input at which a second clock signal is received, and having a parallel output and outputting a buffer overflow/underflow signal; a decoder, having a parallel input coupled to the parallel output of the elastic buffer, and input at which the second clock signal is received, having an 8-bit parallel output, and outputting an error signal; and means for storing a value corresponding to a current depth of the elastic buffer in connection with storage of an incoming entry into the elastic buffer; wherein the apparatus further comprises: a Media Access Channel unit, MAC; a PHY/MAC interface; and means for forwarding the value corresponding to the current depth of the elastic buffer over the PHY/MAC interface to the MAC. a Media Access Channel unit, MAC; a PHY/MAC interface; and means for forwarding the value corresponding to the current depth of the elastic buffer over the PHY/MAC interface to the MAC.