An amplifier (10"), comprising: a first amplifier stage comprising: a pair of first and second transistors (CS FET1, CG FET1) arranged in a cascode amplifier arrangement; and an isolation circuit, which is configured to improve low frequency isolation between the first amplifier stage and a second amplifier stage coupled to an output of the first amplifier stage; a voltage source (Vdd) coupled to the output of the first amplifier stage through the isolation circuit, and further coupled to the second amplifier stage, the isolation circuit being coupled between the second one of the pair of transistors (CG FET1) arranged in the cascode amplifier arrangement and the voltage source (Vdd), wherein the voltage source (Vdd) is configured to produce a current serially through the isolation circuit and the pair of transistors (CS FET1, CG FET1) in the cascode amplifier arrangement, wherein the isolation circuit comprises a pair of serially connected resistors (Rk, RL); a DC bias regulator comprising: a DC bias circuit comprising a current source that is configured to produce a reference current that passes through a resistor for producing a voltage (Vbc), such voltage (Vbc) being coupled to a control electrode of the first one of the pair of transistors (CS FET1) and to a corresponding control electrode of a corresponding second stage transistor (CS FET2) of the second amplifier stage; and a combiner having a pair of inputs (20, 22) coupled to: the voltage (Vdc) produced by the DC bias circuit and a voltage produced by the isolation circuit at a junction between the pair of serially connected resistors (Rk, RL) of the isolation circuit, respectively to produce a DC bias voltage at a control electrode of the second one of the pair of transistors (CG FET1) related to a combination of the voltage produced by the DC bias circuit and the voltage produced by the isolation circuit. a first amplifier stage comprising: a pair of first and second transistors (CS FET1, CG FET1) arranged in a cascode amplifier arrangement; and an isolation circuit, which is configured to improve low frequency isolation between the first amplifier stage and a pair of first and second transistors (CS FET1, CG FET1) arranged in a cascode amplifier arrangement; and an isolation circuit, which is configured to improve low frequency isolation between the first amplifier stage and a second amplifier stage coupled to an output of the first amplifier stage; a voltage source (Vdd) coupled to the output of the first amplifier stage through the isolation circuit, and further coupled to the second amplifier stage, the isolation circuit being coupled between the second one of the pair of transistors (CG FET1) arranged in the cascode amplifier arrangement and the voltage source (Vdd), wherein the voltage source (Vdd) is configured to produce a current serially through the isolation circuit and the pair of transistors (CS FET1, CG FET1) in the cascode amplifier arrangement, wherein the isolation circuit comprises a pair of serially connected resistors (Rk, RL); a DC bias regulator comprising: a DC bias circuit comprising a current source that is configured to produce a reference current that passes through a resistor for producing a voltage (Vbc), such voltage (Vbc) being coupled to a control electrode of the first one of the pair of transistors (CS FET1) and to a corresponding control electrode of a corresponding second stage transistor (CS FET2) of the second amplifier stage; and a combiner having a pair of inputs (20, 22) coupled to: the voltage (Vdc) produced by the DC bias circuit and a voltage produced by the isolation circuit at a junction between the pair of serially connected resistors (Rk, RL) of the isolation circuit, respectively to produce a DC bias voltage at a control electrode of the second one of the pair of transistors (CG FET1) related to a combination of the voltage produced by the DC bias circuit and the voltage produced by the isolation circuit. a DC bias circuit comprising a current source that is configured to produce a reference current that passes through a resistor for producing a voltage (Vbc), such voltage (Vbc) being coupled to a control electrode of the first one of the pair of transistors (CS FET1) and to a corresponding control electrode of a corresponding second stage transistor (CS FET2) of the second amplifier stage; and a combiner having a pair of inputs (20, 22) coupled to: the voltage (Vdc) produced by the DC bias circuit and a voltage produced by the isolation circuit at a junction between the pair of serially connected resistors (Rk, RL) of the isolation circuit, respectively to produce a DC bias voltage at a control electrode of the second one of the pair of transistors (CG FET1) related to a combination of the voltage produced by the DC bias circuit and the voltage produced by the isolation circuit.