An estimation unit (30, 30a-c) for estimating a nonlinearity error of a conversion circuit, wherein the conversion circuit is adapted to receive a continuous-time input signal and to output a digital output signal, wherein the continuous-time input signal is essentially bandlimited to an angular frequency band having a lower limit (ω 1) and an upper limit (ω 2), where ω 1 > ( L -1)π/ T, ω 2 < Lπ / T, L is a positive integer, and T is a sample period of the conversion circuit, the estimation unit (30, 30a-c) comprising: an input port (32, 32a-c) for receiving a digital input signal having a first sample rate 1/ T, wherein the digital input signal is the digital output signal of the conversion circuit; and an output port (34, 34a-c) for outputting a digital estimated error signal having the first sample rate, wherein the digital estimated error signal is an estimate of the nonlinearity error of the conversion circuit, wherein the estimation unit comprises a branch for each P_k, wherein P_k is an integer in a set of integers, k is an integer in a range 1 ≤ k ≤ N and P_k is greater than or equal to 2, each branch comprising: - a first linear filter unit (100- k) for generating a first signal ( s 1 ( n)) as a linear function of the digital input signal; - an interpolation unit (105- k) for interpolating the first signal ( s 1 ( n)) to generate a second signal ( s 2 ( m)) having a second sample rate which is a factor L·R_k higher than the first sample rate, wherein R_k is a value selected so that L·R_k ≥ T· ω 2 ·P_k / π; - a nonlinearity unit (110- k) for generating a third signal ( s 3 ( m)) as said second signal ( s 2 ( m)) to the power P_k; and - a second linear filter unit (115- k) for generating a component of the digital estimated error signal based on the third signal ( s 3 ( m)), wherein said component has the first sample rate, wherein filter coefficients of the first and second linear filter units are set such that the estimation unit is a discrete-time model of the conversion circuit and mimics the behaviour of the conversion circuit with a desired accuracy; and an adder circuit for generating the digital estimated error signal as the sum of all of said components of said branches. an input port (32, 32a-c) for receiving a digital input signal having a first sample rate 1/ T, wherein the digital input signal is the digital output signal of the conversion circuit; and an output port (34, 34a-c) for outputting a digital estimated error signal having the first sample rate, wherein the digital estimated error signal is an estimate of the nonlinearity error of the conversion circuit, wherein the estimation unit comprises a branch for each P_k, wherein P_k is an integer in a set of integers, k is an integer in a range 1 ≤ k ≤ N and P_k is greater than or equal to 2, each branch comprising: - a first linear filter unit (100- k) for generating a first signal ( s 1 ( n)) as a linear function of the digital input signal; - an interpolation unit (105- k) for interpolating the first signal ( s 1 ( n)) to generate a second signal ( s 2 ( m)) having a second sample rate which is a factor L·R_k higher than the first sample rate, wherein R_k is a value selected so that L·R_k ≥ T· ω 2 ·P_k / π; - a nonlinearity unit (110- k) for generating a third signal ( s 3 ( m)) as said second signal ( s 2 ( m)) to the power P_k; and - a second linear filter unit (115- k) for generating a component of the digital estimated error signal based on the third signal ( s 3 ( m)), wherein said component has the first sample rate, - a first linear filter unit (100- k) for generating a first signal ( s 1 ( n)) as a linear function of the digital input signal; - an interpolation unit (105- k) for interpolating the first signal ( s 1 ( n)) to generate a second signal ( s 2 ( m)) having a second sample rate which is a factor L·R_k higher than the first sample rate, wherein R_k is a value selected so that L·R_k ≥ T· ω 2 ·P_k / π; - a nonlinearity unit (110- k) for generating a third signal ( s 3 ( m)) as said second signal ( s 2 ( m)) to the power P_k; and - a second linear filter unit (115- k) for generating a component of the digital estimated error signal based on the third signal ( s 3 ( m)), wherein said component has the first sample rate, wherein filter coefficients of the first and second linear filter units are set such that the estimation unit is a discrete-time model of the conversion circuit and mimics the behaviour of the conversion circuit with a desired accuracy; and an adder circuit for generating the digital estimated error signal as the sum of all of said components of said branches.