A time-delay and charge summation image sensor, the charge summation of which is synchronized with the relative movement of a scene to be observed in front of the sensor, which comprises N rows of photodiode pixels and charge transfer gates, the N rows of pixels being distributed with a pitch D, each pixel of rank i in a column comprising first and second photodiodes (PPDa i, PPDb j) arranged in succession in the direction of the movement, and three charge storage nodes separated from the photodiodes by charge transfer gates, these storage nodes comprising a central node (NDC i) located between the two photodiodes, and two other nodes shared with the adjacent pixels, which nodes are a downstream node (NDE i) located between the first photodiode of the pixel of rank i and the second photodiode of the pixel of rank i+1 located immediately downstream of the pixel of rank i, and an upstream node (NDE i-1) located between the second photodiode of the pixel of rank i and the first photodiode of the pixel of rank i-1 located immediately upstream of the pixel of rank i, the sensor furthermore comprising: - an analog/digital conversion circuit (CONV i) of rank i associated with each pixel of rank i; arranged to convert into a digital format the charges received in at least one of the storage nodes of this pixel of rank i; - means for controlling the transfer gates and the conversion circuits in order to transfer the charges from a photodiode to one or other of the storage nodes that flank it then to convert these charges, in a periodic cycle of period Tp where Tp is the time it takes the image to move a distance equal to the pitch of the rows of pixels, which is a two-phased cycle, the two phases being such that for each pixel of rank i: - at the end of a first phase the charges of the two photodiodes are transferred to the central node for the purpose of a later analog/digital conversion operation by the analog/digital conversion circuit of rank I (CONV I) of the pixel of rank i; - at the end of a second phase of duration Tp/2, the charges of the first photodiode of the pixel of rank i and the charges of the second photodiode of the downstream pixel of rank i+1 are transferred to the downstream node, then the charges present in the downstream node are converted in the conversion circuit of rank i (CONV i) associated with the pixel of rank i; and - means for accumulating, in the conversion circuit of rank i, the results of the one or more conversions carried out during the current two-phase cycle with the result accumulated beforehand in the conversion circuit of rank i-1 at the end of the preceding two-phase cycle. - an analog/digital conversion circuit (CONV i) of rank i associated with each pixel of rank i; arranged to convert into a digital format the charges received in at least one of the storage nodes of this pixel of rank i; - means for controlling the transfer gates and the conversion circuits in order to transfer the charges from a photodiode to one or other of the storage nodes that flank it then to convert these charges, in a periodic cycle of period Tp where Tp is the time it takes the image to move a distance equal to the pitch of the rows of pixels, which is a two-phased cycle, the two phases being such that for each pixel of rank i: - at the end of a first phase the charges of the two photodiodes are transferred to the central node for the purpose of a later analog/digital conversion operation by the analog/digital conversion circuit of rank I (CONV I) of the pixel of rank i; - at the end of a second phase of duration Tp/2, the charges of the first photodiode of the pixel of rank i and the charges of the second photodiode of the downstream pixel of rank i+1 are transferred to the downstream node, then the charges present in the downstream node are converted in the conversion circuit of rank i (CONV i) associated with the pixel of rank i; and - means for accumulating, in the conversion circuit of rank i, the results of the one or more conversions carried out during the current two-phase cycle with the result accumulated beforehand in the conversion circuit of rank i-1 at the end of the preceding two-phase cycle.