An electronic assembly comprising an interconnect carrier comprising an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; a first integrated circuit chip mounted at a first side of the interconnect carrier; a second integrated circuit chip mounted at a second side of the interconnect carrier, wherein the second side is opposite to the first side; and an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip; wherein the electric interconnection structure extends around the insulating core and comprises at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided; wherein the electric conductor path is formed around at least one edge of the insulating core; characterized in that: the electric conductor path comprises at least two conductor tracks (252, 256); and the at least two conductor tracks (252, 254) are realized by a layered structure wherein an insulating layer is formed between the two conductor tracks (252, 254). an interconnect carrier comprising an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; a first integrated circuit chip mounted at a first side of the interconnect carrier; a second integrated circuit chip mounted at a second side of the interconnect carrier, wherein the second side is opposite to the first side; and an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip; wherein the electric interconnection structure extends around the insulating core and comprises at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided; wherein the electric conductor path is formed around at least one edge of the insulating core; characterized in that: the electric conductor path comprises at least two conductor tracks (252, 256); and the at least two conductor tracks (252, 254) are realized by a layered structure wherein an insulating layer is formed between the two conductor tracks (252, 254). wherein the electric interconnection structure extends around the insulating core and comprises at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided; wherein the electric conductor path is formed around at least one edge of the insulating core; characterized in that: the electric conductor path comprises at least two conductor tracks (252, 256); and the at least two conductor tracks (252, 254) are realized by a layered structure wherein an insulating layer is formed between the two conductor tracks (252, 254). the electric conductor path comprises at least two conductor tracks (252, 256); and the at least two conductor tracks (252, 254) are realized by a layered structure wherein an insulating layer is formed between the two conductor tracks (252, 254).