An apparatus comprising: a plurality of reconfigurable logic regions, including a first reconfigurable logic region and a second reconfigurable logic region, each reconfigurable logic region comprising configurable hardware to implement a respective application logic design; and host logic configured to separately encapsulate each of the reconfigurable logic regions, the host logic comprising: a host interface for communicating with a processor; and a plurality of data path functions accessible via the host interface, including a first data path function and a second data path function, each data path function comprising a layer for formatting data transfers between the host interface and the application logic design of a corresponding reconfigurable logic region, and wherein the host interface is configured to arbitrate between resources used by the application logic designs of the respective reconfigurable logic regions; wherein: the first data path function is positioned between the host interface and the first reconfigurable logic region and the second data path function is positioned between the host interface and the second reconfigurable logic region; the first data path function is assigned a first range of addresses and the second data path function is assigned a second range of addresses, different than the first range of addresses; each of the first and second data path functions receive information from the respective first and second reconfigurable logic regions and format the received information for transmission to the host interface including generating control information for one or more transactions; and the first and second data path functions block the first and second reconfigurable logic regions from formatting transactions and directly controlling signals used to drive a physical interconnect coupled to the host interface. a plurality of reconfigurable logic regions, including a first reconfigurable logic region and a second reconfigurable logic region, each reconfigurable logic region comprising configurable hardware to implement a respective application logic design; and host logic configured to separately encapsulate each of the reconfigurable logic regions, the host logic comprising: a host interface for communicating with a processor; and a plurality of data path functions accessible via the host interface, including a first data path function and a second data path function, each data path function comprising a layer for formatting data transfers between the host interface and the application logic design of a corresponding reconfigurable logic region, and wherein the host interface is configured to arbitrate between resources used by the application logic designs of the respective reconfigurable logic regions; wherein: the first data path function is positioned between the host interface and the first reconfigurable logic region and the second data path function is positioned between the host interface and the second reconfigurable logic region; the first data path function is assigned a first range of addresses and the second data path function is assigned a second range of addresses, different than the first range of addresses; each of the first and second data path functions receive information from the respective first and second reconfigurable logic regions and format the received information for transmission to the host interface including generating control information for one or more transactions; and the first and second data path functions block the first and second reconfigurable logic regions from formatting transactions and directly controlling signals used to drive a physical interconnect coupled to the host interface. the first data path function is positioned between the host interface and the first reconfigurable logic region and the second data path function is positioned between the host interface and the second reconfigurable logic region; the first data path function is assigned a first range of addresses and the second data path function is assigned a second range of addresses, different than the first range of addresses; each of the first and second data path functions receive information from the respective first and second reconfigurable logic regions and format the received information for transmission to the host interface including generating control information for one or more transactions; and the first and second data path functions block the first and second reconfigurable logic regions from formatting transactions and directly controlling signals used to drive a physical interconnect coupled to the host interface.