A circuit, comprising: - a switching circuit stage comprising first and second half bridges comprising a first, high-side transistor (H1, H2) and a second, low-side transistor (L1, L2), the first half bridge and the second half bridge comprising respective output nodes (Vout1, Vout2) between the high-side transistor (H1, H2) and the low-side transistor (L1, L2) therein, the output nodes (Vout1, Vout2) configured for supplying an electrical load via respective filter networks (Lo1, C1; LO2, C2) between the output nodes (Vout1, Vout2) and the load, - control circuitry (21 to 27) configured to control (VH1=VL2; VL1=VH2) alternate switching sequences (100 to 110 and 112 to 122) of the high-side (H1, H2) and low-side (L1, L2) transistors in the first and second half bridges wherein a first pair of transistors comprising the high-side transistor (H2 resp. H1) in one (HB2 resp. HB1) of the half bridges (HB1, HB2) and the low-side transistor (L1 resp. L2) in the other (HB1, resp. HB2) of the half bridges (HB1, HB2) is switched to a non-conductive state, and a second pair of transistors comprising the high-side transistor (H1 resp. H2) in the other (HB1 resp. HB2) of the half bridges (HB1, HB2) and the low-side transistor (L2 resp. L1) in the one (HB2 resp. HB1) of the half bridges (HB1, HB2) is switched to a conductive state, wherein the circuit comprises: - a current flow line between the output nodes (Vout1, Vout2) of the first half bridge and the second half bridge, the current flow line comprising an inductance (Laux), a first switch and a second switch, wherein the inductance is set between the first switch and the second switch, the first switch and the second switch selectively switchable between a non-conductive state and at least one conductive state, - first and second capacitances (Caux1, Caux2; CparH1, CparL1, CparH2, CparL2) coupled with the output nodes (Vout1, Vout2) of the first half bridge and the second half bridge, and - the control circuitry (21 to 27) configured to switch the first and second switches to the at least one conductive state at intervals (ta, tb; t1, t2) in said alternate switching sequences (100 to 110 and 112 to 122) between switching the first pair of transistors to a non-conductive state and switching the second pair of transistors to a conductive state. - a switching circuit stage comprising first and second half bridges comprising a first, high-side transistor (H1, H2) and a second, low-side transistor (L1, L2), the first half bridge and the second half bridge comprising respective output nodes (Vout1, Vout2) between the high-side transistor (H1, H2) and the low-side transistor (L1, L2) therein, the output nodes (Vout1, Vout2) configured for supplying an electrical load via respective filter networks (Lo1, C1; LO2, C2) between the output nodes (Vout1, Vout2) and the load, - control circuitry (21 to 27) configured to control (VH1=VL2; VL1=VH2) alternate switching sequences (100 to 110 and 112 to 122) of the high-side (H1, H2) and low-side (L1, L2) transistors in the first and second half bridges wherein a first pair of transistors comprising the high-side transistor (H2 resp. H1) in one (HB2 resp. HB1) of the half bridges (HB1, HB2) and the low-side transistor (L1 resp. L2) in the other (HB1, resp. HB2) of the half bridges (HB1, HB2) is switched to a non-conductive state, and a second pair of transistors comprising the high-side transistor (H1 resp. H2) in the other (HB1 resp. HB2) of the half bridges (HB1, HB2) and the low-side transistor (L2 resp. L1) in the one (HB2 resp. HB1) of the half bridges (HB1, HB2) is switched to a conductive state, - a current flow line between the output nodes (Vout1, Vout2) of the first half bridge and the second half bridge, the current flow line comprising an inductance (Laux), a first switch and a second switch, wherein the inductance is set between the first switch and the second switch, the first switch and the second switch selectively switchable between a non-conductive state and at least one conductive state, - first and second capacitances (Caux1, Caux2; CparH1, CparL1, CparH2, CparL2) coupled with the output nodes (Vout1, Vout2) of the first half bridge and the second half bridge, and - the control circuitry (21 to 27) configured to switch the first and second switches to the at least one conductive state at intervals (ta, tb; t1, t2) in said alternate switching sequences (100 to 110 and 112 to 122) between switching the first pair of transistors to a non-conductive state and switching the second pair of transistors to a conductive state.