A processor configured to control a storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b), the processor comprising: at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) generated based on device information of the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b); a control module configured to control the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), wherein the control module is further configured: to store, in the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), a plurality of write commands generated by a host (20, 2100), to merge the plurality of write commands to generate a merged write command, and to transmit the generated merged write command to the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b); and wherein a size of the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) is allocated based on a unit of interleaving processing for simultaneously processing by several chips in response to a request received from the host (20, 2100), the processor further comprising a meta-memory buffer configured to merge write commands of non-consecutive logical block addresses, wherein the meta-memory buffer is further configured to be dynamically allocated according to a number of write commands merged in the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) and store meta information including at least one of a logical block address and length information of data corresponding to each of the write commands, and wherein the control module, when transmitting a merged write command from a host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), is further configured to generate an extra header segment, EHS, including the meta information, to be transmitted to the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b). at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) generated based on device information of the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b); a control module configured to control the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), wherein the control module is further configured: to store, in the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), a plurality of write commands generated by a host (20, 2100), to merge the plurality of write commands to generate a merged write command, and to transmit the generated merged write command to the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b); and wherein a size of the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) is allocated based on a unit of interleaving processing for simultaneously processing by several chips in response to a request received from the host (20, 2100), the processor further comprising a meta-memory buffer configured to merge write commands of non-consecutive logical block addresses, wherein the meta-memory buffer is further configured to be dynamically allocated according to a number of write commands merged in the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) and store meta information including at least one of a logical block address and length information of data corresponding to each of the write commands, and wherein the control module, when transmitting a merged write command from a host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), is further configured to generate an extra header segment, EHS, including the meta information, to be transmitted to the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b). to store, in the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), a plurality of write commands generated by a host (20, 2100), to merge the plurality of write commands to generate a merged write command, and to transmit the generated merged write command to the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b); and wherein a size of the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) is allocated based on a unit of interleaving processing for simultaneously processing by several chips in response to a request received from the host (20, 2100), the processor further comprising a meta-memory buffer configured to merge write commands of non-consecutive logical block addresses, wherein the meta-memory buffer is further configured to be dynamically allocated according to a number of write commands merged in the at least one host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716) and store meta information including at least one of a logical block address and length information of data corresponding to each of the write commands, and wherein the control module, when transmitting a merged write command from a host write buffer (26, 120, 200, 210, 220, 320, 520, 620, 710, 712, 714, 716), is further configured to generate an extra header segment, EHS, including the meta information, to be transmitted to the storage device (40, 140, 330, 332, 550, 630, 632, 720, 1300a, 1300b).