An amplifier (100, 200) comprising: a driver stage amplifier transistor (130, 230) integrated in a semiconductor die and having a driver stage input terminal (132, 232), a driver stage output terminal (134, 234), and an output impedance, wherein the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output terminal (134, 234); and a final stage amplifier transistor (160, 260) integrated in the semiconductor die and having a final stage input terminal (162, 262), a final stage output terminal (164, 264), and an input impedance, wherein the final stage input terminal (162, 262) is electrically coupled to the driver stage output terminal (134, 234), and the final stage amplifier transistor (160, 260) is configured to operate using a second bias voltage at the final stage output (164, 264), and the second bias voltage is at least twice as large as the first bias voltage, wherein: a ratio of the output impedance of the driver stage amplifier transistor (130, 230) to the input impedance of the final stage amplifier transistor (160, 26) input is less than 10:1; and the amplifier further includes an interstage impedance matching circuit (140, 240) electrically coupled between the driver stage output terminal (134, 234) and the final stage input terminal (162, 262), wherein the interstage impedance matching circuit (140, 240) is configured to perform an impedance transformation from the output impedance of the driver stage amplifier transistor (130, 230) to the input impedance of the final stage amplifier transistor (160, 260). a driver stage amplifier transistor (130, 230) integrated in a semiconductor die and having a driver stage input terminal (132, 232), a driver stage output terminal (134, 234), and an output impedance, wherein the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output terminal (134, 234); and a final stage amplifier transistor (160, 260) integrated in the semiconductor die and having a final stage input terminal (162, 262), a final stage output terminal (164, 264), and an input impedance, wherein the final stage input terminal (162, 262) is electrically coupled to the driver stage output terminal (134, 234), and the final stage amplifier transistor (160, 260) is configured to operate using a second bias voltage at the final stage output (164, 264), and the second bias voltage is at least twice as large as the first bias voltage, wherein: a ratio of the output impedance of the driver stage amplifier transistor (130, 230) to the input impedance of the final stage amplifier transistor (160, 26) input is less than 10:1; and the amplifier further includes an interstage impedance matching circuit (140, 240) electrically coupled between the driver stage output terminal (134, 234) and the final stage input terminal (162, 262), wherein the interstage impedance matching circuit (140, 240) is configured to perform an impedance transformation from the output impedance of the driver stage amplifier transistor (130, 230) to the input impedance of the final stage amplifier transistor (160, 260). a ratio of the output impedance of the driver stage amplifier transistor (130, 230) to the input impedance of the final stage amplifier transistor (160, 26) input is less than 10:1; and the amplifier further includes an interstage impedance matching circuit (140, 240) electrically coupled between the driver stage output terminal (134, 234) and the final stage input terminal (162, 262), wherein the interstage impedance matching circuit (140, 240) is configured to perform an impedance transformation from the output impedance of the driver stage amplifier transistor (130, 230) to the input impedance of the final stage amplifier transistor (160, 260).