A frequency synthesizer system for receiving a frequency reference, FREF, clock and producing a radio frequency, RF, signal with an RF frequency, the system comprising: an inductive-capacitive, LC, tank oscillator circuit configured for use in duty-cycled modes to generate the RF signal, and arranged to pre-charge the capacitive element of the LC tank in a first mode of the duty-cycled modes; a digital to time converter, DTC, circuit configured to output a delayed FREF clock by: operating, for a first edge of the FREF clock, in a baseline mode that introduces a first delay value to the FREF clock; and operating, for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock, wherein the first delay value is different from the second delay value; a controller circuit configured to: enable the LC tank oscillator circuit in response to a first edge of the PREF clock, in a second mode of the duty-cycles modes; and set the second delay value as a function of the frequency of the RF signal; and a phase detector circuit configured to: receive: (i) the delayed FREF clock from the DTC circuit; and (ii) the RF signal from the LC tank oscillator circuit; detect, for the subsequent edges of the FREF clock a phase difference between the delayed FREF clock and the RF signal; and provide a feedback to the LC tank oscillator circuit for adjustment of the frequency of the RF signal. an inductive-capacitive, LC, tank oscillator circuit configured for use in duty-cycled modes to generate the RF signal, and arranged to pre-charge the capacitive element of the LC tank in a first mode of the duty-cycled modes; a digital to time converter, DTC, circuit configured to output a delayed FREF clock by: operating, for a first edge of the FREF clock, in a baseline mode that introduces a first delay value to the FREF clock; and operating, for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock, wherein the first delay value is different from the second delay value; a controller circuit configured to: enable the LC tank oscillator circuit in response to a first edge of the PREF clock, in a second mode of the duty-cycles modes; and set the second delay value as a function of the frequency of the RF signal; and a phase detector circuit configured to: receive: (i) the delayed FREF clock from the DTC circuit; and (ii) the RF signal from the LC tank oscillator circuit; detect, for the subsequent edges of the FREF clock a phase difference between the delayed FREF clock and the RF signal; and provide a feedback to the LC tank oscillator circuit for adjustment of the frequency of the RF signal. operating, for a first edge of the FREF clock, in a baseline mode that introduces a first delay value to the FREF clock; and operating, for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock, wherein the first delay value is different from the second delay value; a controller circuit configured to: enable the LC tank oscillator circuit in response to a first edge of the PREF clock, in a second mode of the duty-cycles modes; and set the second delay value as a function of the frequency of the RF signal; and a phase detector circuit configured to: receive: (i) the delayed FREF clock from the DTC circuit; and (ii) the RF signal from the LC tank oscillator circuit; detect, for the subsequent edges of the FREF clock a phase difference between the delayed FREF clock and the RF signal; and provide a feedback to the LC tank oscillator circuit for adjustment of the frequency of the RF signal. enable the LC tank oscillator circuit in response to a first edge of the PREF clock, in a second mode of the duty-cycles modes; and set the second delay value as a function of the frequency of the RF signal; and a phase detector circuit configured to: receive: (i) the delayed FREF clock from the DTC circuit; and (ii) the RF signal from the LC tank oscillator circuit; detect, for the subsequent edges of the FREF clock a phase difference between the delayed FREF clock and the RF signal; and provide a feedback to the LC tank oscillator circuit for adjustment of the frequency of the RF signal. receive: (i) the delayed FREF clock from the DTC circuit; and (ii) the RF signal from the LC tank oscillator circuit; detect, for the subsequent edges of the FREF clock a phase difference between the delayed FREF clock and the RF signal; and provide a feedback to the LC tank oscillator circuit for adjustment of the frequency of the RF signal.