Matrix-array detector comprising: - an array of pixels arranged in a matrix along rows and down columns, each pixel being capable of generating a signal according to a physical effect; - a signal generator configured to generate two clock signals (CK1, CK2) that are phase-shifted relative to one another; - a row-addressing device comprising a shift register, the shift register comprising a plurality of stages arranged in a cascade, each stage being capable of receiving, in alternation from one stage to another, one clock signal from the two clock signals (CK1, CK2), and being capable of delivering an intermediate output signal (OUTn) that is able to take a high value (Von) and a low value (Voff) allowing the pixels of the row to be activated and to be deactivated, respectively, the signal generator also being configured to generate a third clock signal, the addressing device also comprising a plurality of isolation circuits, each isolation circuit being connected between each stage and the corresponding row of the matrix, and configured to receive the third clock signal, the isolation circuit being configured to deliver a selection signal (OUT_LINE_n) for selecting the corresponding row of the matrix when the intermediate output signal (OUTn) and the third clock signal are at the high level (Von), wherein the isolation circuit comprises an input terminal capable of receiving the intermediate output signal (OUTn), an output terminal configured to deliver the selection signal (OUT_LINE_n), a first transistor referred to as an isolation transistor, the gate of which is connected to the input terminal via a diode-connected transistor (TFTD), the source of which is connected to the output terminal and the drain of which is connected to receive the third clock signal, and a boost capacitor (C_GDFD) that is arranged between the gate and the source of the first isolation transistor, characterized in that the isolation circuit comprises a second transistor referred to as an isolation transistor (TFT_RF) configured to isolate the output terminal from the boost capacitor (C_GDFD) when it is off. - an array of pixels arranged in a matrix along rows and down columns, each pixel being capable of generating a signal according to a physical effect; - a signal generator configured to generate two clock signals (CK1, CK2) that are phase-shifted relative to one another; - a row-addressing device comprising a shift register, the shift register comprising a plurality of stages arranged in a cascade, each stage being capable of receiving, in alternation from one stage to another, one clock signal from the two clock signals (CK1, CK2), and being capable of delivering an intermediate output signal (OUTn) that is able to take a high value (Von) and a low value (Voff) allowing the pixels of the row to be activated and to be deactivated, respectively, the signal generator also being configured to generate a third clock signal, the addressing device also comprising a plurality of isolation circuits, each isolation circuit being connected between each stage and the corresponding row of the matrix, and configured to receive the third clock signal, the isolation circuit being configured to deliver a selection signal (OUT_LINE_n) for selecting the corresponding row of the matrix when the intermediate output signal (OUTn) and the third clock signal are at the high level (Von), wherein the isolation circuit comprises an input terminal capable of receiving the intermediate output signal (OUTn), an output terminal configured to deliver the selection signal (OUT_LINE_n), a first transistor referred to as an isolation transistor, the gate of which is connected to the input terminal via a diode-connected transistor (TFTD), the source of which is connected to the output terminal and the drain of which is connected to receive the third clock signal, and a boost capacitor (C_GDFD) that is arranged between the gate and the source of the first isolation transistor, characterized in that the isolation circuit comprises a second transistor referred to as an isolation transistor (TFT_RF) configured to isolate the output terminal from the boost capacitor (C_GDFD) when it is off. the signal generator also being configured to generate a third clock signal, the addressing device also comprising a plurality of isolation circuits, each isolation circuit being connected between each stage and the corresponding row of the matrix, and configured to receive the third clock signal, the isolation circuit being configured to deliver a selection signal (OUT_LINE_n) for selecting the corresponding row of the matrix when the intermediate output signal (OUTn) and the third clock signal are at the high level (Von), wherein the isolation circuit comprises an input terminal capable of receiving the intermediate output signal (OUTn), an output terminal configured to deliver the selection signal (OUT_LINE_n), a first transistor referred to as an isolation transistor, the gate of which is connected to the input terminal via a diode-connected transistor (TFTD), the source of which is connected to the output terminal and the drain of which is connected to receive the third clock signal, and a boost capacitor (C_GDFD) that is arranged between the gate and the source of the first isolation transistor, characterized in that the isolation circuit comprises a second transistor referred to as an isolation transistor (TFT_RF) configured to isolate the output terminal from the boost capacitor (C_GDFD) when it is off.