An apparatus, comprising: a first circuit path having a first frequency divider configured to frequency divide a first periodic signal to generate a first divided signal; a second circuit path having a second frequency divider configured to frequency divide a second periodic signal to generate a second divided signal; a phase detection circuit coupled to the first and second circuit paths and configured to: compare phases of a first sensing signal based on the first divided signal and of a second sensing signal based on the second divided signal; and generate a first trigger signal if the first and second sensing signals are out-of-phase; a first clock pulse suppression circuit comprised in a first pulse swallowing circuit coupled to the phase detection circuit and configured to suppress a pulse of the first periodic signal for at least one cycle in response to the first trigger signal to adjust a phase of the first divided signal; characterized in that the apparatus further comprises: a third frequency divider configured to frequency divide the first divided signal to generate a third divided signal, wherein the first sensing signal is the third divided signal; and a fourth frequency divider configured to frequency divide the second divided signal to generate a fourth divided signal, wherein the second sensing signal is the fourth divided signal; and a second clock pulse suppression circuit comprised in a second pulse swallowing circuit coupled to the phase detection circuit, wherein the phase detection circuit is configured to generate a second trigger signal if the first and second sensing signals are out-of-phase, wherein the second clock pulse suppression circuit is configured to suppress a pulse of the first divided signal for at least one cycle in response to the second trigger signal to adjust a phase of the third divided signal. a first circuit path having a first frequency divider configured to frequency divide a first periodic signal to generate a first divided signal; a second circuit path having a second frequency divider configured to frequency divide a second periodic signal to generate a second divided signal; a phase detection circuit coupled to the first and second circuit paths and configured to: compare phases of a first sensing signal based on the first divided signal and of a second sensing signal based on the second divided signal; and generate a first trigger signal if the first and second sensing signals are out-of-phase; compare phases of a first sensing signal based on the first divided signal and of a second sensing signal based on the second divided signal; and generate a first trigger signal if the first and second sensing signals are out-of-phase; a first clock pulse suppression circuit comprised in a first pulse swallowing circuit coupled to the phase detection circuit and configured to suppress a pulse of the first periodic signal for at least one cycle in response to the first trigger signal to adjust a phase of the first divided signal; characterized in that the apparatus further comprises: a third frequency divider configured to frequency divide the first divided signal to generate a third divided signal, wherein the first sensing signal is the third divided signal; and a fourth frequency divider configured to frequency divide the second divided signal to generate a fourth divided signal, wherein the second sensing signal is the fourth divided signal; and a second clock pulse suppression circuit comprised in a second pulse swallowing circuit coupled to the phase detection circuit, wherein the phase detection circuit is configured to generate a second trigger signal if the first and second sensing signals are out-of-phase, wherein the second clock pulse suppression circuit is configured to suppress a pulse of the first divided signal for at least one cycle in response to the second trigger signal to adjust a phase of the third divided signal. a third frequency divider configured to frequency divide the first divided signal to generate a third divided signal, wherein the first sensing signal is the third divided signal; and a fourth frequency divider configured to frequency divide the second divided signal to generate a fourth divided signal, wherein the second sensing signal is the fourth divided signal; and a second clock pulse suppression circuit comprised in a second pulse swallowing circuit coupled to the phase detection circuit, wherein the phase detection circuit is configured to generate a second trigger signal if the first and second sensing signals are out-of-phase, wherein the second clock pulse suppression circuit is configured to suppress a pulse of the first divided signal for at least one cycle in response to the second trigger signal to adjust a phase of the third divided signal.