An integrated circuit device (100, 200, 300, 400),comprising: a plurality of inputs/outputs of the integrated circuit device; a plurality of analog blocks, wherein the plurality of analog blocks is different from the plurality of inputs/outputs, the plurality of analog blocks including: a fixed function analog circuit; and a plurality of reconfigurable analog circuit blocks including a continuous time block (406, 408-0, 408-1) comprising a plurality of reconfigurable analog circuits for executing signal processing in a continuous time domain and a discrete time block (412-0, 412-1) comprising reconfigurable analog circuits with a reconfigurable switch network (410-0, 410-1, 410-2); an analog multiplexer configured to selectively connect any of the plurality of input/outputs to the plurality of analog blocks, the analog multiplexer including at least one low noise signal path pair having a lower resistance than other signal paths of the analog multiplexer; a digital section comprising digital circuits; and a processor interface coupled to the plurality of analog blocks; and a reconfigurable routing network configured to provide at least two different types of signal routing between any of the plurality of analog blocks, comprising a standard routing and at least one or more of a low resistance routing and a low noise routing, wherein the reconfigurable routing network is configured to provide at least one of: a buffered differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block to the buffered differential signal path; a driven front-end differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block and the discrete time block to the driven front-end differential signal path; and a filtered differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block and the discrete time block to the filtered differential signal path. a plurality of inputs/outputs of the integrated circuit device; a plurality of analog blocks, wherein the plurality of analog blocks is different from the plurality of inputs/outputs, the plurality of analog blocks including: a fixed function analog circuit; and a plurality of reconfigurable analog circuit blocks including a continuous time block (406, 408-0, 408-1) comprising a plurality of reconfigurable analog circuits for executing signal processing in a continuous time domain and a discrete time block (412-0, 412-1) comprising reconfigurable analog circuits with a reconfigurable switch network (410-0, 410-1, 410-2); an analog multiplexer configured to selectively connect any of the plurality of input/outputs to the plurality of analog blocks, the analog multiplexer including at least one low noise signal path pair having a lower resistance than other signal paths of the analog multiplexer; a fixed function analog circuit; and a plurality of reconfigurable analog circuit blocks including a continuous time block (406, 408-0, 408-1) comprising a plurality of reconfigurable analog circuits for executing signal processing in a continuous time domain and a discrete time block (412-0, 412-1) comprising reconfigurable analog circuits with a reconfigurable switch network (410-0, 410-1, 410-2); an analog multiplexer configured to selectively connect any of the plurality of input/outputs to the plurality of analog blocks, the analog multiplexer including at least one low noise signal path pair having a lower resistance than other signal paths of the analog multiplexer; a digital section comprising digital circuits; and a processor interface coupled to the plurality of analog blocks; and a reconfigurable routing network configured to provide at least two different types of signal routing between any of the plurality of analog blocks, comprising a standard routing and at least one or more of a low resistance routing and a low noise routing, wherein the reconfigurable routing network is configured to provide at least one of: a buffered differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block to the buffered differential signal path; a driven front-end differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block and the discrete time block to the driven front-end differential signal path; and a filtered differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block and the discrete time block to the filtered differential signal path. a buffered differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block to the buffered differential signal path; a driven front-end differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block and the discrete time block to the driven front-end differential signal path; and a filtered differential signal path to the fixed function analog circuit, wherein the reconfigurable analog routing network is configured to couple the continuous time block and the discrete time block to the filtered differential signal path.