A device including: a sample and digital to analog conversion, DAC, circuit configured to sample an input voltage to obtain a first sampled voltage; a first comparator coupled to the sample and DAC circuit; a first set of storage circuits coupled to the first comparator and the sample and DAC circuit, the first set of storage circuits being configured to store a first subset of a plurality of bits corresponding to the input voltage; a second comparator coupled to the sample and DAC circuit; a second set of storage circuits coupled to the second comparator and the sample and DAC circuit, the second set of storage circuits being configured to store a second subset of the plurality of bits corresponding to the input voltage; and a control circuit coupled to the first comparator and the second comparator, the control circuit being configured to select, during a first time period for a first bit of the plurality of bits corresponding to the input voltage, the first comparator to determine a state of the first bit of the plurality of bits according to the first sampled voltage; wherein the sample and DAC circuit is configured to sample, for the first bit of the plurality of bits, the input voltage to obtain the first sampled voltage, wherein the first comparator is configured to determine a state of the first bit of the plurality of bits according to the first sampled voltage; and based at least in part on the determined state of the first bit of the plurality of bits from the corresponding one of the first set of storage circuits, the sample and DAC circuit is configured to sample, for a second bit of the plurality of bits, the input voltage to obtain a second sampled voltage, wherein the second comparator is configured to determine a state of the second bit of the plurality of bits according to the second sampled voltage. a sample and digital to analog conversion, DAC, circuit configured to sample an input voltage to obtain a first sampled voltage; a first comparator coupled to the sample and DAC circuit; a first set of storage circuits coupled to the first comparator and the sample and DAC circuit, the first set of storage circuits being configured to store a first subset of a plurality of bits corresponding to the input voltage; a second comparator coupled to the sample and DAC circuit; a second set of storage circuits coupled to the second comparator and the sample and DAC circuit, the second set of storage circuits being configured to store a second subset of the plurality of bits corresponding to the input voltage; and a control circuit coupled to the first comparator and the second comparator, the control circuit being configured to select, during a first time period for a first bit of the plurality of bits corresponding to the input voltage, the first comparator to determine a state of the first bit of the plurality of bits according to the first sampled voltage; wherein the sample and DAC circuit is configured to sample, for the first bit of the plurality of bits, the input voltage to obtain the first sampled voltage, wherein the first comparator is configured to determine a state of the first bit of the plurality of bits according to the first sampled voltage; and based at least in part on the determined state of the first bit of the plurality of bits from the corresponding one of the first set of storage circuits, the sample and DAC circuit is configured to sample, for a second bit of the plurality of bits, the input voltage to obtain a second sampled voltage, wherein the second comparator is configured to determine a state of the second bit of the plurality of bits according to the second sampled voltage.