A processor (300; 1900; 2170; 2180; 1300) comprising: a decode unit (314; 1314) to decode an instruction, the instruction to indicate a destination memory address information; and an execution unit (316; 1116; 1216; 1310) coupled with the decode unit (314; 1314), the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, to: store memory addresses, for at least all initial writes to corresponding data items, which writes are to occur after the instruction in original program order, to a memory address log, a start of the memory address log to correspond to the destination memory address information, characterized in that the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, is to store the data items, for said at least all initial writes, before the data items are updated due to said at least all initial writes, to a data item log, that the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, is to said store the memory addresses and said store the data items to a combined memory address and data item log, wherein a start of the combined memory address and data item log is to correspond to the destination memory address information, and wherein the corresponding memory addresses and data items are to be interleaved with one another in the combined memory address and data item log, that the combined memory address and data item log is stored in a memory at a starting memory location, which corresponds to destination memory address information indicated by a begin memory write log instruction and that the combined memory address and data item log stores both memory addresses (MAs) of a first size and data items (DIs) of a second size. a decode unit (314; 1314) to decode an instruction, the instruction to indicate a destination memory address information; and an execution unit (316; 1116; 1216; 1310) coupled with the decode unit (314; 1314), the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, to: store memory addresses, for at least all initial writes to corresponding data items, which writes are to occur after the instruction in original program order, to a memory address log, a start of the memory address log to correspond to the destination memory address information, characterized in that the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, is to store the data items, for said at least all initial writes, before the data items are updated due to said at least all initial writes, to a data item log, that the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, is to said store the memory addresses and said store the data items to a combined memory address and data item log, wherein a start of the combined memory address and data item log is to correspond to the destination memory address information, and wherein the corresponding memory addresses and data items are to be interleaved with one another in the combined memory address and data item log, that the combined memory address and data item log is stored in a memory at a starting memory location, which corresponds to destination memory address information indicated by a begin memory write log instruction and that the combined memory address and data item log stores both memory addresses (MAs) of a first size and data items (DIs) of a second size. store memory addresses, for at least all initial writes to corresponding data items, which writes are to occur after the instruction in original program order, to a memory address log, a start of the memory address log to correspond to the destination memory address information, characterized in that the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, is to store the data items, for said at least all initial writes, before the data items are updated due to said at least all initial writes, to a data item log, that the execution unit (316; 1116; 1216; 1310), in response to the decode of the instruction, is to said store the memory addresses and said store the data items to a combined memory address and data item log, wherein a start of the combined memory address and data item log is to correspond to the destination memory address information, and wherein the corresponding memory addresses and data items are to be interleaved with one another in the combined memory address and data item log, that the combined memory address and data item log is stored in a memory at a starting memory location, which corresponds to destination memory address information indicated by a begin memory write log instruction and that the combined memory address and data item log stores both memory addresses (MAs) of a first size and data items (DIs) of a second size.