A receiver circuit comprising: a first pass circuit having a control input coupled to a first output of a differential transmission line and a signal input coupled to a second output of the differential transmission line, an output of the first pass circuit providing a first output signal, the first pass circuit comprising: a first p channel transistor having a drain, a source and a gate electrode; a first n channel transistor having a drain, a source and a gate electrode; wherein the control input of the first pass circuit includes the gate electrode of the first p channel transistor and the gate electrode of the first n channel transistor; wherein the signal input of the first pass circuit includes the source of the first p channel transistor and the source of the first n channel transistor; and wherein the output of the first pass circuit includes the drain of the first p channel transistor and the drain of the first n channel transistor; and a second pass circuit having a control input connected to the second output of the differential transmission line and a signal input coupled to the first output of the differential transmission line, an output of the second pass circuit providing a second output signal (OUT*) the second pass circuit comprising: a second p channel transistor having a drain, a source and a gate electrode; a second n channel transistor having a drain, a source and a gate electrode; wherein the control input of the second pass circuit includes the gate electrode of the second p channel transistor and the gate electrode of the second n channel transistor; wherein the signal input of the second pass circuit includes the source of the second p channel transistor and the source of the second n channel transistor; and wherein the output of the second pass circuit includes the drain of the second p channel transistor and the drain of the second n channel transistor; and a first inverter that is coupled between the first output of the differential transmission line and the control input of the first pass circuit; a second inverter that is coupled between the second output of the differential transmission line and the signal input of the first pass circuit; a third inverter having an input coupled to the first output signal, the third inverter having an output coupled to the second output signal; and a fourth inverter having an input coupled to the second output signal, the fourth inverter having an output coupled to the first output signal. a first p channel transistor having a drain, a source and a gate electrode; a first n channel transistor having a drain, a source and a gate electrode; wherein the control input of the first pass circuit includes the gate electrode of the first p channel transistor and the gate electrode of the first n channel transistor; wherein the signal input of the first pass circuit includes the source of the first p channel transistor and the source of the first n channel transistor; and wherein the output of the first pass circuit includes the drain of the first p channel transistor and the drain of the first n channel transistor; and a second pass circuit having a control input connected to the second output of the differential transmission line and a signal input coupled to the first output of the differential transmission line, an output of the second pass circuit providing a second output signal (OUT*) the second pass circuit comprising: a second p channel transistor having a drain, a source and a gate electrode; a second n channel transistor having a drain, a source and a gate electrode; wherein the control input of the second pass circuit includes the gate electrode of the second p channel transistor and the gate electrode of the second n channel transistor; wherein the signal input of the second pass circuit includes the source of the second p channel transistor and the source of the second n channel transistor; and wherein the output of the second pass circuit includes the drain of the second p channel transistor and the drain of the second n channel transistor; and a second p channel transistor having a drain, a source and a gate electrode; a second n channel transistor having a drain, a source and a gate electrode; wherein the control input of the second pass circuit includes the gate electrode of the second p channel transistor and the gate electrode of the second n channel transistor; wherein the signal input of the second pass circuit includes the source of the second p channel transistor and the source of the second n channel transistor; and wherein the output of the second pass circuit includes the drain of the second p channel transistor and the drain of the second n channel transistor; and