An RF isolation switch circuit comprising: a main N-channel transistor having a first terminal, a second terminal, and a gate terminal; a first turn-off N-channel transistor having a first terminal, a second terminal, and a gate terminal, wherein the second terminal of the first turn-off N-channel transistor is coupled to the gate terminal of the main N-channel transistor; a second turn-off N-channel transistor having a first terminal, a second terminal, and a gate terminal, wherein the second terminal of the second turn-off N-channel transistor is coupled to the first terminal of the first turn-off N-channel transistor, and wherein the first terminal of the second turn-off N-channel transistor is coupled to the first terminal of the main N-channel transistor; and a first control conductor, wherein the main N-channel transistor is configured to be turned off when a first digital control signal on the first control conductor has a first digital logic value, and wherein the main N-channel transistor is configured to be turned on when the first digital control signal on the first control conductor has a second digital logic value opposite the first digital logic value, a first resistor having a first lead coupled to the gate of the main N-channel transistor and having a second lead coupled to the first control conductor; a second control conductor, wherein a second digital control signal is present on the second control conductor, wherein the second digital control signal has the opposite digital logic value to the digital logic value of the first digital control signal on the first control conductor, wherein the second control conductor is coupled to the gate terminals of the first and second turn-off N-channel transistors; and a second resistor having a first lead coupled to the first a control conductor and having a second lead coupled to the first terminal of the first turn-off N-channel transistor. a main N-channel transistor having a first terminal, a second terminal, and a gate terminal; a first turn-off N-channel transistor having a first terminal, a second terminal, and a gate terminal, wherein the second terminal of the first turn-off N-channel transistor is coupled to the gate terminal of the main N-channel transistor; a second turn-off N-channel transistor having a first terminal, a second terminal, and a gate terminal, wherein the second terminal of the second turn-off N-channel transistor is coupled to the first terminal of the first turn-off N-channel transistor, and wherein the first terminal of the second turn-off N-channel transistor is coupled to the first terminal of the main N-channel transistor; and a first control conductor, wherein the main N-channel transistor is configured to be turned off when a first digital control signal on the first control conductor has a first digital logic value, and wherein the main N-channel transistor is configured to be turned on when the first digital control signal on the first control conductor has a second digital logic value opposite the first digital logic value, a first resistor having a first lead coupled to the gate of the main N-channel transistor and having a second lead coupled to the first control conductor; a second control conductor, wherein a second digital control signal is present on the second control conductor, wherein the second digital control signal has the opposite digital logic value to the digital logic value of the first digital control signal on the first control conductor, wherein the second control conductor is coupled to the gate terminals of the first and second turn-off N-channel transistors; and a second resistor having a first lead coupled to the first a control conductor and having a second lead coupled to the first terminal of the first turn-off N-channel transistor.