A display apparatus, comprising: a first pixel (PX (k,p); PX (k,p+1)) comprising a first pixel circuit; a second pixel (PX (k+1,p); PX (k+1,p+1)) comprising a second pixel circuit, wherein the first pixel circuit and the second pixel circuit each comprise wiring extending in a first direction and wiring extending in a second direction that crosses the first direction, wherein the second pixel (PX (k+1,p); PX (k+1,p+1)) is adjacent to the first pixel (PX (k+1,p); PX (k+1,p+1)), and wherein the first pixel (PX (k,p); PX (k,p+1)) and the second pixel (PX (k+1,p); PX (k+1,p+1)) are arranged in a column (p;p+1) extending in the second direction, wherein each of the first pixel circuit and the second pixel circuit comprises a first transistor, and the first transistor comprises a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer comprises a source region and a drain region; a first data line (161) disposed at a first side of the first transistor of each of the first pixel circuit and the second pixel circuit; a second data line (161) disposed at a second side of the first transistor of each of the first pixel circuit and the second pixel circuit, the second side opposing the first side; wherein the first data line (161) and the second data line (161) are arranged in the column (p;p+1) extending the second direction; and wherein the first data line (161 and the second data line (161 are alternately connected to the first pixel (PX(k,p); PX(k,p+1)) and the second pixel (PX(k+1,p); PX(k+1,p+1)); a driving voltage line that is at least partially overlapped by the first data line (161) and the second data line (161), wherein the driving voltage line is provided between the first semiconductor layer and the first (161) and second (161) data lines; wherein the driving voltage line is arranged in a zig-zag formation; and wherein the driving voltage line comprises a first region provided along the second direction that is overlapped by the first data line (161), a second region provided along the second direction that is overlapped by the second data line (161), and a third region that connects the first region to the second region between the first data line (161) and the second data line (161); and a first insulating layer disposed between the first data line (161) and the driving voltage line and between the second data line (161) and the driving voltage line. a first pixel (PX (k,p); PX (k,p+1)) comprising a first pixel circuit; a second pixel (PX (k+1,p); PX (k+1,p+1)) comprising a second pixel circuit, wherein the first pixel circuit and the second pixel circuit each comprise wiring extending in a first direction and wiring extending in a second direction that crosses the first direction, wherein the second pixel (PX (k+1,p); PX (k+1,p+1)) is adjacent to the first pixel (PX (k+1,p); PX (k+1,p+1)), and wherein the first pixel (PX (k,p); PX (k,p+1)) and the second pixel (PX (k+1,p); PX (k+1,p+1)) are arranged in a column (p;p+1) extending in the second direction, wherein each of the first pixel circuit and the second pixel circuit comprises a first transistor, and the first transistor comprises a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer comprises a source region and a drain region; a first data line (161) disposed at a first side of the first transistor of each of the first pixel circuit and the second pixel circuit; a second data line (161) disposed at a second side of the first transistor of each of the first pixel circuit and the second pixel circuit, the second side opposing the first side; wherein the first data line (161) and the second data line (161) are arranged in the column (p;p+1) extending the second direction; and wherein the first data line (161 and the second data line (161 are alternately connected to the first pixel (PX(k,p); PX(k,p+1)) and the second pixel (PX(k+1,p); PX(k+1,p+1)); a driving voltage line that is at least partially overlapped by the first data line (161) and the second data line (161), wherein the driving voltage line is provided between the first semiconductor layer and the first (161) and second (161) data lines; wherein the driving voltage line is arranged in a zig-zag formation; and wherein the driving voltage line comprises a first region provided along the second direction that is overlapped by the first data line (161), a second region provided along the second direction that is overlapped by the second data line (161), and a third region that connects the first region to the second region between the first data line (161) and the second data line (161); and a first insulating layer disposed between the first data line (161) and the driving voltage line and between the second data line (161) and the driving voltage line.