A packing unit comprising: a laminated chip electronic component and a packing sheet including a receiving portion for receiving the laminated chip electronic component, wherein the laminated chip electronic component comprises: external electrodes (40, 44) formed on both end portions of a ceramic body having a hexahedral shape in a length direction; an active layer formed within the ceramic body and including a plurality of internal electrodes (20, 22, 24) disposed to face each other, while having dielectric layers interposed therebetween to form capacitance; an upper cover layer formed on an upper portion of the uppermost internal electrode of the active layer; a lower cover layer formed on a lower portion of the lowermost internal electrode of the active layer, and having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of formation of a capacitance within the lower cover layer, characterized in that when half of the overall thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, and half of the overall thickness of the active layer is defined as C, a ratio (B+C)/A by which a central portion of the active layer deviates from a central portion of the ceramic body satisfies 1.069≤(B+C)/A≤1.763, wherein the internal electrodes are disposed to be aligned in a parallel manner to the printed circuit board and a lower surface of the receiving portion, and the laminated chip electronic component received in the receiving portion is disposed such that the lower cover layer thereof faces the lower surface of the receiving portion. a laminated chip electronic component and a packing sheet including a receiving portion for receiving the laminated chip electronic component, wherein the laminated chip electronic component comprises: external electrodes (40, 44) formed on both end portions of a ceramic body having a hexahedral shape in a length direction; an active layer formed within the ceramic body and including a plurality of internal electrodes (20, 22, 24) disposed to face each other, while having dielectric layers interposed therebetween to form capacitance; an upper cover layer formed on an upper portion of the uppermost internal electrode of the active layer; a lower cover layer formed on a lower portion of the lowermost internal electrode of the active layer, and having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of formation of a capacitance within the lower cover layer, characterized in that when half of the overall thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, and half of the overall thickness of the active layer is defined as C, a ratio (B+C)/A by which a central portion of the active layer deviates from a central portion of the ceramic body satisfies 1.069≤(B+C)/A≤1.763, wherein the internal electrodes are disposed to be aligned in a parallel manner to the printed circuit board and a lower surface of the receiving portion, and the laminated chip electronic component received in the receiving portion is disposed such that the lower cover layer thereof faces the lower surface of the receiving portion. external electrodes (40, 44) formed on both end portions of a ceramic body having a hexahedral shape in a length direction; an active layer formed within the ceramic body and including a plurality of internal electrodes (20, 22, 24) disposed to face each other, while having dielectric layers interposed therebetween to form capacitance; an upper cover layer formed on an upper portion of the uppermost internal electrode of the active layer; a lower cover layer formed on a lower portion of the lowermost internal electrode of the active layer, and having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of formation of a capacitance within the lower cover layer, characterized in that when half of the overall thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, and half of the overall thickness of the active layer is defined as C, a ratio (B+C)/A by which a central portion of the active layer deviates from a central portion of the ceramic body satisfies 1.069≤(B+C)/A≤1.763, wherein the internal electrodes are disposed to be aligned in a parallel manner to the printed circuit board and a lower surface of the receiving portion, and the laminated chip electronic component received in the receiving portion is disposed such that the lower cover layer thereof faces the lower surface of the receiving portion.