An apparatus comprising: a plurality of logical processors; a cache shared by the plurality of logical processors; and a bus to couple the cache to a memory to service a memory request for the memory from the plurality of logical processors; characterized in that the apparatus further comprises: a control register comprising a non-write-back lock disable bit; a memory controller to disable a non-write-back lock access of the bus for a read-modify-write type of the memory request issued by a logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to a first value, and implement the non-write-back lock access of the bus for the read-modify-write type of the memory request when the non-write-back lock disable bit is set to a second value; wherein the apparatus further comprises a capabilities register comprising a capability bit that, when set to a first value, indicates the plurality of logical processors supports a non-write-back lock access disable feature, and, when set to a second value, indicates the plurality of logical processors does not support the non-write-back lock access disable feature; and/or wherein the memory controller is to, when a cache disable bit is set to a value in a second control register to disable the cache, not disable the non-write-back lock access of the bus for the read-modify-write type of the memory request issued by the logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to the first value; and/or wherein the memory controller is to, when extended page tables are enabled and memory type is set to non-write-back, not disable the non-write-back lock access of the bus for the read-modify-write type of the memory request issued by the logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to the first value. a plurality of logical processors; a cache shared by the plurality of logical processors; and a bus to couple the cache to a memory to service a memory request for the memory from the plurality of logical processors; characterized in that the apparatus further comprises: a control register comprising a non-write-back lock disable bit; a memory controller to disable a non-write-back lock access of the bus for a read-modify-write type of the memory request issued by a logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to a first value, and implement the non-write-back lock access of the bus for the read-modify-write type of the memory request when the non-write-back lock disable bit is set to a second value; wherein the apparatus further comprises a capabilities register comprising a capability bit that, when set to a first value, indicates the plurality of logical processors supports a non-write-back lock access disable feature, and, when set to a second value, indicates the plurality of logical processors does not support the non-write-back lock access disable feature; and/or wherein the memory controller is to, when a cache disable bit is set to a value in a second control register to disable the cache, not disable the non-write-back lock access of the bus for the read-modify-write type of the memory request issued by the logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to the first value; and/or wherein the memory controller is to, when extended page tables are enabled and memory type is set to non-write-back, not disable the non-write-back lock access of the bus for the read-modify-write type of the memory request issued by the logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to the first value. a control register comprising a non-write-back lock disable bit; a memory controller to disable a non-write-back lock access of the bus for a read-modify-write type of the memory request issued by a logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to a first value, and implement the non-write-back lock access of the bus for the read-modify-write type of the memory request when the non-write-back lock disable bit is set to a second value; wherein the apparatus further comprises a capabilities register comprising a capability bit that, when set to a first value, indicates the plurality of logical processors supports a non-write-back lock access disable feature, and, when set to a second value, indicates the plurality of logical processors does not support the non-write-back lock access disable feature; and/or wherein the memory controller is to, when a cache disable bit is set to a value in a second control register to disable the cache, not disable the non-write-back lock access of the bus for the read-modify-write type of the memory request issued by the logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to the first value; and/or wherein the memory controller is to, when extended page tables are enabled and memory type is set to non-write-back, not disable the non-write-back lock access of the bus for the read-modify-write type of the memory request issued by the logical processor of the plurality of logical processors when the non-write-back lock disable bit is set to the first value.