A method of manufacturing a semiconductor device comprising the steps of: providing a wafer having a plurality of chips, each chip having a device formed on a main surface of the wafer and a plurality of test areas in plan view, the test areas of the chips being of same size and shape, providing each test area with a plurality of probe contact pads (101, 102, 103, 121, 122) including a first pad and a second pad which are electrically connected to the device formed on the main surface of the wafer, wherein the plurality of probe contact pads (101, 102, 103, 121, 122) are configured at same positions in each test area, probe testing the test areas on the same chip individually using a common set of test probes, such that with repeating predetermined movement of the wafer, the respective pluralities of probe contact pads (101, 102, 103, 121, 122) of different test areas on the same chip are successively brought into coincidence with a plurality of predetermined test probe contact positions for contact with the common set of test probes, wherein the chips are rectangular and the predetermined movement includes movement along a longer side of each chip for successive probe testing of adjacent test areas of each chip, and dicing the wafer and taking out the separated chips after the probe testing, characterized in that - the semiconductor device is an MEMS semiconductor device, - the first pad and the second pad of each test area are probe-tested and wire-bonded after the probe testing is finished, - each of the chips has a non-test area, - the non-test area comprises a third pad which is not probe-tested, but wire-bonded after the probe testing is finished, - the plurality of probe contact pads (101, 102, 103, 121, 122) in each test area further comprises a fourth pad which is probe-tested, but not wire-bonded after the probe testing is finished, and in that the fourth pad in each test area and the third pad are electrically connected by a wiring on each chip at least in the stage of the probe test, wherein in each chip, the wiring and the fourth pads provided for probe tests are either left as they are or removed by etching, or the wiring is cut by laser, after the probe testing is finished. providing a wafer having a plurality of chips, each chip having a device formed on a main surface of the wafer and a plurality of test areas in plan view, the test areas of the chips being of same size and shape, providing each test area with a plurality of probe contact pads (101, 102, 103, 121, 122) including a first pad and a second pad which are electrically connected to the device formed on the main surface of the wafer, wherein the plurality of probe contact pads (101, 102, 103, 121, 122) are configured at same positions in each test area, probe testing the test areas on the same chip individually using a common set of test probes, such that with repeating predetermined movement of the wafer, the respective pluralities of probe contact pads (101, 102, 103, 121, 122) of different test areas on the same chip are successively brought into coincidence with a plurality of predetermined test probe contact positions for contact with the common set of test probes, wherein the chips are rectangular and the predetermined movement includes movement along a longer side of each chip for successive probe testing of adjacent test areas of each chip, - the semiconductor device is an MEMS semiconductor device, - the first pad and the second pad of each test area are probe-tested and wire-bonded after the probe testing is finished, - each of the chips has a non-test area, - the non-test area comprises a third pad which is not probe-tested, but wire-bonded after the probe testing is finished, - the plurality of probe contact pads (101, 102, 103, 121, 122) in each test area further comprises a fourth pad which is probe-tested, but not wire-bonded after the probe testing is finished,