A class AB amplifier comprising: a first inductor (L 1) having a first terminal connected to a voltage source terminal (V dd); a first transistor (T 1) having a drain terminal connected to a second terminal of the first inductor (L 1); a second transistor (T 2) having a source terminal connected to a source terminal of the first transistor (T 1); a second inductor (L 2) having a first terminal connected to a drain terminal of the second transistor (T 2) and a second terminal connected to a reference potential (V ss); a first variable capacitance (C 1) connected in parallel with the first inductor (L 1); a second variable capacitance (C 2) connected in parallel with the second inductor (L 2); a third inductor (L 4) having a first terminal connected to the voltage source terminal (V dd); a third transistor (T 4) having a drain terminal connected to a second terminal of the third inductor (L 4); a fourth transistor (T 3) having a source terminal connected to a source terminal of the third transistor (T 4); and a fourth inductor (L 3) having a first terminal connected to a drain terminal of the fourth transistor (T 3) and a second terminal connected to the reference potential (V ss); a third variable capacitance (C 4) connected in parallel with the third inductor (L 4); a fourth variable capacitance (C 3) connected in parallel with the fourth inductor (L 3); first (C 5) and second (C 6) capacitances connected in series with each other and connected in parallel to the drain terminals of the first transistor (T 1) and the second transistor (T 2), respectively; third (C 7) and fourth (C 8) capacitances connected in series with each other and connected in parallel to the drain terminals of the third transistor (T 4) and the fourth transistor (T 3), respectively; a fifth capacitance (C 10) having a first terminal connected between the first (C 5) and second (C 6) capacitances and to the source terminals of the first transistor (T 2) and the second transistor (T 2) and having a second terminal connected between the third (C 7) and fourth (C 8) capacitances and to the source terminals of the third transistor (T 4) and the fourth transistor (T 3); a sixth capacitance (C 9) having a first terminal connected to the drain terminal of the first transistor (T 2) and a second terminal connected to the drain terminal of the third transistor; and a seventh capacitance (C 11) having a first terminal connected to the drain terminal of the second transistor (T 2) and a second terminal connected to the drain terminal of the fourth transistor. a first inductor (L 1) having a first terminal connected to a voltage source terminal (V dd); a first transistor (T 1) having a drain terminal connected to a second terminal of the first inductor (L 1); a second transistor (T 2) having a source terminal connected to a source terminal of the first transistor (T 1); a second inductor (L 2) having a first terminal connected to a drain terminal of the second transistor (T 2) and a second terminal connected to a reference potential (V ss); a first variable capacitance (C 1) connected in parallel with the first inductor (L 1); a second variable capacitance (C 2) connected in parallel with the second inductor (L 2); a third inductor (L 4) having a first terminal connected to the voltage source terminal (V dd); a third transistor (T 4) having a drain terminal connected to a second terminal of the third inductor (L 4); a fourth transistor (T 3) having a source terminal connected to a source terminal of the third transistor (T 4); and a fourth inductor (L 3) having a first terminal connected to a drain terminal of the fourth transistor (T 3) and a second terminal connected to the reference potential (V ss); a third variable capacitance (C 4) connected in parallel with the third inductor (L 4); a fourth variable capacitance (C 3) connected in parallel with the fourth inductor (L 3); first (C 5) and second (C 6) capacitances connected in series with each other and connected in parallel to the drain terminals of the first transistor (T 1) and the second transistor (T 2), respectively; third (C 7) and fourth (C 8) capacitances connected in series with each other and connected in parallel to the drain terminals of the third transistor (T 4) and the fourth transistor (T 3), respectively; a fifth capacitance (C 10) having a first terminal connected between the first (C 5) and second (C 6) capacitances and to the source terminals of the first transistor (T 2) and the second transistor (T 2) and having a second terminal connected between the third (C 7) and fourth (C 8) capacitances and to the source terminals of the third transistor (T 4) and the fourth transistor (T 3); a sixth capacitance (C 9) having a first terminal connected to the drain terminal of the first transistor (T 2) and a second terminal connected to the drain terminal of the third transistor; and a seventh capacitance (C 11) having a first terminal connected to the drain terminal of the second transistor (T 2) and a second terminal connected to the drain terminal of the fourth transistor.