A display panel comprising: a substrate including a plurality of pixels arranged in a first area and in a second area (CA, PA); a gate driver (130, 140) configured to supply a gate signal to the pixels, the gate driver (130, 140) including at least one first stage connected to the pixels in the first area and at least one second stage connected to the pixels in the second area; at least one amplifier configured to generate a first clock signal (Cka) and a second clock signal (Ckb), the second clock signal (Ckb) having the same phase as the first clock signal (Cka), a first clock signal line connected to the first stage for providing the first clock signal (Cka); and a second clock signal line connected to the second stage for providing the second clock signal (Ckb), wherein the gate driver (130, 140) includes an emission driver and a scan driver, the scan driver comprising the first and second stages, the emission driver comprising emission stages connected to the pixels in the first and second areas, wherein the display panel is configured to be driven either in a normal driving mode or in a partial driving mode, wherein in the partial driving mode the pixels in the first area are controlled to be in an off state by the emission stages of the emission driver connected to the pixels in the first area and wherein the pixels in the second area (CA, PA) are controlled to be in an on state by the emission stages of the emission driver connected to the pixels in the second area (CA, PA), wherein the first stage of the scan driver connected to pixels in the first area and the second stage of the scan driver connected to pixels in the second area (CA, PA) are configured to be driven at the same time in the partial driving mode. a substrate including a plurality of pixels arranged in a first area and in a second area (CA, PA); a gate driver (130, 140) configured to supply a gate signal to the pixels, the gate driver (130, 140) including at least one first stage connected to the pixels in the first area and at least one second stage connected to the pixels in the second area; at least one amplifier configured to generate a first clock signal (Cka) and a second clock signal (Ckb), the second clock signal (Ckb) having the same phase as the first clock signal (Cka), a first clock signal line connected to the first stage for providing the first clock signal (Cka); and a second clock signal line connected to the second stage for providing the second clock signal (Ckb), wherein the gate driver (130, 140) includes an emission driver and a scan driver, the scan driver comprising the first and second stages, the emission driver comprising emission stages connected to the pixels in the first and second areas, wherein the display panel is configured to be driven either in a normal driving mode or in a partial driving mode, wherein in the partial driving mode the pixels in the first area are controlled to be in an off state by the emission stages of the emission driver connected to the pixels in the first area and wherein the pixels in the second area (CA, PA) are controlled to be in an on state by the emission stages of the emission driver connected to the pixels in the second area (CA, PA), a gate driver (130, 140) configured to supply a gate signal to the pixels, the gate driver (130, 140) including at least one first stage connected to the pixels in the first area and at least one second stage connected to the pixels in the second area; at least one amplifier configured to generate a first clock signal (Cka) and a second clock signal (Ckb), the second clock signal (Ckb) having the same phase as the first clock signal (Cka), a first clock signal line connected to the first stage for providing the first clock signal (Cka); and a second clock signal line connected to the second stage for providing the second clock signal (Ckb), wherein the gate driver (130, 140) includes an emission driver and a scan driver, the scan driver comprising the first and second stages, the emission driver comprising emission stages connected to the pixels in the first and second areas, wherein the display panel is configured to be driven either in a normal driving mode or in a partial driving mode, wherein in the partial driving mode the pixels in the first area are controlled to be in an off state by the emission stages of the emission driver connected to the pixels in the first area and wherein the pixels in the second area (CA, PA) are controlled to be in an on state by the emission stages of the emission driver connected to the pixels in the second area (CA, PA), wherein the first stage of the scan driver connected to pixels in the first area and the second stage of the scan driver connected to pixels in the second area (CA, PA) are configured to be driven at the same time in the partial driving mode.