An integrated circuit, comprising: a transmitter, wherein the transmitter comprises: a transmit shift register, an output driver bank, and a tap weight register, wherein the transmitter (201, 531) is configured to transmit a plurality of data values of a digital sequence onto a signal path (202, 532) external to the integrated circuit to a receiver (209, 539), using a signal level that is a logical function of a binary state of a current data value (D 0) to be transmitted and binary state of a first other data value (D +1, D -1, D -2, D -3) of the digital sequence, the first other data value (D +1, D -1, D -2, D -3) being one of a next-to-be-transmitted and/or previously transmitted data value, the transmitter (201, 531) characterized by a peak power constraint, wherein the output driver bank comprises one or more output drivers wherein the outputs of all output drivers are connected to the signal path for generating the signal level, wherein the transmit shift register is configured to store the current data value (D 0) to be transmitted and the first other data value (D +1, D -1, D -2, D -3) of the digital sequence, wherein each element of the transmit shift register is coupled to a respective one of output drivers (205 0 -205 4) within the output driver bank 204, wherein the tap weight register is configured to store a set of tap weights (W N), and wherein each tap weight (W N) is supplied to a respective one of the output drivers to control the level of the output signal generated by the output driver, wherein the tap weight register is configured to receive updated tap weights and to iteratively update the tap weights with updated tap weights (W N+1), and wherein the integrated circuit further comprises means configured to scale the updated tap weights to ensure that the total power indicated by the aggregate magnitudes of the tap weights does not exceed the peak power constraint of the transmit circuit. a transmit shift register, an output driver bank, and a tap weight register, wherein the transmitter (201, 531) is configured to transmit a plurality of data values of a digital sequence onto a signal path (202, 532) external to the integrated circuit to a receiver (209, 539), using a signal level that is a logical function of a binary state of a current data value (D 0) to be transmitted and binary state of a first other data value (D +1, D -1, D -2, D -3) of the digital sequence, the first other data value (D +1, D -1, D -2, D -3) being one of a next-to-be-transmitted and/or previously transmitted data value, the transmitter (201, 531) characterized by a peak power constraint, wherein the output driver bank comprises one or more output drivers wherein the outputs of all output drivers are connected to the signal path for generating the signal level, wherein the transmit shift register is configured to store the current data value (D 0) to be transmitted and the first other data value (D +1, D -1, D -2, D -3) of the digital sequence, wherein each element of the transmit shift register is coupled to a respective one of output drivers (205 0 -205 4) within the output driver bank 204, wherein the tap weight register is configured to store a set of tap weights (W N), and wherein each tap weight (W N) is supplied to a respective one of the output drivers to control the level of the output signal generated by the output driver, wherein the tap weight register is configured to receive updated tap weights and to iteratively update the tap weights with updated tap weights (W N+1), and wherein the integrated circuit further comprises means configured to scale the updated tap weights to ensure that the total power indicated by the aggregate magnitudes of the tap weights does not exceed the peak power constraint of the transmit circuit. the transmitter (201, 531) is configured to transmit a plurality of data values of a digital sequence onto a signal path (202, 532) external to the integrated circuit to a receiver (209, 539), using a signal level that is a logical function of a binary state of a current data value (D 0) to be transmitted and binary state of a first other data value (D +1, D -1, D -2, D -3) of the digital sequence, the first other data value (D +1, D -1, D -2, D -3) being one of a next-to-be-transmitted and/or previously transmitted data value, the transmitter (201, 531) characterized by a peak power constraint, wherein the output driver bank comprises one or more output drivers wherein the outputs of all output drivers are connected to the signal path for generating the signal level, wherein the transmit shift register is configured to store the current data value (D 0) to be transmitted and the first other data value (D +1, D -1, D -2, D -3) of the digital sequence, wherein each element of the transmit shift register is coupled to a respective one of output drivers (205 0 -205 4) within the output driver bank 204, wherein the tap weight register is configured to store a set of tap weights (W N), and wherein each tap weight (W N) is supplied to a respective one of the output drivers to control the level of the output signal generated by the output driver, wherein the tap weight register is configured to receive updated tap weights and to iteratively update the tap weights with updated tap weights (W N+1), and wherein the integrated circuit further comprises means configured to scale the updated tap weights to ensure that the total power indicated by the aggregate magnitudes of the tap weights does not exceed the peak power constraint of the transmit circuit.