A chip with an on-chip sensor hub based on single-chip integration, comprising: a co-processor, fabricated on the chip with a main processor of a mobile device; and an inter-process communication interface, configured for communications within the chip between the co-processor and the main processor, a distributed volatile memory module, comprising a first memory space (SRAM1) and a second memory space (SRAM2) which are powered separately, wherein the co-processor is configured to control a plurality of sensors (S1, S2, S3, S4) of the mobile device based on requests issued from the main processor, and to collect and manage sensor data from the plurality of sensors (S1, S2, S3, S4) to be processed by the main processor; characterized in that: the first memory space (SRAM1) is configured to be used when the co-processor performs a first kind of operation on the sensors (S1, S2, S3, S4); the second memory space (SRAM2) is configured to be used when the co-processor performs a second kind of operations, infrequent in comparison with the first kind of operations, on the sensors (S1, S2, S3, S4); and the co-processor is configured to analyse the requests issued from the main processor and, when the second kind of operations are not being performed, the co-processor is configured to switch the second memory space (SRAM2) to a low-power data retention state independently from the first memory space (SRAM1). a co-processor, fabricated on the chip with a main processor of a mobile device; and an inter-process communication interface, configured for communications within the chip between the co-processor and the main processor, a distributed volatile memory module, comprising a first memory space (SRAM1) and a second memory space (SRAM2) which are powered separately, wherein the co-processor is configured to control a plurality of sensors (S1, S2, S3, S4) of the mobile device based on requests issued from the main processor, and to collect and manage sensor data from the plurality of sensors (S1, S2, S3, S4) to be processed by the main processor; characterized in that: the first memory space (SRAM1) is configured to be used when the co-processor performs a first kind of operation on the sensors (S1, S2, S3, S4); the second memory space (SRAM2) is configured to be used when the co-processor performs a second kind of operations, infrequent in comparison with the first kind of operations, on the sensors (S1, S2, S3, S4); and the co-processor is configured to analyse the requests issued from the main processor and, when the second kind of operations are not being performed, the co-processor is configured to switch the second memory space (SRAM2) to a low-power data retention state independently from the first memory space (SRAM1). the first memory space (SRAM1) is configured to be used when the co-processor performs a first kind of operation on the sensors (S1, S2, S3, S4); the second memory space (SRAM2) is configured to be used when the co-processor performs a second kind of operations, infrequent in comparison with the first kind of operations, on the sensors (S1, S2, S3, S4); and the co-processor is configured to analyse the requests issued from the main processor and, when the second kind of operations are not being performed, the co-processor is configured to switch the second memory space (SRAM2) to a low-power data retention state independently from the first memory space (SRAM1).