A decision feedback circuit comprising a plurality of decision feedback equalizer branches, each DFE branch including: a pre-computation stage configured to generate a set of tap-adjusted inputs (Q[n]), each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; wherein the pre-computation stage comprises, for each of the set of tap-adjusted inputs: a pre-computation circuit configured to adjust an input to the DFE branch by a pre-computed tap value associated with the corresponding previous output value; and a quantizer configured to quantize an output from the pre-computation circuit into one of a set of possible output values to provide a tap-adjusted input in the set of tap-adjusted inputs (Q[n]); and a decision feedback stage comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches and to provide the selected at least one output at input of an unrolling selection multiplexer circuit of the same DFE branch, wherein the unrolling selection multiplexer circuit is configured to select an output value for the same DFE branch from the selected at least one output based only on a previous output value for the same DFE branch; the decision feedback stage of each first DFE branch (Y[n]) of the plurality of DFE branches being characterized in that the multiplexer circuit comprises: a first multiplexer circuit connected at input to at least one output of a quantizer of the first DFE branch; at least one selection input for the first multiplexer circuit connected to at least one output of a quantizer of a second DFE branch (Y[n-1]) of the plurality of DFE branches, where the at least one output of a quantizer of a second DFE branch (Y[n-1]) is at the same time at least one input to a first multiplexer circuit of the second DFE branch (Y[n-1]); a second multiplexer circuit connected to at least one output of the first multiplexer circuit of the first DFE branch at input; and at least one selection input for the second multiplexer circuit connected to an intermediate output of a first multiplexer circuit of a third DFE branch (Y[n-2]) of the plurality of DFE branches, where the intermediate output is an input to a second multiplexer circuit of the third DFE branch (Y[n-2]); wherein the plurality of DFE branches are single-tap (1-Tap) decision feedback equalizers; wherein the first DFE branch (Y[n]) is 1-Tap later than the second DFE branch (Y[n-1], and the second DFE branch (Y[n-1] is 1-Tap later than the third DFE branch (Y[n-2]). a pre-computation stage configured to generate a set of tap-adjusted inputs (Q[n]), each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; wherein the pre-computation stage comprises, for each of the set of tap-adjusted inputs: a pre-computation circuit configured to adjust an input to the DFE branch by a pre-computed tap value associated with the corresponding previous output value; and a quantizer configured to quantize an output from the pre-computation circuit into one of a set of possible output values to provide a tap-adjusted input in the set of tap-adjusted inputs (Q[n]); and a pre-computation circuit configured to adjust an input to the DFE branch by a pre-computed tap value associated with the corresponding previous output value; and a quantizer configured to quantize an output from the pre-computation circuit into one of a set of possible output values to provide a tap-adjusted input in the set of tap-adjusted inputs (Q[n]); a decision feedback stage comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches and to provide the selected at least one output at input of an unrolling selection multiplexer circuit of the same DFE branch, wherein the unrolling selection multiplexer circuit is configured to select an output value for the same DFE branch from the selected at least one output based only on a previous output value for the same DFE branch; the decision feedback stage of each first DFE branch (Y[n]) of the plurality of DFE branches being characterized in that the multiplexer circuit comprises: a first multiplexer circuit connected at input to at least one output of a quantizer of the first DFE branch; at least one selection input for the first multiplexer circuit connected to at least one output of a quantizer of a second DFE branch (Y[n-1]) of the plurality of DFE branches, where the at least one output of a quantizer of a second DFE branch (Y[n-1]) is at the same time at least one input to a first multiplexer circuit of the second DFE branch (Y[n-1]); a second multiplexer circuit connected to at least one output of the first multiplexer circuit of the first DFE branch at input; and at least one selection input for the second multiplexer circuit connected to an intermediate output of a first multiplexer circuit of a third DFE branch (Y[n-2]) of the plurality of DFE branches, where the intermediate output is an input to a second multiplexer circuit of the third DFE branch (Y[n-2]); wherein the plurality of DFE branches are single-tap (1-Tap) decision feedback equalizers; wherein the first DFE branch (Y[n]) is 1-Tap later than the second DFE branch (Y[n-1], and the second DFE branch (Y[n-1] is 1-Tap later than the third DFE branch (Y[n-2]).