A data storage device comprising: a memory board comprising a plurality of NAND memory chips, the chips being single-level cell or multi-level cell memory chips; a controller board that is operably coupled to the memory board, wherein the controller board comprises a field programmable gate array controller that is arranged and configured to control memory operations for the plurality of NAND memory chips, and wherein the controller board is a physically separate board than the memory board; a peripheral component interconnect express interface (108,408) that is operably coupled to the controller board and that is arranged and configured to provide an interface between a host and the field programmable gate array controller to enable the field programmable gate array controller to communicate directly with the host over the peripheral component interconnect express interface (108, 408); and a further memory board, the further memory board comprising a plurality of NAND memory chips, the further memory board being operably coupled to the controller board, wherein the controller board and the further memory board are on their own separate printed circuit boards, and wherein the controller board is arranged on the bottom and the memory board and the further memory board are arranged on the top; and wherein: the controller board and the NAND memory chips (118a, 118b) are arranged and configured to communicate using multiple channels, each channel of the multiple channels is configured to communicate with one or more NAND memory chips (118a, 118b), and the field programmable gate array controller is configured such that commands received from the host may be executed by the field programmable gate array controller using each of the multiple channels simultaneously. a memory board comprising a plurality of NAND memory chips, the chips being single-level cell or multi-level cell memory chips; a controller board that is operably coupled to the memory board, wherein the controller board comprises a field programmable gate array controller that is arranged and configured to control memory operations for the plurality of NAND memory chips, and wherein the controller board is a physically separate board than the memory board; a peripheral component interconnect express interface (108,408) that is operably coupled to the controller board and that is arranged and configured to provide an interface between a host and the field programmable gate array controller to enable the field programmable gate array controller to communicate directly with the host over the peripheral component interconnect express interface (108, 408); and a further memory board, the further memory board comprising a plurality of NAND memory chips, the further memory board being operably coupled to the controller board, wherein the controller board and the further memory board are on their own separate printed circuit boards, and wherein the controller board is arranged on the bottom and the memory board and the further memory board are arranged on the top; and wherein: the controller board and the NAND memory chips (118a, 118b) are arranged and configured to communicate using multiple channels, each channel of the multiple channels is configured to communicate with one or more NAND memory chips (118a, 118b), and the field programmable gate array controller is configured such that commands received from the host may be executed by the field programmable gate array controller using each of the multiple channels simultaneously. the controller board and the NAND memory chips (118a, 118b) are arranged and configured to communicate using multiple channels, each channel of the multiple channels is configured to communicate with one or more NAND memory chips (118a, 118b), and the field programmable gate array controller is configured such that commands received from the host may be executed by the field programmable gate array controller using each of the multiple channels simultaneously.