An integrated circuit comprising: - first logic to issue a partial write command to a volatile memory device; and - second logic capable of issuing either a normal write frame without data mask bits or a partial write frame with data mask bits to generate a partial write frame responsive to the partial write command, if the transaction is a partial write frame, then the second logic uses the data mask bits provided by the partial write frame to mask selected data bits within the partial write frame, wherein: - the partial write frame includes m unit intervals to transfer partial write data for the partial write frame and n unit intervals to transfer data mask bits for the partial write frame, - at least some of the data mask bits for the partial write frame are repeated in more than one of the n unit intervals to allow the partial write frame to be qualified without a corresponding checksum, and - each of the n unit intervals includes a copy of the data mask bits, each of the m unit intervals includes a byte of partial write data; - each of the n unit intervals includes a data mask bit corresponding to each of the m bytes of partial write data; and the number m unit intervals to transfer partial write data for the partial write frame and the number n unit intervals to transfer data mask bits for the partial write frame are equal, - the integrated circuit does not include a data mask pin and is characterised in that - the first logic is capable of enabling a memory device to check for valid mask bits before completing the partial write, based, at least in part, on whether two of the n bytes of data mask bits match. - first logic to issue a partial write command to a volatile memory device; and - second logic capable of issuing either a normal write frame without data mask bits or a partial write frame with data mask bits to generate a partial write frame responsive to the partial write command, if the transaction is a partial write frame, then the second logic uses the data mask bits provided by the partial write frame to mask selected data bits within the partial write frame, wherein: - the partial write frame includes m unit intervals to transfer partial write data for the partial write frame and n unit intervals to transfer data mask bits for the partial write frame, - at least some of the data mask bits for the partial write frame are repeated in more than one of the n unit intervals to allow the partial write frame to be qualified without a corresponding checksum, and - each of the n unit intervals includes a copy of the data mask bits, each of the m unit intervals includes a byte of partial write data; - each of the n unit intervals includes a data mask bit corresponding to each of the m bytes of partial write data; and the number m unit intervals to transfer partial write data for the partial write frame and the number n unit intervals to transfer data mask bits for the partial write frame are equal, - the integrated circuit does not include a data mask pin and is characterised in that - the first logic is capable of enabling a memory device to check for valid mask bits before completing the partial write, based, at least in part, on whether two of the n bytes of data mask bits match.