An apparatus, comprising: an integrated circuit having a clock network in an array of circuit blocks; wherein the clock network includes routing tracks (402, 403), segmented distribution spines (501, 502), clock leaves, and bidirectional couplers; wherein the routing tracks and the distribution spines are bidirectional; wherein the distribution spines include horizontal and vertical distribution spines (501, 502); wherein the routing tracks include horizontal routing tracks and vertical routing tracks (403, 402), the horizontal and vertical routing tracks being dedicated clock resources that provide a route from a clock source to any of one or more horizontal and vertical distribution spine intersections; wherein the clock leaves intersect horizontal segments of horizontal distribution spines; wherein each bidirectional coupler includes a first tri-state buffer and a second tri-state buffer coupled in a loop, one of the vertical routing tracks being coupled to an input of the first tri-state buffer and to an output of the second tri-state buffer, and one of the horizontal routing tracks being coupled to an output of the first tri-state buffer and an input of the second tri-state buffer wherein control signals for each of the tri-state buffers are programmed using configuration memory cells to put the tri-state buffers in either a buffer state or a high impedance tri-state; wherein a clock signal on the one of the vertical routing tracks is passed through the first tri-state buffer to the one of the horizontal routing tracks when the first tri-state buffer is in a buffer state and the second tri-state buffer is in a tri-state state; and wherein a clock signal on the one horizontal routing track is passed through the second tri-state buffer to the vertical routing track when the first tri-state buffer is in a tri-state state and the second tri-state buffer is in a buffer state wherein a set of the leaves is coupled to a horizontal distribution spine of the distribution spines within a circuit block of the circuit blocks for providing a clock signal from the horizontal distribution spine to the set of the leaves; and an interconnect tile is configured for local gating for providing the clock signal to the set of the leaves without going through the horizontal distribution spine. an integrated circuit having a clock network in an array of circuit blocks; wherein the clock network includes routing tracks (402, 403), segmented distribution spines (501, 502), clock leaves, and bidirectional couplers; wherein the routing tracks and the distribution spines are bidirectional; wherein the distribution spines include horizontal and vertical distribution spines (501, 502); wherein the routing tracks include horizontal routing tracks and vertical routing tracks (403, 402), the horizontal and vertical routing tracks being dedicated clock resources that provide a route from a clock source to any of one or more horizontal and vertical distribution spine intersections; wherein the clock leaves intersect horizontal segments of horizontal distribution spines; wherein each bidirectional coupler includes a first tri-state buffer and a second tri-state buffer coupled in a loop, one of the vertical routing tracks being coupled to an input of the first tri-state buffer and to an output of the second tri-state buffer, and one of the horizontal routing tracks being coupled to an output of the first tri-state buffer and an input of the second tri-state buffer wherein control signals for each of the tri-state buffers are programmed using configuration memory cells to put the tri-state buffers in either a buffer state or a high impedance tri-state; wherein a clock signal on the one of the vertical routing tracks is passed through the first tri-state buffer to the one of the horizontal routing tracks when the first tri-state buffer is in a buffer state and the second tri-state buffer is in a tri-state state; and wherein a clock signal on the one horizontal routing track is passed through the second tri-state buffer to the vertical routing track when the first tri-state buffer is in a tri-state state and the second tri-state buffer is in a buffer state wherein a set of the leaves is coupled to a horizontal distribution spine of the distribution spines within a circuit block of the circuit blocks for providing a clock signal from the horizontal distribution spine to the set of the leaves; and an interconnect tile is configured for local gating for providing the clock signal to the set of the leaves without going through the horizontal distribution spine.