A processing system comprising: a data memory having a first memory region allocated to first data associated with a first privilege state, and a second memory region allocated to second data associated with a second privilege state, wherein the first memory region includes a first stack region within which a first stack is maintained, and the second memory region includes a second stack region within which a second stack is maintained; a code memory wherein at least one instruction address range indicator defines one or more first code memory regions within the code memory allocated for storing computer instructions associated with the first privilege state and that defines one or more second code memory regions within the code memory allocated for storing computer instructions associated with the second privilege state; a stack pointer register configured to store an address that corresponds to a top element of the first stack when a current privilege state is the first privilege state, or to store an address that corresponds to a top element of the second stack when the current privilege state is the second privilege state; an alternate stack pointer register configured to store the address that corresponds to the top element of the first stack when the current privilege state is the second privilege state, or to store the address that corresponds to the top element of the second stack when the current privilege state is the first privilege state; a first module configured to maintain knowledge of whether a current privilege state is the first privilege state or the second privilege state based on an address of an instruction fetched from the code memory; and a second module configured to determine whether a next instruction fetch address corresponds to a location within a code memory region (216, 218) associated with the current privilege state or within a code memory region (216, 218) associated with a different privilege state by comparing the next instruction fetch address with the at least one instruction address range indicator, and when the next instruction fetch address is not within the first memory region associated with the current privilege state, to allow the next computer instruction to be fetched only when a transition from the current privilege state to the different privilege state is legal, and when a transition from the current privilege state to the different privilege state is performed, to swap the addresses in the stack pointer register and the alternate stack pointer register. a data memory having a first memory region allocated to first data associated with a first privilege state, and a second memory region allocated to second data associated with a second privilege state, wherein the first memory region includes a first stack region within which a first stack is maintained, and the second memory region includes a second stack region within which a second stack is maintained; a code memory wherein at least one instruction address range indicator defines one or more first code memory regions within the code memory allocated for storing computer instructions associated with the first privilege state and that defines one or more second code memory regions within the code memory allocated for storing computer instructions associated with the second privilege state; a stack pointer register configured to store an address that corresponds to a top element of the first stack when a current privilege state is the first privilege state, or to store an address that corresponds to a top element of the second stack when the current privilege state is the second privilege state; an alternate stack pointer register configured to store the address that corresponds to the top element of the first stack when the current privilege state is the second privilege state, or to store the address that corresponds to the top element of the second stack when the current privilege state is the first privilege state; a first module configured to maintain knowledge of whether a current privilege state is the first privilege state or the second privilege state based on an address of an instruction fetched from the code memory; and a second module configured to determine whether a next instruction fetch address corresponds to a location within a code memory region (216, 218) associated with the current privilege state or within a code memory region (216, 218) associated with a different privilege state by comparing the next instruction fetch address with the at least one instruction address range indicator, and when the next instruction fetch address is not within the first memory region associated with the current privilege state, to allow the next computer instruction to be fetched only when a transition from the current privilege state to the different privilege state is legal, and when a transition from the current privilege state to the different privilege state is performed, to swap the addresses in the stack pointer register and the alternate stack pointer register.