Oscillation reduction unit (15; 150; 1500) for a bus system, having two transistors (151, 152) which are arranged in antiseries between a first bus wire of a bus of the bus system and a second bus wire of the bus, which bus system at least intermittently ensures exclusive collision-free access by a subscriber station (10, 20, 30) to the bus of the bus system, wherein the transistors (151, 152) are PMOS high-voltage cascodes, a resistor, a first high-voltage cascode transistor, connected to a first switch, which is switchable to an inrush-current current source, a second high-voltage cascode transistor, connected to a second switch, which is switchable to a second inrush-current current source, a timing control block for switching the two transistors (151, 152), wherein the timing control block is configured to switch on the two transistors (151, 152) while a signal (CAN_H, CAN_L) on the first and/or second bus wire (41, 42) and/or a transmission signal (TxD), from which the signals on the first and/or second bus wire (41, 42) are generated, is changing from a dominant state to a recessive state, and wherein the timing control block is configured to switch off the two transistors (151, 152) when the signal (CAN_H, CAN_L) on the first and/or second bus wire (41, 42) and/or the transmission signal (TxD) have/has been switched to the recessive state, wherein the time constant consisting of the resistor and of an HV PMOS gate capacitance of the transistors (151, 152) ensures a continuous decay of the short circuit that is created by switching the first and second switches (1581, 1591) during the process of switching from the dominant bus state to the recessive bus state. two transistors (151, 152) which are arranged in antiseries between a first bus wire of a bus of the bus system and a second bus wire of the bus, which bus system at least intermittently ensures exclusive collision-free access by a subscriber station (10, 20, 30) to the bus of the bus system, wherein the transistors (151, 152) are PMOS high-voltage cascodes, a resistor, a first high-voltage cascode transistor, connected to a first switch, which is switchable to an inrush-current current source, a second high-voltage cascode transistor, connected to a second switch, which is switchable to a second inrush-current current source, a timing control block for switching the two transistors (151, 152), wherein the timing control block is configured to switch on the two transistors (151, 152) while a signal (CAN_H, CAN_L) on the first and/or second bus wire (41, 42) and/or a transmission signal (TxD), from which the signals on the first and/or second bus wire (41, 42) are generated, is changing from a dominant state to a recessive state, and wherein the timing control block is configured to switch off the two transistors (151, 152) when the signal (CAN_H, CAN_L) on the first and/or second bus wire (41, 42) and/or the transmission signal (TxD) have/has been switched to the recessive state, wherein the time constant consisting of the resistor and of an HV PMOS gate capacitance of the transistors (151, 152) ensures a continuous decay of the short circuit that is created by switching the first and second switches (1581, 1591) during the process of switching from the dominant bus state to the recessive bus state.