An apparatus, comprising: a set of memory cells (704-714, 724-734, 744-754, 764-774, 2500, 2600) connected to a word line (WL0-WL10), each memory cell is in a respective NAND string (700n, 710n, 720n, 730n), the respective NAND strings are connected to a set of bit lines (BL0-BL4), a first subset (2501, 2601) of the set of memory cells is configured to be programmed to lower data states (A-C, S1-S7) of a set of data states (A-G, S1-S15) and a second subset (2502, 2602) of the set of memory cells is configured to be programmed to higher data states (D-G, S8-S15) of the set of data states; and a control circuit (110, 122), the apparatus being characterised in that the control circuit is configured to: perform a first program pass of a program operation in which the second subset of the set of memory cells is programmed while the first subset of the set of memory cells is inhibited from programming and remains in an erase data state, wherein to perform the first program pass, the control circuit is configured to apply one or more program pulses (2201-2204, 2211-2214) to the word line without performing a verify test for the second subset of the set of memory cells, wherein during a single program pulse of the one or more program pulses, the control circuit is configured to apply different program-enable voltages to respective bit lines of the second subset of the set of memory cells according to different assigned data states of the higher data states and to apply a program-inhibit voltage (2348, Vbl_inh) to respective bit lines of the first subset of the set of memory cells; and perform a second program pass of the program operation in which the first subset of the set of memory cells and the second subset of the set of memory cells are programmed, wherein to perform the second program pass, the control circuit is configured to apply a set of program pulses to the word line and perform verify tests for the first subset of the set of memory cells and the second subset of the set of memory cells. a set of memory cells (704-714, 724-734, 744-754, 764-774, 2500, 2600) connected to a word line (WL0-WL10), each memory cell is in a respective NAND string (700n, 710n, 720n, 730n), the respective NAND strings are connected to a set of bit lines (BL0-BL4), a first subset (2501, 2601) of the set of memory cells is configured to be programmed to lower data states (A-C, S1-S7) of a set of data states (A-G, S1-S15) and a second subset (2502, 2602) of the set of memory cells is configured to be programmed to higher data states (D-G, S8-S15) of the set of data states; and a control circuit (110, 122), the apparatus being characterised in that the control circuit is configured to: perform a first program pass of a program operation in which the second subset of the set of memory cells is programmed while the first subset of the set of memory cells is inhibited from programming and remains in an erase data state, wherein to perform the first program pass, the control circuit is configured to apply one or more program pulses (2201-2204, 2211-2214) to the word line without performing a verify test for the second subset of the set of memory cells, wherein during a single program pulse of the one or more program pulses, the control circuit is configured to apply different program-enable voltages to respective bit lines of the second subset of the set of memory cells according to different assigned data states of the higher data states and to apply a program-inhibit voltage (2348, Vbl_inh) to respective bit lines of the first subset of the set of memory cells; and perform a second program pass of the program operation in which the first subset of the set of memory cells and the second subset of the set of memory cells are programmed, wherein to perform the second program pass, the control circuit is configured to apply a set of program pulses to the word line and perform verify tests for the first subset of the set of memory cells and the second subset of the set of memory cells. perform a first program pass of a program operation in which the second subset of the set of memory cells is programmed while the first subset of the set of memory cells is inhibited from programming and remains in an erase data state, wherein to perform the first program pass, the control circuit is configured to apply one or more program pulses (2201-2204, 2211-2214) to the word line without performing a verify test for the second subset of the set of memory cells, wherein during a single program pulse of the one or more program pulses, the control circuit is configured to apply different program-enable voltages to respective bit lines of the second subset of the set of memory cells according to different assigned data states of the higher data states and to apply a program-inhibit voltage (2348, Vbl_inh) to respective bit lines of the first subset of the set of memory cells; and perform a second program pass of the program operation in which the first subset of the set of memory cells and the second subset of the set of memory cells are programmed, wherein to perform the second program pass, the control circuit is configured to apply a set of program pulses to the word line and perform verify tests for the first subset of the set of memory cells and the second subset of the set of memory cells.