A circuit comprising: a system on chip, SoC, including a physical layer comprising a bidirectional lane front-end circuit, which includes a differential bidirectional terminal (TX_RXP, TX_RXN) selectively configurable for receiving signals in a first mode according to a first protocol and transmitting signals in a second mode according to a second protocol, wherein the first protocol is different from the second protocol; and a transmitting circuit comprising a shared impedance matching circuit, a first transistor, a second transistor, a first resistor and a second resistor; wherein the shared impedance matching circuit comprises a third transistor and a fourth transistor, a third resistor and a fourth resistor; the transmitting circuit being configured to both: 1) couple the differential bidirectional terminal to ground through the third and fourth resistors (R3, R4) for impedance matching when receiving in the first mode and 2) bias the voltage output when transmitting signals in the second mode through the differential bidirectional terminal, wherein a drain of the first transistor is coupled via the first resistor to a first line of the differential bidirectional terminal, wherein the third transistor is coupled to the first line of the differential bidirectional terminal via the third resistor, and wherein a gate of the first transistor and a gate of the third transistor are coupled to a first common terminal (TXP_term), wherein a drain of the second transistor is coupled via a second resistor to a second line of the differential bidirectional terminal, wherein the fourth transistor is coupled to the second line of the differential bidirectional terminal via the fourth resistor, and wherein a gate of the second transistor and a gate of the fourth transistor are coupled to a second common terminal (TXN_term), and wherein the first and second transistors are p-channel metal oxide semiconductor, PMOS, transistors, and wherein the third and fourth transistors are n-channel metal oxide semiconductor, NMOS, transistors, wherein the first and second transistors act as switches allowing the biasing of the voltage output using the first and second resistors and the third and fourth transistors provide a DC current path to ground when transmitting signals in the second mode, and allowing for impedance matching via the third and fourth resistors between the first and second line and an external connector connected to the differential bidirectional terminal when receiving in the first mode. a differential bidirectional terminal (TX_RXP, TX_RXN) selectively configurable for receiving signals in a first mode according to a first protocol and transmitting signals in a second mode according to a second protocol, wherein the first protocol is different from the second protocol; and a transmitting circuit comprising a shared impedance matching circuit, a first transistor, a second transistor, a first resistor and a second resistor; wherein the shared impedance matching circuit comprises a third transistor and a fourth transistor, a third resistor and a fourth resistor; the transmitting circuit being configured to both: 1) couple the differential bidirectional terminal to ground through the third and fourth resistors (R3, R4) for impedance matching when receiving in the first mode and 2) bias the voltage output when transmitting signals in the second mode through the differential bidirectional terminal, wherein a drain of the first transistor is coupled via the first resistor to a first line of the differential bidirectional terminal, wherein the third transistor is coupled to the first line of the differential bidirectional terminal via the third resistor, and wherein a gate of the first transistor and a gate of the third transistor are coupled to a first common terminal (TXP_term), wherein a drain of the second transistor is coupled via a second resistor to a second line of the differential bidirectional terminal, wherein the fourth transistor is coupled to the second line of the differential bidirectional terminal via the fourth resistor, and wherein a gate of the second transistor and a gate of the fourth transistor are coupled to a second common terminal (TXN_term), and wherein the first and second transistors are p-channel metal oxide semiconductor, PMOS, transistors, and wherein the third and fourth transistors are n-channel metal oxide semiconductor, NMOS, transistors, wherein the first and second transistors act as switches allowing the biasing of the voltage output using the first and second resistors and the third and fourth transistors provide a DC current path to ground when transmitting signals in the second mode, and allowing for impedance matching via the third and fourth resistors between the first and second line and an external connector connected to the differential bidirectional terminal when receiving in the first mode.