A first in first out memory device comprising: a plurality of data registers (202, 204, 206, 208) arranged in a pipeline, the plurality of data registers including a first data register to accept writing of data from a write device and a last data register to allow reading of data by a read device, a bubble inserter circuit to cause a bubble of replacement dummy values instead of actual data to be stored in the first data register to prevent a completely empty condition for all data registers; a near empty detect circuit adapted to determine a nearly empty condition of the plurality of data registers; and wherein the bubble inserter circuit includes an arbiter, the arbiter determining whether a data write proceeds or a bubble insertion proceeds for the first data register when the plurality of data registers is near empty as determined by the near empty detect circuit, the memory device further comprising a plurality of bubble bit registers (222, 224, 226, 228), each bubble bit register indicating whether dummy values are stored in the corresponding data register (202, 204, 206, 208), such that the read device ignores the contents of the last data register in response to a read request if the corresponding bubble bit register indicates that the last data register contains a bubble, characterized in that the first in first out memory device is asynchronous and in that each data register has an enable input to indicate a full condition allowing a read of the data register and an empty condition allowing a write to the data register, the near empty detect circuit being coupled to the enable inputs of the plurality of data registers, the plurality of data registers allowing data to be passed in sequence from the first data register to the last data register. a plurality of data registers (202, 204, 206, 208) arranged in a pipeline, the plurality of data registers including a first data register to accept writing of data from a write device and a last data register to allow reading of data by a read device, a bubble inserter circuit to cause a bubble of replacement dummy values instead of actual data to be stored in the first data register to prevent a completely empty condition for all data registers; a near empty detect circuit adapted to determine a nearly empty condition of the plurality of data registers; and wherein the bubble inserter circuit includes an arbiter, the arbiter determining whether a data write proceeds or a bubble insertion proceeds for the first data register when the plurality of data registers is near empty as determined by the near empty detect circuit, the memory device further comprising a plurality of bubble bit registers (222, 224, 226, 228), each bubble bit register indicating whether dummy values are stored in the corresponding data register (202, 204, 206, 208), such that the read device ignores the contents of the last data register in response to a read request if the corresponding bubble bit register indicates that the last data register contains a bubble, characterized in that the first in first out memory device is asynchronous and in that each data register has an enable input to indicate a full condition allowing a read of the data register and an empty condition allowing a write to the data register, the near empty detect circuit being coupled to the enable inputs of the plurality of data registers, the plurality of data registers allowing data to be passed in sequence from the first data register to the last data register.