Method of execution of a binary code of a secure function by a microprocessor, characterized in that this method comprises: a) the recording in a main memory at an address @ j of a code line, each code line corresponding to a machine word which can be transferred in a single clock cycle from the main memory into a register of the microprocessor, this code line containing: - a datum D j to be processed by the microprocessor or a cryptogram of this datum D j, and - a first error-detecting code (ECC Dj, MAC j, ECC Lj) making it possible to detect an error in the datum D j or in its cryptogram if this datum D j or its cryptogram is modified after its recording in the main memory, at least one of the datum D j, of its cryptogram and of the first error-detecting code being encrypted as a function of an initialization vector iv j, this initialization vector iv j varying as a function of the address @ j at which the code line is recorded according to a relation iv j = F iv (@ j), where the function F iv is a preprogrammed function of a securing hardware module of the microprocessor which associates a different initialization vector iv j with each different address @ j of the main memory, b) during the execution of the binary code by the microprocessor, the method comprises the following operations: 1) the execution of a loading instruction by the microprocessor which causes the loading into the registers of the microprocessor of the code line recorded at the address @ j, and then 2) the securing hardware module calculates the initialization vector iv j with the aid of the relation iv j = F iv (@ j), where @ j is the address on the basis of which the code line has been loaded, and then 3) the securing hardware module decrypts the code line loaded with the aid of the initialization vector iv j calculated to obtain: - the datum D j or its cryptogram, and - the first error-detecting code, and then 4) the securing hardware module verifies, with the aid of the first error-detecting code obtained, whether there exists an error in the datum D j or its cryptogram and, if such an error exists, triggers the signalling of an execution fault and, if such an error does not exist, inhibits this signalling of an execution fault. a) the recording in a main memory at an address @ j of a code line, each code line corresponding to a machine word which can be transferred in a single clock cycle from the main memory into a register of the microprocessor, this code line containing: - a datum D j to be processed by the microprocessor or a cryptogram of this datum D j, and - a first error-detecting code (ECC Dj, MAC j, ECC Lj) making it possible to detect an error in the datum D j or in its cryptogram if this datum D j or its cryptogram is modified after its recording in the main memory, at least one of the datum D j, of its cryptogram and of the first error-detecting code being encrypted as a function of an initialization vector iv j, this initialization vector iv j varying as a function of the address @ j at which the code line is recorded according to a relation iv j = F iv (@ j), where the function F iv is a preprogrammed function of a securing hardware module of the microprocessor which associates a different initialization vector iv j with each different address @ j of the main memory, - a datum D j to be processed by the microprocessor or a cryptogram of this datum D j, and - a first error-detecting code (ECC Dj, MAC j, ECC Lj) making it possible to detect an error in the datum D j or in its cryptogram if this datum D j or its cryptogram is modified after its recording in the main memory, b) during the execution of the binary code by the microprocessor, the method comprises the following operations: 1) the execution of a loading instruction by the microprocessor which causes the loading into the registers of the microprocessor of the code line recorded at the address @ j, and then 2) the securing hardware module calculates the initialization vector iv j with the aid of the relation iv j = F iv (@ j), where @ j is the address on the basis of which the code line has been loaded, and then 3) the securing hardware module decrypts the code line loaded with the aid of the initialization vector iv j calculated to obtain: - the datum D j or its cryptogram, and - the first error-detecting code, and then 4) the securing hardware module verifies, with the aid of the first error-detecting code obtained, whether there exists an error in the datum D j or its cryptogram and, if such an error exists, triggers the signalling of an execution fault and, if such an error does not exist, inhibits this signalling of an execution fault. 1) the execution of a loading instruction by the microprocessor which causes the loading into the registers of the microprocessor of the code line recorded at the address @ j, and then 2) the securing hardware module calculates the initialization vector iv j with the aid of the relation iv j = F iv (@ j), where @ j is the address on the basis of which the code line has been loaded, and then 3) the securing hardware module decrypts the code line loaded with the aid of the initialization vector iv j calculated to obtain: - the datum D j or its cryptogram, and - the first error-detecting code, and then - the datum D j or its cryptogram, and - the first error-detecting code, and then 4) the securing hardware module verifies, with the aid of the first error-detecting code obtained, whether there exists an error in the datum D j or its cryptogram and, if such an error exists, triggers the signalling of an execution fault and, if such an error does not exist, inhibits this signalling of an execution fault.