An integrated circuit, IC, comprising: a first region supplied by a first power domain; a second region supplied by a second power domain; a first level shifting circuit coupled to translate a first data from the first power domain to the second power domain; a second level shifting circuit coupled to translate a second data from the second power domain to the first power domain; a power-on-reset system, PORS, comprising: a voltage detection circuit (410, 470a, 470b) configured to detect voltages of the first power domain and the second power domain; a glitch filter circuit (415, 475a, 475b) coupled to the voltage detection circuit (410, 470a, 470b) to indicate a voltage change of the second power domain; and a control circuit coupled to the first level shifting circuit and the second level shifting circuit and configured to generate a first isolation signal to control the first level shifting circuit and a second isolation signal to control the second level shifting circuit in response to the detected voltages of the first power domain and the second power domain; wherein, when the voltage change of the second power domain exceeds a predetermined time period, the control circuit is further configured to disable the second level shifting circuit using the second isolation signal a first predetermined delay after disabling the first level shifting circuit using the first isolation signal. a first region supplied by a first power domain; a second region supplied by a second power domain; a first level shifting circuit coupled to translate a first data from the first power domain to the second power domain; a second level shifting circuit coupled to translate a second data from the second power domain to the first power domain; a power-on-reset system, PORS, comprising: a voltage detection circuit (410, 470a, 470b) configured to detect voltages of the first power domain and the second power domain; a glitch filter circuit (415, 475a, 475b) coupled to the voltage detection circuit (410, 470a, 470b) to indicate a voltage change of the second power domain; and a control circuit coupled to the first level shifting circuit and the second level shifting circuit and configured to generate a first isolation signal to control the first level shifting circuit and a second isolation signal to control the second level shifting circuit in response to the detected voltages of the first power domain and the second power domain; wherein, when the voltage change of the second power domain exceeds a predetermined time period, the control circuit is further configured to disable the second level shifting circuit using the second isolation signal a first predetermined delay after disabling the first level shifting circuit using the first isolation signal. a voltage detection circuit (410, 470a, 470b) configured to detect voltages of the first power domain and the second power domain; a glitch filter circuit (415, 475a, 475b) coupled to the voltage detection circuit (410, 470a, 470b) to indicate a voltage change of the second power domain; and a control circuit coupled to the first level shifting circuit and the second level shifting circuit and configured to generate a first isolation signal to control the first level shifting circuit and a second isolation signal to control the second level shifting circuit in response to the detected voltages of the first power domain and the second power domain; wherein, when the voltage change of the second power domain exceeds a predetermined time period, the control circuit is further configured to disable the second level shifting circuit using the second isolation signal a first predetermined delay after disabling the first level shifting circuit using the first isolation signal.