A sensor array comprising an array of pixels, each pixel comprising: a photodiode; a node arranged to develop a voltage based on charge accumulated at the photodiode due to photogeneration during an integration period; and a first overflow unit coupled to the node, the first overflow unit comprising a first transistor and a first capacitance, the sensor array being arranged to control the first overflow unit to accept overflow charge from the node into the capacitance of the first overflow unit, each pixel comprising one or more further overflow units (202, 203) arranged in series with the first overflow unit, each further overflow unit comprising a further transistor (S2, S3) and a further capacitance (C2, C3), the first overflow unit and the one or more further overflow units (202, 203) each comprising a node (n2, n3, n4) formed at a connection between the transistor and capacitance of the respective overflow unit, the one or more further overflow units (202, 203) connected to node (n2, n3) of a respective preceding overflow unit in the series, the sensor array being arranged to control each further overflow unit to accept overflow charge from the previous overflow unit in the series, and to subsequently read the charge at the photodiode, overflow charge stored at the first capacitance or overflow charge stored at the further capacitance (C2, C3) of the one or more further overflow units, the sensor array characterised by further comprising a decision block arranged to monitor the voltage at each node (n1, n2, n3, n4) and at the end of the integration period check if any of the overflow units (201, 202, 203) or the photodiode are full of charge, and if any of the overflow units or photodiode are full to readout only a next unfilled or partially filled overflow unit in the series. a photodiode; a node arranged to develop a voltage based on charge accumulated at the photodiode due to photogeneration during an integration period; and a first overflow unit coupled to the node, the first overflow unit comprising a first transistor and a first capacitance, the sensor array being arranged to control the first overflow unit to accept overflow charge from the node into the capacitance of the first overflow unit, each pixel comprising one or more further overflow units (202, 203) arranged in series with the first overflow unit, each further overflow unit comprising a further transistor (S2, S3) and a further capacitance (C2, C3), the first overflow unit and the one or more further overflow units (202, 203) each comprising a node (n2, n3, n4) formed at a connection between the transistor and capacitance of the respective overflow unit, the one or more further overflow units (202, 203) connected to node (n2, n3) of a respective preceding overflow unit in the series, the sensor array being arranged to control each further overflow unit to accept overflow charge from the previous overflow unit in the series, and to subsequently read the charge at the photodiode, overflow charge stored at the first capacitance or overflow charge stored at the further capacitance (C2, C3) of the one or more further overflow units, the sensor array characterised by further comprising a decision block arranged to monitor the voltage at each node (n1, n2, n3, n4) and at the end of the integration period check if any of the overflow units (201, 202, 203) or the photodiode are full of charge, and if any of the overflow units or photodiode are full to readout only a next unfilled or partially filled overflow unit in the series.