A system comprising: a plurality of master devices (4, 6) having associated caches (11, 12); and coherency control circuitry to manage coherency between the caches, based on a coherency protocol which assigns one of a plurality of coherency states to each item of data in a given cache; wherein: the coherency control circuitry is configured to support processing of a safe-speculative-read transaction received from a requesting master device, the safe-speculative-read transaction of a type requesting that target data is returned to the requesting master device while prohibiting any change in coherency state associated with the target data in caches of other master devices in response to the safe-speculative-read transaction; and in response to the safe-speculative-read transaction, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry and the second master device is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache; and in response to the safe-speculative-read transaction, when the target data is absent from the second cache and any other caches managed according to the coherency protocol, the coherency control circuitry is configured to obtain the target data from a further level cache or memory shared between the plurality of master devices (4, 6) and return the target data to the requesting master device in a cacheable read response, the cacheable read response permitting the cache associated with the requesting master device to cache the target data. a plurality of master devices (4, 6) having associated caches (11, 12); and coherency control circuitry to manage coherency between the caches, based on a coherency protocol which assigns one of a plurality of coherency states to each item of data in a given cache; wherein: the coherency control circuitry is configured to support processing of a safe-speculative-read transaction received from a requesting master device, the safe-speculative-read transaction of a type requesting that target data is returned to the requesting master device while prohibiting any change in coherency state associated with the target data in caches of other master devices in response to the safe-speculative-read transaction; and in response to the safe-speculative-read transaction, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry and the second master device is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache; and in response to the safe-speculative-read transaction, when the target data is absent from the second cache and any other caches managed according to the coherency protocol, the coherency control circuitry is configured to obtain the target data from a further level cache or memory shared between the plurality of master devices (4, 6) and return the target data to the requesting master device in a cacheable read response, the cacheable read response permitting the cache associated with the requesting master device to cache the target data. the coherency control circuitry is configured to support processing of a safe-speculative-read transaction received from a requesting master device, the safe-speculative-read transaction of a type requesting that target data is returned to the requesting master device while prohibiting any change in coherency state associated with the target data in caches of other master devices in response to the safe-speculative-read transaction; and in response to the safe-speculative-read transaction, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry and the second master device is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache; and in response to the safe-speculative-read transaction, when the target data is absent from the second cache and any other caches managed according to the coherency protocol, the coherency control circuitry is configured to obtain the target data from a further level cache or memory shared between the plurality of master devices (4, 6) and return the target data to the requesting master device in a cacheable read response, the cacheable read response permitting the cache associated with the requesting master device to cache the target data.