A vector processing apparatus comprising: a set of vector registers, each vector register arranged to store a vector operand comprising a plurality of data elements; access circuitry to perform access operations to move data elements of vector operands between data structures in memory and said set of vector registers, each data structure comprising multiple data elements stored at contiguous addresses in said memory; and decode circuitry, responsive to a single access instruction identifying a plurality of vector registers from said set and a plurality of data structures that are located discontiguously with respect to each other in said memory, to generate control signals to control the access circuitry to perform a sequence of said access operations to move said plurality of data structures between said memory and said plurality of vector registers such that the vector operand in each vector register of said plurality holds a corresponding data element from each of said plurality of data structures; wherein: the access circuitry operates on a plurality of lanes, each lane incorporating a corresponding data element position from each of said plurality of vector registers; said single access instruction includes a predicate identifier field providing predicate information used to determine which of said plurality of lanes are active lanes for the sequence of access operations; and the access circuitry being arranged to determine, as said plurality of data structures to be moved, those data structures associated with the active lanes; and wherein the single access instruction is a load instruction, characterized in that: the access circuitry is arranged to perform a compaction operation using said predicate information, the predicate information being used to identify the plurality of data structures to be loaded, and the access circuitry being arranged to store those data structures within a series of consecutive lanes within the plurality of vector registers. a set of vector registers, each vector register arranged to store a vector operand comprising a plurality of data elements; access circuitry to perform access operations to move data elements of vector operands between data structures in memory and said set of vector registers, each data structure comprising multiple data elements stored at contiguous addresses in said memory; and decode circuitry, responsive to a single access instruction identifying a plurality of vector registers from said set and a plurality of data structures that are located discontiguously with respect to each other in said memory, to generate control signals to control the access circuitry to perform a sequence of said access operations to move said plurality of data structures between said memory and said plurality of vector registers such that the vector operand in each vector register of said plurality holds a corresponding data element from each of said plurality of data structures; wherein: the access circuitry operates on a plurality of lanes, each lane incorporating a corresponding data element position from each of said plurality of vector registers; said single access instruction includes a predicate identifier field providing predicate information used to determine which of said plurality of lanes are active lanes for the sequence of access operations; and the access circuitry being arranged to determine, as said plurality of data structures to be moved, those data structures associated with the active lanes; and wherein the single access instruction is a load instruction, characterized in that: the access circuitry is arranged to perform a compaction operation using said predicate information, the predicate information being used to identify the plurality of data structures to be loaded, and the access circuitry being arranged to store those data structures within a series of consecutive lanes within the plurality of vector registers. the access circuitry operates on a plurality of lanes, each lane incorporating a corresponding data element position from each of said plurality of vector registers; said single access instruction includes a predicate identifier field providing predicate information used to determine which of said plurality of lanes are active lanes for the sequence of access operations; and the access circuitry being arranged to determine, as said plurality of data structures to be moved, those data structures associated with the active lanes; and wherein the single access instruction is a load instruction, characterized in that: the access circuitry is arranged to perform a compaction operation using said predicate information, the predicate information being used to identify the plurality of data structures to be loaded, and the access circuitry being arranged to store those data structures within a series of consecutive lanes within the plurality of vector registers.