A dynamic random access memory, DRAM refresh method, wherein a DRAM storage array comprises at least two banks, and is formed by logically and horizontally arranging the at least two banks, each of the at least two banks has a row address decoder, each of the at least two banks comprises rows, each row of the DRAM storage array comprises bank rows corresponding to the at least two banks, wherein a bank row is a row of a bank, the DRAM storage array is divided into at least two refresh blocks, each block comprises at least two rows of the DRAM storage array, and the method comprises: receiving, by a DRAM refresh apparatus, a refresh instruction from a memory controller, wherein the refresh instruction comprises an identifier of a to-be-refreshed block and refresh information used to indicate a to-be-refreshed area, and the refresh instruction is used to instruct the DRAM refresh apparatus to refresh the to-be-refreshed area in the to-be-refreshed block, wherein the to-be-refreshed area includes a to-be-refreshed block row in the to-be-refreshed block, and to-be-refreshed bank rows in the to-be-refreshed block row, wherein a block row is a row of a block; generating, by the DRAM refresh apparatus, addresses of the to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information; and refreshing, by the DRAM refresh apparatus, locations corresponding to the addresses of the bank rows in the to-be-refreshed block; wherein the refresh information comprises first indication information and second indication information, the first indication information is used to indicate the to-be-refreshed block row in the to-be-refreshed block, and the second indication information is used to indicate the to-be-refreshed bank rows; wherein the refreshing, by the DRAM refresh apparatus, locations corresponding to the addresses of the bank rows in the to-be-refreshed block comprises: refreshing, by the DRAM refresh apparatus in N refresh stages according to a quantity M of to-be-refreshed block rows in the to-be-refreshed block, the locations corresponding to the addresses of the bank rows, wherein locations, in a same block row, are refreshed in parallel in a same refresh stage, M is a positive integer greater than 0, and N is a positive integer greater than 0 and less than M; wherein the refresh information further comprises a row combination identifier used to instruct the DRAM refresh apparatus to refresh at least two block rows in the to-be-refreshed block in a same refresh stage; wherein banks in which the to-be-refreshed bank rows in a first block row of the at least two block rows are located do not overlap banks in which the to-be-refreshed bank rows in a second block row of the at least two block rows are located; wherein the refreshing, by the DRAM refresh apparatus, comprises: refreshing the first block row of the at least two block rows and the second block row of the at least two block rows in parallel in the same refresh stage. receiving, by a DRAM refresh apparatus, a refresh instruction from a memory controller, wherein the refresh instruction comprises an identifier of a to-be-refreshed block and refresh information used to indicate a to-be-refreshed area, and the refresh instruction is used to instruct the DRAM refresh apparatus to refresh the to-be-refreshed area in the to-be-refreshed block, wherein the to-be-refreshed area includes a to-be-refreshed block row in the to-be-refreshed block, and to-be-refreshed bank rows in the to-be-refreshed block row, wherein a block row is a row of a block; generating, by the DRAM refresh apparatus, addresses of the to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information; and refreshing, by the DRAM refresh apparatus, locations corresponding to the addresses of the bank rows in the to-be-refreshed block; wherein the refresh information comprises first indication information and second indication information, the first indication information is used to indicate the to-be-refreshed block row in the to-be-refreshed block, and the second indication information is used to indicate the to-be-refreshed bank rows; wherein the refreshing, by the DRAM refresh apparatus, locations corresponding to the addresses of the bank rows in the to-be-refreshed block comprises: refreshing, by the DRAM refresh apparatus in N refresh stages according to a quantity M of to-be-refreshed block rows in the to-be-refreshed block, the locations corresponding to the addresses of the bank rows, wherein locations, in a same block row, are refreshed in parallel in a same refresh stage, M is a positive integer greater than 0, and N is a positive integer greater than 0 and less than M; wherein the refresh information further comprises a row combination identifier used to instruct the DRAM refresh apparatus to refresh at least two block rows in the to-be-refreshed block in a same refresh stage; wherein banks in which the to-be-refreshed bank rows in a first block row of the at least two block rows are located do not overlap banks in which the to-be-refreshed bank rows in a second block row of the at least two block rows are located; wherein the refreshing, by the DRAM refresh apparatus, comprises: refreshing the first block row of the at least two block rows and the second block row of the at least two block rows in parallel in the same refresh stage.