A method for dividing the frequency of a signal using a configurable dividing ratio, comprising: receiving an input signal with a first frequency to drive clocked switches in a frequency divider (942; 1342) with a configurable dividing ratio, wherein the clocked switches comprise p-type MOSFETs (928a-d; 1328a-h) that connect inverters (932a-932d; I332a-I332h) to a direct current, DC, reference voltage and n-typc MOSFETs (930a-d; 1330a-h) that connect the inverters to ground, wherein the inverters (932a-932d; 1332a-1332h) are connected in series with each other in a feedback loop configuration; operating first non-clocked switches inside the frequency divider (942; 1342) to select two out of four dividing ratios, wherein two of the inverters (932b-c; 1332b-e, 1332g-h) are each connected to one of the clocked p-type MOSFETs (928b-c; 1328b-e, 1328g-h) in parallel with a non-clocked p-type MOSFET (946a-b; 1346a-f) driven by a first control signal and one of the clocked n-type MOSFETs (930b-c; 1330b-e, 1330g-h) in parallel with a non-clocked n-type MOSFET (948a-b; 1348a-f) driven by a inverted signal of the first control signal; operating second non-clocked switches inside the frequency divider (942; 1342) to select at another two of the four dividing ratios, wherein another four of the inverters (932b-c; 1332b-e, 1332g-h) are each connected to one of the clocked p-type MOSFETs (928b-c; 1328b-e, 1328g-h) in parallel with a non-clocked p-type MOSFET (946a-b; 1346a-f) driven by a second control signal and one of the clocked n-type MOSFETs (930b-c; 1330b-e, 1330g-h) in parallel with a non-clocked n-type MOSFET (948a-b; 1348a-f) driven by the inverted signal of the second control signal and wherein the total number of said inverters having said clocked switches is 8; and wherein the four dividing ratios are 8, 6, 4 and 2; and outputting an output signal with a second frequency that is the first frequency divided by the selected dividing ratio. receiving an input signal with a first frequency to drive clocked switches in a frequency divider (942; 1342) with a configurable dividing ratio, wherein the clocked switches comprise p-type MOSFETs (928a-d; 1328a-h) that connect inverters (932a-932d; I332a-I332h) to a direct current, DC, reference voltage and n-typc MOSFETs (930a-d; 1330a-h) that connect the inverters to ground, wherein the inverters (932a-932d; 1332a-1332h) are connected in series with each other in a feedback loop configuration; operating first non-clocked switches inside the frequency divider (942; 1342) to select two out of four dividing ratios, wherein two of the inverters (932b-c; 1332b-e, 1332g-h) are each connected to one of the clocked p-type MOSFETs (928b-c; 1328b-e, 1328g-h) in parallel with a non-clocked p-type MOSFET (946a-b; 1346a-f) driven by a first control signal and one of the clocked n-type MOSFETs (930b-c; 1330b-e, 1330g-h) in parallel with a non-clocked n-type MOSFET (948a-b; 1348a-f) driven by a inverted signal of the first control signal; operating second non-clocked switches inside the frequency divider (942; 1342) to select at another two of the four dividing ratios, wherein another four of the inverters (932b-c; 1332b-e, 1332g-h) are each connected to one of the clocked p-type MOSFETs (928b-c; 1328b-e, 1328g-h) in parallel with a non-clocked p-type MOSFET (946a-b; 1346a-f) driven by a second control signal and one of the clocked n-type MOSFETs (930b-c; 1330b-e, 1330g-h) in parallel with a non-clocked n-type MOSFET (948a-b; 1348a-f) driven by the inverted signal of the second control signal and wherein the total number of said inverters having said clocked switches is 8; and wherein the four dividing ratios are 8, 6, 4 and 2; and outputting an output signal with a second frequency that is the first frequency divided by the selected dividing ratio.