A processor-based device, comprising: a system memory comprising a multilevel page table comprising a plurality of page tables (116 -116), each page table comprising a plurality of page table entries (216, 220, 224, 228); and a processing element, PE, comprising: an execution pipeline comprising an instruction decode stage; and a page table walker circuit; the PE configured to: receive, using the instruction decode stage, a memory access instruction comprising a virtual memory address and a traverse indicator that indicates the number T of page table walk levels to traverse; determine, using the page table walker circuit based on the memory access instruction, a number T of page table walk levels to traverse based on the traverse indicator, wherein T is greater than zero and less than or equal to a number of page table walk levels required to fully translate the virtual memory address; perform, using the page table walker circuit based on the virtual memory address, a page table walk of T page table walk levels of the multilevel page table; identify, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level; and perform a memory access operation indicated by the memory access instruction using the physical memory address. a system memory comprising a multilevel page table comprising a plurality of page tables (116 -116), each page table comprising a plurality of page table entries (216, 220, 224, 228); and a processing element, PE, comprising: an execution pipeline comprising an instruction decode stage; and a page table walker circuit; an execution pipeline comprising an instruction decode stage; and a page table walker circuit; the PE configured to: receive, using the instruction decode stage, a memory access instruction comprising a virtual memory address and a traverse indicator that indicates the number T of page table walk levels to traverse; determine, using the page table walker circuit based on the memory access instruction, a number T of page table walk levels to traverse based on the traverse indicator, wherein T is greater than zero and less than or equal to a number of page table walk levels required to fully translate the virtual memory address; perform, using the page table walker circuit based on the virtual memory address, a page table walk of T page table walk levels of the multilevel page table; identify, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level; and perform a memory access operation indicated by the memory access instruction using the physical memory address. receive, using the instruction decode stage, a memory access instruction comprising a virtual memory address and a traverse indicator that indicates the number T of page table walk levels to traverse; determine, using the page table walker circuit based on the memory access instruction, a number T of page table walk levels to traverse based on the traverse indicator, wherein T is greater than zero and less than or equal to a number of page table walk levels required to fully translate the virtual memory address; perform, using the page table walker circuit based on the virtual memory address, a page table walk of T page table walk levels of the multilevel page table; identify, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level; and perform a memory access operation indicated by the memory access instruction using the physical memory address.