Circuit for balancing capacitor voltages (U C1, U C2) at capacitors (C 1, C 2) in a DC circuit, comprising - a first circuit path having at least one first capacitor (C 1) and one second capacitor (C 2) which are connected in series between a first potential (DC+) and a second potential (DC-) of a DC voltage of the DC circuit, wherein a first centre tap is arranged between the first capacitor (C 1) and the second capacitor (C 2), - a second circuit path with a first switchable semiconductor (T 1), a first balancing resistor (R S1), a second balancing resistor (R S2) and a second switchable semiconductor (T 2), which are connected in series between the potentials (DC+, DC-), wherein the first switchable semiconductor (T 1) is arranged at the first potential (DC+) and the second switchable semiconductor (T 2) is arranged at the second potential (DC-), wherein the first balancing resistor (R S1) and the second balancing resistor (R S2) are arranged between the first switchable semiconductor (T 1) and the second switchable semiconductor (T 2), and wherein a second centre tap is arranged between the first balancing resistor (R S1) and the second balancing resistor (R S2), and - a first electrical connection of the first centre tap in the first circuit path to the second centre tap in the second circuit path, characterised in that - in a third circuit path, a first voltage divider resistor (R 1), a voltage stabilisation element and a second voltage divider resistor (R 2) are connected in series between the potentials (DC+, DC-), - the first voltage divider resistor (R 1) is at the first potential (DC+), the second voltage divider resistor (R 2) is at the second potential (DC-) and the voltage stabilisation element is arranged between the voltage divider resistors (R 1, R 2), - a first terminal is arranged between the first voltage divider resistor (R 1) and the voltage stabilisation element and a second terminal is arranged between the second voltage divider resistor (R 2) and the voltage stabilisation element, - a second electrical connection is arranged between the first gate terminal (G 1) of the first switchable semiconductor (T 1) and the first terminal, and a third electrical connection is arranged between the further gate terminal (G 2) of the second switchable semiconductor (T 2) and the second terminal, - a switch element is arranged in a fourth electrical connection between the first terminal and the second terminal, parallel to the voltage stabilisation element and - the voltage stabilisation element in the third circuit path is a Zener diode. - a first circuit path having at least one first capacitor (C 1) and one second capacitor (C 2) which are connected in series between a first potential (DC+) and a second potential (DC-) of a DC voltage of the DC circuit, wherein a first centre tap is arranged between the first capacitor (C 1) and the second capacitor (C 2), - a second circuit path with a first switchable semiconductor (T 1), a first balancing resistor (R S1), a second balancing resistor (R S2) and a second switchable semiconductor (T 2), which are connected in series between the potentials (DC+, DC-), wherein the first switchable semiconductor (T 1) is arranged at the first potential (DC+) and the second switchable semiconductor (T 2) is arranged at the second potential (DC-), wherein the first balancing resistor (R S1) and the second balancing resistor (R S2) are arranged between the first switchable semiconductor (T 1) and the second switchable semiconductor (T 2), and wherein a second centre tap is arranged between the first balancing resistor (R S1) and the second balancing resistor (R S2), and - a first electrical connection of the first centre tap in the first circuit path to the second centre tap in the second circuit path, - in a third circuit path, a first voltage divider resistor (R 1), a voltage stabilisation element and a second voltage divider resistor (R 2) are connected in series between the potentials (DC+, DC-), - the first voltage divider resistor (R 1) is at the first potential (DC+), the second voltage divider resistor (R 2) is at the second potential (DC-) and the voltage stabilisation element is arranged between the voltage divider resistors (R 1, R 2), - a first terminal is arranged between the first voltage divider resistor (R 1) and the voltage stabilisation element and a second terminal is arranged between the second voltage divider resistor (R 2) and the voltage stabilisation element, - a second electrical connection is arranged between the first gate terminal (G 1) of the first switchable semiconductor (T 1) and the first terminal, and a third electrical connection is arranged between the further gate terminal (G 2) of the second switchable semiconductor (T 2) and the second terminal, - a switch element is arranged in a fourth electrical connection between the first terminal and the second terminal, parallel to the voltage stabilisation element and - the voltage stabilisation element in the third circuit path is a Zener diode.