An apparatus for controlling divergent branch instructions in a single instruction, multiple data, SIMD, processing system configured to execute a plurality of threads using a least-value address first program counter approach, the apparatus comprising: means for controlling entry and exit of a subroutine from a program by comparing a target program counter value with a first minimum resume counter, MINRC, and selecting either the target program counter value or the first MINRC value to load into the program counter based on the comparison, the first MINRC specifying a value that is indicative of a smallest resume counter value of a first set of a plurality of resume counter values associated with a plurality of threads that are active when execution of the program is initiated, wherein each of the resume counter values associated with the plurality of threads is indicative of a program counter value at which the thread that corresponds to the respective resume counter value is scheduled to be activated if the respective one of the threads is inactive; and characterized by means for determining a second set of a plurality of resume counter values, wherein the second set is a subset of the first set and excludes one or more resume counter values that correspond to threads that are not active when execution of a subroutine is initiated; and means for controlling, based on a second MINRC associated with the subroutine, the flow instructions of the subroutine by comparing a target program counter value with the second MINRC and selecting either the target program counter value or the second MINRC value to load into the program counter based on the comparison, wherein the second MINRC specifies a value indicative of a smallest resume counter value from the second set of the plurality of resume counter values to ensure that the subroutine does not branch into the program or into another subroutine outside of the execution of a call or return instruction. means for controlling entry and exit of a subroutine from a program by comparing a target program counter value with a first minimum resume counter, MINRC, and selecting either the target program counter value or the first MINRC value to load into the program counter based on the comparison, the first MINRC specifying a value that is indicative of a smallest resume counter value of a first set of a plurality of resume counter values associated with a plurality of threads that are active when execution of the program is initiated, wherein each of the resume counter values associated with the plurality of threads is indicative of a program counter value at which the thread that corresponds to the respective resume counter value is scheduled to be activated if the respective one of the threads is inactive; and characterized by means for determining a second set of a plurality of resume counter values, wherein the second set is a subset of the first set and excludes one or more resume counter values that correspond to threads that are not active when execution of a subroutine is initiated; and means for controlling, based on a second MINRC associated with the subroutine, the flow instructions of the subroutine by comparing a target program counter value with the second MINRC and selecting either the target program counter value or the second MINRC value to load into the program counter based on the comparison, wherein the second MINRC specifies a value indicative of a smallest resume counter value from the second set of the plurality of resume counter values to ensure that the subroutine does not branch into the program or into another subroutine outside of the execution of a call or return instruction.