A liquid crystal display device comprising: a timing controlling unit configured to generate a gate control signal, a data control signal and an image data using an image signal; a data driving unit configured to generate a data voltage using the data control signal and the image data; a gate driving unit configured to generate a gate voltage (Vg) using the gate control signal; and a display panel including a plurality of gate lines and a plurality of data lines crossing each other to define a plurality of pixels, wherein the timing controlling unit is arranged to drive the display panel with a low image refresh rate frequency, f, of 1 Hz for displaying an image with sixty sub-frames having each a duration of 1/60 seconds, wherein the plurality of gate lines are divided into three groups, wherein the gate driving unit is adapted to sequentially apply the gate voltage (Vg) of an active level to the three groups of the plurality of gate lines in three different -sub-frames respectively, wherein said three sub-frames are within ten sub-frames of each other in the first to the sixtieth sub-frames, wherein the three groups consists of first, second and third groups and said three sub-frames are the first, (1+n)th and (1+2n)th sub-frames, where n is an integer equal to or greater than 1 and equal to or smaller than 5, wherein the first group includes (3p+1)th gate lines with p being an integer equal to or greater than 0 such as the first gate line, the fourth gate line, the seventh gate line, the tenth gate line, etc., wherein the second group includes (3p+2)th gate lines with p being an integer equal to or greater than 0 such as the second gate line, the fifth gate line, the eight gate line, the eleventh gate line, etc., wherein the third group includes (3p+3)th gate lines with p being an integer equal to or greater than 0 such as the third gate line, the sixth gate line, the ninth gate line, the twelfth gate line, etc., wherein the gate driving unit is adapted to sequentially apply the gate voltage of the active level to the gate lines of the first group during the first sub-frame, wherein the gate driving unit is adapted to sequentially apply the gate voltage of the active level to the gate lines of the second group during the (1+n)th sub-frame, and wherein the gate driving unit is adapted to sequentially apply the gate voltage of the active level to the gate lines of the third group during the (1+2n)th sub-frame. a timing controlling unit configured to generate a gate control signal, a data control signal and an image data using an image signal; a data driving unit configured to generate a data voltage using the data control signal and the image data; a gate driving unit configured to generate a gate voltage (Vg) using the gate control signal; and a display panel including a plurality of gate lines and a plurality of data lines crossing each other to define a plurality of pixels, wherein the timing controlling unit is arranged to drive the display panel with a low image refresh rate frequency, f, of 1 Hz for displaying an image with sixty sub-frames having each a duration of 1/60 seconds, wherein the plurality of gate lines are divided into three groups, wherein the gate driving unit is adapted to sequentially apply the gate voltage (Vg) of an active level to the three groups of the plurality of gate lines in three different -sub-frames respectively, wherein said three sub-frames are within ten sub-frames of each other in the first to the sixtieth sub-frames, wherein the three groups consists of first, second and third groups and said three sub-frames are the first, (1+n)th and (1+2n)th sub-frames, where n is an integer equal to or greater than 1 and equal to or smaller than 5, wherein the first group includes (3p+1)th gate lines with p being an integer equal to or greater than 0 such as the first gate line, the fourth gate line, the seventh gate line, the tenth gate line, etc., wherein the second group includes (3p+2)th gate lines with p being an integer equal to or greater than 0 such as the second gate line, the fifth gate line, the eight gate line, the eleventh gate line, etc., wherein the third group includes (3p+3)th gate lines with p being an integer equal to or greater than 0 such as the third gate line, the sixth gate line, the ninth gate line, the twelfth gate line, etc., wherein the gate driving unit is adapted to sequentially apply the gate voltage of the active level to the gate lines of the first group during the first sub-frame, wherein the gate driving unit is adapted to sequentially apply the gate voltage of the active level to the gate lines of the second group during the (1+n)th sub-frame, and wherein the gate driving unit is adapted to sequentially apply the gate voltage of the active level to the gate lines of the third group during the (1+2n)th sub-frame.