A memory device structure comprising: a first deck, wherein the first deck comprises: a first plurality of line structures, wherein individual ones of the first plurality of line structures each comprise a first transistor channel (108, 110); a second plurality of line structures substantially orthogonal to the first plurality of line structures, wherein individual ones of the second plurality of line structures each comprise a second transistor channel (118, 120); and a memory cell (122, 124, 126) at each cross-point between the first plurality of line structures and the second plurality of line structures; and a second deck above or below the first deck, wherein the second deck comprises: a third plurality of line structures substantially parallel to the first plurality of line structures, wherein individual ones of the third plurality of line structures each comprise a third transistor channel (138, 140); a fourth plurality of line structures substantially parallel to the second plurality of line structures, wherein individual ones of the fourth plurality of line structures each comprise a fourth transistor channel (148, 150); and a memory cell (152, 153, 164) at each cross-point between the third plurality of line structures and the fourth plurality of line structures, characterised in that the memory device structure further comprises a plurality of terminal interconnects (155, 156) between the first deck and the second deck, wherein individual ones of the plurality of terminal interconnects (155, 156) are coupled between the individual ones of the line structures, in the first deck and corresponding individual ones of the line structures, in the second deck; and wherein individual ones of the transistor channels (108, 110, 118, 120) are between individual ones of the terminal interconnects (155, 156) and the memory cells (122, 124, 126, 152, 153). a first plurality of line structures, wherein individual ones of the first plurality of line structures each comprise a first transistor channel (108, 110); a second plurality of line structures substantially orthogonal to the first plurality of line structures, wherein individual ones of the second plurality of line structures each comprise a second transistor channel (118, 120); and a memory cell (122, 124, 126) at each cross-point between the first plurality of line structures and the second plurality of line structures; and a second deck above or below the first deck, wherein the second deck comprises: a third plurality of line structures substantially parallel to the first plurality of line structures, wherein individual ones of the third plurality of line structures each comprise a third transistor channel (138, 140); a fourth plurality of line structures substantially parallel to the second plurality of line structures, wherein individual ones of the fourth plurality of line structures each comprise a fourth transistor channel (148, 150); and a memory cell (152, 153, 164) at each cross-point between the third plurality of line structures and the fourth plurality of line structures, characterised in that the memory device structure further comprises a plurality of terminal interconnects (155, 156) between the first deck and the second deck, wherein individual ones of the plurality of terminal interconnects (155, 156) are coupled between the individual ones of the line structures, in the first deck and corresponding individual ones of the line structures, in the second deck; and wherein individual ones of the transistor channels (108, 110, 118, 120) are between individual ones of the terminal interconnects (155, 156) and the memory cells (122, 124, 126, 152, 153). a third plurality of line structures substantially parallel to the first plurality of line structures, wherein individual ones of the third plurality of line structures each comprise a third transistor channel (138, 140); a fourth plurality of line structures substantially parallel to the second plurality of line structures, wherein individual ones of the fourth plurality of line structures each comprise a fourth transistor channel (148, 150); and a memory cell (152, 153, 164) at each cross-point between the third plurality of line structures and the fourth plurality of line structures, characterised in that the memory device structure further comprises a plurality of terminal interconnects (155, 156) between the first deck and the second deck, wherein individual ones of the plurality of terminal interconnects (155, 156) are coupled between the individual ones of the line structures, in the first deck and corresponding individual ones of the line structures, in the second deck; and wherein individual ones of the transistor channels (108, 110, 118, 120) are between individual ones of the terminal interconnects (155, 156) and the memory cells (122, 124, 126, 152, 153).