A method of manufacturing a semiconductor device having a semiconductor element, which has a device forming layer and an electrode pad on one surface of the semiconductor element, a wiring pattern formed on the other surface of the semiconductor element, and a through electrode that connects the electrode pad of the semiconductor element and the wiring pattern, the method comprising: a first step of forming a first resist layer on said one surface of the semiconductor element; a second step of forming an opening (84, 86) in the first resist layer and then through the center of the electrode pad by plasma etching, wherein the first resist layer protects the device forming layer from the plasma etching; a third step of forming, by plasma etching, a through hole in the semiconductor element in a position that communicates with the opening (84, 86), wherein the device forming layer is protected by the first resist layer from the plasma etching; a fourth step of forming an insulating layer on the other surface of the semiconductor element and an inner periphery of the through hole; a fifth step of removing a portion of the first resist layer, which covers a surface of the electrode pad, by forming a second resist layer on a surface of the first resist layer, patterning the second resist layer, and removing exposed portions of the first resist layer on the surface of the electrode pad by ashing; a sixth step of forming a power feeding layer on the other surface of the semiconductor element; a seventh step of forming the through electrode in the through hole and on a surface of the electrode pad by depositing a conductive material on a portion of the power feeding layer opposing to the through hole by means of plating, wherein the device forming layer is protected by the first resist layer during the plating; an eighth step of removing the power feeding layer; and forming the wiring pattern on the other surface of the semiconductor element. a first step of forming a first resist layer on said one surface of the semiconductor element; a second step of forming an opening (84, 86) in the first resist layer and then through the center of the electrode pad by plasma etching, wherein the first resist layer protects the device forming layer from the plasma etching; a third step of forming, by plasma etching, a through hole in the semiconductor element in a position that communicates with the opening (84, 86), wherein the device forming layer is protected by the first resist layer from the plasma etching; a fourth step of forming an insulating layer on the other surface of the semiconductor element and an inner periphery of the through hole; a fifth step of removing a portion of the first resist layer, which covers a surface of the electrode pad, by forming a second resist layer on a surface of the first resist layer, patterning the second resist layer, and removing exposed portions of the first resist layer on the surface of the electrode pad by ashing; a sixth step of forming a power feeding layer on the other surface of the semiconductor element; a seventh step of forming the through electrode in the through hole and on a surface of the electrode pad by depositing a conductive material on a portion of the power feeding layer opposing to the through hole by means of plating, wherein the device forming layer is protected by the first resist layer during the plating; an eighth step of removing the power feeding layer; and