An array substrate, comprising: a protective circuit, a voltage input terminal and at least one data line (DL1-DLN), wherein the protective circuit comprises: a control sub-circuit; and a discharge sub-circuit; the control sub-circuit further comprises: a first thin-film transistor (TFT 01) and a second thin-film transistor (TFT 02), wherein both a first electrode and a gate electrode of the first thin-film transistor (TFT 01) are electrically connected to the voltage input terminal, and a second electrode of the first thin-film transistor (TFT 01) is electrically connected to a first electrode of the second thin-film transistor (TFT 02); and a second electrode of the second thin-film transistor (TFT 02) is electrically connected to the first electrode of the first thin-film transistor (TFT 01), and both a first electrode and a gate electrode of the second thin-film transistor (TFT 02) are electrically connected to an output signal line of the discharge sub-circuit; characterized in that, the discharge sub-circuit comprises a plurality of signal lines connected in parallel with one another, and the plurality of signal lines are connected to the output signal line, the discharge sub-circuit further comprises an array of third thin-film transistors (TFTs 03), and each third thin-film transistor (TFT 03) has both a first electrode and a gate electrode electrically connected to a signal line of the plurality of signal lines, the signal line corresponds to a row in which the third thin-film transistor (TFT 03) is located, and a second electrode electrically connected to a data line, corresponding to a column in which the third thin-film transistor (TFT 03) is located, of the at least one data line (DL1-DLN); the voltage input terminal is configured to provide a common voltage signal to turn on the first thin film transistor (TFT 01) and the second thin-film transistor (TFT 02), the output signal line is controlled to output the common voltage signal, to turn on the third thin-film transistor (TFT 03), and the discharge sub-circuit is configured to release electric charges on the at least one data line (DL1-DLN) under the control of the common voltage signal supplied from the control sub-circuit. the control sub-circuit further comprises: a first thin-film transistor (TFT 01) and a second thin-film transistor (TFT 02), wherein both a first electrode and a gate electrode of the first thin-film transistor (TFT 01) are electrically connected to the voltage input terminal, and a second electrode of the first thin-film transistor (TFT 01) is electrically connected to a first electrode of the second thin-film transistor (TFT 02); and a second electrode of the second thin-film transistor (TFT 02) is electrically connected to the first electrode of the first thin-film transistor (TFT 01), and both a first electrode and a gate electrode of the second thin-film transistor (TFT 02) are electrically connected to an output signal line of the discharge sub-circuit; characterized in that, the discharge sub-circuit comprises a plurality of signal lines connected in parallel with one another, and the plurality of signal lines are connected to the output signal line, the discharge sub-circuit further comprises an array of third thin-film transistors (TFTs 03), and each third thin-film transistor (TFT 03) has both a first electrode and a gate electrode electrically connected to a signal line of the plurality of signal lines, the signal line corresponds to a row in which the third thin-film transistor (TFT 03) is located, and a second electrode electrically connected to a data line, corresponding to a column in which the third thin-film transistor (TFT 03) is located, of the at least one data line (DL1-DLN); the voltage input terminal is configured to provide a common voltage signal to turn on the first thin film transistor (TFT 01) and the second thin-film transistor (TFT 02), the output signal line is controlled to output the common voltage signal, to turn on the third thin-film transistor (TFT 03), and the discharge sub-circuit is configured to release electric charges on the at least one data line (DL1-DLN) under the control of the common voltage signal supplied from the control sub-circuit.