A bus interconnect, comprising: an interconnect network configurable to connect at least one master port among a plurality of master ports (16 -16) to at least one slave port; and a controller configured to generate a bus interconnect clock signal to clock the interconnect network;wherein the controller is configured to: receive at least one first bandwidth information related to traffic communicated over the at least one master port; receive at least one second bandwidth information related to traffic communicated over the at least one slave port; characterized in that the controller is further configured to: receive at least one latency information related to traffic communicated over the at least one master port; decrease a frequency of the bus interconnect clock signal in response to: (a) the at least one first bandwidth information meeting a respective at least one first bandwidth condition; and (b) the at least one second bandwidth information meeting a respective at least one second bandwidth condition; and (c) the at least one latency information meeting a respective latency condition. an interconnect network configurable to connect at least one master port among a plurality of master ports (16 -16) to at least one slave port; and a controller configured to generate a bus interconnect clock signal to clock the interconnect network;wherein the controller is configured to: receive at least one first bandwidth information related to traffic communicated over the at least one master port; receive at least one second bandwidth information related to traffic communicated over the at least one slave port; receive at least one first bandwidth information related to traffic communicated over the at least one master port; receive at least one second bandwidth information related to traffic communicated over the at least one slave port; characterized in that the controller is further configured to: receive at least one latency information related to traffic communicated over the at least one master port; decrease a frequency of the bus interconnect clock signal in response to: (a) the at least one first bandwidth information meeting a respective at least one first bandwidth condition; and (b) the at least one second bandwidth information meeting a respective at least one second bandwidth condition; and (c) the at least one latency information meeting a respective latency condition. receive at least one latency information related to traffic communicated over the at least one master port; decrease a frequency of the bus interconnect clock signal in response to: (a) the at least one first bandwidth information meeting a respective at least one first bandwidth condition; and (b) the at least one second bandwidth information meeting a respective at least one second bandwidth condition; and (c) the at least one latency information meeting a respective latency condition. (a) the at least one first bandwidth information meeting a respective at least one first bandwidth condition; and (b) the at least one second bandwidth information meeting a respective at least one second bandwidth condition; and (c) the at least one latency information meeting a respective latency condition.