An electronic processor architecture for use with a memory having storage at physical addresses, the electronic processor architecture comprising: a processor; a memory cache; a cache control circuit configured to cache memory data of a physical address by a virtual address; a translation circuit for translating between a virtual address from the processor and a physical address; and characterized by: a synonym tracking circuit configured to receive a given virtual address from the processor for access to the cache and configured to: determine if the given virtual address is a synonym with an other virtual address mapping to a same given physical memory address of data in the memory cache; and when the given virtual memory address is a synonym, access the memory cache using the other virtual address as an accessing address for the memory cache; wherein the synonym tracking circuit includes a first table of virtual addresses linked as synonyms to determine if a given virtual address is a synonym; wherein the synonym tracking circuit is configured to respond to a cache miss of the memory cache by determining a physical address associated with the given virtual address and applying the determined physical address to a second table linking a physical address and a virtual address, and when a determined physical address links to a virtual address in the second table, using the virtual address of the second table as an accessing address for the memory cache. a processor; a memory cache; a cache control circuit configured to cache memory data of a physical address by a virtual address; a translation circuit for translating between a virtual address from the processor and a physical address; and characterized by: a synonym tracking circuit configured to receive a given virtual address from the processor for access to the cache and configured to: determine if the given virtual address is a synonym with an other virtual address mapping to a same given physical memory address of data in the memory cache; and when the given virtual memory address is a synonym, access the memory cache using the other virtual address as an accessing address for the memory cache; wherein the synonym tracking circuit includes a first table of virtual addresses linked as synonyms to determine if a given virtual address is a synonym; wherein the synonym tracking circuit is configured to respond to a cache miss of the memory cache by determining a physical address associated with the given virtual address and applying the determined physical address to a second table linking a physical address and a virtual address, and when a determined physical address links to a virtual address in the second table, using the virtual address of the second table as an accessing address for the memory cache. a synonym tracking circuit configured to receive a given virtual address from the processor for access to the cache and configured to: determine if the given virtual address is a synonym with an other virtual address mapping to a same given physical memory address of data in the memory cache; and when the given virtual memory address is a synonym, access the memory cache using the other virtual address as an accessing address for the memory cache; determine if the given virtual address is a synonym with an other virtual address mapping to a same given physical memory address of data in the memory cache; and when the given virtual memory address is a synonym, access the memory cache using the other virtual address as an accessing address for the memory cache; wherein the synonym tracking circuit includes a first table of virtual addresses linked as synonyms to determine if a given virtual address is a synonym; wherein the synonym tracking circuit is configured to respond to a cache miss of the memory cache by determining a physical address associated with the given virtual address and applying the determined physical address to a second table linking a physical address and a virtual address, and when a determined physical address links to a virtual address in the second table, using the virtual address of the second table as an accessing address for the memory cache.