An array structure comprising plural memory cells (c11∼c33) in an array arrangement, each of the plural memory cells (c11∼c33) comprising: a latch connected with a first node (a) and a second node (b), and receiving a first power voltage (Vdd) and a second power voltage (Vss), wherein the latch is connected with an enable line, and the latch is selectively enabled or disabled according to an enable line voltage from the enable line; a first antifuse element comprising a first antifuse transistor having a gate terminal connected with the antifuse control line and a first drain/source terminal coupled with the first node (a), wherein if a first voltage difference between the gate terminal and the first drain/source terminal of the first antifuse transistor exceeds a threshold value, a gate oxide layer of the first antifuse transistor is ruptured; a second antifuse element comprising a second antifuse transistor having a gate terminal connected with the antifuse control line and a first drain/source terminal coupled with the second node (b), wherein if a second voltage difference between the gate terminal and the first drain/source terminal of the second antifuse transistor exceeds the threshold value, a gate oxide layer of the second antifuse transistor is ruptured; a first select transistor, wherein a gate terminal of the first select transistor is connected with a word line, a first drain/source terminal of the first select transistor is connected with the first node (a), and a second drain/source terminal of the first select transistor is connected with a bit line; and a second select transistor, wherein a gate terminal of the second select transistor is connected with the word line, a first drain/source terminal of the second select transistor is connected with the second node (b), and a second drain/source terminal of the second select transistor is connected with an inverted bit line. a latch connected with a first node (a) and a second node (b), and receiving a first power voltage (Vdd) and a second power voltage (Vss), wherein the latch is connected with an enable line, and the latch is selectively enabled or disabled according to an enable line voltage from the enable line; a first antifuse element comprising a first antifuse transistor having a gate terminal connected with the antifuse control line and a first drain/source terminal coupled with the first node (a), wherein if a first voltage difference between the gate terminal and the first drain/source terminal of the first antifuse transistor exceeds a threshold value, a gate oxide layer of the first antifuse transistor is ruptured; a second antifuse element comprising a second antifuse transistor having a gate terminal connected with the antifuse control line and a first drain/source terminal coupled with the second node (b), wherein if a second voltage difference between the gate terminal and the first drain/source terminal of the second antifuse transistor exceeds the threshold value, a gate oxide layer of the second antifuse transistor is ruptured; a first select transistor, wherein a gate terminal of the first select transistor is connected with a word line, a first drain/source terminal of the first select transistor is connected with the first node (a), and a second drain/source terminal of the first select transistor is connected with a bit line; and a second select transistor, wherein a gate terminal of the second select transistor is connected with the word line, a first drain/source terminal of the second select transistor is connected with the second node (b), and a second drain/source terminal of the second select transistor is connected with an inverted bit line.