A system comprising a primary device and a secondary device, wherein: the primary device comprises: - a first port connected to a first port of the secondary device and configured to provide a clock signal (ZPclk) determining, for each transmission of a bit (DATA, ACK, CTRL) between the two devices (M, S), a succession of a first phase, a second phase, a third phase and a fourth phase, and - a second port connected to a second port of the secondary device by a wire devoid of pull-up resistor coupling the wire to a node configured to receive a first potential (Vdd); the secondary device is configured to put its second port in a high impedance state during the first, second and fourth phases (P1, P2, P4) of each transmission of a bit (DATA, ACK, CTRL) between the two devices; the secondary device is configured, during the third phase of each transmission of a bit of data (DATA) from the secondary device to the primary device, to discharge its second port to a reference potential different from the first potential (Vdd) when the transmitted bit of data (DATA) has a first value and to leave its second port in a high impedance state when the transmitted bit of data (DATA) has a second value; the primary device is configured to load its second port to the first potential (Vdd) during the first phase of each transmission of a bit of data (DATA) between the two devices; the primary device is configured to put its second port in a high impedance state during the second and fourth phases (P2, P4) of each transmission of a bit of data (DATA) between the two devices; the primary device is configured to put its second port in a high impedance state during the third phase of each transmission of a bit of data (DATA) from the secondary device to the primary device; the primary device is configured, during the fourth phase of each transmission of a bit of data (DATA) from the secondary device to the primary device, to determine a value of the transmitted bit of data (DATA) based on a potential on its second port during said fourth phase; and the primary device is configured to apply the reference potential to its second port during the first phase of each transmission of a bit of control (CTRL) from the primary device to the secondary device. the primary device comprises: - a first port connected to a first port of the secondary device and configured to provide a clock signal (ZPclk) determining, for each transmission of a bit (DATA, ACK, CTRL) between the two devices (M, S), a succession of a first phase, a second phase, a third phase and a fourth phase, and - a second port connected to a second port of the secondary device by a wire devoid of pull-up resistor coupling the wire to a node configured to receive a first potential (Vdd); - a first port connected to a first port of the secondary device and configured to provide a clock signal (ZPclk) determining, for each transmission of a bit (DATA, ACK, CTRL) between the two devices (M, S), a succession of a first phase, a second phase, a third phase and a fourth phase, and - a second port connected to a second port of the secondary device by a wire devoid of pull-up resistor coupling the wire to a node configured to receive a first potential (Vdd); the secondary device is configured to put its second port in a high impedance state during the first, second and fourth phases (P1, P2, P4) of each transmission of a bit (DATA, ACK, CTRL) between the two devices; the secondary device is configured, during the third phase of each transmission of a bit of data (DATA) from the secondary device to the primary device, to discharge its second port to a reference potential different from the first potential (Vdd) when the transmitted bit of data (DATA) has a first value and to leave its second port in a high impedance state when the transmitted bit of data (DATA) has a second value; the primary device is configured to load its second port to the first potential (Vdd) during the first phase of each transmission of a bit of data (DATA) between the two devices; the primary device is configured to put its second port in a high impedance state during the second and fourth phases (P2, P4) of each transmission of a bit of data (DATA) between the two devices; the primary device is configured to put its second port in a high impedance state during the third phase of each transmission of a bit of data (DATA) from the secondary device to the primary device; the primary device is configured, during the fourth phase of each transmission of a bit of data (DATA) from the secondary device to the primary device, to determine a value of the transmitted bit of data (DATA) based on a potential on its second port during said fourth phase; and the primary device is configured to apply the reference potential to its second port during the first phase of each transmission of a bit of control (CTRL) from the primary device to the secondary device.