A cell array structure comprising a first antifuse-type one time programming memory cell, the first antifuse-type one time programming memory cell comprising: a first select device, wherein a first terminal of the first select device is connected with a first bit line, a second terminal of the first select device is connected with a first node, and a select terminal of the first select device is connected with a first word line; a first following device, wherein a first terminal of the first following device is connected with the first node, a second terminal of the first following device is connected with a second node, and a first control terminal of the first following device is connected with a first following control line; and a first antifuse transistor (M AF), wherein a first drain/source terminal of the first antifuse transistor (M AF) is connected with the second node, a gate terminal of the first antifuse transistor (M AF) is connected with a first antifuse control line, and a second drain/source terminal of the first antifuse transistor (M AF) is in a floating state, wherein the first select device comprises a first select transistor (M S1) and a second select transistor (M S2), wherein a first drain/source terminal of the first select transistor (M S1) is connected with the first bit line, a gate terminal of the first select transistor (M S1) is connected with the first word line, a second drain/source terminal of the first select transistor (M S1) is connected with a first drain/source terminal of the second select transistor (M S2), a gate terminal of the second select transistor (M S2) is connected with the first word line, and a second drain/source terminal of the second select transistor (M S2) is connected with the first node; and wherein when a program inhibition action is performed, the first bit line is configured to receive a ground voltage (0 V), the first word line is configured to receive an off voltage, the first following control line is configured to receive a first control voltage (V FL1), and the first antifuse control line is configured to receive a program voltage (V PP), wherein when the program inhibition action is performed, the first select transistor (M S1) and the second select transistor (M S2) of the first select device are configured to be turned off to completely turn off the first select device, the first following device is in a conducting state, and a gate oxide layer of the first antifuse transistor (M AF) is not ruptured, so that the first antifuse-type one time programming memory cell is in a high-resistance storage state. a first select device, wherein a first terminal of the first select device is connected with a first bit line, a second terminal of the first select device is connected with a first node, and a select terminal of the first select device is connected with a first word line; a first following device, wherein a first terminal of the first following device is connected with the first node, a second terminal of the first following device is connected with a second node, and a first control terminal of the first following device is connected with a first following control line; and a first antifuse transistor (M AF), wherein a first drain/source terminal of the first antifuse transistor (M AF) is connected with the second node, a gate terminal of the first antifuse transistor (M AF) is connected with a first antifuse control line, and a second drain/source terminal of the first antifuse transistor (M AF) is in a floating state, wherein the first select device comprises a first select transistor (M S1) and a second select transistor (M S2), wherein a first drain/source terminal of the first select transistor (M S1) is connected with the first bit line, a gate terminal of the first select transistor (M S1) is connected with the first word line, a second drain/source terminal of the first select transistor (M S1) is connected with a first drain/source terminal of the second select transistor (M S2), a gate terminal of the second select transistor (M S2) is connected with the first word line, and a second drain/source terminal of the second select transistor (M S2) is connected with the first node; and wherein when a program inhibition action is performed, the first bit line is configured to receive a ground voltage (0 V), the first word line is configured to receive an off voltage, the first following control line is configured to receive a first control voltage (V FL1), and the first antifuse control line is configured to receive a program voltage (V PP), wherein when the program inhibition action is performed, the first select transistor (M S1) and the second select transistor (M S2) of the first select device are configured to be turned off to completely turn off the first select device, the first following device is in a conducting state, and a gate oxide layer of the first antifuse transistor (M AF) is not ruptured, so that the first antifuse-type one time programming memory cell is in a high-resistance storage state.