A thyristor device comprising: a semiconductor wafer (301; 501) having a first main side and a second main side opposite to the first main side; a first electrode layer, which is arranged on the first main side; a second electrode layer, which is arranged on the first main side and which is electrically separated from the first electrode layer; a third electrode layer, which is arranged on the second main side; wherein the semiconductor wafer (301; 501) includes the following layers: a first emitter layer of a first conductivity type, the first emitter layer being in electrical contact with the first electrode layer; a first base layer of a second conductivity type different from the first conductivity type, wherein the first base layer is in electrical contact with the second electrode layer, and wherein the first base layer and the first emitter layer form a first p-n junction; a second base layer of the first conductivity type, the second base layer and the first base layer forming a second p-n junction; a second emitter layer of the second conductivity type, wherein the second emitter layer is in electrical contact with the third electrode layer, and wherein the second emitter layer and the second base layer form a third p-n junction, wherein the thyristor device comprises a plurality of discrete emitter shorts, each emitter short penetrating through the first emitter layer to electrically connect the first base layer with the first electrode layer, wherein in an orthogonal projection onto a plane parallel to the first main side, a contact area covered by an electrical contact of the first electrode layer with the first emitter layer and the emitter shorts includes areas in the shape of lanes (350A-350F; 550A-550F) in which no emitter shorts are arranged, wherein, in the orthogonal projection onto the plane parallel to the first main side, the lanes (350A-350F; 550A-550F) extend from an edge of the contact area adjacent to the second electrode layer in a direction away from the second electrode layer; characterized in that the width of the lanes (350A-350F; 550A-550F) is at least two times the average distance between centers of emitter shorts next to each other in the contact area, and in that the lanes (350A-350F; 550A-550F) are curved. a semiconductor wafer (301; 501) having a first main side and a second main side opposite to the first main side; a first electrode layer, which is arranged on the first main side; a second electrode layer, which is arranged on the first main side and which is electrically separated from the first electrode layer; a third electrode layer, which is arranged on the second main side; wherein the semiconductor wafer (301; 501) includes the following layers: a first emitter layer of a first conductivity type, the first emitter layer being in electrical contact with the first electrode layer; a first base layer of a second conductivity type different from the first conductivity type, wherein the first base layer is in electrical contact with the second electrode layer, and wherein the first base layer and the first emitter layer form a first p-n junction; a second base layer of the first conductivity type, the second base layer and the first base layer forming a second p-n junction; a second emitter layer of the second conductivity type, wherein the second emitter layer is in electrical contact with the third electrode layer, and wherein the second emitter layer and the second base layer form a third p-n junction, a first emitter layer of a first conductivity type, the first emitter layer being in electrical contact with the first electrode layer; a first base layer of a second conductivity type different from the first conductivity type, wherein the first base layer is in electrical contact with the second electrode layer, and wherein the first base layer and the first emitter layer form a first p-n junction; a second base layer of the first conductivity type, the second base layer and the first base layer forming a second p-n junction; a second emitter layer of the second conductivity type, wherein the second emitter layer is in electrical contact with the third electrode layer, and wherein the second emitter layer and the second base layer form a third p-n junction, wherein the thyristor device comprises a plurality of discrete emitter shorts, each emitter short penetrating through the first emitter layer to electrically connect the first base layer with the first electrode layer, wherein in an orthogonal projection onto a plane parallel to the first main side, a contact area covered by an electrical contact of the first electrode layer with the first emitter layer and the emitter shorts includes areas in the shape of lanes (350A-350F; 550A-550F) in which no emitter shorts are arranged, wherein, in the orthogonal projection onto the plane parallel to the first main side, the lanes (350A-350F; 550A-550F) extend from an edge of the contact area adjacent to the second electrode layer in a direction away from the second electrode layer; characterized in that the width of the lanes (350A-350F; 550A-550F) is at least two times the average distance between centers of emitter shorts next to each other in the contact area, and in that the lanes (350A-350F; 550A-550F) are curved.