A processing system, comprising: a receiving device; a bus having first, second and third channels; and a sending device comprising: means for addressing the receiving device on the first channel; means for reading a payload from the receiving device on the second channel; and means for selecting between the first and third channels to write a payload to the receiving device, the sending device being configured to send, during a first write operation, address data to the receiving device on the first channel with appropriate control signals, while, during the same clock cycle, sending a first part of first payload data to the receiving device on the third channel; to send, during initiation of a second write operation in the following clock cycle, address data on the first channel with appropriate control signals concurrently with a second part of the first payload data on the third channel; and to subsequently send second payload data to the receiving device on the first channel while concurrently completing sending first payload data to the receiving device on the third channel during the next two clock cycles. a receiving device; a bus having first, second and third channels; and a sending device comprising: means for addressing the receiving device on the first channel; means for reading a payload from the receiving device on the second channel; and means for selecting between the first and third channels to write a payload to the receiving device, the sending device being configured to send, during a first write operation, address data to the receiving device on the first channel with appropriate control signals, while, during the same clock cycle, sending a first part of first payload data to the receiving device on the third channel; to send, during initiation of a second write operation in the following clock cycle, address data on the first channel with appropriate control signals concurrently with a second part of the first payload data on the third channel; and to subsequently send second payload data to the receiving device on the first channel while concurrently completing sending first payload data to the receiving device on the third channel during the next two clock cycles. means for addressing the receiving device on the first channel; means for reading a payload from the receiving device on the second channel; and means for selecting between the first and third channels to write a payload to the receiving device, the sending device being configured to send, during a first write operation, address data to the receiving device on the first channel with appropriate control signals, while, during the same clock cycle, sending a first part of first payload data to the receiving device on the third channel; to send, during initiation of a second write operation in the following clock cycle, address data on the first channel with appropriate control signals concurrently with a second part of the first payload data on the third channel; and to subsequently send second payload data to the receiving device on the first channel while concurrently completing sending first payload data to the receiving device on the third channel during the next two clock cycles.