A burst mode receiver for a passive optical network, comprising: (i) a high gain circuitry portion having a plurality of cascaded amplifiers (32a-c), each of the cascaded amplifiers configured to increase a gain of an input signal, and a plurality of high gain switches (SW3, SW4, SW6); and (ii) an adaptive gain circuitry portion having at least one amplifying inverter comprising an p-type metal oxide semiconductor, PMOS, transistor, the adaptive gain circuitry portion configured to adaptively control the gain of the input signal, and a plurality of adaptive gain switches (SW1, SW2, SW5); and wherein the high gain circuitry portion and the adaptive gain circuitry portion comprise a shared input portion comprising at least one n-type metal oxide semiconductor, NMOS, transistor; wherein the combination of PMOS transistor with NMOS transistor forms the amplifying inverter and a first amplifier of the plurality of cascaded amplifiers (32a-c) comprises the NMOS transistor; wherein, when a peak detector detects input current in a first range, the burst mode receiver is configured to activate the high gain circuitry portion and de-activate the adaptive gain circuitry portion, in which the high gain switches (SW3, SW4, SW6) are closed and the adaptive gain switches (SW1, SW2, SW5) are opened, and when the peak detector detects input current in a second range, the burst mode receiver is configured to activate the adaptive gain circuitry portion and de-activate the high gain circuitry portion, in which the high gain switches (SW3, SW4, SW6) are opened and the adaptive gain switches (SW1, SW2, SW5) are closed; and wherein the first range is between 3 μA and 35μA, and the second range is between 25μA and 3 mA comprising a hysteresis, or overlap, region of 10 μA. (i) a high gain circuitry portion having a plurality of cascaded amplifiers (32a-c), each of the cascaded amplifiers configured to increase a gain of an input signal, and a plurality of high gain switches (SW3, SW4, SW6); and (ii) an adaptive gain circuitry portion having at least one amplifying inverter comprising an p-type metal oxide semiconductor, PMOS, transistor, the adaptive gain circuitry portion configured to adaptively control the gain of the input signal, and a plurality of adaptive gain switches (SW1, SW2, SW5); and wherein the high gain circuitry portion and the adaptive gain circuitry portion comprise a shared input portion comprising at least one n-type metal oxide semiconductor, NMOS, transistor; wherein the combination of PMOS transistor with NMOS transistor forms the amplifying inverter and a first amplifier of the plurality of cascaded amplifiers (32a-c) comprises the NMOS transistor; wherein, when a peak detector detects input current in a first range, the burst mode receiver is configured to activate the high gain circuitry portion and de-activate the adaptive gain circuitry portion, in which the high gain switches (SW3, SW4, SW6) are closed and the adaptive gain switches (SW1, SW2, SW5) are opened, and when the peak detector detects input current in a second range, the burst mode receiver is configured to activate the adaptive gain circuitry portion and de-activate the high gain circuitry portion, in which the high gain switches (SW3, SW4, SW6) are opened and the adaptive gain switches (SW1, SW2, SW5) are closed; and wherein the first range is between 3 μA and 35μA, and the second range is between 25μA and 3 mA comprising a hysteresis, or overlap, region of 10 μA. wherein the high gain circuitry portion and the adaptive gain circuitry portion comprise a shared input portion comprising at least one n-type metal oxide semiconductor, NMOS, transistor; wherein the combination of PMOS transistor with NMOS transistor forms the amplifying inverter and a first amplifier of the plurality of cascaded amplifiers (32a-c) comprises the NMOS transistor; wherein, when a peak detector detects input current in a first range, the burst mode receiver is configured to activate the high gain circuitry portion and de-activate the adaptive gain circuitry portion, in which the high gain switches (SW3, SW4, SW6) are closed and the adaptive gain switches (SW1, SW2, SW5) are opened, and when the peak detector detects input current in a second range, the burst mode receiver is configured to activate the adaptive gain circuitry portion and de-activate the high gain circuitry portion, in which the high gain switches (SW3, SW4, SW6) are opened and the adaptive gain switches (SW1, SW2, SW5) are closed; and wherein the first range is between 3 μA and 35μA, and the second range is between 25μA and 3 mA comprising a hysteresis, or overlap, region of 10 μA.