A semiconductor apparatus comprising: a first processor core; a second processor core that has a redundant configuration with respect to the first processor core; a first debug circuit that makes a first debugging setting for the first processor core; a second debug circuit that makes a second debugging setting for the second processor core, the second debugging setting including setting a breakpoint for stopping the execution of the program by the second processor core and being different from the first debugging setting; a determination circuit that determines whether a first processing result of a program by the first processor core matches a second processing result of the program by the second processor core; and an error control circuit capable of outputting an error signal for stopping execution of the program by the first and second processor cores (11, 12) based on a determination result of the determination circuit that the first processing result and the second processing result do not match, wherein the second processor core is configured, if the first processing result and the second processing result match at a time when execution of the program by the second processor core reaches the breakpoint, to transition to a break state in which the second processor core is stopping execution of the program, wherein the error control circuit is configured, when the first processor core is in an execution state in which the first processor core is executing the program and the second processor core is in the break state, to disable outputting the error signal, even if the first processing result and the second processing result do not match each other, and wherein the second debug circuit is configured to acquire internal information of the second processor core after the second processor core has transitioned to the break state. a first processor core; a second processor core that has a redundant configuration with respect to the first processor core; a first debug circuit that makes a first debugging setting for the first processor core; a second debug circuit that makes a second debugging setting for the second processor core, the second debugging setting including setting a breakpoint for stopping the execution of the program by the second processor core and being different from the first debugging setting; a determination circuit that determines whether a first processing result of a program by the first processor core matches a second processing result of the program by the second processor core; and an error control circuit capable of outputting an error signal for stopping execution of the program by the first and second processor cores (11, 12) based on a determination result of the determination circuit that the first processing result and the second processing result do not match, wherein the second processor core is configured, if the first processing result and the second processing result match at a time when execution of the program by the second processor core reaches the breakpoint, to transition to a break state in which the second processor core is stopping execution of the program, wherein the error control circuit is configured, when the first processor core is in an execution state in which the first processor core is executing the program and the second processor core is in the break state, to disable outputting the error signal, even if the first processing result and the second processing result do not match each other, and wherein the second debug circuit is configured to acquire internal information of the second processor core after the second processor core has transitioned to the break state.