A method for transmitting data between a timing controller and a source driver, the method having a bit error rate test function, the method comprising the steps of: (a) transmitting in a normal mode, wherein a clock training step of synchronizing clocks between the timing controller and the source driver, a step of sequentially transmitting a control start packet CTR_START, control packets CTR1 and CTR2, and a data start packet DATA_START for configuration setup of the source driver, and a step of transmitting a data packet RGB DATA are included as one cycle; (b) transmitting in a bit error rate test (BERT) ready mode, wherein logic states of the control start packet and data start packet in the normal mode are changed and transmitted by first and second BERT packets; (c) transmitting in a BERT operation mode, wherein the control packets are disregarded by the first BERT packet in the BERT ready mode, and a pseudo random binary sequence (PRBS) pattern instead of the data packet is transmitted by the second BERT packet, wherein a first linear feedback shift register included in the timing controller outputs a first bit stream, a first XOR gate included in the timing controller outputs the PRBS pattern by performing an XOR operation between the first bit stream and a bit stream in which all the bits have a value of 1, and a second linear feedback shift register included in the source driver outputs a second bit stream, the linear feedback shift registers having the same characteristic equation, and wherein the second bit stream set in the source driver by the second linear feedback shift register is the same as the first bit stream set in the timing controller by the first linear feedback shift register; and (d) comparing the pseudo random binary sequence and the second bit stream set in the source driver, and sensing a bit error rate. (a) transmitting in a normal mode, wherein a clock training step of synchronizing clocks between the timing controller and the source driver, a step of sequentially transmitting a control start packet CTR_START, control packets CTR1 and CTR2, and a data start packet DATA_START for configuration setup of the source driver, and a step of transmitting a data packet RGB DATA are included as one cycle; (b) transmitting in a bit error rate test (BERT) ready mode, wherein logic states of the control start packet and data start packet in the normal mode are changed and transmitted by first and second BERT packets; (c) transmitting in a BERT operation mode, wherein the control packets are disregarded by the first BERT packet in the BERT ready mode, and a pseudo random binary sequence (PRBS) pattern instead of the data packet is transmitted by the second BERT packet, wherein a first linear feedback shift register included in the timing controller outputs a first bit stream, a first XOR gate included in the timing controller outputs the PRBS pattern by performing an XOR operation between the first bit stream and a bit stream in which all the bits have a value of 1, and a second linear feedback shift register included in the source driver outputs a second bit stream, the linear feedback shift registers having the same characteristic equation, and wherein the second bit stream set in the source driver by the second linear feedback shift register is the same as the first bit stream set in the timing controller by the first linear feedback shift register; and (d) comparing the pseudo random binary sequence and the second bit stream set in the source driver, and sensing a bit error rate.