A reception circuit for receiving data in serial communications through a plurality of lanes, comprising: a plurality of buffers each for storing data received through a corresponding lane, one buffer of the plurality of buffers being provided for each lane of the plurality of lanes; a multilane control circuit for detecting the skew between the lanes by detecting a deskew pattern at each buffer's read data, and for outputting, according to the detected skew, a first signal, which does not increment a read address of each of the plurality of buffers and which is for eliminating the skew between the lanes, to a plurality of address control circuits other than an address control circuit corresponding to a lane that is a last to receive the deskew pattern, and for outputting a deskew information indicating that a skew adjustment between the lanes is to be performed; the plurality of address control circuits each for transmitting the first signal to a corresponding buffer when receiving the deskew information, one address control circuit of the plurality of address control circuits being provided for each lane of the plurality of lanes, a plurality of address controllers (502, 503) each for starting writing and reading to the corresponding buffer by detecting a boundary, and constantly incrementing a write address by one after starting the writing; and a plurality of flip-flops that are provided between each of the plurality of address control circuits and the multilane control circuit, wherein each of the plurality of buffers that has received the first signal is arranged to adjust its read address, the plurality of buffers are each configured to output a difference information indicating whether a difference between a write address and a read address is larger or smaller than a predetermined value, the multilane control circuit is configured to output the first signal that does not increment the read address and a second signal, which increments the read address by two, to all the plurality of address control circuits, according to a plurality of difference information at predetermined timing after adjusting skew between lanes, the plurality of address control circuits are each configured to output the first signal and the second signal to the corresponding buffer, corresponding the lane of which skew is adjusted by the multilane control circuit, and the predetermined timing is any timing between detection of one symbol subsequent to a head symbol in a clock frequency difference compensation pattern and detection of one symbol prior to an end symbol in the clock frequency difference compensation pattern in each read data read from each of the plurality of buffers, the predetermined timing depending on a number of the plurality of flip-flops. a plurality of buffers each for storing data received through a corresponding lane, one buffer of the plurality of buffers being provided for each lane of the plurality of lanes; a multilane control circuit for detecting the skew between the lanes by detecting a deskew pattern at each buffer's read data, and for outputting, according to the detected skew, a first signal, which does not increment a read address of each of the plurality of buffers and which is for eliminating the skew between the lanes, to a plurality of address control circuits other than an address control circuit corresponding to a lane that is a last to receive the deskew pattern, and for outputting a deskew information indicating that a skew adjustment between the lanes is to be performed; the plurality of address control circuits each for transmitting the first signal to a corresponding buffer when receiving the deskew information, one address control circuit of the plurality of address control circuits being provided for each lane of the plurality of lanes, a plurality of address controllers (502, 503) each for starting writing and reading to the corresponding buffer by detecting a boundary, and constantly incrementing a write address by one after starting the writing; and a plurality of flip-flops that are provided between each of the plurality of address control circuits and the multilane control circuit, wherein each of the plurality of buffers that has received the first signal is arranged to adjust its read address, the plurality of buffers are each configured to output a difference information indicating whether a difference between a write address and a read address is larger or smaller than a predetermined value, the multilane control circuit is configured to output the first signal that does not increment the read address and a second signal, which increments the read address by two, to all the plurality of address control circuits, according to a plurality of difference information at predetermined timing after adjusting skew between lanes, the plurality of address control circuits are each configured to output the first signal and the second signal to the corresponding buffer, corresponding the lane of which skew is adjusted by the multilane control circuit, and the predetermined timing is any timing between detection of one symbol subsequent to a head symbol in a clock frequency difference compensation pattern and detection of one symbol prior to an end symbol in the clock frequency difference compensation pattern in each read data read from each of the plurality of buffers, the predetermined timing depending on a number of the plurality of flip-flops.