A method, comprising: extracting a first set of IC design features based on each training IC design of a set of training IC designs in a first stage of an IC design flow, wherein the first set of IC design features includes a count of logic stages, required times of timing paths, arrival times of timing paths, a count of fanouts, and clock arrival times, and extracting a first set of IC design labels based on each training IC design of the set of training IC designs in a second stage of the IC design flow, wherein the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow, and wherein the first set of IC design labels includes timing slacks at one or more timing endpoints; training, by a processor, a machine learning model based on the first set of IC design features and the first set of IC design labels; and when a first IC design is in the first stage of the IC design flow, extracting a second set of IC design features from the first IC design, wherein the second set of IC design features includes a count of logic stages, required times of timing paths, arrival times of timing paths, a count of fanouts, and clock arrival times, using the trained machine learning model to predict timing slack at one or more timing endpoints in the first IC design based on the second set of IC design features, and performing an optimization on the first IC design that uses the predicted timing slack at the one or more timing endpoints in the first IC design. extracting a first set of IC design features based on each training IC design of a set of training IC designs in a first stage of an IC design flow, wherein the first set of IC design features includes a count of logic stages, required times of timing paths, arrival times of timing paths, a count of fanouts, and clock arrival times, and extracting a first set of IC design labels based on each training IC design of the set of training IC designs in a second stage of the IC design flow, wherein the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow, and wherein the first set of IC design labels includes timing slacks at one or more timing endpoints; training, by a processor, a machine learning model based on the first set of IC design features and the first set of IC design labels; and when a first IC design is in the first stage of the IC design flow, extracting a second set of IC design features from the first IC design, wherein the second set of IC design features includes a count of logic stages, required times of timing paths, arrival times of timing paths, a count of fanouts, and clock arrival times, using the trained machine learning model to predict timing slack at one or more timing endpoints in the first IC design based on the second set of IC design features, and performing an optimization on the first IC design that uses the predicted timing slack at the one or more timing endpoints in the first IC design. extracting a second set of IC design features from the first IC design, wherein the second set of IC design features includes a count of logic stages, required times of timing paths, arrival times of timing paths, a count of fanouts, and clock arrival times, using the trained machine learning model to predict timing slack at one or more timing endpoints in the first IC design based on the second set of IC design features, and performing an optimization on the first IC design that uses the predicted timing slack at the one or more timing endpoints in the first IC design.