A semiconductor device, comprising: a first semiconductor structure comprising an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts; a second semiconductor structure comprising an array of dynamic random-access memory, DRAM, cells and a second bonding layer comprising a plurality of second bonding contacts; a third semiconductor structure comprising a programmable logic device and a third bonding layer comprising a plurality of third bonding contacts; a first bonding interface between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with a first set of the third bonding contacts at the first bonding interface; and a second bonding interface between the second bonding layer and the third bonding layer, the second bonding contacts being in contact with a second set of the third bonding contacts at the second bonding interface, wherein the first bonding interface and the second bonding interface are in a same plane, wherein the first semiconductor structure comprises: a first substrate; the array of NAND memory cells on the first substrate; and the first bonding layer on the array of NAND memory cells, wherein the second semiconductor structure comprises: a second substrate; the array of DRAM cells on the second substrate; and the second bonding layer on the array of DRAM cells, characterized in that the programmable logic device includes a field-programmable gate array, FPGA, and in that the third semiconductor structure of semiconductor device further includes the entirety or part of the peripheral circuits of the NAND memory in the first semiconductor structure. a first semiconductor structure comprising an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts; a second semiconductor structure comprising an array of dynamic random-access memory, DRAM, cells and a second bonding layer comprising a plurality of second bonding contacts; a third semiconductor structure comprising a programmable logic device and a third bonding layer comprising a plurality of third bonding contacts; a first bonding interface between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with a first set of the third bonding contacts at the first bonding interface; and a second bonding interface between the second bonding layer and the third bonding layer, the second bonding contacts being in contact with a second set of the third bonding contacts at the second bonding interface, wherein the first bonding interface and the second bonding interface are in a same plane, wherein the first semiconductor structure comprises: a first substrate; the array of NAND memory cells on the first substrate; and the first bonding layer on the array of NAND memory cells, a first substrate; the array of NAND memory cells on the first substrate; and the first bonding layer on the array of NAND memory cells, wherein the second semiconductor structure comprises: a second substrate; the array of DRAM cells on the second substrate; and the second bonding layer on the array of DRAM cells, characterized in that the programmable logic device includes a field-programmable gate array, FPGA, and in that the third semiconductor structure of semiconductor device further includes the entirety or part of the peripheral circuits of the NAND memory in the first semiconductor structure. a second substrate; the array of DRAM cells on the second substrate; and the second bonding layer on the array of DRAM cells, characterized in that the programmable logic device includes a field-programmable gate array, FPGA, and in that the third semiconductor structure of semiconductor device further includes the entirety or part of the peripheral circuits of the NAND memory in the first semiconductor structure.