A display module, comprising: a base including a plurality of unit portions (UNP1, UNP2, UNP3, UNP4), each of the plurality of unit portions (UNP1, UNP2, UNP3, UNP4) including an island portion and a plurality of connecting portions extending from the island portion and connecting adjacent island portions; an active pattern disposed on the base and overlapped with the island portion, the active pattern comprising a semiconductor material; a gate insulating layer disposed on the base to cover the active pattern; a gate metal pattern disposed on the gate insulating layer and overlapped with the island portion, the gate metal pattern not extending over the plurality of connecting portions; a first circuit insulating layer disposed on the base to cover at least a portion of the gate insulating layer, the first circuit insulating layer being overlapped with the island portion and the plurality of connecting portions and comprising a first contact hole defined therein; a first metal pattern disposed on the first circuit insulating layer and overlapped with the island portion; a plurality of first lines, which are disposed on the first circuit insulating layer, each of the plurality of first lines being overlapped with at least one of the plurality of connecting portions, and at least one of the plurality of first lines being electrically connected to the gate metal pattern through the first contact hole; a second circuit insulating layer disposed on the first metal pattern and the plurality of first lines; a second metal pattern disposed on the second circuit insulating layer and overlapped with the island portion; a plurality of second lines, which are disposed on the second circuit insulating layer, each of the plurality of second lines being overlapped with at least one of the plurality of connecting portions; a third circuit insulating layer disposed on the second metal pattern and the plurality of second lines; a third metal pattern disposed on the third circuit insulating layer and overlapped with the island portion; and a plurality of third lines, which are disposed on the third circuit insulating layer, each of the plurality of third lines being overlapped with at least one of the plurality of connecting portions, characterized in that at least one of the plurality of connecting portions, at least one of the plurality of first lines, at least one of the plurality of second lines, and at least one of the plurality of third lines are overlapped with each other. a base including a plurality of unit portions (UNP1, UNP2, UNP3, UNP4), each of the plurality of unit portions (UNP1, UNP2, UNP3, UNP4) including an island portion and a plurality of connecting portions extending from the island portion and connecting adjacent island portions; an active pattern disposed on the base and overlapped with the island portion, the active pattern comprising a semiconductor material; a gate insulating layer disposed on the base to cover the active pattern; a gate metal pattern disposed on the gate insulating layer and overlapped with the island portion, the gate metal pattern not extending over the plurality of connecting portions; a first circuit insulating layer disposed on the base to cover at least a portion of the gate insulating layer, the first circuit insulating layer being overlapped with the island portion and the plurality of connecting portions and comprising a first contact hole defined therein; a first metal pattern disposed on the first circuit insulating layer and overlapped with the island portion; a plurality of first lines, which are disposed on the first circuit insulating layer, each of the plurality of first lines being overlapped with at least one of the plurality of connecting portions, and at least one of the plurality of first lines being electrically connected to the gate metal pattern through the first contact hole; a second circuit insulating layer disposed on the first metal pattern and the plurality of first lines; a second metal pattern disposed on the second circuit insulating layer and overlapped with the island portion; a plurality of second lines, which are disposed on the second circuit insulating layer, each of the plurality of second lines being overlapped with at least one of the plurality of connecting portions; a third circuit insulating layer disposed on the second metal pattern and the plurality of second lines; a third metal pattern disposed on the third circuit insulating layer and overlapped with the island portion; and a plurality of third lines, which are disposed on the third circuit insulating layer, each of the plurality of third lines being overlapped with at least one of the plurality of connecting portions, characterized in that at least one of the plurality of connecting portions, at least one of the plurality of first lines, at least one of the plurality of second lines, and at least one of the plurality of third lines are overlapped with each other.