An arrangement of one or several surface mountable devices mounted on a carrier substrate, - said carrier substrate at least comprising a metallic plate or metallic core layer covered by a dielectric layer on which an electrically conductive layer is arranged, - said surface mountable semiconductor device comprising at least one semiconductor element mounted on or integrated in a device substrate, the device substrate having a top surface comprising the semiconductor element and a bottom surface having one or several electrical connection pads and at least one thermal pad at the bottom surface of the device, wherein the thermal pad is separated from the electrical pad(s) by a trench or gap, wherein said electrically conductive layer and said dielectric layer are not present or removed underneath the thermal pad of the device, and wherein said thermal pad being thermally connected by a thermal interconnect layer to the metallic plate or metallic core layer and said electrical connection pads being electrically connected by an electrical interconnect layer to the electrically conductive layer, characterized in that - the electrical connection pads have a first height and at least one thermal pad has a second height, the second height of the thermal pad being larger than the first height of the electrical connection pad(s), - a difference in height of the first height and the second height equals a sum of thicknesses of the electrically conductive layer and the dielectric layer, and - wherein the thermal interconnect layer of the thermal pad and the metallic plate or metallic core layer and the electrical interconnect layer of the electrical connection pads and the electrically conductive layer are uniform deposition layers. - said carrier substrate at least comprising a metallic plate or metallic core layer covered by a dielectric layer on which an electrically conductive layer is arranged, - said surface mountable semiconductor device comprising at least one semiconductor element mounted on or integrated in a device substrate, the device substrate having a top surface comprising the semiconductor element and a bottom surface having one or several electrical connection pads and at least one thermal pad at the bottom surface of the device, wherein the thermal pad is separated from the electrical pad(s) by a trench or gap, wherein said electrically conductive layer and said dielectric layer are not present or removed underneath the thermal pad of the device, and wherein said thermal pad being thermally connected by a thermal interconnect layer to the metallic plate or metallic core layer and said electrical connection pads being electrically connected by an electrical interconnect layer to the electrically conductive layer, - the electrical connection pads have a first height and at least one thermal pad has a second height, the second height of the thermal pad being larger than the first height of the electrical connection pad(s), - a difference in height of the first height and the second height equals a sum of thicknesses of the electrically conductive layer and the dielectric layer, and - wherein the thermal interconnect layer of the thermal pad and the metallic plate or metallic core layer and the electrical interconnect layer of the electrical connection pads and the electrically conductive layer are uniform deposition layers.