An information processing method, wherein the method is applied to a host chip that communicates with a storage chip through a universal flash storage protocol information unit, UPIU, and the method comprises: determining, by the host chip, a first logical address set; generating, by the host chip, first indication information, wherein the first indication information comprises the first logical address set and a first physical address set, wherein the first physical address set is determined based on a mapping relationship between a logical address and a physical address in the storage chip and corresponds to the first logical address set, the first physical address set comprises N physical addresses, the N physical addresses are in a one-to-one correspondence with N logical addresses comprised in the first logical address set, and N is an integer greater than or equal to 2; and sending, by the host chip, a first request to the storage chip, wherein the first request comprises the first indication information, wherein the first request is used to request first data and the first data includes data stored in the first physical address set; and the first request further comprises first control information; and the first control information comprises a first field, and the first field is used to indicate the number of N; and wherein the first control information further comprises a second field; and the second field is used to indicate any one of the following: an access granularity of each physical address in the first physical address set; or an access granularity of each logical address in the first logical address set; or a sum of an access granularity of each physical address in the first physical address set and an access granularity of each logical address in the first logical address set, wherein the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set. determining, by the host chip, a first logical address set; generating, by the host chip, first indication information, wherein the first indication information comprises the first logical address set and a first physical address set, wherein the first physical address set is determined based on a mapping relationship between a logical address and a physical address in the storage chip and corresponds to the first logical address set, the first physical address set comprises N physical addresses, the N physical addresses are in a one-to-one correspondence with N logical addresses comprised in the first logical address set, and N is an integer greater than or equal to 2; and sending, by the host chip, a first request to the storage chip, wherein the first request comprises the first indication information, wherein the first request is used to request first data and the first data includes data stored in the first physical address set; and the first request further comprises first control information; and the first control information comprises a first field, and the first field is used to indicate the number of N; and wherein the first control information further comprises a second field; and the second field is used to indicate any one of the following: an access granularity of each physical address in the first physical address set; or an access granularity of each logical address in the first logical address set; or a sum of an access granularity of each physical address in the first physical address set and an access granularity of each logical address in the first logical address set, wherein the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set. an access granularity of each physical address in the first physical address set; or an access granularity of each logical address in the first logical address set; or a sum of an access granularity of each physical address in the first physical address set and an access granularity of each logical address in the first logical address set, wherein the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.