A data processing system comprising: a universal asynchronous receive/transmit, UART, module having: a first input terminal for receiving an input clock signal (UART INPUT CLOCK); a second input terminal for receiving a receive data signal; an output terminal for providing a transmit data signal, wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter, USART, module; a baud rate generator configured to generate a baud rate based clock signal determined using the input clock signal; an RX timing and control block configured to receive the baud rate clock signal and the received data signal; a TX timing and control block configured to receive the baud rate clock signal and to generate the transmit data signal, wherein said baud rate based clock signal is used by said RX timing and control block and said TX timing and control block to respectively process the receive data signal and the transmit data signal; and a control register in the UART module having a start bit and a stop bit, and wherein disabling the start bit and the stop bit allows a synchronous USART communication mode between the UART module and the USART module; and a timer module coupled to receive the input clock signal (UART INPUT CLOCK), the timer module for providing a duplicate baud rate clock signal (DBCLK) for being communicated to the USART module, wherein the duplicate baud rate clock signal (DBCLK) is substantially the same as the baud rate based clock signal (BCLK). a universal asynchronous receive/transmit, UART, module having: a first input terminal for receiving an input clock signal (UART INPUT CLOCK); a second input terminal for receiving a receive data signal; an output terminal for providing a transmit data signal, wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter, USART, module; a baud rate generator configured to generate a baud rate based clock signal determined using the input clock signal; an RX timing and control block configured to receive the baud rate clock signal and the received data signal; a TX timing and control block configured to receive the baud rate clock signal and to generate the transmit data signal, wherein said baud rate based clock signal is used by said RX timing and control block and said TX timing and control block to respectively process the receive data signal and the transmit data signal; and a control register in the UART module having a start bit and a stop bit, and wherein disabling the start bit and the stop bit allows a synchronous USART communication mode between the UART module and the USART module; and a first input terminal for receiving an input clock signal (UART INPUT CLOCK); a second input terminal for receiving a receive data signal; an output terminal for providing a transmit data signal, wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter, USART, module; a baud rate generator configured to generate a baud rate based clock signal determined using the input clock signal; an RX timing and control block configured to receive the baud rate clock signal and the received data signal; a TX timing and control block configured to receive the baud rate clock signal and to generate the transmit data signal, wherein said baud rate based clock signal is used by said RX timing and control block and said TX timing and control block to respectively process the receive data signal and the transmit data signal; and a control register in the UART module having a start bit and a stop bit, and wherein disabling the start bit and the stop bit allows a synchronous USART communication mode between the UART module and the USART module; and a timer module coupled to receive the input clock signal (UART INPUT CLOCK), the timer module for providing a duplicate baud rate clock signal (DBCLK) for being communicated to the USART module, wherein the duplicate baud rate clock signal (DBCLK) is substantially the same as the baud rate based clock signal (BCLK).