A clock frequency supply device, comprising: a frequency tuner (110, 310) configured to receive an input signal with a carrier frequency, and tune a free running frequency of an oscillator (140, 340) based on the carrier frequency by using a first signal path, thereby minimizing a difference between the free running frequency of the oscillator (140, 340) and the carrier frequency of the input signal; an injector (120, 320, 620) configured to inject a feed signal generated from the input signal directly into the oscillator (140, 340) by using a second signal path different from the first signal path after the tuning of the free running frequency is completed; and the oscillator (140, 340) configured to generate a reference clock signal with a reference clock frequency; wherein the injector (120, 320, 620) comprises: a mode switch configured to control feeding of the feed signal to the oscillator (140, 340); and an injection controller configured to control the mode switch to not feed the feed signal before the tuning of the free running frequency is completed, and to feed the feed signal during an injection locking mode taking place after the tuning of the free runing frequency is completed, wherein during the injection locked mode: fl when a logical state of an envelope of the input signal is low, the oscillator (140, 340) is configured to be free running at its free running frequency in order to generate the reference clock signal, and when the logical state of the envelope of the input signal is high, the oscillator (140, 340) is configured to be injection locked to the carrier frequency based on the feed signal in order to generate the reference clock signal; wherein the periods during which the oscillator (140, 340) is free running are shorter than the periods during which the oscillator (140, 340) is injection locked. a frequency tuner (110, 310) configured to receive an input signal with a carrier frequency, and tune a free running frequency of an oscillator (140, 340) based on the carrier frequency by using a first signal path, thereby minimizing a difference between the free running frequency of the oscillator (140, 340) and the carrier frequency of the input signal; an injector (120, 320, 620) configured to inject a feed signal generated from the input signal directly into the oscillator (140, 340) by using a second signal path different from the first signal path after the tuning of the free running frequency is completed; and the oscillator (140, 340) configured to generate a reference clock signal with a reference clock frequency; wherein the injector (120, 320, 620) comprises: a mode switch configured to control feeding of the feed signal to the oscillator (140, 340); and an injection controller configured to control the mode switch to not feed the feed signal before the tuning of the free running frequency is completed, and to feed the feed signal during an injection locking mode taking place after the tuning of the free runing frequency is completed, a mode switch configured to control feeding of the feed signal to the oscillator (140, 340); and an injection controller configured to control the mode switch to not feed the feed signal before the tuning of the free running frequency is completed, and to feed the feed signal during an injection locking mode taking place after the tuning of the free runing frequency is completed, wherein during the injection locked mode: fl when a logical state of an envelope of the input signal is low, the oscillator (140, 340) is configured to be free running at its free running frequency in order to generate the reference clock signal, and when the logical state of the envelope of the input signal is high, the oscillator (140, 340) is configured to be injection locked to the carrier frequency based on the feed signal in order to generate the reference clock signal; wherein the periods during which the oscillator (140, 340) is free running are shorter than the periods during which the oscillator (140, 340) is injection locked. when a logical state of an envelope of the input signal is low, the oscillator (140, 340) is configured to be free running at its free running frequency in order to generate the reference clock signal, and when the logical state of the envelope of the input signal is high, the oscillator (140, 340) is configured to be injection locked to the carrier frequency based on the feed signal in order to generate the reference clock signal; wherein the periods during which the oscillator (140, 340) is free running are shorter than the periods during which the oscillator (140, 340) is injection locked.