An integrated circuit comprising: an enable pin; a ground pin; an input pin; an output (VOUT) pin; a load switch that is coupled between the input pin and the output pin, wherein the load switch receives a negative voltage through the input pin; and control circuitry (102, 104) that is coupled to the enable pin, the ground pin, and the load switch, wherein the control circuitry controls the load switch, and wherein the control circuitry uses the ground pin as a positive supply rail and the input pin as an internal ground. wherein the control circuitry further comprises: a level shifter that is coupled to the ground pin, the input pin, and the enable pin, the level shifter comprising a transistor having a first passive electrode, a second passive electrode, and a control electrode, and wherein the first passive electrode of the transistor is coupled to the enable pin; and a slew rate controller that is coupled to the level shifter, the input pin, and the load switch; and characterized in that the level shifter further comprises: a current mirror (Q2, Q3) that is coupled to the input pin; a current control circuit (R1, Q1, R2, R3) that is coupled between the ground pin and the current mirror; wherein the control electrode of the transistor is coupled to the ground pin; and an impedance network (R2, R3) that is coupled between the second passive electrode of the transistor and the current mirror and that is coupled to the slew rate controller. an enable pin; a ground pin; an input pin; an output (VOUT) pin; a load switch that is coupled between the input pin and the output pin, wherein the load switch receives a negative voltage through the input pin; and control circuitry (102, 104) that is coupled to the enable pin, the ground pin, and the load switch, wherein the control circuitry controls the load switch, and wherein the control circuitry uses the ground pin as a positive supply rail and the input pin as an internal ground. wherein the control circuitry further comprises: a level shifter that is coupled to the ground pin, the input pin, and the enable pin, the level shifter comprising a transistor having a first passive electrode, a second passive electrode, and a control electrode, and wherein the first passive electrode of the transistor is coupled to the enable pin; and a slew rate controller that is coupled to the level shifter, the input pin, and the load switch; and characterized in that the level shifter further comprises: a current mirror (Q2, Q3) that is coupled to the input pin; a current control circuit (R1, Q1, R2, R3) that is coupled between the ground pin and the current mirror; wherein the control electrode of the transistor is coupled to the ground pin; and an impedance network (R2, R3) that is coupled between the second passive electrode of the transistor and the current mirror and that is coupled to the slew rate controller. a level shifter that is coupled to the ground pin, the input pin, and the enable pin, the level shifter comprising a transistor having a first passive electrode, a second passive electrode, and a control electrode, and wherein the first passive electrode of the transistor is coupled to the enable pin; and a slew rate controller that is coupled to the level shifter, the input pin, and the load switch; and characterized in that the level shifter further comprises: a current mirror (Q2, Q3) that is coupled to the input pin; a current control circuit (R1, Q1, R2, R3) that is coupled between the ground pin and the current mirror; wherein the control electrode of the transistor is coupled to the ground pin; and an impedance network (R2, R3) that is coupled between the second passive electrode of the transistor and the current mirror and that is coupled to the slew rate controller. a current mirror (Q2, Q3) that is coupled to the input pin; a current control circuit (R1, Q1, R2, R3) that is coupled between the ground pin and the current mirror; wherein the control electrode of the transistor is coupled to the ground pin; and an impedance network (R2, R3) that is coupled between the second passive electrode of the transistor and the current mirror and that is coupled to the slew rate controller.