A memory device (100, 300, 400) comprising: a memory bank (102, 304, 406, 402, 510), wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells and wherein each memory cell is arranged to store a data word at one of a plurality of memory addresses; a first level dynamic redundancy register (104, 314, 508, 700) comprising data storage elements a second level dynamic redundancy register (106, 316, 800) comprising data storage elements; and a pipeline bank coupled to the memory bank, the first level dynamic redundancy register, and the second level dynamic redundancy register, wherein the pipeline bank is configured to: write a data word into the memory bank at a selected one of the plurality of memory addresses; verify the data word written into the memory bank to determine whether the data word was successfully written by the write; responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy register; re-write the data word stored in the first level dynamic redundancy register into the memory bank at the selected one of the plurality of memory addresses; perform verification to determine if the data word was successfully written to the memory bank responsive to the re-writing; and responsive to a determination that the data was not successfully written during the rewriting, write the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register. a memory bank (102, 304, 406, 402, 510), wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells and wherein each memory cell is arranged to store a data word at one of a plurality of memory addresses; a first level dynamic redundancy register (104, 314, 508, 700) comprising data storage elements a second level dynamic redundancy register (106, 316, 800) comprising data storage elements; and a pipeline bank coupled to the memory bank, the first level dynamic redundancy register, and the second level dynamic redundancy register, wherein the pipeline bank is configured to: write a data word into the memory bank at a selected one of the plurality of memory addresses; verify the data word written into the memory bank to determine whether the data word was successfully written by the write; responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy register; re-write the data word stored in the first level dynamic redundancy register into the memory bank at the selected one of the plurality of memory addresses; perform verification to determine if the data word was successfully written to the memory bank responsive to the re-writing; and responsive to a determination that the data was not successfully written during the rewriting, write the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register. write a data word into the memory bank at a selected one of the plurality of memory addresses; verify the data word written into the memory bank to determine whether the data word was successfully written by the write; responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy register; re-write the data word stored in the first level dynamic redundancy register into the memory bank at the selected one of the plurality of memory addresses; perform verification to determine if the data word was successfully written to the memory bank responsive to the re-writing; and responsive to a determination that the data was not successfully written during the rewriting, write the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register.