A system on a chip (104, 204, 304, 404), comprising: a data processor (114, 116, 214, 216, 314, 316, 414, 416) having a processor data word size of p x octets, wherein p is a positive integer, and configured to handle data items having a data item size which is a non-integer multiple of the processor data word size; a memory controller for a memory (106, 106'), wherein the memory controller is configured to write data to, or read data from, the memory (106, 106') as multiples of m x octets, wherein m is a positive integer; a bus over which data can be sent between the data processor and the memory controller; a data protection code generator (142, 152, 242, 252, 342, 442) configured to generate a data protection code (ECC_1, ECC_3, ECC_4) for a data item (Data_1, Data_3, Data_4) generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller, and wherein the memory controller is further configured to write at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address (702, 706, 708, 710, 712) of the memory (106, 106'); and a data protection code checker (144, 154, 244, 254, 344, 444) configured to receive a read data protection code (ECC_1, ECC_3, ECC_4) and a read data item (Data_1, Data_3, Data_4) received over the bus and to check the read data item for an error using the read data protection code, and wherein the memory controller is further configured to read at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address (702, 706, 708, 710, 712) of the memory. a data processor (114, 116, 214, 216, 314, 316, 414, 416) having a processor data word size of p x octets, wherein p is a positive integer, and configured to handle data items having a data item size which is a non-integer multiple of the processor data word size; a memory controller for a memory (106, 106'), wherein the memory controller is configured to write data to, or read data from, the memory (106, 106') as multiples of m x octets, wherein m is a positive integer; a bus over which data can be sent between the data processor and the memory controller; a data protection code generator (142, 152, 242, 252, 342, 442) configured to generate a data protection code (ECC_1, ECC_3, ECC_4) for a data item (Data_1, Data_3, Data_4) generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller, and wherein the memory controller is further configured to write at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address (702, 706, 708, 710, 712) of the memory (106, 106'); and a data protection code checker (144, 154, 244, 254, 344, 444) configured to receive a read data protection code (ECC_1, ECC_3, ECC_4) and a read data item (Data_1, Data_3, Data_4) received over the bus and to check the read data item for an error using the read data protection code, and wherein the memory controller is further configured to read at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address (702, 706, 708, 710, 712) of the memory.