A chopping switch time-skew calibration circuit, comprising: a plurality of first circuits, each of the first circuits configured to receive a digital input (dout) from a respective channel of a time-interleaved analog to digital converter,ADC, and each including: a delay circuit configured to generate a delayed version of a respective digital input; a delay subtractor configured to subtract the delayed version from the respective digital input; an absolute value circuit coupled to an output of the delay subtractor configured to output an absolute value of the difference between the inputs; a first accumulator configured to receive a first version of the absolute value and a second accumulator configured to receive a second version of the absolute value, the receiving accumulator determined by a value of a chopping signal; an average circuit coupled to the respective outputs of the first and second accumulators of the plurality of first circuits, configured to average accumulator output across the plurality of first circuits, and a plurality of second circuits each respectively coupled to a corresponding first circuits, and each including: a first adder coupled to outputs of the first accumulator and the second accumulator; a first subtractor coupled to the outputs of the first accumulator and the second accumulator; and a decision circuit configured to combine a difference between an output of the first adder and an output of the average circuit, with an output of the first subtractor, to generate a common mode output and a differential output. a plurality of first circuits, each of the first circuits configured to receive a digital input (dout) from a respective channel of a time-interleaved analog to digital converter,ADC, and each including: a delay circuit configured to generate a delayed version of a respective digital input; a delay subtractor configured to subtract the delayed version from the respective digital input; an absolute value circuit coupled to an output of the delay subtractor configured to output an absolute value of the difference between the inputs; a first accumulator configured to receive a first version of the absolute value and a second accumulator configured to receive a second version of the absolute value, the receiving accumulator determined by a value of a chopping signal; a delay circuit configured to generate a delayed version of a respective digital input; a delay subtractor configured to subtract the delayed version from the respective digital input; an absolute value circuit coupled to an output of the delay subtractor configured to output an absolute value of the difference between the inputs; a first accumulator configured to receive a first version of the absolute value and a second accumulator configured to receive a second version of the absolute value, the receiving accumulator determined by a value of a chopping signal; an average circuit coupled to the respective outputs of the first and second accumulators of the plurality of first circuits, configured to average accumulator output across the plurality of first circuits, and a plurality of second circuits each respectively coupled to a corresponding first circuits, and each including: a first adder coupled to outputs of the first accumulator and the second accumulator; a first subtractor coupled to the outputs of the first accumulator and the second accumulator; and a decision circuit configured to combine a difference between an output of the first adder and an output of the average circuit, with an output of the first subtractor, to generate a common mode output and a differential output. a first adder coupled to outputs of the first accumulator and the second accumulator; a first subtractor coupled to the outputs of the first accumulator and the second accumulator; and a decision circuit configured to combine a difference between an output of the first adder and an output of the average circuit, with an output of the first subtractor, to generate a common mode output and a differential output.