A memory array, comprising: a plurality of memory cells (odd1-odd4, even1-even4), wherein each of the memory cells comprises: a first switch device, having: a control terminal coupled to a column select line (SLe, SLo), wherein the first switch device is controlled by the column select line (SLe, SLo) to be turned-on or turned-off; a first terminal, coupled to a bit line (BL1-BL4); and a second terminal; a second switch device, having: a first terminal, coupled to the second terminal of the first switch device; a control terminal coupled to a word line (WL1, WL2) wherein the second switch device is controlled by the word line (WL1, WL2) to be turned-on or turned-off; and a second terminal; and a capacitor, having a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein data is read from the capacitor or written to the capacitor via the bit line (BL1-BL4); the memory array characterized in that the bit line (BL1-BL4) is parallel with the column select line (SLe, SLo); and the word line (WL1, WL2) is orthogonal to the bit line (BL1-BL4) and the column select line (SLe, SLo). a plurality of memory cells (odd1-odd4, even1-even4), wherein each of the memory cells comprises: a first switch device, having: a control terminal coupled to a column select line (SLe, SLo), wherein the first switch device is controlled by the column select line (SLe, SLo) to be turned-on or turned-off; a first terminal, coupled to a bit line (BL1-BL4); and a second terminal; a second switch device, having: a first terminal, coupled to the second terminal of the first switch device; a control terminal coupled to a word line (WL1, WL2) wherein the second switch device is controlled by the word line (WL1, WL2) to be turned-on or turned-off; and a second terminal; and a capacitor, having a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein data is read from the capacitor or written to the capacitor via the bit line (BL1-BL4); a first switch device, having: a control terminal coupled to a column select line (SLe, SLo), wherein the first switch device is controlled by the column select line (SLe, SLo) to be turned-on or turned-off; a first terminal, coupled to a bit line (BL1-BL4); and a second terminal; a control terminal coupled to a column select line (SLe, SLo), wherein the first switch device is controlled by the column select line (SLe, SLo) to be turned-on or turned-off; a first terminal, coupled to a bit line (BL1-BL4); and a second terminal; a second switch device, having: a first terminal, coupled to the second terminal of the first switch device; a control terminal coupled to a word line (WL1, WL2) wherein the second switch device is controlled by the word line (WL1, WL2) to be turned-on or turned-off; and a second terminal; and a first terminal, coupled to the second terminal of the first switch device; a control terminal coupled to a word line (WL1, WL2) wherein the second switch device is controlled by the word line (WL1, WL2) to be turned-on or turned-off; and a second terminal; and a capacitor, having a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein data is read from the capacitor or written to the capacitor via the bit line (BL1-BL4);