A data memory including variable resistive memory elements arranged in a three-dimensional pattern defined by rectangular coordinates along x, y and z-directions and with a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate, the memory further comprising: a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction; a plurality of second conductive lines elongated in the x-direction across each of the plurality of planes and spaced apart in the y-direction between and separated from the plurality of first conductive lines in each of the plurality of planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the plurality of planes; a plurality of variable resistive non-volatile re-programmable memory elements, each memory element being connected between a corresponding first conductive line and a corresponding second conductive line crossing adjacent each other at an associated location of the plurality of locations with memory elements being connected to respective rows of first conductive lines on both sides of each second conductive line and each memory element storing at least one bit of data, wherein each pair of memory elements located adjacent in the same plane and having in between a corresponding second conductive line to which they are connected to are independently programmable; and wherein: said plurality of first conductive lines have odd (LBL 11, LBL21, LBL31,...; LBL13, LBL23, LBL33,...;...) and even (LBL12, LBL22, LBL32,...; LBL14, LBL24, LBL34,...;...) rows spaced apart in the y-direction; the memory further comprises: a first set of third conductive lines (GBL1A, GBL2A, GBL3A,...) switchably connected to an odd row of first conductive lines (LBL11, LBL21, LBL31,...); and a second set of third conductive lines (GBL1B, GBL2B, GBL3B,...) switchably connected to an even row of first conductive lines (LBL12, LBL22, LBL32,...), the odd row is adjacent to the even row; and the data memory is configured to connect a selected one of said odd row and even row of first conductive lines to respective sense amplifiers for reading via a corresponding set of said first and second sets of third conductive lines and to connect the other one of said odd row and even row of first conductive lines to a reference voltage source via a corresponding complement set of said first and second sets of third conductive lines, such that the first conductive lines of said odd row and even row are at a same reference voltage level. a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction; a plurality of second conductive lines elongated in the x-direction across each of the plurality of planes and spaced apart in the y-direction between and separated from the plurality of first conductive lines in each of the plurality of planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the plurality of planes; a plurality of variable resistive non-volatile re-programmable memory elements, each memory element being connected between a corresponding first conductive line and a corresponding second conductive line crossing adjacent each other at an associated location of the plurality of locations with memory elements being connected to respective rows of first conductive lines on both sides of each second conductive line and each memory element storing at least one bit of data, wherein each pair of memory elements located adjacent in the same plane and having in between a corresponding second conductive line to which they are connected to are independently programmable; and wherein: said plurality of first conductive lines have odd (LBL 11, LBL21, LBL31,...; LBL13, LBL23, LBL33,...;...) and even (LBL12, LBL22, LBL32,...; LBL14, LBL24, LBL34,...;...) rows spaced apart in the y-direction; said plurality of first conductive lines have odd (LBL 11, LBL21, LBL31,...; LBL13, LBL23, LBL33,...;...) and even (LBL12, LBL22, LBL32,...; LBL14, LBL24, LBL34,...;...) rows spaced apart in the y-direction; a first set of third conductive lines (GBL1A, GBL2A, GBL3A,...) switchably connected to an odd row of first conductive lines (LBL11, LBL21, LBL31,...); and a second set of third conductive lines (GBL1B, GBL2B, GBL3B,...) switchably connected to an even row of first conductive lines (LBL12, LBL22, LBL32,...),