A switched capacitor converter comprising: a first summer; a second summer; a quantizer; at least one integrator (115,125), the first summer, the quantizer, and the at least one integrator being configured as a chopper-stabilized sigma-delta modulator; wherein the at least one integrator comprises a first integrator and a second integrator, the first integrator being coupled to the first summer to receive output of the first summer, the second integrator being coupled to the second summer to provide an input to the second summer, wherein the first integrator is configured with chopper stabilization, and the second integrator is configured without chopper stabilization; a feedforward amplifier in a feedforward path between the first integrator and the second summer; a feedback digital-to-analog converter in a feedback path from the quantizer to the first summer; a clock generator module configured to generate a first phase of a sampling clock ((Φ 1), the first phase of the sampling clock is for the first and the second integrator sampling their input signals, a second phase of the sampling clock (Φ 2), the second phase of the sampling clock is for the first and the second integrator integrating the sampled input signals, wherein the second integrator samples the output signal of the first integrator in a subsequent first phase of the sampling clock, a first phase of a chopping clock, and a second phase of the chopping clock, the first and second phases of the sampling clock being non-overlapping, the first and second phases of the chopping clock being non-overlapping, the clock generator module being configured to cause transitions from active to inactive of the first and second phases of the chopping clock when the first phase and the second phase of the sampling clock are inactive (405,420), wherein the clock generator module is further configured to cause transitions from inactive to active of the first and second phases of the chopping clock when the first phase and the second phase of the sampling clock are inactive (410,425), and wherein the clock generator module is further configured to cause at least one transition from inactive to active of the second phase of the sampling clock in response to inactive to active transitions of the first phase of the chopping clock, and to cause at least one transition from inactive to active of the second phase of the sampling clock in response to inactive to active transitions of the second phase of the chopping clock; and wherein the clock generator module comprises an asynchronous state machine for controlling clock transitions. a first summer; a second summer; a quantizer; at least one integrator (115,125), the first summer, the quantizer, and the at least one integrator being configured as a chopper-stabilized sigma-delta modulator; wherein the at least one integrator comprises a first integrator and a second integrator, the first integrator being coupled to the first summer to receive output of the first summer, the second integrator being coupled to the second summer to provide an input to the second summer, wherein the first integrator is configured with chopper stabilization, and the second integrator is configured without chopper stabilization; a feedforward amplifier in a feedforward path between the first integrator and the second summer; a feedback digital-to-analog converter in a feedback path from the quantizer to the first summer; a clock generator module configured to generate a first phase of a sampling clock ((Φ 1), the first phase of the sampling clock is for the first and the second integrator sampling their input signals, a second phase of the sampling clock (Φ 2), the second phase of the sampling clock is for the first and the second integrator integrating the sampled input signals, wherein the second integrator samples the output signal of the first integrator in a subsequent first phase of the sampling clock, a first phase of a chopping clock, and a second phase of the chopping clock, the first and second phases of the sampling clock being non-overlapping, the first and second phases of the chopping clock being non-overlapping, the clock generator module being configured to cause transitions from active to inactive of the first and second phases of the chopping clock when the first phase and the second phase of the sampling clock are inactive (405,420), wherein the clock generator module is further configured to cause transitions from inactive to active of the first and second phases of the chopping clock when the first phase and the second phase of the sampling clock are inactive (410,425), and wherein the clock generator module is further configured to cause at least one transition from inactive to active of the second phase of the sampling clock in response to inactive to active transitions of the first phase of the chopping clock, and to cause at least one transition from inactive to active of the second phase of the sampling clock in response to inactive to active transitions of the second phase of the chopping clock; and wherein the clock generator module comprises an asynchronous state machine for controlling clock transitions.