A chip that includes: a branch target computation unit (116; 215) having a branch target computation unit output line, wherein the branch target computation unit is operable to detect and indicate a carry over at a particular bit position in computing a branch target, wherein the carry over at the particular bit position corresponds to a page boundary crossing event and wherein the branch target computation unit is operable to provide a first page boundary crossing event signal on the branch target computation unit output line indicating whether a page boundary crossing event is detected; a branch misprediction and exception line for providing a branch misprediction indication signal or an exception indication signal; a sequential fetch computation unit (113; 213) having a sequential fetch computation unit output line, wherein the sequential fetch computation unit is operable to provide a second page boundary crossing event signal on the sequential fetch computation unit output line where the sequential fetch computation unit detects a page boundary crossing event; a select unit (103; 203) having a select output line for providing a select signal; a multiplexing unit (111; 205) connected to the branch target computation unit output line, to the branch misprediction line, to the sequential fetch computation unit output line and to the select unit output line and having a multiplexing unit output line, the multiplexing unit being operable to pass a signal from one of the branch target computation unit output line, the branch misprediction line and the sequential fetch computation unit output line to the multiplexing unit output line according to the select signal on the select unit output line; an address translation buffer (101;201) connected to the multiplexing unit output line, wherein the address translation buffer is operable to condition translation of address representations of instruction instances where a signal on the multiplexing unit output line indicates a page boundary crossing event during execution of a stream of instruction instances and to bypass address translation where a signal on the multiplexing unit output line indicates a page boundary crossing event does not occur, wherein a page boundary crossing event comprises any one of an exception, a branch mis-prediction, a linear page boundary crossing, and a non-linear page boundary crossing. a branch target computation unit (116; 215) having a branch target computation unit output line, wherein the branch target computation unit is operable to detect and indicate a carry over at a particular bit position in computing a branch target, wherein the carry over at the particular bit position corresponds to a page boundary crossing event and wherein the branch target computation unit is operable to provide a first page boundary crossing event signal on the branch target computation unit output line indicating whether a page boundary crossing event is detected; a branch misprediction and exception line for providing a branch misprediction indication signal or an exception indication signal; a sequential fetch computation unit (113; 213) having a sequential fetch computation unit output line, wherein the sequential fetch computation unit is operable to provide a second page boundary crossing event signal on the sequential fetch computation unit output line where the sequential fetch computation unit detects a page boundary crossing event; a select unit (103; 203) having a select output line for providing a select signal; a multiplexing unit (111; 205) connected to the branch target computation unit output line, to the branch misprediction line, to the sequential fetch computation unit output line and to the select unit output line and having a multiplexing unit output line, the multiplexing unit being operable to pass a signal from one of the branch target computation unit output line, the branch misprediction line and the sequential fetch computation unit output line to the multiplexing unit output line according to the select signal on the select unit output line; an address translation buffer (101;201) connected to the multiplexing unit output line, wherein the address translation buffer is operable to condition translation of address representations of instruction instances where a signal on the multiplexing unit output line indicates a page boundary crossing event during execution of a stream of instruction instances and to bypass address translation where a signal on the multiplexing unit output line indicates a page boundary crossing event does not occur, wherein a page boundary crossing event comprises any one of an exception, a branch mis-prediction, a linear page boundary crossing, and a non-linear page boundary crossing.