A circuit arrangement for resistance measurement of at least one resistor (RM1A, RM1B, RM2A, RM2B, RM3A, RM3B, RM3C, RM4A, RM4B, RM4C, RM4D, RM5A, RM5B), the circuit arrangement comprising a capacitor (C1, C2, C3, C4, C5) coupled between a first potential node and a second potential node, a first pair of terminals (10, 20, 30, 40) and second pair of terminals (10, 20, 30, 40), each of the first and second pairs comprises a first terminal (11, 21, 31, 41) and a second terminal (12, 22, 32, 43), the first and second terminals (11, 12, 21, 22, 31, 32, 41, 42) being coupleable to one of the at least two resistors (RM1A, RM1B, RM2A, RM2B, RM3A, RM3B, RM3C, RM4A, RM4B, RM4C, RM4D, RM5A, RM5B), a first set of circuit branches and a second set of circuit branches, each of the first and second sets comprising a first circuit branch (101, 201, 301, 401) that comprises a switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H), a second circuit branch (102, 202, 302, 402) that comprises a switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H), a third circuit branch (103, 203, 303, 403) that comprises a switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H), and a fourth circuit branch (104, 204, 304, 404) that comprises a switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H), the switches (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H) being switchable between a conductive state and an insulating state, the first terminal (11, 21, 31, 41) of the first pair being coupled to the first potential node via the first circuit branch (101, 201, 301, 401) and the second circuit branch (102, 202, 302, 402) of the first set, the first and second circuit branches (101, 102, 201, 202, 301, 302, 401, 402) of the first set being connected in parallel, the second terminal (12, 22, 32, 42) of the first pair being coupled to the second potential node via the third circuit branch (103, 203, 303, 403) and the fourth circuit branch (104, 204 304, 404) of the first set, the third and fourth circuit branches (103, 104, 203, 204, 303, 304, 403, 404) of the first set being connected in parallel the first terminal (11, 21, 31, 41) of the second pair being coupled to the first potential node via the first circuit branch (101, 201, 301, 401) and the second circuit branch (102, 202, 302, 402) of the second set, the first and second circuit branches (101, 102, 201, 202, 301, 302, 401, 402) of the second set being connected in parallel, the second terminal (12, 22, 32, 42) of the second pair being coupled to the second potential node via the third circuit branch (103, 203, 303, 403) and the fourth circuit branch (104, 204 304, 404) of the second set, the third and fourth circuit branches (103, 104, 203, 204, 303, 304, 403, 404) of the second set being connected in parallel, wherein the first terminals (11, 21) of the first and second pairs are connected by a direct conductive connection, and the first circuit branches (101, 201) of the first and second sets comprise the same switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H) and the second circuit branches (102, 202) of the first and second sets comprise the same switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H), or wherein the second terminals (12, 22) of the first and second pairs are connected by a direct conductive connection, and the third circuit branches (103, 203) of the first and second sets comprise the same switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H) and the fourth circuit branches (104, 204) of the first and second sets comprise the same switch (S1A...S1H, S2A...S2H, S3A...S3M, S4A...S4W, S5A...S5H).