A single photon counting pixel detector chip, comprising: a) a layer of photosensitive material; b) an N x M array of photo-detector diodes arranged in said layer of photosensitive material; each of said photo-detector diodes having a diode output interface; c) a N x M array of readout unit cells, one readout unit cell for each photo-detector diode; d) said readout unit cell comprising: d1) an input interface connected to said diode output interface, a high-gain charge to voltage amplifying means and a pixel counter being connected to an output of the high-gain charge to voltage amplifying means, characterized in that d2) said pixel counter being split into a number of nibble counters (4a to 4c), said nibble counters (4a to 4c) having a predetermined number of bits wherein for each bit a basic counter cell is provided; said basic counter cell comprising a counting element (T Flip-Flop), a switch, a temporary storage element (C store) and an output stage, wherein the nibble counters (4a to 4c) are chained and controlled to form a pixel counter having a depth depending on the number of chained nibble counters (4a to 4c) and wherein an overflow logic receives as an input a chip mode (Mode) defining the number of chained nibble counters (4a to 4c) and the state of the nibble counters (4a to 4c) indicating whether the dynamic range of the pixel counter is exceeded; e) a side shift register to read out a selectable row of nibble counters (4a to 4c) wherein a predetermined number of rows of nibble counters is selectable and wherein the data stored in the temporary storage elements on a selected row of nibble counters are sent on a parallel bus as currents and are transformed in digital levels by parallel bus receivers. a) a layer of photosensitive material; b) an N x M array of photo-detector diodes arranged in said layer of photosensitive material; each of said photo-detector diodes having a diode output interface; c) a N x M array of readout unit cells, one readout unit cell for each photo-detector diode; d) said readout unit cell comprising: d1) an input interface connected to said diode output interface, a high-gain charge to voltage amplifying means and a pixel counter being connected to an output of the high-gain charge to voltage amplifying means, characterized in that d2) said pixel counter being split into a number of nibble counters (4a to 4c), said nibble counters (4a to 4c) having a predetermined number of bits wherein for each bit a basic counter cell is provided; said basic counter cell comprising a counting element (T Flip-Flop), a switch, a temporary storage element (C store) and an output stage, wherein the nibble counters (4a to 4c) are chained and controlled to form a pixel counter having a depth depending on the number of chained nibble counters (4a to 4c) and wherein an overflow logic receives as an input a chip mode (Mode) defining the number of chained nibble counters (4a to 4c) and the state of the nibble counters (4a to 4c) indicating whether the dynamic range of the pixel counter is exceeded; d1) an input interface connected to said diode output interface, a high-gain charge to voltage amplifying means and a pixel counter being connected to an output of the high-gain charge to voltage amplifying means, characterized in that d2) said pixel counter being split into a number of nibble counters (4a to 4c), said nibble counters (4a to 4c) having a predetermined number of bits wherein for each bit a basic counter cell is provided; said basic counter cell comprising a counting element (T Flip-Flop), a switch, a temporary storage element (C store) and an output stage, wherein the nibble counters (4a to 4c) are chained and controlled to form a pixel counter having a depth depending on the number of chained nibble counters (4a to 4c) and wherein an overflow logic receives as an input a chip mode (Mode) defining the number of chained nibble counters (4a to 4c) and the state of the nibble counters (4a to 4c) indicating whether the dynamic range of the pixel counter is exceeded; e) a side shift register to read out a selectable row of nibble counters (4a to 4c) wherein a predetermined number of rows of nibble counters is selectable and wherein the data stored in the temporary storage elements on a selected row of nibble counters are sent on a parallel bus as currents and are transformed in digital levels by parallel bus receivers.