A display panel comprising: a plurality of data lines configured to deliver data voltages (VDATA); a plurality of gate lines configured to deliver scanning signals (SCAN); a plurality of subpixels defined by the plurality of data lines and the plurality of gate lines; a plurality of power supply voltage lines configured to deliver a power voltage (ELVDD); two or more gate clock signal lines configured to deliver two or more gate clock signals (GLCK) having different phases, each of the gate clock signals (GCLK) including a plurality of pulses including a first pulse and a second pulse following the first pulse, wherein a pulse width of the second pulse is shorter than a pulse width of the first pulse; and a gate driver circuit, configured to generate scanning signals (SCAN) using the two or more gate clock signals (GLCK) having different phases and to transfer the scanning signals (SCAN) to the plurality of gate lines, wherein the first pulse corresponds to a first horizontal line in the display panel, and the second pulse corresponds to a second horizontal line in the display panel, the second horizontal line being located farther from a power supply voltage position (Pin) than the first horizontal line such that a path on which the power voltage (ELVDD) is delivered to a second subpixel, among the plurality of subpixels, disposed on the second horizontal line, is longer than a path on which the power voltage (ELVDD) is delivered to a first subpixel, among the plurality of subpixels, disposed on the first horizontal line; wherein each of the plurality of subpixels comprises: an organic light-emitting diode (OLED); a driving transistor configured to drive the organic light-emitting diode (OLED), the driving transistor comprising a first node connected to receive the power voltage (ELVDD), a second node corresponding to a gate node, and a third node electrically connected to the organic light-emitting diode (OLED); a first transistor electrically connected between the first node of the driving transistor and a data line among the plurality of data lines; a second transistor (SAMT) electrically connected between the second node and the third node of the driving transistor; and a capacitor electrically connected between the first node and the second node of the driving transistor; wherein the scanning signals (SCAN) are employed to, during a threshold voltage (V th) sampling period, control the ON time of the second transistor (SAMT) leading to a different voltage stored across the capacitor of the first subpixel and of the second subpixel at the end of the threshold voltage (V th) sampling period. a plurality of data lines configured to deliver data voltages (VDATA); a plurality of gate lines configured to deliver scanning signals (SCAN); a plurality of subpixels defined by the plurality of data lines and the plurality of gate lines; a plurality of power supply voltage lines configured to deliver a power voltage (ELVDD); two or more gate clock signal lines configured to deliver two or more gate clock signals (GLCK) having different phases, each of the gate clock signals (GCLK) including a plurality of pulses including a first pulse and a second pulse following the first pulse, wherein a pulse width of the second pulse is shorter than a pulse width of the first pulse; and a gate driver circuit, configured to generate scanning signals (SCAN) using the two or more gate clock signals (GLCK) having different phases and to transfer the scanning signals (SCAN) to the plurality of gate lines, wherein the first pulse corresponds to a first horizontal line in the display panel, and the second pulse corresponds to a second horizontal line in the display panel, the second horizontal line being located farther from a power supply voltage position (Pin) than the first horizontal line such that a path on which the power voltage (ELVDD) is delivered to a second subpixel, among the plurality of subpixels, disposed on the second horizontal line, is longer than a path on which the power voltage (ELVDD) is delivered to a first subpixel, among the plurality of subpixels, disposed on the first horizontal line; an organic light-emitting diode (OLED); a driving transistor configured to drive the organic light-emitting diode (OLED), the driving transistor comprising a first node connected to receive the power voltage (ELVDD), a second node corresponding to a gate node, and a third node electrically connected to the organic light-emitting diode (OLED); a first transistor electrically connected between the first node of the driving transistor and a data line among the plurality of data lines; a second transistor (SAMT) electrically connected between the second node and the third node of the driving transistor; and a capacitor electrically connected between the first node and the second node of the driving transistor;