A storage system which controls data transfers between a host and storage areas, comprising: a first controller with a first processor and a first memory; and a second controller with a second processor and a second memory; and a bus which connects the first and second processors (101a, 101b), wherein data stored in a shared area in the first memory and a shared area in the second memory is to be used by the first processor and the second processor, wherein the first processor is configured to: receive an I/O request comprising request information from the host; determine whether the request information requests the second processor to access the shared area in the second memory; transmit request information which is to be processed by the second processor to the second processor, wherein the second processor processes the request information and sends back a response to the first processor, wherein when the first processor determines that the request information for accessing the shared area in the second memory is to be prioritized, the first processor is configured to transmit the request information indicating its priority to the second processor, and wait for a response from the second processor before processing a next process, wherein when the first processor determines that the request information for requesting data transmission is not to be prioritized, the first processor is configured to send the request information not indicating its priority to the second processor, and process the next process without waiting for the response from the second processor, wherein the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized, and prioritizes a processing of the request information with priority over the request information without the priority. a first controller with a first processor and a first memory; and a second controller with a second processor and a second memory; and a bus which connects the first and second processors (101a, 101b), wherein data stored in a shared area in the first memory and a shared area in the second memory is to be used by the first processor and the second processor, wherein the first processor is configured to: receive an I/O request comprising request information from the host; determine whether the request information requests the second processor to access the shared area in the second memory; transmit request information which is to be processed by the second processor to the second processor, wherein the second processor processes the request information and sends back a response to the first processor, wherein when the first processor determines that the request information for accessing the shared area in the second memory is to be prioritized, the first processor is configured to transmit the request information indicating its priority to the second processor, and wait for a response from the second processor before processing a next process, wherein when the first processor determines that the request information for requesting data transmission is not to be prioritized, the first processor is configured to send the request information not indicating its priority to the second processor, and process the next process without waiting for the response from the second processor, wherein the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized, and prioritizes a processing of the request information with priority over the request information without the priority. receive an I/O request comprising request information from the host; determine whether the request information requests the second processor to access the shared area in the second memory; transmit request information which is to be processed by the second processor to the second processor, wherein the second processor processes the request information and sends back a response to the first processor, wherein when the first processor determines that the request information for accessing the shared area in the second memory is to be prioritized, the first processor is configured to transmit the request information indicating its priority to the second processor, and wait for a response from the second processor before processing a next process, wherein when the first processor determines that the request information for requesting data transmission is not to be prioritized, the first processor is configured to send the request information not indicating its priority to the second processor, and process the next process without waiting for the response from the second processor, wherein the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized, and prioritizes a processing of the request information with priority over the request information without the priority.