An apparatus comprising an upper level apparatus and a wireless LAN apparatus, the wireless LAN apparatus comprising: a module group section (1000D; 500D; 600D) that is connected to an upper level CPU (1; 91) of the upper level apparatus; an RF processing part (41; 94) that is connected to the module group section (11000D; 500D; 600D); the upper level CPU (1; 91) comprising a power reduction instruction dispatching section (1000A; 500A; 600A) for dispatching a power reduction instruction; either the upper level CPU (1; 91) or the wireless LAN apparatus further comprising: a power reduction instruction receiving section (1000B; 500B; 600B) for receiving the power reduction instruction dispatched from the power reduction instruction dispatching section (1000A; 500A; 600A) and a power reduction sequence controlling section (1000C; 500C; 600C) for controlling power of the module group section (1000D; 500D; 600D) in a predetermined order in accordance with the power reduction instruction dispatched by the power reduction instruction dispatching section (1000A; 500A; 600A); characterized in that the module group section (1000D; 500D; 600D) is an IC chip and comprises a MAC processing part (23; 92) for conducting media access control, a BB processing part (24; 93) for processing base band signals, and an oscillator (3, 5, 95) for supplying an oscillator clock signal; and in that said power reduction sequence controlling section (1000C; 500C; 600C) is configured to reduce the power of the MAC processing part (23; 92), the BB processing part (24; 93) and the oscillator (3; 5; 95) in the order: the MAC processing part (23; 92), the BB processing part (24; 93), the oscillator (3; 5; 95) and to maintain the RF processing part (41; 94) still operable to receive wireless signals. a module group section (1000D; 500D; 600D) that is connected to an upper level CPU (1; 91) of the upper level apparatus; an RF processing part (41; 94) that is connected to the module group section (11000D; 500D; 600D); the upper level CPU (1; 91) comprising a power reduction instruction dispatching section (1000A; 500A; 600A) for dispatching a power reduction instruction; either the upper level CPU (1; 91) or the wireless LAN apparatus further comprising: a power reduction instruction receiving section (1000B; 500B; 600B) for receiving the power reduction instruction dispatched from the power reduction instruction dispatching section (1000A; 500A; 600A) and a power reduction sequence controlling section (1000C; 500C; 600C) for controlling power of the module group section (1000D; 500D; 600D) in a predetermined order in accordance with the power reduction instruction dispatched by the power reduction instruction dispatching section (1000A; 500A; 600A); characterized in that the module group section (1000D; 500D; 600D) is an IC chip and comprises a MAC processing part (23; 92) for conducting media access control, a BB processing part (24; 93) for processing base band signals, and an oscillator (3, 5, 95) for supplying an oscillator clock signal; and in that said power reduction sequence controlling section (1000C; 500C; 600C) is configured to reduce the power of the MAC processing part (23; 92), the BB processing part (24; 93) and the oscillator (3; 5; 95) in the order: the MAC processing part (23; 92), the BB processing part (24; 93), the oscillator (3; 5; 95) and to maintain the RF processing part (41; 94) still operable to receive wireless signals.