A computer (CALC) for executing a computation algorithm involving a digital variable (w) in accordance with at least two operating phases, the first operating phase comprising a plurality of iterations of a first operation for using the digital variable and an operation for updating the digital variable; the second operating phase comprising a second operation for using the digital variable; with each digital variable being divided into a first binary sub-word (w ox) made up of the most significant bits of the variable and a second binary sub-word (w Fe) made up of the least significant bits of the variable, the computer (CALC) comprising: - a memory stage (MEM_POIDS) comprising: ∘ a first set of memories (MEM_1) for storing the first sub-word (w ox) of each digital variable (w), with each memory of said first set (MEM_1) being non-volatile and having a first read endurance and a first write cyclability; ∘ a second set of memories (MEM _2) for storing the second sub-word (w Fe) of each digital variable (w), with each memory of said second set having a second read endurance and a second write cyclability; - a variable processing circuit configured to generate, for each digital variable (w), at least one approximated operational variable (w op1, w op2, w op3) of the digital variable based on the first and the second sub-word (w ox, w Fe) according to the selected operating phase; - a computation network for implementing computation operations having the at least one operational variable (w op1, w op2, w op3) as an operand according to the selected operating phase; with the first read endurance being greater than the second read endurance and the first write cyclability being less than the second write cyclability. the first operating phase comprising a plurality of iterations of a first operation for using the digital variable and an operation for updating the digital variable; the second operating phase comprising a second operation for using the digital variable; with each digital variable being divided into a first binary sub-word (w ox) made up of the most significant bits of the variable and a second binary sub-word (w Fe) made up of the least significant bits of the variable, the computer (CALC) comprising: - a memory stage (MEM_POIDS) comprising: ∘ a first set of memories (MEM_1) for storing the first sub-word (w ox) of each digital variable (w), with each memory of said first set (MEM_1) being non-volatile and having a first read endurance and a first write cyclability; ∘ a second set of memories (MEM _2) for storing the second sub-word (w Fe) of each digital variable (w), with each memory of said second set having a second read endurance and a second write cyclability; - a variable processing circuit configured to generate, for each digital variable (w), at least one approximated operational variable (w op1, w op2, w op3) of the digital variable based on the first and the second sub-word (w ox, w Fe) according to the selected operating phase; - a computation network for implementing computation operations having the at least one operational variable (w op1, w op2, w op3) as an operand according to the selected operating phase; - a memory stage (MEM_POIDS) comprising: ∘ a first set of memories (MEM_1) for storing the first sub-word (w ox) of each digital variable (w), with each memory of said first set (MEM_1) being non-volatile and having a first read endurance and a first write cyclability; ∘ a second set of memories (MEM _2) for storing the second sub-word (w Fe) of each digital variable (w), with each memory of said second set having a second read endurance and a second write cyclability; ∘ a first set of memories (MEM_1) for storing the first sub-word (w ox) of each digital variable (w), with each memory of said first set (MEM_1) being non-volatile and having a first read endurance and a first write cyclability; ∘ a second set of memories (MEM _2) for storing the second sub-word (w Fe) of each digital variable (w), with each memory of said second set having a second read endurance and a second write cyclability; - a variable processing circuit configured to generate, for each digital variable (w), at least one approximated operational variable (w op1, w op2, w op3) of the digital variable based on the first and the second sub-word (w ox, w Fe) according to the selected operating phase; - a computation network for implementing computation operations having the at least one operational variable (w op1, w op2, w op3) as an operand according to the selected operating phase; with the first read endurance being greater than the second read endurance and the first write cyclability being less than the second write cyclability.