A data storage circuit comprising: - a matrix of memory cells such that each memory cell (CM ij) comprises: • an elementary storage component of ferroelectric type with variable electric bias and having a first electrode and a second electrode; • a first input/output node connected to the second electrode; a second input/output node; a selection node; • a selection transistor having a gate connected to the selection node and linking the first electrode to the second input/output node; wherein each memory cell can have a first ("0") or a second ("1") logic state corresponding respectively to different levels of charges stored in the associated elementary storage component; - a read circuit associated with at least one memory cell, comprising: • a capacitive transimpedance amplifier stage configured to read a piece of data stored in a memory cell (CM ij) selected via the switching-on of the corresponding selection transistor by applying a selection signal to the selection node; said capacitive transimpedance amplifier stage comprising: ∘ an operational amplifier having: a first input (e1_ao) connected to the second input/output node of the associated memory cell, a second input (e2_ao) for receiving a first reference signal (VREF1); and an output (s1_ao) for providing an analogue read signal (Vs1_ao); ∘ a feedback capacitive impedance mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier; - a sequencer circuit configured to, following the reading of a piece of data corresponding to the second logic state ("1"), apply a control signal to the first input/output node having an amplitude lower than the first reference signal (VREF1) and maintain the selection transistor in an on state so as to restore, in the elementary storage component of the selected memory cell, a level of charges corresponding to a second logic state ("1"). - a matrix of memory cells such that each memory cell (CM ij) comprises: • an elementary storage component of ferroelectric type with variable electric bias and having a first electrode and a second electrode; • a first input/output node connected to the second electrode; a second input/output node; a selection node; • a selection transistor having a gate connected to the selection node and linking the first electrode to the second input/output node; wherein each memory cell can have a first ("0") or a second ("1") logic state corresponding respectively to different levels of charges stored in the associated elementary storage component; • an elementary storage component of ferroelectric type with variable electric bias and having a first electrode and a second electrode; • a first input/output node connected to the second electrode; a second input/output node; a selection node; • a selection transistor having a gate connected to the selection node and linking the first electrode to the second input/output node; wherein each memory cell can have a first ("0") or a second ("1") logic state corresponding respectively to different levels of charges stored in the associated elementary storage component; - a read circuit associated with at least one memory cell, comprising: • a capacitive transimpedance amplifier stage configured to read a piece of data stored in a memory cell (CM ij) selected via the switching-on of the corresponding selection transistor by applying a selection signal to the selection node; said capacitive transimpedance amplifier stage comprising: ∘ an operational amplifier having: a first input (e1_ao) connected to the second input/output node of the associated memory cell, a second input (e2_ao) for receiving a first reference signal (VREF1); and an output (s1_ao) for providing an analogue read signal (Vs1_ao); ∘ a feedback capacitive impedance mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier; • a capacitive transimpedance amplifier stage configured to read a piece of data stored in a memory cell (CM ij) selected via the switching-on of the corresponding selection transistor by applying a selection signal to the selection node; said capacitive transimpedance amplifier stage comprising: ∘ an operational amplifier having: a first input (e1_ao) connected to the second input/output node of the associated memory cell, a second input (e2_ao) for receiving a first reference signal (VREF1); and an output (s1_ao) for providing an analogue read signal (Vs1_ao); ∘ a feedback capacitive impedance mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier; ∘ an operational amplifier having: a first input (e1_ao) connected to the second input/output node of the associated memory cell, a second input (e2_ao) for receiving a first reference signal (VREF1); and an output (s1_ao) for providing an analogue read signal (Vs1_ao); ∘ a feedback capacitive impedance mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier; - a sequencer circuit configured to, following the reading of a piece of data corresponding to the second logic state ("1"), apply a control signal to the first input/output node having an amplitude lower than the first reference signal (VREF1) and maintain the selection transistor in an on state so as to restore, in the elementary storage component of the selected memory cell, a level of charges corresponding to a second logic state ("1").