An apparatus, comprising: a multicore processor including a plurality of processing cores each associated with a memory management unit and one or more peripheral access management units (212, 213, 214, 215, 216), the memory management units and the peripheral access management units (212, 213, 214, 215, 216) each configured to selectively enforce static virtual address mappings; a first shared cache and a second shared cache adapted to be shared by the plurality of processing cores; and a separation kernel configured to execute within each of the plurality of processing cores, the separation kernel configured to cause the memory management units and the peripheral access management units (212, 213, 214, 215, 216) to enforce the static virtual address mappings to form at least two isolated memory domains within a shared system memory, wherein the apparatus is configured to operate at least a first of the processing cores with a first of the at least two isolated memory domains exclusive of a second of the at least two isolated memory domains and to separately operate at least a second of the processing cores with the second of the at least two isolated memory domains exclusive of the first of the at least two isolated memory domains, wherein two or more of the processing cores including the first processing core and excluding the second processing core are configured to employ the first shared cache, wherein two or more of the processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache, and wherein the apparatus is configured to disable all caches shared by the processing cores. a multicore processor including a plurality of processing cores each associated with a memory management unit and one or more peripheral access management units (212, 213, 214, 215, 216), the memory management units and the peripheral access management units (212, 213, 214, 215, 216) each configured to selectively enforce static virtual address mappings; a first shared cache and a second shared cache adapted to be shared by the plurality of processing cores; and a separation kernel configured to execute within each of the plurality of processing cores, the separation kernel configured to cause the memory management units and the peripheral access management units (212, 213, 214, 215, 216) to enforce the static virtual address mappings to form at least two isolated memory domains within a shared system memory, wherein the apparatus is configured to operate at least a first of the processing cores with a first of the at least two isolated memory domains exclusive of a second of the at least two isolated memory domains and to separately operate at least a second of the processing cores with the second of the at least two isolated memory domains exclusive of the first of the at least two isolated memory domains, wherein two or more of the processing cores including the first processing core and excluding the second processing core are configured to employ the first shared cache, wherein two or more of the processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache, and wherein the apparatus is configured to disable all caches shared by the processing cores.