A first system-on-chip comprising: a plurality of non-hopping bus interfaces (92, 107, 109) comprising a first non-hopping bus interface and a second non-hopping bus interface, wherein the first non-hopping bus interface is configured to, based on a first protocol, receive information; a hopping bus comprising a plurality of intra-chip adaptors (76, 78, 80, 268), wherein the plurality of intra-chip adaptors (76, 78, 80, 268) are connected in series and respectively to the plurality of non-hopping bus interfaces (92, 107, 109), the plurality of intra-chip adaptors (76, 78, 80, 268) are configured to i) according to a second protocol, convert the information into a first format for transmission over the hopping bus including packetizing the information to generate one or more packets, and ii) transfer the information in the first format over the hopping bus and between the plurality of intra-chip adaptors (76, 78, 80, 268), the second protocol is different than the first protocol, and the second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus; a control module (86, 256) configured to i) load up boot code for the first system-on-chip (70, 252) and a second system-on-chip (72, 254), and ii) transmit a ready signal to a first intra-chip adaptor (76, 268), wherein the ready signal indicates the boot code for the second system-on-chip (72, 254) is ready, and wherein the plurality of intra-chip adaptors (76, 78, 80, 268) comprise the first intra-chip adaptor (76, 268); and a first inter-chip adaptor (82, 266) configured to i) transfer the ready signal from the first intra-chip adaptor (76, 268) to the second system-on-chip (72, 254) via an inter-chip bus, and ii) based on the ready signal, receive an access signal from the second system-on-chip (72, 254), and iii) based on the access signal, transfer the boot code for the second system-on-chip (72, 254) to the second system-on-chip (72, 254), wherein the inter-chip bus extends between the first system-on-chip (70, 252) and the second system-on-chip (72, 254). a plurality of non-hopping bus interfaces (92, 107, 109) comprising a first non-hopping bus interface and a second non-hopping bus interface, wherein the first non-hopping bus interface is configured to, based on a first protocol, receive information; a hopping bus comprising a plurality of intra-chip adaptors (76, 78, 80, 268), wherein the plurality of intra-chip adaptors (76, 78, 80, 268) are connected in series and respectively to the plurality of non-hopping bus interfaces (92, 107, 109), the plurality of intra-chip adaptors (76, 78, 80, 268) are configured to i) according to a second protocol, convert the information into a first format for transmission over the hopping bus including packetizing the information to generate one or more packets, and ii) transfer the information in the first format over the hopping bus and between the plurality of intra-chip adaptors (76, 78, 80, 268), the second protocol is different than the first protocol, and the second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus; the plurality of intra-chip adaptors (76, 78, 80, 268) are connected in series and respectively to the plurality of non-hopping bus interfaces (92, 107, 109), the plurality of intra-chip adaptors (76, 78, 80, 268) are configured to i) according to a second protocol, convert the information into a first format for transmission over the hopping bus including packetizing the information to generate one or more packets, and ii) transfer the information in the first format over the hopping bus and between the plurality of intra-chip adaptors (76, 78, 80, 268), the second protocol is different than the first protocol, and the second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus; a control module (86, 256) configured to i) load up boot code for the first system-on-chip (70, 252) and a second system-on-chip (72, 254), and ii) transmit a ready signal to a first intra-chip adaptor (76, 268), wherein the ready signal indicates the boot code for the second system-on-chip (72, 254) is ready, and wherein the plurality of intra-chip adaptors (76, 78, 80, 268) comprise the first intra-chip adaptor (76, 268); and a first inter-chip adaptor (82, 266) configured to i) transfer the ready signal from the first intra-chip adaptor (76, 268) to the second system-on-chip (72, 254) via an inter-chip bus, and ii) based on the ready signal, receive an access signal from the second system-on-chip (72, 254), and iii) based on the access signal, transfer the boot code for the second system-on-chip (72, 254) to the second system-on-chip (72, 254), wherein the inter-chip bus extends between the first system-on-chip (70, 252) and the second system-on-chip (72, 254).