A method of forming a three-dimensional memory device, comprising: forming an alternating stack (32, 46) of insulating layers and spacer material layers over a substrate (9, 10), wherein the spacer material layers are formed as, or are subsequently replaced by, electrically conductive layers; forming memory openings through the alternating stack (32, 46); forming memory stack structures in the memory openings, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; forming at least one drain select level dielectric layer over the alternating stack (32, 46); forming drain select level openings (609, 609') through the at least one drain select level dielectric layer; forming drain select level lateral recesses by removing portions of the at least one drain select level dielectric layer through the drain select level openings (609, 609'), wherein the drain select level lateral recesses are laterally spaced among one another by electrically insulating line structures that are remaining portions of the at least one drain select level dielectric layer; forming at least one drain select level conductive layer in the drain select level lateral recesses, wherein each of the at least one drain select level conductive layer comprises electrically conductive line structures that laterally extend along a first horizontal direction and are laterally spaced apart among one another by the electrically insulating line structures along a second horizontal direction; forming drain select level gate dielectrics at a periphery of each of the drain select level openings (609, 609'); and forming drain select level channel portions in remaining volumes of the drain select level openings (609, 609'). forming an alternating stack (32, 46) of insulating layers and spacer material layers over a substrate (9, 10), wherein the spacer material layers are formed as, or are subsequently replaced by, electrically conductive layers; forming memory openings through the alternating stack (32, 46); forming memory stack structures in the memory openings, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; forming at least one drain select level dielectric layer over the alternating stack (32, 46); forming drain select level openings (609, 609') through the at least one drain select level dielectric layer; forming drain select level lateral recesses by removing portions of the at least one drain select level dielectric layer through the drain select level openings (609, 609'), wherein the drain select level lateral recesses are laterally spaced among one another by electrically insulating line structures that are remaining portions of the at least one drain select level dielectric layer; forming at least one drain select level conductive layer in the drain select level lateral recesses, wherein each of the at least one drain select level conductive layer comprises electrically conductive line structures that laterally extend along a first horizontal direction and are laterally spaced apart among one another by the electrically insulating line structures along a second horizontal direction; forming drain select level gate dielectrics at a periphery of each of the drain select level openings (609, 609'); and forming drain select level channel portions in remaining volumes of the drain select level openings (609, 609').