A cryptographic device, comprising: a device input, coupled to receive a first input value; a device output; and a logic core, coupled to the device input so as to receive and process the first input value using a secret value stored in the logical core so as to provide an output value at the device output, the logic core comprising: an input generator, configured to provide a second input value that is uncorrelated with the first input value; and a plurality of logic units, comprising at least: a first logic unit, comprising a first logic input, which is coupled to receive, at an initial cycle of the cryptographic device, the first input value from the device input and to receive, at subsequent cycles of the cryptographic device, first intermediate values generated by another one of the logic units; and first processing logic configured to operate on first data values provided by the first logic input using the secret value, thereby generating second intermediate values; and a second logic unit, comprising a second logic input, which is coupled to receive the second input value from the input generator at the initial cycle of the cryptographic device and to receive, at subsequent cycles of the cryptographic device, the second intermediate values; and second processing logic identical to the first processing logic and configured to operate, in synchrony with the first processing logic, on second data values provided by the second logic input, thereby generating further intermediate values for input to a further one of the logic units. a device input, coupled to receive a first input value; a device output; and a logic core, coupled to the device input so as to receive and process the first input value using a secret value stored in the logical core so as to provide an output value at the device output, the logic core comprising: an input generator, configured to provide a second input value that is uncorrelated with the first input value; and a plurality of logic units, comprising at least: a first logic unit, comprising a first logic input, which is coupled to receive, at an initial cycle of the cryptographic device, the first input value from the device input and to receive, at subsequent cycles of the cryptographic device, first intermediate values generated by another one of the logic units; and first processing logic configured to operate on first data values provided by the first logic input using the secret value, thereby generating second intermediate values; and a second logic unit, comprising a second logic input, which is coupled to receive the second input value from the input generator at the initial cycle of the cryptographic device and to receive, at subsequent cycles of the cryptographic device, the second intermediate values; and second processing logic identical to the first processing logic and configured to operate, in synchrony with the first processing logic, on second data values provided by the second logic input, thereby generating further intermediate values for input to a further one of the logic units. an input generator, configured to provide a second input value that is uncorrelated with the first input value; and a plurality of logic units, comprising at least: a first logic unit, comprising a first logic input, which is coupled to receive, at an initial cycle of the cryptographic device, the first input value from the device input and to receive, at subsequent cycles of the cryptographic device, first intermediate values generated by another one of the logic units; and first processing logic configured to operate on first data values provided by the first logic input using the secret value, thereby generating second intermediate values; and a second logic unit, comprising a second logic input, which is coupled to receive the second input value from the input generator at the initial cycle of the cryptographic device and to receive, at subsequent cycles of the cryptographic device, the second intermediate values; and second processing logic identical to the first processing logic and configured to operate, in synchrony with the first processing logic, on second data values provided by the second logic input, thereby generating further intermediate values for input to a further one of the logic units. a first logic unit, comprising a first logic input, which is coupled to receive, at an initial cycle of the cryptographic device, the first input value from the device input and to receive, at subsequent cycles of the cryptographic device, first intermediate values generated by another one of the logic units; and first processing logic configured to operate on first data values provided by the first logic input using the secret value, thereby generating second intermediate values; and a second logic unit, comprising a second logic input, which is coupled to receive the second input value from the input generator at the initial cycle of the cryptographic device and to receive, at subsequent cycles of the cryptographic device, the second intermediate values; and second processing logic identical to the first processing logic and configured to operate, in synchrony with the first processing logic, on second data values provided by the second logic input, thereby generating further intermediate values for input to a further one of the logic units.