An image sensor comprising: (a) a plurality of pixels disposed on a substrate and arranged in rows and columns, at least two adjacent pixels (235, 236) comprising only one power supply diffusion and each pixel (235, 236) including: (i) at least one photosensitive region (232, 233, 237, 238) that collects charges in response to incident light; (ii) a charge-to-voltage conversion node (218, 228) for sensing the charge from the at least one photosensitive region (232, 233, 237, 238) and converting the charge to a voltage; (iii) an amplifier transistor (210, 220) having a source connected to an output node (242, 243), having a gate connected to the charge-to-voltage conversion node (218, 228) and having a drain connected to a portion of the a power supply diffusion; and (iv) a reset transistor (212, 222) for connecting the output node (242, 243) and the charge-to-voltage conversion node (218, 228), characterized in that one pixel of said at least two adjacent pixels includes a sequential spatial order as follows: the charge-to-voltage conversion node, a reset gate of the reset transistor, the output node, the gate of the amplifier transistor and a portion of the power supply diffusion and the adjacent pixel of said at least two adjacent pixels includes a sequential spatial order as follows: a remaining portion of the power supply diffusion, the gate of the amplifier transistor, the output node, a reset gate of the reset transistor, and a charge-to-voltage conversion node. (a) a plurality of pixels disposed on a substrate and arranged in rows and columns, at least two adjacent pixels (235, 236) comprising only one power supply diffusion and each pixel (235, 236) including: (i) at least one photosensitive region (232, 233, 237, 238) that collects charges in response to incident light; (ii) a charge-to-voltage conversion node (218, 228) for sensing the charge from the at least one photosensitive region (232, 233, 237, 238) and converting the charge to a voltage; (iii) an amplifier transistor (210, 220) having a source connected to an output node (242, 243), having a gate connected to the charge-to-voltage conversion node (218, 228) and having a drain connected to a portion of the a power supply diffusion; and (iv) a reset transistor (212, 222) for connecting the output node (242, 243) and the charge-to-voltage conversion node (218, 228), characterized in that one pixel of said at least two adjacent pixels includes a sequential spatial order as follows: the charge-to-voltage conversion node, a reset gate of the reset transistor, the output node, the gate of the amplifier transistor and a portion of the power supply diffusion and the adjacent pixel of said at least two adjacent pixels includes a sequential spatial order as follows: a remaining portion of the power supply diffusion, the gate of the amplifier transistor, the output node, a reset gate of the reset transistor, and a charge-to-voltage conversion node. (i) at least one photosensitive region (232, 233, 237, 238) that collects charges in response to incident light; (ii) a charge-to-voltage conversion node (218, 228) for sensing the charge from the at least one photosensitive region (232, 233, 237, 238) and converting the charge to a voltage; (iii) an amplifier transistor (210, 220) having a source connected to an output node (242, 243), having a gate connected to the charge-to-voltage conversion node (218, 228) and having a drain connected to a portion of the a power supply diffusion; and (iv) a reset transistor (212, 222) for connecting the output node (242, 243) and the charge-to-voltage conversion node (218, 228), characterized in that one pixel of said at least two adjacent pixels includes a sequential spatial order as follows: the charge-to-voltage conversion node, a reset gate of the reset transistor, the output node, the gate of the amplifier transistor and a portion of the power supply diffusion and the adjacent pixel of said at least two adjacent pixels includes a sequential spatial order as follows: a remaining portion of the power supply diffusion, the gate of the amplifier transistor, the output node, a reset gate of the reset transistor, and a charge-to-voltage conversion node.