A processor comprising: a plurality of cores to execute instructions; a shared circuitry region to be shared by the plurality of cores; first cache management circuitry associated with the shared circuitry region to receive delayed prefetch messages from the cores, each delayed prefetch message comprising an address or portion thereof usable to identify a cache line and being for prefetching the cache line, delayed until a notification is received that the cache line is being modified; and a delayed prefetch manager comprising a plurality of entries, each entry associated with at least one of the delayed prefetch messages, the delayed prefetch manager to update one or more of the entries or generate a new entry in accordance with receipt of each new delayed prefetch message, wherein upon receiving a notification that a first cache line is being modified by a first core, the delayed prefetch manager is to transmit delayed prefetch response messages to one or more cores identified in a first entry associated with the first cache line, wherein the delayed prefetch manager comprises a table or buffer to store the entries, and wherein each entry includes a first field to identify a cache line and a second field to identify one or more cores, wherein the second field comprises a bit vector with a bit associated with each core, wherein a first bit is to be set to a first value upon receipt of a first delayed prefetch request message identifying the first cache line from a first core corresponding to the first bit and wherein a second bit is to be set to a second value upon receipt of a second delayed prefetch request message identifying the first cache line from a second core corresponding to the second bit, and wherein upon receipt of a first notification that the first cache line is being modified by a third core, the delayed prefetch manager is to responsively read the bit vector to identify the first and second cores, and to transmit delayed prefetch response messages to both the first core and the second core. a plurality of cores to execute instructions; a shared circuitry region to be shared by the plurality of cores; first cache management circuitry associated with the shared circuitry region to receive delayed prefetch messages from the cores, each delayed prefetch message comprising an address or portion thereof usable to identify a cache line and being for prefetching the cache line, delayed until a notification is received that the cache line is being modified; and a delayed prefetch manager comprising a plurality of entries, each entry associated with at least one of the delayed prefetch messages, the delayed prefetch manager to update one or more of the entries or generate a new entry in accordance with receipt of each new delayed prefetch message, wherein upon receiving a notification that a first cache line is being modified by a first core, the delayed prefetch manager is to transmit delayed prefetch response messages to one or more cores identified in a first entry associated with the first cache line, wherein the delayed prefetch manager comprises a table or buffer to store the entries, and wherein each entry includes a first field to identify a cache line and a second field to identify one or more cores, wherein the second field comprises a bit vector with a bit associated with each core, wherein a first bit is to be set to a first value upon receipt of a first delayed prefetch request message identifying the first cache line from a first core corresponding to the first bit and wherein a second bit is to be set to a second value upon receipt of a second delayed prefetch request message identifying the first cache line from a second core corresponding to the second bit, and wherein upon receipt of a first notification that the first cache line is being modified by a third core, the delayed prefetch manager is to responsively read the bit vector to identify the first and second cores, and to transmit delayed prefetch response messages to both the first core and the second core.