An electronic circuit with an array of programmable logic cells, each of the cells comprising: - an input circuit with a plurality of logic inputs (21, 72); - an output circuit; - a plurality of programmable logic units (24a-d), coupled in parallel between the input circuit and the output circuit, the logic cell being configurable between a random logic mode and a multi-bit operand processing mode; wherein at least one of the programmable logic units (24a-d) comprises: - a configurable look-up table circuit, having inputs coupled to receive the logic input signals (A, B) from the input circuit and having an output; - a controllable inverter/non-inverter circuit, having an input connected to the output of the look-up table circuit, and being controllable by an input carry signal; - a first output node connected to receive the output of the inverter/non-inverter circuit, and coupled to the output circuit for providing a multi-bit operand processing mode output signal; and - a second output node connected to receive the output of the look-up table circuit, for providing a random logic mode output signal, characterized in that: the input circuit is arranged to be configurable to provide only a proper subset of all possible couplings between the signal inputs of the cell and inputs of the programmable logic units (24a-d), the subset comprising a multi-bit operand coupling, in which respective ones of the signal inputs (21, 72) are coupled to respective inputs of respective ones of the programmable logic units (24a-d), and a random logic coupling in which a subset of the signal inputs (21, 72) is coupled to the inputs of each of the programmable logic units (24a-d). - an input circuit with a plurality of logic inputs (21, 72); - an output circuit; - a plurality of programmable logic units (24a-d), coupled in parallel between the input circuit and the output circuit, the logic cell being configurable between a random logic mode and a multi-bit operand processing mode; wherein at least one of the programmable logic units (24a-d) comprises: - a configurable look-up table circuit, having inputs coupled to receive the logic input signals (A, B) from the input circuit and having an output; - a controllable inverter/non-inverter circuit, having an input connected to the output of the look-up table circuit, and being controllable by an input carry signal; - a first output node connected to receive the output of the inverter/non-inverter circuit, and coupled to the output circuit for providing a multi-bit operand processing mode output signal; and - a second output node connected to receive the output of the look-up table circuit, for providing a random logic mode output signal, characterized in that: the input circuit is arranged to be configurable to provide only a proper subset of all possible couplings between the signal inputs of the cell and inputs of the programmable logic units (24a-d), the subset comprising a multi-bit operand coupling, in which respective ones of the signal inputs (21, 72) are coupled to respective inputs of respective ones of the programmable logic units (24a-d), and a random logic coupling in which a subset of the signal inputs (21, 72) is coupled to the inputs of each of the programmable logic units (24a-d). - a configurable look-up table circuit, having inputs coupled to receive the logic input signals (A, B) from the input circuit and having an output; - a controllable inverter/non-inverter circuit, having an input connected to the output of the look-up table circuit, and being controllable by an input carry signal; - a first output node connected to receive the output of the inverter/non-inverter circuit, and coupled to the output circuit for providing a multi-bit operand processing mode output signal; and - a second output node connected to receive the output of the look-up table circuit, for providing a random logic mode output signal, characterized in that: the input circuit is arranged to be configurable to provide only a proper subset of all possible couplings between the signal inputs of the cell and inputs of the programmable logic units (24a-d), the subset comprising a multi-bit operand coupling, in which respective ones of the signal inputs (21, 72) are coupled to respective inputs of respective ones of the programmable logic units (24a-d), and a random logic coupling in which a subset of the signal inputs (21, 72) is coupled to the inputs of each of the programmable logic units (24a-d). the input circuit is arranged to be configurable to provide only a proper subset of all possible couplings between the signal inputs of the cell and inputs of the programmable logic units (24a-d), the subset comprising a multi-bit operand coupling, in which respective ones of the signal inputs (21, 72) are coupled to respective inputs of respective ones of the programmable logic units (24a-d), and a random logic coupling in which a subset of the signal inputs (21, 72) is coupled to the inputs of each of the programmable logic units (24a-d).