An apparatus for controlling parameters of a plurality of processors/cores (11,...,1N) embedded in a chip, the apparatus comprising: a state machine (121,...,12N) coupled to the processors/cores, the state machine controlling selected parameters of the processors/cores, the state machine identifying the selected parameters of the processors/cores; a chip interface unit containing a logic unit coupled to the state machines, the logic unit providing control signals forcing the state machines into a predetermined state in response to test and debug procedures, the predetermined state having the selected parameters; wherein the chip interface unit and the plurality of processors/cores each contain a switch unit (30,331,...,33N) a JTAG TAP unit; (301,111,...,11N) wherein the JTAG TDI and TCLK signals entering the chip are first provided to the interface switch unit and then serially connected to all switch units, and wherein the TMS and TRST signals entering the chip are provided to all switch units in parallel; wherein the chip interface unit further contains a logic unit and status and control registers; the logic unit operable to receive signals from a register in the chip interface TAP unit and provide switch control signals to all switch units, wherein the switch signals indicate for each switch unit whether it feeds the incoming TDI signal through its corresponding TAP unit or directly to the next switch unit; wherein certain status parameters of the processors/cores are provided to the status and control registers in the interface unit via the logic unit, and from there are transferred into a data register of the TAP in the chip interface unit and scanned out to an external test and debug apparatus; and wherein the test and debug apparatus can provide control signals to the chip by which all state machines in the TAP units are forced into a predetermined state. a state machine (121,...,12N) coupled to the processors/cores, the state machine controlling selected parameters of the processors/cores, the state machine identifying the selected parameters of the processors/cores; a chip interface unit containing a logic unit coupled to the state machines, the logic unit providing control signals forcing the state machines into a predetermined state in response to test and debug procedures, the predetermined state having the selected parameters; wherein the chip interface unit and the plurality of processors/cores each contain a switch unit (30,331,...,33N) a JTAG TAP unit; (301,111,...,11N) wherein the JTAG TDI and TCLK signals entering the chip are first provided to the interface switch unit and then serially connected to all switch units, and wherein the TMS and TRST signals entering the chip are provided to all switch units in parallel; wherein the chip interface unit further contains a logic unit and status and control registers; the logic unit operable to receive signals from a register in the chip interface TAP unit and provide switch control signals to all switch units, wherein the switch signals indicate for each switch unit whether it feeds the incoming TDI signal through its corresponding TAP unit or directly to the next switch unit; wherein certain status parameters of the processors/cores are provided to the status and control registers in the interface unit via the logic unit, and from there are transferred into a data register of the TAP in the chip interface unit and scanned out to an external test and debug apparatus; and wherein the test and debug apparatus can provide control signals to the chip by which all state machines in the TAP units are forced into a predetermined state. wherein the JTAG TDI and TCLK signals entering the chip are first provided to the interface switch unit and then serially connected to all switch units, and wherein the TMS and TRST signals entering the chip are provided to all switch units in parallel; wherein the chip interface unit further contains a logic unit and status and control registers; the logic unit operable to receive signals from a register in the chip interface TAP unit and provide switch control signals to all switch units, wherein the switch signals indicate for each switch unit whether it feeds the incoming TDI signal through its corresponding TAP unit or directly to the next switch unit; wherein certain status parameters of the processors/cores are provided to the status and control registers in the interface unit via the logic unit, and from there are transferred into a data register of the TAP in the chip interface unit and scanned out to an external test and debug apparatus; and wherein the test and debug apparatus can provide control signals to the chip by which all state machines in the TAP units are forced into a predetermined state.