A method of forming a bipolar transistor, comprising the steps of: forming a collector region in a substrate; forming a base (57, 58) including a base stack region, and an emitter region, over the substrate, wherein the step forming the base comprises: forming a first base layer (4, 54) on the substrate; forming a planarization layer on the first base layer; defining a base window through the planarization layer and the first base layer to expose the collector region, including etching the planarization layer to a greater lateral extent than the first base layer on which it is formed; depositing a base epitaxial layer on the exposed collector region and a base stack on sidewalls of the base window; the method further comprising: laterally separating the base stack region and the emitter region from one another by forming an electrically insulating spacer therebetween by forming an electrically insulating layer (41, 42, 43) in the base window and etching the insulating layer so as to leave a residual portion thereof that covers the portion of the base stack that forms the sidewalls of the base window, wherein the greater lateral extent of the etch of the planarization layer results in a widening of the spacer or a sloping outward of the spacer at least part way up the spacer such that the insulating spacer has a width dimension at its top end that is larger than the width dimension at its bottom end; forming an emitter region in the base window by depositing a semiconductor material over the first base layer and the spacer; planarizing the resultant structure by removing all layers down to a depth part way through the planarization layer; and forming a silicide layer on the base stack and the emitter region on either side of the spacer, the silicide layer being discontinuous over the top surface of the spacer. forming a collector region in a substrate; forming a base (57, 58) including a base stack region, and an emitter region, over the substrate, wherein the step forming the base comprises: forming a first base layer (4, 54) on the substrate; forming a planarization layer on the first base layer; defining a base window through the planarization layer and the first base layer to expose the collector region, including etching the planarization layer to a greater lateral extent than the first base layer on which it is formed; depositing a base epitaxial layer on the exposed collector region and a base stack on sidewalls of the base window; the method further comprising: laterally separating the base stack region and the emitter region from one another by forming an electrically insulating spacer therebetween by forming an electrically insulating layer (41, 42, 43) in the base window and etching the insulating layer so as to leave a residual portion thereof that covers the portion of the base stack that forms the sidewalls of the base window, wherein the greater lateral extent of the etch of the planarization layer results in a widening of the spacer or a sloping outward of the spacer at least part way up the spacer such that the insulating spacer has a width dimension at its top end that is larger than the width dimension at its bottom end; forming a first base layer (4, 54) on the substrate; forming a planarization layer on the first base layer; defining a base window through the planarization layer and the first base layer to expose the collector region, including etching the planarization layer to a greater lateral extent than the first base layer on which it is formed; depositing a base epitaxial layer on the exposed collector region and a base stack on sidewalls of the base window; the method further comprising: laterally separating the base stack region and the emitter region from one another by forming an electrically insulating spacer therebetween by forming an electrically insulating layer (41, 42, 43) in the base window and etching the insulating layer so as to leave a residual portion thereof that covers the portion of the base stack that forms the sidewalls of the base window, wherein the greater lateral extent of the etch of the planarization layer results in a widening of the spacer or a sloping outward of the spacer at least part way up the spacer such that the insulating spacer has a width dimension at its top end that is larger than the width dimension at its bottom end; laterally separating the base stack region and the emitter region from one another by forming an electrically insulating spacer therebetween by forming an electrically insulating layer (41, 42, 43) in the base window and etching the insulating layer so as to leave a residual portion thereof that covers the portion of the base stack that forms the sidewalls of the base window, wherein the greater lateral extent of the etch of the planarization layer results in a widening of the spacer or a sloping outward of the spacer at least part way up the spacer such that the insulating spacer has a width dimension at its top end that is larger than the width dimension at its bottom end;