A non-volatile semiconductor memory device comprising: a semiconductor substrate; a non-volatile memory area including a non-volatile memory cell having a gate electrode including a floating gate, an inter-electrode insulating film and a control gate stacked above said semiconductor substrate and having first insulating side walls formed on side walls of said gate electrode; a peripheral circuit area including a transistor having a single-layer gate electrode formed above said semiconductor substrate, said single-layer gate electrode being made of a same layer as a layer of said control gate; and a first border area between said non-volatile memory area and said peripheral circuit area, including: a first isolation region formed in said semiconductor substrate for isolating said non-volatile memory area and said peripheral circuit area; and characterized by an insulating film region made of a same layer as said inter-electrode insulating film, and the whole of said insulating film region being formed directly on said first isolation region; a first conductive pattern being formed on said insulating film region and including a portion made of a same layer as the layer of said control gate, said insulating film region and said portion of said first conductive pattern providing a polysilicon guard; and a first redundant insulating side wall made of a same layer as a layer of said first insulating side wall and formed on a side wall of said first conductive pattern on said first isolation region on a side of said non-volatile memory area. a semiconductor substrate; a non-volatile memory area including a non-volatile memory cell having a gate electrode including a floating gate, an inter-electrode insulating film and a control gate stacked above said semiconductor substrate and having first insulating side walls formed on side walls of said gate electrode; a peripheral circuit area including a transistor having a single-layer gate electrode formed above said semiconductor substrate, said single-layer gate electrode being made of a same layer as a layer of said control gate; and a first border area between said non-volatile memory area and said peripheral circuit area, including: a first isolation region formed in said semiconductor substrate for isolating said non-volatile memory area and said peripheral circuit area; and characterized by an insulating film region made of a same layer as said inter-electrode insulating film, and the whole of said insulating film region being formed directly on said first isolation region; a first conductive pattern being formed on said insulating film region and including a portion made of a same layer as the layer of said control gate, said insulating film region and said portion of said first conductive pattern providing a polysilicon guard; and a first redundant insulating side wall made of a same layer as a layer of said first insulating side wall and formed on a side wall of said first conductive pattern on said first isolation region on a side of said non-volatile memory area. a first isolation region formed in said semiconductor substrate for isolating said non-volatile memory area and said peripheral circuit area; and characterized by an insulating film region made of a same layer as said inter-electrode insulating film, and the whole of said insulating film region being formed directly on said first isolation region; a first conductive pattern being formed on said insulating film region and including a portion made of a same layer as the layer of said control gate, said insulating film region and said portion of said first conductive pattern providing a polysilicon guard; and a first redundant insulating side wall made of a same layer as a layer of said first insulating side wall and formed on a side wall of said first conductive pattern on said first isolation region on a side of said non-volatile memory area.