A hardware processor comprising: a core to execute a thread and offload an operation; and a first hardware accelerator and a second hardware accelerator to execute the operation to generate output data and consume input data, wherein the first hardware accelerator and the second hardware accelerator are coupled to a plurality of shared buffers to store the output data from the first hardware accelerator and provide the output data as the input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer; wherein the second hardware accelerator is to compare an index for a last valid input entry of the input buffer descriptor array to an index for a last consumed input response entry of the input buffer response descriptor array to determine when the second hardware accelerator is to execute to consume input data from the plurality of shared buffers, and the first hardware accelerator is to compare an index for a last valid output entry of the output buffer descriptor array to an index for a last consumed output response entry of the output buffer response descriptor array to determine when the first hardware accelerator is to execute to generate output data into the plurality of shared buffers. a core to execute a thread and offload an operation; and a first hardware accelerator and a second hardware accelerator to execute the operation to generate output data and consume input data, wherein the first hardware accelerator and the second hardware accelerator are coupled to a plurality of shared buffers to store the output data from the first hardware accelerator and provide the output data as the input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer; wherein the second hardware accelerator is to compare an index for a last valid input entry of the input buffer descriptor array to an index for a last consumed input response entry of the input buffer response descriptor array to determine when the second hardware accelerator is to execute to consume input data from the plurality of shared buffers, and the first hardware accelerator is to compare an index for a last valid output entry of the output buffer descriptor array to an index for a last consumed output response entry of the output buffer response descriptor array to determine when the first hardware accelerator is to execute to generate output data into the plurality of shared buffers.