An interconnect circuit (200, 302) for a programmable integrated circuit, comprising: an input terminal coupled to receive an input signal (In1, In2) from a node (204, 206) in the programmable IC, wherein the input signal (In1, In2) is configured to transition from a first supply voltage (V DD) to a reference voltage or from the reference voltage to the first supply voltage (V DD); an output terminal coupled to transmit towards another node in the programmable IC; first and second control terminals (222, 224) coupled to receive from a memory cell (212, 214) of the programmable IC; and a complementary metal oxide semiconductor (CMOS) pass-gate (202-1, 202-2) coupled between the input terminal and the output terminal and to the first and second control terminals (222, 224), the CMOS pass-gate including an N-channel transistor (Q1, Q3) coupled in parallel with a P-channel transistor (Q2, Q4) configured with a threshold voltage and a low threshold voltage, respectively, selected from a plurality of threshold voltages for a CMOS process used to fabricate the programmable IC; wherein the P-channel transistor includes a body terminal coupled to the first supply voltage; wherein the N-channel transistor includes a body terminal coupled to the reference voltage with respect to the first supply voltage; wherein, to disable the CMOS pass-gate (202-1, 202-2), a gate terminal of the P-channel transistor (Q2, Q4) is coupled to a first control signal (M1', M2') having a second supply voltage (V GG) higher than the first supply voltage (V DD) coupled to the body terminal of the P-channel transistor, and lower than a voltage that causes the P-channel transistor to operate in a band-to-band tunneling region, and a gate terminal of N-channel transistor (Q1, Q3) is coupled to a second control signal (M1, M2) having the reference voltage, and wherein, to enable the CMOS pass-gate (202-1, 202-2), the gate terminal of the P-channel transistor (Q2, Q4) is coupled to the first control signal (M1', M2') having the reference voltage, and the gate terminal of the N-channel transistor is coupled to the second control signal (M1, M2) having the second supply voltage (V GG). an input terminal coupled to receive an input signal (In1, In2) from a node (204, 206) in the programmable IC, wherein the input signal (In1, In2) is configured to transition from a first supply voltage (V DD) to a reference voltage or from the reference voltage to the first supply voltage (V DD); an output terminal coupled to transmit towards another node in the programmable IC; first and second control terminals (222, 224) coupled to receive from a memory cell (212, 214) of the programmable IC; and a complementary metal oxide semiconductor (CMOS) pass-gate (202-1, 202-2) coupled between the input terminal and the output terminal and to the first and second control terminals (222, 224), the CMOS pass-gate including an N-channel transistor (Q1, Q3) coupled in parallel with a P-channel transistor (Q2, Q4) configured with a threshold voltage and a low threshold voltage, respectively, selected from a plurality of threshold voltages for a CMOS process used to fabricate the programmable IC; wherein the P-channel transistor includes a body terminal coupled to the first supply voltage; wherein the N-channel transistor includes a body terminal coupled to the reference voltage with respect to the first supply voltage; wherein, to disable the CMOS pass-gate (202-1, 202-2), a gate terminal of the P-channel transistor (Q2, Q4) is coupled to a first control signal (M1', M2') having a second supply voltage (V GG) higher than the first supply voltage (V DD) coupled to the body terminal of the P-channel transistor, and lower than a voltage that causes the P-channel transistor to operate in a band-to-band tunneling region, and a gate terminal of N-channel transistor (Q1, Q3) is coupled to a second control signal (M1, M2) having the reference voltage, and wherein, to enable the CMOS pass-gate (202-1, 202-2), the gate terminal of the P-channel transistor (Q2, Q4) is coupled to the first control signal (M1', M2') having the reference voltage, and the gate terminal of the N-channel transistor is coupled to the second control signal (M1, M2) having the second supply voltage (V GG).