An electrically alterable memory device, comprising: a plurality of electrodes in electrical communication with a stacked chalcogenide material, said stacked chalcogenide material including a first memory cell and a second memory cell and a common layer of tellurium (19,22) located between said first memory cell and said second memory cell; wherein each of said first and second memory cells includes a chalcogenide alloy (18, 23) and an interface (20, 24) between said layer of tellurium and said chalcogenide alloy; wherein each of said chalcogenide alloys being formed of an alloy having equal percentages of tellurium and stanum (SnTe x) or tellurium and germanium (GeTe x) and containing inside a fitted thin film of dielectric material (17,25) interposed therebetween; said dielectric films used as a source of negatively charged impurities in said chalcogenide alloys; wherein said layer of tellurium being formed of a stacked tellurium layer containing the positively charged impurities; wherein said stacked tellurium layer includes an ion source layer and two tellerium layers (19,22), and wherein said ion source layer being located between said two tellurium layers; wherein said plurality of electrodes include a first electrode, a second electrode, and two offset electrodes (13,14) said first electrode positioned beneath and electrically coupled to said chalcogenide alloy of said first memory cell, said second electrode positioned above and electrically coupled to said chalcogenide alloy of said second memory cell, and said two offset electrodes interposed between said first and said second electrodes and electrically coupled to an ion source layer of said stacked tellurium layer. a plurality of electrodes in electrical communication with a stacked chalcogenide material, said stacked chalcogenide material including a first memory cell and a second memory cell and a common layer of tellurium (19,22) located between said first memory cell and said second memory cell; wherein each of said first and second memory cells includes a chalcogenide alloy (18, 23) and an interface (20, 24) between said layer of tellurium and said chalcogenide alloy; wherein each of said chalcogenide alloys being formed of an alloy having equal percentages of tellurium and stanum (SnTe x) or tellurium and germanium (GeTe x) and containing inside a fitted thin film of dielectric material (17,25) interposed therebetween; said dielectric films used as a source of negatively charged impurities in said chalcogenide alloys; wherein said layer of tellurium being formed of a stacked tellurium layer containing the positively charged impurities; wherein said stacked tellurium layer includes an ion source layer and two tellerium layers (19,22), and wherein said ion source layer being located between said two tellurium layers; wherein said plurality of electrodes include a first electrode, a second electrode, and two offset electrodes (13,14) said first electrode positioned beneath and electrically coupled to said chalcogenide alloy of said first memory cell, said second electrode positioned above and electrically coupled to said chalcogenide alloy of said second memory cell, and said two offset electrodes interposed between said first and said second electrodes and electrically coupled to an ion source layer of said stacked tellurium layer.