A shift-register circuit comprising: a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port, the pull-up sub-circuit being configured to pass a first clock signal from the first clock port to the output port in response to the pull-up node being set to a turn-on voltage; a storage capacitor having a first terminal coupled to the pull-up node and a second terminal coupled to the output port; and a chamfering sub-circuit coupled to the pull-up node, the first clock port, a chamfering clock port, and the output port, the chamfering sub-circuit being configured to pass a chamfering clock signal with the turn-on voltage from the chamfering clock port to the output port simultaneously as the first clock signal is provided at the first clock port, and the chamfering sub-circuit being further configured to switch off the chamfering clock signal to a turn-off voltage earlier in time than the first clock signal, wherein the chamfering sub-circuit comprises a first transistor and a second transistor, the first transistor having a gate coupled to the first clock port, a first terminal coupled to the chamfering clock port, and a second terminal coupled to a first terminal of the second transistor; and the second transistor having a gate coupled to the pull-up node, the first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the output port, wherein the pull-up sub-circuit comprises a third transistor having a gate coupled to the pull-up node, a first terminal coupled to the first clock port, and a second terminal coupled to the output port, the shift register circuit being further configured to provide: in an output period, the turn-on voltage at the first clock port and the turn-on voltage at the chamfering clock port, in a chamfering period, the turn-on voltage at the first clock port and the turn-off voltage at the chamfering clock port, in a scanning period, the turn-on voltage at the first control port and the turn-off voltage at the second control port, in a blank period, the turn-off voltage at the first control port and the turn-on voltage at the second control port. a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port, the pull-up sub-circuit being configured to pass a first clock signal from the first clock port to the output port in response to the pull-up node being set to a turn-on voltage; a storage capacitor having a first terminal coupled to the pull-up node and a second terminal coupled to the output port; and a chamfering sub-circuit coupled to the pull-up node, the first clock port, a chamfering clock port, and the output port, the chamfering sub-circuit being configured to pass a chamfering clock signal with the turn-on voltage from the chamfering clock port to the output port simultaneously as the first clock signal is provided at the first clock port, and the chamfering sub-circuit being further configured to switch off the chamfering clock signal to a turn-off voltage earlier in time than the first clock signal, wherein the chamfering sub-circuit comprises a first transistor and a second transistor, the first transistor having a gate coupled to the first clock port, a first terminal coupled to the chamfering clock port, and a second terminal coupled to a first terminal of the second transistor; and the second transistor having a gate coupled to the pull-up node, the first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the output port, wherein the pull-up sub-circuit comprises a third transistor having a gate coupled to the pull-up node, a first terminal coupled to the first clock port, and a second terminal coupled to the output port, the shift register circuit being further configured to provide: in an output period, the turn-on voltage at the first clock port and the turn-on voltage at the chamfering clock port, in a chamfering period, the turn-on voltage at the first clock port and the turn-off voltage at the chamfering clock port, in a scanning period, the turn-on voltage at the first control port and the turn-off voltage at the second control port, in a blank period, the turn-off voltage at the first control port and the turn-on voltage at the second control port. in an output period, the turn-on voltage at the first clock port and the turn-on voltage at the chamfering clock port, in a chamfering period, the turn-on voltage at the first clock port and the turn-off voltage at the chamfering clock port, in a scanning period, the turn-on voltage at the first control port and the turn-off voltage at the second control port, in a blank period, the turn-off voltage at the first control port and the turn-on voltage at the second control port.