An active-matrix substrate (20a; 120a; 220a) comprising: a plurality of data lines; a plurality of control signal lines and power supply lines (15L1) substantially parallel to the data lines; a plurality of gate lines crossing the plurality of data lines, the plurality of gate lines extending from one end to the other end of the substrate, are separated at a constant distance and are substantially parallel to each other, pixel regions (211R, 211G, 211B, 212R, 212G, 212B, 213R, 213G, 213B) formed at the intersections of the data lines and the gate lines, pixel electrodes, wherein each pixel electrode is located in a respective pixel region (211R, 211G, 211 B, 212R, 212G, 212B, 213R, 213G, 213B) and connected with one of the gate lines and one of the data lines; first terminals connected to the plurality of data lines, said first terminals being connectable to a source driver external to the active-matrix substrate; second terminals connected to the plurality of control signal lines and power supply lines (15L1), said second terminals being connectable to a display control circuit and power supply circuit both external to the active-matrix substrate; the active-matrix substrate further comprising gate driving circuits, each gate driving circuit being connected to a plurality of control signal lines and power supply lines and to one of the plurality of gate lines and being configured to output a scan signal to said one gate line (13G: GL(n)) in response to control signals (CKA, CKB, VSS, CLR) received via the control signal lines and the power supply lines from the display control circuit and power supply circuit when the plurality of control signal lines and power supply lines are connected to the display control circuit and power supply circuit, each gate driving circuit being provided between the one of the gate lines (13G: GL(n)) to which the gate driving circuit is connected and an another one of the gate lines (13G: GL(n-1)) directly adjacent to said one of the gate lines (13G: GL(n)) in a display region of the active-matrix substrate (20a; 120a; 220a), wherein a plurality of the gate driving circuits,separated substantially by the same distance, is connected with each gate line, wherein each gate driving circuit includes a plurality of switching elements (TFT-A - TFT-J) and capacitor (Cbst), each of said switching elements (TFT-A - TFT-J) and capacitor of a gate driving circuit being arranged in a respective one of a plurality of pixel regions aligned along the gate line to which the gate driving circuit is connected. a plurality of data lines; a plurality of control signal lines and power supply lines (15L1) substantially parallel to the data lines; a plurality of gate lines crossing the plurality of data lines, the plurality of gate lines extending from one end to the other end of the substrate, are separated at a constant distance and are substantially parallel to each other, pixel regions (211R, 211G, 211B, 212R, 212G, 212B, 213R, 213G, 213B) formed at the intersections of the data lines and the gate lines, pixel electrodes, wherein each pixel electrode is located in a respective pixel region (211R, 211G, 211 B, 212R, 212G, 212B, 213R, 213G, 213B) and connected with one of the gate lines and one of the data lines; first terminals connected to the plurality of data lines, said first terminals being connectable to a source driver external to the active-matrix substrate; second terminals connected to the plurality of control signal lines and power supply lines (15L1), said second terminals being connectable to a display control circuit and power supply circuit both external to the active-matrix substrate; the active-matrix substrate further comprising gate driving circuits, each gate driving circuit being connected to a plurality of control signal lines and power supply lines and to one of the plurality of gate lines and being configured to output a scan signal to said one gate line (13G: GL(n)) in response to control signals (CKA, CKB, VSS, CLR) received via the control signal lines and the power supply lines from the display control circuit and power supply circuit when the plurality of control signal lines and power supply lines are connected to the display control circuit and power supply circuit, each gate driving circuit being provided between the one of the gate lines (13G: GL(n)) to which the gate driving circuit is connected and an another one of the gate lines (13G: GL(n-1)) directly adjacent to said one of the gate lines (13G: GL(n)) in a display region of the active-matrix substrate (20a; 120a; 220a), wherein a plurality of the gate driving circuits,separated substantially by the same distance, is connected with each gate line, wherein each gate driving circuit includes a plurality of switching elements (TFT-A - TFT-J) and capacitor (Cbst), each of said switching elements (TFT-A - TFT-J) and capacitor of a gate driving circuit being arranged in a respective one of a plurality of pixel regions aligned along the gate line to which the gate driving circuit is connected.