An audio signal processing circuit comprising: a plurality of N (N represents an integer of 2 or more) FIR (Finite Impulse Response) filters; a plurality of N first input ports that respectively correspond to the plurality of N FIR filters; a plurality of N second input ports that respectively correspond to the plurality of N FIR filters; a plurality of N first output ports (OUTA) that respectively correspond to the plurality of N FIR filters; and a plurality of N second output ports (OUTB) that respectively correspond to the plurality of N FIR filters; wherein the first input ports, the second input ports, the first output ports (OUTA), and the second output ports (OUTB) are integrated on a single semiconductor substrate, wherein each FIR filter comprises: a first input terminal; a second input terminal; a first output terminal; a second output terminal; a plurality of m (m represents an integer of 2 or more) delay elements (d1-dm) connected in series between the first input terminal and the first output terminal; a plurality of multipliers (K1-Km) that multiply, by predetermined coefficient, data at a plurality of taps provided to the m delay elements (K1-Km); and an adder circuit that outputs, via the second output terminal, product-sum data obtained by adding data input to the second input terminal and output data of the plurality of multipliers (K1-Km), and wherein the i-th (2 ≤ i ≤ N) FIR filter (106_i) is configured to be switchable between: (i) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, data output from the first output terminal of the (i-1)-th FIR filter (106_(i-1)), and receives, at its second input terminal, data output from the second output terminal of the (i-1)-th FIR filter (106_(i-1)); (ii) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, data of the i-th first input port, and receives, at its second input terminal, data of the i-th second input port; and (iii) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, the data of the i-th first input port, and receives zero at its second input terminal. a plurality of N (N represents an integer of 2 or more) FIR (Finite Impulse Response) filters; a plurality of N first input ports that respectively correspond to the plurality of N FIR filters; a plurality of N second input ports that respectively correspond to the plurality of N FIR filters; a plurality of N first output ports (OUTA) that respectively correspond to the plurality of N FIR filters; and a plurality of N second output ports (OUTB) that respectively correspond to the plurality of N FIR filters; wherein the first input ports, the second input ports, the first output ports (OUTA), and the second output ports (OUTB) are integrated on a single semiconductor substrate, wherein each FIR filter comprises: a first input terminal; a second input terminal; a first output terminal; a second output terminal; a plurality of m (m represents an integer of 2 or more) delay elements (d1-dm) connected in series between the first input terminal and the first output terminal; a plurality of multipliers (K1-Km) that multiply, by predetermined coefficient, data at a plurality of taps provided to the m delay elements (K1-Km); and an adder circuit that outputs, via the second output terminal, product-sum data obtained by adding data input to the second input terminal and output data of the plurality of multipliers (K1-Km), a first input terminal; a second input terminal; a first output terminal; a second output terminal; a plurality of m (m represents an integer of 2 or more) delay elements (d1-dm) connected in series between the first input terminal and the first output terminal; a plurality of multipliers (K1-Km) that multiply, by predetermined coefficient, data at a plurality of taps provided to the m delay elements (K1-Km); and an adder circuit that outputs, via the second output terminal, product-sum data obtained by adding data input to the second input terminal and output data of the plurality of multipliers (K1-Km), and wherein the i-th (2 ≤ i ≤ N) FIR filter (106_i) is configured to be switchable between: (i) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, data output from the first output terminal of the (i-1)-th FIR filter (106_(i-1)), and receives, at its second input terminal, data output from the second output terminal of the (i-1)-th FIR filter (106_(i-1)); (ii) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, data of the i-th first input port, and receives, at its second input terminal, data of the i-th second input port; and (iii) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, the data of the i-th first input port, and receives zero at its second input terminal. (i) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, data output from the first output terminal of the (i-1)-th FIR filter (106_(i-1)), and receives, at its second input terminal, data output from the second output terminal of the (i-1)-th FIR filter (106_(i-1)); (ii) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, data of the i-th first input port, and receives, at its second input terminal, data of the i-th second input port; and (iii) a state in which the i-th FIR filter (106_i) receives, at its first input terminal, the data of the i-th first input port, and receives zero at its second input terminal.