A memory module having a width of Nxn bits and configured to communicate with a memory controller via one or more clock signal lines, a set of control signal lines, and N sets of n-bit-wide data lines, where N and n are integers larger than one, comprising: a control circuit configured to receive a system clock from the memory controller via the one or more clock signal lines, and to receive input address and control (C/A) signals from the memory controller via the control signal lines, wherein the control circuit is further configured to generate a module clock signal, module C/A signals and data buffer control signals in response to the system clock and the input C/A signals; N data buffers each n -bits wide and each configured to operatively couple to a respective set of the N sets of n-bit-wide data lines, wherein each respective data buffer of the N data buffers is configured to receive the module clock signal and the data buffer control signals from the module control circuit, and to generate a respective local clock signal in response to the module clock signal, the each respective data buffer including n-bit-wide data paths (320/620) and logic configured to control the data paths in response to the data buffer control signals; and memory devices configured to receive the module C/A signals from the control circuit, the memory devices including N groups of memory devices corresponding to respective ones of the N data buffers, wherein each respective group of the N groups of memory devices is configured to receive the module C/A signals from the control circuit and to receive the local clock signal from a corresponding one of the N data buffers, wherein the each respective group of the N groups of memory devices is further configured to receive or output a respective n-bit section of one or more data signals associated with the input C/A signals in response to the module C/A signals and the respective local clock signal, and wherein the respective n-bit section of the one or more data signals is transmitted via the n-bit-wide data paths in the corresponding one of the N data buffers in response to the data buffer control signals. a control circuit configured to receive a system clock from the memory controller via the one or more clock signal lines, and to receive input address and control (C/A) signals from the memory controller via the control signal lines, wherein the control circuit is further configured to generate a module clock signal, module C/A signals and data buffer control signals in response to the system clock and the input C/A signals; N data buffers each n -bits wide and each configured to operatively couple to a respective set of the N sets of n-bit-wide data lines, wherein each respective data buffer of the N data buffers is configured to receive the module clock signal and the data buffer control signals from the module control circuit, and to generate a respective local clock signal in response to the module clock signal, the each respective data buffer including n-bit-wide data paths (320/620) and logic configured to control the data paths in response to the data buffer control signals; and memory devices configured to receive the module C/A signals from the control circuit, the memory devices including N groups of memory devices corresponding to respective ones of the N data buffers, wherein each respective group of the N groups of memory devices is configured to receive the module C/A signals from the control circuit and to receive the local clock signal from a corresponding one of the N data buffers, wherein the each respective group of the N groups of memory devices is further configured to receive or output a respective n-bit section of one or more data signals associated with the input C/A signals in response to the module C/A signals and the respective local clock signal, and wherein the respective n-bit section of the one or more data signals is transmitted via the n-bit-wide data paths in the corresponding one of the N data buffers in response to the data buffer control signals.