A convolutional neural network, CNN, processing method, comprising: acquiring an intensity type of a first module in a CNN model, the intensity type of the first module in the CNN model being a type determined based on a computation-intensity degree of a layer of the convolution neural network; in a case that the intensity type of the first module is a computation-intensity type, deploying the first module on a field programmable gate array, FPGA, and acquiring a plurality of arithmetic unit resources of the FPGA which are occupied by the first module; obtaining a first resource merging module by merging identical arithmetic unit resources, among the plurality of arithmetic unit resources of the FPGA which are occupied by the first module; operating the first resource merging module by the FPGA; acquiring an intensity type of a second module in the CNN model), the intensity type of the second module in the CNN model being a type determined based on a computation-intensity degree of a layer of the convolution neural network; in a case that the intensity type of the second module is the computation-intensity type, deploying the second module on the FPGA and acquiring a plurality of arithmetic unit resources of the FPGA which are occupied by the second module; in a case that the arithmetic unit resources occupied by the first module are identical or partially identical to the arithmetic unit resources occupied by the second module, merging the first module and the second module to obtain a third module, wherein a function of the third module comprises a function of the first module and a function of the second module; and operating the third module by the FPGA, wherein the merging the first module and the second module comprises: reusing identical arithmetic unit resources of the FPGA which are occupied by the first module and the second module; and merging an input interface of the first module and an input interface of the second module, and merging an output interface of the first module and an output interface of the second module. acquiring an intensity type of a first module in a CNN model, the intensity type of the first module in the CNN model being a type determined based on a computation-intensity degree of a layer of the convolution neural network; in a case that the intensity type of the first module is a computation-intensity type, deploying the first module on a field programmable gate array, FPGA, and acquiring a plurality of arithmetic unit resources of the FPGA which are occupied by the first module; obtaining a first resource merging module by merging identical arithmetic unit resources, among the plurality of arithmetic unit resources of the FPGA which are occupied by the first module; operating the first resource merging module by the FPGA; acquiring an intensity type of a second module in the CNN model), the intensity type of the second module in the CNN model being a type determined based on a computation-intensity degree of a layer of the convolution neural network; in a case that the intensity type of the second module is the computation-intensity type, deploying the second module on the FPGA and acquiring a plurality of arithmetic unit resources of the FPGA which are occupied by the second module; in a case that the arithmetic unit resources occupied by the first module are identical or partially identical to the arithmetic unit resources occupied by the second module, merging the first module and the second module to obtain a third module, wherein a function of the third module comprises a function of the first module and a function of the second module; and operating the third module by the FPGA, wherein the merging the first module and the second module comprises: reusing identical arithmetic unit resources of the FPGA which are occupied by the first module and the second module; and merging an input interface of the first module and an input interface of the second module, and merging an output interface of the first module and an output interface of the second module. reusing identical arithmetic unit resources of the FPGA which are occupied by the first module and the second module; and merging an input interface of the first module and an input interface of the second module, and merging an output interface of the first module and an output interface of the second module.