An analog to digital converter, ADC comprising: • a NOT-gate type circuit comprising: ∘ an input end configured to receive a pulse signal having a period T; ∘ an output end; ∘ a power supply terminal coupled to a power supply; and ∘ a ground terminal coupled to a resistance variable circuit; • a capacitor, wherein one end of the capacitor is grounded and the other end of the capacitor is connected to the output end of the NOT-gate type circuit; • the resistance variable circuit comprising: ∘ a first end coupled to the ground terminal of the NOT-gate type circuit; ∘ a second end being grounded; and ∘ a plurality of resistance elements each configured to be selectively connected between ground and the NOT-gate type circuit respectively using a plurality of first gate switches, wherein each resistance element of the plurality of resistance elements comprises at least one resistor, ▪ wherein the plurality of first gate switches is configured to successively connect the plurality of resistance elements between ground and the NOT-gate type circuit, one at a time, with a period of T, wherein each resistance element has a different resistance value and the resistance value of the resistance variable circuit is changed based on a period of n*T, wherein n≥2 and n is an integer; • a mixer coupled to the output end of the NOT-gate type circuit and configured to generate n channels of sampling signals whose periods are n*T, wherein within each period n*T, a level of an ith channel of sampling signals is the same as a level of an output signal at the output end of the NOT-gate type circuit in an (i-i)th time segment whose duration is T and is a low level within other time segments, and • n ADC chips each connected to a respective one of the n channels of sampling signals and configured to use the respective one of the n channels of sampling signals as a sampling clock. • a NOT-gate type circuit comprising: ∘ an input end configured to receive a pulse signal having a period T; ∘ an output end; ∘ a power supply terminal coupled to a power supply; and ∘ a ground terminal coupled to a resistance variable circuit; ∘ an input end configured to receive a pulse signal having a period T; ∘ an output end; ∘ a power supply terminal coupled to a power supply; and ∘ a ground terminal coupled to a resistance variable circuit; • a capacitor, wherein one end of the capacitor is grounded and the other end of the capacitor is connected to the output end of the NOT-gate type circuit; • the resistance variable circuit comprising: ∘ a first end coupled to the ground terminal of the NOT-gate type circuit; ∘ a second end being grounded; and ∘ a plurality of resistance elements each configured to be selectively connected between ground and the NOT-gate type circuit respectively using a plurality of first gate switches, wherein each resistance element of the plurality of resistance elements comprises at least one resistor, ▪ wherein the plurality of first gate switches is configured to successively connect the plurality of resistance elements between ground and the NOT-gate type circuit, one at a time, with a period of T, wherein each resistance element has a different resistance value and the resistance value of the resistance variable circuit is changed based on a period of n*T, wherein n≥2 and n is an integer; ∘ a first end coupled to the ground terminal of the NOT-gate type circuit; ∘ a second end being grounded; and ∘ a plurality of resistance elements each configured to be selectively connected between ground and the NOT-gate type circuit respectively using a plurality of first gate switches, wherein each resistance element of the plurality of resistance elements comprises at least one resistor, ▪ wherein the plurality of first gate switches is configured to successively connect the plurality of resistance elements between ground and the NOT-gate type circuit, one at a time, with a period of T, wherein each resistance element has a different resistance value and the resistance value of the resistance variable circuit is changed based on a period of n*T, wherein n≥2 and n is an integer; ▪ wherein the plurality of first gate switches is configured to successively connect the plurality of resistance elements between ground and the NOT-gate type circuit, one at a time, with a period of T, wherein each resistance element has a different resistance value and the resistance value of the resistance variable circuit is changed based on a period of n*T, wherein n≥2 and n is an integer; • a mixer coupled to the output end of the NOT-gate type circuit and configured to generate n channels of sampling signals whose periods are n*T, wherein within each period n*T, a level of an ith channel of sampling signals is the same as a level of an output signal at the output end of the NOT-gate type circuit in an (i-i)th time segment whose duration is T and is a low level within other time segments, and • n ADC chips each connected to a respective one of the n channels of sampling signals and configured to use the respective one of the n channels of sampling signals as a sampling clock.