A switching power supply circuit comprising: a transformer; a switching unit which comprises a first switch and a second switch; wherein the first switch is configured to switch between one end of an output of the transformer and a ground, and the second switch is configured to switch between an opposite end of the output of the transformer and the ground, characterized by further comprising: a switching controller which comprises a comparing unit and a clock generating unit and an output waveform generating unit and is configured to control the switching unit, wherein the comparing unit is configured to output comparator signals to the clock generating unit, and comprises a first comparator having an input terminal connected to an output terminal of the first switch and a first reference voltage (Vref), and a second comparator having an input terminal connected to an output terminal of the second switch and a second reference voltage (Vref), wherein the clock generating unit comprises a NOR gate for receiving comparator signals of the comparing unit as inputs thereof and is configured to output a clock signal (sfw) to the output waveform generating unit, wherein the output waveform generating unit comprises a D flip-flop, wherein the clock signal (sfw) of the NOR gate is input to a clock input terminal of the D flip-flop, wherein an inverted output of the D flip-flop is connected to an input terminal of the D flip-flop, wherein a non-inverted output of the D flip-flop controls the first switch and the inverted output of the D flip-flop controls the second switch, and wherein the first switch is shorted when the non-inverted output is logic high, and the second switch is shorted when the inverted output is logic high. a transformer; a switching unit which comprises a first switch and a second switch; wherein the first switch is configured to switch between one end of an output of the transformer and a ground, and the second switch is configured to switch between an opposite end of the output of the transformer and the ground, characterized by further comprising: a switching controller which comprises a comparing unit and a clock generating unit and an output waveform generating unit and is configured to control the switching unit, wherein the comparing unit is configured to output comparator signals to the clock generating unit, and comprises a first comparator having an input terminal connected to an output terminal of the first switch and a first reference voltage (Vref), and a second comparator having an input terminal connected to an output terminal of the second switch and a second reference voltage (Vref), wherein the clock generating unit comprises a NOR gate for receiving comparator signals of the comparing unit as inputs thereof and is configured to output a clock signal (sfw) to the output waveform generating unit, wherein the output waveform generating unit comprises a D flip-flop, wherein the clock signal (sfw) of the NOR gate is input to a clock input terminal of the D flip-flop, wherein an inverted output of the D flip-flop is connected to an input terminal of the D flip-flop, wherein a non-inverted output of the D flip-flop controls the first switch and the inverted output of the D flip-flop controls the second switch, and wherein the first switch is shorted when the non-inverted output is logic high, and the second switch is shorted when the inverted output is logic high. a switching controller which comprises a comparing unit and a clock generating unit and an output waveform generating unit and is configured to control the switching unit, wherein the comparing unit is configured to output comparator signals to the clock generating unit, and comprises a first comparator having an input terminal connected to an output terminal of the first switch and a first reference voltage (Vref), and a second comparator having an input terminal connected to an output terminal of the second switch and a second reference voltage (Vref), wherein the clock generating unit comprises a NOR gate for receiving comparator signals of the comparing unit as inputs thereof and is configured to output a clock signal (sfw) to the output waveform generating unit, wherein the output waveform generating unit comprises a D flip-flop, wherein the clock signal (sfw) of the NOR gate is input to a clock input terminal of the D flip-flop, wherein an inverted output of the D flip-flop is connected to an input terminal of the D flip-flop, wherein a non-inverted output of the D flip-flop controls the first switch and the inverted output of the D flip-flop controls the second switch, and wherein the first switch is shorted when the non-inverted output is logic high, and the second switch is shorted when the inverted output is logic high.