A method performed by a network element (100-0, 100-1, 100-2, 100-3) comprising a plurality of ports for communicating a common clock signal with one or more neighboring network elements, the method comprising: for at least one port of the plurality of ports: determining, while the port is in a predefined listening mode, whether the port is connected with a neighboring network element; calculating, when the port is connected, a respective clock phase delay value between the network element and the neighboring network element; and based on a role assigned to the network element from a plurality of predefined roles, assigning a clock signal synchronization role to the port, wherein the network element is configured to communicate, with the neighboring network element, the common clock signal using the respective clock phase delay value and using the clock signal synchronization role, and wherein the plurality of predefined roles comprise a master role and a slave role, and wherein the clock signal synchronization role is one of a master role, a backup master role, an alternate master role, a forwarding role, or a disabled role; receiving the common clock signal from the neighboring network element; generating a first reference clock signal with a frequency greater than the common clock signal, wherein the first reference clock signal is frequency synchronized with the common clock signal; responsive to a positive edge of the common clock signal, beginning decrementing a first counter from a predefined value using the first reference clock signal; responsive to a negative edge of the common clock signal, beginning decrementing a second counter from the predefined value using the first reference clock signal; generating a positive edge of a phase-compensated clock signal when the first counter decrements to a zero value; and generating a negative edge of the phase-compensated clock signal when the second counter decrements to a zero value. for at least one port of the plurality of ports: determining, while the port is in a predefined listening mode, whether the port is connected with a neighboring network element; calculating, when the port is connected, a respective clock phase delay value between the network element and the neighboring network element; and based on a role assigned to the network element from a plurality of predefined roles, assigning a clock signal synchronization role to the port, wherein the network element is configured to communicate, with the neighboring network element, the common clock signal using the respective clock phase delay value and using the clock signal synchronization role, and wherein the plurality of predefined roles comprise a master role and a slave role, and wherein the clock signal synchronization role is one of a master role, a backup master role, an alternate master role, a forwarding role, or a disabled role; determining, while the port is in a predefined listening mode, whether the port is connected with a neighboring network element; calculating, when the port is connected, a respective clock phase delay value between the network element and the neighboring network element; and based on a role assigned to the network element from a plurality of predefined roles, assigning a clock signal synchronization role to the port, wherein the network element is configured to communicate, with the neighboring network element, the common clock signal using the respective clock phase delay value and using the clock signal synchronization role, and wherein the plurality of predefined roles comprise a master role and a slave role, and wherein the clock signal synchronization role is one of a master role, a backup master role, an alternate master role, a forwarding role, or a disabled role; receiving the common clock signal from the neighboring network element; generating a first reference clock signal with a frequency greater than the common clock signal, wherein the first reference clock signal is frequency synchronized with the common clock signal; responsive to a positive edge of the common clock signal, beginning decrementing a first counter from a predefined value using the first reference clock signal; responsive to a negative edge of the common clock signal, beginning decrementing a second counter from the predefined value using the first reference clock signal; generating a positive edge of a phase-compensated clock signal when the first counter decrements to a zero value; and generating a negative edge of the phase-compensated clock signal when the second counter decrements to a zero value.