Device for generating random numbers, comprising: - a pair of memristors (P,Q) comprising a first and a second memristor, each memristor of the pair comprising a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode, - an output terminal operatively connected to said pair of memristors, - a control logic adapted to apply a transition voltage at the ends of each memristor in order to cause a change of resistance in the memristor, characterized in that - the device further comprises a circuit comparator having a first input terminal and a second input terminal which is grounded; the first and second memristors (P,Q) being connected in parallel to said first input terminal; - each memristor is operatively connected to the output terminal by means of its bottom electrode, and in that the control logic is configured to: - fix the voltage of the output terminal to a predetermined value and apply said transition voltage to cause a change of resistance in at least one memristor of the pair, - leave the voltage at said output terminal floating and apply to the top electrodes of said first and second memristor two read voltages having opposite sign and amplitude lower than said transition voltage; wherein the control logic is further configured according to the following feature a) OR the following feature b): a) wherein the transition voltage is a SET voltage such to cause a transition from high resistance to low resistance in said at least one memristor of the pair, and wherein the control logic is further configured to apply a RESET voltage to said pair of memristors such to cause a transition from low to high resistance in both the memristors of the pair, the control logic being adapted to apply said SET voltage after said RESET voltage; b) wherein the transition voltage is a RESET voltage such to cause a transition from low resistance to high resistance in both the memristors of the pair, and wherein the control logic is further configured to apply a SET voltage to said pair of memristors such to cause a transition from high to low resistance in at least one memristor of the pair, said SET voltage being applied before said RESET voltage. - a pair of memristors (P,Q) comprising a first and a second memristor, each memristor of the pair comprising a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode, - an output terminal operatively connected to said pair of memristors, - a control logic adapted to apply a transition voltage at the ends of each memristor in order to cause a change of resistance in the memristor, characterized in that - the device further comprises a circuit comparator having a first input terminal and a second input terminal which is grounded; the first and second memristors (P,Q) being connected in parallel to said first input terminal; - each memristor is operatively connected to the output terminal by means of its bottom electrode, - the device further comprises a circuit comparator having a first input terminal and a second input terminal which is grounded; the first and second memristors (P,Q) being connected in parallel to said first input terminal; - each memristor is operatively connected to the output terminal by means of its bottom electrode, - fix the voltage of the output terminal to a predetermined value and apply said transition voltage to cause a change of resistance in at least one memristor of the pair, - leave the voltage at said output terminal floating and apply to the top electrodes of said first and second memristor two read voltages having opposite sign and amplitude lower than said transition voltage; wherein the control logic is further configured according to the following feature a) OR the following feature b): a) wherein the transition voltage is a SET voltage such to cause a transition from high resistance to low resistance in said at least one memristor of the pair, and wherein the control logic is further configured to apply a RESET voltage to said pair of memristors such to cause a transition from low to high resistance in both the memristors of the pair, the control logic being adapted to apply said SET voltage after said RESET voltage; b) wherein the transition voltage is a RESET voltage such to cause a transition from low resistance to high resistance in both the memristors of the pair, and wherein the control logic is further configured to apply a SET voltage to said pair of memristors such to cause a transition from high to low resistance in at least one memristor of the pair, said SET voltage being applied before said RESET voltage. a) wherein the transition voltage is a SET voltage such to cause a transition from high resistance to low resistance in said at least one memristor of the pair, and wherein the control logic is further configured to apply a RESET voltage to said pair of memristors such to cause a transition from low to high resistance in both the memristors of the pair, the control logic being adapted to apply said SET voltage after said RESET voltage; b) wherein the transition voltage is a RESET voltage such to cause a transition from low resistance to high resistance in both the memristors of the pair, and wherein the control logic is further configured to apply a SET voltage to said pair of memristors such to cause a transition from high to low resistance in at least one memristor of the pair, said SET voltage being applied before said RESET voltage.