A method for forming at least one source/drain region (51, 52) of at least one transistor, comprising the following steps: - providing a bulk substrate carrying a transistor pattern, said bulk substrate comprising: ∘ a base portion made of a semiconductor material having an upper face extending in a basal plane and elongated along a longitudinal axis (x), and ∘ first and second insulation portions (11, 12) located on either side of said base portion, said transistor pattern comprising: ∘ a channel (20, 21) surmounting the base portion and extending in particular along the longitudinal axis (x), ∘ a transistor gate pattern surrounding a central portion of the channel (20, 21), the gate pattern having a side, ∘ a spacer covering the side of the gate pattern and transversely surrounding a lateral portion (210, 220) of the channel (20, 21), the lateral portion (210, 220) of the channel and the spacer respectively having a facet (211a-211i, 221a-221i) and a side (411, 421) extending transversely to the longitudinal axis (x), - forming an additional insulation portion (110, 120) in the base portion, by oxidation of the semiconductor material from the upper face of the base portion, - forming by selective epitaxy a source/drain region (51, 52) from said facet (211a-211i, 221a-221i) of the channel, the method being characterised in that it further comprises the following steps: - before forming the additional insulation portion (110, 120), forming a protective layer on the facet (211a-211i, 221a-221i) of the channel, said protective layer being configured to prevent oxidation of the lateral portion (210, 220) of the channel when forming the additional insulation portion (110, 120) by oxidation, - after forming the additional insulation portion (110, 120) and before forming the source/drain region (51, 52), removing the protective layer so as to expose the facet (211a-211i, 221a-221i). - providing a bulk substrate carrying a transistor pattern, said bulk substrate comprising: ∘ a base portion made of a semiconductor material having an upper face extending in a basal plane and elongated along a longitudinal axis (x), and ∘ first and second insulation portions (11, 12) located on either side of said base portion, said transistor pattern comprising: ∘ a channel (20, 21) surmounting the base portion and extending in particular along the longitudinal axis (x), ∘ a transistor gate pattern surrounding a central portion of the channel (20, 21), the gate pattern having a side, ∘ a spacer covering the side of the gate pattern and transversely surrounding a lateral portion (210, 220) of the channel (20, 21), the lateral portion (210, 220) of the channel and the spacer respectively having a facet (211a-211i, 221a-221i) and a side (411, 421) extending transversely to the longitudinal axis (x), said bulk substrate comprising: ∘ a base portion made of a semiconductor material having an upper face extending in a basal plane and elongated along a longitudinal axis (x), and ∘ first and second insulation portions (11, 12) located on either side of said base portion, ∘ a base portion made of a semiconductor material having an upper face extending in a basal plane and elongated along a longitudinal axis (x), and ∘ first and second insulation portions (11, 12) located on either side of said base portion, said transistor pattern comprising: ∘ a channel (20, 21) surmounting the base portion and extending in particular along the longitudinal axis (x), ∘ a transistor gate pattern surrounding a central portion of the channel (20, 21), the gate pattern having a side, ∘ a spacer covering the side of the gate pattern and transversely surrounding a lateral portion (210, 220) of the channel (20, 21), ∘ a channel (20, 21) surmounting the base portion and extending in particular along the longitudinal axis (x), ∘ a transistor gate pattern surrounding a central portion of the channel (20, 21), the gate pattern having a side, ∘ a spacer covering the side of the gate pattern and transversely surrounding a lateral portion (210, 220) of the channel (20, 21), the lateral portion (210, 220) of the channel and the spacer respectively having a facet (211a-211i, 221a-221i) and a side (411, 421) extending transversely to the longitudinal axis (x), - forming an additional insulation portion (110, 120) in the base portion, by oxidation of the semiconductor material from the upper face of the base portion, - forming by selective epitaxy a source/drain region (51, 52) from said facet (211a-211i, 221a-221i) of the channel, - before forming the additional insulation portion (110, 120), forming a protective layer on the facet (211a-211i, 221a-221i) of the channel, said protective layer being configured to prevent oxidation of the lateral portion (210, 220) of the channel when forming the additional insulation portion (110, 120) by oxidation, - after forming the additional insulation portion (110, 120) and before forming the source/drain region (51, 52), removing the protective layer so as to expose the facet (211a-211i, 221a-221i).