A semiconductor device comprising a first charge pump cell and a second charge pump cell cascaded together with an output of the first charge pump cell being coupled to an input of the second charge pump cell, the semiconductor device comprising: a p-type substrate; each of the first and second charge pump cell comprising: a voltage input terminal; a first well region formed in the substrate and coupled to the voltage input terminal, wherein the first well region is doped with n-type material; a second well region formed within the first well region and coupled to the first well region and the voltage input terminal, wherein the second well region is doped with p-type material; a first transistor formed in the second well region, wherein the first transistor is an n-channel metal-oxide-semiconductor, NMOS, transistor, wherein a conduction region of the first transistor is formed in the second well region as a source of the first transistor, and wherein the conduction region of the first transistor is doped with n-type material and coupled to the voltage input terminal, the first well region and the second well region; a second transistor formed in the second well region, wherein the second transistor is an NMOS transistor, wherein a conduction region of the second transistor is formed in the second well region as a source of the second transistor, and wherein the conduction region of the second transistor is doped with n-type material and coupled to the voltage input terminal; a third well region formed in the substrate, wherein the third well region is doped with n-type material; a third transistor formed in the third well region, wherein the third transistor is a p-channel metal-oxide-semiconductor, PMOS, transistor, wherein a conduction region of the third transistor is formed in the third well region as a source of the third transistor, and wherein the conduction region of the third transistor is doped with p-type material; a fourth transistor formed in the third well region, wherein the fourth transistor is a PMOS transistor, wherein a conduction region of the fourth transistor is formed in the third well region as a source of the fourth transistor, and wherein the conduction region of the fourth transistor is doped with p-type material; a voltage output terminal coupled to the conduction region of the third transistor and to the conduction region of the fourth transistor; a first clock terminal coupled through a first capacitor to a first node, the first node being coupled to the gate of the first transistor, to the gate of the third transistor, to the drain of the second transistor and to the drain of the fourth transistor; and a second clock terminal coupled through a second capacitor to a second node, the second node being coupled to the gate of the second transistor, to the gate of the fourth transistor, to the drain of the first transistor and to the drain of the third transistor; characterised in that: in each of the first and second charge pump cells, the third well region is coupled to the voltage output terminal, and the third well region of the first charge pump cell is the same physical region as the first well region of the second charge pump cell. a p-type substrate; each of the first and second charge pump cell comprising: