A host device including a host controller and a host memory, and the host controller includes a host controller interface configured to provide interfacing between the host device and a storage device (27, 200, 1300a, 1300b, 3150, 3150n, 3250, 3250m) and to transfer a command to the storage device (27, 200, 1300a, 1300b, 3150, 3150n, 3250, 3250m), the host controller interface comprising: processing circuitry; a doorbell register (191, 197) configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues, wherein the host device includes a first core (112, 121) configured to process a first submission queue and a first completion queue, and a second core (113, 123) configured to process a second submission queue and a second completion queue, and wherein the processing circuitry is configured to, determine first and second priorities for the first submission queue and the second submission queue, respectively, and processes a queue, from among the first submission queue and the second submission queue, for which the highest priority was determined, from among the first priority and the second priority. processing circuitry; a doorbell register (191, 197) configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues, wherein the host device includes a first core (112, 121) configured to process a first submission queue and a first completion queue, and a second core (113, 123) configured to process a second submission queue and a second completion queue, and wherein the processing circuitry is configured to, determine first and second priorities for the first submission queue and the second submission queue, respectively, and processes a queue, from among the first submission queue and the second submission queue, for which the highest priority was determined, from among the first priority and the second priority. determine first and second priorities for the first submission queue and the second submission queue, respectively, and processes a queue, from among the first submission queue and the second submission queue, for which the highest priority was determined, from among the first priority and the second priority.