A system for the implementation of a hash table characterized by the fact that it consists of at least one basic block, a corresponding number of masking blocks, a counter, an address splitter, a demultiplexer and a second multiplexer, where each basic block consists of a flag register memory, a first multiplexer and a circuit for write permit to the flag register memory, wherein the flag register memory is implemented as a LUT table and contains flags of data validity, wherein the first multiplexer is equipped with first and second address inputs (5, 6) and with an output connected to a third address input of the flag register memory and wherein the circuit for write permit to the flag register memory is equipped with an input of a control signal for writing to the flag register memory and with an output connected to an input of a write signal to the flag register memory and wherein said flag register memory is further equipped with a clock signal input and a data input, which is, via an inverter, connected to an input of a control signal for initialization of the flag register memory, whereby said input of the control signal for initialization of the flag register memory is also interconnected with the control input of the first multiplexer and with the control input of the circuit for write permit to the flag register memory, and wherein a data output from the flag register memory of each basic block is connected to one input of a masking block relevant for the given basic block, where outputs of these masking blocks are connected to inputs of the second multiplexer, wherein the output of said second multiplexer is the output of a system of flags, and where the input of the control signal for writing to the flag register memory of each basic block is connected to the output of the demultiplexer and simultaneously to a second input of the masking block relevant for the given basic block, and where this demultiplexer is equipped with an input of the write permit signal, and with a fourth address input, which is connected to an output of the address splitter equipped with a fifth address input of an address for the system of flags for a normal operating mode with a width of K bits, where K is a positive integer number, and wherein said address splitter is equipped with an output of an address signal for addressing the flag register memory during a normal operating mode, and wherein the address splitter splits the address from the fifth address input into L significant bits, where L corresponds to the number of bits at the third address input of the flag register memory in the basic block and this L significant bits represent the first address input for addressing the flag register memories during normal operating mode of all basic blocks whereas the K-L most significant bits are connected to the fourth address input of the demultiplexer which transforms the value at the fourth address input into activation of one of the outputs connected to the inputs of the control signal for writing into the flag register memories of all the individual basic blocks, while the output of said address signal is interconnected with the first address inputs of the first multiplexers of all basic blocks, while the second address inputs of the first multiplexers of all basic blocks are interconnected with an output of a counter while a first input of the counter is interconnected with the inputs of the control signal for the initialization of the flag register memory of the basic blocks and a second input of the counter is the clock signal.