A method for programmable logic controller program randomization in a redundant PLC architecture system, the method comprising: a) receiving, by an engineering system (100, 305) computer, source code corresponding to a PLC program; b) compiling, by the engineering system computer (105, 105A), the source code into a plurality of functionally equivalent intermediate representations of the PLC program, wherein the program structure of the PLC program is randomized during compilation utilizing code and memory path randomization such that each intermediate representation is unique among the plurality of intermediate representations; and c) transmitting, by the engineering system computer, the plurality of intermediate representations to one or more PLCs; and d1) receiving, by the PLC, a first intermediate representation of the PLC program; d2) compiling, by the PLC, the first intermediate representation into a PLC assembly code, wherein the program structure of the first intermediate representation is randomized during compilation; and d3) executing, by the PLC, the PLC assembly code; and e1) following failover of the PLC, re-compiling the first intermediate representation into a new PLC assembly code, wherein the program structure of the first intermediate representation is randomized during re-compilation; and e2) executing, by the PLC, the new PLC assembly code; wherein f) randomization occurs in two stages: at the high-level compile time where the PLC source code is transformed into the PLC intermediate representation; and at runtime where the PLC intermediate representation is transformed into assembly instructions for execution in the PLC processor. a) receiving, by an engineering system (100, 305) computer, source code corresponding to a PLC program; b) compiling, by the engineering system computer (105, 105A), the source code into a plurality of functionally equivalent intermediate representations of the PLC program, wherein the program structure of the PLC program is randomized during compilation utilizing code and memory path randomization such that each intermediate representation is unique among the plurality of intermediate representations; and c) transmitting, by the engineering system computer, the plurality of intermediate representations to one or more PLCs; and d1) receiving, by the PLC, a first intermediate representation of the PLC program; d2) compiling, by the PLC, the first intermediate representation into a PLC assembly code, wherein the program structure of the first intermediate representation is randomized during compilation; and d3) executing, by the PLC, the PLC assembly code; and e1) following failover of the PLC, re-compiling the first intermediate representation into a new PLC assembly code, wherein the program structure of the first intermediate representation is randomized during re-compilation; and e2) executing, by the PLC, the new PLC assembly code; wherein f) randomization occurs in two stages: at the high-level compile time where the PLC source code is transformed into the PLC intermediate representation; and at runtime where the PLC intermediate representation is transformed into assembly instructions for execution in the PLC processor.