An organic light-emitting display device, comprising: an organic light-emitting display panel; a plurality of data lines arranged in a display area (A/A) of the display panel; an auxiliary power line arranged along a region of a non-display area (N/A) of the display panel, the non-display area (N/A) surrounding the display area (A/A); a power line arranged to receive a driving voltage (Vdd, Vss) introduced through a first portion of the non-display area (N/A) adjacent a first side of the display area (A/A); and a plurality of first transistors each connected between a respective data line and the auxiliary power line, wherein the auxiliary power line is electrically connected to the plurality of data lines via the first transistors; a second transistor (330; 350) connected between the power line and the auxiliary power line, whereby the auxiliary power line is electrically connected to the power line via the second transistor (330; 350),wherein the plurality of first transistors and the second transistor are in a second portion of the non-display area (N/A) adjacent a second side of the display area (A/A), a first auxiliary driving line connected to a gate node of each of the first transistors and a second auxiliary driving line (340; 360) connected to a gate node of the second transistor (330; 350), a controller configured to control a voltage supplied to the first auxiliary driving line and second auxiliary driving line (340; 360) such that: during a display driving period, the first transistors are in an 'off' state and the second transistor (330; 350) is in an 'on' state; and during a non display driving period, the first transistors are in an 'on' state and the second transistor (330; 350) is in an 'off' state. an organic light-emitting display panel; a plurality of data lines arranged in a display area (A/A) of the display panel; an auxiliary power line arranged along a region of a non-display area (N/A) of the display panel, the non-display area (N/A) surrounding the display area (A/A); a power line arranged to receive a driving voltage (Vdd, Vss) introduced through a first portion of the non-display area (N/A) adjacent a first side of the display area (A/A); and a plurality of first transistors each connected between a respective data line and the auxiliary power line, wherein the auxiliary power line is electrically connected to the plurality of data lines via the first transistors; a second transistor (330; 350) connected between the power line and the auxiliary power line, whereby the auxiliary power line is electrically connected to the power line via the second transistor (330; 350),wherein the plurality of first transistors and the second transistor are in a second portion of the non-display area (N/A) adjacent a second side of the display area (A/A), a first auxiliary driving line connected to a gate node of each of the first transistors and a second auxiliary driving line (340; 360) connected to a gate node of the second transistor (330; 350), a controller configured to control a voltage supplied to the first auxiliary driving line and second auxiliary driving line (340; 360) such that: during a display driving period, the first transistors are in an 'off' state and the second transistor (330; 350) is in an 'on' state; and during a non display driving period, the first transistors are in an 'on' state and the second transistor (330; 350) is in an 'off' state. during a display driving period, the first transistors are in an 'off' state and the second transistor (330; 350) is in an 'on' state; and during a non display driving period, the first transistors are in an 'on' state and the second transistor (330; 350) is in an 'off' state.