A self-organizing logic gate comprising: terminals comprising a first set of the terminals (22, 42) and a second set of the terminals (24, 44); memristor devices connected between the first set of the terminals (22, 42) and the second set of the terminals (24, 44); and dynamic correction modules connected to each of the terminals, the dynamic correction modules configured to drive an unstable configuration of the self-organizing logic gate toward a stable configuration of the self-organizing logic gate in response to a signal applied to any of the terminals, each of the dynamic correction modules comprising a resistor, a nonlinear conductor, a plurality of memristor devices, and a plurality of voltage-controlled voltage generators connected to each of the resistor, nonlinear conductor, and plurality of memristor devices wherein: the self-organizing logic gate is configured to implement a logic function between signals at the terminals; wherein in the stable configuration the signals at the terminals satisfy the logic function and the signals remain constant in time, and in the unstable configuration the signals at the terminals do not satisfy the logic function and the dynamic correction modules generate voltage that is dependent upon voltages at each of the terminals to drive the self-organizing logic gate toward a stable condition; and the self-organizing logic gate is configured to implement forward logic wherein signals are applied to the first set of the terminals (22, 42) and the dynamic correction modules drive the self-organizing logic gate toward a stable condition where the signals at the second set of the terminals (24, 44) satisfy the logic condition, and reverse logic wherein signals are applied to the second set of the terminals (24, 44) and the dynamic correction modules drive the self-organizing logic gate toward a stable condition where the signals at the first set of the terminals (22, 42) satisfy the logic condition. terminals comprising a first set of the terminals (22, 42) and a second set of the terminals (24, 44); memristor devices connected between the first set of the terminals (22, 42) and the second set of the terminals (24, 44); and dynamic correction modules connected to each of the terminals, the dynamic correction modules configured to drive an unstable configuration of the self-organizing logic gate toward a stable configuration of the self-organizing logic gate in response to a signal applied to any of the terminals, each of the dynamic correction modules comprising a resistor, a nonlinear conductor, a plurality of memristor devices, and a plurality of voltage-controlled voltage generators connected to each of the resistor, nonlinear conductor, and plurality of memristor devices wherein: the self-organizing logic gate is configured to implement a logic function between signals at the terminals; wherein in the stable configuration the signals at the terminals satisfy the logic function and the signals remain constant in time, and in the unstable configuration the signals at the terminals do not satisfy the logic function and the dynamic correction modules generate voltage that is dependent upon voltages at each of the terminals to drive the self-organizing logic gate toward a stable condition; and the self-organizing logic gate is configured to implement forward logic wherein signals are applied to the first set of the terminals (22, 42) and the dynamic correction modules drive the self-organizing logic gate toward a stable condition where the signals at the second set of the terminals (24, 44) satisfy the logic condition, and reverse logic wherein signals are applied to the second set of the terminals (24, 44) and the dynamic correction modules drive the self-organizing logic gate toward a stable condition where the signals at the first set of the terminals (22, 42) satisfy the logic condition. the self-organizing logic gate is configured to implement a logic function between signals at the terminals; wherein in the stable configuration the signals at the terminals satisfy the logic function and the signals remain constant in time, and in the unstable configuration the signals at the terminals do not satisfy the logic function and the dynamic correction modules generate voltage that is dependent upon voltages at each of the terminals to drive the self-organizing logic gate toward a stable condition; and the self-organizing logic gate is configured to implement forward logic wherein signals are applied to the first set of the terminals (22, 42) and the dynamic correction modules drive the self-organizing logic gate toward a stable condition where the signals at the second set of the terminals (24, 44) satisfy the logic condition, and reverse logic wherein signals are applied to the second set of the terminals (24, 44) and the dynamic correction modules drive the self-organizing logic gate toward a stable condition where the signals at the first set of the terminals (22, 42) satisfy the logic condition.