A method of fabricating a high-voltage field-effect transistor comprising the steps of: (a) forming a well region (17, 123) of a first conductivity type in a substrate (16, 121) of a second conductivity type, the well region having a laterally extended portion with a lateral boundary; (b) high-energy ion implanting in a plurality of K implantation steps a dopant of the second conductivity type into the substrate (16, 121) to form a plurality of K buried regions (60, 150) within the laterally extended portion of the well region and produce an associated plurality of K+1 JFET conduction channels (41, 160) interleaved with the buried regions, wherein a uppermost buried region is formed below a surface of the well region; (e) forming a gate insulated from the substrate (16, 121) by a gate oxide layer (36, 170), the gate extending over the substrate (16, 121) adjacent the well region (17, 123); (d) implanting a dopant of the first conductivity type into the substrate (16, 121) to form a source diffusion region (14, 128) spaced-apart from the well region (17, 123), the dopant being implanted into the well region (17, 123) to form a drain diffusion region (19, 131) spaced-apart from the first buried region (60, 150), a channel region being formed between the source diffusion region (14, 128) and the well region (17, 123) under the gate; and (e) forming source and drain electrodes connected to the source (14, 128) and drain diffusion regions (19, 131), respectively, wherein, when the high-voltage field-effect transistor is in the on-state, current is enabled to flow from the source diffusion region (14, 128) through the channel region, and then through the plurality of K+1, parallel junction field-effect transistor channels and to the drain diffusion region (19, 131). (a) forming a well region (17, 123) of a first conductivity type in a substrate (16, 121) of a second conductivity type, the well region having a laterally extended portion with a lateral boundary; (b) high-energy ion implanting in a plurality of K implantation steps a dopant of the second conductivity type into the substrate (16, 121) to form a plurality of K buried regions (60, 150) within the laterally extended portion of the well region and produce an associated plurality of K+1 JFET conduction channels (41, 160) interleaved with the buried regions, wherein a uppermost buried region is formed below a surface of the well region; (e) forming a gate insulated from the substrate (16, 121) by a gate oxide layer (36, 170), the gate extending over the substrate (16, 121) adjacent the well region (17, 123); (d) implanting a dopant of the first conductivity type into the substrate (16, 121) to form a source diffusion region (14, 128) spaced-apart from the well region (17, 123), the dopant being implanted into the well region (17, 123) to form a drain diffusion region (19, 131) spaced-apart from the first buried region (60, 150), a channel region being formed between the source diffusion region (14, 128) and the well region (17, 123) under the gate; and (e) forming source and drain electrodes connected to the source (14, 128) and drain diffusion regions (19, 131), respectively, wherein, when the high-voltage field-effect transistor is in the on-state, current is enabled to flow from the source diffusion region (14, 128) through the channel region, and then through the plurality of K+1, parallel junction field-effect transistor channels and to the drain diffusion region (19, 131).