A programmable device, comprising: one or more programming regions (122,123), each region comprising a plurality of configurable logic blocks, wherein each configurable logic block of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block of the plurality of configurable logic blocks via a programmable interconnect fabric, wherein a first programming region of the one or more programming regions is configured to execute a first instruction in an instruction stream; configuration memory configured to, for each programming region of the one or more programming regions, record a current configuration of the programming region; a function table configured to associate an opcode of a second instruction in the instruction stream with an address of a configuration bitstream; and configuration logic configured to, in response to the second instruction in the instruction stream, determine whether the second instruction is executable using the current configuration of any of the one or more programming regions, and in response to determining that the second instruction is not executable using the current configuration of any of the one or more programming regions, reconfigure hardware in one or more of the plurality of configurable logic blocks in the first programming region independently from any other programming region of the one or more programming regions by determining the configuration bitstream based on a lookup of the opcode in the function table, wherein the first programming region is configured to execute the second instruction using the reconfigured hardware in the one or more of the plurality of configurable logic blocks in the first programming region. one or more programming regions (122,123), each region comprising a plurality of configurable logic blocks, wherein each configurable logic block of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block of the plurality of configurable logic blocks via a programmable interconnect fabric, wherein a first programming region of the one or more programming regions is configured to execute a first instruction in an instruction stream; configuration memory configured to, for each programming region of the one or more programming regions, record a current configuration of the programming region; a function table configured to associate an opcode of a second instruction in the instruction stream with an address of a configuration bitstream; and configuration logic configured to, in response to the second instruction in the instruction stream, determine whether the second instruction is executable using the current configuration of any of the one or more programming regions, and in response to determining that the second instruction is not executable using the current configuration of any of the one or more programming regions, reconfigure hardware in one or more of the plurality of configurable logic blocks in the first programming region independently from any other programming region of the one or more programming regions by determining the configuration bitstream based on a lookup of the opcode in the function table, wherein the first programming region is configured to execute the second instruction using the reconfigured hardware in the one or more of the plurality of configurable logic blocks in the first programming region. determine whether the second instruction is executable using the current configuration of any of the one or more programming regions, and in response to determining that the second instruction is not executable using the current configuration of any of the one or more programming regions, reconfigure hardware in one or more of the plurality of configurable logic blocks in the first programming region independently from any other programming region of the one or more programming regions by determining the configuration bitstream based on a lookup of the opcode in the function table, wherein the first programming region is configured to execute the second instruction using the reconfigured hardware in the one or more of the plurality of configurable logic blocks in the first programming region.