An electronic device comprising: a processor first voltage generation means configured to generate a first voltage to be supplied to the processor in accordance with a first enable signal; second voltage generation means configured to generate a second voltage to be supplied to the processor in accordance with a second enable signal; third voltage generation means configured to generate a third voltage to be supplied to the processor in accordance with a third enable signal; power-on control means configured to output the first enable signal to enable the first voltage generation means to generate the first voltage in accordance with a power-on instruction, output, when the first voltage generated by the first voltage generation means is higher than or equal to a predetermined voltage, a second enable signal to enable the second voltage generation means to generate the second voltage, and output, when the second voltage generated by the second voltage generation means is higher than or equal to another predetermined voltage, a third enable signal to enable the third voltage generation means to generate the third voltage; first switching means configured to output or stop the first enable signal outputted from the power-on control means in accordance with a first off signal; second switching means configured to output or stop the second enable signal outputted from the power-on control means in accordance with a second off signal; third switching means configured to output or stop the third enable signal outputted from the power-on control means in accordance with a third off signal; a first discharge circuit configured to control a first fall time period taken for the first voltage generation means to be powered off; a second discharge circuit configured to control a second fall time period taken for the second voltage generation means to be powered off; a third discharge circuit configured to control a third fall time period taken for the third voltage generation means to be powered off; and power-off control means configured to output the third off signal to the third switching means after a first time period has elapsed from a power-off instruction, output the second off signal to the second switching means after a second time period longer than the first time period and the third fall time period has elapsed from the power-off instruction, and output the first off signal to the first switching means after a third time period longer than the second time period and the second fall time period has elapsed from the power-off instruction. a processor first voltage generation means configured to generate a first voltage to be supplied to the processor in accordance with a first enable signal; second voltage generation means configured to generate a second voltage to be supplied to the processor in accordance with a second enable signal; third voltage generation means configured to generate a third voltage to be supplied to the processor in accordance with a third enable signal; power-on control means configured to output the first enable signal to enable the first voltage generation means to generate the first voltage in accordance with a power-on instruction, output, when the first voltage generated by the first voltage generation means is higher than or equal to a predetermined voltage, a second enable signal to enable the second voltage generation means to generate the second voltage, and output, when the second voltage generated by the second voltage generation means is higher than or equal to another predetermined voltage, a third enable signal to enable the third voltage generation means to generate the third voltage; first switching means configured to output or stop the first enable signal outputted from the power-on control means in accordance with a first off signal; second switching means configured to output or stop the second enable signal outputted from the power-on control means in accordance with a second off signal; third switching means configured to output or stop the third enable signal outputted from the power-on control means in accordance with a third off signal; a first discharge circuit configured to control a first fall time period taken for the first voltage generation means to be powered off; a second discharge circuit configured to control a second fall time period taken for the second voltage generation means to be powered off; a third discharge circuit configured to control a third fall time period taken for the third voltage generation means to be powered off; and power-off control means configured to output the third off signal to the third switching means after a first time period has elapsed from a power-off instruction, output the second off signal to the second switching means after a second time period longer than the first time period and the third fall time period has elapsed from the power-off instruction, and output the first off signal to the first switching means after a third time period longer than the second time period and the second fall time period has elapsed from the power-off instruction.