A sigma-delta modulator comprising: - a chopper voltage reference circuit, preferably a bandgap chopper voltage reference circuit, adapted to generate a reference signal (VREFP, VREFM) having a clock dependent offset voltage (V offset), - a plurality of capacitor pairs; - a plurality of switches (210, 220, 230, 240, 250, 260) adapted to couple any pair of capacitors (104a, 104b) from said plurality of capacitor pairs selectively to an input signal (VINP, VINM) or the reference signal (VREFP, VREFM) or optionally to a common mode, wherein when at least one capacitor pair (104a, 104b) of said plurality of capacitor pairs is coupled with the reference signal (VREFP, VREFM) through a respective pair of switches (240, 250) the function of a single-bit or multi-bit digital-to-analog converter, DAC, is performed, the DAC being adapted to receive a feedback input value (DAC Level) from an output of said sigma-delta modulator; and - control means adapted to control said plurality of switches (210, 220, 230, 240, 250, 260) so as to perform a sample and charge transfer in two phases (P1, P2), characterized in that: - the control means is adapted to rotate the plurality of capacitor pairs cyclically such that after a rotation cycle, each capacitor pair (104a, 104b) has been assigned a first predetermined number of times to the input signal (VINP, VINM), and has also been assigned a second predetermined number of times to the reference signal (VREFP, VREFM) so that after a plurality of charge transfers a cancellation of a gain error of the sigma delta modulator due to influence of mismatched capacitors is performed, and - wherein for a plurality of sets of the DAC feedback input value (DAC Level) and a value of the offset voltage (V offset) of said chopper voltage reference circuit, the control means is adapted: to associate each set with a different switching sequence, for each switching sequence, to independently perform said cyclical rotating of said plurality of capacitor pairs and to select at least one switching sequence depending on a set of a current value of the DAC feedback input value (DAC Level) and a current value of the offset voltage (V offset) of the chopper voltage reference circuit. - a chopper voltage reference circuit, preferably a bandgap chopper voltage reference circuit, adapted to generate a reference signal (VREFP, VREFM) having a clock dependent offset voltage (V offset), - a plurality of capacitor pairs; - a plurality of switches (210, 220, 230, 240, 250, 260) adapted to couple any pair of capacitors (104a, 104b) from said plurality of capacitor pairs selectively to an input signal (VINP, VINM) or the reference signal (VREFP, VREFM) or optionally to a common mode, wherein when at least one capacitor pair (104a, 104b) of said plurality of capacitor pairs is coupled with the reference signal (VREFP, VREFM) through a respective pair of switches (240, 250) the function of a single-bit or multi-bit digital-to-analog converter, DAC, is performed, the DAC being adapted to receive a feedback input value (DAC Level) from an output of said sigma-delta modulator; and - control means adapted to control said plurality of switches (210, 220, 230, 240, 250, 260) so as to perform a sample and charge transfer in two phases (P1, P2), characterized in that: - the control means is adapted to rotate the plurality of capacitor pairs cyclically such that after a rotation cycle, each capacitor pair (104a, 104b) has been assigned a first predetermined number of times to the input signal (VINP, VINM), and has also been assigned a second predetermined number of times to the reference signal (VREFP, VREFM) so that after a plurality of charge transfers a cancellation of a gain error of the sigma delta modulator due to influence of mismatched capacitors is performed, and - wherein for a plurality of sets of the DAC feedback input value (DAC Level) and a value of the offset voltage (V offset) of said chopper voltage reference circuit, the control means is adapted: to associate each set with a different switching sequence, for each switching sequence, to independently perform said cyclical rotating of said plurality of capacitor pairs and to select at least one switching sequence depending on a set of a current value of the DAC feedback input value (DAC Level) and a current value of the offset voltage (V offset) of the chopper voltage reference circuit. to associate each set with a different switching sequence, for each switching sequence, to independently perform said cyclical rotating of said plurality of capacitor pairs and to select at least one switching sequence depending on a set of a current value of the DAC feedback input value (DAC Level) and a current value of the offset voltage (V offset) of the chopper voltage reference circuit.