A power combiner for coupling and/or splitting high-frequency signals having a frequency greater than 1 MHz to an output power greater than 100W, wherein the power combiner has: a) a first input for a first high-frequency signal; b) a second input for a second high-frequency signal; c) an output; d) a balancing connection; e) a first electrical conductor between the first input and the output, wherein the first electrical conductor is designed largely in the form of a planar surface electrode; f) a second electrical conductor between the second input and the balancing connection, wherein the second electrical conductor is designed largely in the form of a planar surface electrode and wherein the second electrical conductor is capacitively and inductively coupled to the first electrical conductor, and - a dielectric, in particular in the form of a printed circuit board, is arranged between the electrical conductors (14, 16), - wherein a first electrically conductive layer is arranged on a first planar main side of the dielectric and a second electrically conductive layer is arranged on a second planar main side of the dielectric, which runs parallel to the first electrically conductive layer, - wherein the first electrical conductor and the second electrical conductor are each designed in sections and alternately in the first electrically conductive layer and the second electrically conductive layer, - wherein the first electrical conductor and the second electrical conductor are each designed in the form of surface electrodes, which each have sections (24a-d, 26a-d) that run alternately above and below the dielectric, - wherein the surface electrodes of the sections (24a-d) of the first electrical conductor each run congruently and coplanar with the sections (26a-d) of the second electrical conductor, g) a heat sink, - wherein the heat sink is connected to a ground of the power combiner, - so that a symmetrical parasitic capacitance is formed between the first electrical conductor and the heat sink and between the second electrical conductor and the heat sink due to the first and second electrical conductors (14, 16) running symmetrically to the dielectric. a) a first input for a first high-frequency signal; b) a second input for a second high-frequency signal; c) an output; d) a balancing connection; e) a first electrical conductor between the first input and the output, wherein the first electrical conductor is designed largely in the form of a planar surface electrode; f) a second electrical conductor between the second input and the balancing connection, wherein the second electrical conductor is designed largely in the form of a planar surface electrode and wherein the second electrical conductor is capacitively and inductively coupled to the first electrical conductor, and - a dielectric, in particular in the form of a printed circuit board, is arranged between the electrical conductors (14, 16), - wherein a first electrically conductive layer is arranged on a first planar main side of the dielectric and a second electrically conductive layer is arranged on a second planar main side of the dielectric, which runs parallel to the first electrically conductive layer, - wherein the first electrical conductor and the second electrical conductor are each designed in sections and alternately in the first electrically conductive layer and the second electrically conductive layer, - wherein the first electrical conductor and the second electrical conductor are each designed in the form of surface electrodes, which each have sections (24a-d, 26a-d) that run alternately above and below the dielectric, - wherein the surface electrodes of the sections (24a-d) of the first electrical conductor each run congruently and coplanar with the sections (26a-d) of the second electrical conductor, - a dielectric, in particular in the form of a printed circuit board, is arranged between the electrical conductors (14, 16), - wherein a first electrically conductive layer is arranged on a first planar main side of the dielectric and a second electrically conductive layer is arranged on a second planar main side of the dielectric, which runs parallel to the first electrically conductive layer, - wherein the first electrical conductor and the second electrical conductor are each designed in sections and alternately in the first electrically conductive layer and the second electrically conductive layer, - wherein the first electrical conductor and the second electrical conductor are each designed in the form of surface electrodes, which each have sections (24a-d, 26a-d) that run alternately above and below the dielectric, - wherein the surface electrodes of the sections (24a-d) of the first electrical conductor each run congruently and coplanar with the sections (26a-d) of the second electrical conductor, g) a heat sink, - wherein the heat sink is connected to a ground of the power combiner, - so that a symmetrical parasitic capacitance is formed between the first electrical conductor and the heat sink and between the second electrical conductor and the heat sink due to the first and second electrical conductors (14, 16) running symmetrically to the dielectric. - wherein the heat sink is connected to a ground of the power combiner, - so that a symmetrical parasitic capacitance is formed between the first electrical conductor and the heat sink and between the second electrical conductor and the heat sink due to the first and second electrical conductors (14, 16) running symmetrically to the dielectric.