An apparatus, comprising: a plurality of stacked memory die (101, 301, 401) adjacent to and coupled to one another; a logic die (302, 402, 502), wherein the plurality of stacked memory die (101, 301, 401) are interconnected to the logic die by through silicon vias, TSVs; wherein at least one memory die (101, 301, 401) comprises a plurality of partitioned banks (221, 321, 421, 521), each bank (221, 321, 421, 521) comprising: an array of memory cells (130, 330, 630); sensing circuitry (150, 350, 550, 650) coupled to the array (130, 330, 630), the sensing circuitry (150, 350, 550, 650) including a sense amplifier (606, 706) and a compute component (631, 731); and timing circuitry (233, 333, 533) coupled to the array (130, 330, 630) and sensing circuitry (150, 350, 550, 650), the timing circuitry (233, 333, 533) configured to control timing of operations for the sensing circuitry (150, 350, 550, 650); and wherein the logic die (302, 402, 502) comprises switching circuitry (323, 523) and control logic (231, 331, 531) coupled to the timing circuitry (223, 333, 533) and, wherein: the control logic (231, 331) is configured to execute instructions to cause the sensing circuitry (150, 350, 550, 650) to perform the operations; and the switching circuitry (323, 523) is configured to: route memory array requests received from a host (110, 510); and route processing in memory, PIM, requests received from the host (110, 510) to perform a logical operation using the sensing circuitry (150, 350, 550, 650). a plurality of stacked memory die (101, 301, 401) adjacent to and coupled to one another; a logic die (302, 402, 502), wherein the plurality of stacked memory die (101, 301, 401) are interconnected to the logic die by through silicon vias, TSVs; wherein at least one memory die (101, 301, 401) comprises a plurality of partitioned banks (221, 321, 421, 521), each bank (221, 321, 421, 521) comprising: an array of memory cells (130, 330, 630); sensing circuitry (150, 350, 550, 650) coupled to the array (130, 330, 630), the sensing circuitry (150, 350, 550, 650) including a sense amplifier (606, 706) and a compute component (631, 731); and timing circuitry (233, 333, 533) coupled to the array (130, 330, 630) and sensing circuitry (150, 350, 550, 650), the timing circuitry (233, 333, 533) configured to control timing of operations for the sensing circuitry (150, 350, 550, 650); and an array of memory cells (130, 330, 630); sensing circuitry (150, 350, 550, 650) coupled to the array (130, 330, 630), the sensing circuitry (150, 350, 550, 650) including a sense amplifier (606, 706) and a compute component (631, 731); and timing circuitry (233, 333, 533) coupled to the array (130, 330, 630) and sensing circuitry (150, 350, 550, 650), the timing circuitry (233, 333, 533) configured to control timing of operations for the sensing circuitry (150, 350, 550, 650); and wherein the logic die (302, 402, 502) comprises switching circuitry (323, 523) and control logic (231, 331, 531) coupled to the timing circuitry (223, 333, 533) and, wherein: the control logic (231, 331) is configured to execute instructions to cause the sensing circuitry (150, 350, 550, 650) to perform the operations; and the switching circuitry (323, 523) is configured to: route memory array requests received from a host (110, 510); and route processing in memory, PIM, requests received from the host (110, 510) to perform a logical operation using the sensing circuitry (150, 350, 550, 650). the control logic (231, 331) is configured to execute instructions to cause the sensing circuitry (150, 350, 550, 650) to perform the operations; and the switching circuitry (323, 523) is configured to: route memory array requests received from a host (110, 510); and route processing in memory, PIM, requests received from the host (110, 510) to perform a logical operation using the sensing circuitry (150, 350, 550, 650). route memory array requests received from a host (110, 510); and route processing in memory, PIM, requests received from the host (110, 510) to perform a logical operation using the sensing circuitry (150, 350, 550, 650).