A semiconductor device (1, 2), comprising: an SiC semiconductor substrate having a trench formed in one main surface; a first insulating film arranged on and in contact with a wall surface of said trench; a gate electrode arranged on and in contact with said first insulating film; and a first interconnection arranged on said one main surface, said semiconductor substrate including a drift layer having a first conductivity type, and a body layer having a second conductivity type, which is arranged on said drift layer, said trench being formed to penetrate said body layer and to reach said drift layer, said trench including an outer peripheral trench arranged to surround an active region, a potential fixing region where said body layer is exposed being formed in said one main surface opposite to said active region when viewed from said outer peripheral trench, said first interconnection being arranged to lie over said active region, said potential fixing region being electrically connected to said first interconnection, and wherein in a region of said drift layer in contact with said outer peripheral trench, an electric field relaxing region having the second conductivity type is formed, said electric field relaxing region is connected to said potential fixing region, the impurity concentration value of impurity having the second conductivity type in the electric field relaxing region is higher than the impurity concentration value having the first conductivity type in the drift layer, further comprising: an interlayer insulating film which is arranged on said potential fixing region; a second interconnection which is arranged on said interlayer insulating film to lie over said potential fixing region; and a gate electrode which is formed to bury said outer periphery trench, said first interconnection being formed to lie over said potential fixing region, and said second interconnection being formed to lie over said gate electrode which is located at the side of said active region when viewed from said potential fixing region. an SiC semiconductor substrate having a trench formed in one main surface; a first insulating film arranged on and in contact with a wall surface of said trench; a gate electrode arranged on and in contact with said first insulating film; and a first interconnection arranged on said one main surface, said semiconductor substrate including a drift layer having a first conductivity type, and a body layer having a second conductivity type, which is arranged on said drift layer, said trench being formed to penetrate said body layer and to reach said drift layer, said trench including an outer peripheral trench arranged to surround an active region, a potential fixing region where said body layer is exposed being formed in said one main surface opposite to said active region when viewed from said outer peripheral trench, said first interconnection being arranged to lie over said active region, said potential fixing region being electrically connected to said first interconnection, and wherein in a region of said drift layer in contact with said outer peripheral trench, an electric field relaxing region having the second conductivity type is formed, said electric field relaxing region is connected to said potential fixing region, the impurity concentration value of impurity having the second conductivity type in the electric field relaxing region is higher than the impurity concentration value having the first conductivity type in the drift layer, further comprising: an interlayer insulating film which is arranged on said potential fixing region; a second interconnection which is arranged on said interlayer insulating film to lie over said potential fixing region; and a gate electrode which is formed to bury said outer periphery trench, said first interconnection being formed to lie over said potential fixing region, and said second interconnection being formed to lie over said gate electrode which is located at the side of said active region when viewed from said potential fixing region. an interlayer insulating film which is arranged on said potential fixing region; a second interconnection which is arranged on said interlayer insulating film to lie over said potential fixing region; and a gate electrode which is formed to bury said outer periphery trench, said first interconnection being formed to lie over said potential fixing region, and said second interconnection being formed to lie over said gate electrode which is located at the side of said active region when viewed from said potential fixing region.