A thin film transistor comprising: an oxide semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, and a drain electrode formed on a substrate in a coplanar configuration, wherein the source electrode and the drain electrode are disposed on the second insulating layer; a first conductive member in direct contact with the oxide semiconductor layer and in direct contact with the source electrode; a second conductive member in direct contact with the oxide semiconductor layer and in direct contact with the drain electrode, wherein the first and the second conductive members (131, 132) are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes (181, 182); and an insulating member between the first and second conductive members (131, 132) and on the channel region of the oxide semiconductor layer, wherein the first conductive member, the insulating member, and the second conductive member disposed on the same plane and have the same thickness, wherein the first conductive member is on a source region of the oxide semiconductor layer and the second conductive member is on a drain region of the oxide semiconductor layer, wherein the first and second conductive members (131, 132) comprise an oxidizable metal having an electron mobility higher than that of the material of the oxide semiconductor layer and the insulating member comprises a corresponding oxide of the oxidizable metal constituting the first and second conductive members (131, 132), wherein the first insulating layer is formed of a material different from the insulating member, wherein the first insulating layer is disposed between the oxide semiconductor layer and the gate electrode, wherein the insulating member is disposed between the oxide semiconductor layer and the first insulating layer, configured to act as a double-insulating layer between the oxide semiconductor layer and the gate electrode with the first insulating layer, and wherein a thickness of the double-insulating layer is a sum of a thickness of the insulating member and a thickness of the first insulating layer. an oxide semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, and a drain electrode formed on a substrate in a coplanar configuration, wherein the source electrode and the drain electrode are disposed on the second insulating layer; a first conductive member in direct contact with the oxide semiconductor layer and in direct contact with the source electrode; a second conductive member in direct contact with the oxide semiconductor layer and in direct contact with the drain electrode, wherein the first and the second conductive members (131, 132) are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes (181, 182); and an insulating member between the first and second conductive members (131, 132) and on the channel region of the oxide semiconductor layer, wherein the first conductive member, the insulating member, and the second conductive member disposed on the same plane and have the same thickness, wherein the first conductive member is on a source region of the oxide semiconductor layer and the second conductive member is on a drain region of the oxide semiconductor layer, wherein the first and second conductive members (131, 132) comprise an oxidizable metal having an electron mobility higher than that of the material of the oxide semiconductor layer and the insulating member comprises a corresponding oxide of the oxidizable metal constituting the first and second conductive members (131, 132), wherein the first insulating layer is formed of a material different from the insulating member, wherein the first insulating layer is disposed between the oxide semiconductor layer and the gate electrode, wherein the insulating member is disposed between the oxide semiconductor layer and the first insulating layer, configured to act as a double-insulating layer between the oxide semiconductor layer and the gate electrode with the first insulating layer, and wherein a thickness of the double-insulating layer is a sum of a thickness of the insulating member and a thickness of the first insulating layer.