A method for manufacturing a semiconductor device comprising: forming a first semiconductor circuit comprising devices in a first surface of a first semiconductor substrate and a first multi-wiring layer on the first surface; forming a second semiconductor integrated circuit comprising devices in a first surface of a second semiconductor substrate and a second multi-wiring layer on the first surface of the second semiconductor substrate; forming a hole from the first surface of the second semiconductor substrate to an intermediate point in the second semiconductor substrate depositing copper, tungsten, or polysilicon in the hole to form a deposited connection conductor; thereafter, bonding the first semiconductor substrate with the second semiconductor substrate; thereafter, thinning the second semiconductor substrate after the bonding step to expose the hole at a second surface of the second semiconductor substrate, wherein the second surface is opposite the first surface of the second semiconductor substrate; forming a connection through-hole in the first semiconductor substrate, wherein the connection through-hole extends from a second surface of the first semiconductor substrate, wherein the second surface of the first semiconductor substrate is facing away from the second semiconductor substrate, to an uppermost wiring layer of the second multi-wiring layer through the first semiconductor substrate; forming a connection hole in the first semiconductor substrate, wherein the connection hole extends from the second surface of the first semiconductor substrate to the first multi-wiring layer; forming a through-connection conductor embedded in the connection through-hole; forming a connection conductor embedded in the connection hole; forming a connection wiring on the second surface of the first semiconductor substrate to make a connection between the through-connection conductor and the connection conductor; forming a bump at the second surface of the second semiconductor substrate, the bump being configured to electrically connect the first semiconductor circuit in the first semiconductor substrate through the connection conductor, the connection wiring, the through-connection conductor and the deposited connection conductor with an external wiring by bonding, such that the first and second multi-wiring layers face each other, wherein a bonding surface of each of the first and second semiconductors includes one of a plasma TEOS film, a plasma SiN film, a SiON film, or an SiC film, wherein the connection conductor is electrically connected to a metal at a lowest metal layer of the first multi-wiring layer, the lowest metal layer being a metal layer of the first multi-wiring layer that is farthest from the second semiconductor substrate. forming a first semiconductor circuit comprising devices in a first surface of a first semiconductor substrate and a first multi-wiring layer on the first surface; forming a second semiconductor integrated circuit comprising devices in a first surface of a second semiconductor substrate and a second multi-wiring layer on the first surface of the second semiconductor substrate; forming a hole from the first surface of the second semiconductor substrate to an intermediate point in the second semiconductor substrate depositing copper, tungsten, or polysilicon in the hole to form a deposited connection conductor; thereafter, bonding the first semiconductor substrate with the second semiconductor substrate; thereafter, thinning the second semiconductor substrate after the bonding step to expose the hole at a second surface of the second semiconductor substrate, wherein the second surface is opposite the first surface of the second semiconductor substrate; forming a connection through-hole in the first semiconductor substrate, wherein the connection through-hole extends from a second surface of the first semiconductor substrate, wherein the second surface of the first semiconductor substrate is facing away from the second semiconductor substrate, to an uppermost wiring layer of the second multi-wiring layer through the first semiconductor substrate; forming a connection hole in the first semiconductor substrate, wherein the connection hole extends from the second surface of the first semiconductor substrate to the first multi-wiring layer; forming a through-connection conductor embedded in the connection through-hole; forming a connection conductor embedded in the connection hole; forming a connection wiring on the second surface of the first semiconductor substrate to make a connection between the through-connection conductor and the connection conductor; forming a bump at the second surface of the second semiconductor substrate, the bump being configured to electrically connect the first semiconductor circuit in the first semiconductor substrate through the connection conductor, the connection wiring, the through-connection conductor and the deposited connection conductor with an external wiring by bonding, such that the first and second multi-wiring layers face each other, wherein a bonding surface of each of the first and second semiconductors includes one of a plasma TEOS film, a plasma SiN film, a SiON film, or an SiC film, wherein the connection conductor is electrically connected to a metal at a lowest metal layer of the first multi-wiring layer, the lowest metal layer being a metal layer of the first multi-wiring layer that is farthest from the second semiconductor substrate.