A method of manufacturing an electronic display device, comprising the steps of: a) forming a plurality of chips, each comprising: - a plurality of electric connection areas (125, 126, 127, 128) arranged on a connection surface of the chip, and - at least one first pad arranged in the vicinity of the chip connection surface; b) forming a transfer substrate comprising, for each chip: - a plurality of electric connection areas (155, 156, 157, 158) arranged on a connection surface of the transfer substrate, and - at least one second pad arranged in the vicinity of the connection surface of the transfer substrate, one of the first and second pads being a permanent magnet and the other of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and c) affixing the chips to the transfer substrate by direct bonding to electrically connect the electric connection areas (125, 126, 127, 128) of each chip to the corresponding electric connection areas (155, 156, 157, 158) of the transfer substrate, by using the magnetic force between the first and second pads to align the electric connection areas of the chips with the corresponding electric connection areas of the transfer substrate, wherein, in each chip, the connection surface of the chip is planar, the electric connection areas (125, 126, 127, and 128) of the chip being flush with an external surface of a passivation layer of the chip, and wherein the connection surface of the transfer substrate is planar, the electric connection areas (155, 156, 157, 158) of the transfer substrate being flush with an external surface of a passivation layer of the transfer substrate, characterized in that each chip comprises a stack of a LED and of an active circuit for controlling the LED, the active circuit comprising a plurality of transistors and at least one capacitive element for holding a bias signal, for the individual control of LED. a) forming a plurality of chips, each comprising: - a plurality of electric connection areas (125, 126, 127, 128) arranged on a connection surface of the chip, and - at least one first pad arranged in the vicinity of the chip connection surface; - a plurality of electric connection areas (125, 126, 127, 128) arranged on a connection surface of the chip, and - at least one first pad arranged in the vicinity of the chip connection surface; b) forming a transfer substrate comprising, for each chip: - a plurality of electric connection areas (155, 156, 157, 158) arranged on a connection surface of the transfer substrate, and - at least one second pad arranged in the vicinity of the connection surface of the transfer substrate, one of the first and second pads being a permanent magnet and the other of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and - a plurality of electric connection areas (155, 156, 157, 158) arranged on a connection surface of the transfer substrate, and - at least one second pad arranged in the vicinity of the connection surface of the transfer substrate, one of the first and second pads being a permanent magnet and the other of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and c) affixing the chips to the transfer substrate by direct bonding to electrically connect the electric connection areas (125, 126, 127, 128) of each chip to the corresponding electric connection areas (155, 156, 157, 158) of the transfer substrate, by using the magnetic force between the first and second pads to align the electric connection areas of the chips with the corresponding electric connection areas of the transfer substrate, wherein, in each chip, the connection surface of the chip is planar, the electric connection areas (125, 126, 127, and 128) of the chip being flush with an external surface of a passivation layer of the chip, and wherein the connection surface of the transfer substrate is planar, the electric connection areas (155, 156, 157, 158) of the transfer substrate being flush with an external surface of a passivation layer of the transfer substrate, characterized in that each chip comprises a stack of a LED and of an active circuit for controlling the LED, the active circuit comprising a plurality of transistors and at least one capacitive element for holding a bias signal, for the individual control of LED.