An amplifier, comprising a first MOS transistor, a second MOS transistor, and a third MOS transistor, wherein a gate of the first MOS transistor is separately coupled to a signal input end and a bias voltage input end, a source of the first MOS transistor is coupled to a power supply, and a drain of the first MOS transistor is separately coupled to a source of the second MOS transistor and a source of the third MOS transistor, a drain of the third MOS transistor is coupled to the ground, and a drain of the second MOS transistor is coupled to a signal output end, wherein a gate of the second MOS transistor is used to make the second MOS transistor in a conductive state under control of a first gate control signal; a gate of the third MOS transistor is used to: under control of a second gate control signal, change a cut-off state or a conductive state of the third MOS transistor to perform bypass control on an alternating current signal that is output by the drain of the first MOS transistor, and to change a gain of the amplifier by dividing the alternating current signal from an output of the drain of the first MOS transistor; wherein the bias voltage input end is configured to receive a bias voltage; characterized in that when the third MOS transistor is in the cut-off state, the bias voltage received by the bias voltage input end is a first bias voltage; when the third MOS transistor is in the conductive state, the bias voltage received by the bias voltage input end is a second bias voltage, where the first bias voltage is greater than the second bias voltage, and wherein when the bias voltage input end receives the first bias voltage, the amplifier is in the first gain state; when the bias voltage input end receives the second bias voltage, the amplifier is in the second gain state, where the first gain is greater than the second gain, wherein the second bias voltage is determined according to the first bias voltage and a formula g m 2,max -( g m 2 + g m 3) to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end, wherein g m 2,max represents a transconductance of the second MOS transistor when the amplifier is in the first gain state; g m 2 represents a transconductance of the second MOS transistor when the amplifier is in the second gain state; g m 3 represents a transconductance of the third MOS transistor in the conductive state. a gate of the first MOS transistor is separately coupled to a signal input end and a bias voltage input end, a source of the first MOS transistor is coupled to a power supply, and a drain of the first MOS transistor is separately coupled to a source of the second MOS transistor and a source of the third MOS transistor, a drain of the third MOS transistor is coupled to the ground, and a drain of the second MOS transistor is coupled to a signal output end, wherein a gate of the second MOS transistor is used to make the second MOS transistor in a conductive state under control of a first gate control signal; a gate of the third MOS transistor is used to: under control of a second gate control signal, change a cut-off state or a conductive state of the third MOS transistor to perform bypass control on an alternating current signal that is output by the drain of the first MOS transistor, and to change a gain of the amplifier by dividing the alternating current signal from an output of the drain of the first MOS transistor; wherein the bias voltage input end is configured to receive a bias voltage; characterized in that when the third MOS transistor is in the cut-off state, the bias voltage received by the bias voltage input end is a first bias voltage; when the third MOS transistor is in the conductive state, the bias voltage received by the bias voltage input end is a second bias voltage, where the first bias voltage is greater than the second bias voltage, and wherein when the bias voltage input end receives the first bias voltage, the amplifier is in the first gain state; when the bias voltage input end receives the second bias voltage, the amplifier is in the second gain state, where the first gain is greater than the second gain, wherein the second bias voltage is determined according to the first bias voltage and a formula g m 2,max -( g m 2 + g m 3) to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end, wherein g m 2,max represents a transconductance of the second MOS transistor when the amplifier is in the first gain state; g m 2 represents a transconductance of the second MOS transistor when the amplifier is in the second gain state; g m 3 represents a transconductance of the third MOS transistor in the conductive state.