A memory array (FIG. 6A) comprising a first bit line, a first antifuse control line, a second antifuse control line and a first one time programming memory cell, wherein the first one time programming memory cell comprises: a first antifuse transistor (A1 in FIGS. 4A∼4C), wherein a first drain/source terminal of the first antifuse transistor is connected with the first bit line, and a gate terminal of the first antifuse transistor is connected with the first antifuse control line, wherein the gate terminal of the first antifuse transistor comprises a first gate oxide layer with a first part and a second part, and the first part is thinner than the second part; and a second antifuse transistor, wherein a first drain/source terminal of the second antifuse transistor is connected with a second drain/source terminal of the first antifuse transistor, a gate terminal of the second antifuse transistor is connected with the second antifuse control line, a second drain/source terminal of the second antifuse transistor is connected with the first bit line, wherein the gate terminal of the second antifuse transistor comprises a second gate oxide layer with a third part and a fourth part, and the third part is thinner than the fourth part, characterized in that wherein during a program cycle, a ground voltage is provided to the first bit line, and a program voltage is provided to the first antifuse control line and the second antifuse control line, wherein the program voltage is applied to both of the first antifuse transistor and the second antifuse transistor, so that a storing state of the first antifuse transistor or the second antifuse transistor is changed, wherein during a read cycle, the ground voltage is provided to the first bit line, a read voltage is provided to the first antifuse control line, and the ground voltage is provided to the second antifuse control line, so that the first antifuse transistor generates a first read current to the first bit line, wherein the first antifuse transistor is judged to have a first storing state or a second storing state according to the first read current, and one bit of a random code for a physically unclonable function technology is realized according to the first storing state or the second storing state of the first antifuse transistor. a first antifuse transistor (A1 in FIGS. 4A∼4C), wherein a first drain/source terminal of the first antifuse transistor is connected with the first bit line, and a gate terminal of the first antifuse transistor is connected with the first antifuse control line, wherein the gate terminal of the first antifuse transistor comprises a first gate oxide layer with a first part and a second part, and the first part is thinner than the second part; and a second antifuse transistor, wherein a first drain/source terminal of the second antifuse transistor is connected with a second drain/source terminal of the first antifuse transistor, a gate terminal of the second antifuse transistor is connected with the second antifuse control line, a second drain/source terminal of the second antifuse transistor is connected with the first bit line, wherein the gate terminal of the second antifuse transistor comprises a second gate oxide layer with a third part and a fourth part, and the third part is thinner than the fourth part, characterized in that wherein during a program cycle, a ground voltage is provided to the first bit line, and a program voltage is provided to the first antifuse control line and the second antifuse control line, wherein the program voltage is applied to both of the first antifuse transistor and the second antifuse transistor, so that a storing state of the first antifuse transistor or the second antifuse transistor is changed, wherein during a read cycle, the ground voltage is provided to the first bit line, a read voltage is provided to the first antifuse control line, and the ground voltage is provided to the second antifuse control line, so that the first antifuse transistor generates a first read current to the first bit line, wherein the first antifuse transistor is judged to have a first storing state or a second storing state according to the first read current, and one bit of a random code for a physically unclonable function technology is realized according to the first storing state or the second storing state of the first antifuse transistor.