A memory device, comprising: a plurality of NAND flash chips (150, 250, 170a, 170b, 170c,..., 170n), each of the plurality of NAND flash chips comprising a memory section, wherein each memory section comprises a plurality of pages, and wherein each NAND flash chip has a first storage capacity; a dynamic random access memory, DRAM, portion (255, 225, 270) in data communication with the NAND flash chips, the DRAM portion having a second storage capacity that is at least as large as the first storage capacity of each of the plurality of NAND flash chips; and a controller configured to use the plurality of NAND flash chips as swap space by: selecting one of the NAND flash chips as a currently selected NAND flash chip for writing data; selecting another one of the plurality of NAND flash chips as a queued NAND flash chip for writing data after the currently selected NAND flash chip is identified as full; copying all valid pages in the currently selected NAND flash chip and in the queued NAND flash chip into the DRAM portion to cache said valid pages in the DRAM portion; in response to a write request to a logical memory location that is mapped to a particular physical location in one of the NAND flash chips, allocating the currently selected NAND flash chip for writing to a particular page that includes the particular physical location, and executing the writing to the particular page of the allocated NAND flash chip, wherein reads and writes to pages, which were stored in the allocated NAND flash chip and the queued NAND flash chip, are served from the DRAM portion, and wherein new writes are made to the allocated NAND flash chip; and if a subsequent write request is received and the allocated NAND flash chip is full, allocating the queued NAND flash chip for writing in response to the subsequent write request and selecting a further NAND flash chip of the plurality of NAND flash chips as the queued NAND flash chip for writing data after the allocated NAND flash chip is identified as full. a plurality of NAND flash chips (150, 250, 170a, 170b, 170c,..., 170n), each of the plurality of NAND flash chips comprising a memory section, wherein each memory section comprises a plurality of pages, and wherein each NAND flash chip has a first storage capacity; a dynamic random access memory, DRAM, portion (255, 225, 270) in data communication with the NAND flash chips, the DRAM portion having a second storage capacity that is at least as large as the first storage capacity of each of the plurality of NAND flash chips; and a controller configured to use the plurality of NAND flash chips as swap space by: selecting one of the NAND flash chips as a currently selected NAND flash chip for writing data; selecting another one of the plurality of NAND flash chips as a queued NAND flash chip for writing data after the currently selected NAND flash chip is identified as full; copying all valid pages in the currently selected NAND flash chip and in the queued NAND flash chip into the DRAM portion to cache said valid pages in the DRAM portion; in response to a write request to a logical memory location that is mapped to a particular physical location in one of the NAND flash chips, allocating the currently selected NAND flash chip for writing to a particular page that includes the particular physical location, and executing the writing to the particular page of the allocated NAND flash chip, wherein reads and writes to pages, which were stored in the allocated NAND flash chip and the queued NAND flash chip, are served from the DRAM portion, and wherein new writes are made to the allocated NAND flash chip; and if a subsequent write request is received and the allocated NAND flash chip is full, allocating the queued NAND flash chip for writing in response to the subsequent write request and selecting a further NAND flash chip of the plurality of NAND flash chips as the queued NAND flash chip for writing data after the allocated NAND flash chip is identified as full. selecting one of the NAND flash chips as a currently selected NAND flash chip for writing data; selecting another one of the plurality of NAND flash chips as a queued NAND flash chip for writing data after the currently selected NAND flash chip is identified as full; copying all valid pages in the currently selected NAND flash chip and in the queued NAND flash chip into the DRAM portion to cache said valid pages in the DRAM portion; in response to a write request to a logical memory location that is mapped to a particular physical location in one of the NAND flash chips, allocating the currently selected NAND flash chip for writing to a particular page that includes the particular physical location, and executing the writing to the particular page of the allocated NAND flash chip, wherein reads and writes to pages, which were stored in the allocated NAND flash chip and the queued NAND flash chip, are served from the DRAM portion, and wherein new writes are made to the allocated NAND flash chip; and if a subsequent write request is received and the allocated NAND flash chip is full, allocating the queued NAND flash chip for writing in response to the subsequent write request and selecting a further NAND flash chip of the plurality of NAND flash chips as the queued NAND flash chip for writing data after the allocated NAND flash chip is identified as full.