A memory cell comprising: a phase hysteretic magnetic Josephson junction, PHMJJ, that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state; a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell; and at least one Josephson junction (14, 16) configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state, characterised in that the superconducting phase is a first superconducting phase, wherein the superconducting read-select device is configured as a magnetic-barrier Josephson junction, MBJJ, configured to provide a second superconducting phase in response to the read current to trigger the at least one Josephson junction, wherein the read current comprises a first read current (I BR) and a second read current (I WR) that are both provided to the memory cell during a read operation, wherein the first read current is provided to a node interconnecting the MBJJ and the PHMJJ to bias the at least one Josephson junction (14, 16) and the second read current is inductively coupled to the MBJJ to switch the MBJJ from a zero-state to a π -state to provide the second superconducting phase, and wherein the PHMJJ is configured to generate the superconducting phase in response to storing one of the first and second binary logic states, wherein the PHMJJ is configured to trigger the at least one Josephson junction during the read operation based on the superconducting phase, the read current, and the superconducting read-select device to provide a voltage having a first magnitude at an output of the memory cell, the first magnitude of the voltage being indicative of the one of the first and second binary logic states. a phase hysteretic magnetic Josephson junction, PHMJJ, that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state; a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell; and at least one Josephson junction (14, 16) configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state, characterised in that the superconducting phase is a first superconducting phase, wherein the superconducting read-select device is configured as a magnetic-barrier Josephson junction, MBJJ, configured to provide a second superconducting phase in response to the read current to trigger the at least one Josephson junction, wherein the read current comprises a first read current (I BR) and a second read current (I WR) that are both provided to the memory cell during a read operation, wherein the first read current is provided to a node interconnecting the MBJJ and the PHMJJ to bias the at least one Josephson junction (14, 16) and the second read current is inductively coupled to the MBJJ to switch the MBJJ from a zero-state to a π -state to provide the second superconducting phase, and wherein the PHMJJ is configured to generate the superconducting phase in response to storing one of the first and second binary logic states, wherein the PHMJJ is configured to trigger the at least one Josephson junction during the read operation based on the superconducting phase, the read current, and the superconducting read-select device to provide a voltage having a first magnitude at an output of the memory cell, the first magnitude of the voltage being indicative of the one of the first and second binary logic states.