An electrostatic discharge circuit connected to a power pad and a first node (g), the ESD circuit comprising: a RC circuit connected between the power pad and the first node (g), wherein the RC circuit is capable of providing a first control voltage (Va) and a second control voltage (Vb); and a first ESD current path connected between the power pad and the first node (g), wherein when the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage (Va) and the second control voltage (Vb) provided by the RC circuit, so that an ESD current flows from the power pad to the first node (g) through the first ESD current path; wherein the first ESD current path comprises a first P-type transistor and a first N-type transistor, a first drain/source terminal and a body terminal of the first P-type transistor are connected to the power pad, a gate terminal of the first P-type transistor receives the first control voltage (Va), a second drain/source terminal of the first P-type transistor is connected to a second node (d), a first drain/source terminal of the first N-type transistor is connected to the second node (d), a gate terminal of the first N-type transistor receives the second control voltage (Vb), and a second drain/source terminal and a body terminal of the first N-type transistor are connected to the first node (g); wherein the RC circuit includes: a first resistor and a second resistor and a capacitor bank, a first terminal of the first resistor is connected to the power pad, a second terminal of the first resistor is connected to a third node (a), a first terminal of the second resistor is connected to a fourth node (b), a second terminal of the second resistor is connected to the first node (g), a first terminal of the capacitor bank is connected to the third node (a), a second terminal of the capacitor bank is connected to the fourth node (b), the third node (a) outputs the first control voltage, and the fourth node (b) outputs the second control voltage; and characterised in that the capacitor bank is not connected to the second node (d). a RC circuit connected between the power pad and the first node (g), wherein the RC circuit is capable of providing a first control voltage (Va) and a second control voltage (Vb); and a first ESD current path connected between the power pad and the first node (g), wherein when the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage (Va) and the second control voltage (Vb) provided by the RC circuit, so that an ESD current flows from the power pad to the first node (g) through the first ESD current path; wherein the first ESD current path comprises a first P-type transistor and a first N-type transistor, a first drain/source terminal and a body terminal of the first P-type transistor are connected to the power pad, a gate terminal of the first P-type transistor receives the first control voltage (Va), a second drain/source terminal of the first P-type transistor is connected to a second node (d), a first drain/source terminal of the first N-type transistor is connected to the second node (d), a gate terminal of the first N-type transistor receives the second control voltage (Vb), and a second drain/source terminal and a body terminal of the first N-type transistor are connected to the first node (g); wherein the RC circuit includes: a first resistor and a second resistor and a capacitor bank, a first terminal of the first resistor is connected to the power pad, a second terminal of the first resistor is connected to a third node (a), a first terminal of the second resistor is connected to a fourth node (b), a second terminal of the second resistor is connected to the first node (g), a first terminal of the capacitor bank is connected to the third node (a), a second terminal of the capacitor bank is connected to the fourth node (b), the third node (a) outputs the first control voltage, and the fourth node (b) outputs the second control voltage; and characterised in that the capacitor bank is not connected to the second node (d).