An encoder module for encoding L-digit portions of a K-digit message into an N-digit coded message with P parity digits according to a non-binary linear block code, where L is an integer greater than one, K is a positive integer multiple of L, N is a positive integer multiple of L and is greater than K, P is N-K, the encoder module comprising: an input (Din) configured to receive the L-digit portions of the K-digit message; an output (Dout) configured to output the N-digit coded message; a shift register circuit coupled to the input and the output; a plurality of parity shift registers consisting of P/L parity shift registers (403, 403', 403") that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers (403, 403', 403") is coupled to the input (Din) of the encoder module, and an output of the last parity shift register (403") is coupled to the output (Dout) of the encoder module; and a feedback circuit comprising P/L parity generation modules, wherein an input of each of the parity generation modules is coupled to the output of a corresponding one of the parity shift registers (403, 403', 403") by a switch (S1, S2, S3, S4), and an output of each of the parity generation modules is coupled to an input of the first parity shift register, wherein each parity generation module generates L parity digits based on a generator polynomial, and wherein each corresponding one of the parity shift registers (403, 403', 403") corresponding to the parity generation module stores the L parity digits when the corresponding switch (S1, S2, S3, S4) is closed; wherein each parity generation module of the feedback circuit receives data from the corresponding parity shift register (403, 403', 403") and generates the L parity digits during one of (K/L) clock cycles of the encoder clock signal, and the one of the parity shift registers (403") is configured to forward information stored therein to the output during one of (K/L) + 2 to (N/L) + 1 clock cycles of the clock signal; and wherein the switches (S1, S2, S3, S4) are closed during the (K/L) clock cycles of the clock signal and the switches (S1, S2, S3, S4) are open during the (K/L) + 2 to (N/L) + 1 clock cycles of the clock signal. an input (Din) configured to receive the L-digit portions of the K-digit message; an output (Dout) configured to output the N-digit coded message; a shift register circuit coupled to the input and the output; a plurality of parity shift registers consisting of P/L parity shift registers (403, 403', 403") that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers (403, 403', 403") is coupled to the input (Din) of the encoder module, and an output of the last parity shift register (403") is coupled to the output (Dout) of the encoder module; and a feedback circuit comprising P/L parity generation modules, wherein an input of each of the parity generation modules is coupled to the output of a corresponding one of the parity shift registers (403, 403', 403") by a switch (S1, S2, S3, S4), and an output of each of the parity generation modules is coupled to an input of the first parity shift register, wherein each parity generation module generates L parity digits based on a generator polynomial, and wherein each corresponding one of the parity shift registers (403, 403', 403") corresponding to the parity generation module stores the L parity digits when the corresponding switch (S1, S2, S3, S4) is closed;