A cache apparatus comprising a plurality of data processing apparatuses, each of the plurality of data processing apparatuses including: a first pipeline which includes a plurality of first nodes (310, 330) and is adapted to shift an address held in one first node to another first node located in a first direction with respect to the one first node; a second pipeline which includes a plurality of second nodes (370, 380) and is adapted to shift a cache tag held in one second node to another second node located in a second direction opposite to the first direction with respect to the one second node, wherein each first node corresponds to one of the plurality of second nodes; and a comparison means, for each of the first nodes of the first pipeline, said comparison means comprising two comparison circuits (342, 344) which are adapted to simultaneously compare an address held in the respective first node with a cache tag held in a second node, to which the respective first node corresponds, and a cache tag held in a neighboring node of the second node, to which the respective first node corresponds, on an upstream side in the second direction, and said comparison means being adapted to determine whether or not the address matches any one of the cache tags; the cache apparatus further comprising: a cache memory which is adapted to store data; an acquisition means which is adapted to acquire a request of data from a processing apparatus; a first input means which is adapted to replicate an address of the acquired data, and to input the replicated address to the first pipelines of the plurality of data processing apparatuses; a second input means which is adapted to input a cache tag of data stored in the cache memory to the second pipeline of one of the plurality of data processing apparatuses; and a determination means which is adapted to determine, when the comparison means of one of the data processing apparatuses indicates a match, a cache hit of the acquired data, wherein the second pipelines of the plurality of data processing apparatuses are connected in series. a first pipeline which includes a plurality of first nodes (310, 330) and is adapted to shift an address held in one first node to another first node located in a first direction with respect to the one first node; a second pipeline which includes a plurality of second nodes (370, 380) and is adapted to shift a cache tag held in one second node to another second node located in a second direction opposite to the first direction with respect to the one second node, wherein each first node corresponds to one of the plurality of second nodes; and a comparison means, for each of the first nodes of the first pipeline, said comparison means comprising two comparison circuits (342, 344) which are adapted to simultaneously compare an address held in the respective first node with a cache tag held in a second node, to which the respective first node corresponds, and a cache tag held in a neighboring node of the second node, to which the respective first node corresponds, on an upstream side in the second direction, and said comparison means being adapted to determine whether or not the address matches any one of the cache tags; the cache apparatus further comprising: a cache memory which is adapted to store data; an acquisition means which is adapted to acquire a request of data from a processing apparatus; a first input means which is adapted to replicate an address of the acquired data, and to input the replicated address to the first pipelines of the plurality of data processing apparatuses; a second input means which is adapted to input a cache tag of data stored in the cache memory to the second pipeline of one of the plurality of data processing apparatuses; and a determination means which is adapted to determine, when the comparison means of one of the data processing apparatuses indicates a match, a cache hit of the acquired data, wherein the second pipelines of the plurality of data processing apparatuses are connected in series.