A device comprising: a multi-path, rectifying analog-to-digital converter, ADC, for converting an analog signal into a plurality of bits, the ADC comprising: a first path for determining a first bit in the plurality of bits, the first path comprising: a first comparator (410, 515, 1020) for generating the first bit, where the first comparator (410, 515, 1020) is configured to receive an analog signal at a first time; and a second path for determining second bits in the plurality of bits, the second path comprising: a rectifier (415, 525, 1040), where the rectifier (415, 525, 1040) is configured to receive the analog signal at a second time after the first time; an amplifier, wherein the rectifier is coupled to an output of the amplifier; and a plurality of second comparators (C28,...,C34) coupled to an output of the rectifier (415, 525, 1040), the plurality of second comparators being configured to generate the second bits; a signal hold circuit (405, 505, 1010) operating in parallel with the first comparator (410, 515, 1020) in the first path, wherein the amplifier is coupled to an output of the signal hold circuit (405, 505, 1010); characterized in that the first comparator comprises a first offset calibrator and the plurality of second comparators comprise a second offset calibrator, and wherein the first and second offset calibrators are configured to operate independent of one another to separately calibrate a first offset for the first comparator and a second offset for each comparator in the plurality of second comparators; further characterized in that the amplifier comprises a third offset calibrator configured to operate independent of the first and the second offset calibrators to separately calibrate a third offset for the amplifier. a multi-path, rectifying analog-to-digital converter, ADC, for converting an analog signal into a plurality of bits, the ADC comprising: a first path for determining a first bit in the plurality of bits, the first path comprising: a first comparator (410, 515, 1020) for generating the first bit, where the first comparator (410, 515, 1020) is configured to receive an analog signal at a first time; and a second path for determining second bits in the plurality of bits, the second a first comparator (410, 515, 1020) for generating the first bit, where the first comparator (410, 515, 1020) is configured to receive an analog signal at a first time; and a second path for determining second bits in the plurality of bits, the second path comprising: a rectifier (415, 525, 1040), where the rectifier (415, 525, 1040) is configured to receive the analog signal at a second time after the first time; an amplifier, wherein the rectifier is coupled to an output of the amplifier; and a plurality of second comparators (C28,...,C34) coupled to an output of the rectifier (415, 525, 1040), the plurality of second comparators being configured to generate the second bits; a signal hold circuit (405, 505, 1010) operating in parallel with the first comparator (410, 515, 1020) in the first path, wherein the amplifier is coupled to an output of the signal hold circuit (405, 505, 1010); a rectifier (415, 525, 1040), where the rectifier (415, 525, 1040) is configured to receive the analog signal at a second time after the first time; an amplifier, wherein the rectifier is coupled to an output of the amplifier; and a plurality of second comparators (C28,...,C34) coupled to an output of the rectifier (415, 525, 1040), the plurality of second comparators being configured to generate the second bits; a signal hold circuit (405, 505, 1010) operating in parallel with the first comparator (410, 515, 1020) in the first path, wherein the amplifier is coupled to an output of the signal hold circuit (405, 505, 1010); characterized in that the first comparator comprises a first offset calibrator and the plurality of second comparators comprise a second offset calibrator, and wherein the first and second offset calibrators are configured to operate independent of one another to separately calibrate a first offset for the first comparator and a second offset for each comparator in the plurality of second comparators; further characterized in that the amplifier comprises a third offset calibrator configured to operate independent of the first and the second offset calibrators to separately calibrate a third offset for the amplifier.