A method of fabricating a microelectronic transistor comprising: forming a microelectronic substrate; forming a source region and a drain region in the microelectronic substrate; forming an interlayer dielectric material over the microelectronic substrate; forming a source contact extending through the interlayer dielectric material and electrically contacting the source region; forming a drain contact extending through the interlayer dielectric material and electrically contacting the drain region; forming a gate electrode positioned between the source contact and the drain contact; forming airgap spacers positioned between the gate electrode and the source contact and between the gate electrode and the drain contact; forming a sacrificial material layer on the microelectronic substrate and forming a hard mask material layer on the sacrificial material layer prior to forming the source region and the drain region in the microelectronic substrate; patterning an etch block structure on the hard mask material layer, wherein the etch block structure has low etch selectivity to the hard mask material layer; etching the sacrificial material layer and the hard mask material layer to form a sacrificial gate material structure with a hard mask thereon, wherein the etch block structure shrinks during the etching process to form curved surfaces of the hard mask prior to forming of the interlayer dielectric material; planarizing the interlayer dielectric material to expose a portion of the hard mask; selectively etching a trench through a portion of the hard mask and a portion of the sacrificial gate material structure, wherein a portion of the interlayer dielectric material abutting the hard mask curved surfaces extends over and protects a portion of the hard mask and a portion of the sacrificial gate material structure that remains after the selective etching of the trench; forming a gate dielectric layer and the gate electrode in the trench, wherein the gate dielectric layer is disposed between the gate electrode and the microelectronic substrate; and removing the portion of the sacrificial gate material structure remaining after selectively etching the trench to form the airgap spacers. forming a microelectronic substrate; forming a source region and a drain region in the microelectronic substrate; forming an interlayer dielectric material over the microelectronic substrate; forming a source contact extending through the interlayer dielectric material and electrically contacting the source region; forming a drain contact extending through the interlayer dielectric material and electrically contacting the drain region; forming a gate electrode positioned between the source contact and the drain contact; forming airgap spacers positioned between the gate electrode and the source contact and between the gate electrode and the drain contact; forming a sacrificial material layer on the microelectronic substrate and forming a hard mask material layer on the sacrificial material layer prior to forming the source region and the drain region in the microelectronic substrate; patterning an etch block structure on the hard mask material layer, wherein the etch block structure has low etch selectivity to the hard mask material layer; etching the sacrificial material layer and the hard mask material layer to form a sacrificial gate material structure with a hard mask thereon, wherein the etch block structure shrinks during the etching process to form curved surfaces of the hard mask prior to forming of the interlayer dielectric material; planarizing the interlayer dielectric material to expose a portion of the hard mask; selectively etching a trench through a portion of the hard mask and a portion of the sacrificial gate material structure, wherein a portion of the interlayer dielectric material abutting the hard mask curved surfaces extends over and protects a portion of the hard mask and a portion of the sacrificial gate material structure that remains after the selective etching of the trench; forming a gate dielectric layer and the gate electrode in the trench, wherein the gate dielectric layer is disposed between the gate electrode and the microelectronic substrate; and removing the portion of the sacrificial gate material structure remaining after selectively etching the trench to form the airgap spacers.