A processor (112, 800, 970, 980,...) comprising: a processor core (114, 790) is configured to: initialize a trust domain, TD (150, 150A, 150B), and a trust domain resource manager, TDRM, to manage the TD (150, 150A, 150B); initialize a TD virtual machine monitor, TD-VMM, within the TD (150, 150A, 150B) to manage a plurality of TD virtual machines, TD-VMs (155A, 155B); responsive to receiving an instruction from the TDRM, exclusively associate a plurality of memory pages with the TD (150, 150A, 150B), wherein the plurality of memory pages are encrypted with a TD private encryption key inaccessible to the TDRM; and characterized in that the processor core (114, 790) is further configured to: deploy a secure arbitration mode, SEAM, module interfacing with the TDRM and the plurality of TD-VMs (155A, 155B) to enable a SEAM of the processor (112, 800, 970, 980,...), the SEAM being assigned a SEAM range of memory comprising one or more memory pages wherein the SEAM module is configured to encrypt/decrypt the memory pages in the SEAM range of memory using a SEAM private encryption key inaccessible to the TDRM; and control access to the SEAM private encryption key to ensure that the SEAM private encryption key cannot be accessed by the TDRM; wherein the processor (112, 800, 970, 980,...) further comprises one or more registers to store: an identifier of the SEAM range of memory; and a TD key identifier, key ID, identifying the TD private encryption key. a processor core (114, 790) is configured to: initialize a trust domain, TD (150, 150A, 150B), and a trust domain resource manager, TDRM, to manage the TD (150, 150A, 150B); initialize a TD virtual machine monitor, TD-VMM, within the TD (150, 150A, 150B) to manage a plurality of TD virtual machines, TD-VMs (155A, 155B); responsive to receiving an instruction from the TDRM, exclusively associate a plurality of memory pages with the TD (150, 150A, 150B), wherein the plurality of memory pages are encrypted with a TD private encryption key inaccessible to the TDRM; and initialize a trust domain, TD (150, 150A, 150B), and a trust domain resource manager, TDRM, to manage the TD (150, 150A, 150B); initialize a TD virtual machine monitor, TD-VMM, within the TD (150, 150A, 150B) to manage a plurality of TD virtual machines, TD-VMs (155A, 155B); responsive to receiving an instruction from the TDRM, exclusively associate a plurality of memory pages with the TD (150, 150A, 150B), wherein the plurality of memory pages are encrypted with a TD private encryption key inaccessible to the TDRM; and characterized in that the processor core (114, 790) is further configured to: deploy a secure arbitration mode, SEAM, module interfacing with the TDRM and the plurality of TD-VMs (155A, 155B) to enable a SEAM of the processor (112, 800, 970, 980,...), the SEAM being assigned a SEAM range of memory comprising one or more memory pages wherein the SEAM module is configured to encrypt/decrypt the memory pages in the SEAM range of memory using a SEAM private encryption key inaccessible to the TDRM; and control access to the SEAM private encryption key to ensure that the SEAM private encryption key cannot be accessed by the TDRM; wherein the processor (112, 800, 970, 980,...) further comprises one or more registers to store: an identifier of the SEAM range of memory; and a TD key identifier, key ID, identifying the TD private encryption key. deploy a secure arbitration mode, SEAM, module interfacing with the TDRM and the plurality of TD-VMs (155A, 155B) to enable a SEAM of the processor (112, 800, 970, 980,...), the SEAM being assigned a SEAM range of memory comprising one or more memory pages wherein the SEAM module is configured to encrypt/decrypt the memory pages in the SEAM range of memory using a SEAM private encryption key inaccessible to the TDRM; and control access to the SEAM private encryption key to ensure that the SEAM private encryption key cannot be accessed by the TDRM; wherein the processor (112, 800, 970, 980,...) further comprises one or more registers to store: an identifier of the SEAM range of memory; and a TD key identifier, key ID, identifying the TD private encryption key. an identifier of the SEAM range of memory; and a TD key identifier, key ID, identifying the TD private encryption key.