Memory arrangement, comprising - a non-volatile memory plane, - a replacement plane, - an address select block, - an address replacement plane, and - a counter arrangement comprising a first number N of counters (310 to 312), wherein the non-volatile memory plane comprises a second number M of preselected bit cells with the second number M equal or smaller than the first number N, wherein one of the first number N of counters (310 to 312) is incremented at a write cycle of a corresponding preselected bit cell of the second number M of preselected bit cells and the address select block switches from the preselected bit cell to a corresponding replacement bit cell of the replacement plane, if the counter value of said counter (310 to 312) is higher than a predetermined limit corresponding to said preselected bit cell, wherein the address replacement plane stores the addresses of the second number M of preselected bit cells, wherein the addresses of the second number M of preselected bit cells are determined in a test phase, the test phase is before an operation phase and the preselected bit cells are not changed in the operation phase, wherein an erase test and a program test are performed in the test phase, wherein the erase test of a bit cell is performed by - programming the bit cell, - determining a first value (Icelll) of a bit cell current (ICELL) flowing through the bit cell, - providing an erase pulse to the bit cell, - determining a second value (IcellO) of the bit cell current (ICELL) flowing through the bit cell and - setting the bit cell as a preselected bit cell, if the difference (ΔI) between the first value (Icelll) and the second value (IcellO) of the bit cell current (ICELL) is outside of a first predetermined current range, wherein the program test of the bit cell is performed by - erasing the bit cell, - determining a first value (Icelll) of the bit cell current (ICELL) flowing through the bit cell, - providing a programming pulse to the bit cell, - determining a second value (IcellO) of the bit cell current (ICELL) flowing through the bit cell and - setting the bit cell as a preselected bit cell, if the difference (ΔI) between the first value (Icelll) and the second value (IcellO) of the bit cell current (ICELL) is outside of a first predetermined current range, and wherein an information about the predetermined limit of write cycles is stored for the preselected bit cell in the address replacement plane depending on the result of the erase test and/or on the result of the program test of the preselected bit cell. - a non-volatile memory plane, - a replacement plane, - an address select block, - an address replacement plane, and - a counter arrangement comprising a first number N of counters (310 to 312), wherein the non-volatile memory plane comprises a second number M of preselected bit cells with the second number M equal or smaller than the first number N, wherein one of the first number N of counters (310 to 312) is incremented at a write cycle of a corresponding preselected bit cell of the second number M of preselected bit cells and the address select block switches from the preselected bit cell to a corresponding replacement bit cell of the replacement plane, if the counter value of said counter (310 to 312) is higher than a predetermined limit corresponding to said preselected bit cell, wherein the address replacement plane stores the addresses of the second number M of preselected bit cells, wherein the addresses of the second number M of preselected bit cells are determined in a test phase, the test phase is before an operation phase and the preselected bit cells are not changed in the operation phase, wherein an erase test and a program test are performed in the test phase, wherein the erase test of a bit cell is performed by - programming the bit cell, - determining a first value (Icelll) of a bit cell current (ICELL) flowing through the bit cell, - providing an erase pulse to the bit cell, - determining a second value (IcellO) of the bit cell current (ICELL) flowing through the bit cell and - setting the bit cell as a preselected bit cell, if the difference (ΔI) between the first value (Icelll) and the second value (IcellO) of the bit cell current (ICELL) is outside of a first predetermined current range, wherein the program test of the bit cell is performed by - erasing the bit cell, - determining a first value (Icelll) of the bit cell current (ICELL) flowing through the bit cell, - providing a programming pulse to the bit cell, - determining a second value (IcellO) of the bit cell current (ICELL) flowing through the bit cell and - setting the bit cell as a preselected bit cell, if the difference (ΔI) between the first value (Icelll) and the second value (IcellO) of the bit cell current (ICELL) is outside of a first predetermined current range, and wherein an information about the predetermined limit of write cycles is stored for the preselected bit cell in the address replacement plane depending on the result of the erase test and/or on the result of the program test of the preselected bit cell.