A receiver for receiving a plurality of data bits comprising: a forward strobe clock recovery circuit (112) configurable to align a forward strobe sampling clock (DQSrclk) with a received forward strobe clock by generating a forward strobe clock offset (DQSPC) which represents the number of delays required to achieve alignment of the forward strobe sampling clock (DQSrclk) and the received forward strobe clock; and at least one data bit clock recovery circuit (113()) configurable to align a data bit sampling clock (DQrclk) with a received data bit (DQ()) wherein the receiver operates in one of a normal operation, a training phase for the forward strobe clock recovery circuit (112), or a training phase for the data bit clock recovery circuit (113()); wherein the training phase for the forward strobe clock recovery circuit (112) occurs before the training phase for the data bit clock recovery circuit (113()) and normal operation; wherein during the training phase for the data bit clock recovery circuit (113()) the forward strobe clock recovery circuit (112) is inactive and the at least one data bit clock recovery circuit (113()) is active, and the data bit sampling clock (DQrclk) is aligned with a received data bit (DQ()) by a data bit clock offset with the at least one data bit clock recovery circuit (113()), and wherein the data bit clock offset includes an intermediate data bit clock offset (DQPC()) combined with the forward strobe clock offset (DQSPC), wherein the intermediate data bit clock offset (DQPC) is determined from a phase difference between the data bit sampling clock and the received data bit; and wherein during normal operation of the receiver, the at least one data bit clock recovery circuit (113()) is inactive, the forward strobe clock recovery circuit is active, the intermediate data bit clock offset (DQPC()) is fixed, and the data bit clock offset varies with the forward strobe clock offset (DQSPC); and wherein during the training phase for the forward strobe clock recovery circuit the forward strobe clock recovery circuit (112) is active, the at least one data bit clock recovery circuit is inactive, and the forward strobe clock recovery circuit aligns the forward strobe sampling clock (DQSrclk) with the received forward strobe clock. a forward strobe clock recovery circuit (112) configurable to align a forward strobe sampling clock (DQSrclk) with a received forward strobe clock by generating a forward strobe clock offset (DQSPC) which represents the number of delays required to achieve alignment of the forward strobe sampling clock (DQSrclk) and the received forward strobe clock; and at least one data bit clock recovery circuit (113()) configurable to align a data bit sampling clock (DQrclk) with a received data bit (DQ()) wherein the receiver operates in one of a normal operation, a training phase for the forward strobe clock recovery circuit (112), or a training phase for the data bit clock recovery circuit (113()); wherein the training phase for the forward strobe clock recovery circuit (112) occurs before the training phase for the data bit clock recovery circuit (113()) and normal operation; wherein during the training phase for the data bit clock recovery circuit (113()) the forward strobe clock recovery circuit (112) is inactive and the at least one data bit clock recovery circuit (113()) is active, and the data bit sampling clock (DQrclk) is aligned with a received data bit (DQ()) by a data bit clock offset with the at least one data bit clock recovery circuit (113()), and wherein the data bit clock offset includes an intermediate data bit clock offset (DQPC()) combined with the forward strobe clock offset (DQSPC), wherein the intermediate data bit clock offset (DQPC) is determined from a phase difference between the data bit sampling clock and the received data bit; and wherein during normal operation of the receiver, the at least one data bit clock recovery circuit (113()) is inactive, the forward strobe clock recovery circuit is active, the intermediate data bit clock offset (DQPC()) is fixed, and the data bit clock offset varies with the forward strobe clock offset (DQSPC); and wherein during the training phase for the forward strobe clock recovery circuit the forward strobe clock recovery circuit (112) is active, the at least one data bit clock recovery circuit is inactive, and the forward strobe clock recovery circuit aligns the forward strobe sampling clock (DQSrclk) with the received forward strobe clock.