A method to achieve a fully differential amplifier operating in class AB mode, comprising an arrangement for a differential drive intermediate stage to control a differential loop, a common mode regulation and class AB regulation, comprising the following steps: providing a fully differential amplifier operating in class AB mode comprising ports for differential input error signals Vip and Vim and for differential output signals Vop and Vom, wherein Vop is generated by a first output branch (M12, M5) of an output stage and Vom is generated by a second output branch (M11, M6) of the output stage wherein each output branch comprises high side (M11, M12) and low side transistors (M6, M5), wherein the amplifier comprises an intermediate stage processing the input signals; splitting the intermediate stage into two simple differential stages, wherein a first (M1, M2) of these differential stages controls the low side transistors (M5, M6) and a second differential stage (M3, M4) controls the high side transistors (M11, M12) thus enabling differential output regulation by introducing dual differentiation of the input error signal to support common mode regulation by splitting driving signals of a first transistor of each of said output branch from a control path of a second transistor of each of said output branch; reducing a common mode error by decreasing both voltages Vop and Vom if a differential output common mode (CMFB) is higher than a common mode reference (VREF), wherein a pair of NMOS transistors (M13/M14) compares the differential common mode (CMFB) with the common mode reference (VREF) and reduces the common mode error via said first and second differential stages; and regulating quiescent currents of both output branches inside the amplifier by sensing a current of a transistor (M5/M12, M6/M11) of each output branch conducting the smallest current, comparing it with an internal reference current (IREF) in order to regulate the quiescent current, wherein said regulation of the quiescent current is performed by having each output branch being connected to a respective active load and feeding back a result of the comparison of the smallest current of each transistor (M5/M12, M6/M11) of each output branch with the internal reference current (IREF) to the respective active loads, thus decreasing voltages at corresponding nodes of each output branch and thus decreasing the quiescent currents. providing a fully differential amplifier operating in class AB mode comprising ports for differential input error signals Vip and Vim and for differential output signals Vop and Vom, wherein Vop is generated by a first output branch (M12, M5) of an output stage and Vom is generated by a second output branch (M11, M6) of the output stage wherein each output branch comprises high side (M11, M12) and low side transistors (M6, M5), wherein the amplifier comprises an intermediate stage processing the input signals; splitting the intermediate stage into two simple differential stages, wherein a first (M1, M2) of these differential stages controls the low side transistors (M5, M6) and a second differential stage (M3, M4) controls the high side transistors (M11, M12) thus enabling differential output regulation by introducing dual differentiation of the input error signal to support common mode regulation by splitting driving signals of a first transistor of each of said output branch from a control path of a second transistor of each of said output branch; reducing a common mode error by decreasing both voltages Vop and Vom if a differential output common mode (CMFB) is higher than a common mode reference (VREF), wherein a pair of NMOS transistors (M13/M14) compares the differential common mode (CMFB) with the common mode reference (VREF) and reduces the common mode error via said first and second differential stages; and regulating quiescent currents of both output branches inside the amplifier by sensing a current of a transistor (M5/M12, M6/M11) of each output branch conducting the smallest current, comparing it with an internal reference current (IREF) in order to regulate the quiescent current, wherein said regulation of the quiescent current is performed by having each output branch being connected to a respective active load and feeding back a result of the comparison of the smallest current of each transistor (M5/M12, M6/M11) of each output branch with the internal reference current (IREF) to the respective active loads, thus decreasing voltages at corresponding nodes of each output branch and thus decreasing the quiescent currents.