A N-time time interleaved digital-to-analog converter, DAC, comprising: a first set of N/2 DACs and N/2 replica DACs configured to operate at a clock A having a frequency FS/2, a second set of N/2 DACs and N/2 replica DACs configured to operate at a clock B, having the frequency FS/2, and wherein N is at least two, and wherein an output of the first set of N/2 DACs and an output of the second set of N/2 DACs are input to a multiplexer configured to operate according to a multiplexer clock signal (CLOCK_MUX) at a multiplexer frequency, and to generate the output of the N-time interleaved DAC, a phase detector connected to the first set of N/2 replica DACs and the second set of N/2 replica DACs, where the first set of N/2 replica DACs and the second set of N/2 replica DACs form a data path replication circuit which mimic the delay that the data path of the first set of N/2 DACs and the second set of N/2 DACs goes through; said first set of N/2 replica DACs being configured to process an input DATA-RA and said second set of N/2 replica DACs being configured to process an input DATA-RB, wherein either a) the first set of N/2 replica DACs is configured to process the input DATA_RA having a FS/4 in-phase clock signal, (FS4-I) and the second set of N/2 replica DACs is configured to process the input DATA_RB having a FS/4 quadrature-phase clock signal (FS4-Q) or b) the first set of N/2 replica DACs is configured to process the input DATA_RA having a having a FS/4 quadrature-phase clock signal (FS4-Q) and the second set of N/2 replica DACs is configured to process the input DATA_RB having a FS/4 in-phase clock signal, (FS4-I) the phase detector configured to generate a phase detection output (PD_OUT) by comparing first outputs of the first set of N/2 replica DACs and second outputs of the second set of N/2 replica DACs with the multiplexer clock signal (MUX_CLOCK), wherein the multiplexer frequency is a multiple of the clock A or the clock B, wherein phases of the clock A and the clock B are advanced until the phase detection output (PD_OUT) indicates alignment. a first set of N/2 DACs and N/2 replica DACs configured to operate at a clock A having a frequency FS/2, a second set of N/2 DACs and N/2 replica DACs configured to operate at a clock B, having the frequency FS/2, and wherein N is at least two, and wherein an output of the first set of N/2 DACs and an output of the second set of N/2 DACs are input to a multiplexer configured to operate according to a multiplexer clock signal (CLOCK_MUX) at a multiplexer frequency, and to generate the output of the N-time interleaved DAC, a phase detector connected to the first set of N/2 replica DACs and the second set of N/2 replica DACs, where the first set of N/2 replica DACs and the second set of N/2 replica DACs form a data path replication circuit which mimic the delay that the data path of the first set of N/2 DACs and the second set of N/2 DACs goes through; said first set of N/2 replica DACs being configured to process an input DATA-RA and said second set of N/2 replica DACs being configured to process an input DATA-RB, wherein either a) the first set of N/2 replica DACs is configured to process the input DATA_RA having a FS/4 in-phase clock signal, (FS4-I) and the second set of N/2 replica DACs is configured to process the input DATA_RB having a FS/4 quadrature-phase clock signal (FS4-Q) or b) the first set of N/2 replica DACs is configured to process the input DATA_RA having a having a FS/4 quadrature-phase clock signal (FS4-Q) and a) the first set of N/2 replica DACs is configured to process the input DATA_RA having a FS/4 in-phase clock signal, (FS4-I) and the second set of N/2 replica DACs is configured to process the input DATA_RB having a FS/4 quadrature-phase clock signal (FS4-Q) or b) the first set of N/2 replica DACs is configured to process the input DATA_RA having a having a FS/4 quadrature-phase clock signal (FS4-Q) and the second set of N/2 replica DACs is configured to process the input DATA_RB having a FS/4 in-phase clock signal, (FS4-I) the phase detector configured to generate a phase detection output (PD_OUT) by comparing first outputs of the first set of N/2 replica DACs and second outputs of the second set of N/2 replica DACs with the multiplexer clock signal (MUX_CLOCK), wherein the multiplexer frequency is a multiple of the clock A or the clock B, wherein phases of the clock A and the clock B are advanced until the phase detection output (PD_OUT) indicates alignment.