A computer program-implemented method for defining an integrated circuit on a base array, comprising: identifying a standard cell used in a netlist for the integrated circuit, wherein the standard cell has corresponding target performance specifications for leakage, speed, and power consumption; determining a logic function of the identified standard cell; identifying one or more primitive logic cells from within a primitive library as needed to duplicate the determined logic function of the identified standard cell, the one or more primitive logic cells defined based on specifications of the base array, wherein the primitive library includes fourteen primitive logic cells including 1) a two input NAND gate, 2) a three input NAND gate, 3) a two input NOR gate, 4) a three input NOR gate, 5) a pass gate, 6) a latch element, 7) a single PMOS stack, 8) a double PMOS stack, 9) a triple PMOS stack, 10) a single NMOS stack, 11) a double NMOS stack, 12) a triple NMOS stack, 13) an inverter, and 14) a tri-state inverter, wherein the primitive logic cells within the primitive library are defined based on transistor device characteristics of the base array on which the integrated circuit is to be manufactured; constructing a primitive-based version of the identified standard cell using the identified one or more primitive logic cells; analyzing electrical performance of the primitive-based version of the identified standard cell with respect to timing, leakage, and power consumption; comparing results of analyzing the electrical performance of the primitive-based version of the identified standard cell with target electrical performance specifications of the identified standard cell to determine whether or not the electrical performance of the primitive-based version of the identified standard cell is acceptable; and upon determining that the electrical performance of the primitive-based version of the identified standard cell is acceptable, recording the primitive-based version of the identified standard cell. identifying a standard cell used in a netlist for the integrated circuit, wherein the standard cell has corresponding target performance specifications for leakage, speed, and power consumption; determining a logic function of the identified standard cell; identifying one or more primitive logic cells from within a primitive library as needed to duplicate the determined logic function of the identified standard cell, the one or more primitive logic cells defined based on specifications of the base array, wherein the primitive library includes fourteen primitive logic cells including 1) a two input NAND gate, 2) a three input NAND gate, 3) a two input NOR gate, 4) a three input NOR gate, 5) a pass gate, 6) a latch element, 7) a single PMOS stack, 8) a double PMOS stack, 9) a triple PMOS stack, 10) a single NMOS stack, 11) a double NMOS stack, 12) a triple NMOS stack, 13) an inverter, and 14) a tri-state inverter, wherein the primitive logic cells within the primitive library are defined based on transistor device characteristics of the base array on which the integrated circuit is to be manufactured; constructing a primitive-based version of the identified standard cell using the identified one or more primitive logic cells; analyzing electrical performance of the primitive-based version of the identified standard cell with respect to timing, leakage, and power consumption; comparing results of analyzing the electrical performance of the primitive-based version of the identified standard cell with target electrical performance specifications of the identified standard cell to determine whether or not the electrical performance of the primitive-based version of the identified standard cell is acceptable; and upon determining that the electrical performance of the primitive-based version of the identified standard cell is acceptable, recording the primitive-based version of the identified standard cell.