A re-programmable non-volatile semiconductor memory, comprising: a plurality of planes stacked on top of one another over a semiconductor substrate, in each one of the planes, a plurality of word lines (WL i0, WL i1, WL i2, WL i3, i=1 or 2) elongated in a x-direction and spaced apart in a y-direction across the plane, a plurality of local bit lines (LBL 11, LBL 12, LBL 13, LBL 21,..., LBL 33) extending from the substrate in a z-direction through the plurality of planes, arranged in a two-dimensional rectangular array in the x and y-directions and positioned through the planes between the word lines (WL 10, WL 11, WL 12, WL 13, WL 20,...WL 23) in the y-direction, the word lines and the local bit lines therefore crossing adjacent each other at a plurality of crossings in the plurality of planes, wherein the x, y and z-directions are orthogonal with each other as three-dimensional rectangular coordinates, a plurality of re-programmable non-volatile memory elements (M 111, M 112, M 113,..., M 236) each non-volatile memory element (M 112) being connected between a corresponding word line (WL 11) and a corresponding local bit line (LBL 11) adjacent a corresponding crossing of the plurality of crossings, each non-volatile memory element having a detectable electrical characteristic that reversibly changes between at least two stable states in response to electrical stimuli applied thereto, a plurality of select devices (Q 11, Q 12, Q 13, Q 21...Q 33) formed in the substrate, each select device (Q ij) being able to connect a corresponding one (LBL ij) of the local bit lines to a corresponding one (GBLi) of global bit lines formed in the substrate; and word line select circuits for addressing one or more word lines of one or more groups of the plurality of non-volatiles memory elements to be reset CHARACTERISED IN: a control circuit formed in the substrate to connect, in response to control signals including addresses of one or more groups (M114, M124, M134, M115, M125, M135) of the plurality of memory elements to be reset, selected ones (LBL 12, LBL 22, LBL 32, LBL 13, LBL 23, LBL 33) of the plurality of local bit lines to the plurality of global bit lines (GBL 1, GBL 2, GBL 3) in a manner that for each global bit line (GBL 1) at least two local bit lines (LBL 12, LBL 13) adjacent to each other are connected to said global bit line (GBL 1) at a same time, said two local bit lines (LBL 12, LBL 13) being connected each via a single memory element (M 114, M 115) to a same corresponding selected word line (WL 12) a plurality of planes stacked on top of one another over a semiconductor substrate, in each one of the planes, a plurality of word lines (WL i0, WL i1, WL i2, WL i3, i=1 or 2) elongated in a x-direction and spaced apart in a y-direction across the plane, a plurality of local bit lines (LBL 11, LBL 12, LBL 13, LBL 21,..., LBL 33) extending from the substrate in a z-direction through the plurality of planes, arranged in a two-dimensional rectangular array in the x and y-directions and positioned through the planes between the word lines (WL 10, WL 11, WL 12, WL 13, WL 20,...WL 23) in the y-direction, the word lines and the local bit lines therefore crossing adjacent each other at a plurality of crossings in the plurality of planes, wherein the x, y and z-directions are orthogonal with each other as three-dimensional rectangular coordinates, a plurality of re-programmable non-volatile memory elements (M 111, M 112, M 113,..., M 236) each non-volatile memory element (M 112) being connected between a corresponding word line (WL 11) and a corresponding local bit line (LBL 11) adjacent a corresponding crossing of the plurality of crossings, each non-volatile memory element having a detectable electrical characteristic that reversibly changes between at least two stable states in response to electrical stimuli applied thereto, a plurality of select devices (Q 11, Q 12, Q 13, Q 21...Q 33) formed in the substrate, each select device (Q ij) being able to connect a corresponding one (LBL ij) of the local bit lines to a corresponding one (GBLi) of global bit lines formed in the substrate; and word line select circuits for addressing one or more word lines of one or more groups of the plurality of non-volatiles memory elements to be reset CHARACTERISED IN: a control circuit formed in the substrate to connect, in response to control signals including addresses of one or more groups (M114, M124, M134, M115, M125, M135) of the plurality of memory elements to be reset, selected ones (LBL 12, LBL 22, LBL 32, LBL 13, LBL 23, LBL 33) of the plurality of local bit lines to the plurality of global bit lines (GBL 1, GBL 2, GBL 3) in a manner that for each global bit line (GBL 1) at least two local bit lines (LBL 12, LBL 13) adjacent to each other are connected to said global bit line (GBL 1) at a same time, said two local bit lines (LBL 12, LBL 13) being connected each via a single memory element (M 114, M 115) to a same corresponding selected word line (WL 12)