A processor having a scalable processor architecture comprising: a first multiply-accumulate, MAC, unit coupled to a register file, the first MAC unit comprising: a first multiplier operable to receive and multiply first and second operands from the register file and to provide a first product to a first intermediate register, a first arithmetic logic unit, ALU, comprising a first input and a second input, the first input operable to selectively receive the first product from the first intermediate register and the first operand via a first multiplexer, the second input operable to selectively receive the second operand and a third operand from the register file via a second multiplexer, the first ALU operable to provide a first output ( to the register file, wherein the second multiplexer is not coupled to any multiplier output, a second MAC unit operable to receive and multiply fourth and fifth operands from the register file to obtain a second product, to store the second product in a second intermediate register, to add a sixth operand with either the stored second product or a sum of the stored first and second product, and to provide a second output to the register file; wherein the first MAC unit and the second MAC unit are responsive to a processor instruction to dynamically reconfigure between a first configuration in which the first MAC unit and the second MAC unit operate as dual independent MAC units, and a second configuration in which the first MAC unit and the second MAC unit operate as coupled MAC units; and a second ALU to provide a third output to the register file independent of the first and second MAC units; wherein operations of the first and second MAC units occur in parallel with an operation of the second ALU. a first multiply-accumulate, MAC, unit coupled to a register file, the first MAC unit comprising: a first multiplier operable to receive and multiply first and second operands from the register file and to provide a first product to a first intermediate register, a first arithmetic logic unit, ALU, comprising a first input and a second input, the first input operable to selectively receive the first product from the first intermediate register and the first operand via a first multiplexer, the second input operable to selectively receive the second operand and a third operand from the register file via a second multiplexer, the first ALU operable to provide a first output ( to the register file, wherein the second multiplexer is not coupled to any multiplier output, a first multiplier operable to receive and multiply first and second operands from the register file and to provide a first product to a first intermediate register, a first arithmetic logic unit, ALU, comprising a first input and a second input, the first input operable to selectively receive the first product from the first intermediate register and the first operand via a first multiplexer, the second input operable to selectively receive the second operand and a third operand from the register file via a second multiplexer, the first ALU operable to provide a first output ( to the register file, wherein the second multiplexer is not coupled to any multiplier output, a second MAC unit operable to receive and multiply fourth and fifth operands from the register file to obtain a second product, to store the second product in a second intermediate register, to add a sixth operand with either the stored second product or a sum of the stored first and second product, and to provide a second output to the register file; wherein the first MAC unit and the second MAC unit are responsive to a processor instruction to dynamically reconfigure between a first configuration in which the first MAC unit and the second MAC unit operate as dual independent MAC units, and a second configuration in which the first MAC unit and the second MAC unit operate as coupled MAC units; and a second ALU to provide a third output to the register file independent of the first and second MAC units; wherein operations of the first and second MAC units occur in parallel with an operation of the second ALU.