An apparatus, comprising: a first synchronizer unit (410a, 420a) connected to a first clock signal, having a first input configured to receive a clock select signal and a second input configured to receive a status signal of a second clock and configured to generate a synchronized enable request signal of the first clock and a synchronized status signal of the second clock; a first processor configured to receive the synchronized enable request signal of the first clock and the synchronized status signal of the second clock and configured to generate a synchronized enable signal of the first clock and a status signal of the first clock; a first clock gate configured to receive the enable signal of the first clock to gate the first clock signal and to transmit the first clock signal to an output gate; a second synchronizer unit (410b, 420b) connected to a second clock signal, having a first input configured to receive an inverted signal of the clock select signal and a second input configured to receive the status signal of the first clock and configured to generate a synchronized enable request signal of the second clock and a synchronized status signal of the first clock; a second processor configured to receive the synchronized enable request signal of the second clock and the synchronized status signal of the first clock and configured to generate an enable signal of the second clock and the status signal of the second clock; and a second clock gate configured to receive the enable signal of the second clock to gate the second clock signal and to transmit the second clock signal to the output gate which generates an output clock signal, wherein the apparatus is characterized by: the status signal of the second clock being for indicating when the second clock is enabled and for indicating when the second clock is to be enabled; and the status signal (461 a) of the first clock being for indicating when the first clock is enabled and for indicating when the first clock is to be enabled. a first synchronizer unit (410a, 420a) connected to a first clock signal, having a first input configured to receive a clock select signal and a second input configured to receive a status signal of a second clock and configured to generate a synchronized enable request signal of the first clock and a synchronized status signal of the second clock; a first processor configured to receive the synchronized enable request signal of the first clock and the synchronized status signal of the second clock and configured to generate a synchronized enable signal of the first clock and a status signal of the first clock; a first clock gate configured to receive the enable signal of the first clock to gate the first clock signal and to transmit the first clock signal to an output gate; a second synchronizer unit (410b, 420b) connected to a second clock signal, having a first input configured to receive an inverted signal of the clock select signal and a second input configured to receive the status signal of the first clock and configured to generate a synchronized enable request signal of the second clock and a synchronized status signal of the first clock; a second processor configured to receive the synchronized enable request signal of the second clock and the synchronized status signal of the first clock and configured to generate an enable signal of the second clock and the status signal of the second clock; and a second clock gate configured to receive the enable signal of the second clock to gate the second clock signal and to transmit the second clock signal to the output gate which generates an output clock signal, wherein the apparatus is characterized by: the status signal of the second clock being for indicating when the second clock is enabled and for indicating when the second clock is to be enabled; and the status signal (461 a) of the first clock being for indicating when the first clock is enabled and for indicating when the first clock is to be enabled.