A microprocessor, comprising: condition flags; an instruction translator configured to receive a conditional load instruction that specifies a condition, a destination register, a base register, an offset source, and a memory addressing mode, wherein the instruction instructs the microprocessor to load data from a memory location into the destination register only if the condition flags satisfy the condition, wherein the offset source specifies whether the offset is an immediate value or a value in an offset register, wherein the addressing mode specifies whether or not the base register is updated when the condition flags satisfy the condition; wherein the addressing mode further specifies whether the memory location address is the unchanged base register value or one of a sum and a difference of the base register value and the offset; wherein the instruction translator is configured to translate the conditional load instruction into a number of microinstructions, wherein the number of microinstructions varies as a function of the offset source and the addressing mode; and an out-of-order execution pipeline configured to execute the microinstructions to generate results specified by the instruction; wherein when the addressing mode specifies the memory location address is the one of the sum and the difference, the microinstructions comprise at least: a first microinstruction, wherein to execute the first microinstruction an execution unit of the execution pipeline is configured to generate the one of the sum and the difference; and a second microinstruction, wherein to execute the second microinstruction an execution unit of the execution pipeline is configured to receive the previous value of the destination register and the one of the sum and the difference and generate a result that is the data loaded from the memory location whose address is the one of the sum and the difference if the condition flags satisfy the condition but is the previous value of the destination register if the condition flags do not satisfy the condition; wherein the previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction. condition flags; an instruction translator configured to receive a conditional load instruction that specifies a condition, a destination register, a base register, an offset source, and a memory addressing mode, wherein the instruction instructs the microprocessor to load data from a memory location into the destination register only if the condition flags satisfy the condition, wherein the offset source specifies whether the offset is an immediate value or a value in an offset register, wherein the addressing mode specifies whether or not the base register is updated when the condition flags satisfy the condition; wherein the addressing mode further specifies whether the memory location address is the unchanged base register value or one of a sum and a difference of the base register value and the offset; wherein the instruction translator is configured to translate the conditional load instruction into a number of microinstructions, wherein the number of microinstructions varies as a function of the offset source and the addressing mode; and an out-of-order execution pipeline configured to execute the microinstructions to generate results specified by the instruction; wherein when the addressing mode specifies the memory location address is the one of the sum and the difference, the microinstructions comprise at least: a first microinstruction, wherein to execute the first microinstruction an execution unit of the execution pipeline is configured to generate the one of the sum and the difference; and a second microinstruction, wherein to execute the second microinstruction an execution unit of the execution pipeline is configured to receive the previous value of the destination register and the one of the sum and the difference and generate a result that is the data loaded from the memory location whose address is the one of the sum and the difference if the condition flags satisfy the condition but is the previous value of the destination register if the condition flags do not satisfy the condition; wherein the previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction. a first microinstruction, wherein to execute the first microinstruction an execution unit of the execution pipeline is configured to generate the one of the sum and the difference; and a second microinstruction, wherein to execute the second microinstruction an execution unit of the execution pipeline is configured to receive the previous value of the destination register and the one of the sum and the difference and generate a result that is the data loaded from the memory location whose address is the one of the sum and the difference if the condition flags satisfy the condition but is the previous value of the destination register if the condition flags do not satisfy the condition; wherein the previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.