An array substrate (101,201) comprising: a layer arrangement including a pixel region, the pixel region being part of a plurality of pixel regions of the array substrate (101,201), wherein the pixel region is defined by a gate line extending in a first direction and a data line extending in a second direction and crossing the gate line, and wherein the data line comprises a data line pattern and a data line connection portion, the data line connection portion overlapping and crossing the gate line; a gate electrode formed in the pixel region at the crossing portion of the gate line and the data line; a plurality of trenches (tch) having a depth from a surface of the layer arrangement, the plurality of trenches (tch) extending in the first and second directions and formed corresponding to the gate line, the gate electrode and the data line pattern; wherein the gate line, the gate electrode and the data line pattern fill the respective trenches (tch), wherein the data line pattern has two ends and is between adjacent gate lines of adjacent pixel regions of the plurality of pixel regions; a gate insulating layer on the gate line, the gate electrode and the data line pattern, substantially flat over the layer arrangement, and including contact holes that expose both ends of the data line pattern, respectively, and wherein the data line connection portion is on the gate insulating layer and contacting adjacent data line patterns of the adjacent pixel regions of the plurality of pixel regions through the contact holes; a semiconductor layer on the gate insulating layer over the gate electrode; a source electrode connected to the data line connection portion, and a drain electrode spaced apart from the source electrode; a passivation layer on the data line connection portion and the source and drain electrodes (133, 136), the passivation layer including a drain contact hole exposing the drain electrode and the passivation layer having a double-layered structure with a first layer made of inorganic insulating material, and a second layer made of organic insulating material on the first layer; and a pixel electrode on the second layer and connected to the drain electrode through the drain contact hole. a layer arrangement including a pixel region, the pixel region being part of a plurality of pixel regions of the array substrate (101,201), wherein the pixel region is defined by a gate line extending in a first direction and a data line extending in a second direction and crossing the gate line, and wherein the data line comprises a data line pattern and a data line connection portion, the data line connection portion overlapping and crossing the gate line; a gate electrode formed in the pixel region at the crossing portion of the gate line and the data line; a plurality of trenches (tch) having a depth from a surface of the layer arrangement, the plurality of trenches (tch) extending in the first and second directions and formed corresponding to the gate line, the gate electrode and the data line pattern; wherein the gate line, the gate electrode and the data line pattern fill the respective trenches (tch), wherein the data line pattern has two ends and is between adjacent gate lines of adjacent pixel regions of the plurality of pixel regions; a gate insulating layer on the gate line, the gate electrode and the data line pattern, substantially flat over the layer arrangement, and including contact holes that expose both ends of the data line pattern, respectively, and wherein the data line connection portion is on the gate insulating layer and contacting adjacent data line patterns of the adjacent pixel regions of the plurality of pixel regions through the contact holes; a semiconductor layer on the gate insulating layer over the gate electrode; a source electrode connected to the data line connection portion, and a drain electrode spaced apart from the source electrode; a passivation layer on the data line connection portion and the source and drain electrodes (133, 136), the passivation layer including a drain contact hole exposing the drain electrode and the passivation layer having a double-layered structure with a first layer made of inorganic insulating material, and a second layer made of organic insulating material on the first layer; and a pixel electrode on the second layer and connected to the drain electrode through the drain contact hole.