A programmable layer of an artificial neural network, comprising: a vector-by-matrix multiplication array (1701, 1702, 1704, 1705, 2501) comprising rows and columns of flash memory cells, the flash memory cells storing weights, the array configured to receive input voltages on lines coupled to a plurality of rows of the array that are multiplied by the weights to generate output currents on lines coupled to a plurality of columns of the array, wherein the input voltages are inputs to the programmable layer of the artificial neural network; and a neuron output circuit (1703, 1706, 2000) comprising: a plurality of summer circuits (2000, 2504), each summer circuit configured to receive an output current from one of the plurality of columns in response to the vector-by-matrix multiplication array receiving the input voltages and to generate a sum voltage based on the output current, each summer circuit comprising an operational amplifier comprising an inverting terminal to receive the output current, a non-inverting terminal receiving a voltage reference (VREF), and an output terminal, and a variable resistor coupled between the inverting terminal and the output terminal; and a plurality of activation circuits, each activation circuit configured to receive a sum voltage from a respective summer circuit and rectify the sum voltage to generate an output analog voltage, wherein the output analog voltages from the plurality of activation circuits are outputs of the programmable layer of the artificial neural network; and a control system (2502, 2600) for adjusting a resistance of the variable resistor in each summer circuit to minimize power based on a maximum current of the output currents using one or more of configuration bits and trimbits, wherein the maximum current is dependent on the number of synapses and weight values contained in the VMM. a vector-by-matrix multiplication array (1701, 1702, 1704, 1705, 2501) comprising rows and columns of flash memory cells, the flash memory cells storing weights, the array configured to receive input voltages on lines coupled to a plurality of rows of the array that are multiplied by the weights to generate output currents on lines coupled to a plurality of columns of the array, wherein the input voltages are inputs to the programmable layer of the artificial neural network; and a neuron output circuit (1703, 1706, 2000) comprising: a plurality of summer circuits (2000, 2504), each summer circuit configured to receive an output current from one of the plurality of columns in response to the vector-by-matrix multiplication array receiving the input voltages and to generate a sum voltage based on the output current, each summer circuit comprising an operational amplifier comprising an inverting terminal to receive the output current, a non-inverting terminal receiving a voltage reference (VREF), and an output terminal, and a variable resistor coupled between the inverting terminal and the output terminal; and a plurality of activation circuits, each activation circuit configured to receive a sum voltage from a respective summer circuit and rectify the sum voltage to generate an output analog voltage, wherein the output analog voltages from the plurality of activation circuits are outputs of the programmable layer of the artificial neural network; and a plurality of summer circuits (2000, 2504), each summer circuit configured to receive an output current from one of the plurality of columns in response to the vector-by-matrix multiplication array receiving the input voltages and to generate a sum voltage based on the output current, each summer circuit comprising an operational amplifier comprising an inverting terminal to receive the output current, a non-inverting terminal receiving a voltage reference (VREF), and an output terminal, and a variable resistor coupled between the inverting terminal and the output terminal; and a plurality of activation circuits, each activation circuit configured to receive a sum voltage from a respective summer circuit and rectify the sum voltage to generate an output analog voltage, wherein the output analog voltages from the plurality of activation circuits are outputs of the programmable layer of the artificial neural network; and a control system (2502, 2600) for adjusting a resistance of the variable resistor in each summer circuit to minimize power based on a maximum current of the output currents using one or more of configuration bits and trimbits, wherein the maximum current is dependent on the number of synapses and weight values contained in the VMM.