A minimum mean square error equalization processor for MIMO decoding, comprising: a time division multiplexer (604, 705) configured to receive a plurality of channel matrices corresponding to a plurality of subcarriers (H A and H B) and interleave the plurality of channel matrices to produce an input set, H AB, of time division multiplexed matrices; a first systolic array (210, 400, 612, 712) configured to operate in first and second modes and receive the input set, H AB, of time division multiplexed matrices from a plurality of channel matrices; wherein the first systolic array operating in the first mode is configured to perform triangularization on the input set, H AB, of time division multiplexed matrices to produce a first set, R, of time division multiplexed output matrices, and operating in the second mode is configured to perform back-substitution on the first set, R, to produce and output a second set, R -1, of time division multiplexed output matrices; a second systolic array (220, 1100, 616, 716) configured to operate in first and second modes and receive the second set, R -1, of time division multiplexed output matrices from the first systolic array and the input set, H AB, of time division multiplexed output matrices; wherein the second systolic array operating in the first mode is configured to perform left multiplication on the second set of time division multiplexed output matrices with the input set, H AB, of time division multiplexed output matrices to produce a third set, Q 1, of time division multiplexed output matrices, where Q 1 = H AB R -1; wherein the second systolic array operating in the second mode: is configured to perform cross diagonal transposition on the third set, Q 1, of time division multiplexed output matrices to produce a fourth set, Q 1 ', of time division multiplexed output matrices; and is configured to perform right multiplication on the second set, R -1, of time division multiplexed output matrices with the fourth set, Q ' 1, of time division multiplexed output matrices to produce a fifth set, W, of time division multiplexed output matrices; wherein the second set, R -1, of outputs of the first systolic array is coupled to a first set of corresponding inputs of the second systolic array; and wherein the first systolic array is configured to switch from the first mode to the second mode after triangularization is completed, and the second systolic array is configured to switch from the first mode to the second mode after left multiplication is completed. a time division multiplexer (604, 705) configured to receive a plurality of channel matrices corresponding to a plurality of subcarriers (H A and H B) and interleave the plurality of channel matrices to produce an input set, H AB, of time division multiplexed matrices; a first systolic array (210, 400, 612, 712) configured to operate in first and second modes and receive the input set, H AB, of time division multiplexed matrices from a plurality of channel matrices; wherein the first systolic array operating in the first mode is configured to perform triangularization on the input set, H AB, of time division multiplexed matrices to produce a first set, R, of time division multiplexed output matrices, and operating in the second mode is configured to perform back-substitution on the first set, R, to produce and output a second set, R -1, of time division multiplexed output matrices; a second systolic array (220, 1100, 616, 716) configured to operate in first and second modes and receive the second set, R -1, of time division multiplexed output matrices from the first systolic array and the input set, H AB, of time division multiplexed output matrices; wherein the second systolic array operating in the first mode is configured to perform left multiplication on the second set of time division multiplexed output matrices with the input set, H AB, of time division multiplexed output matrices to produce a third set, Q 1, of time division multiplexed output matrices, where Q 1 = H AB R -1; wherein the second systolic array operating in the second mode: is configured to perform cross diagonal transposition on the third set, Q 1, of time division multiplexed output matrices to produce a fourth set, Q 1 ', of time division multiplexed output matrices; and is configured to perform right multiplication on the second set, R -1, of time division multiplexed output matrices with the fourth set, Q ' 1, of time division multiplexed output matrices to produce a fifth set, W, of time division multiplexed output matrices; is configured to perform cross diagonal transposition on the third set, Q 1, of time division multiplexed output matrices to produce a fourth set, Q 1 ', of time division multiplexed output matrices; and is configured to perform right multiplication on the second set, R -1, of time division multiplexed output matrices with the fourth set, Q ' 1, of time division multiplexed output matrices to produce a fifth set, W, of time division multiplexed output matrices; wherein the second set, R -1, of outputs of the first systolic array is coupled to a first set of corresponding inputs of the second systolic array; and wherein the first systolic array is configured to switch from the first mode to the second mode after triangularization is completed, and the second systolic array is configured to switch from the first mode to the second mode after left multiplication is completed.