A magnetic random access memory, MRAM, comprising: a plurality of memory columns, each of the plurality of memory columns having at least one magnetic bit cell; a plurality of source lines, each associated with a corresponding column of the plurality of memory columns, each of the plurality of source lines coupled to one terminal of the at least one magnetic bit cell of said corresponding column; a plurality of bit lines, each associated with said corresponding column, each of the plurality of bit lines coupled to another terminal of the at least one magnetic bit cell of said corresponding column; a plurality of first drivers, each coupled to a corresponding source line of the plurality of source lines, the plurality of first drivers applying a first driver voltage to change the at least one magnetic bit cell from a first state to a second state and applying a ground voltage to change the at least one magnetic bit cell from the second state to the first state; and a plurality of second drivers, each coupled to a corresponding bit line of the plurality of bit lines, the plurality of second drivers applying a second driver voltage to change the at least one magnetic bit cell from the second state to the first state and applying a ground voltage to change the at least one magnetic bit cell from the first state to the second state, wherein the first driver voltage is different from the second driver voltage, and wherein the first driver voltage is a core network voltage and the second driver voltage is an input/output (I/O) network voltage, or the first driver voltage is an I/O network voltage and the second driver voltage is a core network voltage. a plurality of memory columns, each of the plurality of memory columns having at least one magnetic bit cell; a plurality of source lines, each associated with a corresponding column of the plurality of memory columns, each of the plurality of source lines coupled to one terminal of the at least one magnetic bit cell of said corresponding column; a plurality of bit lines, each associated with said corresponding column, each of the plurality of bit lines coupled to another terminal of the at least one magnetic bit cell of said corresponding column; a plurality of first drivers, each coupled to a corresponding source line of the plurality of source lines, the plurality of first drivers applying a first driver voltage to change the at least one magnetic bit cell from a first state to a second state and applying a ground voltage to change the at least one magnetic bit cell from the second state to the first state; and a plurality of second drivers, each coupled to a corresponding bit line of the plurality of bit lines, the plurality of second drivers applying a second driver voltage to change the at least one magnetic bit cell from the second state to the first state and applying a ground voltage to change the at least one magnetic bit cell from the first state to the second state, wherein the first driver voltage is different from the second driver voltage, and wherein the first driver voltage is a core network voltage and the second driver voltage is an input/output (I/O) network voltage, or the first driver voltage is an I/O network voltage and the second driver voltage is a core network voltage.