A current digital-to-analog converter (IDAC) comprising: a first current source arranged to provide current to a first supply node of the IDAC; a first compensating capacitor (C p ') comprising a first terminal and second terminal wherein the first terminal is connected to the first supply node; a first output (OUTP) of the IDAC; a second output (OUTN) of the IDAC driving circuitry configured to supply compensating current to the first compensating capacitor (C p '), wherein the driving circuitry comprises an amplifier having a first output connected to the second terminal of the first compensating capacitor and a first input arranged to receive a signal that is output from the IDAC and wherein the compensating current essentially nulls a current that would charge a capacitance C p associated with the first current source; a first switch and a second switch arranged to intermittently conduct current to and from the first output of the IDAC, wherein the driving circuity is configured to be switched to receive and amplify, with the amplifier, a signal from the first output of the IDAC with a first control signal that controls the first switch; a third switch and a fourth switch arranged to conduct current intermittently to and from the second output of the IDAC (OUTN), wherein the first switch and the fourth switch are configured to be controlled by the first control signal, and the second switch and the third switch are configured to be controlled by a second control signal, wherein the second control signal is an inverse of the first control signal;; and a second input of the amplifier connected to a reference voltage (V cm), wherein the first input of the amplifier connects to a fifth switch that is configured to be controlled by the first control signal that controls the first switch and the fourth switch, and wherein the first input of the amplifier connects to a sixth switch that is configured to be controlled by the second control signal that controls the second switch and the third switch. a first current source arranged to provide current to a first supply node of the IDAC; a first compensating capacitor (C p ') comprising a first terminal and second terminal wherein the first terminal is connected to the first supply node; a first output (OUTP) of the IDAC; a second output (OUTN) of the IDAC driving circuitry configured to supply compensating current to the first compensating capacitor (C p '), wherein the driving circuitry comprises an amplifier having a first output connected to the second terminal of the first compensating capacitor and a first input arranged to receive a signal that is output from the IDAC and wherein the compensating current essentially nulls a current that would charge a capacitance C p associated with the first current source; a first switch and a second switch arranged to intermittently conduct current to and from the first output of the IDAC, wherein the driving circuity is configured to be switched to receive and amplify, with the amplifier, a signal from the first output of the IDAC with a first control signal that controls the first switch; a third switch and a fourth switch arranged to conduct current intermittently to and from the second output of the IDAC (OUTN), wherein the first switch and the fourth switch are configured to be controlled by the first control signal, and the second switch and the third switch are configured to be controlled by a second control signal, wherein the second control signal is an inverse of the first control signal;; and a second input of the amplifier connected to a reference voltage (V cm), wherein the first input of the amplifier connects to a fifth switch that is configured to be controlled by the first control signal that controls the first switch and the fourth switch, and wherein the first input of the amplifier connects to a sixth switch that is configured to be controlled by the second control signal that controls the second switch and the third switch.