An apparatus, comprising: a memory (210-1, 210-2,..., 210-N) comprising a plurality of mixed mode blocks (116-0, 116-1,..., 116-B), wherein: the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) comprise memory cells capable of being operated in both a single level cell, SLC, mode and an extra level cell, XLC, mode; and XLC memory cells are cells programmed to a targeted one of more than two different data states such that the cells are configured to store more than a single data unit; a controller (208, 308) configured to: write a first portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) of the memory (210-1, 210-2,..., 210-N) in the SLC mode; and write a second portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) in the XLC mode; wherein writing the second portion of sequential host data includes performing a garbage collection operation that includes: adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B); and folding at least two data units of the first portion into a same block as at least one data unit of the second portion. a memory (210-1, 210-2,..., 210-N) comprising a plurality of mixed mode blocks (116-0, 116-1,..., 116-B), wherein: the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) comprise memory cells capable of being operated in both a single level cell, SLC, mode and an extra level cell, XLC, mode; and XLC memory cells are cells programmed to a targeted one of more than two different data states such that the cells are configured to store more than a single data unit; the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) comprise memory cells capable of being operated in both a single level cell, SLC, mode and an extra level cell, XLC, mode; and XLC memory cells are cells programmed to a targeted one of more than two different data states such that the cells are configured to store more than a single data unit; a controller (208, 308) configured to: write a first portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) of the memory (210-1, 210-2,..., 210-N) in the SLC mode; and write a second portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) in the XLC mode; wherein writing the second portion of sequential host data includes performing a garbage collection operation that includes: adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B); and folding at least two data units of the first portion into a same block as at least one data unit of the second portion. write a first portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) of the memory (210-1, 210-2,..., 210-N) in the SLC mode; and write a second portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B) in the XLC mode; wherein writing the second portion of sequential host data includes performing a garbage collection operation that includes: adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B); and folding at least two data units of the first portion into a same block as at least one data unit of the second portion. adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks (116-0, 116-1,..., 116-B); and folding at least two data units of the first portion into a same block as at least one data unit of the second portion.