A flash memory device comprising: a) a flash memory including a plurality of flash memory dies (110A, 110N), each flash memory die including a respective cache storage area (122A, 122N) and a respective main storage area (124A, 124N); and b) control circuitry operative to: i) receive data from an external host device; ii) determine to which main storage area (124A, 124N) the received data is addressed, thereby specifying one of the plurality of flash memory dies (110A, 110N) as a target die for the received data; and iii) whenever the received data is written into a cache storage area (122A, 122N) before being written into a main storage area (124A, 124N), write the received data into the cache storage area (122A, 122N) of the specified target die (110A, 110N); c) the control circuitry is operative such that some data received from the external host device is written into a cache storage area (122A, 122N) before being written into a main storage area (124A, 124N), while other data received from the external host device is written into a main storage area (124A, 124N) without first being written into a cache storage area (122A, 122N), wherein the control circuitry is operative to determine whether or not data is to be written to the cache storage area (122A, 122N) before being written to the main storage area (124A, 124N) according to a rate at which data is received into the flash memory device and/or in accordance with how full the cache storage area (122A, 122N) is. a) a flash memory including a plurality of flash memory dies (110A, 110N), each flash memory die including a respective cache storage area (122A, 122N) and a respective main storage area (124A, 124N); and b) control circuitry operative to: i) receive data from an external host device; ii) determine to which main storage area (124A, 124N) the received data is addressed, thereby specifying one of the plurality of flash memory dies (110A, 110N) as a target die for the received data; and iii) whenever the received data is written into a cache storage area (122A, 122N) before being written into a main storage area (124A, 124N), write the received data into the cache storage area (122A, 122N) of the specified target die (110A, 110N); i) receive data from an external host device; ii) determine to which main storage area (124A, 124N) the received data is addressed, thereby specifying one of the plurality of flash memory dies (110A, 110N) as a target die for the received data; and iii) whenever the received data is written into a cache storage area (122A, 122N) before being written into a main storage area (124A, 124N), write the received data into the cache storage area (122A, 122N) of the specified target die (110A, 110N); c) the control circuitry is operative such that some data received from the external host device is written into a cache storage area (122A, 122N) before being written into a main storage area (124A, 124N), while other data received from the external host device is written into a main storage area (124A, 124N) without first being written into a cache storage area (122A, 122N), wherein the control circuitry is operative to determine whether or not data is to be written to the cache storage area (122A, 122N) before being written to the main storage area (124A, 124N) according to a rate at which data is received into the flash memory device and/or in accordance with how full the cache storage area (122A, 122N) is.