A thin-film transistor array formed on an insulating substrate suitable for an electronic paper displaying device combined with a radio frequency identification device, wherein: the thin-film transistor array comprises a plurality of pixels each including a thin-film transistor, a pixel electrode, and a capacitor electrode; the plurality of pixels are arranged in a matrix, being located at positions where a plurality of column wirings extending in a column direction intersect a plurality of row wirings perpendicular to the column wirings and extending in a row direction; the thin-film transistor includes a gate electrode, a source electrode, a drain electrode, and a semiconductor pattern located between the source electrode and the drain electrode; the semiconductor pattern is disposed at a position aligning with the gate electrode in a lamination direction via a gate insulating film; the capacitor electrode is disposed above the thin-film transistor in the lamination direction via an interlayer insulating film; the pixel electrode is disposed above the capacitor electrode in the lamination direction via a capacitor insulating film; the source electrode is connected to a corresponding one of the column wirings; the gate electrode is connected to a corresponding one of the row wirings; the drain electrode is connected to the pixel electrode; the capacitor electrode is connected to a capacitor wiring; the pixel electrode is formed by two electrically conductive layers which are a lower layer electrode serving as a lower pixel electrode, and an upper layer electrode serving as an upper pixel electrode; an intermediate insulating film is sandwiched between the lower pixel electrode and the upper pixel electrode; the upper pixel electrode is connected to the lower pixel electrode through an opening of the intermediate insulating film; a capacitance is configured by an overlap between the capacitor electrode and the lower pixel electrode; and the corresponding one of the column wirings is disposed at a position providing no overlap with the capacitor electrode and the lower pixel electrode, but providing an overlap with the upper pixel electrode, in the lamination direction. the thin-film transistor array comprises a plurality of pixels each including a thin-film transistor, a pixel electrode, and a capacitor electrode; the plurality of pixels are arranged in a matrix, being located at positions where a plurality of column wirings extending in a column direction intersect a plurality of row wirings perpendicular to the column wirings and extending in a row direction; the thin-film transistor includes a gate electrode, a source electrode, a drain electrode, and a semiconductor pattern located between the source electrode and the drain electrode; the semiconductor pattern is disposed at a position aligning with the gate electrode in a lamination direction via a gate insulating film; the capacitor electrode is disposed above the thin-film transistor in the lamination direction via an interlayer insulating film; the pixel electrode is disposed above the capacitor electrode in the lamination direction via a capacitor insulating film; the source electrode is connected to a corresponding one of the column wirings; the gate electrode is connected to a corresponding one of the row wirings; the drain electrode is connected to the pixel electrode; the capacitor electrode is connected to a capacitor wiring; the pixel electrode is formed by two electrically conductive layers which are a lower layer electrode serving as a lower pixel electrode, and an upper layer electrode serving as an upper pixel electrode; an intermediate insulating film is sandwiched between the lower pixel electrode and the upper pixel electrode; the upper pixel electrode is connected to the lower pixel electrode through an opening of the intermediate insulating film; a capacitance is configured by an overlap between the capacitor electrode and the lower pixel electrode; and the corresponding one of the column wirings is disposed at a position providing no overlap with the capacitor electrode and the lower pixel electrode, but providing an overlap with the upper pixel electrode, in the lamination direction.