A method of forming a memory cell, comprising: forming a first insulation layer on a semiconductor substrate having a first conductivity type; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first conductive layer; forming a second conductive layer on the second insulation layer; forming a third insulation layer on the second conductive layer; forming a trench that extends through the third insulation layer, the second conductive layer, and the second insulation layer; forming insulation spacers (24, 26, 28) along a sidewall of the trench; extending the trench through the first conductive layer between the insulation spacers; forming a word line gate in the trench, wherein the word line gate is disposed vertically over and insulated from the substrate; forming an erase gate in the trench, wherein the erase gate is disposed vertically over and insulated from the word line gate; removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates (18a, 18b), and removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates (14a, 14b); and forming first and second regions (44a, 44b) in the substrate and having a second conductivity type different than the first conductivity type, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first and second regions; wherein: the first floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate, the second floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate, the first coupling gate is disposed over and insulated from the first floating gate, and the second coupling gate is disposed over and insulated from the second floating gate. forming a first insulation layer on a semiconductor substrate having a first conductivity type; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first conductive layer; forming a second conductive layer on the second insulation layer; forming a third insulation layer on the second conductive layer; forming a trench that extends through the third insulation layer, the second conductive layer, and the second insulation layer; forming insulation spacers (24, 26, 28) along a sidewall of the trench; extending the trench through the first conductive layer between the insulation spacers; forming a word line gate in the trench, wherein the word line gate is disposed vertically over and insulated from the substrate; forming an erase gate in the trench, wherein the erase gate is disposed vertically over and insulated from the word line gate; removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates (18a, 18b), and removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates (14a, 14b); and forming first and second regions (44a, 44b) in the substrate and having a second conductivity type different than the first conductivity type, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first and second regions; wherein: the first floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate, the second floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate, the first coupling gate is disposed over and insulated from the first floating gate, and the second coupling gate is disposed over and insulated from the second floating gate. the first floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate, the second floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate, the first coupling gate is disposed over and insulated from the first floating gate, and the second coupling gate is disposed over and insulated from the second floating gate.