A device, comprising: a first p-type metal oxide semiconductor transistor, wherein a source of the first p-type metal oxide semiconductor transistor is connected to an input of the device; and a first circuit, for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated, wherein the first circuit comprises: a second p-type metal oxide semiconductor transistor, wherein a source of the second p-type metal oxide semiconductor transistor is connected to the input of the device and wherein a gate of the second p-type metal oxide semiconductor transistor is connected to the enable signal; a first n-type metal oxide semiconductor transistor, wherein a source of the first n-type metal oxide semiconductor transistor is connected to ground, wherein a drain of the first n-type metal oxide semiconductor transistor is connected to a drain of the second p-type metal oxide semiconductor transistor, wherein a gate of the first n-type metal oxide semiconductor transistor is connected to the enable signal; and a second n-type metal oxide semiconductor transistor, wherein a gate of the second n-type metal oxide semiconductor transistor is connected to an inversion of the enable signal, wherein a source of the second n-type metal oxide semiconductor transistor is connected to the input of the device, and wherein the drain of the second p-type metal oxide semiconductor transistor, the drain of the first n-type metal oxide semiconductor transistor, and a drain of the second n-type metal oxide semiconductor transistor are connected to the gate of the first p-type metal oxide semiconductor transistor. a first p-type metal oxide semiconductor transistor, wherein a source of the first p-type metal oxide semiconductor transistor is connected to an input of the device; and a first circuit, for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated, wherein the first circuit comprises: a second p-type metal oxide semiconductor transistor, wherein a source of the second p-type metal oxide semiconductor transistor is connected to the input of the device and wherein a gate of the second p-type metal oxide semiconductor transistor is connected to the enable signal; a first n-type metal oxide semiconductor transistor, wherein a source of the first n-type metal oxide semiconductor transistor is connected to ground, wherein a drain of the first n-type metal oxide semiconductor transistor is connected to a drain of the second p-type metal oxide semiconductor transistor, wherein a gate of the first n-type metal oxide semiconductor transistor is connected to the enable signal; and a second n-type metal oxide semiconductor transistor, wherein a gate of the second n-type metal oxide semiconductor transistor is connected to an inversion of the enable signal, wherein a source of the second n-type metal oxide semiconductor transistor is connected to the input of the device, and wherein the drain of the second p-type metal oxide semiconductor transistor, the drain of the first n-type metal oxide semiconductor transistor, and a drain of the second n-type metal oxide semiconductor transistor are connected to the gate of the first p-type metal oxide semiconductor transistor. a second p-type metal oxide semiconductor transistor, wherein a source of the second p-type metal oxide semiconductor transistor is connected to the input of the device and wherein a gate of the second p-type metal oxide semiconductor transistor is connected to the enable signal; a first n-type metal oxide semiconductor transistor, wherein a source of the first n-type metal oxide semiconductor transistor is connected to ground, wherein a drain of the first n-type metal oxide semiconductor transistor is connected to a drain of the second p-type metal oxide semiconductor transistor, wherein a gate of the first n-type metal oxide semiconductor transistor is connected to the enable signal; and a second n-type metal oxide semiconductor transistor, wherein a gate of the second n-type metal oxide semiconductor transistor is connected to an inversion of the enable signal, wherein a source of the second n-type metal oxide semiconductor transistor is connected to the input of the device, and wherein the drain of the second p-type metal oxide semiconductor transistor, the drain of the first n-type metal oxide semiconductor transistor, and a drain of the second n-type metal oxide semiconductor transistor are connected to the gate of the first p-type metal oxide semiconductor transistor.