An apparatus, comprising: a NAND string (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n) comprising a set of memory cells (702-716, 722-736, 742-756, 762-776) between a source end of the NAND string and a drain end of the NAND string, wherein the drain end comprises a select gate transistor (717, 718, 737, 738, 757, 758, 777, 778), and wherein the NAND string has a channel (665, 700a, 710a, 720a, 730a) extending between the source end and the drain end; and a control circuit (110, 122), wherein the control circuit, to perform an erase operation for the set of memory cells, is configured to: (i) drive control gate voltages of the memory cells at a lower level, below a current level, to down couple a voltage in the channel to a relatively lower down coupled voltage level; (ii) when the control gate voltages are driven from the current level to the lower level, drive a voltage at the source end and the drain end from an initial level to an intermediate level (Vint), below an erase level, and then hold the voltage at the source end and the drain end at the intermediate level for a first time period sufficient for the voltage in the channel to recover from its down coupled voltage level; (iii) upon expiry of the first time period, drive the voltage at the source end and the drain end higher to the erase level (Verase) for a second time period to charge up the channel to a peak charged up level; and (iv) hold the control gate voltages of the memory cells at a fixed level (1400, 1401) during the second time period to erase the memory cells while the channel is at the peak charged up level. a NAND string (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n) comprising a set of memory cells (702-716, 722-736, 742-756, 762-776) between a source end of the NAND string and a drain end of the NAND string, wherein the drain end comprises a select gate transistor (717, 718, 737, 738, 757, 758, 777, 778), and wherein the NAND string has a channel (665, 700a, 710a, 720a, 730a) extending between the source end and the drain end; and a control circuit (110, 122), wherein the control circuit, to perform an erase operation for the set of memory cells, is configured to: (i) drive control gate voltages of the memory cells at a lower level, below a current level, to down couple a voltage in the channel to a relatively lower down coupled voltage level; (ii) when the control gate voltages are driven from the current level to the lower level, drive a voltage at the source end and the drain end from an initial level to an intermediate level (Vint), below an erase level, and then hold the voltage at the source end and the drain end at the intermediate level for a first time period sufficient for the voltage in the channel to recover from its down coupled voltage level; (iii) upon expiry of the first time period, drive the voltage at the source end and the drain end higher to the erase level (Verase) for a second time period to charge up the channel to a peak charged up level; and (iv) hold the control gate voltages of the memory cells at a fixed level (1400, 1401) during the second time period to erase the memory cells while the channel is at the peak charged up level. (i) drive control gate voltages of the memory cells at a lower level, below a current level, to down couple a voltage in the channel to a relatively lower down coupled voltage level; (ii) when the control gate voltages are driven from the current level to the lower level, drive a voltage at the source end and the drain end from an initial level to an intermediate level (Vint), below an erase level, and then hold the voltage at the source end and the drain end at the intermediate level for a first time period sufficient for the voltage in the channel to recover from its down coupled voltage level; (iii) upon expiry of the first time period, drive the voltage at the source end and the drain end higher to the erase level (Verase) for a second time period to charge up the channel to a peak charged up level; and (iv) hold the control gate voltages of the memory cells at a fixed level (1400, 1401) during the second time period to erase the memory cells while the channel is at the peak charged up level.