A transactional shared memory system, comprising: a plurality of discrete application nodes; a plurality of discrete memory nodes collectively providing an address space of shared memory; a network interconnecting the plurality of discrete application nodes and the plurality of discrete memory nodes, such that the address space is available to the application nodes; and a controller for directing transactions in a distributed system utilizing the shared memory, comprising instructions to permit an application node to transfer to at least one memory node a batched transaction instruction set, the batched transaction instruction set comprising a data structure including instruction subsets selected from the group consisting of: a write subset having at least one write member specifying a memory node identifier, a memory address range, and write data; a compare subset having at least one compare member specifying a memory node identifier, a memory address range, and compare data; a read subset having at least one read member specifying a memory node identifier, and a memory address range; and combinations of the write, compare and read subsets (322, 324, 326); wherein the data structure is arranged to accommodate a variable number of members for each selected respective subset, at least one member having a valid non null memory node identifier and memory address range; the controller further comprising instructions to control the memory node responding to receipt of the batched transaction instruction set from an application node to safeguard the one or more memory address ranges specified by the members of the batched transaction instruction set for the duration of the execution of the batched transaction instruction set;wherein the write subset is collectively executed atomically. a plurality of discrete application nodes; a plurality of discrete memory nodes collectively providing an address space of shared memory; a network interconnecting the plurality of discrete application nodes and the plurality of discrete memory nodes, such that the address space is available to the application nodes; and a controller for directing transactions in a distributed system utilizing the shared memory, comprising instructions to permit an application node to transfer to at least one memory node a batched transaction instruction set, the batched transaction instruction set comprising a data structure including instruction subsets selected from the group consisting of: a write subset having at least one write member specifying a memory node identifier, a memory address range, and write data; a compare subset having at least one compare member specifying a memory node identifier, a memory address range, and compare data; a read subset having at least one read member specifying a memory node identifier, and a memory address range; and combinations of the write, compare and read subsets (322, 324, 326); wherein the data structure is arranged to accommodate a variable number of members for each selected respective subset, at least one member having a valid non null memory node identifier and memory address range; the controller further comprising instructions to control the memory node responding to receipt of the batched transaction instruction set from an application node to safeguard the one or more memory address ranges specified by the members of the batched transaction instruction set for the duration of the execution of the batched transaction instruction set;wherein the write subset is collectively executed atomically. a write subset having at least one write member specifying a memory node identifier, a memory address range, and write data; a compare subset having at least one compare member specifying a memory node identifier, a memory address range, and compare data; a read subset having at least one read member specifying a memory node identifier, and a memory address range; and combinations of the write, compare and read subsets (322, 324, 326); wherein the data structure is arranged to accommodate a variable number of members for each selected respective subset, at least one member having a valid non null memory node identifier and memory address range; the controller further comprising instructions to control the memory node responding to receipt of the batched transaction instruction set from an application node to safeguard the one or more memory address ranges specified by the members of the batched transaction instruction set for the duration of the execution of the batched transaction instruction set;wherein the write subset is collectively executed atomically.