A storage device comprising: at least one semiconductor memory device (400a-400k) configured to receive write data based on a data strobe signal and a plurality of data signals, and configured to output read data based on the data strobe signal and the plurality of data signals; and a storage controller configured to transmit the data strobe signal and the plurality of data signals in parallel to the at least one semiconductor memory device through a plurality of signal lines, wherein the storage controller includes: a processor configured to perform training to search for first skew offsets for minimizing crosstalk occurring among signal lines while transmitting training patterns to the at least one semiconductor memory device through the signal lines; a first register configured to store the first skew offsets as skew information based on a result of the training; a memory interface configured to transmit the skew information to the at least one semiconductor memory device; and a first delay circuit configured to delay the plurality of data signals, the data signals each having a window defined by a first edge and a second edge, such that at least some edges of windows of the plurality of data signals on the plurality of signal lines are desynchronized by respective first skew offsets, the respective first skew offsets being different from one another, wherein the memory interface configured to transmit the delayed data signals and the data strobe signal to the at least one semiconductor memory device through the signal lines, wherein the at least one semiconductor memory device includes a second register configured to store the skew information; and a second delay circuit configured to delay the data signals by second skew offsets based on the skew information to cancel the first skew offsets to provide original data signals. at least one semiconductor memory device (400a-400k) configured to receive write data based on a data strobe signal and a plurality of data signals, and configured to output read data based on the data strobe signal and the plurality of data signals; and a storage controller configured to transmit the data strobe signal and the plurality of data signals in parallel to the at least one semiconductor memory device through a plurality of signal lines, wherein the storage controller includes: a processor configured to perform training to search for first skew offsets for minimizing crosstalk occurring among signal lines while transmitting training patterns to the at least one semiconductor memory device through the signal lines; a first register configured to store the first skew offsets as skew information based on a result of the training; a memory interface configured to transmit the skew information to the at least one semiconductor memory device; and a first delay circuit configured to delay the plurality of data signals, the data signals each having a window defined by a first edge and a second edge, such that at least some edges of windows of the plurality of data signals on the plurality of signal lines are desynchronized by respective first skew offsets, the respective first skew offsets being different from one another, wherein the memory interface configured to transmit the delayed data signals and the data strobe signal to the at least one semiconductor memory device through the signal lines, wherein the at least one semiconductor memory device includes a second register configured to store the skew information; and a second delay circuit configured to delay the data signals by second skew offsets based on the skew information to cancel the first skew offsets to provide original data signals. a processor configured to perform training to search for first skew offsets for minimizing crosstalk occurring among signal lines while transmitting training patterns to the at least one semiconductor memory device through the signal lines; a first register configured to store the first skew offsets as skew information based on a result of the training; a memory interface configured to transmit the skew information to the at least one semiconductor memory device; and a first delay circuit configured to delay the plurality of data signals, the data signals each having a window defined by a first edge and a second edge, such that at least some edges of windows of the plurality of data signals on the plurality of signal lines are desynchronized by respective first skew offsets, the respective first skew offsets being different from one another, wherein the memory interface configured to transmit the delayed data signals and the data strobe signal to the at least one semiconductor memory device through the signal lines, wherein the at least one semiconductor memory device includes a second register configured to store the skew information; and a second delay circuit configured to delay the data signals by second skew offsets based on the skew information to cancel the first skew offsets to provide original data signals. a second register configured to store the skew information; and a second delay circuit configured to delay the data signals by second skew offsets based on the skew information to cancel the first skew offsets to provide original data signals.