A display system, comprising: a drive circuit (104, 164, 164A, 214) for a pixel (100, 130, 160, 160A, 160B, 190, 210, 240) having a light emitting device (102, 132, 162, 212, 242), comprising: a drive transistor (106, 166, 216) connected to the light emitting device, the drive transistor including a gate terminal, a first terminal and a second terminal; a first transistor (110, 170, 220) including a gate terminal, a first terminal and a second terminal, the gate terminal of the first transistor being connected to a select line, the first terminal of the first transistor being connected to a data line (VDATA); a storage capacitor (112, 174, 224) including a first terminal and a second terminal, the first terminal of the storage capacitor being connected to the gate terminal of the drive transistor at a node (A1, A2, A3), the second terminal of the storage capacitor (112, 174, 224) being connected to the second terminal of the drive transistor (106, 166, 216), wherein the storage capacitor is adapted such that the storage capacitor is charged according to a programming voltage during a programming cycle; and characterized by a circuit for adjusting the gate voltage of the drive transistor (106, 166, 216), the circuit including: a discharging transistor (108, 168, 218) having a gate terminal, a first terminal and a second terminal, the first terminal of the discharging transistor being connected to the gate terminal of the drive transistor, the gate terminal of the discharging transistor being directly connected to the gate terminal of the drive transistor, the second terminal of the discharging transistor being directly connected to the second terminal of the drive transistor (106, 166, 216); and wherein the voltage of the storage capacitor at the node is discharged through the discharging transistor in a cycle following the programming cycle. a drive circuit (104, 164, 164A, 214) for a pixel (100, 130, 160, 160A, 160B, 190, 210, 240) having a light emitting device (102, 132, 162, 212, 242), comprising: a drive transistor (106, 166, 216) connected to the light emitting device, the drive transistor including a gate terminal, a first terminal and a second terminal; a first transistor (110, 170, 220) including a gate terminal, a first terminal and a second terminal, the gate terminal of the first transistor being connected to a select line, the first terminal of the first transistor being connected to a data line (VDATA); a storage capacitor (112, 174, 224) including a first terminal and a second terminal, the first terminal of the storage capacitor being connected to the gate terminal of the drive transistor at a node (A1, A2, A3), the second terminal of the storage capacitor (112, 174, 224) being connected to the second terminal of the drive transistor (106, 166, 216), wherein the storage capacitor is adapted such that the storage capacitor is charged according to a programming voltage during a programming cycle; and characterized by a drive transistor (106, 166, 216) connected to the light emitting device, the drive transistor including a gate terminal, a first terminal and a second terminal; a first transistor (110, 170, 220) including a gate terminal, a first terminal and a second terminal, the gate terminal of the first transistor being connected to a select line, the first terminal of the first transistor being connected to a data line (VDATA); a storage capacitor (112, 174, 224) including a first terminal and a second terminal, the first terminal of the storage capacitor being connected to the gate terminal of the drive transistor at a node (A1, A2, A3), the second terminal of the storage capacitor (112, 174, 224) being connected to the second terminal of the drive transistor (106, 166, 216), wherein the storage capacitor is adapted such that the storage capacitor is charged according to a programming voltage during a programming cycle; and characterized by a circuit for adjusting the gate voltage of the drive transistor (106, 166, 216), the circuit including: a discharging transistor (108, 168, 218) having a gate terminal, a first terminal and a second terminal, the first terminal of the discharging transistor being connected to the gate terminal of the drive transistor, the gate terminal of the discharging transistor being directly connected to the gate terminal of the drive transistor, the second terminal of the discharging transistor being directly connected to the second terminal of the drive transistor (106, 166, 216); and a discharging transistor (108, 168, 218) having a gate terminal, a first terminal and a second terminal, the first terminal of the discharging transistor being connected to the gate terminal of the drive transistor, the gate terminal of the discharging transistor being directly connected to the gate terminal of the drive transistor, the second terminal of the discharging transistor being directly connected to the second terminal of the drive transistor (106, 166, 216); and wherein the voltage of the storage capacitor at the node is discharged through the discharging transistor in a cycle following the programming cycle.