A power-on reset circuit that is configured to generate a power-on reset, POR signal, comprising: a first comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first reference voltage, and the second input terminal coupled to a first voltage proportionate to a supply voltage (Vdd); a second comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a second voltage proportionate to the supply voltage (Vdd), and the second input terminal coupled to a second reference voltage, wherein the first and second reference voltages are proportional to a regulator voltage; and a latch circuit comprising a first NAND gate having a first input terminal, a second input terminal, and an output, and a second NAND gate having a first input terminal, a second input terminal and an output cross-coupled to the second terminal of the first gate, wherein the output terminal of the first comparator is coupled to the first input terminal of the first gate, the output terminal of the second comparator is coupled to the second input terminal of the second gate, and the output of the first gate is coupled to the first input terminal of the second gate of the latch circuit, wherein the output of the second gate is coupled to the second input terminal of the first gate to generate said POR signal as a de-assert signal to de-assert a reset state in response to the first voltage increasing above the first reference voltage once the supply voltage reaches a first threshold level and to generate said POR signal as a re-assert signal to re-assert the reset state in response to the second voltage dropping below the second reference voltage once the supply voltage falls below a second threshold level; and a storage circuit wherein the storage circuit comprises a NMOS transistor and a capacitor, the transistor having a drain coupled to the second reference voltage, a bulk terminal of the transistor that is grounded, a gate coupled to the supply voltage (Vdd), and a source coupled to the capacitor, wherein when the supply voltage (Vdd) exceeds the first threshold, the NMOS transistor is turned on whereby the capacitor is charged through the NMOS transistor to the same voltage level as the second reference voltage to store a stored version of the second reference voltage. a first comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first reference voltage, and the second input terminal coupled to a first voltage proportionate to a supply voltage (Vdd); a second comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a second voltage proportionate to the supply voltage (Vdd), and the second input terminal coupled to a second reference voltage, wherein the first and second reference voltages are proportional to a regulator voltage; and a latch circuit comprising a first NAND gate having a first input terminal, a second input terminal, and an output, and a second NAND gate having a first input terminal, a second input terminal and an output cross-coupled to the second terminal of the first gate, wherein the output terminal of the first comparator is coupled to the first input terminal of the first gate, the output terminal of the second comparator is coupled to the second input terminal of the second gate, and the output of the first gate is coupled to the first input terminal of the second gate of the latch circuit, wherein the output of the second gate is coupled to the second input terminal of the first gate to generate said POR signal as a de-assert signal to de-assert a reset state in response to the first voltage increasing above the first reference voltage once the supply voltage reaches a first threshold level and to generate said POR signal as a re-assert signal to re-assert the reset state in response to the second voltage dropping below the second reference voltage once the supply voltage falls below a second threshold level; and a storage circuit wherein the storage circuit comprises a NMOS transistor and a capacitor, the transistor having a drain coupled to the second reference voltage, a bulk terminal of the transistor that is grounded, a gate coupled to the supply voltage (Vdd), and a source coupled to the capacitor, wherein when the supply voltage (Vdd) exceeds the first threshold, the NMOS transistor is turned on whereby the capacitor is charged through the NMOS transistor to the same voltage level as the second reference voltage to store a stored version of the second reference voltage.