A transceiver circuit, comprising a first interface and a second interface that are connected to an optical transceiver device, a receiver circuit, a transmitter circuit, and a compensation circuit, wherein the receiver circuit comprises a differential amplifier, wherein a first phase input terminal of the differential amplifier is coupled to the first interface, and a second phase input terminal of the differential amplifier is coupled to the second interface; the transmitter circuit comprises a first transistor, wherein a terminal (r) of the first transistor is coupled to the second phase input terminal, and another terminal (t) of the first transistor is coupled to a ground terminal; and the compensation circuit is configured to provide a leakage path for the first phase input terminal; characterized in that when the compensation circuit is configured to provide the leakage path for the first phase input terminal, the compensation circuit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein a first terminal (j) of the sixth transistor is coupled to the first phase input terminal, a second terminal (m) of the sixth transistor is coupled to a ground terminal, and a gate control terminal (o) of the sixth transistor is coupled to a gate control terminal (q) of the fifth transistor; the gate control terminal of the fifth transistor is coupled to a first terminal (x) of the fifth transistor, the first terminal of the fifth transistor is coupled to a first terminal (p) of the fourth transistor, and a second terminal (y) of the fifth transistor is coupled to a ground terminal; a second terminal (z) of the fourth transistor is coupled to the first interface, and a gate control terminal of the fourth transistor is coupled to the gate control terminal of the third transistor; a first terminal of the third transistor is coupled to the first interface, a second terminal of the third transistor is coupled to a first terminal (u) of the second transistor, and the second terminal of the third transistor is coupled to a gate control terminal of the third transistor; and a second terminal (w) of the second transistor and a gate control terminal (v) of the second transistor are coupled to a ground terminal; or a gate control terminal of the second transistor is coupled to the first interface, and a second terminal of the second transistor is coupled to a ground terminal. the receiver circuit comprises a differential amplifier, wherein a first phase input terminal of the differential amplifier is coupled to the first interface, and a second phase input terminal of the differential amplifier is coupled to the second interface; the transmitter circuit comprises a first transistor, wherein a terminal (r) of the first transistor is coupled to the second phase input terminal, and another terminal (t) of the first transistor is coupled to a ground terminal; and the compensation circuit is configured to provide a leakage path for the first phase input terminal; characterized in that when the compensation circuit is configured to provide the leakage path for the first phase input terminal, the compensation circuit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein a first terminal (j) of the sixth transistor is coupled to the first phase input terminal, a second terminal (m) of the sixth transistor is coupled to a ground terminal, and a gate control terminal (o) of the sixth transistor is coupled to a gate control terminal (q) of the fifth transistor; the gate control terminal of the fifth transistor is coupled to a first terminal (x) of the fifth transistor, the first terminal of the fifth transistor is coupled to a first terminal (p) of the fourth transistor, and a second terminal (y) of the fifth transistor is coupled to a ground terminal; a second terminal (z) of the fourth transistor is coupled to the first interface, and a gate control terminal of the fourth transistor is coupled to the gate control terminal of the third transistor; a first terminal of the third transistor is coupled to the first interface, a second terminal of the third transistor is coupled to a first terminal (u) of the second transistor, and the second terminal of the third transistor is coupled to a gate control terminal of the third transistor; and a second terminal (w) of the second transistor and a gate control terminal (v) of the second transistor are coupled to a ground terminal; or a gate control terminal of the second transistor is coupled to the first interface, and a second terminal of the second transistor is coupled to a ground terminal.