A sampling switch circuit, comprising: an input node (V IN), connected to receive an input voltage signal; a sampling transistor (M S) comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node (V IN); a hold-control node connected to receive a hold-control voltage signal; an output node (V OUT) connected to the drain terminal of the sampling transistor (M S); a buffer circuit having a buffer input connected to the input node (V IN) and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal (V IN); and switching circuitry configured to connect the gate terminal of the sampling transistor (M S) to the track-control node or to the hold-control node in dependence upon a clock signal, the sampling switch circuit further comprising a potential divider circuit connected to the input node (V IN) and the buffer input to provide a buffer-input voltage signal dependent on the input voltage signal at the buffer input, the potential divider circuit comprising: a first impedance (R 1) connected between the input node (V IN) and the buffer input; a second impedance (R 2) connected between the buffer input and a first reference node (V REF); a third impedance (R 3) connected between the input node (V IN) and a sample node; and a fourth impedance (R 4) connected between the sample node and a second reference node, wherein: the source terminal of the sampling transistor is connected to the sample node and connected to the input node (V IN) via the sample node; and the first reference node (V REF) is connected to receive a first DC reference voltage signal and the second reference node is connected to receive a second DC reference voltage signal. an input node (V IN), connected to receive an input voltage signal; a sampling transistor (M S) comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node (V IN); a hold-control node connected to receive a hold-control voltage signal; an output node (V OUT) connected to the drain terminal of the sampling transistor (M S); a buffer circuit having a buffer input connected to the input node (V IN) and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal (V IN); and switching circuitry configured to connect the gate terminal of the sampling transistor (M S) to the track-control node or to the hold-control node in dependence upon a clock signal, the sampling switch circuit further comprising a potential divider circuit connected to the input node (V IN) and the buffer input to provide a buffer-input voltage signal dependent on the input voltage signal at the buffer input, the potential divider circuit comprising: a first impedance (R 1) connected between the input node (V IN) and the buffer input; a second impedance (R 2) connected between the buffer input and a first reference node (V REF); a third impedance (R 3) connected between the input node (V IN) and a sample node; and a fourth impedance (R 4) connected between the sample node and a second reference node, wherein: the source terminal of the sampling transistor is connected to the sample node and connected to the input node (V IN) via the sample node; and the first reference node (V REF) is connected to receive a first DC reference voltage signal and the second reference node is connected to receive a second DC reference voltage signal. a first impedance (R 1) connected between the input node (V IN) and the buffer input; a second impedance (R 2) connected between the buffer input and a first reference node (V REF); a third impedance (R 3) connected between the input node (V IN) and a sample node; and a fourth impedance (R 4) connected between the sample node and a second reference node, wherein: the source terminal of the sampling transistor is connected to the sample node and connected to the input node (V IN) via the sample node; and the first reference node (V REF) is connected to receive a first DC reference voltage signal and the second reference node is connected to receive a second DC reference voltage signal. the source terminal of the sampling transistor is connected to the sample node and connected to the input node (V IN) via the sample node; and the first reference node (V REF) is connected to receive a first DC reference voltage signal and the second reference node is connected to receive a second DC reference voltage signal.