A phase interpolator configured to receive a first input clock having a first input clock edge with a first phase, and a second input clock having a second input clock edge with a second phase delayed from the first phase; and produce an output clock having an output clock edge; the phase interpolator comprising an interpolating circuit unit comprising, between a first and a second supply line (155, 156) for receiving a first and a second DC potential, respectively, the first and the second DC potentials differing from each other: a plurality of resistors (153a, 153b) in parallel; for each of the resistors (153a, 153b), a connecting switch (157a, 157b) configured to connect and disconnect, in response to one of the first and the second input clocks (110, 120), the resistor (153a, 153b) to and from the first supply line, respectively; a capacitor in series with the plurality of the resistors (153a, 153b), wherein the capacitor is connected in between the plurality of resistors and the second supply line; an inverter having an inverter input connected to a node between the resistors (153a, 153b) and the capacitor to receive the voltage over the capacitor, the inverter being configured to determine an output signal of the interpolating circuit unit on the basis of the voltage over the capacitor passing a threshold voltage of the inverter after the second input clock edge; and a reset switch configured, when closed, to short circuit the capacitor; the phase interpolator being configured to: allow controlling of a partial group of the connecting switches (157a, 157b) to be operated in accordance with the first input clock, and controlling the rest of the connecting switches (157a, 157b) to be operated in accordance with the second input clock; and determine the output clock on the basis of the output signal of the interpolating circuit unit. a plurality of resistors (153a, 153b) in parallel; for each of the resistors (153a, 153b), a connecting switch (157a, 157b) configured to connect and disconnect, in response to one of the first and the second input clocks (110, 120), the resistor (153a, 153b) to and from the first supply line, respectively; a capacitor in series with the plurality of the resistors (153a, 153b), wherein the capacitor is connected in between the plurality of resistors and the second supply line; an inverter having an inverter input connected to a node between the resistors (153a, 153b) and the capacitor to receive the voltage over the capacitor, the inverter being configured to determine an output signal of the interpolating circuit unit on the basis of the voltage over the capacitor passing a threshold voltage of the inverter after the second input clock edge; and a reset switch configured, when closed, to short circuit the capacitor; the phase interpolator being configured to: allow controlling of a partial group of the connecting switches (157a, 157b) to be operated in accordance with the first input clock, and controlling the rest of the connecting switches (157a, 157b) to be operated in accordance with the second input clock; and determine the output clock on the basis of the output signal of the interpolating circuit unit. allow controlling of a partial group of the connecting switches (157a, 157b) to be operated in accordance with the first input clock, and controlling the rest of the connecting switches (157a, 157b) to be operated in accordance with the second input clock; and determine the output clock on the basis of the output signal of the interpolating circuit unit.