An imaging apparatus for use in an inspection machine which inspects the configuration of plural parts on a substrate, the apparatus comprising an imaging unit which comprises: an imaging region having a plurality of X- address line and a plurality of Y-address lines formed thereon, a plurality of pixels being formed near the intersections of the X-address lines and the Y-address lines, each pixel having an independent address, wherein the imaging region provides each pixel with a reading address; characterized in that said imaging unit further comprises: a first Y-register and a second Y-register arranged to select an arbitrary line out of said plurality of Y-address lines; a first X-register and a second X-register arranged to select an arbitrary line out of said plurality of X-address lines; a first switch arranged to supply output address data to the first Y-register or the second Y-register; a second switch arranged to supply output address data from the first Y-register or the second Y-register to a plurality of the Y-address lines; a third switch arranged to supply output address data to the first X-register or the second X-register; a fourth switch arranged to supply output address data from the first X-register or the second X-register to a plurality of the X-address lines; a RAM memory unit having stored therein the address data for specifying each pixel in regions corresponding to the plural parts; and a timing control unit adapted to provide to a timing pulse and clock, wherein the timing control unit is adapted to control the timing of the switching of the switches (711D, 711G, 712D, 712C), such that when X-address data is being read from one of the X-registers (712A, 712B), the next X-address data is being written into the other X-register (712B, 712A), and, when Y-address data is being read from one of the Y-registers (711A, 711B), the next Y- address data is being written into the other Y-register (711B, 711A). an imaging region having a plurality of X- address line and a plurality of Y-address lines formed thereon, a plurality of pixels being formed near the intersections of the X-address lines and the Y-address lines, each pixel having an independent address, wherein the imaging region provides each pixel with a reading address; characterized in that said imaging unit further comprises: a first Y-register and a second Y-register arranged to select an arbitrary line out of said plurality of Y-address lines; a first X-register and a second X-register arranged to select an arbitrary line out of said plurality of X-address lines; a first switch arranged to supply output address data to the first Y-register or the second Y-register; a second switch arranged to supply output address data from the first Y-register or the second Y-register to a plurality of the Y-address lines; a third switch arranged to supply output address data to the first X-register or the second X-register; a fourth switch arranged to supply output address data from the first X-register or the second X-register to a plurality of the X-address lines; a RAM memory unit having stored therein the address data for specifying each pixel in regions corresponding to the plural parts; and a timing control unit adapted to provide to a timing pulse and clock, wherein the timing control unit is adapted to control the timing of the switching of the switches (711D, 711G, 712D, 712C), such that when X-address data is being read from one of the X-registers (712A, 712B), the next X-address data is being written into the other X-register (712B, 712A), and, when Y-address data is being read from one of the Y-registers (711A, 711B), the next Y- address data is being written into the other Y-register (711B, 711A). a first Y-register and a second Y-register arranged to select an arbitrary line out of said plurality of Y-address lines; a first X-register and a second X-register arranged to select an arbitrary line out of said plurality of X-address lines; a first switch arranged to supply output address data to the first Y-register or the second Y-register; a second switch arranged to supply output address data from the first Y-register or the second Y-register to a plurality of the Y-address lines; a third switch arranged to supply output address data to the first X-register or the second X-register; a fourth switch arranged to supply output address data from the first X-register or the second X-register to a plurality of the X-address lines; a RAM memory unit having stored therein the address data for specifying each pixel in regions corresponding to the plural parts; and a timing control unit adapted to provide to a timing pulse and clock, wherein the timing control unit is adapted to control the timing of the switching of the switches (711D, 711G, 712D, 712C), such that when X-address data is being read from one of the X-registers (712A, 712B), the next X-address data is being written into the other X-register (712B, 712A), and, when Y-address data is being read from one of the Y-registers (711A, 711B), the next Y- address data is being written into the other Y-register (711B, 711A).