A power converter (11, 120) for synchronous rectification, comprising: 2N (N is an integer no less than two) switching elements (31, 33, 35, 37, 39, 311), of N phases, provided in higher and lower arms in a bridge arrangement; 2N freewheeling diodes (32, 34, 36, 38, 310, 312) connected in parallel with corresponding ones of the 2N switching elements (31, 33, 35, 37, 39, 311); and a diode conducting state detector arranged to determine times at which the 2N freewheeling diodes are turned on and off, characterized in that the power converter (11, 120) further comprises: an ON PLL circuit arranged to generate an ON synchronized signal formed as a result of synchronization control based on the times determined by the diode conducting state detector when the 2N freewheeling diodes (32, 34, 36, 38, 310, 312) are turned on; an OFF PLL circuit arranged to generate an OFF synchronized signal formed as a result of synchronization control based on the times determined by the diode conducting state detector when the 2N freewheeling diodes (32, 34, 36, 38, 310, 312) are turned off; and a gate instruction generator PWM section arranged to generate a gate instruction signal on the basis of the ON synchronized signal and the OFF synchronized signal, the gate instruction signal for controlling switching of the switching elements (31, 33, 35, 37, 39, 311). 2N (N is an integer no less than two) switching elements (31, 33, 35, 37, 39, 311), of N phases, provided in higher and lower arms in a bridge arrangement; 2N freewheeling diodes (32, 34, 36, 38, 310, 312) connected in parallel with corresponding ones of the 2N switching elements (31, 33, 35, 37, 39, 311); and a diode conducting state detector arranged to determine times at which the 2N freewheeling diodes are turned on and off, characterized in that the power converter (11, 120) further comprises: an ON PLL circuit arranged to generate an ON synchronized signal formed as a result of synchronization control based on the times determined by the diode conducting state detector when the 2N freewheeling diodes (32, 34, 36, 38, 310, 312) are turned on; an OFF PLL circuit arranged to generate an OFF synchronized signal formed as a result of synchronization control based on the times determined by the diode conducting state detector when the 2N freewheeling diodes (32, 34, 36, 38, 310, 312) are turned off; and a gate instruction generator PWM section arranged to generate a gate instruction signal on the basis of the ON synchronized signal and the OFF synchronized signal, the gate instruction signal for controlling switching of the switching elements (31, 33, 35, 37, 39, 311). an ON PLL circuit arranged to generate an ON synchronized signal formed as a result of synchronization control based on the times determined by the diode conducting state detector when the 2N freewheeling diodes (32, 34, 36, 38, 310, 312) are turned on; an OFF PLL circuit arranged to generate an OFF synchronized signal formed as a result of synchronization control based on the times determined by the diode conducting state detector when the 2N freewheeling diodes (32, 34, 36, 38, 310, 312) are turned off; and a gate instruction generator PWM section arranged to generate a gate instruction signal on the basis of the ON synchronized signal and the OFF synchronized signal, the gate instruction signal for controlling switching of the switching elements (31, 33, 35, 37, 39, 311).