An electronic component for providing a level shifted signal, comprising: one or more switches, configured to output the level-shifted signal; and a switch driver circuit, to drive the one or more switches, the switch driver circuit comprising: an input, to receive an input clock signal; an output, to provide an output clock signal to the one or more switches; a first transistor and a second transistor, each including a first terminal, a second terminal and a third terminal; a third transistor, including a first terminal, a second terminal and a third terminal, and coupled to the first transistor in a cascode arrangement; a coupling capacitor having a first capacitor electrode coupled to the input and a second capacitor electrode coupled to the first terminal of the second transistor; and a level shifter circuit, configured to level-shift the input clock signal to generate a level-shifted input clock signal to the second transistor, wherein: the first terminal of the first transistor is configured to receive the input clock signal, the first terminal of the second transistor is configured to receive the level-shifted input clock signal, the second terminal of the first transistor is coupled to the third terminal of the third transistor, the second terminal of the third transistor is coupled to the output, the second terminal of the second transistor is coupled to the output, the third terminal of the first transistor is coupled to a ground, the third terminal of the second transistor is coupled to a first reference voltage, and the first terminal of the third transistor is coupled to a second reference voltage. one or more switches, configured to output the level-shifted signal; and a switch driver circuit, to drive the one or more switches, the switch driver circuit comprising: an input, to receive an input clock signal; an output, to provide an output clock signal to the one or more switches; a first transistor and a second transistor, each including a first terminal, a second terminal and a third terminal; a third transistor, including a first terminal, a second terminal and a third terminal, and coupled to the first transistor in a cascode arrangement; a coupling capacitor having a first capacitor electrode coupled to the input and a second capacitor electrode coupled to the first terminal of the second transistor; and a level shifter circuit, configured to level-shift the input clock signal to generate a level-shifted input clock signal to the second transistor, an input, to receive an input clock signal; an output, to provide an output clock signal to the one or more switches; a first transistor and a second transistor, each including a first terminal, a second terminal and a third terminal; a third transistor, including a first terminal, a second terminal and a third terminal, and coupled to the first transistor in a cascode arrangement; a coupling capacitor having a first capacitor electrode coupled to the input and a second capacitor electrode coupled to the first terminal of the second transistor; and a level shifter circuit, configured to level-shift the input clock signal to generate a level-shifted input clock signal to the second transistor, wherein: the first terminal of the first transistor is configured to receive the input clock signal, the first terminal of the second transistor is configured to receive the level-shifted input clock signal, the second terminal of the first transistor is coupled to the third terminal of the third transistor, the second terminal of the third transistor is coupled to the output, the second terminal of the second transistor is coupled to the output, the third terminal of the first transistor is coupled to a ground, the third terminal of the second transistor is coupled to a first reference voltage, and the first terminal of the third transistor is coupled to a second reference voltage. the first terminal of the first transistor is configured to receive the input clock signal, the first terminal of the second transistor is configured to receive the level-shifted input clock signal, the second terminal of the first transistor is coupled to the third terminal of the third transistor, the second terminal of the third transistor is coupled to the output, the second terminal of the second transistor is coupled to the output, the third terminal of the first transistor is coupled to a ground, the third terminal of the second transistor is coupled to a first reference voltage, and the first terminal of the third transistor is coupled to a second reference voltage.