An electronic device (101, 201, 1101, 1201) comprising: a display (160, 260); and a processor (120, 220) including a plurality of cores (221, 222, 223), the plurality of cores including at least a first core of a first type, a second core of a second type and a third core of a third type, wherein the processor (120, 220) is configured to: identify a first application satisfying a designated condition related to boosting of the processor (120, 220) among at least one application running on the processor; identify a first instruction set architecture, ISA, of the first application; and boost a frequency of a clock signal applied to at least one core among the plurality of cores (221, 222, 223) included in the processor (120, 220) according to the first instruction set architecture, wherein the processor (120, 220) is configured to: determine a frequency value for boosting the at least one core according to the first instruction set architecture; and control the at least one core to be driven using a clock signal having a frequency equal to or greater than the determined frequency value, characterized in that, the processor (120, 220) is configured to determine the frequency value using a table corresponding performance and power consumption of each of the first, second and third types of cores (221, 222, 223) to specific frequency values according to a type of instruction set architecture. a display (160, 260); and a processor (120, 220) including a plurality of cores (221, 222, 223), the plurality of cores including at least a first core of a first type, a second core of a second type and a third core of a third type, wherein the processor (120, 220) is configured to: identify a first application satisfying a designated condition related to boosting of the processor (120, 220) among at least one application running on the processor; identify a first instruction set architecture, ISA, of the first application; and boost a frequency of a clock signal applied to at least one core among the plurality of cores (221, 222, 223) included in the processor (120, 220) according to the first instruction set architecture, wherein the processor (120, 220) is configured to: determine a frequency value for boosting the at least one core according to the first instruction set architecture; and control the at least one core to be driven using a clock signal having a frequency equal to or greater than the determined frequency value, characterized in that, the processor (120, 220) is configured to determine the frequency value using a table corresponding performance and power consumption of each of the first, second and third types of cores (221, 222, 223) to specific frequency values according to a type of instruction set architecture. determine a frequency value for boosting the at least one core according to the first instruction set architecture; and control the at least one core to be driven using a clock signal having a frequency equal to or greater than the determined frequency value, characterized in that, the processor (120, 220) is configured to determine the frequency value using a table corresponding performance and power consumption of each of the first, second and third types of cores (221, 222, 223) to specific frequency values according to a type of instruction set architecture.