A method of forming a memory device, comprising: forming, in a substrate of a first conductivity type, spaced apart first and second regions (50, 82) of a second conductivity type, defining a channel region therebetween; forming a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region; forming a control gate disposed over and insulated from the floating gate; forming an erase gate disposed over and insulated from the first region; forming a select gate over and insulated from a second portion of the channel region which is adjacent to the second region; forming a first logic gate over and insulated from the substrate; forming in the substrate spaced apart third and fourth regions (90, 92) of the second conductivity type, defining a second channel region therebetween, wherein the first logic gate is disposed over the second channel region; wherein the forming of the floating gate includes depositing a first polysilicon layer over and insulated from the substrate, and etching through the first polysilicon layer leaving a block of the first polysilicon layer that constitutes the floating gate; wherein the forming of the control gate includes depositing a second polysilicon layer over and insulated from the first polysilicon layer, and etching through the second polysilicon layer leaving a block of the second polysilicon layer that constitutes the control gate; wherein the forming of the erase gate includes depositing a third polysilicon layer over and insulated from the first region; wherein the forming of the select gate includes depositing a fourth polysilicon layer over and insulated from the substrate, and etching through a first portion of the fourth polysilicon layer leaving a first block of the fourth polysilicon layer laterally adjacent to and insulated from the floating gate and the control gate; wherein the forming of the first logic gate includes forming an oxide layer over a second portion of the fourth polysilicon layer such that the first portion of the fourth polysilicon layer is left exposed, characterized in that, the method further comprises forming polysilicon over the oxide layer and thickening the first portion of the fourth polysilicon layer, removing the polysilicon over the oxide layer and reducing a height of the first portion of the fourth polysilicon layer, removing the oxide layer, and etching through the second portion of the fourth polysilicon layer leaving a second block of the fourth polysilicon layer, wherein the first block of the fourth polysilicon layer has a height greater than that of the second block of the fourth polysilicon layer. forming, in a substrate of a first conductivity type, spaced apart first and second regions (50, 82) of a second conductivity type, defining a channel region therebetween; forming a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region; forming a control gate disposed over and insulated from the floating gate; forming an erase gate disposed over and insulated from the first region; forming a select gate over and insulated from a second portion of the channel region which is adjacent to the second region; forming a first logic gate over and insulated from the substrate; forming in the substrate spaced apart third and fourth regions (90, 92) of the second conductivity type, defining a second channel region therebetween, wherein the first logic gate is disposed over the second channel region; wherein the forming of the floating gate includes depositing a first polysilicon layer over and insulated from the substrate, and etching through the first polysilicon layer leaving a block of the first polysilicon layer that constitutes the floating gate; wherein the forming of the control gate includes depositing a second polysilicon layer over and insulated from the first polysilicon layer, and etching through the second polysilicon layer leaving a block of the second polysilicon layer that constitutes the control gate; wherein the forming of the erase gate includes depositing a third polysilicon layer over and insulated from the first region; wherein the forming of the select gate includes depositing a fourth polysilicon layer over and insulated from the substrate, and etching through a first portion of the fourth polysilicon layer leaving a first block of the fourth polysilicon layer laterally adjacent to and insulated from the floating gate and the control gate; wherein the forming of the first logic gate includes forming an oxide layer over a second portion of the fourth polysilicon layer such that the first portion of the fourth polysilicon layer is left exposed, characterized in that, the method further comprises forming polysilicon over the oxide layer and thickening the first portion of the fourth polysilicon layer, removing the polysilicon over the oxide layer and reducing a height of the first portion of the fourth polysilicon layer, removing the oxide layer, and etching through the second portion of the fourth polysilicon layer leaving a second block of the fourth polysilicon layer, wherein the first block of the fourth polysilicon layer has a height greater than that of the second block of the fourth polysilicon layer.