An apparatus comprising: a hardware processing core in a multi-processing core system, wherein the hardware processing core is configured to execute a sequence of instructions as an atomic memory transaction, wherein the hardware processing core is configured to issue each instruction in the sequence to an execution pipeline, wherein the execution pipeline is configured to validate each instruction of the sequence during a validate stage of the execution pipeline that is prior to an execute stage of the execution pipeline, wherein the execute stage is configured to compute instruction results; wherein the apparatus is configured to identify the sequence of instructions based on demarcation information that specifies a start and an end of the sequence of instructions; wherein the validate stage is configured to determine types of instructions in the sequence based on opcodes of the instructions in the sequence, and wherein the validate stage is configured to allow execution of the sequence of instructions as an atomic memory transaction only if none of the instructions in the sequence of instructions have an opcode indicating an instruction type that permits direct access to shared memory; wherein the apparatus is configured to: store memory data from a source cache line into a target register and lock the source cache line before storing the memory data from the source cache line into the target register; store a modified value from the target register to the source cache line after reading data from the target register and writing data to the target register based on executing the sequence of instructions; and unlock the source cache line after storing the value from the target register to the source cache line. a hardware processing core in a multi-processing core system, wherein the hardware processing core is configured to execute a sequence of instructions as an atomic memory transaction, wherein the hardware processing core is configured to issue each instruction in the sequence to an execution pipeline, wherein the execution pipeline is configured to validate each instruction of the sequence during a validate stage of the execution pipeline that is prior to an execute stage of the execution pipeline, wherein the execute stage is configured to compute instruction results; wherein the apparatus is configured to identify the sequence of instructions based on demarcation information that specifies a start and an end of the sequence of instructions; wherein the validate stage is configured to determine types of instructions in the sequence based on opcodes of the instructions in the sequence, and wherein the validate stage is configured to allow execution of the sequence of instructions as an atomic memory transaction only if none of the instructions in the sequence of instructions have an opcode indicating an instruction type that permits direct access to shared memory; wherein the apparatus is configured to: store memory data from a source cache line into a target register and lock the source cache line before storing the memory data from the source cache line into the target register; store a modified value from the target register to the source cache line after reading data from the target register and writing data to the target register based on executing the sequence of instructions; and unlock the source cache line after storing the value from the target register to the source cache line. store memory data from a source cache line into a target register and lock the source cache line before storing the memory data from the source cache line into the target register; store a modified value from the target register to the source cache line after reading data from the target register and writing data to the target register based on executing the sequence of instructions; and unlock the source cache line after storing the value from the target register to the source cache line.