An array substrate, comprising: a fan-out lead structure, wherein the fan-out lead structure comprises a plurality of data fan-out leads; and a power line structure, comprising a conductive plate, wherein the conductive plate comprises a through hole disposing area, and in the through hole disposing area the conductive plate is provided with a plurality of through holes; wherein an orthogonal projection of at least a part of the plurality of through holes on a surface of the array substrate is partially overlapped with an orthogonal projection of the plurality of data fan-out leads on the surface of the array substrate; wherein: the power line structure and the plurality of data fan-out leads are provided in different layers, and the plurality of through holes are configured to reduce crosstalk caused by an overlap between the conductive plate and the plurality of data fan-out leads; the conductive plate comprises a first input terminal and a second input terminal disposed on a side of the conductive plate; the conductive plate comprises a plurality of output terminals disposed on the other side of the conductive plate opposite to the first and second input terminals (111, 112); a distribution density of the plurality of through holes increases linearly from the first input terminal to a middle point between the first input terminal and the second input terminal; and a distribution density of the plurality of through holes increases linearly from the second input terminal to the middle point between the first input terminal and the second input terminal. a fan-out lead structure, wherein the fan-out lead structure comprises a plurality of data fan-out leads; and a power line structure, comprising a conductive plate, wherein the conductive plate comprises a through hole disposing area, and in the through hole disposing area the conductive plate is provided with a plurality of through holes; wherein an orthogonal projection of at least a part of the plurality of through holes on a surface of the array substrate is partially overlapped with an orthogonal projection of the plurality of data fan-out leads on the surface of the array substrate; wherein: the power line structure and the plurality of data fan-out leads are provided in different layers, and the plurality of through holes are configured to reduce crosstalk caused by an overlap between the conductive plate and the plurality of data fan-out leads; the conductive plate comprises a first input terminal and a second input terminal disposed on a side of the conductive plate; the conductive plate comprises a plurality of output terminals disposed on the other side of the conductive plate opposite to the first and second input terminals (111, 112); a distribution density of the plurality of through holes increases linearly from the first input terminal to a middle point between the first input terminal and the second input terminal; and a distribution density of the plurality of through holes increases linearly from the second input terminal to the middle point between the first input terminal and the second input terminal. the power line structure and the plurality of data fan-out leads are provided in different layers, and the plurality of through holes are configured to reduce crosstalk caused by an overlap between the conductive plate and the plurality of data fan-out leads; the conductive plate comprises a first input terminal and a second input terminal disposed on a side of the conductive plate; the conductive plate comprises a plurality of output terminals disposed on the other side of the conductive plate opposite to the first and second input terminals (111, 112); a distribution density of the plurality of through holes increases linearly from the first input terminal to a middle point between the first input terminal and the second input terminal; and a distribution density of the plurality of through holes increases linearly from the second input terminal to the middle point between the first input terminal and the second input terminal.