A method, comprising: transitioning a memory device from a first power level to a second power level; initiating a training procedure comprising a baseline level training procedure and a plurality of individual level training procedures based at least in part on transitioning the memory device from the first power level to the second power level; receiving, from a transmitting device, a single training burst comprising a plurality of symbols during a series of unit intervals (305; 505; 605) based at least in part on initiating the training procedure, each unit interval of the series of unit intervals (305; 505; 605) being defined by a clock signal and comprising one symbol of the plurality of symbols; identifying, based at least in part on initiating the baseline level training procedure, a baseline level offset associated with a first reference voltage (315; 510, 515; 615) for distinguishing a first symbol candidate from a second symbol candidate in the plurality of symbols of the single training burst; identifying, based at least in part on initiating the baseline level training procedure, a first level offset for the first reference voltage (315; 515; 615) in a first unit interval (305-a; 505-a; 605-a) of the series of unit intervals (305; 505; 605) and a second level offset for the first reference voltage (315; 615) in a second unit interval (305-b; 505-b; 605-b) of the series of unit intervals (305; 505; 605) after identifying the baseline level offset, the first level offset being different than the second level offset; and configuring, based at least in part on performing the baseline level training procedure and the plurality of individual level training procedures, the first reference voltage in the first unit interval (305-a; 505-a; 605-a) with the first level offset and the first reference voltage in the second unit interval (305-b; 505-b; 605-b) with the second level offset. transitioning a memory device from a first power level to a second power level; initiating a training procedure comprising a baseline level training procedure and a plurality of individual level training procedures based at least in part on transitioning the memory device from the first power level to the second power level; receiving, from a transmitting device, a single training burst comprising a plurality of symbols during a series of unit intervals (305; 505; 605) based at least in part on initiating the training procedure, each unit interval of the series of unit intervals (305; 505; 605) being defined by a clock signal and comprising one symbol of the plurality of symbols; identifying, based at least in part on initiating the baseline level training procedure, a baseline level offset associated with a first reference voltage (315; 510, 515; 615) for distinguishing a first symbol candidate from a second symbol candidate in the plurality of symbols of the single training burst; identifying, based at least in part on initiating the baseline level training procedure, a first level offset for the first reference voltage (315; 515; 615) in a first unit interval (305-a; 505-a; 605-a) of the series of unit intervals (305; 505; 605) and a second level offset for the first reference voltage (315; 615) in a second unit interval (305-b; 505-b; 605-b) of the series of unit intervals (305; 505; 605) after identifying the baseline level offset, the first level offset being different than the second level offset; and configuring, based at least in part on performing the baseline level training procedure and the plurality of individual level training procedures, the first reference voltage in the first unit interval (305-a; 505-a; 605-a) with the first level offset and the first reference voltage in the second unit interval (305-b; 505-b; 605-b) with the second level offset.