A differential low noise amplifier, LNA, having a differential input and a differential output, the LNA comprising: a plurality of DC biasing circuits (DC BIAS); a radio frequency differential input stage (RFINP, RFINM) comprising: a pair of RF input transistors, each RF input transistor (M1, M2) having a source/emitter node, a gate/base node and a drain/collector node, an RF inductor (L s) associated with each RF input transistor (M1, M2) and configured to couple the associated RF transistor source/emitter node to a reference voltage, a DC bias resistor associated with each RF input transistor (M1, M2) and configured to couple the associated RF transistor to a DC bias source, and a cascode stage (M3,M4) associated with each RF input transistor (M1, M2) and connected between the drain/collector of the associated RF input transistor and a node of the differential output of the LNA; a RF output matching stage comprising an adjustable inductor (502,504), wherein the adjustable inductor comprises: a primary inductor connected between the nodes (RFOUTM, RFOUTP) of the differential output of the LNA; a secondary inductor having a first and a second terminal, wherein said primary and secondary inductors are magnetically coupled; wherein each DC biasing circuit (DC BIAS) comprises a DC bias switch (M5-M8) associated with one of the RF input transistors (M1, M2) and is configured to selectively couple the associated RF input transistor drain/collector node to either first or second terminal of the secondary inductor, wherein each DC bias switch (M5-M8) comprises a transistor selectively activated via a DC bias source (DC BIAS/VSS). a plurality of DC biasing circuits (DC BIAS); a radio frequency differential input stage (RFINP, RFINM) comprising: a pair of RF input transistors, each RF input transistor (M1, M2) having a source/emitter node, a gate/base node and a drain/collector node, an RF inductor (L s) associated with each RF input transistor (M1, M2) and configured to couple the associated RF transistor source/emitter node to a reference voltage, a DC bias resistor associated with each RF input transistor (M1, M2) and configured to couple the associated RF transistor to a DC bias source, and a cascode stage (M3,M4) associated with each RF input transistor (M1, M2) and connected between the drain/collector of the associated RF input transistor and a node of the differential output of the LNA; a pair of RF input transistors, each RF input transistor (M1, M2) having a source/emitter node, a gate/base node and a drain/collector node, an RF inductor (L s) associated with each RF input transistor (M1, M2) and configured to couple the associated RF transistor source/emitter node to a reference voltage, a DC bias resistor associated with each RF input transistor (M1, M2) and configured to couple the associated RF transistor to a DC bias source, and a cascode stage (M3,M4) associated with each RF input transistor (M1, M2) and connected between the drain/collector of the associated RF input transistor and a node of the differential output of the LNA; a RF output matching stage comprising an adjustable inductor (502,504), wherein the adjustable inductor comprises: a primary inductor connected between the nodes (RFOUTM, RFOUTP) of the differential output of the LNA; a secondary inductor having a first and a second terminal, wherein said primary and secondary inductors are magnetically coupled; a primary inductor connected between the nodes (RFOUTM, RFOUTP) of the differential output of the LNA; a secondary inductor having a first and a second terminal, wherein said primary and secondary inductors are magnetically coupled; wherein each DC biasing circuit (DC BIAS) comprises a DC bias switch (M5-M8) associated with one of the RF input transistors (M1, M2) and is configured to selectively couple the associated RF input transistor drain/collector node to either first or second terminal of the secondary inductor, wherein each DC bias switch (M5-M8) comprises a transistor selectively activated via a DC bias source (DC BIAS/VSS).