A method for running integration tests using unit tests during model-based development, the method comprising: receiving, by a processor circuit, a plurality of models making-up a system, wherein each model comprises a logic circuit (202, 206) defining a requirement (204, 208), part of a requirement, or a group of requirements that the system is configured to satisfy, wherein each model is configured to generate one or more expected outputs in response to one or more inputs based on the logic circuit (202, 206) associated with the particular model; automatically running, by the processor circuit, a unit test for each model of the plurality of models making-up the system, by generating an expected output value for each of one or more outputs of each model in response to an input value for each of one or more inputs of each model for all combinations of possible different input values for each model, wherein each particular model is unit tested independent from other models of other system requirements (204, 208) that provide inputs to the particular model; determining groups of interfacing models (104a, 104b) of the plurality of models, wherein each group of interfacing models (104, 104b) include two or more models that interface with each other; automatically running, by the processor circuit, an integration test for each group of interfacing models (104a, 104b) of the plurality of models using the unit tests for each model of the interfacing models (104a, 104b), by automatically generating a table for each group of interfacing models (104a, 104b) from the unit tests for each model, the table for a particular group of interfacing models (104a, 104b) comprising an expected output value for each of one or more outputs of the particular group of interfacing models (104a, 104b) associated with an input value for each of one or more inputs of the particular group of interfacing models (104a, 104b) for each combination of possible different input values of the particular group of interfacing models (104a, 104b); automatically detecting, by the processor circuit, at least one of inconsistent, incomplete or incorrect data transmitted between the interfacing models (104a, 104b) for each group of interfacing models (104a, 104b), wherein the table for a particular group of interfacing models (104a, 104b) is used to detect at least one of inconsistent, incomplete or incorrect data between the interfacing models (104a, 104b) of said particular group of interfacing models (104a, 104b); and performing a model-based development of the system using the detected inconsistent, incomplete or incorrect data. receiving, by a processor circuit, a plurality of models making-up a system, wherein each model comprises a logic circuit (202, 206) defining a requirement (204, 208), part of a requirement, or a group of requirements that the system is configured to satisfy, wherein each model is configured to generate one or more expected outputs in response to one or more inputs based on the logic circuit (202, 206) associated with the particular model; automatically running, by the processor circuit, a unit test for each model of the plurality of models making-up the system, by generating an expected output value for each of one or more outputs of each model in response to an input value for each of one or more inputs of each model for all combinations of possible different input values for each model, wherein each particular model is unit tested independent from other models of other system requirements (204, 208) that provide inputs to the particular model; determining groups of interfacing models (104a, 104b) of the plurality of models, wherein each group of interfacing models (104, 104b) include two or more models that interface with each other; automatically running, by the processor circuit, an integration test for each group of interfacing models (104a, 104b) of the plurality of models using the unit tests for each model of the interfacing models (104a, 104b), by automatically generating a table for each group of interfacing models (104a, 104b) from the unit tests for each model, the table for a particular group of interfacing models (104a, 104b) comprising an expected output value for each of one or more outputs of the particular group of interfacing models (104a, 104b) associated with an input value for each of one or more inputs of the particular group of interfacing models (104a, 104b) for each combination of possible different input values of the particular group of interfacing models (104a, 104b); automatically detecting, by the processor circuit, at least one of inconsistent, incomplete or incorrect data transmitted between the interfacing models (104a, 104b) for each group of interfacing models (104a, 104b), wherein the table for a particular group of interfacing models (104a, 104b) is used to detect at least one of inconsistent, incomplete or incorrect data between the interfacing models (104a, 104b) of said particular group of interfacing models (104a, 104b); and performing a model-based development of the system using the detected inconsistent, incomplete or incorrect data.