A display device comprising: a display unit comprising a plurality of pixels configured to display an image by emitting light based on a data voltage corresponding to an image data signal; a driving circuit configured to drive the display unit; at least one clock signal wire (CL1, CL2, CL3) configured to transmit a clock signal to the driving circuit; and a static electricity prevention circuit comprising: at least one transistor (T1, T2, T3) wherein the clock signal wire is coupled with a gate electrode (1 G) of the transistor through a gate metal wire (GL1, GL2, GL3); and at least one capacitor (C1, C2, C3) comprising a first electrode (CE1, CE2) coupled to a source electrode and to a drain electrode of the transistor, and a second electrode configured to be maintained at a voltage; wherein the gate metal wire (GL1, GL2, GL3) does not follow the antenna rule such that when an external static electricity flows through the clock signal wire (CL1, CL2, CL3), a gate insulation layer of the transistor (T1, T2, T3) is burnt or damaged and the gate insulation layer is creating an electrical short-circuit by the static electricity current flowing through the at least one clock signal wire; wherein the capacitor is configured to accumulate the inflowing static electricity current when the gate insulation layer is short-circuited. a display unit comprising a plurality of pixels configured to display an image by emitting light based on a data voltage corresponding to an image data signal; a driving circuit configured to drive the display unit; at least one clock signal wire (CL1, CL2, CL3) configured to transmit a clock signal to the driving circuit; and a static electricity prevention circuit comprising: at least one transistor (T1, T2, T3) wherein the clock signal wire is coupled with a gate electrode (1 G) of the transistor through a gate metal wire (GL1, GL2, GL3); and at least one capacitor (C1, C2, C3) comprising a first electrode (CE1, CE2) coupled to a source electrode and to a drain electrode of the transistor, and a second electrode configured to be maintained at a voltage; wherein the gate metal wire (GL1, GL2, GL3) does not follow the antenna rule such that when an external static electricity flows through the clock signal wire (CL1, CL2, CL3), a gate insulation layer of the transistor (T1, T2, T3) is burnt or damaged and the gate insulation layer is creating an electrical short-circuit by the static electricity current flowing through the at least one clock signal wire; at least one transistor (T1, T2, T3) wherein the clock signal wire is coupled with a gate electrode (1 G) of the transistor through a gate metal wire (GL1, GL2, GL3); and at least one capacitor (C1, C2, C3) comprising a first electrode (CE1, CE2) coupled to a source electrode and to a drain electrode of the transistor, and a second electrode configured to be maintained at a voltage; wherein the gate metal wire (GL1, GL2, GL3) does not follow the antenna rule such that when an external static electricity flows through the clock signal wire (CL1, CL2, CL3), a gate insulation layer of the transistor (T1, T2, T3) is burnt or damaged and the gate insulation layer is creating an electrical short-circuit by the static electricity current flowing through the at least one clock signal wire;