An apparatus, comprising: a set of NAND strings (700n, 710n, 720n, 730n), the set of NAND strings (700n, 710n, 720n, 730n) extends in a lower tier (600, 1605) and an upper tier (601, 1616) of a stack, the lower tier separated from the upper tier by an interface, each NAND string comprising a channel (700a, 710a, 720a, 730a), a set of memory cells (703-714, 713-734, 743-754, 753-774), a source end, a drain end and a drain-side select gate transistor (716, 736, 756, 776); and a control circuit (110, 122) configured to, in response to a read command, discharge the channels during a discharge period (1205a, 1205b) before reading selected memory cells in the set of NAND strings (700n, 710n, 720n, 730n), wherein the discharge period is longer when the selected memory cells are at a top of the lower tier (600, 1605) than when the selected memory cells are at a bottom of the lower tier (600, 1605), wherein in the discharge period, a voltage applied to the selected memory cells is ramped up from an initial voltage to a peak voltage while the drain ends and source ends of the NAND strings (700n, 710n, 720n, 730n) are grounded; wherein when the selected memory cells are in the lower tier (600, 1605): the control circuit (110, 122) is configured to increase the discharge period (1205a, 1205b) as a function of an increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a bottom of the lower tier (600, 1605); and the discharge period (1205a, 1205b) is non-increasing with the increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a top of the lower tier (600, 1605). a set of NAND strings (700n, 710n, 720n, 730n), the set of NAND strings (700n, 710n, 720n, 730n) extends in a lower tier (600, 1605) and an upper tier (601, 1616) of a stack, the lower tier separated from the upper tier by an interface, each NAND string comprising a channel (700a, 710a, 720a, 730a), a set of memory cells (703-714, 713-734, 743-754, 753-774), a source end, a drain end and a drain-side select gate transistor (716, 736, 756, 776); and a control circuit (110, 122) configured to, in response to a read command, discharge the channels during a discharge period (1205a, 1205b) before reading selected memory cells in the set of NAND strings (700n, 710n, 720n, 730n), wherein the discharge period is longer when the selected memory cells are at a top of the lower tier (600, 1605) than when the selected memory cells are at a bottom of the lower tier (600, 1605), wherein in the discharge period, a voltage applied to the selected memory cells is ramped up from an initial voltage to a peak voltage while the drain ends and source ends of the NAND strings (700n, 710n, 720n, 730n) are grounded; wherein when the selected memory cells are in the lower tier (600, 1605): the control circuit (110, 122) is configured to increase the discharge period (1205a, 1205b) as a function of an increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a bottom of the lower tier (600, 1605); and the discharge period (1205a, 1205b) is non-increasing with the increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a top of the lower tier (600, 1605). the control circuit (110, 122) is configured to increase the discharge period (1205a, 1205b) as a function of an increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a bottom of the lower tier (600, 1605); and the discharge period (1205a, 1205b) is non-increasing with the increasing height of the selected memory cells when the selected memory cells are in a group of memory cells adjacent to a top of the lower tier (600, 1605).