A method for fabricating a memory device, comprising: forming a stack (1000a, 1100a, 1200a) comprising alternating control gate layers (SGS0, SGS1, WLD4, WLD3, WLLO-WLL10, WLD1, WLD2, SGD1, SGD0) and dielectric layers (DLO-DL19), wherein the control gate layers comprise a control gate layer (SGD0, SGD1) for a select gate transistor (1020, 1022, 1130, 1132, 1230, 1232) of a NAND string (NS1, NS2; NSO_SBa, NS0_SBb, NS0_SBc and NS0_SBd) above control gate layers for memory cells (1024, 1134, 1234) of the NAND string; etching a memory hole (618, 619; 630, 710, 711, 714-719; 1001, 1002; 1101, 1102; 1201, 1202) in the stack; providing memory films (1003, 1004, 1005; 1103, 1104, 1105; 1203, 1204, 1205) along a wall of the memory hole adjacent to the control gate layers for the memory cells; providing polysilicon in the memory hole and converting the polysilicon to crystalline silicon (1010, 1010a) using laser thermal annealing, wherein the crystalline silicon spans the control gate layer for the select gate transistor; and providing a metal in the control gate layer for the select gate transistor, wherein the crystalline silicon forms a channel (1005, 1020ch, 1022ch) of the select gate transistor, the metal provides a control gate (1020cg, 1022cg) of the select gate transistor and a gate oxide (1020ox, 1022ox) of the select gate transistor is provided between the metal and the crystalline silicon, wherein: the select gate transistor is a topmost select gate transistor among a plurality of select gate transistors at a top of the NAND string; and an additional select gate transistor is provided below the topmost select gate transistor; characterised in that: the memory films extend to a height of the additional select gate transistor; a bottom of the crystalline silicon is above a top of the additional select gate transistor; and a bottom of the gate oxide is above the top of the additional select gate transistor. forming a stack (1000a, 1100a, 1200a) comprising alternating control gate layers (SGS0, SGS1, WLD4, WLD3, WLLO-WLL10, WLD1, WLD2, SGD1, SGD0) and dielectric layers (DLO-DL19), wherein the control gate layers comprise a control gate layer (SGD0, SGD1) for a select gate transistor (1020, 1022, 1130, 1132, 1230, 1232) of a NAND string (NS1, NS2; NSO_SBa, NS0_SBb, NS0_SBc and NS0_SBd) above control gate layers for memory cells (1024, 1134, 1234) of the NAND string; etching a memory hole (618, 619; 630, 710, 711, 714-719; 1001, 1002; 1101, 1102; 1201, 1202) in the stack; providing memory films (1003, 1004, 1005; 1103, 1104, 1105; 1203, 1204, 1205) along a wall of the memory hole adjacent to the control gate layers for the memory cells; providing polysilicon in the memory hole and converting the polysilicon to crystalline silicon (1010, 1010a) using laser thermal annealing, wherein the crystalline silicon spans the control gate layer for the select gate transistor; and providing a metal in the control gate layer for the select gate transistor, wherein the crystalline silicon forms a channel (1005, 1020ch, 1022ch) of the select gate transistor, the metal provides a control gate (1020cg, 1022cg) of the select gate transistor and a gate oxide (1020ox, 1022ox) of the select gate transistor is provided between the metal and the crystalline silicon, wherein: the select gate transistor is a topmost select gate transistor among a plurality of select gate transistors at a top of the NAND string; and an additional select gate transistor is provided below the topmost select gate transistor; characterised in that: the memory films extend to a height of the additional select gate transistor; a bottom of the crystalline silicon is above a top of the additional select gate transistor; and a bottom of the gate oxide is above the top of the additional select gate transistor. the select gate transistor is a topmost select gate transistor among a plurality of select gate transistors at a top of the NAND string; and an additional select gate transistor is provided below the topmost select gate transistor; the memory films extend to a height of the additional select gate transistor; a bottom of the crystalline silicon is above a top of the additional select gate transistor; and a bottom of the gate oxide is above the top of the additional select gate transistor.