A transmitter, comprising: an output signal terminal; a plurality of pull-up paths coupled in parallel between the output signal terminal and a power supply node for supplying a low power supply voltage, wherein each pull-up path includes a first pull-up transistor in series with a second pull-up transistor; a plurality of pull-down paths coupled in parallel between the output signal terminal and ground, wherein each pull-down path includes a first pull-down transistor in series with a second pull-down transistor; a controller configured to switch on the second pull-up transistors in a subset of the pull-up paths from the plurality of pull-up paths and to configure the first pull-up transistors in the subset of the pull-up paths to switch on in response to a first binary value of an input data signal, and wherein the controller is further configured to switch on the second pull-down transistors in a subset of the pull-down paths from the plurality of pull-down paths and to configure the first pull-down transistors in the subset of the pull-down paths to switch on in response to a second binary value of the input data signal, wherein each pull-up path's first pull-up transistor is a thin-oxide PMOS transistor having a source coupled to the power supply node, and wherein each pull-up path's second pull-up transistor is a thick-oxide NMOS transistor having a drain coupled to a drain for the pull-up path's PMOS transistor and a source coupled to the output signal terminal, wherein a gate oxide layer for each thick-oxide NMOS transistor is greater than a gate oxide layer for each thin-oxide PMOS transistor; and a plurality of first multiplexers and a plurality of second multiplexers both corresponding to the plurality of pull-up legs on a one-to-one basis, wherein each first multiplexer is configured to select between a high power supply voltage (VDDHV) and ground (VSSX) to drive a gate of the thick-oxide NMOS transistor in the corresponding pull-up leg, and wherein each second multiplexer is configured to select between the input data signal and the low power supply voltage (VDDIO) to drive a gate of the thin-oxide PMOS transistor in the corresponding pull-up leg, and wherein the high power supply voltage is greater than the low power supply voltage. an output signal terminal; a plurality of pull-up paths coupled in parallel between the output signal terminal and a power supply node for supplying a low power supply voltage, wherein each pull-up path includes a first pull-up transistor in series with a second pull-up transistor; a plurality of pull-down paths coupled in parallel between the output signal terminal and ground, wherein each pull-down path includes a first pull-down transistor in series with a second pull-down transistor; a controller configured to switch on the second pull-up transistors in a subset of the pull-up paths from the plurality of pull-up paths and to configure the first pull-up transistors in the subset of the pull-up paths to switch on in response to a first binary value of an input data signal, and wherein the controller is further configured to switch on the second pull-down transistors in a subset of the pull-down paths from the plurality of pull-down paths and to configure the first pull-down transistors in the subset of the pull-down paths to switch on in response to a second binary value of the input data signal, wherein each pull-up path's first pull-up transistor is a thin-oxide PMOS transistor having a source coupled to the power supply node, and wherein each pull-up path's second pull-up transistor is a thick-oxide NMOS transistor having a drain coupled to a drain for the pull-up path's PMOS transistor and a source coupled to the output signal terminal, wherein a gate oxide layer for each thick-oxide NMOS transistor is greater than a gate oxide layer for each thin-oxide PMOS transistor; and a plurality of first multiplexers and a plurality of second multiplexers both corresponding to the plurality of pull-up legs on a one-to-one basis, wherein each first multiplexer is configured to select between a high power supply voltage (VDDHV) and ground (VSSX) to drive a gate of the thick-oxide NMOS transistor in the corresponding pull-up leg, and wherein each second multiplexer is configured to select between the input data signal and the low power supply voltage (VDDIO) to drive a gate of the thin-oxide PMOS transistor in the corresponding pull-up leg, and wherein the high power supply voltage is greater than the low power supply voltage.