A class D amplifier output stage comprising a power transistor, an integrated high side gate driver structure for driving the power transistor, and a floating voltage regulator, the integrated high side gate driver structure comprising: a semiconductor substrate comprising a first polarity semiconductor material in which a first well diffusion (430, 426, DNW) is formed, the first polarity being a P polarity, the first well diffusion (426, 430, DNW) comprising a second polarity semiconductor material and having a peripheral outer wall abutted to the semiconductor substrate, the second polarity being an N polarity, a second well diffusion (427, 429) comprising first polarity semiconductor material arranged inside the first well diffusion (426, 430, DNW) such that an outer peripheral wall of the second well diffusion (427, 429) is abutted to an inner peripheral wall of the first well diffusion (426, 430, DNW) and a gate driver comprising a high side positive supply voltage port, a high side negative supply voltage port, a driver input and a driver output, wherein the gate driver comprises a transistor driver (401, 403) arranged in the second well diffusion (427, 429) such that a control terminal and an output terminal of the transistor driver (401, 403) are coupled to the driver input and driver output, respectively, a first electrical connection between the first well diffusion (426, 430, DNW) and the high side negative supply voltage port and a second electrical connection between the second well diffusion (427, 429) and the high side negative supply voltage port, the power transistor comprising a control terminal connected to the driver output of the gate driver, and the floating voltage regulator being arranged in the semiconductor substrate and comprising: a positive voltage input coupled to a high side DC voltage supply of the class D amplifier output stage, a regulated DC voltage output coupled to the high side positive supply voltage port of the gate driver, and a DC voltage reference generator (VREF) coupled between the high side negative supply voltage port of the gate driver and a reference voltage input of the floating voltage regulator. the integrated high side gate driver structure comprising: a semiconductor substrate comprising a first polarity semiconductor material in which a first well diffusion (430, 426, DNW) is formed, the first polarity being a P polarity, the first well diffusion (426, 430, DNW) comprising a second polarity semiconductor material and having a peripheral outer wall abutted to the semiconductor substrate, the second polarity being an N polarity, a second well diffusion (427, 429) comprising first polarity semiconductor material arranged inside the first well diffusion (426, 430, DNW) such that an outer peripheral wall of the second well diffusion (427, 429) is abutted to an inner peripheral wall of the first well diffusion (426, 430, DNW) and a gate driver comprising a high side positive supply voltage port, a high side negative supply voltage port, a driver input and a driver output, a semiconductor substrate comprising a first polarity semiconductor material in which a first well diffusion (430, 426, DNW) is formed, the first polarity being a P polarity, the first well diffusion (426, 430, DNW) comprising a second polarity semiconductor material and having a peripheral outer wall abutted to the semiconductor substrate, the second polarity being an N polarity, a second well diffusion (427, 429) comprising first polarity semiconductor material arranged inside the first well diffusion (426, 430, DNW) such that an outer peripheral wall of the second well diffusion (427, 429) is abutted to an inner peripheral wall of the first well diffusion (426, 430, DNW) and a gate driver comprising a high side positive supply voltage port, a high side negative supply voltage port, a driver input and a driver output, wherein the gate driver comprises a transistor driver (401, 403) arranged in the second well diffusion (427, 429) such that a control terminal and an output terminal of the transistor driver (401, 403) are coupled to the driver input and driver output, respectively, a first electrical connection between the first well diffusion (426, 430, DNW) and the high side negative supply voltage port and a second electrical connection between the second well diffusion (427, 429) and the high side negative supply voltage port, the power transistor comprising a control terminal connected to the driver output of the gate driver, and the floating voltage regulator being arranged in the semiconductor substrate and comprising: a positive voltage input coupled to a high side DC voltage supply of the class D amplifier output stage, a regulated DC voltage output coupled to the high side positive supply voltage port of the gate driver, and a DC voltage reference generator (VREF) coupled between the high side negative supply voltage port of the gate driver and a reference voltage input of the floating voltage regulator. a positive voltage input coupled to a high side DC voltage supply of the class D amplifier output stage, a regulated DC voltage output coupled to the high side positive supply voltage port of the gate driver, and a DC voltage reference generator (VREF) coupled between the high side negative supply voltage port of the gate driver and a reference voltage input of the floating voltage regulator.