A multicore architecture for railway safety-related applications, the architecture comprising: a data splitting device being configured to split data packets into safety-related data packets, which is all data which is categorized within one of safety integrity levels 1 to 4, and into the non-safety-related data packets, which is all data which either has no categorization or which belongs to safety integrity level 0, a logic device in form of a reconfigurable field programmable gate array (FPGA); the logic device including a first CPU and a second CPU; the first CPU being configured to process safety-related data packets; and the second CPU being configured to process non-safety-related data packets only, whereas an interprocessor communication device is provided for linking the first CPU to the second CPU, whereas the interprocessor communication device is implemented on the reconfigurable logic device itself and serves as a hardware firewall, whereas the interprocessor communication device is configured to grant access to the data of or on the second CPU, but it is configured to deny access to the data of or on the first CPU, such that the first CPU may access to the data on the second CPU, but not the other way round, and thereby blocking interference and/or disturbance of the processes running on the first CPU by the processes of the second CPU, characterized in that the first CPU comprises an encryption unit to process safety-related data packets, whereas the encryption unit is configured to include a safety layer into one or more processed safety-related data packets, whereas the safety layer adds a checksum and/or other information to the processed safety-related data packets enabling a host device to detect if a data packet is intact or not. a data splitting device being configured to split data packets into safety-related data packets, which is all data which is categorized within one of safety integrity levels 1 to 4, and into the non-safety-related data packets, which is all data which either has no categorization or which belongs to safety integrity level 0, a logic device in form of a reconfigurable field programmable gate array (FPGA); the logic device including a first CPU and a second CPU; the first CPU being configured to process safety-related data packets; and the second CPU being configured to process non-safety-related data packets only, whereas an interprocessor communication device is provided for linking the first CPU to the second CPU, whereas the interprocessor communication device is implemented on the reconfigurable logic device itself and serves as a hardware firewall, whereas the interprocessor communication device is configured to grant access to the data of or on the second CPU, but it is configured to deny access to the data of or on the first CPU, such that the first CPU may access to the data on the second CPU, but not the other way round, and thereby blocking interference and/or disturbance of the processes running on the first CPU by the processes of the second CPU, characterized in that the first CPU comprises an encryption unit to process safety-related data packets, whereas the encryption unit is configured to include a safety layer into one or more processed safety-related data packets, whereas the safety layer adds a checksum and/or other information to the processed safety-related data packets enabling a host device to detect if a data packet is intact or not.