A demodulation device, comprising: a plurality of demodulator chips (250 1, 250 2,...,250 M) configured to each demodulate a respective modulated input video data stream from a plurality of modulated input video data streams, wherein each of the demodulator chips includes a transport interface; multiplexed transport interface transmission circuitry, including a number of interconnect pins, configured to: receive demodulated video data generated by a variable number of the plurality of demodulator chips while maintaining a same number of multiplexed transport interface interconnect pins independent of a number of demodulator chips generating demodulated video data, multiplex the demodulated video data generated by the plurality of demodulator chips, and output the multiplexed demodulated video data as packets via a multiplexed transport interface including said number of interconnect pins to a video processing system-on-chip, SoC; wherein the demodulation device is configured to: generate timestamps based on a first timestamp counter in the demodulation device and timestamp packets communicated to said video processing SoC via the multiplexed transport interface with the generated timestamps; wherein the video processing SoC compares the received timestamps with values generated by a second timestamp counter at the video processing SoC; synchronize operations of the first with the second timestamp counter by way of at least one timestamp counter synchronization signal received from the video processing SoC. a plurality of demodulator chips (250 1, 250 2,...,250 M) configured to each demodulate a respective modulated input video data stream from a plurality of modulated input video data streams, wherein each of the demodulator chips includes a transport interface; multiplexed transport interface transmission circuitry, including a number of interconnect pins, configured to: receive demodulated video data generated by a variable number of the plurality of demodulator chips while maintaining a same number of multiplexed transport interface interconnect pins independent of a number of demodulator chips generating demodulated video data, multiplex the demodulated video data generated by the plurality of demodulator chips, and output the multiplexed demodulated video data as packets via a multiplexed transport interface including said number of interconnect pins to a video processing system-on-chip, SoC; wherein the demodulation device is configured to: generate timestamps based on a first timestamp counter in the demodulation device and timestamp packets communicated to said video processing SoC via the multiplexed transport interface with the generated timestamps; wherein the video processing SoC compares the received timestamps with values generated by a second timestamp counter at the video processing SoC; synchronize operations of the first with the second timestamp counter by way of at least one timestamp counter synchronization signal received from the video processing SoC. receive demodulated video data generated by a variable number of the plurality of demodulator chips while maintaining a same number of multiplexed transport interface interconnect pins independent of a number of demodulator chips generating demodulated video data, multiplex the demodulated video data generated by the plurality of demodulator chips, and output the multiplexed demodulated video data as packets via a multiplexed transport interface including said number of interconnect pins to a video processing system-on-chip, SoC; wherein the demodulation device is configured to: generate timestamps based on a first timestamp counter in the demodulation device and timestamp packets communicated to said video processing SoC via the multiplexed transport interface with the generated timestamps; wherein the video processing SoC compares the received timestamps with values generated by a second timestamp counter at the video processing SoC; synchronize operations of the first with the second timestamp counter by way of at least one timestamp counter synchronization signal received from the video processing SoC. generate timestamps based on a first timestamp counter in the demodulation device and timestamp packets communicated to said video processing SoC via the multiplexed transport interface with the generated timestamps; wherein the video processing SoC compares the received timestamps with values generated by a second timestamp counter at the video processing SoC; synchronize operations of the first with the second timestamp counter by way of at least one timestamp counter synchronization signal received from the video processing SoC.