A three-dimensional memory device (200, 300), comprising: a memory array structure (206-1, 206-2); and a staircase structure (204, 301, 400) in an intermediate of the memory array structure (206-1, 206-2) and laterally dividing the memory array structure (206-1, 206-2) into a first memory array structure and a second memory array structure, the staircase structure (204, 301, 400) comprising a first staircase zone and a bridge structure (306, 404) connecting the first memory array structure and the second memory array structure, wherein the first staircase zone comprises a plurality of pairs of staircases in a first lateral direction including a first pair of staircases (406-1, 406-2) facing each other in the first lateral direction and at different depths, a second pair of staircases (410-1, 410-2) facing each other in the first lateral direction and at different depths, and a third pair of staircases (416-1, 416-2) facing each other in the first lateral direction and at different depths, each staircase comprising a plurality of stairs; and at least one stair in the first pair of staircases (406-1, 406-2) is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure (306, 404), wherein the depth of a staircase is the depth of a bottom stair of the staircase in a z-direction, wherein a substrate of the 3D memory device (200, 300) extends laterally in a plane along the first and the second lateral direction (xy) wherein the z-direction is perpendicular to said plane, characterized in that each pair of staircases (406-1/406-2, 410-1/410-2, or 416-1/416-2) are not overlapped in the z-direction, wherein each staircase of the at least one pair of staircases (406-1/406-2, 410-1/410-2, or 416-1/416-2) comprises a plurality of divisions (408-1 to 408-4), in the second lateral direction (y), wherein a stair in one of the divisions is vertically between two stairs in another one of the divisions (408-1 to 408-4). a memory array structure (206-1, 206-2); and a staircase structure (204, 301, 400) in an intermediate of the memory array structure (206-1, 206-2) and laterally dividing the memory array structure (206-1, 206-2) into a first memory array structure and a second memory array structure, the staircase structure (204, 301, 400) comprising a first staircase zone and a bridge structure (306, 404) connecting the first memory array structure and the second memory array structure, wherein the first staircase zone comprises a plurality of pairs of staircases in a first lateral direction including a first pair of staircases (406-1, 406-2) facing each other in the first lateral direction and at different depths, a second pair of staircases (410-1, 410-2) facing each other in the first lateral direction and at different depths, and a third pair of staircases (416-1, 416-2) facing each other in the first lateral direction and at different depths, each staircase comprising a plurality of stairs; and at least one stair in the first pair of staircases (406-1, 406-2) is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure (306, 404), wherein the depth of a staircase is the depth of a bottom stair of the staircase in a z-direction, wherein a substrate of the 3D memory device (200, 300) extends laterally in a plane along the first and the second lateral direction (xy) wherein the z-direction is perpendicular to said plane, characterized in that each pair of staircases (406-1/406-2, 410-1/410-2, or 416-1/416-2) are not overlapped in the z-direction, wherein each staircase of the at least one pair of staircases (406-1/406-2, 410-1/410-2, or 416-1/416-2) comprises a plurality of divisions (408-1 to 408-4), in the second lateral direction (y), wherein a stair in one of the divisions is vertically between two stairs in another one of the divisions (408-1 to 408-4).