A hardware system comprising: a plurality of hardware blocks each comprising one or more hardware components; a hardware power controller configured to control a plurality of power domains of the hardware system, the plurality of power domains comprising power domains of the plurality of hardware blocks; and a hardware interface, wherein the hardware interface is a ring bus, communicatively coupled with each of the plurality of hardware blocks via a corresponding Input Output Socket and configured to: receive at least one message for a first hardware block of the plurality of hardware blocks; store the at least one message; in response to receiving the at least one message for the first hardware block, activate a power request from the hardware interface to the hardware power controller by asserting a corresponding logical signal, to thereby request that the power domain of the first hardware block be powered up; receive an indication from the first hardware block that the hardware block is ready to accept messages from the hardware interface; and provide the at least one message to the first hardware block in response to receiving the indication from the first hardware block that the first hardware block is ready to accept messages from the hardware interface; wherein each of the plurality of hardware blocks is configured to activate a message accept indicator to the hardware interface prior to receiving messages from the hardware interface. a plurality of hardware blocks each comprising one or more hardware components; a hardware power controller configured to control a plurality of power domains of the hardware system, the plurality of power domains comprising power domains of the plurality of hardware blocks; and a hardware interface, wherein the hardware interface is a ring bus, communicatively coupled with each of the plurality of hardware blocks via a corresponding Input Output Socket and configured to: receive at least one message for a first hardware block of the plurality of hardware blocks; store the at least one message; in response to receiving the at least one message for the first hardware block, activate a power request from the hardware interface to the hardware power controller by asserting a corresponding logical signal, to thereby request that the power domain of the first hardware block be powered up; receive an indication from the first hardware block that the hardware block is ready to accept messages from the hardware interface; and provide the at least one message to the first hardware block in response to receiving the indication from the first hardware block that the first hardware block is ready to accept messages from the hardware interface; receive at least one message for a first hardware block of the plurality of hardware blocks; store the at least one message; in response to receiving the at least one message for the first hardware block, activate a power request from the hardware interface to the hardware power controller by asserting a corresponding logical signal, to thereby request that the power domain of the first hardware block be powered up; receive an indication from the first hardware block that the hardware block is ready to accept messages from the hardware interface; and provide the at least one message to the first hardware block in response to receiving the indication from the first hardware block that the first hardware block is ready to accept messages from the hardware interface; wherein each of the plurality of hardware blocks is configured to activate a message accept indicator to the hardware interface prior to receiving messages from the hardware interface.