A chip package structure (10, 20), comprising: a chip package (100, 100') over a printed circuit board, wherein the chip package (100, 100') includes a substrate and one or more semiconductor dies (108; 108A, 108B; 208A, 208B) disposed over the substrate; a plurality of conductive elements (109A, 109B) formed between the substrate and the semiconductor dies (108; 108A, 108B; 208A, 208B); a first plurality of conductive pads formed at a first surface side of the substrate and electrically connected to the conductive elements (109A, 109B); a second plurality of conductive pads (106A, 106B) formed at a second surface side of the substrate, said second surface side opposite from said first surface side of the substrate; a plurality of conductive bumps (116, 212) between the chip package (100, 100') and the printed circuit board, wherein a conductive bump (116, 212) among said plurality of conductive bumps (116, 212) is bonded to a first conductive pad among said second plurality of conductive pads (106A, 106B); at least one thermal conductive element between the chip package (100, 100') and the printed circuit board, wherein the thermal conductive element is electrically connected to a second conductive pad among said second plurality of conductive pads (106A, 106B), and has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps (116, 212); a first bonding layer between the thermal conductive element and the chip package (100, 100'); and a second bonding layer between the thermal conductive element and the printed circuit board; wherein the first bonding layer and the second bonding layer are made of different solder materials; wherein the first bonding layer has a melting point higher than that of the second bonding layer. a chip package (100, 100') over a printed circuit board, wherein the chip package (100, 100') includes a substrate and one or more semiconductor dies (108; 108A, 108B; 208A, 208B) disposed over the substrate; a plurality of conductive elements (109A, 109B) formed between the substrate and the semiconductor dies (108; 108A, 108B; 208A, 208B); a first plurality of conductive pads formed at a first surface side of the substrate and electrically connected to the conductive elements (109A, 109B); a second plurality of conductive pads (106A, 106B) formed at a second surface side of the substrate, said second surface side opposite from said first surface side of the substrate; a plurality of conductive bumps (116, 212) between the chip package (100, 100') and the printed circuit board, wherein a conductive bump (116, 212) among said plurality of conductive bumps (116, 212) is bonded to a first conductive pad among said second plurality of conductive pads (106A, 106B); at least one thermal conductive element between the chip package (100, 100') and the printed circuit board, wherein the thermal conductive element is electrically connected to a second conductive pad among said second plurality of conductive pads (106A, 106B), and has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps (116, 212); a first bonding layer between the thermal conductive element and the chip package (100, 100'); and a second bonding layer between the thermal conductive element and the printed circuit board; wherein the first bonding layer and the second bonding layer are made of different solder materials; wherein the first bonding layer has a melting point higher than that of the second bonding layer.