A turn-off power semiconductor device comprising: a semiconductor wafer having a first main side and a second main side opposite to the first main side; a plurality of thyristor cells, each of the plurality of thyristor cells comprising in the order from the first main side to the second main side: (a) a cathode region (54a, 54b, 54c) of a first conductivity type; (b) a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region (54a, 54b, 54c) is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region (54a, 54b, 54c); (c) a drift layer of the first conductivity type forming a second p-n junction with the base layer; and (d) an anode layer of the second conductivity type separated from the base layer by the drift layer, wherein each thyristor cell further comprises: a gate electrode which is arranged lateral to the cathode region (54a, 54b, 54c) and forms an ohmic contact with the base layer; a cathode electrode (53a, 53b, 53c) arranged on the first main side and forming an ohmic contact with the cathode region (54a, 54b, 54c); and an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer, wherein interfaces between the cathode regions (54a, 54b, 54c) and the cathode electrodes (53a, 53b, 53c) and interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar, and wherein the base layer includes a gate well region extending from its contact with the gate electrode to a depth (d W) which is at least half of a depth (d C) of the cathode region (54a, 54b, 54c), characterized in that, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region (54a, 54b, 54c) and the gate well region at this depth and at a lateral positon, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 μm from the cathode region (54a, 54b, 54c), and the base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region (54a, 54b, 54c) and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4. a semiconductor wafer having a first main side and a second main side opposite to the first main side; a plurality of thyristor cells, each of the plurality of thyristor cells comprising in the order from the first main side to the second main side: (a) a cathode region (54a, 54b, 54c) of a first conductivity type; (b) a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region (54a, 54b, 54c) is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region (54a, 54b, 54c); (c) a drift layer of the first conductivity type forming a second p-n junction with the base layer; and (d) an anode layer of the second conductivity type separated from the base layer by the drift layer, (a) a cathode region (54a, 54b, 54c) of a first conductivity type; (b) a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region (54a, 54b, 54c) is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region (54a, 54b, 54c); (c) a drift layer of the first conductivity type forming a second p-n junction with the base layer; and (d) an anode layer of the second conductivity type separated from the base layer by the drift layer, wherein each thyristor cell further comprises: a gate electrode which is arranged lateral to the cathode region (54a, 54b, 54c) and forms an ohmic contact with the base layer; a cathode electrode (53a, 53b, 53c) arranged on the first main side and forming an ohmic contact with the cathode region (54a, 54b, 54c); and an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer, wherein interfaces between the cathode regions (54a, 54b, 54c) and the cathode electrodes (53a, 53b, 53c) and interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar, and wherein the base layer includes a gate well region extending from its contact with the gate electrode to a depth (d W) which is at least half of a depth (d C) of the cathode region (54a, 54b, 54c), characterized in that, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region (54a, 54b, 54c) and the gate well region at this depth and at a lateral positon, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 μm from the cathode region (54a, 54b, 54c), and the base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region (54a, 54b, 54c) and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.