A processor-implemented method for message based communication and failure recovery for FPGA middleware framework, the method comprising: receiving a plurality of Internet Protocol, IP, from a plurality of third party application as input to an active FPGA middleware framework, wherein the plurality of IP comprises a plurality of fragments and a sequence numbers corresponding to each of the plurality of fragments, wherein the plurality of fragments of the received plurality of IP comprises a Transmission Control Protocol, TCP or a User Datagram Protocol, UDP; re-assembling the received TCP and the received UDP, wherein the re-assembling is based on the sequence number of the plurality of fragments; checking the re-assembled UDP for a missing sequence of fragments and requesting a re-transmission of the missing sequence of re-assembled UDP over a TCP channel from a plurality of third party application; inserting the re-assembled UDP and the re-transmitted missing sequence of UDP to form a complete message with plurality of sequence numbers in the active FPGA middleware framework; transmitting the complete message with plurality of sequence numbers from the active FPGA middleware framework to a passive FPGA middleware framework for maintaining a real-time and dynamic synchronization of the received IP between the active FPGA middleware framework and passive FPGA middleware framework; detecting a failover of the active FPGA middleware framework based on transmission of a plurality of sequence numbers of the complete message to the passive FPGA middleware, wherein the step of detecting a failover of the active FPGA middleware framework further comprising: transmitting the complete message with plurality of sequence numbers from the active FPGA middleware framework to the passive FPGA middleware framework; receiving and saving the complete message with plurality of sequence numbers in the passive FPGA middleware framework for processing; transmitting a receipt from passive FPGA to active FPGA middleware framework, wherein the receipt comprises a saved previous consecutive sequence number of received complete message; detecting a failover of the active FPGA middleware framework based on comparison of the received sequence number with the saved previous consecutive sequence in the passive FPGA; and; recovering from the detected failover by activating the passive FPGA middleware framework after detecting a failure of the active FPGA middleware framework. receiving a plurality of Internet Protocol, IP, from a plurality of third party application as input to an active FPGA middleware framework, wherein the plurality of IP comprises a plurality of fragments and a sequence numbers corresponding to each of the plurality of fragments, wherein the plurality of fragments of the received plurality of IP comprises a Transmission Control Protocol, TCP or a User Datagram Protocol, UDP; re-assembling the received TCP and the received UDP, wherein the re-assembling is based on the sequence number of the plurality of fragments; checking the re-assembled UDP for a missing sequence of fragments and requesting a re-transmission of the missing sequence of re-assembled UDP over a TCP channel from a plurality of third party application; inserting the re-assembled UDP and the re-transmitted missing sequence of UDP to form a complete message with plurality of sequence numbers in the active FPGA middleware framework; transmitting the complete message with plurality of sequence numbers from the active FPGA middleware framework to a passive FPGA middleware framework for maintaining a real-time and dynamic synchronization of the received IP between the active FPGA middleware framework and passive FPGA middleware framework; transmitting the complete message with plurality of sequence numbers from the active FPGA middleware framework to the passive FPGA middleware framework; receiving and saving the complete message with plurality of sequence numbers in the passive FPGA middleware framework for processing; transmitting a receipt from passive FPGA to active FPGA middleware framework, wherein the receipt comprises a saved previous consecutive sequence number of received complete message; detecting a failover of the active FPGA middleware framework based on comparison of the received sequence number with the saved previous consecutive sequence in the passive FPGA; and; recovering from the detected failover by activating the passive FPGA middleware framework after detecting a failure of the active FPGA middleware framework.