A charge pump circuit, comprising: a first circuit (240, 250, and 260) powered by a first supply voltage and configured and arranged to adjust a voltage of an output (Vout) in response to first and second sets of control signals (220 and 222), the first circuit including a set of transistors having respective switching voltages, wherein the switching voltages of a transistor are defined as the actual voltages that must be applied to a gate of the transistor to turn it on and off; a control circuit powered by a second voltage (Vdrive) that is less than the first supply voltage (Vdd), the control circuit configured and arranged to generate the first set of control signals as a function of a voltage of a first command signal and generate the second set of control signals as a function of a voltage of a second command signal; and a voltage shifting circuit configured and arranged to bias voltages of the first and second sets of control signals relative to the switching voltages; wherein the first circuit includes:. first and second switching circuits, each configured and arranged to adjust voltage of a respective output nodes in response to first and second sets of control signals, wherein the output node of the first switching circuit is connected to the output; and a unit gain buffer configured and arranged to bias a voltage of the output node of the second switching circuit toward a voltage of the output node of the first switching circuit; wherein the circuit further comprises a compensation circuit configured and arranged to reduce power consumption of the unit gain buffer by injecting a compensation signal into the respective output node of the second switching circuit, the compensation signal having a current that is complementary to a current provided to the respective output node by the second switching circuit. a first circuit (240, 250, and 260) powered by a first supply voltage and configured and arranged to adjust a voltage of an output (Vout) in response to first and second sets of control signals (220 and 222), the first circuit including a set of transistors having respective switching voltages, wherein the switching voltages of a transistor are defined as the actual voltages that must be applied to a gate of the transistor to turn it on and off; a control circuit powered by a second voltage (Vdrive) that is less than the first supply voltage (Vdd), the control circuit configured and arranged to generate the first set of control signals as a function of a voltage of a first command signal and generate the second set of control signals as a function of a voltage of a second command signal; and a voltage shifting circuit configured and arranged to bias voltages of the first and second sets of control signals relative to the switching voltages; wherein the first circuit includes:. first and second switching circuits, each configured and arranged to adjust voltage of a respective output nodes in response to first and second sets of control signals, wherein the output node of the first switching circuit is connected to the output; and a unit gain buffer configured and arranged to bias a voltage of the output node of the second switching circuit toward a voltage of the output node of the first switching circuit; wherein the circuit further comprises a compensation circuit configured and arranged to reduce power consumption of the unit gain buffer by injecting a compensation signal into the respective output node of the second switching circuit, the compensation signal having a current that is complementary to a current provided to the respective output node by the second switching circuit. first and second switching circuits, each configured and arranged to adjust voltage of a respective output nodes in response to first and second sets of control signals, wherein the output node of the first switching circuit is connected to the output; and a unit gain buffer configured and arranged to bias a voltage of the output node of the second switching circuit toward a voltage of the output node of the first switching circuit; wherein the circuit further comprises a compensation circuit configured and arranged to reduce power consumption of the unit gain buffer by injecting a compensation signal into the respective output node of the second switching circuit, the compensation signal having a current that is complementary to a current provided to the respective output node by the second switching circuit.