An insulated gate bipolar transistor (IGBT) with a trench-type gate structure comprising: a channel region of a first-conductivity-type semiconductor; a first-conductivity-type emitter region arranged on a surface side of a semiconductor substrate and being in contact with the channel region, and being a first-conductivity-type semiconductor (P +) with higher concentration than that of the channel region; the channel region and the first-conductivity-type emitter region constitute a first-conductivity-type region; two gate electrodes arranged linearly in a vertically striped pattern on the surface side of the semiconductor substrate and penetrating the channel region, and insulated from the channel region and the first-conductivity-type emitter region; an emitter electrode being in contact with the channel region and with the first-conductivity-type emitter region; a second-conductivity-type emitter region disposed on the surface side of the semiconductor substrate discretely between adjoining gate electrodes and being insulated from the gate electrodes, the second-conductivity-type emitter region being a second-conductivity-type semiconductor (N +), the first-conductivity-type region and the second-conductivity-type emitter region form a unit which is repeated in the vertical direction on the surface side of the semiconductor substrate; and wherein the second-conductivity-type emitter regions are in contact with the channel region and the emitter electrode, and the gate electrodes, with a facing surface thereof, face in the horizontal direction the second-conductivity-type emitter regions, the channel region and a contact portion of those regions; a ratio X/W is between 1/10 and 1/2, wherein X denotes a vertical direction width of the second-conductivity-type emitter region in a direction parallel to said facing surface and parallel to the surface side of the semiconductor substrate, and W denotes a vertical direction width of the first-conductivity-type region in a direction parallel to said facing surface and parallel to the surface side of the semiconductor substrate; and said width X is 20 μm or less; and a width, in the horizontal direction perpendicular to said facing surface, of the first-conductivity-type emitter region is narrower than a width, in the horizontal direction perpendicular to said facing surface, where the emitter electrode is in contact with the channel region and with the first-conductivity-type emitter region. a channel region of a first-conductivity-type semiconductor; a first-conductivity-type emitter region arranged on a surface side of a semiconductor substrate and being in contact with the channel region, and being a first-conductivity-type semiconductor (P +) with higher concentration than that of the channel region; the channel region and the first-conductivity-type emitter region constitute a first-conductivity-type region; two gate electrodes arranged linearly in a vertically striped pattern on the surface side of the semiconductor substrate and penetrating the channel region, and insulated from the channel region and the first-conductivity-type emitter region; an emitter electrode being in contact with the channel region and with the first-conductivity-type emitter region; a second-conductivity-type emitter region disposed on the surface side of the semiconductor substrate discretely between adjoining gate electrodes and being insulated from the gate electrodes, the second-conductivity-type emitter region being a second-conductivity-type semiconductor (N +), the first-conductivity-type region and the second-conductivity-type emitter region form a unit which is repeated in the vertical direction on the surface side of the semiconductor substrate; and wherein the second-conductivity-type emitter regions are in contact with the channel region and the emitter electrode, and the gate electrodes, with a facing surface thereof, face in the horizontal direction the second-conductivity-type emitter regions, the channel region and a contact portion of those regions; a ratio X/W is between 1/10 and 1/2, wherein X denotes a vertical direction width of the second-conductivity-type emitter region in a direction parallel to said facing surface and parallel to the surface side of the semiconductor substrate, and W denotes a vertical direction width of the first-conductivity-type region in a direction parallel to said facing surface and parallel to the surface side of the semiconductor substrate; and said width X is 20 μm or less; and a width, in the horizontal direction perpendicular to said facing surface, of the first-conductivity-type emitter region is narrower than a width, in the horizontal direction perpendicular to said facing surface, where the emitter electrode is in contact with the channel region and with the first-conductivity-type emitter region.