A data communications receiver (102, 302, 502, 610) comprising: a receiver coil; a first amplification stage (110, 310, 510) coupled to the receiver coil, the first amplification circuitry to amplify a difference between a) at least part of a signal (104, 304, 316, 504, 516) received by the receiver coil and b) a threshold (336, 436, 536); a second amplification stage (112, 312, 512) coupled to receive and amplify the amplified difference (118, 318, 518) from the first amplification stage, the second amplification stage comprising a current mirror, and hysteretic level shifting circuitry (114, 314, 514) to shift a level of a) part of the signal received by the receiver coil, b) the threshold, or c) part of the signal received by the receiver coil and the threshold such that, in response to the at least part of the signal received by the receiver coil having crossed the threshold, a threshold crossing in the other direction is delayed, wherein the current mirror has an input coupled to receive the amplified difference from the first amplification stage, wherein the current mirror comprises a first MOSFET (328, 528) having a control terminal, a first of the source/drain coupled to the input of the current mirror, and a second of the source/drain coupled to a first reference potential, and a second MOSFET (329, 529) having a control terminal coupled to the input of the current mirror, a first of the source/drain coupled to the output of the current mirror, and a second of the source/drain coupled to a second reference potential (V SS), wherein, in operation, the control terminal of the first MOSFET is biased so that the first MOSFET remains in a conductive state. a receiver coil; a first amplification stage (110, 310, 510) coupled to the receiver coil, the first amplification circuitry to amplify a difference between a) at least part of a signal (104, 304, 316, 504, 516) received by the receiver coil and b) a threshold (336, 436, 536); a) at least part of a signal (104, 304, 316, 504, 516) received by the receiver coil and b) a threshold (336, 436, 536); a second amplification stage (112, 312, 512) coupled to receive and amplify the amplified difference (118, 318, 518) from the first amplification stage, the second amplification stage comprising a current mirror, and hysteretic level shifting circuitry (114, 314, 514) to shift a level of a) part of the signal received by the receiver coil, b) the threshold, or c) part of the signal received by the receiver coil and the threshold a) part of the signal received by the receiver coil, b) the threshold, or c) part of the signal received by the receiver coil and the threshold such that, in response to the at least part of the signal received by the receiver coil having crossed the threshold, a threshold crossing in the other direction is delayed, wherein the current mirror has an input coupled to receive the amplified difference from the first amplification stage, wherein the current mirror comprises a first MOSFET (328, 528) having a control terminal, a first of the source/drain coupled to the input of the current mirror, and a second of the source/drain coupled to a first reference potential, and a second MOSFET (329, 529) having a control terminal coupled to the input of the current mirror, a first of the source/drain coupled to the output of the current mirror, and a second of the source/drain coupled to a second reference potential (V SS), wherein, in operation, the control terminal of the first MOSFET is biased so that the first MOSFET remains in a conductive state. a first MOSFET (328, 528) having a control terminal, a first of the source/drain coupled to the input of the current mirror, and a second of the source/drain coupled to a first reference potential, and a control terminal, a first of the source/drain coupled to the input of the current mirror, and a second of the source/drain coupled to a first reference potential, and a second MOSFET (329, 529) having a control terminal coupled to the input of the current mirror, a first of the source/drain coupled to the output of the current mirror, and a second of the source/drain coupled to a second reference potential (V SS), a control terminal coupled to the input of the current mirror, a first of the source/drain coupled to the output of the current mirror, and a second of the source/drain coupled to a second reference potential (V SS), wherein, in operation, the control terminal of the first MOSFET is biased so that the first MOSFET remains in a conductive state.