A microprocessor that emulates the Advanced RISC Machines instruction set architecture, by emulating a plurality of ARM ISA processor modes, including a User mode, an FIQ exception mode, and a plurality of non-FIQ exception modes, and by emulating architectural registers associated with each of the plurality of processor modes, and by emulating an ARM ISA store multiple instruction that instructs the microprocessor to store data to memory from one or more of the architectural registers (502, 506) specified by the store multiple instruction, the microprocessor characterized by comprising: a direct storage, that holds data associated with a first portion of the emulated architectural registers (502, 506) of the current ARM ISA processor mode and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit; and an indirect storage, that holds data associated with a multiple of second portions of the emulated architectural registers, each second portion being associated with an ARM ISA processor mode, wherein if the current processor mode is the ARM ISA User mode then the direct storage holds data associated with the User mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA exception modes and the R8-R12 architectural registers of the ARM ISA FIQ mode; wherein if the current processor mode is the ARM ISA FIQ mode then the direct storage holds data associated with the FIQ mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-FIQ exception modes and the R8-R12 architectural registers of the ARM ISA mode previous to the current mode; and wherein if the current processor mode is an ARM ISA non-FIQ exception mode then the direct storage holds data associated with the non-FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-current exception mode and the R8-R12 architectural registers of the ARM ISA FIQ mode; and wherein in order to obtain access to the data in the indirect storage, the microprocessor loads data from the indirect storage to the direct storage and then stores the data to memory from the direct storage, and wherein for each of the architectural registers (502, 506) specified by the store multiple instruction, and according to the current processor mode, if the architectural register (502, 506) is in the first portion, the microprocessor stores data to memory from the direct storage; and if the architectural register (502, 506) is in the second portion, the microprocessor loads data from the indirect storage to the direct storage and then stores the data to memory from the direct storage. a direct storage, that holds data associated with a first portion of the emulated architectural registers (502, 506) of the current ARM ISA processor mode and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit; and an indirect storage, that holds data associated with a multiple of second portions of the emulated architectural registers, each second portion being associated with an ARM ISA processor mode, wherein if the current processor mode is the ARM ISA User mode then the direct storage holds data associated with the User mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA exception modes and the R8-R12 architectural registers of the ARM ISA FIQ mode; wherein if the current processor mode is the ARM ISA FIQ mode then the direct storage holds data associated with the FIQ mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-FIQ exception modes and the R8-R12 architectural registers of the ARM ISA mode previous to the current mode; and wherein if the current processor mode is an ARM ISA non-FIQ exception mode then the direct storage holds data associated with the non-FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-current exception mode and the R8-R12 architectural registers of the ARM ISA FIQ mode; and wherein in order to obtain access to the data in the indirect storage, the microprocessor loads data from the indirect storage to the direct storage and then stores the data to memory from the direct storage, and wherein for each of the architectural registers (502, 506) specified by the store multiple instruction, and according to the current processor mode, if the architectural register (502, 506) is in the first portion, the microprocessor stores data to memory from the direct storage; and if the architectural register (502, 506) is in the second portion, the microprocessor loads data from the indirect storage to the direct storage and then stores the data to memory from the direct storage. if the architectural register (502, 506) is in the first portion, the microprocessor stores data to memory from the direct storage; and if the architectural register (502, 506) is in the second portion, the microprocessor loads data from the indirect storage to the direct storage and then stores the data to memory from the direct storage.