A processor that is configured to, within the processor, load values from a vector of values into a series of subregisters (122, 124, 126) of a SIMD register: wherein values within the vector of values are contiguous; wherein each value in the vector of values is represented by a fixed number of bits; wherein the fixed number of bits used to represent every value in the vector of values is the same; wherein the processor is further configured to respond to one or more instructions by: based on the one or more instructions, subdividing the SIMD register into the series of subregisters (122, 124, 126); wherein each subregister (122, 124, 126) in the series of subregisters (122, 124, 126) holds a greater number of bits than the fixed number of bits; loading each subregister (122, 124, 126), of the series of subregisters (122, 124, 126), with a portion of the vector of values; wherein loading each subregister (122, 124, 126) includes loading the same portion of the vector of values into both a first subregister and a second subregister of the series of subregisters (122, 124, 126); wherein the portion of the vector of values that is loaded into both the first subregister and the second subregister includes both a first value and a second value; after said loading each subregister (122, 124, 126) with a portion of the vector of values, performing a plurality of subregister shifting operations; wherein the plurality of subregister shifting operations includes a first subregister shifting operation that shifts, by a first amount, the first subregister of the series of subregisters (122, 124, 126); wherein the plurality of subregister shifting operations includes a second subregister shifting operation that shifts, by a second amount, the second subregister of the series of subregisters (122, 124, 126); wherein the first amount is different than the second amount; and setting to zero all bits in the first subregister other than bits storing the first value; and setting to zero all bits in the second subregister other than bits storing the second value. wherein values within the vector of values are contiguous; wherein each value in the vector of values is represented by a fixed number of bits; wherein the fixed number of bits used to represent every value in the vector of values is the same; wherein the processor is further configured to respond to one or more instructions by: based on the one or more instructions, subdividing the SIMD register into the series of subregisters (122, 124, 126); wherein each subregister (122, 124, 126) in the series of subregisters (122, 124, 126) holds a greater number of bits than the fixed number of bits; loading each subregister (122, 124, 126), of the series of subregisters (122, 124, 126), with a portion of the vector of values; wherein loading each subregister (122, 124, 126) includes loading the same portion of the vector of values into both a first subregister and a second subregister of the series of subregisters (122, 124, 126); wherein the portion of the vector of values that is loaded into both the first subregister and the second subregister includes both a first value and a second value; after said loading each subregister (122, 124, 126) with a portion of the vector of values, performing a plurality of subregister shifting operations; wherein the plurality of subregister shifting operations includes a first subregister shifting operation that shifts, by a first amount, the first subregister of the series of subregisters (122, 124, 126); wherein the plurality of subregister shifting operations includes a second subregister shifting operation that shifts, by a second amount, the second subregister of the series of subregisters (122, 124, 126); wherein the first amount is different than the second amount; and setting to zero all bits in the first subregister other than bits storing the first value; and setting to zero all bits in the second subregister other than bits storing the second value. based on the one or more instructions, subdividing the SIMD register into the series of subregisters (122, 124, 126); wherein each subregister (122, 124, 126) in the series of subregisters (122, 124, 126) holds a greater number of bits than the fixed number of bits; loading each subregister (122, 124, 126), of the series of subregisters (122, 124, 126), with a portion of the vector of values; wherein loading each subregister (122, 124, 126) includes loading the same portion of the vector of values into both a first subregister and a second subregister of the series of subregisters (122, 124, 126); wherein the portion of the vector of values that is loaded into both the first subregister and the second subregister includes both a first value and a second value; after said loading each subregister (122, 124, 126) with a portion of the vector of values, performing a plurality of subregister shifting operations; wherein the plurality of subregister shifting operations includes a first subregister shifting operation that shifts, by a first amount, the first subregister of the series of subregisters (122, 124, 126); wherein the plurality of subregister shifting operations includes a second subregister shifting operation that shifts, by a second amount, the second subregister of the series of subregisters (122, 124, 126); wherein the first amount is different than the second amount; and setting to zero all bits in the first subregister other than bits storing the first value; and setting to zero all bits in the second subregister other than bits storing the second value.