An configurable processing block (310, 401), comprising: a sequencer circuit (320, 403) configured to provide a plurality of signals in a predetermined order; and an arithmetic block (310, 401) comprising: an output; a first input coupled to the sequencer circuit (320, 403), wherein the first input receives a first signal of the plurality of signals provided from the sequencer circuit (320, 403); second and third inputs that receive a second signal and third signal; a multiplier that has a first input port, a second input port and an output port, wherein the output port of the multiplier is coupled to the output; configuration circuitry (460, 463, 431, 432, 434, 435) adapted to configure the arithmetic block (310, 401) to implement a first arithmetic function by routing the first and second signals to the first and second input ports of the multiplier in a first mode, and to configure the arithmetic block (310, 401) to implement a second arithmetic function by routing the second and third signals to the first and second input ports of the multiplier in a second mode; and an adder that has a first input port, a second input port and an output port, wherein the first input port of the adder is coupled to the output port of the multiplier and the output port of the adder is coupled to the output; characterized in that the arithmetic block (310, 401) further comprises: a register coupled between the output port of the adder and the second input port of the adder, wherein the register and the adder are configured to collectively implement an accumulate function; a fourth input coupled to the sequencer circuit (320, 403), wherein the fourth input receives a control signal (ACCUM) from the sequencer circuit (320, 403) as a fourth signal; and a multiplexer coupled between the register and the second input port of the adder, wherein the multiplexer is configured to decouple the register from the second input port of the adder based on the fourth signal (ACCUM). a sequencer circuit (320, 403) configured to provide a plurality of signals in a predetermined order; and an arithmetic block (310, 401) comprising: an output; a first input coupled to the sequencer circuit (320, 403), wherein the first input receives a first signal of the plurality of signals provided from the sequencer circuit (320, 403); second and third inputs that receive a second signal and third signal; a multiplier that has a first input port, a second input port and an output port, wherein the output port of the multiplier is coupled to the output; configuration circuitry (460, 463, 431, 432, 434, 435) adapted to configure the arithmetic block (310, 401) to implement a first arithmetic function by routing the first and second signals to the first and second input ports of the multiplier in a first mode, and to configure the arithmetic block (310, 401) to implement a second arithmetic function by routing the second and third signals to the first and second input ports of the multiplier in a second mode; and an adder that has a first input port, a second input port and an output port, wherein the first input port of the adder is coupled to the output port of the multiplier and the output port of the adder is coupled to the output; an output; a first input coupled to the sequencer circuit (320, 403), wherein the first input receives a first signal of the plurality of signals provided from the sequencer circuit (320, 403); second and third inputs that receive a second signal and third signal; a multiplier that has a first input port, a second input port and an output port, wherein the output port of the multiplier is coupled to the output; configuration circuitry (460, 463, 431, 432, 434, 435) adapted to configure the arithmetic block (310, 401) to implement a first arithmetic function by routing the first and second signals to the first and second input ports of the multiplier in a first mode, and to configure the arithmetic block (310, 401) to implement a second arithmetic function by routing the second and third signals to the first and second input ports of the multiplier in a second mode; and an adder that has a first input port, a second input port and an output port, wherein the first input port of the adder is coupled to the output port of the multiplier and the output port of the adder is coupled to the output; characterized in that the arithmetic block (310, 401) further comprises: a register coupled between the output port of the adder and the second input port of the adder, wherein the register and the adder are configured to collectively implement an accumulate function; a fourth input coupled to the sequencer circuit (320, 403), wherein the fourth input receives a control signal (ACCUM) from the sequencer circuit (320, 403) as a fourth signal; and a multiplexer coupled between the register and the second input port of the adder, wherein the multiplexer is configured to decouple the register from the second input port of the adder based on the fourth signal (ACCUM). a register coupled between the output port of the adder and the second input port of the adder, wherein the register and the adder are configured to collectively implement an accumulate function; a fourth input coupled to the sequencer circuit (320, 403), wherein the fourth input receives a control signal (ACCUM) from the sequencer circuit (320, 403) as a fourth signal; and a multiplexer coupled between the register and the second input port of the adder, wherein the multiplexer is configured to decouple the register from the second input port of the adder based on the fourth signal (ACCUM).