A method of clock managing in a packet data network, PDN, implementing a time-transfer protocol, the network comprising a plurality of nodes (21-1 to 21-8, 202, 204) and a computer-based clock controller operatively connected to at least part of the nodes, the method comprising: obtaining, by the clock controller, topology data informative of a master clock node (12-8, 202) and a slave clock node (12-1, 12-3, 12-4, 12-7, 204) constituting end points of a communication path in the PDN and further informative of at least part of transit nodes of said communication path; characterized by periodically obtaining by the clock controller data informative of queue size and link rate characterizing, during a collection period, the at least part of transit nodes in master-slave, MS, and slave-master, SM, directions, thereby giving rise to queue-related data; for each collection period, using the obtained queue-related data to estimate, by the clock controller, queue-induced delay asymmetry of the communication path, wherein estimating the queue-induced delay asymmetry for a given collection period comprises: - for each node of the at least part of transit nodes, processing a plurality of samples informative of queue size and link rate at MS and/or SM directions and received during the collection period, thereby calculating a corresponding plurality of sample delays in MS and/or SM directions; - for each node of the at least part of transit nodes, selecting, among the plurality of sample delays calculated for a given direction, minimal sample delay values; - summarizing the minimal sample delay values over all nodes, of the at least part of transit nodes, located on the communication path in MS direction and summarizing the minimal sample delay values over all nodes, of the at least part of transit nodes, located on the communication path in SM direction; and - estimating the queue-induced delay asymmetry of the communication path as a half of the difference between the summaries of minimal sample delay values obtained in MS and SM directions; and sending by the clock controller the estimated value of queue-induced delay asymmetry to the slave node, the estimated value to be used by a clock residing on the slave node as delay asymmetry correction parameter. obtaining, by the clock controller, topology data informative of a master clock node (12-8, 202) and a slave clock node (12-1, 12-3, 12-4, 12-7, 204) constituting end points of a communication path in the PDN and further informative of at least part of transit nodes of said communication path; characterized by periodically obtaining by the clock controller data informative of queue size and link rate characterizing, during a collection period, the at least part of transit nodes in master-slave, MS, and slave-master, SM, directions, thereby giving rise to queue-related data; for each collection period, using the obtained queue-related data to estimate, by the clock controller, queue-induced delay asymmetry of the communication path, wherein estimating the queue-induced delay asymmetry for a given collection period comprises: - for each node of the at least part of transit nodes, processing a plurality of samples informative of queue size and link rate at MS and/or SM directions and received during the collection period, thereby calculating a corresponding plurality of sample delays in MS and/or SM directions; - for each node of the at least part of transit nodes, selecting, among the plurality of sample delays calculated for a given direction, minimal sample delay values; - summarizing the minimal sample delay values over all nodes, of the at least part of transit nodes, located on the communication path in MS direction and summarizing the minimal sample delay values over all nodes, of the at least part of transit nodes, located on the communication path in SM direction; and - estimating the queue-induced delay asymmetry of the communication path as a half of the difference between the summaries of minimal sample delay values obtained in MS and SM directions; and - for each node of the at least part of transit nodes, processing a plurality of samples informative of queue size and link rate at MS and/or SM directions and received during the collection period, thereby calculating a corresponding plurality of sample delays in MS and/or SM directions; - for each node of the at least part of transit nodes, selecting, among the plurality of sample delays calculated for a given direction, minimal sample delay values; - summarizing the minimal sample delay values over all nodes, of the at least part of transit nodes, located on the communication path in MS direction and summarizing the minimal sample delay values over all nodes, of the at least part of transit nodes, located on the communication path in SM direction; and - estimating the queue-induced delay asymmetry of the communication path as a half of the difference between the summaries of minimal sample delay values obtained in MS and SM directions; and sending by the clock controller the estimated value of queue-induced delay asymmetry to the slave node, the estimated value to be used by a clock residing on the slave node as delay asymmetry correction parameter.