A memory arrangement, comprising: a plurality of memory blocks; a first group of access ports, and a second group of access ports; characterized by further comprising routing circuitry coupling each pair of the first and second groups of access ports to a respective one of the plurality of memory blocks, each pair of the first and second groups of access ports including a first access port (Port 1A, 2A, 3A, 4A) from the first group of access ports and a second access port (Port 1 B, 2B, 3B, 4B) from the second group of access ports; and wherein: each first access port has write access to a first portion of the respective one of the plurality of memory blocks, has read access to a second portion of the respective one of the plurality of memory blocks, does not have read access to the first portion of the respective one of the plurality of memory blocks, and does not have write access to the second portion of the respective one of the plurality of memory blocks; and each second access port has write access to the second portion of the respective one of the plurality of memory blocks, has read access to the first portion of the respective one of the plurality of memory blocks, does not have read access to the second portion of the respective one of the plurality of memory blocks, and does not have write access to the first portion of the respective one of the plurality of memory blocks. a plurality of memory blocks; a first group of access ports, and a second group of access ports; characterized by further comprising routing circuitry coupling each pair of the first and second groups of access ports to a respective one of the plurality of memory blocks, each pair of the first and second groups of access ports including a first access port (Port 1A, 2A, 3A, 4A) from the first group of access ports and a second access port (Port 1 B, 2B, 3B, 4B) from the second group of access ports; and wherein: each first access port has write access to a first portion of the respective one of the plurality of memory blocks, has read access to a second portion of the respective one of the plurality of memory blocks, does not have read access to the first portion of the respective one of the plurality of memory blocks, and does not have write access to the second portion of the respective one of the plurality of memory blocks; and each second access port has write access to the second portion of the respective one of the plurality of memory blocks, has read access to the first portion of the respective one of the plurality of memory blocks, does not have read access to the second portion of the respective one of the plurality of memory blocks, and does not have write access to the first portion of the respective one of the plurality of memory blocks. each first access port has write access to a first portion of the respective one of the plurality of memory blocks, has read access to a second portion of the respective one of the plurality of memory blocks, does not have read access to the first portion of the respective one of the plurality of memory blocks, and does not have write access to the second portion of the respective one of the plurality of memory blocks; and each second access port has write access to the second portion of the respective one of the plurality of memory blocks, has read access to the first portion of the respective one of the plurality of memory blocks, does not have read access to the second portion of the respective one of the plurality of memory blocks, and does not have write access to the first portion of the respective one of the plurality of memory blocks.