A method for programming in a 3D NAND flash stacked non-volatile memory device, comprising: driving a voltage (Vch_uninhibited) of a channel of an uninhibited NAND string, the uninhibited NAND string is selected for programming and comprises a selected non-volatile storage element which is selected for programming and a plurality of unselected non-volatile storage elements (M03, M02, M01, M00, M10, M11, M12) which are not selected for programming; during the driving, floating a voltage (Vch_inhibited) of a channel (CH, CHd, CHi, CHs) of an inhibited NAND string (NSOA) by providing a drain-side select gate (SGDOA) and a source-side select gate (SGSOA) of the inhibited NAND string in a non-conductive state, the inhibited NAND string comprises a non-volatile storage element (M13A) which is connected to the selected non-volatile storage element via a selected word line (WL_sel, 830), and a plurality of non-volatile storage elements (M03A, M02A, M01A, M00A, M10A, M11A, M12A) which are connected to the plurality of unselected non-volatile storage elements via unselected word lines (WL_unsel, 822, 824, 826, 828, 836, 834, 832); characterized by comprising: during the floating, increasing the voltage of the channel of the inhibited NAND string to a pre-charge level (Vpre-charge) using gate-induced drain leakage from the drain-side select gate and from the pre-charge level to a program inhibit level using capacitive coupling; while the voltage of the channel of the inhibited NAND string is at the program inhibit level, increasing a voltage of the selected word line to a programming level (Vpgm) and maintaining the voltage of the selected word line at the programming level; wherein the capacitive coupling is achieved by increasing a voltage (WL_unsel) on the unselected word lines from an initial level (0 V) to a pass voltage level (Vpass) which is less than the programming level, and the gate-induced drain leakage is achieved by providing a drain-to-gate voltage of the drain-side select gate at a level (Vbl_high-Vsgd) which is above a threshold level, the threshold level for generation of electron-holes pairs from gate-induced drain leakage. driving a voltage (Vch_uninhibited) of a channel of an uninhibited NAND string, the uninhibited NAND string is selected for programming and comprises a selected non-volatile storage element which is selected for programming and a plurality of unselected non-volatile storage elements (M03, M02, M01, M00, M10, M11, M12) which are not selected for programming; during the driving, floating a voltage (Vch_inhibited) of a channel (CH, CHd, CHi, CHs) of an inhibited NAND string (NSOA) by providing a drain-side select gate (SGDOA) and a source-side select gate (SGSOA) of the inhibited NAND string in a non-conductive state, the inhibited NAND string comprises a non-volatile storage element (M13A) which is connected to the selected non-volatile storage element via a selected word line (WL_sel, 830), and a plurality of non-volatile storage elements (M03A, M02A, M01A, M00A, M10A, M11A, M12A) which are connected to the plurality of unselected non-volatile storage elements via unselected word lines (WL_unsel, 822, 824, 826, 828, 836, 834, 832); characterized by comprising: during the floating, increasing the voltage of the channel of the inhibited NAND string to a pre-charge level (Vpre-charge) using gate-induced drain leakage from the drain-side select gate and from the pre-charge level to a program inhibit level using capacitive coupling; while the voltage of the channel of the inhibited NAND string is at the program inhibit level, increasing a voltage of the selected word line to a programming level (Vpgm) and maintaining the voltage of the selected word line at the programming level; wherein the capacitive coupling is achieved by increasing a voltage (WL_unsel) on the unselected word lines from an initial level (0 V) to a pass voltage level (Vpass) which is less than the programming level, and the gate-induced drain leakage is achieved by providing a drain-to-gate voltage of the drain-side select gate at a level (Vbl_high-Vsgd) which is above a threshold level, the threshold level for generation of electron-holes pairs from gate-induced drain leakage. during the floating, increasing the voltage of the channel of the inhibited NAND string to a pre-charge level (Vpre-charge) using gate-induced drain leakage from the drain-side select gate and from the pre-charge level to a program inhibit level using capacitive coupling; while the voltage of the channel of the inhibited NAND string is at the program inhibit level, increasing a voltage of the selected word line to a programming level (Vpgm) and maintaining the voltage of the selected word line at the programming level; wherein the capacitive coupling is achieved by increasing a voltage (WL_unsel) on the unselected word lines from an initial level (0 V) to a pass voltage level (Vpass) which is less than the programming level, and the gate-induced drain leakage is achieved by providing a drain-to-gate voltage of the drain-side select gate at a level (Vbl_high-Vsgd) which is above a threshold level, the threshold level for generation of electron-holes pairs from gate-induced drain leakage.