A semiconductor device having a semiconductor island isolated by two first shallow trench isolations on two opposite sides of the semiconductor island extending along a first direction and two second shallow trench isolations on two other opposite sides of the semiconductor island extending along a second direction, wherein the first shallow trench isolations intersect the second shallow trench isolations; a gate trench extending along the second direction and recessed into the semiconductor island; a gate extending along the second direction and disposed at the gate trench; a first dielectric layer(28, 32, 66) encapsulating the gate in the gate;trench; a first source/drain regions disposed along the second direction at a first side of the gate trench and disposed with respect to a top surface of the semiconductor island; a second dielectric layer (14,114) embedded in the semiconductor island and disposed between the first source/drain regions; a first U-shaped channel region disposed around the second dielectric layer (14,114) and between the first source/drain regions; a second source/drain regions disposed along the second direction at a second side of the gate trench which is different from and directly opposite to the first side and disposed with respect to the top surface of the semiconductor island; a third dielectric layer (14, 214) embedded in the semiconductor island and between the second source/drain regions; a second U-shaped channel region disposed around the third dielectric layer (14, 214) and between the second source/drain regions; characterized by first conductive layers, each disposed on a respective one of said first source/drain regions, in the gate trench and on the first dielectric layer (28, 32, 66) and second conductive layers each disposed on a respective one of said second source/drain regions, in the gate trench and on the first dielectric layer (28, 32, 66); a source line coupling a first source of the first source/drain regions to a second source of the second source/drain regions via said respective first and second conductive layers (46, 48) and a drain contact coupling a first drain of the first source/drain regions to a second drain of the second source/ drain regions via said respective first and second conductive layers (46, 48) so as to provide a dual-channel single-gate transistor. a semiconductor island isolated by two first shallow trench isolations on two opposite sides of the semiconductor island extending along a first direction and two second shallow trench isolations on two other opposite sides of the semiconductor island extending along a second direction, wherein the first shallow trench isolations intersect the second shallow trench isolations; a gate trench extending along the second direction and recessed into the semiconductor island; a gate extending along the second direction and disposed at the gate trench; a first dielectric layer(28, 32, 66) encapsulating the gate in the gate;trench; a first source/drain regions disposed along the second direction at a first side of the gate trench and disposed with respect to a top surface of the semiconductor island; a second dielectric layer (14,114) embedded in the semiconductor island and disposed between the first source/drain regions; a first U-shaped channel region disposed around the second dielectric layer (14,114) and between the first source/drain regions; a second source/drain regions disposed along the second direction at a second side of the gate trench which is different from and directly opposite to the first side and disposed with respect to the top surface of the semiconductor island; a third dielectric layer (14, 214) embedded in the semiconductor island and between the second source/drain regions; a second U-shaped channel region disposed around the third dielectric layer (14, 214) and between the second source/drain regions; characterized by first conductive layers, each disposed on a respective one of said first source/drain regions, in the gate trench and on the first dielectric layer (28, 32, 66) and second conductive layers each disposed on a respective one of said second source/drain regions, in the gate trench and on the first dielectric layer (28, 32, 66); a source line coupling a first source of the first source/drain regions to a second source of the second source/drain regions via said respective first and second conductive layers (46, 48) and a drain contact coupling a first drain of the first source/drain regions to a second drain of the second source/ drain regions via said respective first and second conductive layers (46, 48) so as to provide a dual-channel single-gate transistor.