An integrated circuit in a ring transmission system in which a plurality of integrated circuits are connected as a ring through serial links, comprising: a link controller for performing transmission, reception, and relay processing on a packet that includes destination information; and a PHY for switching a communication mode of operation between (i) a normal mode of performing interconversion between serial data input and output via the serial links and parallel data handled by the link controller, and (ii) a loopback mode of looping back the serial data input via an earlier serial link, before handover to the link controller, for output to a later serial link, wherein the link controller includes: a symbol generator for making an idle frame transmission instruction for maintaining symbol lock to the PHY during a pregap between a transmission request packet and a data packet; and a loopback controller for making a transition instruction from the normal mode to the loopback mode to the PHY during the pregap and after the relay processing is performed in the normal mode on a transmission request packet addressed to another integrated circuit in order to cause a data packet addressed to the other integrated circuit to be looped back for output, during the normal mode, the PHY is adapted to output an idle frame to the later serial link in accordance with the transmission instruction from the symbol generator, the PHY is adapted to transition from the normal mode to the loopback mode in accordance with the transition instruction with timing such that symbol lock is maintained between (i) the idle frame output to the later serial link in accordance with the transmission instruction during the normal mode, and (ii) an idle frame input from an earlier integrated circuit looped back for output to the later serial link during the loopback mode, and during the loopback mode, the PHY is adapted to loop back the idle frame from the earlier integrated circuit for output to the later serial link, and to perform the relay processing on the data packet addressed to the other integrated circuit. a link controller for performing transmission, reception, and relay processing on a packet that includes destination information; and a PHY for switching a communication mode of operation between (i) a normal mode of performing interconversion between serial data input and output via the serial links and parallel data handled by the link controller, and (ii) a loopback mode of looping back the serial data input via an earlier serial link, before handover to the link controller, for output to a later serial link, wherein the link controller includes: a symbol generator for making an idle frame transmission instruction for maintaining symbol lock to the PHY during a pregap between a transmission request packet and a data packet; and a loopback controller for making a transition instruction from the normal mode to the loopback mode to the PHY during the pregap and after the relay processing is performed in the normal mode on a transmission request packet addressed to another integrated circuit in order to cause a data packet addressed to the other integrated circuit to be looped back for output, during the normal mode, the PHY is adapted to output an idle frame to the later serial link in accordance with the transmission instruction from the symbol generator, the PHY is adapted to transition from the normal mode to the loopback mode in accordance with the transition instruction with timing such that symbol lock is maintained between (i) the idle frame output to the later serial link in accordance with the transmission instruction during the normal mode, and (ii) an idle frame input from an earlier integrated circuit looped back for output to the later serial link during the loopback mode, and during the loopback mode, the PHY is adapted to loop back the idle frame from the earlier integrated circuit for output to the later serial link, and to perform the relay processing on the data packet addressed to the other integrated circuit. a symbol generator for making an idle frame transmission instruction for maintaining symbol lock to the PHY during a pregap between a transmission request packet and a data packet; and a loopback controller for making a transition instruction from the normal mode to the loopback mode to the PHY during the pregap and after the relay processing is performed in the normal mode on a transmission request packet addressed to another integrated circuit in order to cause a data packet addressed to the other integrated circuit to be looped back for output, during the normal mode, the PHY is adapted to output an idle frame to the later serial link in accordance with the transmission instruction from the symbol generator, the PHY is adapted to transition from the normal mode to the loopback mode in accordance with the transition instruction with timing such that symbol lock is maintained between (i) the idle frame output to the later serial link in accordance with the transmission instruction during the normal mode, and (ii) an idle frame input from an earlier integrated circuit looped back for output to the later serial link during the loopback mode, and during the loopback mode, the PHY is adapted to loop back the idle frame from the earlier integrated circuit for output to the later serial link, and to perform the relay processing on the data packet addressed to the other integrated circuit.