A printed circuit board comprising: an insulating layer; a plating seed layer on the insulating layer; a circuit pattern on the plating seed layer; and a surface treatment layer on the circuit pattern, wherein the surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern, wherein the bottom surface of the surface treatment layer comprises: a first portion contacted with the top surface of the circuit pattern, and a second portion spaced apart from the insulating layer, the plating seed layer and the circuit pattern by a predetermined distance, wherein the width of the top surface of the circuit pattern is narrower than a width of a bottom surface of the circuit pattern, the bottom surface of the circuit pattern comprises a first area vertically overlapped with the top surface of the circuit pattern and a second area except for the first area, wherein the second area of the circuit pattern comprises a third area that is not vertically overlapped with the second portion of the surface treatment layer and a fourth area vertically overlapped with the second portion of the surface treatment layer, and wherein the third area has a width wider than a width of the fourth area, wherein the plating seed layer serves as a seed layer for the circuit pattern and the surface treatment layer, wherein each of the plating seed layer and the circuit pattern is formed of metal including copper, Cu, and having electrical conductivity, wherein the surface treatment layer is formed of metal including gold, Au, or an alloy including Au. an insulating layer; a plating seed layer on the insulating layer; a circuit pattern on the plating seed layer; and a surface treatment layer on the circuit pattern, wherein the surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern, wherein the bottom surface of the surface treatment layer comprises: a first portion contacted with the top surface of the circuit pattern, and a second portion spaced apart from the insulating layer, the plating seed layer and the circuit pattern by a predetermined distance, wherein the width of the top surface of the circuit pattern is narrower than a width of a bottom surface of the circuit pattern, the bottom surface of the circuit pattern comprises a first area vertically overlapped with the top surface of the circuit pattern and a second area except for the first area, wherein the second area of the circuit pattern comprises a third area that is not vertically overlapped with the second portion of the surface treatment layer and a fourth area vertically overlapped with the second portion of the surface treatment layer, and wherein the third area has a width wider than a width of the fourth area, wherein the plating seed layer serves as a seed layer for the circuit pattern and the surface treatment layer, wherein each of the plating seed layer and the circuit pattern is formed of metal including copper, Cu, and having electrical conductivity, wherein the surface treatment layer is formed of metal including gold, Au, or an alloy including Au. a first portion contacted with the top surface of the circuit pattern, and a second portion spaced apart from the insulating layer, the plating seed layer and the circuit pattern by a predetermined distance, wherein the width of the top surface of the circuit pattern is narrower than a width of a bottom surface of the circuit pattern, the bottom surface of the circuit pattern comprises a first area vertically overlapped with the top surface of the circuit pattern and a second area except for the first area, wherein the second area of the circuit pattern comprises a third area that is not vertically overlapped with the second portion of the surface treatment layer and a fourth area vertically overlapped with the second portion of the surface treatment layer, and wherein the third area has a width wider than a width of the fourth area, wherein the plating seed layer serves as a seed layer for the circuit pattern and the surface treatment layer, wherein each of the plating seed layer and the circuit pattern is formed of metal including copper, Cu, and having electrical conductivity, wherein the surface treatment layer is formed of metal including gold, Au, or an alloy including Au.