A semiconductor package comprising: a top-drain vertical FET in a first active die, a source of said top-drain vertical FET situated on a source side of said first active die and a drain and a gate of said top-drain vertical FET situated on a drain side of said first active die; a bottom-drain vertical FET in a second active die, a source and a gate of said bottom-drain vertical FET situated on a source side of said second active die and a drain of said bottom-drain vertical FET situated on a drain side of said second active die; a conductive carrier attached to said source side of said first active die and to said drain side of said second active die; said conductive carrier coupling said source of said top-drain vertical FET to said drain of said bottom-drain vertical FET on a top surface of said conductive carrier, and providing a switch node contact extending through a patterned dielectric layer on said top surface of said conductive carrier, wherein said patterned dielectric layer comprises windows exposing a top surface of said conductive carrier adjacent one of the first active die and said second active die, said source and said gate on said source side of said second active die, said drain and said gate on said drain side of said first active die, a patterned conductive layer forming a source contact and a gate contact on said source side of said second active die, a drain contact and a gate contact on said drain side of said first active die, and said switch node, and a patterned insulator layer on the patterned dielectric layer, the patterned insulator layer having a surface and exposing said source contact and said gate contact on said source side of said second active die, said drain contact and said gate contact on said drain side of said first active die, and said switch node accessible through said surface. a top-drain vertical FET in a first active die, a source of said top-drain vertical FET situated on a source side of said first active die and a drain and a gate of said top-drain vertical FET situated on a drain side of said first active die; a bottom-drain vertical FET in a second active die, a source and a gate of said bottom-drain vertical FET situated on a source side of said second active die and a drain of said bottom-drain vertical FET situated on a drain side of said second active die; a conductive carrier attached to said source side of said first active die and to said drain side of said second active die; said conductive carrier coupling said source of said top-drain vertical FET to said drain of said bottom-drain vertical FET on a top surface of said conductive carrier, and providing a switch node contact extending through a patterned dielectric layer on said top surface of said conductive carrier, wherein said patterned dielectric layer comprises windows exposing a top surface of said conductive carrier adjacent one of the first active die and said second active die, said source and said gate on said source side of said second active die, said drain and said gate on said drain side of said first active die, a patterned conductive layer forming a source contact and a gate contact on said source side of said second active die, a drain contact and a gate contact on said drain side of said first active die, and said switch node, and a patterned insulator layer on the patterned dielectric layer, the patterned insulator layer having a surface and exposing said source contact and said gate contact on said source side of said second active die, said drain contact and said gate contact on said drain side of said first active die, and said switch node accessible through said surface.