A system for a functional timing sensor, comprising: a setup time violation detecting circuit (111; 600); a hold time violation detecting circuit (112; 700; 800; 1100); and an interface from the setup time violation detecting circuit and the hold time violation detecting circuit, the interface providing a notification upon detection of a violation by either the setup time violation detecting circuit or the hold time violation detecting circuit;. wherein the setup time violation detecting circuit further comprises: a data launching device; a state based device; a delay device operatively intermediate the data launching device and the state based device, the delay device configured to cause the state based device to output a delayed data signal relative to an undelayed data signal output by the data launching device; and a digital comparator logic device configured to indicate a setup time violation if the delayed data signal from the state based device violates a condition of comparison to the undelayed data signal from the data launching device; wherein the data launching device, the state based device, the delay device, and the digital comparator logic device comprise a first branch of a setup time violation detecting circuit, and wherein a complementary second branch of the setup time violation detecting circuit receives the undelayed data signal output from the data launching device, the complementary second branch being functionally identical to the first branch, such that the setup time violation detecting circuit tests both rise time delays and fall time delays concurrently. a setup time violation detecting circuit (111; 600); a hold time violation detecting circuit (112; 700; 800; 1100); and an interface from the setup time violation detecting circuit and the hold time violation detecting circuit, the interface providing a notification upon detection of a violation by either the setup time violation detecting circuit or the hold time violation detecting circuit;. wherein the setup time violation detecting circuit further comprises: a data launching device; a state based device; a delay device operatively intermediate the data launching device and the state based device, the delay device configured to cause the state based device to output a delayed data signal relative to an undelayed data signal output by the data launching device; and a digital comparator logic device configured to indicate a setup time violation if the delayed data signal from the state based device violates a condition of comparison to the undelayed data signal from the data launching device; a data launching device; a state based device; a delay device operatively intermediate the data launching device and the state based device, the delay device configured to cause the state based device to output a delayed data signal relative to an undelayed data signal output by the data launching device; and a digital comparator logic device configured to indicate a setup time violation if the delayed data signal from the state based device violates a condition of comparison to the undelayed data signal from the data launching device; wherein the data launching device, the state based device, the delay device, and the digital comparator logic device comprise a first branch of a setup time violation detecting circuit, and wherein a complementary second branch of the setup time violation detecting circuit receives the undelayed data signal output from the data launching device, the complementary second branch being functionally identical to the first branch, such that the setup time violation detecting circuit tests both rise time delays and fall time delays concurrently.