A circuit, comprising: a first transistor; a current source for driving a drain of the first transistor with a bias current; a first decoupling capacitor for isolating a direct current, DC, drain voltage of the first transistor from a DC gate voltage of the first transistor, wherein a gate of the first transistor is configured to be driven by an AC input voltage from a crystal through the first decoupling capacitor; an operational amplifier configured to further bias the gate of the first transistor to regulate the DC drain voltage of the first transistor; a voltage divider having a first resistor having a first terminal connected to the drain of the first transistor and having a second terminal connected to a first terminal of a second resistor, wherein the operational amplifier has a first input connected to the second terminal of the first resistor and has a second input connected to a reference voltage node for carrying a reference voltage, wherein a second terminal of the voltage divider is coupled to a terminal of the first decoupling capacitor; the circuit being characterized in that it further comprises a third inverter comprising a reference PMOS transistor having a source connected to a power supply node for supplying a power supply voltage, a reference NMOS transistor having a source connected to ground and having a drain connected to a drain for the reference PMOS transistor, and a reference resistor (RREF) connected between the drain of the reference NMOS transistor and the reference voltage node for supplying the reference voltage, wherein the reference voltage node is connected to a gate of the reference PMOS transistor and to a gate of the reference NMOS transistor; a first inverter configured to invert a voltage of the terminal of the first decoupling capacitor; and a second inverter configured to invert an output signal of the first inverter to provide an output voltage (Out) for the circuit, wherein the PMOS and NMOS transistors in the third inverter are matched to respective transistors in the first inverter and second inverter each being formed by an analogous serial stack of a PMOS transistor and an NMOS transistor. a first transistor; a current source for driving a drain of the first transistor with a bias current; a first decoupling capacitor for isolating a direct current, DC, drain voltage of the first transistor from a DC gate voltage of the first transistor, wherein a gate of the first transistor is configured to be driven by an AC input voltage from a crystal through the first decoupling capacitor; an operational amplifier configured to further bias the gate of the first transistor to regulate the DC drain voltage of the first transistor; a voltage divider having a first resistor having a first terminal connected to the drain of the first transistor and having a second terminal connected to a first terminal of a second resistor, wherein the operational amplifier has a first input connected to the second terminal of the first resistor and has a second input connected to a reference voltage node for carrying a reference voltage, wherein a second terminal of the voltage divider is coupled to a terminal of the first decoupling capacitor; the circuit being characterized in that it further comprises a third inverter comprising a reference PMOS transistor having a source connected to a power supply node for supplying a power supply voltage, a reference NMOS transistor having a source connected to ground and having a drain connected to a drain for the reference PMOS transistor, and a reference resistor (RREF) connected between the drain of the reference NMOS transistor and the reference voltage node for supplying the reference voltage, wherein the reference voltage node is connected to a gate of the reference PMOS transistor and to a gate of the reference NMOS transistor; a first inverter configured to invert a voltage of the terminal of the first decoupling capacitor; and a second inverter configured to invert an output signal of the first inverter to provide an output voltage (Out) for the circuit, wherein the PMOS and NMOS transistors in the third inverter are matched to respective transistors in the first inverter and second inverter each being formed by an analogous serial stack of a PMOS transistor and an NMOS transistor.