A memory device comprising: a dynamic random-access memory, DRAM, including a plurality of stacked memory dies, each memory die including a plurality of memory arrays, each memory array including peripheral logic circuits and a configurable logic, wherein the peripheral logic circuits of a memory array in a memory die may be shared with one or more other memory dies of the plurality of memory dies; and a system element coupled with the DRAM, the system element including a memory controller; wherein the memory controller is to control the configurable logic (510, 560) of the memory arrays to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O, input/output, connections between the memory arrays (510, 552); wherein the memory controller is to establish a first mode by: setting the configuration logic for a first array on a first die and a second array on a second die to provide that the peripheral logic circuits operate as separate peripheral logic circuits for each of the memory arrays; and setting the peripheral logic to provide for disabling I/O connections between the first array on the first die and the second array on the second die; wherein the memory controller is to establish a second mode by: setting the configuration logic for the first array on the first die and the second array on the second die to enable the peripheral logic circuits of the first array on the first die operate as shared peripheral logic circuits for the first array on the first die and the second array on the second die and to disable the peripheral logic circuits of the second array on the second die; and setting the peripheral logic to provide for enabling I/O connections between the first array on the first die and the second array on the second die. a dynamic random-access memory, DRAM, including a plurality of stacked memory dies, each memory die including a plurality of memory arrays, each memory array including peripheral logic circuits and a configurable logic, wherein the peripheral logic circuits of a memory array in a memory die may be shared with one or more other memory dies of the plurality of memory dies; and a system element coupled with the DRAM, the system element including a memory controller; wherein the memory controller is to control the configurable logic (510, 560) of the memory arrays to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O, input/output, connections between the memory arrays (510, 552); wherein the memory controller is to establish a first mode by: setting the configuration logic for a first array on a first die and a second array on a second die to provide that the peripheral logic circuits operate as separate peripheral logic circuits for each of the memory arrays; and setting the peripheral logic to provide for disabling I/O connections between the first array on the first die and the second array on the second die; setting the configuration logic for a first array on a first die and a second array on a second die to provide that the peripheral logic circuits operate as separate peripheral logic circuits for each of the memory arrays; and setting the peripheral logic to provide for disabling I/O connections between the first array on the first die and the second array on the second die; wherein the memory controller is to establish a second mode by: setting the configuration logic for the first array on the first die and the second array on the second die to enable the peripheral logic circuits of the first array on the first die operate as shared peripheral logic circuits for the first array on the first die and the second array on the second die and to disable the peripheral logic circuits of the second array on the second die; and setting the peripheral logic to provide for enabling I/O connections between the first array on the first die and the second array on the second die. setting the configuration logic for the first array on the first die and the second array on the second die to enable the peripheral logic circuits of the first array on the first die operate as shared peripheral logic circuits for the first array on the first die and the second array on the second die and to disable the peripheral logic circuits of the second array on the second die; and setting the peripheral logic to provide for enabling I/O connections between the first array on the first die and the second array on the second die.