A memory device, comprising: a multiplying cell (210, 310) comprising: a memory cell in which a value is stored, wherein the memory cell comprises a pair of inverters (INV1, INV2) comprising a first inverter and a second inverter, each inverter comprising an input and an output, wherein the input of the first inverter is connected to the output of the second inverter at a first end of the pair of inverters, and wherein the output of the first inverter is connected to the input of the second inverter at a second end of the pair of inverters, a first transistor connected to the first end of the pair of inverters, and a second transistor connected to the second end of the pair of inverters; and a switching element configured as a pull-up transistor and connected to an output end (N out) of the memory cell, the pull-up transistor configured to select one operation from between a first operation and a second operation and perform the selected operation, and to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the stored value, wherein the first operation comprises driving a voltage at an output end of the pull-up transistor to a supply voltage in response to a voltage less than the supply voltage being applied through a word line (WL m) in some multiplication operations in a series of multiplication operations, and outputting each time a multiplication operation result according to an input supplied to the memory device (100, 200), and wherein the second operation comprises driving a voltage at the output end of the pull-up transistor to the supply voltage in a pre-charge phase for each multiplication operation, and performing a multiplication operation in an evaluation phase. a memory cell in which a value is stored, wherein the memory cell comprises a pair of inverters (INV1, INV2) comprising a first inverter and a second inverter, each inverter comprising an input and an output, wherein the input of the first inverter is connected to the output of the second inverter at a first end of the pair of inverters, and wherein the output of the first inverter is connected to the input of the second inverter at a second end of the pair of inverters, a first transistor connected to the first end of the pair of inverters, and a second transistor connected to the second end of the pair of inverters; and a switching element configured as a pull-up transistor and connected to an output end (N out) of the memory cell, the pull-up transistor configured to select one operation from between a first operation and a second operation and perform the selected operation, and to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the stored value, a first inverter and a second inverter, each inverter comprising an input and an output, wherein the input of the first inverter is connected to the output of the second inverter at a first end of the pair of inverters, and wherein the output of the first inverter is connected to the input of the second inverter at a second end of the pair of inverters, a first transistor connected to the first end of the pair of inverters, and a second transistor connected to the second end of the pair of inverters; and a switching element configured as a pull-up transistor and connected to an output end (N out) of the memory cell, the pull-up transistor configured to select one operation from between a first operation and a second operation and perform the selected operation, and to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the stored value, wherein the first operation comprises driving a voltage at an output end of the pull-up transistor to a supply voltage in response to a voltage less than the supply voltage being applied through a word line (WL m) in some multiplication operations in a series of multiplication operations, and outputting each time a multiplication operation result according to an input supplied to the memory device (100, 200), and wherein the second operation comprises driving a voltage at the output end of the pull-up transistor to the supply voltage in a pre-charge phase for each multiplication operation, and performing a multiplication operation in an evaluation phase.