A semiconductor memory device comprising: a first interconnection line (ML1,ML2) and a second interconnection line on a substrate; and a first stack and a second stack between the substrate and the first and second interconnection lines, wherein each of the first and second stacks comprises: a plurality of semiconductor patterns vertically stacked on the substrate; a plurality of conductive bit lines connected to the plurality of semiconductor patterns, respectively, each of the plurality of conductive bit lines extending in a first horizontal direction; and a word line comprising a gate electrode that is adjacent to the plurality of semiconductor patterns and extends in a vertical direction, wherein the plurality of conductive bit lines of the first stack comprise a first conductive bit line, and the plurality of conductive bit lines of the second stack comprise a second conductive bit line, and a lower surface of the first conductive bit line is at a level equal to a level of a lower surface of the second conductive bit line, wherein the first interconnection line is electrically connected to at least one of the first and second conductive bit lines, and wherein the gate electrode of the first stack comprises a first gate electrode, the gate electrode of the second stack comprises a second gate electrode, and the second interconnection line is electrically connected to at least one of the first and second gate electrodes, wherein each of the plurality of semiconductor patterns comprises: a data storing element, a first impurity region, a second impurity region, and a channel region between the first and second impurity regions, wherein the data storing element is a capacitor having a first electrode connected to the second impurity region and a second electrode connected to a ground line, wherein each of the plurality of conductive bit lines is electrically connected to the first impurity region of each of the plurality of semiconductor patterns, and wherein each of the first and second gate electrodes is adjacent to the respective channel region of the plurality of semiconductor patterns, and wherein each of the plurality of semiconductor patterns further comprises an end layer between the first impurity region and a respective one of the plurality of conductive bit lines, and wherein the end layer comprises a first semiconductor material whose band gap is smaller than a band gap of a second semiconductor material of the channel region. a first interconnection line (ML1,ML2) and a second interconnection line on a substrate; and a first stack and a second stack between the substrate and the first and second interconnection lines, wherein each of the first and second stacks comprises: a plurality of semiconductor patterns vertically stacked on the substrate; a plurality of conductive bit lines connected to the plurality of semiconductor patterns, respectively, each of the plurality of conductive bit lines extending in a first horizontal direction; and a word line comprising a gate electrode that is adjacent to the plurality of semiconductor patterns and extends in a vertical direction, a plurality of semiconductor patterns vertically stacked on the substrate; a plurality of conductive bit lines connected to the plurality of semiconductor patterns, respectively, each of the plurality of conductive bit lines extending in a first horizontal direction; and a word line comprising a gate electrode that is adjacent to the plurality of semiconductor patterns and extends in a vertical direction, wherein the plurality of conductive bit lines of the first stack comprise a first conductive bit line, and the plurality of conductive bit lines of the second stack comprise a second conductive bit line, and a lower surface of the first conductive bit line is at a level equal to a level of a lower surface of the second conductive bit line, wherein the first interconnection line is electrically connected to at least one of the first and second conductive bit lines, and wherein the gate electrode of the first stack comprises a first gate electrode, the gate electrode of the second stack comprises a second gate electrode, and the second interconnection line is electrically connected to at least one of the first and second gate electrodes, wherein each of the plurality of semiconductor patterns comprises: a data storing element, a first impurity region, a second impurity region, and a channel region between the first and second impurity regions, wherein the data storing element is a capacitor having a first electrode connected to the second impurity region and a second electrode connected to a ground line, wherein each of the plurality of conductive bit lines is electrically connected to the first impurity region of each of the plurality of semiconductor patterns, and wherein each of the first and second gate electrodes is adjacent to the respective channel region of the plurality of semiconductor patterns, and wherein each of the plurality of semiconductor patterns further comprises an end layer between the first impurity region and a respective one of the plurality of conductive bit lines, and wherein the end layer comprises a first semiconductor material whose band gap is smaller than a band gap of a second semiconductor material of the channel region.