A microprocessor, comprising: a plurality of registers, that holds an architectural state of the microprocessor; a hardware instruction translator; and an execution pipeline, coupled to the hardware instruction translator, the microprocessor being characterized in that: the hardware instruction translator translates x86 instruction set architecture, ISA, instructions and Advanced RISC Machines, ARM, ISA instructions into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are from a microinstruction set that is distinct from the x86 ISA and the ARM ISA, wherein the hardware instruction translator translates, as instructions of a boot ISA of the microprocessor, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal; the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions; the boot ISA is either the x86 ISA or the ARM ISA, depending on a default ISA boot mode of the microprocessor; and in response to the reset signal, the microprocessor is arranged to: determine the default ISA boot mode; and initialize a first subset of its architectural state registers to x86 ISA default values, initialize a second subset of its architectural state registers to ARM ISA default values, and initialize a third subset of its architectural state registers to values defined by the boot ISA, wherein the microprocessor is arranged to initialize the first, second and third subsets prior to fetching the initial ISA instructions. a plurality of registers, that holds an architectural state of the microprocessor; a hardware instruction translator; and an execution pipeline, coupled to the hardware instruction translator, the microprocessor being characterized in that: the hardware instruction translator translates x86 instruction set architecture, ISA, instructions and Advanced RISC Machines, ARM, ISA instructions into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are from a microinstruction set that is distinct from the x86 ISA and the ARM ISA, wherein the hardware instruction translator translates, as instructions of a boot ISA of the microprocessor, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal; the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions; the boot ISA is either the x86 ISA or the ARM ISA, depending on a default ISA boot mode of the microprocessor; and in response to the reset signal, the microprocessor is arranged to: determine the default ISA boot mode; and initialize a first subset of its architectural state registers to x86 ISA default values, initialize a second subset of its architectural state registers to ARM ISA default values, and initialize a third subset of its architectural state registers to values defined by the boot ISA, wherein the microprocessor is arranged to initialize the first, second and third subsets prior to fetching the initial ISA instructions. the hardware instruction translator translates x86 instruction set architecture, ISA, instructions and Advanced RISC Machines, ARM, ISA instructions into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are from a microinstruction set that is distinct from the x86 ISA and the ARM ISA, wherein the hardware instruction translator translates, as instructions of a boot ISA of the microprocessor, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal; the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions; the boot ISA is either the x86 ISA or the ARM ISA, depending on a default ISA boot mode of the microprocessor; and in response to the reset signal, the microprocessor is arranged to: determine the default ISA boot mode; and initialize a first subset of its architectural state registers to x86 ISA default values, initialize a second subset of its architectural state registers to ARM ISA default values, and initialize a third subset of its architectural state registers to values defined by the boot ISA, wherein the microprocessor is arranged to initialize the first, second and third subsets prior to fetching the initial ISA instructions. determine the default ISA boot mode; and initialize a first subset of its architectural state registers to x86 ISA default values, initialize a second subset of its architectural state registers to ARM ISA default values, and initialize a third subset of its architectural state registers to values defined by the boot ISA, wherein the microprocessor is arranged to initialize the first, second and third subsets prior to fetching the initial ISA instructions.