A memory cell (2a, 2b, 2c, 2d) comprising: a drain region disposed on a surface of a memory well (MPW, MPW1), a bit line (BL1, BL2) being connected to the drain region; a source region disposed on the surface of the memory well (MPW, MPW1), a source line being connected to the source region; a memory gate structure disposed between the drain region and the source region, the memory gate structure including a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked in this order over the memory well (MPW, MPW1); a first select gate structure including a first select gate electrode and a first select gate insulating film, the first select gate electrode being disposed through the first select gate insulating film over the memory well (MPW, MPW1) between the drain region and the memory gate structure, the first select gate structure being adjacent to a first sidewall of the memory gate structure through a first sidewall spacer; and a second select gate structure including a second select gate electrode and a second select gate insulating film, the second select gate electrode being disposed through the second select gate insulating film over the memory well (MPW, MPW1) between the source region and the memory gate structure, the second select gate structure being adjacent to a second sidewall of the memory gate structure through a second sidewall spacer; wherein: the charge storage layer of the memory gate structure is disposed only in a region through which the memory gate electrode faces the memory well (MPW, MPW1), and the charge storage layer is in neither of the first sidewall spacer nor the second sidewall spacer, the first sidewall spacer being disposed between the memory gate structure and the first select gate structure, the second sidewall spacer being disposed between the memory gate structure and the second select gate structure; each of the first select gate electrode and the second select gate electrode has a sidewall shape with respect to the memory gate electrode, the first and second select gate electrodes (DG, SG) being disposed along the first and second sidewalls of the memory gate electrode through the first and second sidewall spacers (28a, 28b), the first and second select gate electrodes (DG, SG) facing each other; and impurity concentration of a region from the surface to a depth of 50 nm in the memory well (MPW, MPW1) between the first select gate electrode and the second select gate electrode is less than or equal to 3E18/cm3, and a thickness of each of the first select gate insulating film and the second select gate insulating film is less than or equal to 3 nm. a drain region disposed on a surface of a memory well (MPW, MPW1), a bit line (BL1, BL2) being connected to the drain region; a source region disposed on the surface of the memory well (MPW, MPW1), a source line being connected to the source region; a memory gate structure disposed between the drain region and the source region, the memory gate structure including a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked in this order over the memory well (MPW, MPW1); a first select gate structure including a first select gate electrode and a first select gate insulating film, the first select gate electrode being disposed through the first select gate insulating film over the memory well (MPW, MPW1) between the drain region and the memory gate structure, the first select gate structure being adjacent to a first sidewall of the memory gate structure through a first sidewall spacer; and a second select gate structure including a second select gate electrode and a second select gate insulating film, the second select gate electrode being disposed through the second select gate insulating film over the memory well (MPW, MPW1) between the source region and the memory gate structure, the second select gate structure being adjacent to a second sidewall of the memory gate structure through a second sidewall spacer; wherein: the charge storage layer of the memory gate structure is disposed only in a region through which the memory gate electrode faces the memory well (MPW, MPW1), and the charge storage layer is in neither of the first sidewall spacer nor the second sidewall spacer, the first sidewall spacer being disposed between the memory gate structure and the first select gate structure, the second sidewall spacer being disposed between the memory gate structure and the second select gate structure; each of the first select gate electrode and the second select gate electrode has a sidewall shape with respect to the memory gate electrode, the first and second select gate electrodes (DG, SG) being disposed along the first and second sidewalls of the memory gate electrode through the first and second sidewall spacers (28a, 28b), the first and second select gate electrodes (DG, SG) facing each other; and impurity concentration of a region from the surface to a depth of 50 nm in the memory well (MPW, MPW1) between the first select gate electrode and the second select gate electrode is less than or equal to 3E18/cm3, and a thickness of each of the first select gate insulating film and the second select gate insulating film is less than or equal to 3 nm.