A trench-gated MIS device formed in a semiconductor chip and comprising: an active area including transistor cells; a gate metal area containing no transistor cells; and a gate metal layer, wherein a trench (84, 303) is formed in a pattern on a surface of the semiconductor chip, the trench (84, 303) extending from the active area into the gate metal area, the trench (84, 303) having walls lined with a layer of an insulating material (85, 304), a conductive gate material (86, 305) being disposed in the trench (84, 303), a top surface (87, 306) of the conductive gate material (86, 305) being at a level below a top surface of the semiconductor chip, a nonconductive layer (89, 308) overlying the active area and gate metal area, an aperture being formed in the nonconductive layer (89, 308) over a portion of the trench (84, 303) in the gate metal area, the aperture being filled with the gate metal layer such that the gate metal layer contacts the conductive gate material (86, 305) in an area of contact within the trench (84, 303); wherein: the trench (84, 303) is a first gate finger, the device further comprising a second gate finger extending from the active area to the gate metal area, wherein the first gate finger includes a first widened portion, wherein the second gate finger includes a second widened portion, wherein the aperture in the nonconductive layer (89, 308) overlies the first widened portion, wherein a second aperture in the nonconductive layer (89, 308) overlies the second widened portion, the second aperture being filled with the gate metal layer such that the gate metal layer contacts the conductive gate material (86, 305) at a level no higher than the top surface of the semiconductor chip, the device characterized in that the first and second widened portions are offset with respect to each other in a direction parallel to the first and second gate fingers. an active area including transistor cells; a gate metal area containing no transistor cells; and a gate metal layer, wherein a trench (84, 303) is formed in a pattern on a surface of the semiconductor chip, the trench (84, 303) extending from the active area into the gate metal area, the trench (84, 303) having walls lined with a layer of an insulating material (85, 304), a conductive gate material (86, 305) being disposed in the trench (84, 303), a top surface (87, 306) of the conductive gate material (86, 305) being at a level below a top surface of the semiconductor chip, a nonconductive layer (89, 308) overlying the active area and gate metal area, an aperture being formed in the nonconductive layer (89, 308) over a portion of the trench (84, 303) in the gate metal area, the aperture being filled with the gate metal layer such that the gate metal layer contacts the conductive gate material (86, 305) in an area of contact within the trench (84, 303); wherein: the trench (84, 303) is a first gate finger, the device further comprising a second gate finger extending from the active area to the gate metal area, wherein the first gate finger includes a first widened portion, wherein the second gate finger includes a second widened portion, wherein the aperture in the nonconductive layer (89, 308) overlies the first widened portion, wherein a second aperture in the nonconductive layer (89, 308) overlies the second widened portion, the second aperture being filled with the gate metal layer such that the gate metal layer contacts the conductive gate material (86, 305) at a level no higher than the top surface of the semiconductor chip, the device characterized in that the first and second widened portions are offset with respect to each other in a direction parallel to the first and second gate fingers. the trench (84, 303) is a first gate finger, the device further comprising a second gate finger extending from the active area to the gate metal area, wherein the first gate finger includes a first widened portion, wherein the second gate finger includes a second widened portion, wherein the aperture in the nonconductive layer (89, 308) overlies the first widened portion, wherein a second aperture in the nonconductive layer (89, 308) overlies the second widened portion, the second aperture being filled with the gate metal layer such that the gate metal layer contacts the conductive gate material (86, 305) at a level no higher than the top surface of the semiconductor chip, the device characterized in that the first and second widened portions are offset with respect to each other in a direction parallel to the first and second gate fingers.