An apparatus, comprising: a plurality of memory cells (680a, 681a, 682a, 683a, 684a and 685a, 703-716, 723-736, 743-756, 763-776) arranged in a NAND string (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n), the plurality of memory cells comprise first memory cells (680a, 681a, 684a and 685a) spaced apart by a first distance and second memory cells (682a, 683a) spaced apart by a second distance, larger than the first distance, wherein the first and second distances are inter-cell distances between adjacent memory cells of the NAND string; and a control circuit (51-53, 110, 122) configured to sense a conductive state of a selected memory cell in the NAND string while applying a pass voltage (Vpass) to the first memory cells and to the second memory cells, and, after sensing the conductive state of the selected memory cell and when one or more conditions are met, complete a decrease of voltages (1210d, 1210e, 1210f) of the second memory cells from the pass voltage to a steady state voltage after completing a decrease of voltages of the first memory cells from the pass voltage to the steady state voltage, wherein the one or more conditions comprise the selected memory cell being within a specified range of positions (source side-IF) in the NAND string; wherein: the NAND string has a source end and a drain end; and the specified range of positions in the NAND string comprise positions between the source end and the second memory cells but not between the drain end and the second memory cells. a plurality of memory cells (680a, 681a, 682a, 683a, 684a and 685a, 703-716, 723-736, 743-756, 763-776) arranged in a NAND string (NS1, NS2, 700n-703n, 710n-713n, 720n-723n, 730n-733n), the plurality of memory cells comprise first memory cells (680a, 681a, 684a and 685a) spaced apart by a first distance and second memory cells (682a, 683a) spaced apart by a second distance, larger than the first distance, wherein the first and second distances are inter-cell distances between adjacent memory cells of the NAND string; and a control circuit (51-53, 110, 122) configured to sense a conductive state of a selected memory cell in the NAND string while applying a pass voltage (Vpass) to the first memory cells and to the second memory cells, and, after sensing the conductive state of the selected memory cell and when one or more conditions are met, complete a decrease of voltages (1210d, 1210e, 1210f) of the second memory cells from the pass voltage to a steady state voltage after completing a decrease of voltages of the first memory cells from the pass voltage to the steady state voltage, wherein the one or more conditions comprise the selected memory cell being within a specified range of positions (source side-IF) in the NAND string; wherein: the NAND string has a source end and a drain end; and the specified range of positions in the NAND string comprise positions between the source end and the second memory cells but not between the drain end and the second memory cells. the NAND string has a source end and a drain end; and the specified range of positions in the NAND string comprise positions between the source end and the second memory cells but not between the drain end and the second memory cells.