A digital-to-analog converter, DAC, comprising: a latch circuit comprising: a latch that receives a first digital signal and a clock signal and outputs, according to the clock signal, an intermediate signal and an inverse intermediate signal that is an inverse of the intermediate signal; and an N-type metal-oxide semiconductor, NMOS, field effect transistor-based buffer coupled to receive the intermediate signal and the inverse intermediate signal from the latch and output a buffered intermediate signal and a buffered inverse intermediate signal that is an inverse of the buffered intermediate signal, one of the buffered intermediate signal and the buffered inverse intermediate signal being a second digital signal, wherein the second digital signal (Q, QB) is output from the NMOS field effect transistor-based buffer according to the clock signal and wherein the second digital signal (Q, QB) is associated with the first digital signal; and a cell circuit, coupled to the latch circuit, that receives the second digital signal (Q, QB) and outputs an analog signal (outp, putn) representative of the first digital signal, wherein the cell circuit comprises a pair of differential p-type metal-oxide-semiconductor, PMOS, field effect transistors (212, 214) having a first PMOS transistor switched on or off according to the buffered intermediate signal and a second PMOS transistor switched on or off according to the buffered inverse intermediate signal. a latch circuit comprising: a latch that receives a first digital signal and a clock signal and outputs, according to the clock signal, an intermediate signal and an inverse intermediate signal that is an inverse of the intermediate signal; and an N-type metal-oxide semiconductor, NMOS, field effect transistor-based buffer coupled to receive the intermediate signal and the inverse intermediate signal from the latch and output a buffered intermediate signal and a buffered inverse intermediate signal that is an inverse of the buffered intermediate signal, one of the buffered intermediate signal and the buffered inverse intermediate signal being a second digital signal, wherein the second digital signal (Q, QB) is output from the NMOS field effect transistor-based buffer according to the clock signal and wherein the second digital signal (Q, QB) is associated with the first digital signal; and a latch that receives a first digital signal and a clock signal and outputs, according to the clock signal, an intermediate signal and an inverse intermediate signal that is an inverse of the intermediate signal; and an N-type metal-oxide semiconductor, NMOS, field effect transistor-based buffer coupled to receive the intermediate signal and the inverse intermediate signal from the latch and output a buffered intermediate signal and a buffered inverse intermediate signal that is an inverse of the buffered intermediate signal, one of the buffered intermediate signal and the buffered inverse intermediate signal being a second digital signal, wherein the second digital signal (Q, QB) is output from the NMOS field effect transistor-based buffer according to the clock signal and wherein the second digital signal (Q, QB) is associated with the first digital signal; and a cell circuit, coupled to the latch circuit, that receives the second digital signal (Q, QB) and outputs an analog signal (outp, putn) representative of the first digital signal, wherein the cell circuit comprises a pair of differential p-type metal-oxide-semiconductor, PMOS, field effect transistors (212, 214) having a first PMOS transistor switched on or off according to the buffered intermediate signal and a second PMOS transistor switched on or off according to the buffered inverse intermediate signal.