A semiconductor device comprising: a first master device and a second master device; a slave device accessible by the first and second master devices (101, 102); a bus connecting the first and second master devices (101, 102) and the slave device; a priority generation circuit for outputting a priority (PRTY) indicating whether the priority of the first master device is high or low, based on a transfer amount between the first master device and the slave device; and an arbitration circuit for performing an arbitration based on the priority (PRTY) when the first master and the second master simultaneously issue access requests to the slave device, wherein the priority generation circuit includes: a target determination circuit configured to assert an enable signal when a transfer address of the first master device matches with an address of the slave device; a cycle counter configured to repeatedly count a unitary unit cycle set in a cycle setting register from an initial assertion of the enable signal, and assert a count end flag (CEND) at an end of a unitary unit count; a transfer amount counter configured to increment a transfer size when the enable signal is asserted, and initialize its count value to 0 when the count end flag (CEND) is asserted; a threshold value determination circuit configured to determine whether a value of the transfer amount counter has reached a threshold value set in a threshold value setting register, and assert a threshold determination signal when the value of the transfer amount counter is smaller than the threshold value; and a priority determination circuit configured to generate the priority (PRTY) indicating that the priority of the first master device is high when the enable signal and the threshold value determination signal are both asserted; and wherein the arbitration circuit is configured to issue use permission of the bus to the first master device when the priority (PRTY) indicates that the priority of the first master device is high. a first master device and a second master device; a slave device accessible by the first and second master devices (101, 102); a bus connecting the first and second master devices (101, 102) and the slave device; a priority generation circuit for outputting a priority (PRTY) indicating whether the priority of the first master device is high or low, based on a transfer amount between the first master device and the slave device; and an arbitration circuit for performing an arbitration based on the priority (PRTY) when the first master and the second master simultaneously issue access requests to the slave device, wherein the priority generation circuit includes: a target determination circuit configured to assert an enable signal when a transfer address of the first master device matches with an address of the slave device; a cycle counter configured to repeatedly count a unitary unit cycle set in a cycle setting register from an initial assertion of the enable signal, and assert a count end flag (CEND) at an end of a unitary unit count; a transfer amount counter configured to increment a transfer size when the enable signal is asserted, and initialize its count value to 0 when the count end flag (CEND) is asserted; a threshold value determination circuit configured to determine whether a value of the transfer amount counter has reached a threshold value set in a threshold value setting register, and assert a threshold determination signal when the value of the transfer amount counter is smaller than the threshold value; and a priority determination circuit configured to generate the priority (PRTY) indicating that the priority of the first master device is high when the enable signal and the threshold value determination signal are both asserted; and a target determination circuit configured to assert an enable signal when a transfer address of the first master device matches with an address of the slave device; a cycle counter configured to repeatedly count a unitary unit cycle set in a cycle setting register from an initial assertion of the enable signal, and assert a count end flag (CEND) at an end of a unitary unit count; a transfer amount counter configured to increment a transfer size when the enable signal is asserted, and initialize its count value to 0 when the count end flag (CEND) is asserted; a threshold value determination circuit configured to determine whether a value of the transfer amount counter has reached a threshold value set in a threshold value setting register, and assert a threshold determination signal when the value of the transfer amount counter is smaller than the threshold value; and a priority determination circuit configured to generate the priority (PRTY) indicating that the priority of the first master device is high when the enable signal and the threshold value determination signal are both asserted; and wherein the arbitration circuit is configured to issue use permission of the bus to the first master device when the priority (PRTY) indicates that the priority of the first master device is high.