A microprocessor, comprising: a processing unit; a translation lookaside buffer comprising a plurality of TLB slots; a memory cache comprising a plurality of cache slots; and control logic that is characterized to configure the microprocessor to at least: identify a first TLB entry in a first of the plurality of TLB slots, the first TLB entry comprising a first mapping between a first virtual address of a first virtual memory page within a first virtual address space and a physical address of a physical memory page within a hardware memory; initiate logging of the first TLB entry into an execution trace, including initiating logging of at least (i) the first virtual address, and (ii) a first identifier for the first TLB entry; identify a second TLB entry in a second of the plurality of TLB slots, the second TLB entry comprising a second mapping between a second virtual address of a second virtual memory page within a second virtual address space and the physical address of the physical memory page within the hardware memory that is mapped to by the first TLB entry; initiate logging of the second TLB entry into the execution trace, including initiating logging of at least (i) the second virtual address, and (ii) a second identifier for the second TLB entry; in connection with initiating logging of the second TLB entry into the execution trace, determine that the first TLB entry and the second TLB entry each (i) are live in the TLB, (ii) are logged into the execution trace, and (iii) have common mappings to the physical address; and based at least on the determination, ensure that the execution trace indicates that the first TLB entry and the second TLB entry each map to the physical address. a processing unit; a translation lookaside buffer comprising a plurality of TLB slots; a memory cache comprising a plurality of cache slots; and control logic that is characterized to configure the microprocessor to at least: identify a first TLB entry in a first of the plurality of TLB slots, the first TLB entry comprising a first mapping between a first virtual address of a first virtual memory page within a first virtual address space and a physical address of a physical memory page within a hardware memory; initiate logging of the first TLB entry into an execution trace, including initiating logging of at least (i) the first virtual address, and (ii) a first identifier for the first TLB entry; identify a second TLB entry in a second of the plurality of TLB slots, the second TLB entry comprising a second mapping between a second virtual address of a second virtual memory page within a second virtual address space and the physical address of the physical memory page within the hardware memory that is mapped to by the first TLB entry; initiate logging of the second TLB entry into the execution trace, including initiating logging of at least (i) the second virtual address, and (ii) a second identifier for the second TLB entry; in connection with initiating logging of the second TLB entry into the execution trace, determine that the first TLB entry and the second TLB entry each (i) are live in the TLB, (ii) are logged into the execution trace, and (iii) have common mappings to the physical address; and based at least on the determination, ensure that the execution trace indicates that the first TLB entry and the second TLB entry each map to the physical address. identify a first TLB entry in a first of the plurality of TLB slots, the first TLB entry comprising a first mapping between a first virtual address of a first virtual memory page within a first virtual address space and a physical address of a physical memory page within a hardware memory; initiate logging of the first TLB entry into an execution trace, including initiating logging of at least (i) the first virtual address, and (ii) a first identifier for the first TLB entry; identify a second TLB entry in a second of the plurality of TLB slots, the second TLB entry comprising a second mapping between a second virtual address of a second virtual memory page within a second virtual address space and the physical address of the physical memory page within the hardware memory that is mapped to by the first TLB entry; initiate logging of the second TLB entry into the execution trace, including initiating logging of at least (i) the second virtual address, and (ii) a second identifier for the second TLB entry; in connection with initiating logging of the second TLB entry into the execution trace, determine that the first TLB entry and the second TLB entry each (i) are live in the TLB, (ii) are logged into the execution trace, and (iii) have common mappings to the physical address; and based at least on the determination, ensure that the execution trace indicates that the first TLB entry and the second TLB entry each map to the physical address.