A shift register comprising at least four shift register units in stages, one of the at least four shift register units comprising: a first capacitor, a first transistor, a pull-up module, a first pull-down module, and a second pull-down module, wherein the first transistor has a first electrode configured to receive a clock signal, a gate connected with one terminal of the first capacitor, the pull-up module and the first pull-down module, and a second electrode connected with the other terminal of the first capacitor; the pull-up module is configured to output a first level signal to the gate of the first transistor when the clock signal is at a second level and a pull-up selection signal (OUT(n-1)) is at a first level; and to not output the first level signal to the gate of the first transistor when the clock signal is at the first level and the pull-up selection signal (OUT(n-1)) is at the second level, wherein the pull-up selection signal (OUT(n-1)) is a signal output from the shift register unit of said at least four register units one-stage previous to said one of the at least four shift register units; the first pull-down module is configured to control the gate of the first transistor to be connected to a second level signal input terminal when the clock signal is at the first level and a first pull-down selection signal (OUT(n+2)) is at the first level, wherein the first pull-down selection signal (OUT(n+2)) is a signal output from the shift register unit of said at least four register units two-stages subsequent to said one of the at least four shift register units; the first transistor is configured to output the received clock signal from the second electrode of the first transistor when a signal at the gate of the first transistor is at the first level; and to not output the received clock signal from the second electrode of the first transistor when the signal at the gate of the first transistor is at the second level; the second pull-down module is connected with the gate and the second electrode of the first transistor, characterized in that the second pull-down module is configured to - control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal in response to the pull-up selection signal (OUT(n-1)) being at the first level; - control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal in response to a second pull-down selection signal (OUT(n+1)) being at the first level; - control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal in response to a clock blocking signal (CLKB) being at the second level; and - control the gate and the second electrode of the first transistor to be connected with the second level signal input terminal in response to the pull-up selection signal (OUT(n-1)), the first pull-down selection signal (OUT(n+2)), and the second pull-down selection signal (OUT(n+1)) all being at the second level, the clock signal being at the second level and the clock blocking signal (CLKB) being at the first level, wherein the second pull-down selection signal (OUT(n+1)) is a signal output from the shift register unit of said at least four shift register units one-stage subsequent to said one of the at least four shift register units. - control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal in response to the pull-up selection signal (OUT(n-1)) being at the first level; - control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal in response to a second pull-down selection signal (OUT(n+1)) being at the first level; - control the gate and the second electrode of the first transistor to be disconnected from the second level signal input terminal in response to a clock blocking signal (CLKB) being at the second level; and - control the gate and the second electrode of the first transistor to be connected with the second level signal input terminal in response to the pull-up selection signal (OUT(n-1)), the first pull-down selection signal (OUT(n+2)), and the second pull-down selection signal (OUT(n+1)) all being at the second level, the clock signal being at the second level and the clock blocking signal (CLKB) being at the first level, wherein the second pull-down selection signal (OUT(n+1)) is a signal output from the shift register unit of said at least four shift register units one-stage subsequent to said one of the at least four shift register units.