A device, comprising: a first delay line having a plurality of delay elements (NS2-NS9), the first delay line being configured to receive a first input clock signal (INPX) and output to a sampler circuit a first plurality of output clock signals having different phases compared to a phase of the first input clock signal (INPX); a second delay line having a plurality of delay elements (S2-S9), the second delay line being configured to receive a second input clock signal (INNX) and output to a sampler circuit a second plurality of output clock signals having different phases compared to a phase of the second input clock signal (INNX); and a control circuit configured to control the first and second delay lines (202a, 202b) based at least in part upon a rising or falling edge of at least one output clock signal of the first plurality of output clocks signals and at least one output clock signal of the second plurality of output clock signals, characterized in that the device further comprises a crossover control module communicatively coupled to the first and second delay lines (202a, 202b), the crossover control module being configured to receive clock signals (INN, INP) from a clock signal source, receive output signals (FBCLKO, NFBCLKO) from a first delay element and a second delay element of the plurality of delay elements, the second delay element being complementary to the first delay element, utilize a signal crossover point for the output signals (FBCLK0, NFBCLKO) from the first delay element and the second delay element to determine a crossover error in the complementary clock input signals (INN and INP) and thereby generate the first and second input clock signals (INPX INNX) for the first and second delay lines (202a, 202b) respectively using the crossover error. a first delay line having a plurality of delay elements (NS2-NS9), the first delay line being configured to receive a first input clock signal (INPX) and output to a sampler circuit a first plurality of output clock signals having different phases compared to a phase of the first input clock signal (INPX); a second delay line having a plurality of delay elements (S2-S9), the second delay line being configured to receive a second input clock signal (INNX) and output to a sampler circuit a second plurality of output clock signals having different phases compared to a phase of the second input clock signal (INNX); and a control circuit configured to control the first and second delay lines (202a, 202b) based at least in part upon a rising or falling edge of at least one output clock signal of the first plurality of output clocks signals and at least one output clock signal of the second plurality of output clock signals, characterized in that the device further comprises a crossover control module communicatively coupled to the first and second delay lines (202a, 202b), the crossover control module being configured to receive clock signals (INN, INP) from a clock signal source, receive output signals (FBCLKO, NFBCLKO) from a first delay element and a second delay element of the plurality of delay elements, the second delay element being complementary to the first delay element, utilize a signal crossover point for the output signals (FBCLK0, NFBCLKO) from the first delay element and the second delay element to determine a crossover error in the complementary clock input signals (INN and INP) and thereby generate the first and second input clock signals (INPX INNX) for the first and second delay lines (202a, 202b) respectively using the crossover error. receive clock signals (INN, INP) from a clock signal source, receive output signals (FBCLKO, NFBCLKO) from a first delay element and a second delay element of the plurality of delay elements, the second delay element being complementary to the first delay element, utilize a signal crossover point for the output signals (FBCLK0, NFBCLKO) from the first delay element and the second delay element to determine a crossover error in the complementary clock input signals (INN and INP) and thereby generate the first and second input clock signals (INPX INNX) for the first and second delay lines (202a, 202b) respectively using the crossover error.