A method of fabricating a planar gate power metal-oxide-semiconductor field effect transistor, power MOSFET, comprising: providing a planar gate power MOSFET die including a plurality of transistor cells including a first cell and at least a second cell formed on a substrate having a semiconductor surface layer doped to a first conductivity type, said first cell having a first gate stack and said second cell having a second gate stack, each said gate stack including a gate electrode on a gate dielectric over a body region, a trench having an aspect ratio of at least 3 extending down from a top side of said semiconductor surface layer between said first and said second gate stack, the trench comprising a source contact from said substrate to a source doped to a second conductivity type, a field plate over said gate stacks extending to provide a liner for said trench, said trench having a refractory or platinum-group metal filler within, and a drain doped to said second conductivity type in said semiconductor surface layer on a side of said gate stacks opposite said trench; wherein forming said metal filler comprises: a first step of forming metal filler material within said trench; a second step of etching back said metal filler material for removing said metal filler material along a sidewall of said field plate next to said drain and removing a portion of said metal filler material in said trench; a third step of depositing metal filler material to fill said trench, and a fourth step of etching back metal filler material. providing a planar gate power MOSFET die including a plurality of transistor cells including a first cell and at least a second cell formed on a substrate having a semiconductor surface layer doped to a first conductivity type, said first cell having a first gate stack and said second cell having a second gate stack, each said gate stack including a gate electrode on a gate dielectric over a body region, a trench having an aspect ratio of at least 3 extending down from a top side of said semiconductor surface layer between said first and said second gate stack, the trench comprising a source contact from said substrate to a source doped to a second conductivity type, a field plate over said gate stacks extending to provide a liner for said trench, said trench having a refractory or platinum-group metal filler within, and a drain doped to said second conductivity type in said semiconductor surface layer on a side of said gate stacks opposite said trench; wherein forming said metal filler comprises: a first step of forming metal filler material within said trench; a second step of etching back said metal filler material for removing said metal filler material along a sidewall of said field plate next to said drain and removing a portion of said metal filler material in said trench; a third step of depositing metal filler material to fill said trench, and a fourth step of etching back metal filler material. a first step of forming metal filler material within said trench; a second step of etching back said metal filler material for removing said metal filler material along a sidewall of said field plate next to said drain and removing a portion of said metal filler material in said trench; a third step of depositing metal filler material to fill said trench, and a fourth step of etching back metal filler material.