A successive approximation register, hereinafter SAR, analog-to-digital converter, hereinafter ADC, comprising: a capacitor-based digital-to-analog converter, also referred to as CDAC, for receiving an input Voltage (V in) and generating a sampled input voltage (V' in); a comparing module, arranged to generate a first comparison result by comparing the sampled input voltage (V' in) of the SAR ADC with a first voltage value (V cm +V delta) and a second comparison result by comparing the sampled input voltage (V' in) with a second voltage value (V cm -V delta); a calibration circuit, coupled to the comparing module, for generating a determination result determining whether the sampled input voltage (V' in) is in a predetermined range according to the first comparison result and the second comparison result, and configured to enter a calibration mode when the determination result indicates that the sampled input voltage (V'in) is in the predetermined range; wherein the SAR ADC further comprises: a SAR logic circuit, arranged to generate an n-bit output signal, based on a comparison of the sampled input voltage and a third voltage value, wherein the third voltage value is a common mode voltage (V cm), the first and the second voltage values correspond respectively a sum and a difference of the common mode voltage and a voltage difference (V delta), wherein n is a positive integer; wherein the calibration circuit performs, in the calibration mode, a weighted number calibration for at least one bit of the n-bit output signal of the SAR logic circuit according to the determination result; wherein each of the at least one bit of the n-bit output signal corresponds to a weighted number. a capacitor-based digital-to-analog converter, also referred to as CDAC, for receiving an input Voltage (V in) and generating a sampled input voltage (V' in); a comparing module, arranged to generate a first comparison result by comparing the sampled input voltage (V' in) of the SAR ADC with a first voltage value (V cm +V delta) and a second comparison result by comparing the sampled input voltage (V' in) with a second voltage value (V cm -V delta); a calibration circuit, coupled to the comparing module, for generating a determination result determining whether the sampled input voltage (V' in) is in a predetermined range according to the first comparison result and the second comparison result, and configured to enter a calibration mode when the determination result indicates that the sampled input voltage (V'in) is in the predetermined range; wherein the SAR ADC further comprises: a SAR logic circuit, arranged to generate an n-bit output signal, based on a comparison of the sampled input voltage and a third voltage value, wherein the third voltage value is a common mode voltage (V cm), the first and the second voltage values correspond respectively a sum and a difference of the common mode voltage and a voltage difference (V delta), wherein n is a positive integer; wherein the calibration circuit performs, in the calibration mode, a weighted number calibration for at least one bit of the n-bit output signal of the SAR logic circuit according to the determination result; wherein each of the at least one bit of the n-bit output signal corresponds to a weighted number. a SAR logic circuit, arranged to generate an n-bit output signal, based on a comparison of the sampled input voltage and a third voltage value, wherein the third voltage value is a common mode voltage (V cm), the first and the second voltage values correspond respectively a sum and a difference of the common mode voltage and a voltage difference (V delta), wherein n is a positive integer; wherein the calibration circuit performs, in the calibration mode, a weighted number calibration for at least one bit of the n-bit output signal of the SAR logic circuit according to the determination result; wherein each of the at least one bit of the n-bit output signal corresponds to a weighted number.