A low dropout, LDO, voltage regulator comprising: an LDO input configured to receive an input voltage signal; an LDO output configured to output an output voltage signal; an error amplifying circuit, which is configured to receive a reference signal and a feedback signal associated with the output voltage signal, the error amplifying circuit being further configured to output an error signal; an output stage, which is configured to receive the error signal and output a control signal; and an output device, which is connected to the LDO input and configured to provide the output voltage signal and which is controlled by the control signal for regulating the output voltage signal; wherein the output stage is connected to the LDO input for receiving an adaptive bias current, and wherein the output stage comprises: a current mirror and an output stage active load transistor, wherein a gate and drain of the output stage active load transistor is connected to an output of the current mirror and a source of the output stage active load transistor is connected to the LDO input, and the gate of the output stage active load transistor further being connected to the output device for providing the control signal, and characterized in that the output stage further comprises an impedance circuit, which is connected in parallel to the output stage active load transistor and which is configured to selectively provide an impedance when an output current of the LDO voltage regulator is below a threshold, wherein the impedance circuit comprises a control transistor, which is configured to control a current through the impedance circuit, the impedance circuit further comprising a diode-connected transistor connected to the control transistor, the diode-connected transistor having a lower threshold voltage than the output stage active load transistor. an LDO input configured to receive an input voltage signal; an LDO output configured to output an output voltage signal; an error amplifying circuit, which is configured to receive a reference signal and a feedback signal associated with the output voltage signal, the error amplifying circuit being further configured to output an error signal; an output stage, which is configured to receive the error signal and output a control signal; and an output device, which is connected to the LDO input and configured to provide the output voltage signal and which is controlled by the control signal for regulating the output voltage signal; wherein the output stage is connected to the LDO input for receiving an adaptive bias current, and wherein the output stage comprises: a current mirror and an output stage active load transistor, wherein a gate and drain of the output stage active load transistor is connected to an output of the current mirror and a source of the output stage active load transistor is connected to the LDO input, and the gate of the output stage active load transistor further being connected to the output device for providing the control signal, and characterized in that the output stage further comprises an impedance circuit, which is connected in parallel to the output stage active load transistor and which is configured to selectively provide an impedance when an output current of the LDO voltage regulator is below a threshold, wherein the impedance circuit comprises a control transistor, which is configured to control a current through the impedance circuit, the impedance circuit further comprising a diode-connected transistor connected to the control transistor, the diode-connected transistor having a lower threshold voltage than the output stage active load transistor. a current mirror and an output stage active load transistor, wherein a gate and drain of the output stage active load transistor is connected to an output of the current mirror and a source of the output stage active load transistor is connected to the LDO input, and the gate of the output stage active load transistor further being connected to the output device for providing the control signal, and characterized in that the output stage further comprises an impedance circuit, which is connected in parallel to the output stage active load transistor and which is configured to selectively provide an impedance when an output current of the LDO voltage regulator is below a threshold, wherein the impedance circuit comprises a control transistor, which is configured to control a current through the impedance circuit, the impedance circuit further comprising a diode-connected transistor connected to the control transistor, the diode-connected transistor having a lower threshold voltage than the output stage active load transistor.