A method of fabricating a non-volatile storage device, the method comprising: fabricating a semiconductor channel (337; 699); fabricating a tunnel dielectric region (335; 698) wherein the tunnel dielectric region is adjacent to the semiconductor channel, wherein the tunnel dielectric region comprises a first dielectric layer (335; 712); fabricating a charge trapping region (CS0-CS7; 697) having a first charge trapping layer (341; 710), a second charge trapping layer (343; 708), and a third charge trapping layer (345; 706), including forming the second charge trapping layer between the first and third charge trapping layers, wherein the first charge trapping layer is adjacent to the tunnel dielectric region wherein the second charge trapping layer has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the first charge trapping layer relative to the semiconductor channel and has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the third charge trapping layer relative to the semiconductor channel, wherein the first charge trapping layer has a smaller valance band offset relative to the semiconductor channel than a valance band offset of the first dielectric layer relative to the semiconductor channel, wherein the second charge trapping layer comprises a high-k material having a dielectric constant greater than 7.9; fabricating a control gate dielectric (333; 696), wherein the charge trapping region is between the control gate dielectric and the tunnel dielectric; and fabricating a control gate (351; 605), wherein the control gate dielectric is between the control gate and the charge trapping region; the method characterised in that: forming the second charge trapping layer comprises depositing ZrON with ZnO; and the first charge trapping layer and the third charge trapping layer comprise lanthanum oxide. fabricating a semiconductor channel (337; 699); fabricating a tunnel dielectric region (335; 698) wherein the tunnel dielectric region is adjacent to the semiconductor channel, wherein the tunnel dielectric region comprises a first dielectric layer (335; 712); fabricating a charge trapping region (CS0-CS7; 697) having a first charge trapping layer (341; 710), a second charge trapping layer (343; 708), and a third charge trapping layer (345; 706), including forming the second charge trapping layer between the first and third charge trapping layers, wherein the first charge trapping layer is adjacent to the tunnel dielectric region wherein the second charge trapping layer has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the first charge trapping layer relative to the semiconductor channel and has a smaller conduction band offset relative to the semiconductor channel than a conduction band offset of the third charge trapping layer relative to the semiconductor channel, wherein the first charge trapping layer has a smaller valance band offset relative to the semiconductor channel than a valance band offset of the first dielectric layer relative to the semiconductor channel, wherein the second charge trapping layer comprises a high-k material having a dielectric constant greater than 7.9; fabricating a control gate dielectric (333; 696), wherein the charge trapping region is between the control gate dielectric and the tunnel dielectric; and fabricating a control gate (351; 605), wherein the control gate dielectric is between the control gate and the charge trapping region; the method characterised in that: forming the second charge trapping layer comprises depositing ZrON with ZnO; and the first charge trapping layer and the third charge trapping layer comprise lanthanum oxide. forming the second charge trapping layer comprises depositing ZrON with ZnO; and the first charge trapping layer and the third charge trapping layer comprise lanthanum oxide.