A sensor circuit (20, 24A, 24B) for sensing a parameter over a dynamic range, the sensor circuit (20, 24A, 24B) comprising: a capacitance sensor (22, 22A, 22B) that includes a sensor capacitor and a reference capacitor (CR,Cref), a sensor plate terminal connected to a first plate of the sensor capacitor, a reference plate terminal connected to a first plate of the reference capacitor, and a common plate terminal connected to a second plate of the sensor capacitor and a second plate of the reference capacitor (CR, Cref), wherein spacing between the first and second plates of the sensor capacitor changes in relation to the sensed parameter; and a capacitance-to-digital sigma delta modulator that includes an integrator having an input connected to the common plate terminal for integrating a charge generated by the capacitive sensor (20, 22A, 22B) and an output, a quantizer connected to the output of the integrator that produces a pulse code modulated output signal having a first state and a second state in response to a first clock signal (φ1) and a second clock signal (φ2) that are complementary to one another, and an excitation signal generator configured to provide a sensor excitation signal (Vexc _sen) by applying a first excitation voltage (VN, VSSA) to the sensor plate terminal when either the pulse code modulated output signal is in the first state or the first clock signal (φ1) is high and applying a second excitation voltage (VP, VP1) to the sensor plate terminal when both the pulse code modulated output signal is in the second state and the second clock signal (φ2) is high, and to provide a reference excitation signal (Vexc_ref) by applying the first excitation voltage (VN, VSSA) to the reference plate terminal when the second clock signal (φ2) is high, and either applying the second excitation voltage (VP, VP1) to the reference plate terminal when the first clock signal (φ1) is high; or applying a third reference voltage to the reference plate terminal when both the pulse code modulated output signal is in the second state and the first clock signal (φ1) is high and applying a fourth reference voltage to the reference plate terminal when both the pulse code modulated output signal is in the first state and the first clock signal (φ1) is high. a capacitance sensor (22, 22A, 22B) that includes a sensor capacitor and a reference capacitor (CR,Cref), a sensor plate terminal connected to a first plate of the sensor capacitor, a reference plate terminal connected to a first plate of the reference capacitor, and a common plate terminal connected to a second plate of the sensor capacitor and a second plate of the reference capacitor (CR, Cref), wherein spacing between the first and second plates of the sensor capacitor changes in relation to the sensed parameter; and a capacitance-to-digital sigma delta modulator that includes an integrator having an input connected to the common plate terminal for integrating a charge generated by the capacitive sensor (20, 22A, 22B) and an output, a quantizer connected to the output of the integrator that produces a pulse code modulated output signal having a first state and a second state in response to a first clock signal (φ1) and a second clock signal (φ2) that are complementary to one another, and an excitation signal generator configured to provide a sensor excitation signal (Vexc _sen) by applying a first excitation voltage (VN, VSSA) to the sensor plate terminal when either the pulse code modulated output signal is in the first state or the first clock signal (φ1) is high and applying a second excitation voltage (VP, VP1) to the sensor plate terminal when both the pulse code modulated output signal is in the second state and the second clock signal (φ2) is high, and to provide a reference excitation signal (Vexc_ref) by applying the first excitation voltage (VN, VSSA) to the reference plate terminal when the second clock signal (φ2) is high, and either applying the second excitation voltage (VP, VP1) to the reference plate terminal when the first clock signal (φ1) is high; or applying a third reference voltage to the reference plate terminal when both the pulse code modulated output signal is in the second state and the first clock signal (φ1) is high and applying a fourth reference voltage to the reference plate terminal when both the pulse code modulated output signal is in the first state and the first clock signal (φ1) is high.