A liquid crystal display comprising: a first substrate, a second substrate facing said first substrate, and a seal provided between said first substrate and said second substrate, wherein said first substrate includes an insulating substrate, a shift register (73a, 73b) monolithically formed on said insulating substrate, a plurality of bus lines (12, 13), a first end side of said first substrate, and a display region, said shift register (73a, 73b) includes a plurality of multistage-connected unit circuits (SR1,..., SRn) and wiring (74 to 76) connected to said plurality of unit circuits (SR1,..., SRn), the shift register (73a, 73b) being arranged in a region between said first end side and said display region, at least one of said plurality of unit circuits (SR1,..., SRn) includes: a clock terminal (CKA, CKB) into which a clock signal is input, an output terminal connected to a corresponding bus line, the output terminal outputting an output signal (SROUT), a first transistor with one of a source and a drain being connected to said clock terminal (CKA, CKB) and the other of said source and said drain being connected to said output terminal, a second transistor (Tr2, Tr3, Tr4), and a capacitor with a first terminal being connected to a gate of said first transistor and a second terminal being connected to said output terminal, and said first transistor and said capacitor are arranged in a region between said first end side and one of said wiring (74 to 76) and said second transistor (Tr2, Tr3, Tr4), characterized in that said wiring (74 to 76) and said second transistor (Tr2, Tr3, Tr4) are arranged in a region between said display region and one of said first transistor and said capacitor. a first substrate, a second substrate facing said first substrate, and a seal provided between said first substrate and said second substrate, wherein said first substrate includes an insulating substrate, a shift register (73a, 73b) monolithically formed on said insulating substrate, a plurality of bus lines (12, 13), a first end side of said first substrate, and a display region, said shift register (73a, 73b) includes a plurality of multistage-connected unit circuits (SR1,..., SRn) and wiring (74 to 76) connected to said plurality of unit circuits (SR1,..., SRn), the shift register (73a, 73b) being arranged in a region between said first end side and said display region, at least one of said plurality of unit circuits (SR1,..., SRn) includes: a clock terminal (CKA, CKB) into which a clock signal is input, an output terminal connected to a corresponding bus line, the output terminal outputting an output signal (SROUT), a first transistor with one of a source and a drain being connected to said clock terminal (CKA, CKB) and the other of said source and said drain being connected to said output terminal, a second transistor (Tr2, Tr3, Tr4), and a capacitor with a first terminal being connected to a gate of said first transistor and a second terminal being connected to said output terminal, and said first transistor and said capacitor are arranged in a region between said first end side and one of said wiring (74 to 76) and said second transistor (Tr2, Tr3, Tr4), characterized in that said wiring (74 to 76) and said second transistor (Tr2, Tr3, Tr4) are arranged in a region between said display region and one of said first transistor and said capacitor. a clock terminal (CKA, CKB) into which a clock signal is input, an output terminal connected to a corresponding bus line, the output terminal outputting an output signal (SROUT), a first transistor with one of a source and a drain being connected to said clock terminal (CKA, CKB) and the other of said source and said drain being connected to said output terminal, a second transistor (Tr2, Tr3, Tr4), and a capacitor with a first terminal being connected to a gate of said first transistor and a second terminal being connected to said output terminal, and said first transistor and said capacitor are arranged in a region between said first end side and one of said wiring (74 to 76) and said second transistor (Tr2, Tr3, Tr4), characterized in that said wiring (74 to 76) and said second transistor (Tr2, Tr3, Tr4) are arranged in a region between said display region and one of said first transistor and said capacitor.