A semiconductor light-emitting element, comprising: a semiconductor stack including an n-type layer, a light-emitting layer above the n-type layer, and a p-type layer above the light-emitting layer, the semiconductor stack having at least one n exposure portion (30e, 30eb, 30es) which is a recess at which the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer that (i) continuously covers inner lateral surfaces of the at least one n exposure portion (30e, 30eb, 30es) and part of a top surface the p wiring electrode layer and (ii) has an opening portion (44a, 44ab, 44as) that exposes the n-type layer at a bottom surface of the at least one n exposure portion (30e, 30eb, 30es); an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer via the insulating layer, the n wiring electrode layer being in contact with the n-type layer in the opening portion (44a, 44ab, 44as); at least one first n connecting member (51, 51b, 51s, 251, 251a, 251b, 351) that is a conductive member for electric connection to an external conductor; a p connecting member (60, 260, 360) in a region of the p wiring electrode layer, the region being exposed from the n wiring electrode layer and the insulating layer; and a void portion (251av, 251bv) between the at least one first n connecting member and the n wiring electrode layer, wherein the at least one first n connecting member is connected to the n wiring electrode layer in at least one first n terminal region (51r, 51rb, 51rs,251ar, 251br, 251r, 351r), in a plan view, the at least one first n terminal region (51r, 51rb, 51rs, 251ar, 251br, 251r, 351r) includes at least a portion of a region above the opening portion (44a, 44ab, 44as), and the n wiring electrode layer and the p-type layer are disposed below the at least one first n terminal region in a cross section parallel to a stacking direction of the semiconductor stack. a semiconductor stack including an n-type layer, a light-emitting layer above the n-type layer, and a p-type layer above the light-emitting layer, the semiconductor stack having at least one n exposure portion (30e, 30eb, 30es) which is a recess at which the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer that (i) continuously covers inner lateral surfaces of the at least one n exposure portion (30e, 30eb, 30es) and part of a top surface the p wiring electrode layer and (ii) has an opening portion (44a, 44ab, 44as) that exposes the n-type layer at a bottom surface of the at least one n exposure portion (30e, 30eb, 30es); an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer via the insulating layer, the n wiring electrode layer being in contact with the n-type layer in the opening portion (44a, 44ab, 44as); at least one first n connecting member (51, 51b, 51s, 251, 251a, 251b, 351) that is a conductive member for electric connection to an external conductor; a p connecting member (60, 260, 360) in a region of the p wiring electrode layer, the region being exposed from the n wiring electrode layer and the insulating layer; and a void portion (251av, 251bv) between the at least one first n connecting member and the n wiring electrode layer, wherein the at least one first n connecting member is connected to the n wiring electrode layer in at least one first n terminal region (51r, 51rb, 51rs,251ar, 251br, 251r, 351r), in a plan view, the at least one first n terminal region (51r, 51rb, 51rs, 251ar, 251br, 251r, 351r) includes at least a portion of a region above the opening portion (44a, 44ab, 44as), and the n wiring electrode layer and the p-type layer are disposed below the at least one first n terminal region in a cross section parallel to a stacking direction of the semiconductor stack.