A signal conversion system for converting an input signal (1, 1105) to a pulse width modulated, PWM, output signal (125, 125a, 125b, 925b) comprising: a clock source for generating and/or means for accepting a clock signal (3, 3b); a carrier generator configured to generate a carrier signal (225, 245, 1115) with a carrier signal frequency; a sample rate converter comprising: a counter configured to generate a count-disparity signal from the clock signal (3, 3b) and the input signal (1, 1105); a first sigma delta unit configured to calculate a temporal correction value from the count disparity signal; a resampled clock generator configured to generate one or more resampled clock signals from the temporal correction value; and a second sigma delta unit configured to generate a resampled signal (150, 450) from one or more of the resampled clock signals and the input signal (1, 1105); a cross-point section, CPS, block (210, 230, 1120) comprising a CPS comparator to compare the carrier signal (225, 245, 1115) to the input signal (1, 1105) or a signal derived from the input signal (1, 1105) to produce a triggered signal (215, 235, 1125) based on the comparison and the input signal (1, 1105) or the signal derived from the input signal (1, 1105); a noise shaper (810, 1130) configured to bit depth reduce the triggered signal (215, 235, 1125) to form a truncated signal; and a PWM comparator configured to compare the truncated signal and/or a signal generated from the truncated signal with the carrier signal (225, 245, 1115) to produce the PWM output signal (125, 125a, 125b, 925b). a clock source for generating and/or means for accepting a clock signal (3, 3b); a carrier generator configured to generate a carrier signal (225, 245, 1115) with a carrier signal frequency; a sample rate converter comprising: a counter configured to generate a count-disparity signal from the clock signal (3, 3b) and the input signal (1, 1105); a first sigma delta unit configured to calculate a temporal correction value from the count disparity signal; a resampled clock generator configured to generate one or more resampled clock signals from the temporal correction value; and a second sigma delta unit configured to generate a resampled signal (150, 450) from one or more of the resampled clock signals and the input signal (1, 1105); a counter configured to generate a count-disparity signal from the clock signal (3, 3b) and the input signal (1, 1105); a first sigma delta unit configured to calculate a temporal correction value from the count disparity signal; a resampled clock generator configured to generate one or more resampled clock signals from the temporal correction value; and a second sigma delta unit configured to generate a resampled signal (150, 450) from one or more of the resampled clock signals and the input signal (1, 1105); a cross-point section, CPS, block (210, 230, 1120) comprising a CPS comparator to compare the carrier signal (225, 245, 1115) to the input signal (1, 1105) or a signal derived from the input signal (1, 1105) to produce a triggered signal (215, 235, 1125) based on the comparison and the input signal (1, 1105) or the signal derived from the input signal (1, 1105); a noise shaper (810, 1130) configured to bit depth reduce the triggered signal (215, 235, 1125) to form a truncated signal; and a PWM comparator configured to compare the truncated signal and/or a signal generated from the truncated signal with the carrier signal (225, 245, 1115) to produce the PWM output signal (125, 125a, 125b, 925b).