A three-dimensional memory device, comprising: a memory stack comprising interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack; a plurality of channel structures extending vertically through the memory stack into the substrate, the plurality of channel structures and the plurality of conductor layers intersecting with one another and forming a plurality of memory cells; at least one slit structure (123, 124) extending vertically and laterally in the memory stack and dividing the plurality of memory cells into at least one memory block, the at least one slit structure (123, 124) each comprising a plurality of slit openings and a support structure between adjacent slit openings, the support structure being in contact with adjacent memory blocks and contacting the substrate; and a source structure comprising an insulating spacer (136, 137) in each of the plurality of slit openings and a source contact (125, 126) in the respective insulating spacer, wherein the support structure extends vertically through the memory stack to the substrate and is insulated from adjacent source contacts (125, 126) by respective insulating spacers of the adjacent source contacts (125, 126), wherein the support structure comprises a dividing structure; the dividing structure extends laterally to connect the adjacent memory blocks and the interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks, characterized in that the dividing structure extends vertically into a first insulating layer of the memory stack, the dividing structure is over an interleaved plurality of conductor portions and a plurality of insulating portions and a bottom surface of dividing structure is between a top surface and a bottom surface of top insulating layer, wherein the support structure divides the source structure into a plurality of disconnected source contacts (125, 126) each in the respective insulating spacer (136, 137), wherein a width of the dividing structure along another lateral direction, perpendicular to the lateral direction along which the at least one slit structure extends, is greater than a width of each of the adjacent slit openings along said another lateral direction. a memory stack comprising interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack; a plurality of channel structures extending vertically through the memory stack into the substrate, the plurality of channel structures and the plurality of conductor layers intersecting with one another and forming a plurality of memory cells; at least one slit structure (123, 124) extending vertically and laterally in the memory stack and dividing the plurality of memory cells into at least one memory block, the at least one slit structure (123, 124) each comprising a plurality of slit openings and a support structure between adjacent slit openings, the support structure being in contact with adjacent memory blocks and contacting the substrate; and a source structure comprising an insulating spacer (136, 137) in each of the plurality of slit openings and a source contact (125, 126) in the respective insulating spacer, wherein the support structure extends vertically through the memory stack to the substrate and is insulated from adjacent source contacts (125, 126) by respective insulating spacers of the adjacent source contacts (125, 126), wherein the support structure comprises a dividing structure; the dividing structure extends laterally to connect the adjacent memory blocks and the interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks, characterized in that the dividing structure extends vertically into a first insulating layer of the memory stack, the dividing structure is over an interleaved plurality of conductor portions and a plurality of insulating portions and a bottom surface of dividing structure is between a top surface and a bottom surface of top insulating layer, wherein the support structure divides the source structure into a plurality of disconnected source contacts (125, 126) each in the respective insulating spacer (136, 137), wherein a width of the dividing structure along another lateral direction, perpendicular to the lateral direction along which the at least one slit structure extends, is greater than a width of each of the adjacent slit openings along said another lateral direction.