A flip-flop (FF101, FF102, FF103, FF104, FF105) comprising: a first transistor (p1, p3, P1, P3) which is a P channel transistor; a second transistor (n1, n3, N1, N3) which is an N channel transistor; a third transistor (p2, p4, P2, P4) which is a P channel transistor; a fourth transistor (n2, n4, N2, N4) which is an N channel transistor; a plurality of input terminals (R, RB, S, SB, INIT, INITB) receiving respective input signals of the flip-flop, each of said input signals having a temporal change (FF101, FF102, FF103, FF104, FF105); a first output terminal; a second output terminal; and the first transistor (p1, p3, P1, P3) and the second transistor (n1, n3, N1, N3) constituting a first CMOS circuit such that their gate terminals are connected to each other and their drain terminals are connected to each other, the third transistor (p2, p4, P2, P4) and the fourth transistor (n2, n4, N2, N4) constituting a second CMOS circuit such that their gate terminals are connected to each other and their drain terminals are connected to each other, the first output terminal being connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal being connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, one of the first transistor, the second transistor, the third transistor, and the fourth transistor is a first input transistor, said first input transistor has its source terminal connected to a first one of the plurality of input terminals (R, RB, S, SB, INIT, INITB), characterized in that the other one of the first transistor, the second transistor, the third transistor, and the fourth transistor, having the same channel polarity as the first input transistor, has its source terminal connected to either one of a second one of the plurality of input terminals (R, RB, S, SB, INIT, INITB), being different from the first one of the plurality of input terminals, or an electric potential of a power source (VDD; VSS). a first transistor (p1, p3, P1, P3) which is a P channel transistor; a second transistor (n1, n3, N1, N3) which is an N channel transistor; a third transistor (p2, p4, P2, P4) which is a P channel transistor; a fourth transistor (n2, n4, N2, N4) which is an N channel transistor; a plurality of input terminals (R, RB, S, SB, INIT, INITB) receiving respective input signals of the flip-flop, each of said input signals having a temporal change (FF101, FF102, FF103, FF104, FF105); a first output terminal; a second output terminal; and the first transistor (p1, p3, P1, P3) and the second transistor (n1, n3, N1, N3) constituting a first CMOS circuit such that their gate terminals are connected to each other and their drain terminals are connected to each other, the third transistor (p2, p4, P2, P4) and the fourth transistor (n2, n4, N2, N4) constituting a second CMOS circuit such that their gate terminals are connected to each other and their drain terminals are connected to each other, the first output terminal being connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal being connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, one of the first transistor, the second transistor, the third transistor, and the fourth transistor is a first input transistor, said first input transistor has its source terminal connected to a first one of the plurality of input terminals (R, RB, S, SB, INIT, INITB), characterized in that the other one of the first transistor, the second transistor, the third transistor, and the fourth transistor, having the same channel polarity as the first input transistor, has its source terminal connected to either one of a second one of the plurality of input terminals (R, RB, S, SB, INIT, INITB), being different from the first one of the plurality of input terminals, or an electric potential of a power source (VDD; VSS).