A controller configured to control at least three electronically commutated brushless motors, the controller comprising a control unit and a power unit, the power unit comprising: a motor phase current sampler operable to provide, to the control unit, motor phase current samples from motor phase currents of each one of the motors; a motor position encoder operable to provide, to the control unit, encoded motor position data for angular positions of the motors; and a plurality of drivers, each driver being operable to generate commutation signals, on the basis of respective motor driving current signals, the control unit comprising: a digital signal processor, DSP, and a field programmable gate array, FPGA, having an input memory mapped to the DSP, the DSP being operable to determine motor repositioning signals, on the basis of a received motor position demand signal describing demanded motor positions and the encoded motor position data, and to load the motor repositioning signals into the input memory of the FPGA, and the FPGA being operable to execute a Field Oriented Control FOC current control algorithm by converting the motor repositioning signals generated by the DSP into information from which the motor driving current signals can be derived, and generate the motor driving current signals for driving said motors into said demanded motor positions, on the basis of the motor repositioning signals and the motor phase current samples, and to output said motor driving current signals to the power unit; characterized in that the FPGA is operable to establish a respective process for the generation of motor driving current signals for each controlled motor, the FPGA further comprising a state machine operable to switch between processes per motor. the power unit comprising: a motor phase current sampler operable to provide, to the control unit, motor phase current samples from motor phase currents of each one of the motors; a motor position encoder operable to provide, to the control unit, encoded motor position data for angular positions of the motors; and a plurality of drivers, each driver being operable to generate commutation signals, on the basis of respective motor driving current signals, a motor phase current sampler operable to provide, to the control unit, motor phase current samples from motor phase currents of each one of the motors; a motor position encoder operable to provide, to the control unit, encoded motor position data for angular positions of the motors; and a plurality of drivers, each driver being operable to generate commutation signals, on the basis of respective motor driving current signals, the control unit comprising: a digital signal processor, DSP, and a field programmable gate array, FPGA, having an input memory mapped to the DSP, the DSP being operable to determine motor repositioning signals, on the basis of a received motor position demand signal describing demanded motor positions and the encoded motor position data, and to load the motor repositioning signals into the input memory of the FPGA, and the FPGA being operable to execute a Field Oriented Control FOC current control algorithm by converting the motor repositioning signals generated by the DSP into information from which the motor driving current signals can be derived, and generate the motor driving current signals for driving said motors into said demanded motor positions, on the basis of the motor repositioning signals and the motor phase current samples, and to output said motor driving current signals to the power unit; characterized in that the FPGA is operable to establish a respective process for the generation of motor driving current signals for each controlled motor, the FPGA further comprising a state machine operable to switch between processes per motor. a digital signal processor, DSP, and a field programmable gate array, FPGA, having an input memory mapped to the DSP, the DSP being operable to determine motor repositioning signals, on the basis of a received motor position demand signal describing demanded motor positions and the encoded motor position data, and to load the motor repositioning signals into the input memory of the FPGA, and the FPGA being operable to execute a Field Oriented Control FOC current control algorithm by converting the motor repositioning signals generated by the DSP into information from which the motor driving current signals can be derived, and generate the motor driving current signals for driving said motors into said demanded motor positions, on the basis of the motor repositioning signals and the motor phase current samples, and to output said motor driving current signals to the power unit; characterized in that the FPGA is operable to establish a respective process for the generation of motor driving current signals for each controlled motor, the FPGA further comprising a state machine operable to switch between processes per motor.