A phase locked loop comprising: a phase detector configured to determine a phase difference between a reference signal and a feedback signal based on an output signal; a loop filter configured to perform a filtering operation on a first signal derived from the phase difference and to provide a first, second and third control signals therefrom; a frequency controlled oscillator configured to receive the control signals (PVT, TR, ACQ) and provide the output signal with a frequency that varies according to the control signals; and a lock detector, including: a phase lock detector configured to receive the first signal derived from the phase detector, and to derive a phase lock signal from the first signal, the phase lock signal indicating whether the phase locked loop is in phase lock, wherein the phase lock detector comprises: a first comparator configured to receive the first signal and to provide a first comparator output signal indicating whether the magnitude of the first signal exceeds a first threshold value; and a first timer configured to receive the first comparator output signal, and to provide a first timer output indicating whether the first comparator output signal has indicated that the magnitude of the first signal did not exceed the first threshold value for a first period; and a frequency lock detector configured to receive the second control signal from the loop filter, and to derive a frequency lock signal from the second control signal, the frequency lock signal indicating whether the phase locked loop is in frequency lock. a phase detector configured to determine a phase difference between a reference signal and a feedback signal based on an output signal; a loop filter configured to perform a filtering operation on a first signal derived from the phase difference and to provide a first, second and third control signals therefrom; a frequency controlled oscillator configured to receive the control signals (PVT, TR, ACQ) and provide the output signal with a frequency that varies according to the control signals; and a lock detector, including: a phase lock detector configured to receive the first signal derived from the phase detector, and to derive a phase lock signal from the first signal, the phase lock signal indicating whether the phase locked loop is in phase lock, wherein the phase lock detector comprises: a first comparator configured to receive the first signal and to provide a first comparator output signal indicating whether the magnitude of the first signal exceeds a first threshold value; and a first timer configured to receive the first comparator output signal, and to provide a first timer output indicating whether the first comparator output signal has indicated that the magnitude of the first signal did not exceed the first threshold value for a first period; and a frequency lock detector configured to receive the second control signal from the loop filter, and to derive a frequency lock signal from the second control signal, the frequency lock signal indicating whether the phase locked loop is in frequency lock. a phase lock detector configured to receive the first signal derived from the phase detector, and to derive a phase lock signal from the first signal, the phase lock signal indicating whether the phase locked loop is in phase lock, wherein the phase lock detector comprises: a first comparator configured to receive the first signal and to provide a first comparator output signal indicating whether the magnitude of the first signal exceeds a first threshold value; and a first timer configured to receive the first comparator output signal, and to provide a first timer output indicating whether the first comparator output signal has indicated that the magnitude of the first signal did not exceed the first threshold value for a first period; and a first comparator configured to receive the first signal and to provide a first comparator output signal indicating whether the magnitude of the first signal exceeds a first threshold value; and a first timer configured to receive the first comparator output signal, and to provide a first timer output indicating whether the first comparator output signal has indicated that the magnitude of the first signal did not exceed the first threshold value for a first period; and a frequency lock detector configured to receive the second control signal from the loop filter, and to derive a frequency lock signal from the second control signal, the frequency lock signal indicating whether the phase locked loop is in frequency lock.