A processor (100, 705, 1000, 1100, 1200) comprising a plurality of block-based processor cores implementing a block-based process instruction set architecture for executing a program comprising a plurality of instruction blocks wherein the plurality of block-based processor cores are connected to each other via a core interconnect, each block-based processor core (111, 720, 800, 1020, 1120, 1220) comprising: an instruction pipeline comprising fetch, decode and execute stages; a plurality of sharable memory resources (820, 830, 880); and state access logic, the state access logic comprising one or more programmable control registers (900, 920) comprising a composition control register and a composition topological register for configuring a first resource of the plurality of sharable memory resources to be powered up and enabled for sharing with other processor cores of the plurality of processor cores and a second resource of the plurality of shareable resources to be powered down while the first resource is enabled for sharing, the one or more programmable control registers (900, 920) being programmable during execution of the program; wherein: the composition control register comprises a master control register field comprising a number of bits that indicate which resources of the respective core of the processor, including the first resource, are to be shared among the respective core of the processor and a group of processor cores of the plurality of processor cores; and the composition topological register specifies which processor cores are part of the group of processor cores. an instruction pipeline comprising fetch, decode and execute stages; a plurality of sharable memory resources (820, 830, 880); and state access logic, the state access logic comprising one or more programmable control registers (900, 920) comprising a composition control register and a composition topological register for configuring a first resource of the plurality of sharable memory resources to be powered up and enabled for sharing with other processor cores of the plurality of processor cores and a second resource of the plurality of shareable resources to be powered down while the first resource is enabled for sharing, the one or more programmable control registers (900, 920) being programmable during execution of the program; wherein: the composition control register comprises a master control register field comprising a number of bits that indicate which resources of the respective core of the processor, including the first resource, are to be shared among the respective core of the processor and a group of processor cores of the plurality of processor cores; and the composition topological register specifies which processor cores are part of the group of processor cores. the composition control register comprises a master control register field comprising a number of bits that indicate which resources of the respective core of the processor, including the first resource, are to be shared among the respective core of the processor and a group of processor cores of the plurality of processor cores; and the composition topological register specifies which processor cores are part of the group of processor cores.