A logic switching device comprising: a channel; a source and a drain both connected to the channel; a gate electrode arranged to face the channel; and a domain switching layer between the channel and the gate electrode, wherein the domain switching layer is a non-memory element and comprises at least one structure including at least one ferroelectric material region comprising a ferroelectric domain and at least one anti-ferroelectric material region comprising an anti-ferroelectric domain, wherein: the at least one ferroelectric material region and the at least one anti-ferroelectric material region arranged alternately in a direction parallel or perpendicular to a bottom surface plane of the gate electrode; or wherein the domain switching layer comprises two structures, a first structure including the at least one ferroelectric material region and the at least one anti-ferroelectric material region arranged alternately in the direction parallel to the bottom surface plane of the gate electrode and a second structure including at least one ferroelectric material region and at least one anti-ferroelectric material region arranged alternately in the direction perpendicular to the bottom surface plane of the gate electrode, wherein the at least one ferroelectric material region is in contact with the at least one anti-ferroelectric material region, and wherein the domain switching layer has a non-hysteretic behavior characteristic at a polarization change according to an external electric field, wherein capacitance matching using the at least one ferroelectric material region and the at least one anti-ferroelectric material region results in the non-hysteretic behavior characteristic, the capacitance matching performed by selecting a volume ratio of the at least one ferroelectric material region and the at least one anti-ferroelectric material region formed in the domain switching layer. a channel; a source and a drain both connected to the channel; a gate electrode arranged to face the channel; and a domain switching layer between the channel and the gate electrode, wherein the domain switching layer is a non-memory element and comprises at least one structure including at least one ferroelectric material region comprising a ferroelectric domain and at least one anti-ferroelectric material region comprising an anti-ferroelectric domain, wherein: the at least one ferroelectric material region and the at least one anti-ferroelectric material region arranged alternately in a direction parallel or perpendicular to a bottom surface plane of the gate electrode; or wherein the domain switching layer comprises two structures, a first structure including the at least one ferroelectric material region and the at least one anti-ferroelectric material region arranged alternately in the direction parallel to the bottom surface plane of the gate electrode and a second structure including at least one ferroelectric material region and at least one anti-ferroelectric material region arranged alternately in the direction perpendicular to the bottom surface plane of the gate electrode, the at least one ferroelectric material region and the at least one anti-ferroelectric material region arranged alternately in a direction parallel or perpendicular to a bottom surface plane of the gate electrode; or wherein the domain switching layer comprises two structures, a first structure including the at least one ferroelectric material region and the at least one anti-ferroelectric material region arranged alternately in the direction parallel to the bottom surface plane of the gate electrode and a second structure including at least one ferroelectric material region and at least one anti-ferroelectric material region arranged alternately in the direction perpendicular to the bottom surface plane of the gate electrode, wherein the at least one ferroelectric material region is in contact with the at least one anti-ferroelectric material region, and wherein the domain switching layer has a non-hysteretic behavior characteristic at a polarization change according to an external electric field, wherein capacitance matching using the at least one ferroelectric material region and the at least one anti-ferroelectric material region results in the non-hysteretic behavior characteristic, the capacitance matching performed by selecting a volume ratio of the at least one ferroelectric material region and the at least one anti-ferroelectric material region formed in the domain switching layer.