A circuit for providing voltage level shifting in an integrated circuit, the circuit comprising: an inverter having an input coupled to receive an input signal having a first voltage level (VDDL); an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level (VDDH); wherein the first transistor comprises a first p-channel transistor, and the second transistor comprises a first n-channel transistor; wherein a gate of the second transistor is coupled to an output of the inverter; a third transistor having its source connected to a reference voltage (VDDH) having the second voltage level, and the third transistor having its drain connected to a gate of the first transistor; and a switch comprising a second p-channel transistor and a second n-channel transistor, a source of the second p-channel transistor being coupled to a drain of the second n-channel transistor and a drain of the second p-channel transistor being coupled to a source of the second n-channel transistor, wherein the drain of the second n-channel transistor and the source of the second p-channel transistor are coupled to the gate of the first p-channel transistor, wherein the source of the second n-channel transistor and the drain of the second p-channel transistor are coupled to the gate of the first n-channel transistor, wherein a source of the second n-channel transistor and a drain of the second p-channel transistor are coupled to the gate of the first n-channel transistor, wherein a gate of the second n-channel transistor is coupled to the input of the inverter, wherein the circuit is configured to control a voltage at the gate of the first p-channel transistor during a first phase of a transition of a voltage at the gate of the first p-channel transistor such that, when a signal at the input of the inverter goes low, the voltage at the gate of the first p-channel transistor charges to the first voltage level (VDDL) through the second p-channel transistor, such that the first n-channel transistor is turned on and the first p-channel transistor is turned off. an inverter having an input coupled to receive an input signal having a first voltage level (VDDL); an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level (VDDH); wherein the first transistor comprises a first p-channel transistor, and the second transistor comprises a first n-channel transistor; wherein a gate of the second transistor is coupled to an output of the inverter; a third transistor having its source connected to a reference voltage (VDDH) having the second voltage level, and the third transistor having its drain connected to a gate of the first transistor; and a switch comprising a second p-channel transistor and a second n-channel transistor, a source of the second p-channel transistor being coupled to a drain of the second n-channel transistor and a drain of the second p-channel transistor being coupled to a source of the second n-channel transistor, wherein the drain of the second n-channel transistor and the source of the second p-channel transistor are coupled to the gate of the first p-channel transistor, wherein the source of the second n-channel transistor and the drain of the second p-channel transistor are coupled to the gate of the first n-channel transistor, wherein a source of the second n-channel transistor and a drain of the second p-channel transistor are coupled to the gate of the first n-channel transistor, wherein a gate of the second n-channel transistor is coupled to the input of the inverter, wherein the circuit is configured to control a voltage at the gate of the first p-channel transistor during a first phase of a transition of a voltage at the gate of the first p-channel transistor such that, when a signal at the input of the inverter goes low, the voltage at the gate of the first p-channel transistor charges to the first voltage level (VDDL) through the second p-channel transistor, such that the first n-channel transistor is turned on and the first p-channel transistor is turned off.