A power amplifier (200, 600) comprising: a first switch (M1 a) comprising a first drain terminal (D1 a); a second switch (M1 b) comprising a second drain terminal (D1 b), wherein the first switch and the second switch are configured to receive differential signals corresponding to an input signal having a first harmonic frequency (f H1), a second harmonic frequency (f H2) and a third harmonic frequency (f H3); a second harmonic trap circuitry configured to be coupled to the first drain terminal and the second drain terminal, and configured to have a first impedance between the first drain terminal and a common voltage at f H2, and a second impedance between the first drain terminal and the common voltage at f H3, wherein the first impedance is smaller than the second impedance; a pair of differential output terminals (T 1a, T 1b) coupled to the first and second drain terminal; and a matching network configured to be coupled between the pair of differential output terminals, the matching network having a single-ended output configured to be coupled to a load resistance, wherein the matching network is configured to match the impedance between the pair of differential output terminals and the load resistance, wherein: the matching network comprises a first matching capacitor (Cs) coupled between the single-ended output and a first differential output terminal (T 1a) of the pair of differential output terminals; a second matching capacitor (Cp) coupled between a second differential output terminal (T 1b) of the pair of differential output terminals and a second node (N 2); a first matching inductor (Lp) coupled between the first differential output terminal and the second node; a second matching inductor (Ls) coupled between the second differential output terminal and the single-ended output; a ground network coupled between the ground and the second node, wherein the second node is connected to a terminal of a capacitor and a terminal of an inductor, wherein the ground network is configured to have a first ground network impedance at f H1, and a second ground network impedance at f H3 different from the first ground network impedance, and wherein the second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. a first switch (M1 a) comprising a first drain terminal (D1 a); a second switch (M1 b) comprising a second drain terminal (D1 b), wherein the first switch and the second switch are configured to receive differential signals corresponding to an input signal having a first harmonic frequency (f H1), a second harmonic frequency (f H2) and a third harmonic frequency (f H3); a second harmonic trap circuitry configured to be coupled to the first drain terminal and the second drain terminal, and configured to have a first impedance between the first drain terminal and a common voltage at f H2, and a second impedance between the first drain terminal and the common voltage at f H3, wherein the first impedance is smaller than the second impedance; a pair of differential output terminals (T 1a, T 1b) coupled to the first and second drain terminal; and a matching network configured to be coupled between the pair of differential output terminals, the matching network having a single-ended output configured to be coupled to a load resistance, wherein the matching network is configured to match the impedance between the pair of differential output terminals and the load resistance, wherein: the matching network comprises a first matching capacitor (Cs) coupled between the single-ended output and a first differential output terminal (T 1a) of the pair of differential output terminals; a second matching capacitor (Cp) coupled between a second differential output terminal (T 1b) of the pair of differential output terminals and a second node (N 2); a first matching inductor (Lp) coupled between the first differential output terminal and the second node; a second matching inductor (Ls) coupled between the second differential output terminal and the single-ended output; a ground network coupled between the ground and the second node, wherein the second node is connected to a terminal of a capacitor and a terminal of an inductor, wherein the ground network is configured to have a first ground network impedance at f H1, and a second ground network impedance at f H3 different from the first ground network impedance, and wherein the second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. the matching network comprises a first matching capacitor (Cs) coupled between the single-ended output and a first differential output terminal (T 1a) of the pair of differential output terminals; a second matching capacitor (Cp) coupled between a second differential output terminal (T 1b) of the pair of differential output terminals and a second node (N 2); a first matching inductor (Lp) coupled between the first differential output terminal and the second node; a second matching inductor (Ls) coupled between the second differential output terminal and the single-ended output; a ground network coupled between the ground and the second node, wherein the second node is connected to a terminal of a capacitor and a terminal of an inductor, wherein the ground network is configured to have a first ground network impedance at f H1, and a second ground network impedance at f H3 different from the first ground network impedance, and wherein the second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components.