An amplifier circuit, comprising: a plurality of stacked field-effect, FET, transistors (M1,..., Mn) comprising an input transistor and one or more cascode transistors (M2,..., Mn), the one or more cascode transistors comprising an output transistor (Mn), a drain of the output transistor coupled to a load (Z L, R L) for output of an RF voltage; and one or more compensation networks (Zg2,..., Zgn), each coupled to a gate (G2,..., Gn) of a respective cascode transistor of the one or more cascode transistors; wherein each compensation network comprises: a series-connected resistive-capacitive network and a parallel-connected resistive-inductive network, the series-connected resistive-capacitive network coupled to the gate of the respective cascode transistor, and the parallel-connected resistive-inductive network coupled between a reference ground and the series-connected resistive-capacitive network, wherein the series-connected resistive-capacitive network comprises a resistor (R Sk) in series connection with a capacitor (Ck), wherein the parallel-connected resistive-inductive network comprises a resistor (R pk) connected in parallel with an inductor (Lk), and wherein values of the resistors (R Sk, R pk), the capacitor (Ck) and the inductor (Lk) are selected to provide, in combination with internal elements/parameters of the respective cascode transistor, a value of a real part and a value of an imaginary part of a source impedance (Z Sk) looking into the source of the respective cascode transistor such as to obtain a desired distribution of the RF voltage across the plurality of stacked FET transistors. a plurality of stacked field-effect, FET, transistors (M1,..., Mn) comprising an input transistor and one or more cascode transistors (M2,..., Mn), the one or more cascode transistors comprising an output transistor (Mn), a drain of the output transistor coupled to a load (Z L, R L) for output of an RF voltage; and one or more compensation networks (Zg2,..., Zgn), each coupled to a gate (G2,..., Gn) of a respective cascode transistor of the one or more cascode transistors; wherein each compensation network comprises: a series-connected resistive-capacitive network and a parallel-connected resistive-inductive network, the series-connected resistive-capacitive network coupled to the gate of the respective cascode transistor, and the parallel-connected resistive-inductive network coupled between a reference ground and the series-connected resistive-capacitive network, wherein the series-connected resistive-capacitive network comprises a resistor (R Sk) in series connection with a capacitor (Ck), wherein the parallel-connected resistive-inductive network comprises a resistor (R pk) connected in parallel with an inductor (Lk), and wherein values of the resistors (R Sk, R pk), the capacitor (Ck) and the inductor (Lk) are selected to provide, in combination with internal elements/parameters of the respective cascode transistor, a value of a real part and a value of an imaginary part of a source impedance (Z Sk) looking into the source of the respective cascode transistor such as to obtain a desired distribution of the RF voltage across the plurality of stacked FET transistors.