A method for providing memory atomicity in a data processing system, the method comprising: adding a store buffer entry to an SB in a processor core in a data processing system, in response to execution, by the processor core, of a store instruction that is part of an atomic region of code; retiring the store instruction by a retirement unit in the processor core which makes the SB entry a senior SB entry; and committing the atomic region by committing a transaction comprising the instructions within the atomic region by the retirement unit which makes the SB entry walk enabled allowing the SB entry to be read out by a store pipeline, wherein: the operations of adding the SB entry to the SB, making the SB entry senior, and making the SB entry walk enabled, in response to the retirement unit committing the transaction associated with the atomic region, are performed by low-overhead memory atomicity (LOMA) facilities in the data processing system, the LOMA facilities providing for memory atomicity with low atomicity overhead by using a delayed reclamation technique, wherein the delayed reclamation technique makes execution of memory instructions appear atomic to the external world; characterized in that the method further comprises making an individual SB entry walk enabled, in response to the retirement unit retiring an individual store instruction which corresponds to the individual SB entry; and the operation of making the individual SB entry walk enabled, in response to the retirement unit retiring the individual store instruction which corresponds to the individual SB entry, is performed by robust memory atomicity facilities in the data processing system, the RMA facilities providing for memory atomicity with higher atomicity overhead compared to the LOMA facilities based on a data cache unit. adding a store buffer entry to an SB in a processor core in a data processing system, in response to execution, by the processor core, of a store instruction that is part of an atomic region of code; retiring the store instruction by a retirement unit in the processor core which makes the SB entry a senior SB entry; and committing the atomic region by committing a transaction comprising the instructions within the atomic region by the retirement unit which makes the SB entry walk enabled allowing the SB entry to be read out by a store pipeline, wherein: the operations of adding the SB entry to the SB, making the SB entry senior, and making the SB entry walk enabled, in response to the retirement unit committing the transaction associated with the atomic region, are performed by low-overhead memory atomicity (LOMA) facilities in the data processing system, the LOMA facilities providing for memory atomicity with low atomicity overhead by using a delayed reclamation technique, wherein the delayed reclamation technique makes execution of memory instructions appear atomic to the external world; characterized in that the method further comprises making an individual SB entry walk enabled, in response to the retirement unit retiring an individual store instruction which corresponds to the individual SB entry; and the operation of making the individual SB entry walk enabled, in response to the retirement unit retiring the individual store instruction which corresponds to the individual SB entry, is performed by robust memory atomicity facilities in the data processing system, the RMA facilities providing for memory atomicity with higher atomicity overhead compared to the LOMA facilities based on a data cache unit. the operations of adding the SB entry to the SB, making the SB entry senior, and making the SB entry walk enabled, in response to the retirement unit committing the transaction associated with the atomic region, are performed by low-overhead memory atomicity (LOMA) facilities in the data processing system, the LOMA facilities providing for memory atomicity with low atomicity overhead by using a delayed reclamation technique, wherein the delayed reclamation technique makes execution of memory instructions appear atomic to the external world; characterized in that the method further comprises making an individual SB entry walk enabled, in response to the retirement unit retiring an individual store instruction which corresponds to the individual SB entry; and the operation of making the individual SB entry walk enabled, in response to the retirement unit retiring the individual store instruction which corresponds to the individual SB entry, is performed by robust memory atomicity facilities in the data processing system, the RMA facilities providing for memory atomicity with higher atomicity overhead compared to the LOMA facilities based on a data cache unit.