A method of programming a 3D-NAND flash memory device (100, 500) which includes a plurality of memory cells, a plurality of word lines (WL1, WL2, WL3, WL4), a plurality of bit lines (BL 1 -BL M), a plurality of top select gates and a bottom select gate, the method comprising: performing a first program step on the plurality of memory cells; performing a first verify step on the plurality of memory cells after performing the first program step; performing a preparation step during consecutive first time period, second time period and third time period on the plurality of memory cells after performing the first verify step by: biasing the bottom select gate at ground voltage during first, second and third time periods; ramping a selected bit line and an unselected bit line among the plurality of bit lines (BL 1 -BL M) to a pre-charge voltage (V PRE) during the first time period; ramping a selected word line among the plurality of word lines (WL1, WL2, WL3, WL4)to a third turn-on voltage (V ON3) during the first time period; biasing an unselected word line among the plurality of word lines at a fourth turn-on voltage (V ON4) during the first time period; ramping the selected word line and the unselected word line among the plurality of word lines (WL1, WL2, WL3, WL4) to ground voltage during the second time period; ramping a selected top select gate from a first turn-on voltage (V ON1) to ground voltage during the third time period and an unselected top select gate among the plurality of top select gates from a second turn on voltage (V ON2) to ground voltage during the third time period; biasing the selected top select gate at the first turn-on voltage (V ON1) during the first and second time periods; and performing a second program step on one or multiple memory cells among the plurality of memory cells which fail the first verify step after performing the preparation step. performing a first program step on the plurality of memory cells; performing a first verify step on the plurality of memory cells after performing the first program step; performing a preparation step during consecutive first time period, second time period and third time period on the plurality of memory cells after performing the first verify step by: biasing the bottom select gate at ground voltage during first, second and third time periods; ramping a selected bit line and an unselected bit line among the plurality of bit lines (BL 1 -BL M) to a pre-charge voltage (V PRE) during the first time period; ramping a selected word line among the plurality of word lines (WL1, WL2, WL3, WL4)to a third turn-on voltage (V ON3) during the first time period; biasing an unselected word line among the plurality of word lines at a fourth turn-on voltage (V ON4) during the first time period; ramping the selected word line and the unselected word line among the plurality of word lines (WL1, WL2, WL3, WL4) to ground voltage during the second time period; ramping a selected top select gate from a first turn-on voltage (V ON1) to ground voltage during the third time period and an unselected top select gate among the plurality of top select gates from a second turn on voltage (V ON2) to ground voltage during the third time period; biasing the selected top select gate at the first turn-on voltage (V ON1) during the first and second time periods; and performing a second program step on one or multiple memory cells among the plurality of memory cells which fail the first verify step after performing the preparation step. biasing the bottom select gate at ground voltage during first, second and third time periods; ramping a selected bit line and an unselected bit line among the plurality of bit lines (BL 1 -BL M) to a pre-charge voltage (V PRE) during the first time period; ramping a selected word line among the plurality of word lines (WL1, WL2, WL3, WL4)to a third turn-on voltage (V ON3) during the first time period; biasing an unselected word line among the plurality of word lines at a fourth turn-on voltage (V ON4) during the first time period; ramping the selected word line and the unselected word line among the plurality of word lines (WL1, WL2, WL3, WL4) to ground voltage during the second time period; ramping a selected top select gate from a first turn-on voltage (V ON1) to ground voltage during the third time period and an unselected top select gate among the plurality of top select gates from a second turn on voltage (V ON2) to ground voltage during the third time period; biasing the selected top select gate at the first turn-on voltage (V ON1) during the first and second time periods; and performing a second program step on one or multiple memory cells among the plurality of memory cells which fail the first verify step after performing the preparation step.