A reconfigurable pin-to-pin interface (400, 500, 600, 700) comprising: a plurality of lane circuits (CSIA_DPHY_L0, CSIA_DPHY_L1, CSIA_DPHY_L2, CSIB_DPHY_L0, CSIB_DPHY_L1, and CSIB_DPHY_L2), each arranged to obtain a received signal by receiving an input signal transmitted via a lane, wherein the lane circuits comprise: a first lane circuit, arranged to obtain a first received signal by receiving a first input signal transmitted via a first lane, the first lane circuit having a first output port (CK_OUT) and a first clock input port (CK_IN); and a second lane circuit, arranged to obtain a second received signal by receiving a second input signal transmitted via a second lane, the second lane circuit having a second output port (CK_OUT) and a second clock input port (CK_IN); and a reconfiguration circuit (402, 502, 602, 702) comprising a first switch circuit, wherein the first switch circuit comprises a first internal clock lane (UNI_CK0) and a first plurality of switches (SW01-SW04) each of which has one end coupled to the first internal clock lane (UNI_CK0) and another end respectively coupled to the first output port (CK_OUT), the first clock input port (CK_IN), the second output port (CK_OUT), and the second clock input port (CK_IN), wherein when the second lane is used as one data lane and the first lane is used as one clock lane, the first received signal is a clock signal and the first plurality of switches (SW01-SW04) are switched to redirect the first received signal from the first output port (CK_OUT) of the first lane circuit (CSIA_DPHY_L0) to the second clock input port (CK_IN) of the second lane circuit (CSIA_DPHY_L1) for acting as a clock input of the second lane circuit (CSIA_DPHY_L1), and wherein when the first lane is used as one data lane, the first received signal is a data signal and the plurality of switches (SW01-SW04) are switched to block the first received signal from being redirected from the first output port (CK_OUT) of the first lane circuit (CSIA_DPHY_L0) to the second clock input port (CK_IN) of the second lane circuit (CSIA_DPHY_L1) for acting as the clock input of the second lane circuit (CSIA_DPHY_L1). a plurality of lane circuits (CSIA_DPHY_L0, CSIA_DPHY_L1, CSIA_DPHY_L2, CSIB_DPHY_L0, CSIB_DPHY_L1, and CSIB_DPHY_L2), each arranged to obtain a received signal by receiving an input signal transmitted via a lane, wherein the lane circuits comprise: a first lane circuit, arranged to obtain a first received signal by receiving a first input signal transmitted via a first lane, the first lane circuit having a first output port (CK_OUT) and a first clock input port (CK_IN); and a second lane circuit, arranged to obtain a second received signal by receiving a second input signal transmitted via a second lane, the second lane circuit having a second output port (CK_OUT) and a second clock input port (CK_IN); and a first lane circuit, arranged to obtain a first received signal by receiving a first input signal transmitted via a first lane, the first lane circuit having a first output port (CK_OUT) and a first clock input port (CK_IN); and a second lane circuit, arranged to obtain a second received signal by receiving a second input signal transmitted via a second lane, the second lane circuit having a second output port (CK_OUT) and a second clock input port (CK_IN); and a reconfiguration circuit (402, 502, 602, 702) comprising a first switch circuit, wherein the first switch circuit comprises a first internal clock lane (UNI_CK0) and a first plurality of switches (SW01-SW04) each of which has one end coupled to the first internal clock lane (UNI_CK0) and another end respectively coupled to the first output port (CK_OUT), the first clock input port (CK_IN), the second output port (CK_OUT), and the second clock input port (CK_IN), wherein when the second lane is used as one data lane and the first lane is used as one clock lane, the first received signal is a clock signal and the first plurality of switches (SW01-SW04) are switched to redirect the first received signal from the first output port (CK_OUT) of the first lane circuit (CSIA_DPHY_L0) to the second clock input port (CK_IN) of the second lane circuit (CSIA_DPHY_L1) for acting as a clock input of the second lane circuit (CSIA_DPHY_L1), and wherein when the first lane is used as one data lane, the first received signal is a data signal and the plurality of switches (SW01-SW04) are switched to block the first received signal from being redirected from the first output port (CK_OUT) of the first lane circuit (CSIA_DPHY_L0) to the second clock input port (CK_IN) of the second lane circuit (CSIA_DPHY_L1) for acting as the clock input of the second lane circuit (CSIA_DPHY_L1).