A solid-state imaging device (1,1A) comprising: a pixel array unit (10,10A) including a plurality of pixel units arrayed at least in a first direction and each including a photodiode and an amplification MOS transistor, and for outputting a signal according to an amount of charges generated in the photodiode in each of the plurality of pixel units to, among a plurality of signal lines (L(n)), a signal line (L(n)) provided corresponding to the pixel unit; a current source array unit including a plurality of current sources, each of the plurality of current sources being connected to the corresponding pixel unit among the plurality of pixel units via the signal line (L(n)); and a signal readout unit for inputting signals input via the plurality of signal lines (L(n)), and sequentially reading out the signals according to the amounts of charges generated in the photodiodes in the plurality of pixel units; wherein in the pixel unit, the amplification MOS transistor is provided between a first reference potential supply line (Vr) extending in the first direction and the signal line (L(n)), a voltage according to the amount of charges generated in the photodiode is applied to a gate of the amplification MOS transistor, and a signal according to the gate voltage is output from the amplification MOS transistor to the signal line (L(n)), and each of one or more specific current sources included in the plurality of current sources includes: a first MOS transistor provided between a second reference potential supply terminal and a common node (Nc) and having a gate to which a first bias voltage (Vbias1) is applied; a second MOS transistor provided between the common node (Nc) and the signal line (L(n)) and having a gate to which a second bias voltage (Vbias2) is applied; a third MOS transistor provided between the first reference potential supply line (Vr) at a same position along the first reference potential supply line as the amplification MOS transistor, and the common node; and a setting circuit for applying a gate voltage according to a voltage of the signal line (L(n)) to a gate of the third MOS transistor to set ON/OFF of the third MOS transistor, and suppressing fluctuations in an amount of current flowing from the first reference potential supply line (Vr) to the second reference potential supply terminal via the first MOS transistor and the common node. a pixel array unit (10,10A) including a plurality of pixel units arrayed at least in a first direction and each including a photodiode and an amplification MOS transistor, and for outputting a signal according to an amount of charges generated in the photodiode in each of the plurality of pixel units to, among a plurality of signal lines (L(n)), a signal line (L(n)) provided corresponding to the pixel unit; a current source array unit including a plurality of current sources, each of the plurality of current sources being connected to the corresponding pixel unit among the plurality of pixel units via the signal line (L(n)); and a signal readout unit for inputting signals input via the plurality of signal lines (L(n)), and sequentially reading out the signals according to the amounts of charges generated in the photodiodes in the plurality of pixel units; wherein in the pixel unit, the amplification MOS transistor is provided between a first reference potential supply line (Vr) extending in the first direction and the signal line (L(n)), a voltage according to the amount of charges generated in the photodiode is applied to a gate of the amplification MOS transistor, and a signal according to the gate voltage is output from the amplification MOS transistor to the signal line (L(n)), and each of one or more specific current sources included in the plurality of current sources includes: a first MOS transistor provided between a second reference potential supply terminal and a common node (Nc) and having a gate to which a first bias voltage (Vbias1) is applied; a second MOS transistor provided between the common node (Nc) and the signal line (L(n)) and having a gate to which a second bias voltage (Vbias2) is applied; a third MOS transistor provided between the first reference potential supply line (Vr) at a same position along the first reference potential supply line as the amplification MOS transistor, and the common node; and a setting circuit for applying a gate voltage according to a voltage of the signal line (L(n)) to a gate of the third MOS transistor to set ON/OFF of the third MOS transistor, and suppressing fluctuations in an amount of current flowing from the first reference potential supply line (Vr) to the second reference potential supply terminal via the first MOS transistor and the common node. a first MOS transistor provided between a second reference potential supply terminal and a common node (Nc) and having a gate to which a first bias voltage (Vbias1) is applied; a second MOS transistor provided between the common node (Nc) and the signal line (L(n)) and having a gate to which a second bias voltage (Vbias2) is applied; a third MOS transistor provided between the first reference potential supply line (Vr) at a same position along the first reference potential supply line as the amplification MOS transistor, and the common node; and a setting circuit for applying a gate voltage according to a voltage of the signal line (L(n)) to a gate of the third MOS transistor to set ON/OFF of the third MOS transistor, and suppressing fluctuations in an amount of current flowing from the first reference potential supply line (Vr) to the second reference potential supply terminal via the first MOS transistor and the common node.