A method for driving a resonant converter comprising: - a primary switching circuit having at least a primary winding and a primary full-bridge switching stage (M1, M2, M3, M4), which is configured for driving said primary winding, and a resonance inductor (Lres) in series with the primary winding, the full-bridge switching stage (M1, M2, M3, M4) including an upper switching half-bridge (M1, M2) and a lower switching half-bridge (M3, M4), - a secondary resonant circuit having a secondary winding magnetically coupled to the primary winding, and a resonance capacitor (Cres) electrically connected in parallel to the secondary winding, - a secondary rectification stage electrically connected in parallel to the resonance capacitor (Cres), and - a driving module, configured for: - receiving at input a signal (PHX, PHY) representing the voltage measured at a common node of the pair of switches of the upper switching half-bridge (M1, M2) or the lower switching half-bridge (M3, M4), - detecting the presence of a negative voltage in the signal (PHX, PHY) representing the voltage measured at said common node of the pair of switches of said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4), - at each cycle anticipating (Tshift_nom) the control signal (PWMY_OUT, PWMX_OUT) for control of the switches of the lower switching half-bridge (M3, M4) or upper switching half-bridge (M1, M2), that is to be activated at the next switching cycle, by a shift time (Tshift) that is reduced (δtshift) at each cycle until (Tshift_targ) the condition of absence of negative voltage in the signal (PHX, PHY) representing the voltage measured at said common node of the pair of switches of said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4) is satisfied. - a primary switching circuit having at least a primary winding and a primary full-bridge switching stage (M1, M2, M3, M4), which is configured for driving said primary winding, and a resonance inductor (Lres) in series with the primary winding, the full-bridge switching stage (M1, M2, M3, M4) including an upper switching half-bridge (M1, M2) and a lower switching half-bridge (M3, M4), - a secondary resonant circuit having a secondary winding magnetically coupled to the primary winding, and a resonance capacitor (Cres) electrically connected in parallel to the secondary winding, - a secondary rectification stage electrically connected in parallel to the resonance capacitor (Cres), and - a driving module, configured for: - receiving at input a signal (PHX, PHY) representing the voltage measured at a common node of the pair of switches of the upper switching half-bridge (M1, M2) or the lower switching half-bridge (M3, M4), - detecting the presence of a negative voltage in the signal (PHX, PHY) representing the voltage measured at said common node of the pair of switches of said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4), - at each cycle anticipating (Tshift_nom) the control signal (PWMY_OUT, PWMX_OUT) for control of the switches of the lower switching half-bridge (M3, M4) or upper switching half-bridge (M1, M2), that is to be activated at the next switching cycle, by a shift time (Tshift) that is reduced (δtshift) at each cycle until (Tshift_targ) the condition of absence of negative voltage in the signal (PHX, PHY) representing the voltage measured at said common node of the pair of switches of said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4) is satisfied. - receiving at input a signal (PHX, PHY) representing the voltage measured at a common node of the pair of switches of the upper switching half-bridge (M1, M2) or the lower switching half-bridge (M3, M4), - detecting the presence of a negative voltage in the signal (PHX, PHY) representing the voltage measured at said common node of the pair of switches of said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4), - at each cycle anticipating (Tshift_nom) the control signal (PWMY_OUT, PWMX_OUT) for control of the switches of the lower switching half-bridge (M3, M4) or upper switching half-bridge (M1, M2), that is to be activated at the next switching cycle, by a shift time (Tshift) that is reduced (δtshift) at each cycle until (Tshift_targ) the condition of absence of negative voltage in the signal (PHX, PHY) representing the voltage measured at said common node of the pair of switches of said upper switching half-bridge (M1, M2) or said lower switching half-bridge (M3, M4) is satisfied.