A power consumption control circuit comprising: a detection means (6, 7, 8) configured to detect the presence or absence of an input of a digital input signal, during a first period of time; a signal delay means configured to delay said digital input signal by a second period of time which is equivalent to said first period of time, and to output the delayed signal; a digital-analog conversion means configured to convert said delayed signal into an analog signal, and to output the analog signal; an amplification device configured to generate an amplification action when a bias is applied to it; and a bias control means configured to apply said bias to said amplification device, on the basis of a detection result obtained by said detection means; wherein either said amplification device is a field effect transistor and said bias is configured to be applied to a gate terminal of said field effect transistor; or said amplification device is a bipolar transistor and said bias is configured to be applied to a base terminal of said bipolar transistor; wherein said bias control means is configured to start said bias application when the presence of an input of said digital input signal is detected by said detection means, and to suspend said bias application when the absence of an input of said digital input signal is detected by said detection means, and wherein said detection means is configured to perform a detection a plurality of times, and said bias control means is configured to start said bias application when the presence of an input of said digital input signal is detected a first number of times successively by said detection means, and said bias control means is configured to suspend said bias application when the absence of an input of said digital input signal is detected a second number of times successively by said detection means. a detection means (6, 7, 8) configured to detect the presence or absence of an input of a digital input signal, during a first period of time; a signal delay means configured to delay said digital input signal by a second period of time which is equivalent to said first period of time, and to output the delayed signal; a digital-analog conversion means configured to convert said delayed signal into an analog signal, and to output the analog signal; an amplification device configured to generate an amplification action when a bias is applied to it; and a bias control means configured to apply said bias to said amplification device, on the basis of a detection result obtained by said detection means; wherein either said amplification device is a field effect transistor and said bias is configured to be applied to a gate terminal of said field effect transistor; or said amplification device is a bipolar transistor and said bias is configured to be applied to a base terminal of said bipolar transistor; wherein said bias control means is configured to start said bias application when the presence of an input of said digital input signal is detected by said detection means, and to suspend said bias application when the absence of an input of said digital input signal is detected by said detection means, and wherein said detection means is configured to perform a detection a plurality of times, and said bias control means is configured to start said bias application when the presence of an input of said digital input signal is detected a first number of times successively by said detection means, and said bias control means is configured to suspend said bias application when the absence of an input of said digital input signal is detected a second number of times successively by said detection means.