A memory device, comprising: a silicon semiconductor substrate; spaced apart source and drain regions (12, 14) formed in the silicon semiconductor substrate with a channel region there between; a conductive floating gate disposed over and insulated from a first portion of the channel region and a first portion of the source region, wherein the floating gate includes lower and upper surface and an inwardly slanted sidewall terminating at the upper surface in a sharp edge such that a width of the floating gate at the lower surface is less than a width of the floating gate at the upper surface; a conductive erase gate that includes: a first portion that is laterally adjacent to and insulated from the floating gate, and is over and insulated from the source region, and a second portion that extends up and over, and is insulated from, the floating gate, wherein the second portion of the erase gate wraps around the sharp edge, and wherein a tunneling oxide layer is positioned between the floating gate and the second portion of the erase gate so that the tunneling oxide is protected; a conductive word line gate disposed over and insulated from a second portion of the channel region, wherein the word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate; wherein a thickness of insulation separating the word line gate from the second portion of the channel region is less than a thickness of insulation separating the floating gate from the erase gate; wherein the erase gate is the only conductive gate disposed over the floating gate and the erase gate second portion among the first portion of the erase gate and the second portion of the erase gate is the only gate portion disposed over the floating gate; wherein the word line gate comprises: a bottom surface facing the second portion of the channel region, wherein the bottom surface is planar, and a top surface opposite the bottom surface, wherein the top surface is planar; wherein the erase gate comprises: a second bottom surface facing the source region; and a second top surface opposite the second bottom surface that is planar. a silicon semiconductor substrate; spaced apart source and drain regions (12, 14) formed in the silicon semiconductor substrate with a channel region there between; a conductive floating gate disposed over and insulated from a first portion of the channel region and a first portion of the source region, wherein the floating gate includes lower and upper surface and an inwardly slanted sidewall terminating at the upper surface in a sharp edge such that a width of the floating gate at the lower surface is less than a width of the floating gate at the upper surface; a conductive erase gate that includes: a first portion that is laterally adjacent to and insulated from the floating gate, and is over and insulated from the source region, and a second portion that extends up and over, and is insulated from, the floating gate, wherein the second portion of the erase gate wraps around the sharp edge, and wherein a tunneling oxide layer is positioned between the floating gate and the second portion of the erase gate so that the tunneling oxide is protected; a first portion that is laterally adjacent to and insulated from the floating gate, and is over and insulated from the source region, and a second portion that extends up and over, and is insulated from, the floating gate, wherein the second portion of the erase gate wraps around the sharp edge, and wherein a tunneling oxide layer is positioned between the floating gate and the second portion of the erase gate so that the tunneling oxide is protected; a conductive word line gate disposed over and insulated from a second portion of the channel region, wherein the word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate; wherein a thickness of insulation separating the word line gate from the second portion of the channel region is less than a thickness of insulation separating the floating gate from the erase gate; wherein the erase gate is the only conductive gate disposed over the floating gate and the erase gate second portion among the first portion of the erase gate and the second portion of the erase gate is the only gate portion disposed over the floating gate; wherein the word line gate comprises: a bottom surface facing the second portion of the channel region, wherein the bottom surface is planar, and a top surface opposite the bottom surface, wherein the top surface is planar; a bottom surface facing the second portion of the channel region, wherein the bottom surface is planar, and a top surface opposite the bottom surface, wherein the top surface is planar; wherein the erase gate comprises: a second bottom surface facing the source region; and a second top surface opposite the second bottom surface that is planar. a second bottom surface facing the source region; and a second top surface opposite the second bottom surface that is planar.