A circuit for driving a load, the circuit comprising: an input driver; a first signal path portion that is a portion of a first signal path from the input driver to the load; a second signal path portion that is a portion of a second signal path from the input driver to the load; a first clock path portion configured to provide a first clock signal to control a timing of the first signal path portion; a second clock path portion configured to provide a second clock signal to control a timing of the second signal path portion; and control circuitry configured to: control the first clock path portion to form a first ring oscillator with a first controllable delay element during a first time period and sense a first cadence of the first ring oscillator; control the second clock path portion to form a second ring oscillator with a second controllable delay element during a second time period and sense a second cadence of the second ring oscillator; sense a first delay introduced by the first controllable delay element and sense a second delay introduced by the second delay element at least partially based on the first cadence and the second cadence, respectively, and compute a difference between the first and second delays; control the first and second delays such that said difference substantially matches a delay mismatch between a delay introduced by the first signal path and a delay introduced by the second signal path; wherein the input driver is configured to drive the first signal path portion with a first signal and drive the second signal path portion with a second signal after the circuit is controlled to control said first and second delays. an input driver; a first signal path portion that is a portion of a first signal path from the input driver to the load; a second signal path portion that is a portion of a second signal path from the input driver to the load; a first clock path portion configured to provide a first clock signal to control a timing of the first signal path portion; a second clock path portion configured to provide a second clock signal to control a timing of the second signal path portion; and control circuitry configured to: control the first clock path portion to form a first ring oscillator with a first controllable delay element during a first time period and sense a first cadence of the first ring oscillator; control the second clock path portion to form a second ring oscillator with a second controllable delay element during a second time period and sense a second cadence of the second ring oscillator; sense a first delay introduced by the first controllable delay element and sense a second delay introduced by the second delay element at least partially based on the first cadence and the second cadence, respectively, and compute a difference between the first and second delays; control the first and second delays such that said difference substantially matches a delay mismatch between a delay introduced by the first signal path and a delay introduced by the second signal path; wherein the input driver is configured to drive the first signal path portion with a first signal and drive the second signal path portion with a second signal after the circuit is controlled to control said first and second delays. control the first clock path portion to form a first ring oscillator with a first controllable delay element during a first time period and sense a first cadence of the first ring oscillator; control the second clock path portion to form a second ring oscillator with a second controllable delay element during a second time period and sense a second cadence of the second ring oscillator; sense a first delay introduced by the first controllable delay element and sense a second delay introduced by the second delay element at least partially based on the first cadence and the second cadence, respectively, and compute a difference between the first and second delays; control the first and second delays such that said difference substantially matches a delay mismatch between a delay introduced by the first signal path and a delay introduced by the second signal path; wherein the input driver is configured to drive the first signal path portion with a first signal and drive the second signal path portion with a second signal after the circuit is controlled to control said first and second delays.