A semiconductor integrated circuit device comprising: a plurality of analog ports (ANO, AN1, AN2, AN3); an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through the analog ports into a digital signal for preset virtual channels; and an A/D conversion control part operable to control an action of the A/D conversion part, wherein the A/D conversion control part includes: virtual channel registers (SVCR0 - SVCR47) adapted to store correspondence information between the virtual channels and the analog ports; and a scan-group-forming register on which a start pointer showing a start position of a scan group and an end pointer showing an end position of the scan group can be set; and wherein the A/D conversion control part is adapted to successively select one of the virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer and control the A/D conversion part to execute the A/D conversion process on the selected virtual channel, characterized in that the virtual channel registers (SVCR0 - SVCR47) are further adapted to store delay information for each of the virtual channels and that the A/D conversion process is delayed after the selection of the virtual channel based on the delay information corresponding to the selected virtual channel. a plurality of analog ports (ANO, AN1, AN2, AN3); an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through the analog ports into a digital signal for preset virtual channels; and an A/D conversion control part operable to control an action of the A/D conversion part, wherein the A/D conversion control part includes: virtual channel registers (SVCR0 - SVCR47) adapted to store correspondence information between the virtual channels and the analog ports; and a scan-group-forming register on which a start pointer showing a start position of a scan group and an end pointer showing an end position of the scan group can be set; and wherein the A/D conversion control part is adapted to successively select one of the virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer and control the A/D conversion part to execute the A/D conversion process on the selected virtual channel, virtual channel registers (SVCR0 - SVCR47) adapted to store correspondence information between the virtual channels and the analog ports; and a scan-group-forming register on which a start pointer showing a start position of a scan group and an end pointer showing an end position of the scan group can be set; and wherein the A/D conversion control part is adapted to successively select one of the virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer and control the A/D conversion part to execute the A/D conversion process on the selected virtual channel, characterized in that the virtual channel registers (SVCR0 - SVCR47) are further adapted to store delay information for each of the virtual channels and that the A/D conversion process is delayed after the selection of the virtual channel based on the delay information corresponding to the selected virtual channel.