A synchronous boost regulator circuit (50, 70) with pass-through operation control and low quiescent current and configured to supply a current at a regulated output voltage (V OUT_REG) to an output node (V OUT) configured to be coupled to a load, the synchronous boost regulator circuit (50, 70) comprising: a power stage circuit coupled to supply the current to the output node (V OUT), the power stage circuit including a low-side switch (105, 205), a high-side switch (103, 203), and an inductor; a first comparator (160, 260) configured to compare a representation of an input node voltage (V IN) and an output node voltage (V OUT) to generate a first control signal (VINHIGH); an error amplifier configured to receive a representation of the output node voltage (V OUT), receive a first reference voltage (V REF1) and generate a current control signal, based on their difference, to control an inductor current so as to maintain the output node (V OUT) at the regulated output voltage (V OUT_REG); a clock (136, 236) configured to trigger the low-side switch (105, 205) to turn ON; and a pass-through operation control circuit (151, 251) configured to control the high-side switch (103, 203), characterized in that the pass-through operation control circuit (151, 251) includes: pass-through operation detection circuitry responsive to the first control signal (VINHIGH) and the current control signal and configured to generate a pass-through control signal (PASSTROUGH 168) indicating that the regulator circuit (50, 70) has entered or exited a pass-through operation; and sleep mode circuitry configured to receive the pass-through control signal (PASSTROUGH 168) and generate a sleep mode signal (SLEEP) that causes at least the clock (136,236) to enter and exit a sleep mode, wherein entering the sleep mode blocks the clock (136, 236) to trigger the low-side switch (105, 205) to turn ON and reduces a quiescent current of at least the clock (136, 236); wherein the pass-through operation control circuit (151, 251) is configured to enter the pass-through operation and keep the high-side switch (103, 203) ON constantly during the pass-through operation when the output node voltage (V OUT) exceeds the regulated output voltage (V OUT_REG) and when the input node voltage (V IN) exceeds the output node voltage (V OUT). a power stage circuit coupled to supply the current to the output node (V OUT), the power stage circuit including a low-side switch (105, 205), a high-side switch (103, 203), and an inductor; a first comparator (160, 260) configured to compare a representation of an input node voltage (V IN) and an output node voltage (V OUT) to generate a first control signal (VINHIGH); an error amplifier configured to receive a representation of the output node voltage (V OUT), receive a first reference voltage (V REF1) and generate a current control signal, based on their difference, to control an inductor current so as to maintain the output node (V OUT) at the regulated output voltage (V OUT_REG); a clock (136, 236) configured to trigger the low-side switch (105, 205) to turn ON; and a pass-through operation control circuit (151, 251) configured to control the high-side switch (103, 203), characterized in that the pass-through operation control circuit (151, 251) includes: pass-through operation detection circuitry responsive to the first control signal (VINHIGH) and the current control signal and configured to generate a pass-through control signal (PASSTROUGH 168) indicating that the regulator circuit (50, 70) has entered or exited a pass-through operation; and sleep mode circuitry configured to receive the pass-through control signal (PASSTROUGH 168) and generate a sleep mode signal (SLEEP) that causes at least the clock (136,236) to enter and exit a sleep mode, wherein entering the sleep mode blocks the clock (136, 236) to trigger the low-side switch (105, 205) to turn ON and reduces a quiescent current of at least the clock (136, 236); pass-through operation detection circuitry responsive to the first control signal (VINHIGH) and the current control signal and configured to generate a pass-through control signal (PASSTROUGH 168) indicating that the regulator circuit (50, 70) has entered or exited a pass-through operation; and sleep mode circuitry configured to receive the pass-through control signal (PASSTROUGH 168) and generate a sleep mode signal (SLEEP) that causes at least the clock (136,236) to enter and exit a sleep mode, wherein entering the sleep mode blocks the clock (136, 236) to trigger the low-side switch (105, 205) to turn ON and reduces a quiescent current of at least the clock (136, 236); wherein the pass-through operation control circuit (151, 251) is configured to enter the pass-through operation and keep the high-side switch (103, 203) ON constantly during the pass-through operation when the output node voltage (V OUT) exceeds the regulated output voltage (V OUT_REG) and when the input node voltage (V IN) exceeds the output node voltage (V OUT).