A semiconductor chip package, comprising: a lead frame having a chip carrier and a plurality of leads, wherein the chip carrier has a first surface and an opposite second surface; a semiconductor chip mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier, wherein at least one lead of the lead frame is electrically connected to the bonding pad, respectively; and a package substrate comprising a central region attached to the second surface, having an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a marginal region of the package substrate, wherein the package substrate is free from overlapping the leads of the lead frame from a top view, wherein some of the bonding pads of the semiconductor chip are electrically connected to a top surface of the package substrate, which faces the second surface of the chip carrier, said semiconductor chip package further comprises: a covering material encapsulating the semiconductor chip, an inner portion of the lead frame and a portion of the package substrate, leaving a bottom surface of the package substrate exposed from the covering material; a plurality of conductive planes (226, 227, 252) on the top surface in the marginal region, electrically connected to the bonding pads of the semiconductor chip; and a plurality of vias drilled through the package substrate, wherein some of the vias are electrically connected to the conductive planes on the top surface of the package substrate and a plurality of ball pads on the bottom surface of the package substrate, characterized in that the conductive planes (226, 227, 252) comprise power planes or ground planes, wherein the ball pads are coplanar with the covering material, the ball pads having attached thereto solder balls mountable to a printed circuit board. a lead frame having a chip carrier and a plurality of leads, wherein the chip carrier has a first surface and an opposite second surface; a semiconductor chip mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier, wherein at least one lead of the lead frame is electrically connected to the bonding pad, respectively; and a package substrate comprising a central region attached to the second surface, having an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a marginal region of the package substrate, wherein the package substrate is free from overlapping the leads of the lead frame from a top view, wherein some of the bonding pads of the semiconductor chip are electrically connected to a top surface of the package substrate, which faces the second surface of the chip carrier, said semiconductor chip package further comprises: a covering material encapsulating the semiconductor chip, an inner portion of the lead frame and a portion of the package substrate, leaving a bottom surface of the package substrate exposed from the covering material; a plurality of conductive planes (226, 227, 252) on the top surface in the marginal region, electrically connected to the bonding pads of the semiconductor chip; and a plurality of vias drilled through the package substrate, wherein some of the vias are electrically connected to the conductive planes on the top surface of the package substrate and a plurality of ball pads on the bottom surface of the package substrate, characterized in that the conductive planes (226, 227, 252) comprise power planes or ground planes, wherein the ball pads are coplanar with the covering material, the ball pads having attached thereto solder balls mountable to a printed circuit board. a covering material encapsulating the semiconductor chip, an inner portion of the lead frame and a portion of the package substrate, leaving a bottom surface of the package substrate exposed from the covering material; a plurality of conductive planes (226, 227, 252) on the top surface in the marginal region, electrically connected to the bonding pads of the semiconductor chip; and a plurality of vias drilled through the package substrate, wherein some of the vias are electrically connected to the conductive planes on the top surface of the package substrate and a plurality of ball pads on the bottom surface of the package substrate, characterized in that the conductive planes (226, 227, 252) comprise power planes or ground planes, wherein the ball pads are coplanar with the covering material, the ball pads having attached thereto solder balls mountable to a printed circuit board.