A method of operating a single-phase multi-level inverter for generating a sine wave AC output signal having a first frequency, wherein the single-phase multi-level comprises: • four banks of N series connected MOSFET transistors, a first bank (S1A-S6A) being connected in series with a second bank (S1B-S6B), a third bank (S1C-S6C) being connected in series with a fourth bank (S1D-S6D), and the first and the second bank being in parallel to the third bank and the fourth bank, • at least one first capacitor (C1-C5), each of the at least one first capacitor (C1-C5) connected between two adjacent MOSFET transistors of the first bank (S1A-S6A) and two adjacent MOSFET transistors of the second bank (S1B-S6B); • at least one second capacitor (C6-C10), each of the at least one second capacitor (C6-C10) connected between two adjacent MOSFET transistors of the third bank (S1C-S6C) and two adjacent MOSFET transistors of the fourth bank (S1D-S6D); • a first terminal and a second terminal for providing the sine wave AC output signal having a first frequency there between, wherein ∘ the first terminal is between the first bank (S1A-S6A) and the second bank (S1B-S6B), and ∘ the second terminal is between the third bank (S1C-S6C) and the fourth bank (S1D-S6D); the method being characterized by: switching, at a switching frequency that is greater than the first frequency, each of the plurality of MOSFET transistors in each bank by: • controlling, based on N first control signals, each of the N MOSFET transistors of the first bank (S1A-S6A) at staggered times during each cycle of the switching frequency; • controlling, based on N second control signals that correspond to inverted versions of the N first control signals, each of the N MOSFET transistors in the second bank (S1B-S6B) at staggered times during each cycle of the switching frequency; • controlling, based on the N second control signals, each of the N MOSFET transistors in the third bank (S1C-S6C) at staggered times during each cycle of the switching frequency; and • controlling, based on the N first control signals, each of the N MOSFET transistors in the fourth bank (S1D-S6D) at staggered times during each cycle of the switching frequency; and wherein in each of the four banks of series connected MOSFET transistors, turning on of any one MOSFET transistor in the respective bank occurs with a time delay between turning on another MOSFET transistor in the respective bank, wherein the time delay is equal to 1/N of the cycle. • four banks of N series connected MOSFET transistors, a first bank (S1A-S6A) being connected in series with a second bank (S1B-S6B), a third bank (S1C-S6C) being connected in series with a fourth bank (S1D-S6D), and the first and the second bank being in parallel to the third bank and the fourth bank, • at least one first capacitor (C1-C5), each of the at least one first capacitor (C1-C5) connected between two adjacent MOSFET transistors of the first bank (S1A-S6A) and two adjacent MOSFET transistors of the second bank (S1B-S6B); • at least one second capacitor (C6-C10), each of the at least one second capacitor (C6-C10) connected between two adjacent MOSFET transistors of the third bank (S1C-S6C) and two adjacent MOSFET transistors of the fourth bank (S1D-S6D); • a first terminal and a second terminal for providing the sine wave AC output signal having a first frequency there between, wherein ∘ the first terminal is between the first bank (S1A-S6A) and the second bank (S1B-S6B), and ∘ the second terminal is between the third bank (S1C-S6C) and the fourth bank (S1D-S6D); ∘ the first terminal is between the first bank (S1A-S6A) and the second bank (S1B-S6B), and ∘ the second terminal is between the third bank (S1C-S6C) and the fourth bank (S1D-S6D); • controlling, based on N first control signals, each of the N MOSFET transistors of the first bank (S1A-S6A) at staggered times during each cycle of the switching frequency; • controlling, based on N second control signals that correspond to inverted versions of the N first control signals, each of the N MOSFET transistors in the second bank (S1B-S6B) at staggered times during each cycle of the switching frequency; • controlling, based on the N second control signals, each of the N MOSFET transistors in the third bank (S1C-S6C) at staggered times during each cycle of the switching frequency; and • controlling, based on the N first control signals, each of the N MOSFET transistors in the fourth bank (S1D-S6D) at staggered times during each cycle of the switching frequency; and