An apparatus comprising: a plurality of memory elements (805a, 805b) that compose a shared memory pool; a plurality of computing nodes; three shared memory controllers (815, 815a-c), wherein each shared memory controller is directly connected to and provide access to a respective subset of the plurality memory elements that compose the shared memory pool; and the three shared memory controllers are directly interconnected with each other; a first shared memory controller (815, 815a-c) of the three of shared memory controllers comprising: a first interface to receive, from a computing node of the plurality of computing nodes, a request associated with a memory transaction involving a particular line in a memory pool, wherein the request includes first address (1440, 1540), including a node address according to an independent node address map (1305, 1310) of the computing node of the plurality of computing nodes; translation logic to use an address translation structure to translate the first address into a corresponding second address according to a global address map for the memory pool; routing logic (1205a, 1205b, 1215a-h) is configured to: determine that a particular one of the three shared memory controllers is associated with the second address in the global address map; route the request directly between the first and the particular shared memory controller; and cause the particular shared memory controller to handle the request wherein the independent node address map and the global address map comprise a global coherent software shared memory region accessible by the plurality of computing nodes. a plurality of memory elements (805a, 805b) that compose a shared memory pool; a plurality of computing nodes; three shared memory controllers (815, 815a-c), wherein each shared memory controller is directly connected to and provide access to a respective subset of the plurality memory elements that compose the shared memory pool; and the three shared memory controllers are directly interconnected with each other; a first shared memory controller (815, 815a-c) of the three of shared memory controllers comprising: a first interface to receive, from a computing node of the plurality of computing nodes, a request associated with a memory transaction involving a particular line in a memory pool, wherein the request includes first address (1440, 1540), including a node address according to an independent node address map (1305, 1310) of the computing node of the plurality of computing nodes; translation logic to use an address translation structure to translate the first address into a corresponding second address according to a global address map for the memory pool; routing logic (1205a, 1205b, 1215a-h) is configured to: determine that a particular one of the three shared memory controllers is associated with the second address in the global address map; route the request directly between the first and the particular shared memory controller; and cause the particular shared memory controller to handle the request wherein the independent node address map and the global address map comprise a global coherent software shared memory region accessible by the plurality of computing nodes. a first interface to receive, from a computing node of the plurality of computing nodes, a request associated with a memory transaction involving a particular line in a memory pool, wherein the request includes first address (1440, 1540), including a node address according to an independent node address map (1305, 1310) of the computing node of the plurality of computing nodes; translation logic to use an address translation structure to translate the first address into a corresponding second address according to a global address map for the memory pool; routing logic (1205a, 1205b, 1215a-h) is configured to: determine that a particular one of the three shared memory controllers is associated with the second address in the global address map; route the request directly between the first and the particular shared memory controller; and cause the particular shared memory controller to handle the request wherein the independent node address map and the global address map comprise a global coherent software shared memory region accessible by the plurality of computing nodes. determine that a particular one of the three shared memory controllers is associated with the second address in the global address map; route the request directly between the first and the particular shared memory controller; and cause the particular shared memory controller to handle the request wherein the independent node address map and the global address map comprise a global coherent software shared memory region accessible by the plurality of computing nodes.