A method of manufacturing a flat panel display apparatus, the method comprising: sequentially forming a semiconductor layer and a first conductive layer on a substrate; simultaneously patterning the semiconductor layer and the first conductive layer to form an active layer of a thin-film transistor and a capacitor having a first bottom electrode and a first top electrode in a first masking operation; forming a first insulation layer on a structure formed by the first masking operation; sequentially forming a second conductive layer and a third conductive layer on the first insulation layer; simultaneously patterning each of the second conductive layer and the third conductive layer to respectively form a gate bottom electrode and a gate top electrode of the TFT, to form a second bottom electrode and a second top electrode of the capacitor, and to form a pixel bottom electrode and a pixel top electrode in a second masking operation; forming a second insulation layer on the structure formed by the second masking operation; patterning the second insulation layer to partially expose the source region (21 a) and the drain region (21 b) and edges of the pixel top electrode in a third masking operation; forming a fourth conductive layer on the structure formed by the third masking operation; patterning the fourth conductive layer to form a source electrode and a drain electrode of the TFT in a fourth masking operation; forming a third insulation layer on the structure formed by the fourth masking operation; and removing the second insulation layer, the third insulation layer and the pixel top electrode such that the pixel bottom electrode is exposed, in a fifth masking operation. sequentially forming a semiconductor layer and a first conductive layer on a substrate; simultaneously patterning the semiconductor layer and the first conductive layer to form an active layer of a thin-film transistor and a capacitor having a first bottom electrode and a first top electrode in a first masking operation; forming a first insulation layer on a structure formed by the first masking operation; sequentially forming a second conductive layer and a third conductive layer on the first insulation layer; simultaneously patterning each of the second conductive layer and the third conductive layer to respectively form a gate bottom electrode and a gate top electrode of the TFT, to form a second bottom electrode and a second top electrode of the capacitor, and to form a pixel bottom electrode and a pixel top electrode in a second masking operation; forming a second insulation layer on the structure formed by the second masking operation; patterning the second insulation layer to partially expose the source region (21 a) and the drain region (21 b) and edges of the pixel top electrode in a third masking operation; forming a fourth conductive layer on the structure formed by the third masking operation; patterning the fourth conductive layer to form a source electrode and a drain electrode of the TFT in a fourth masking operation; forming a third insulation layer on the structure formed by the fourth masking operation; and removing the second insulation layer, the third insulation layer and the pixel top electrode such that the pixel bottom electrode is exposed, in a fifth masking operation.