An array substrate, comprising: a plurality of pixels including sub-pixels (R, G, B) and forming a matrix, each sub-pixel (R, G, B) including a pair of sub-pixel portions (1A, 1B); a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line and are configured to control a pair of sub-pixel portions (1A, 1B) in neighboring rows of sub-pixel portions (1A, 1B), each of the plurality of sub-pixels (R, G, B) comprises two pixel electrodes corresponding to the pair of sub-pixel portions (1A, 1B); the two pixel electrodes are insulated from one another, and are arranged to generate two liquid crystal domains which are symmetrical along the gate line; the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; one gate line is arranged between two rows of sub-pixel portions; the pair of transistors are disposed across the gate line and at one side of the data line; and characterized in that for each pair of transistors, gate electrodes of the pair of transistors are formed by a single, commonly shared gate electrode and are coupled with the gate line; and drain electrodes of the pair of transistors are respectively disposed at two sides of the gate line and are formed by a single, commonly shared drain electrode and source electrodes of the pair of transistors are formed by a portion of the data line located above the gate electrode. a plurality of pixels including sub-pixels (R, G, B) and forming a matrix, each sub-pixel (R, G, B) including a pair of sub-pixel portions (1A, 1B); a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line and are configured to control a pair of sub-pixel portions (1A, 1B) in neighboring rows of sub-pixel portions (1A, 1B), each of the plurality of sub-pixels (R, G, B) comprises two pixel electrodes corresponding to the pair of sub-pixel portions (1A, 1B); the two pixel electrodes are insulated from one another, and are arranged to generate two liquid crystal domains which are symmetrical along the gate line; the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; one gate line is arranged between two rows of sub-pixel portions; the pair of transistors are disposed across the gate line and at one side of the data line; and characterized in that for each pair of transistors, gate electrodes of the pair of transistors are formed by a single, commonly shared gate electrode and are coupled with the gate line; and drain electrodes of the pair of transistors are respectively disposed at two sides of the gate line and are formed by a single, commonly shared drain electrode and source electrodes of the pair of transistors are formed by a portion of the data line located above the gate electrode. each pair of transistors are disposed adjacent to an intersection between a gate line and a data line and are configured to control a pair of sub-pixel portions (1A, 1B) in neighboring rows of sub-pixel portions (1A, 1B), each of the plurality of sub-pixels (R, G, B) comprises two pixel electrodes corresponding to the pair of sub-pixel portions (1A, 1B); the two pixel electrodes are insulated from one another, and are arranged to generate two liquid crystal domains which are symmetrical along the gate line; the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; one gate line is arranged between two rows of sub-pixel portions; the pair of transistors are disposed across the gate line and at one side of the data line; and characterized in that for each pair of transistors, gate electrodes of the pair of transistors are formed by a single, commonly shared gate electrode and are coupled with the gate line; and drain electrodes of the pair of transistors are respectively disposed at two sides of the gate line and are formed by a single, commonly shared drain electrode and source electrodes of the pair of transistors are formed by a portion of the data line located above the gate electrode.