A data processing device comprising: a first body circuit and a first check circuit which are duplicated to each other in a first clock domain (ACLK); a second body circuit and a second check circuit which are duplicated to each other in a second clock domain (BCLK) which is asynchronous to the first clock domain (ACLK); and an asynchronous transfer circuit that transfers a payload signal between the first clock domain (ACLK) and the second clock domain (BCLK), wherein the asynchronous transfer circuit includes: a first body-side bridge circuit and a first check-side bridge circuit which are respectively connected to the first body circuit and the first check circuit and are duplicated to each other in the first clock domain (ACLK), and a second body-side bridge circuit and a second check-side bridge circuit which are respectively connected to the second body circuit and the second check circuit and are duplicated to each other in the second clock domain (BCLK); characterized in that: the asynchronous transfer circuit further includes a comparison circuit (2_3) that operates in the first clock domain (ACLK), wherein the first body-side bridge circuit outputs the payload signal and a control signal (CsRAB) indicating a timing at which the payload signal is stable on a reception side to the second body-side bridge circuit and the second check-side bridge circuit, wherein the first check-side bridge circuit outputs a check payload signal and a check control signal (CsCAB) which indicates a timing at which the check payload signal is stable on a reception side, and wherein the comparison circuit (2_3) compares the control signal (CsRAB) and the check control signal (CsCAB) based on cycles of the first clock domain (ACLK). a first body circuit and a first check circuit which are duplicated to each other in a first clock domain (ACLK); a second body circuit and a second check circuit which are duplicated to each other in a second clock domain (BCLK) which is asynchronous to the first clock domain (ACLK); and an asynchronous transfer circuit that transfers a payload signal between the first clock domain (ACLK) and the second clock domain (BCLK), wherein the asynchronous transfer circuit includes: a first body-side bridge circuit and a first check-side bridge circuit which are respectively connected to the first body circuit and the first check circuit and are duplicated to each other in the first clock domain (ACLK), and a second body-side bridge circuit and a second check-side bridge circuit which are respectively connected to the second body circuit and the second check circuit and are duplicated to each other in the second clock domain (BCLK); characterized in that: the asynchronous transfer circuit further includes a comparison circuit (2_3) that operates in the first clock domain (ACLK), wherein the first body-side bridge circuit outputs the payload signal and a control signal (CsRAB) indicating a timing at which the payload signal is stable on a reception side to the second body-side bridge circuit and the second check-side bridge circuit, wherein the first check-side bridge circuit outputs a check payload signal and a check control signal (CsCAB) which indicates a timing at which the check payload signal is stable on a reception side, and wherein the comparison circuit (2_3) compares the control signal (CsRAB) and the check control signal (CsCAB) based on cycles of the first clock domain (ACLK). a first body-side bridge circuit and a first check-side bridge circuit which are respectively connected to the first body circuit and the first check circuit and are duplicated to each other in the first clock domain (ACLK), and a second body-side bridge circuit and a second check-side bridge circuit which are respectively connected to the second body circuit and the second check circuit and are duplicated to each other in the second clock domain (BCLK); characterized in that: the asynchronous transfer circuit further includes a comparison circuit (2_3) that operates in the first clock domain (ACLK), wherein the first body-side bridge circuit outputs the payload signal and a control signal (CsRAB) indicating a timing at which the payload signal is stable on a reception side to the second body-side bridge circuit and the second check-side bridge circuit, wherein the first check-side bridge circuit outputs a check payload signal and a check control signal (CsCAB) which indicates a timing at which the check payload signal is stable on a reception side, and wherein the comparison circuit (2_3) compares the control signal (CsRAB) and the check control signal (CsCAB) based on cycles of the first clock domain (ACLK). the asynchronous transfer circuit further includes a comparison circuit (2_3) that operates in the first clock domain (ACLK), wherein the first body-side bridge circuit outputs the payload signal and a control signal (CsRAB) indicating a timing at which the payload signal is stable on a reception side to the second body-side bridge circuit and the second check-side bridge circuit, wherein the first check-side bridge circuit outputs a check payload signal and a check control signal (CsCAB) which indicates a timing at which the check payload signal is stable on a reception side, and wherein the comparison circuit (2_3) compares the control signal (CsRAB) and the check control signal (CsCAB) based on cycles of the first clock domain (ACLK).