An electronic device, comprising: a boot-code memory that stores boot code; a plurality of hardware modules including: a boot core that accesses the boot-code memory to execute the boot code at startup of the electronic device, wherein the boot core is capable of executing application code after the startup is complete; and one or more master cores that execute application code; and an access control circuit that prevents the boot core from accessing the boot-code memory when the boot core is executing application code; wherein the access control circuit prevents each of the one or more hardware modules from accessing the boot-code memory at any time, wherein each of the boot core and each hardware module is assigned a unique module ID value, and when one of the hardware modules attempts to access the boot-code memory, the access control circuit compares the module ID value of the one hardware module with the module ID value of the boot core to determine whether to allow the one hardware module to access the boot-code memory; and wherein the access control circuit comprises a general purpose register,GPR, logic circuitry, a sticky register, and gating logic; the boot code causes the boot core to (i) set the GPR value and (ii) place the boot core into a sleep state at the end of the startup; the GPR value and a sleep-state parameter are applied to the logic circuitry, which generates a delayed, logic output signal that is (i) applied to the sticky register and (ii) fed back to the boot core to remove the boot core from the sleep state; the sticky register generates a boot disable parameter based on the delayed, logic output signal; and when one of the hardware modules attempts to access the boot-code memory, the gating logic determines whether to allow said access based on at least the boot disable parameter. a boot core that accesses the boot-code memory to execute the boot code at startup of the electronic device, wherein the boot core is capable of executing application code after the startup is complete; and one or more master cores that execute application code; and an access control circuit that prevents the boot core from accessing the boot-code memory when the boot core is executing application code; wherein the access control circuit prevents each of the one or more hardware modules from accessing the boot-code memory at any time, wherein each of the boot core and each hardware module is assigned a unique module ID value, and when one of the hardware modules attempts to access the boot-code memory, the access control circuit compares the module ID value of the one hardware module with the module ID value of the boot core to determine whether to allow the one hardware module to access the boot-code memory; and wherein the access control circuit comprises a general purpose register,GPR, logic circuitry, a sticky register, and gating logic; the boot code causes the boot core to (i) set the GPR value and (ii) place the boot core into a sleep state at the end of the startup; the GPR value and a sleep-state parameter are applied to the logic circuitry, which generates a delayed, logic output signal that is (i) applied to the sticky register and (ii) fed back to the boot core to remove the boot core from the sleep state; the sticky register generates a boot disable parameter based on the delayed, logic output signal; and when one of the hardware modules attempts to access the boot-code memory, the gating logic determines whether to allow said access based on at least the boot disable parameter.