Circuit comprising: a first clock source, a second clock source and a third clock source, a first processing unit which is connected to the first clock source and has a first logic circuit and a first storage circuit connected to the first logic circuit, wherein the first storage circuit stores a first set of instructions which is configured to implement a first control program when executed by the first logic circuit, wherein the first clock source is configured to predefine a clock rate of the execution of the first set of instructions, a second processing unit which is connected to the second clock source and has a second logic circuit and a second storage circuit connected to the second logic circuit, wherein the second storage circuit stores a second set of instructions which is configured to implement a second control program when executed by the second logic circuit, wherein the second clock source is configured to predefine a clock rate of the execution of the second set of instructions, and the second set of instructions is a functionally identical copy of the first set of instructions, and an input unit, wherein the first processing unit is configured to query an input state of the input unit in response to a signal from the third clock source and to output the queried input state at an output of the first processing unit, wherein the circuit is also configured to compare a first control signal generated by the first processing unit by executing the first set of instructions with a second control signal generated by the second processing unit by executing the second set of instructions and to generate an error signal in the event of discrepancies between the first control signal and the second control signal; characterized in that an input of the second processing unit is connected to the output of the first processing unit, and the first processing unit and the second processing unit are configured to determine the input state which has been output after a predefined nominal period, I nom, after the signal from the third clock source and to execute the instructions if execution of the instructions is assigned to the determined input state. a first clock source, a second clock source and a third clock source, a first processing unit which is connected to the first clock source and has a first logic circuit and a first storage circuit connected to the first logic circuit, wherein the first storage circuit stores a first set of instructions which is configured to implement a first control program when executed by the first logic circuit, wherein the first clock source is configured to predefine a clock rate of the execution of the first set of instructions, a second processing unit which is connected to the second clock source and has a second logic circuit and a second storage circuit connected to the second logic circuit, wherein the second storage circuit stores a second set of instructions which is configured to implement a second control program when executed by the second logic circuit, wherein the second clock source is configured to predefine a clock rate of the execution of the second set of instructions, and the second set of instructions is a functionally identical copy of the first set of instructions, and an input unit, wherein the first processing unit is configured to query an input state of the input unit in response to a signal from the third clock source and to output the queried input state at an output of the first processing unit, wherein the circuit is also configured to compare a first control signal generated by the first processing unit by executing the first set of instructions with a second control signal generated by the second processing unit by executing the second set of instructions and to generate an error signal in the event of discrepancies between the first control signal and the second control signal; characterized in that an input of the second processing unit is connected to the output of the first processing unit, and the first processing unit and the second processing unit are configured to determine the input state which has been output after a predefined nominal period, I nom, after the signal from the third clock source and to execute the instructions if execution of the instructions is assigned to the determined input state.