A semiconductor structure, comprising: a III-V substrate structure having an enhancement mode transistor device disposed in a second region of the structure and depletion mode transistor device disposed in a laterally displaced first region of the structure, such structure having a channel layer for the depletion mode and enhancement mode transistor devices (40, 41), such structure having: an enhancement mode transistor device InGaP etch stop layer disposed over the channel layer; a first layer disposed on the InGaP layer; a depletion mode transistor device etch stop layer disposed on the first layer; a second layer disposed on the depletion mode transistor device etch stop layer; and a N-type GaAs layer; wherein: the InGaP layer is In 0.48 Ga 0.52 P, such layer being lattice matched to the first layer; the depletion mode transistor device has a gate recess passing through the GaAs layer, the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer; the enhancement mode transistor device has a gate recess passing through the GaAs layer, the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer; and the material of the first layer is different from InGaP; wherein the depletion mode transistor device includes a gate electrode in Schottky contact with the first layer and the enhancement mode device includes a gate electrode in Schottky contact with the InGaP layer; and source and drain electrodes (76, 78, 80) for the transistor devices are provided in ohmic contact with the GaAs layer. a III-V substrate structure having an enhancement mode transistor device disposed in a second region of the structure and depletion mode transistor device disposed in a laterally displaced first region of the structure, such structure having a channel layer for the depletion mode and enhancement mode transistor devices (40, 41), such structure having: an enhancement mode transistor device InGaP etch stop layer disposed over the channel layer; a first layer disposed on the InGaP layer; a depletion mode transistor device etch stop layer disposed on the first layer; a second layer disposed on the depletion mode transistor device etch stop layer; and a N-type GaAs layer; wherein: the InGaP layer is In 0.48 Ga 0.52 P, such layer being lattice matched to the first layer; the depletion mode transistor device has a gate recess passing through the GaAs layer, the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer; the enhancement mode transistor device has a gate recess passing through the GaAs layer, the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer; and the material of the first layer is different from InGaP; wherein the depletion mode transistor device includes a gate electrode in Schottky contact with the first layer and the enhancement mode device includes a gate electrode in Schottky contact with the InGaP layer; and source and drain electrodes (76, 78, 80) for the transistor devices are provided in ohmic contact with the GaAs layer. an enhancement mode transistor device InGaP etch stop layer disposed over the channel layer; a first layer disposed on the InGaP layer; a depletion mode transistor device etch stop layer disposed on the first layer; a second layer disposed on the depletion mode transistor device etch stop layer; and a N-type GaAs layer; the InGaP layer is In 0.48 Ga 0.52 P, such layer being lattice matched to the first layer; the depletion mode transistor device has a gate recess passing through the GaAs layer, the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer; the enhancement mode transistor device has a gate recess passing through the GaAs layer, the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer; and the material of the first layer is different from InGaP; wherein the depletion mode transistor device includes a gate electrode in Schottky contact with the first layer and the enhancement mode device includes a gate electrode in Schottky contact with the InGaP layer; and source and drain electrodes (76, 78, 80) for the transistor devices are provided in ohmic contact with the GaAs layer.