A method of forming a memory device, comprising: providing a semiconductor substrate with a substrate upper surface having a memory cell region and a logic region; forming a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in an edge; forming an oxide layer having a first portion that extends along the logic region of the substrate upper surface, a second portion that extends along the memory cell region of the substrate upper surface, and a third portion that extends along the edge of the floating gate; forming a non-conformal layer having a first portion that covers the oxide layer first portion, a second portion that covers the oxide layer second portion, and a third portion that covers the oxide layer third portion, wherein the third portion of the non-conformal layer has a thickness that is less than a thickness of the first and second portions of the non-conformal layer; performing an etch that removes the third portion of the non-conformal layer, and thins but does not entirely remove the first and second portions of the non-conformal layer; performing an oxide etch that reduces a thickness of the third portion of the oxide layer, wherein the first and second portions of the oxide layer are protected from the oxide etch by the first and second portions of the non-conformal layer; removing the first and second portions of the non-conformal layer; forming a control gate having a first portion on the second portion of the oxide layer and a second portion that extends up and over the floating gate, wherein the control gate is insulated from the edge of the floating gate by the third portion of the oxide layer having the reduced thickness; and forming a logic gate on the first portion of the oxide layer; wherein the forming of the control gate and the forming of the logic gate comprise: forming a polysilicon layer on the first, second and third portions of the oxide layer; selectively removing portions of the polysilicon layer leaving a first portion of the polysilicon layer as the formed control gate and leaving a second portion of the polysilicon layer as the formed logic gate. providing a semiconductor substrate with a substrate upper surface having a memory cell region and a logic region; forming a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in an edge; forming an oxide layer having a first portion that extends along the logic region of the substrate upper surface, a second portion that extends along the memory cell region of the substrate upper surface, and a third portion that extends along the edge of the floating gate; forming a non-conformal layer having a first portion that covers the oxide layer first portion, a second portion that covers the oxide layer second portion, and a third portion that covers the oxide layer third portion, wherein the third portion of the non-conformal layer has a thickness that is less than a thickness of the first and second portions of the non-conformal layer; performing an etch that removes the third portion of the non-conformal layer, and thins but does not entirely remove the first and second portions of the non-conformal layer; performing an oxide etch that reduces a thickness of the third portion of the oxide layer, wherein the first and second portions of the oxide layer are protected from the oxide etch by the first and second portions of the non-conformal layer; removing the first and second portions of the non-conformal layer; forming a control gate having a first portion on the second portion of the oxide layer and a second portion that extends up and over the floating gate, wherein the control gate is insulated from the edge of the floating gate by the third portion of the oxide layer having the reduced thickness; and forming a logic gate on the first portion of the oxide layer; wherein the forming of the control gate and the forming of the logic gate comprise: forming a polysilicon layer on the first, second and third portions of the oxide layer; selectively removing portions of the polysilicon layer leaving a first portion of the polysilicon layer as the formed control gate and leaving a second portion of the polysilicon layer as the formed logic gate. forming a polysilicon layer on the first, second and third portions of the oxide layer; selectively removing portions of the polysilicon layer leaving a first portion of the polysilicon layer as the formed control gate and leaving a second portion of the polysilicon layer as the formed logic gate.