A memory controller (320, 420), comprising: control circuitry coupled to one or more memory devices (230-0, 230-1, 230-2, 230-3, 330-0, 330-1, 330-N) having multiple Groups (240-0, 240-1) of planes associated therewith, each Group (240-0, 240-1) including at least two planes of physical blocks organized into Super Blocks (245-0, 245-1, 245-N), with each Super Block (245-0, 245-1, 245-N) including a physical block from each of the at least two planes, and wherein the control circuitry is configured to: receive an unassigned logical block address (331, 431) associated with a write operation; characterised in that the control circuitry is further configured to: determine, based on a maintained count of free Super Blocks available in the respective multiple Groups (240-0, 240-1), a particular free Super Block (245-0, 245-1, 245-N) within a selected one (435, 438) of the multiple Groups (240-0, 240-1) to receive data associated with the write operation; and assign the unassigned LBA (331, 431) to the selected one of the multiple Groups (240-0, 240-1) such that data associated with all subsequent write operations corresponding to the previously unassigned LBA (331, 431) is written to a free Super Block of the Super Blocks within the respective assigned Group. control circuitry coupled to one or more memory devices (230-0, 230-1, 230-2, 230-3, 330-0, 330-1, 330-N) having multiple Groups (240-0, 240-1) of planes associated therewith, each Group (240-0, 240-1) including at least two planes of physical blocks organized into Super Blocks (245-0, 245-1, 245-N), with each Super Block (245-0, 245-1, 245-N) including a physical block from each of the at least two planes, and wherein the control circuitry is configured to: receive an unassigned logical block address (331, 431) associated with a write operation; characterised in that the control circuitry is further configured to: determine, based on a maintained count of free Super Blocks available in the respective multiple Groups (240-0, 240-1), a particular free Super Block (245-0, 245-1, 245-N) within a selected one (435, 438) of the multiple Groups (240-0, 240-1) to receive data associated with the write operation; and assign the unassigned LBA (331, 431) to the selected one of the multiple Groups (240-0, 240-1) such that data associated with all subsequent write operations corresponding to the previously unassigned LBA (331, 431) is written to a free Super Block of the Super Blocks within the respective assigned Group. receive an unassigned logical block address (331, 431) associated with a write operation; characterised in that the control circuitry is further configured to: determine, based on a maintained count of free Super Blocks available in the respective multiple Groups (240-0, 240-1), a particular free Super Block (245-0, 245-1, 245-N) within a selected one (435, 438) of the multiple Groups (240-0, 240-1) to receive data associated with the write operation; and assign the unassigned LBA (331, 431) to the selected one of the multiple Groups (240-0, 240-1) such that data associated with all subsequent write operations corresponding to the previously unassigned LBA (331, 431) is written to a free Super Block of the Super Blocks within the respective assigned Group. determine, based on a maintained count of free Super Blocks available in the respective multiple Groups (240-0, 240-1), a particular free Super Block (245-0, 245-1, 245-N) within a selected one (435, 438) of the multiple Groups (240-0, 240-1) to receive data associated with the write operation; and assign the unassigned LBA (331, 431) to the selected one of the multiple Groups (240-0, 240-1) such that data associated with all subsequent write operations corresponding to the previously unassigned LBA (331, 431) is written to a free Super Block of the Super Blocks within the respective assigned Group.