A method of transferring an integrated circuit, IC, onto an alternative substrate at a wafer level to enable coefficient of thermal expansion, CTE, matching for a circuit layer to a different material, the method being executed on a wafer with a circuit layer, a first major surface of the circuit layer, a second major surface of the circuit layer opposite the first major surface, and a substrate affixed to the first major surface, the method comprising: temporarily bonding a handle to the second major surface; removing all the substrate to expose the first major surface, or removing a substantial portion of the substrate to leave a thin layer of substrate remainder; bonding a second substrate to the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, wherein bonding the second substrate to the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, comprises: depositing a bonding material comprising bonding oxide onto the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, up to a first thickness T1; and then polishing the bonding material down to a second thickness T2; removing the handle from the second major surface; and subsequently hybridizing the circuit layer to a thermally matched additional substrate using interconnects that are deposited on the second major surface of the circuit layer and on a complimentary surface of the additional substrate. the method being executed on a wafer with a circuit layer, a first major surface of the circuit layer, a second major surface of the circuit layer opposite the first major surface, and a substrate affixed to the first major surface, the method comprising: temporarily bonding a handle to the second major surface; removing all the substrate to expose the first major surface, or removing a substantial portion of the substrate to leave a thin layer of substrate remainder; bonding a second substrate to the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, wherein bonding the second substrate to the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, comprises: depositing a bonding material comprising bonding oxide onto the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, up to a first thickness T1; and then polishing the bonding material down to a second thickness T2; removing the handle from the second major surface; and subsequently hybridizing the circuit layer to a thermally matched additional substrate using interconnects that are deposited on the second major surface of the circuit layer and on a complimentary surface of the additional substrate. temporarily bonding a handle to the second major surface; removing all the substrate to expose the first major surface, or removing a substantial portion of the substrate to leave a thin layer of substrate remainder; bonding a second substrate to the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, wherein bonding the second substrate to the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, comprises: depositing a bonding material comprising bonding oxide onto the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, up to a first thickness T1; and then polishing the bonding material down to a second thickness T2; depositing a bonding material comprising bonding oxide onto the first major surface, or to the thin layer of substrate remainder that remains on the first major surface, up to a first thickness T1; and then polishing the bonding material down to a second thickness T2; removing the handle from the second major surface; and subsequently hybridizing the circuit layer to a thermally matched additional substrate using interconnects that are deposited on the second major surface of the circuit layer and on a complimentary surface of the additional substrate.