A gate driving circuit comprising a shift register that has a plurality of stages (SRC1 to SRC(n+1)) cascade-connected to each other, each of which comprises: a pull-up section including a pull-up section transistor having a gate electrode connected to a first node, a drain electrode arranged to receive a first clock signal (CK, CK1), and a source electrode arranged to pass the first clock signal (CK, CK1) as a gate line signal (GOUT1 to GOUT(n+1)) to an output node when a first node signal is driven to a high voltage in response to a first input signal; a discharging section arranged to discharge the first node signal to the off-voltage in response to a second input signal; a first holding section including a first holding section transistor responsive to the first clock signal (CK, CK1), arranged to maintain the first node signal at the off-voltage when said output node has been discharged to the off-voltage; a second holding section including a second holding section transistor having a gate electrode arranged to receive a second clock signal (CKB, CK2), a drain electrode arranged to receive the first input signal, and a source electrode connected to said first node, the second holding section being arranged to maintain the first node at the off-voltage when the first input signal is at the off-voltage; a carry section including a carry section transistor having a gate electrode connected to the first node, a drain electrode arranged to receive the first clock signal (CK, CK1), and a source electrode arranged to pass the first clock signal (CK, CK1) as a carry signal in response to the first node signal; a third holding section including a third holding section transistor having a gate electrode arranged to receive the second clock signal (CKB,CK2), a source electrode arranged to receive an off-voltage, and a drain electrode arranged to maintain said output node at the off-voltage in response to the second clock signal (CKB, CK2); a fourth holding section, and a switching section arranged to switch the fourth holding section on and off, the third holding section and the switching section being arranged to be alternatingly operated to maintain the output node signal at the off-voltage; and a pull-down section is arranged to discharge said output node to an off-voltage in response to the second input signal; and characterized in that said second holding section transistor has a smaller transistor width-to-length ratio than a sum of transistor width-to-length ratios of said first holding section transistor and the carry section transistor; and the second holding section transistor has a greater transistor width-to-length ratio than the first holding section transistor. a pull-up section including a pull-up section transistor having a gate electrode connected to a first node, a drain electrode arranged to receive a first clock signal (CK, CK1), and a source electrode arranged to pass the first clock signal (CK, CK1) as a gate line signal (GOUT1 to GOUT(n+1)) to an output node when a first node signal is driven to a high voltage in response to a first input signal; a discharging section arranged to discharge the first node signal to the off-voltage in response to a second input signal; a first holding section including a first holding section transistor responsive to the first clock signal (CK, CK1), arranged to maintain the first node signal at the off-voltage when said output node has been discharged to the off-voltage; a second holding section including a second holding section transistor having a gate electrode arranged to receive a second clock signal (CKB, CK2), a drain electrode arranged to receive the first input signal, and a source electrode connected to said first node, the second holding section being arranged to maintain the first node at the off-voltage when the first input signal is at the off-voltage; a carry section including a carry section transistor having a gate electrode connected to the first node, a drain electrode arranged to receive the first clock signal (CK, CK1), and a source electrode arranged to pass the first clock signal (CK, CK1) as a carry signal in response to the first node signal; a third holding section including a third holding section transistor having a gate electrode arranged to receive the second clock signal (CKB,CK2), a source electrode arranged to receive an off-voltage, and a drain electrode arranged to maintain said output node at the off-voltage in response to the second clock signal (CKB, CK2); a fourth holding section, and a switching section arranged to switch the fourth holding section on and off, the third holding section and the switching section being arranged to be alternatingly operated to maintain the output node signal at the off-voltage; and a pull-down section is arranged to discharge said output node to an off-voltage in response to the second input signal; and characterized in that said second holding section transistor has a smaller transistor width-to-length ratio than a sum of transistor width-to-length ratios of said first holding section transistor and the carry section transistor; and the second holding section transistor has a greater transistor width-to-length ratio than the first holding section transistor.