A decision feedback equalizer, DFE, circuit, comprising: a first equalization path and a second equalization path, each of the first equalization path and the second equalization path including: a summing node (112,152); a first synchronization latch (114,154) configured to latch data received from the summing node; a second synchronization latch (116,156) configured to latch data received from the first synchronization latch; a feedback latch (118,158) coupled to an output of the first synchronization latch and configured to latch data received from the first synchronization latch; a feedback shift register (120,160) coupled to an output of one of the second synchronization latch and the feedback latch, the feedback shift register including a plurality of sequentially coupled shift latches; and a multiplexer coupled to the second synchronization latch of each equalization path, and configured to selectively route, based on a first clock, data received from the second synchronization latch of each equalization path to an output of the DFE circuit; wherein: a first of the shift latches is configured to latch data received from one of the second synchronization latch and the feedback latch and provide data to the summing node; a second of the shift latches is configured to latch data received from the first of the shift latches; in the first equalization path, the feedback latch and the second of the shift latches are configured to provide data to the summing node of the second equalization path; and, in the second equalization path, the feedback latch and the second of the shift latches are configured to provide data to the summing node of the first equalization path; wherein the feedback latch is clocked by a clock that clocks the first synchronization latch shifted by 90 degrees; and wherein: in the first equalization path: the first synchronization latch is clocked by the first clock having a period that is twice the symbol interval time of the data received at the input of the DFE circuit; the second synchronization latch is clocked by a second clock that is an inversion of the first clock; and the first of the shift latches is clocked by a third clock that is a quadrature phase shifted version of the second clock; and in the second equalization path: the first synchronization latch is clocked by the second clock; the second synchronization latch is clocked by the first clock; and the feedback shift register is clocked by a fourth clock that is an inversion of the third clock. a first equalization path and a second equalization path, each of the first equalization path and the second equalization path including: a summing node (112,152); a first synchronization latch (114,154) configured to latch data received from the summing node; a second synchronization latch (116,156) configured to latch data received from the first synchronization latch; a feedback latch (118,158) coupled to an output of the first synchronization latch and configured to latch data received from the first synchronization latch; a feedback shift register (120,160) coupled to an output of one of the second synchronization latch and the feedback latch, the feedback shift register including a plurality of sequentially coupled shift latches; and a multiplexer coupled to the second synchronization latch of each equalization path, and configured to selectively route, based on a first clock, data received from the second synchronization latch of each equalization path to an output of the DFE circuit; wherein: a first of the shift latches is configured to latch data received from one of the second synchronization latch and the feedback latch and provide data to the summing node; a second of the shift latches is configured to latch data received from the first of the shift latches; in the first equalization path, the feedback latch and the second of the shift latches are configured to provide data to the summing node of the second equalization path; and, in the second equalization path, the feedback latch and the second of the shift latches are configured to provide data to the summing node of the first equalization path; wherein the feedback latch is clocked by a clock that clocks the first synchronization latch shifted by 90 degrees; and in the first equalization path: the first synchronization latch is clocked by the first clock having a period that is twice the symbol interval time of the data received at the input of the DFE circuit; the second synchronization latch is clocked by a second clock that is an inversion of the first clock; and the first of the shift latches is clocked by a third clock that is a quadrature phase shifted version of the second clock; and in the second equalization path: the first synchronization latch is clocked by the second clock; the second synchronization latch is clocked by the first clock; and the feedback shift register is clocked by a fourth clock that is an inversion of the third clock.