A content addressable memory comprising: a plurality of Ternary Content Addressable Memory, TCAM, Static Random Access Memory, SRAM, cells; a plurality of pairs of word lines (WLA, WLB) coupled to the TCAM SRAM cells, each pair of word lines being a first word line and a second word line; a plurality of pairs of bit lines (BB, BT) coupled to the TCAM SRAM cells; a plurality of pairs of search lines (ST, SB) coupled to the TCAM SRAM cells; a plurality of match lines coupled to the TCAM SRAM cells; a match amplifying unit coupled to the match lines; and a scan input circuit that supplies test search data to the pairs of search lines (ST, SB), wherein the match amplifying unit includes a plurality of latch circuits and a plurality of selection circuits, wherein each of the selection circuits of the match amplifying unit includes a first input coupled to the corresponding match line and a second input coupled to the output of the corresponding latch circuit, wherein the latch circuits and the selection circuits configure a scan path between a scan input terminal and a scan output terminal, wherein the content addressable memory further comprises: a match line selection circuit unit coupled to the word lines (WLA, WLB) and the outputs of the latch circuits; and a reading line, wherein the match line selection circuit unit includes a plurality of selection circuits coupled to the corresponding word lines (WLA, WLB) and the outputs of the corresponding latch circuits, and wherein each of the selection circuits of the match line selecting circuit unit outputs the output of the corresponding latch circuit to the reading line in accordance with the selection level of the first word line or the second word line. a plurality of Ternary Content Addressable Memory, TCAM, Static Random Access Memory, SRAM, cells; a plurality of pairs of word lines (WLA, WLB) coupled to the TCAM SRAM cells, each pair of word lines being a first word line and a second word line; a plurality of pairs of bit lines (BB, BT) coupled to the TCAM SRAM cells; a plurality of pairs of search lines (ST, SB) coupled to the TCAM SRAM cells; a plurality of match lines coupled to the TCAM SRAM cells; a match amplifying unit coupled to the match lines; and a scan input circuit that supplies test search data to the pairs of search lines (ST, SB), wherein the match amplifying unit includes a plurality of latch circuits and a plurality of selection circuits, wherein each of the selection circuits of the match amplifying unit includes a first input coupled to the corresponding match line and a second input coupled to the output of the corresponding latch circuit, wherein the latch circuits and the selection circuits configure a scan path between a scan input terminal and a scan output terminal, wherein the content addressable memory further comprises: a match line selection circuit unit coupled to the word lines (WLA, WLB) and the outputs of the latch circuits; and a reading line, wherein the match line selection circuit unit includes a plurality of selection circuits coupled to the corresponding word lines (WLA, WLB) and the outputs of the corresponding latch circuits, and wherein each of the selection circuits of the match line selecting circuit unit outputs the output of the corresponding latch circuit to the reading line in accordance with the selection level of the first word line or the second word line. a match line selection circuit unit coupled to the word lines (WLA, WLB) and the outputs of the latch circuits; and a reading line, wherein the match line selection circuit unit includes a plurality of selection circuits coupled to the corresponding word lines (WLA, WLB) and the outputs of the corresponding latch circuits, and wherein each of the selection circuits of the match line selecting circuit unit outputs the output of the corresponding latch circuit to the reading line in accordance with the selection level of the first word line or the second word line.