An integrated circuit, comprising: a parent terrain denoted as V 0; voltage islands denoted as V 1 and V 2, wherein the voltage island V 1 is nested within the parent terrain V 0 and the voltage island V 2 is nested within the voltage island V 1; and characterised by: additional voltage islands denoted as V 3, V 4,..., V N, a voltage island V Z nested within a voltage island V Z-1 for Z=3, 4,..., N, wherein N is an integer of at least 3; a logic circuit voltage power supply VDDI connected to a logic circuit(38, 42); and an externally supplied state saving power supply VDDSS connected to a logic state saving circuit, wherein the logic circuit and the state saving circuit are within either the voltage island V 1 or the voltage island V 2; and wherein each voltage island comprises: an externally supplied VDDN power supply and a further circuit means, wherein the further circuit means is selected from a group comprising a voltage shifting means, a fencing means, and the voltage shifting means and the fencing means; and one or more substructures selected from a group consisting of: an internal voltage island VDDI power distribution network, state saving means, one or more switching elements coupled between the externally supplied VDDN power supply and the internal voltage island VDDI power distribution network, and one or more voltage buffering circuits. a parent terrain denoted as V 0; voltage islands denoted as V 1 and V 2, wherein the voltage island V 1 is nested within the parent terrain V 0 and the voltage island V 2 is nested within the voltage island V 1; and characterised by: additional voltage islands denoted as V 3, V 4,..., V N, a voltage island V Z nested within a voltage island V Z-1 for Z=3, 4,..., N, wherein N is an integer of at least 3; a logic circuit voltage power supply VDDI connected to a logic circuit(38, 42); and an externally supplied state saving power supply VDDSS connected to a logic state saving circuit, wherein the logic circuit and the state saving circuit are within either the voltage island V 1 or the voltage island V 2; and additional voltage islands denoted as V 3, V 4,..., V N, a voltage island V Z nested within a voltage island V Z-1 for Z=3, 4,..., N, wherein N is an integer of at least 3; a logic circuit voltage power supply VDDI connected to a logic circuit(38, 42); and an externally supplied state saving power supply VDDSS connected to a logic state saving circuit, wherein the logic circuit and the state saving circuit are within either the voltage island V 1 or the voltage island V 2; and wherein each voltage island comprises: an externally supplied VDDN power supply and a further circuit means, wherein the further circuit means is selected from a group comprising a voltage shifting means, a fencing means, and the voltage shifting means and the fencing means; and an externally supplied VDDN power supply and a further circuit means, wherein the further circuit means is selected from a group comprising a voltage shifting means, a fencing means, and the voltage shifting means and the fencing means; and one or more substructures selected from a group consisting of: an internal voltage island VDDI power distribution network, state saving means, one or more switching elements coupled between the externally supplied VDDN power supply and the internal voltage island VDDI power distribution network, and one or more voltage buffering circuits. an internal voltage island VDDI power distribution network, state saving means, one or more switching elements coupled between the externally supplied VDDN power supply and the internal voltage island VDDI power distribution network, and one or more voltage buffering circuits.