A process for manufacturing a heterostructure field-effect transistor (50; 150; 250), comprising the steps of: - in a wafer comprising a channel layer of a first semiconductor material, a barrier layer of a second semiconductor material, and a passivation layer (105; 205) of dielectric material, forming a gate region (109; 209) extending through the wafer; - forming drain and source electrodes (115, 116) extending through the wafer on different sides of the gate region (109; 209); - forming a dielectric layer over the gate region (109; 209) and the passivation layer (105; 205); - removing selective portions of the dielectric layer so as to remove it from over the drain and source electrodes; and - removing selective portions of the dielectric layer through a plurality of etches so as to form a cavity (126; 140) arranged between the gate region (109; 209) and the drain electrode and having a surface (133; 144) facing toward the wafer, the surface having a plurality of steps (132; 143), the steps having respective different vertical distances above the wafer; - depositing, over the dielectric layer, inside the cavity (126; 140) and inside the removed portions of the dielectric layer, a conductive material completely filling the cavity (126; 140); - defining the conductive material to form a drain contact region over and in contact with the drain electrode and a field plate (131; 142) coupled to the source electrode and having a planar portion (125; 139) and a projecting region (124; 145), the planar portion (125; 139) being in direct electrical contact with the source electrode, forming a source contact, and extending over the gate region (109; 209) and the area comprised between the gate region (109; 209) and the drain electrode, and the projecting region (124; 145) extending from and under the planar portion, inside the cavity, toward the wafer. - in a wafer comprising a channel layer of a first semiconductor material, a barrier layer of a second semiconductor material, and a passivation layer (105; 205) of dielectric material, forming a gate region (109; 209) extending through the wafer; - forming drain and source electrodes (115, 116) extending through the wafer on different sides of the gate region (109; 209); - forming a dielectric layer over the gate region (109; 209) and the passivation layer (105; 205); - removing selective portions of the dielectric layer so as to remove it from over the drain and source electrodes; and - removing selective portions of the dielectric layer through a plurality of etches so as to form a cavity (126; 140) arranged between the gate region (109; 209) and the drain electrode and having a surface (133; 144) facing toward the wafer, the surface having a plurality of steps (132; 143), the steps having respective different vertical distances above the wafer; - depositing, over the dielectric layer, inside the cavity (126; 140) and inside the removed portions of the dielectric layer, a conductive material completely filling the cavity (126; 140); - defining the conductive material to form a drain contact region over and in contact with the drain electrode and a field plate (131; 142) coupled to the source electrode and having a planar portion (125; 139) and a projecting region (124; 145), the planar portion (125; 139) being in direct electrical contact with the source electrode, forming a source contact, and extending over the gate region (109; 209) and the area comprised between the gate region (109; 209) and the drain electrode, and the projecting region (124; 145) extending from and under the planar portion, inside the cavity, toward the wafer. the planar portion (125; 139) being in direct electrical contact with the source electrode, forming a source contact, and extending over the gate region (109; 209) and the area comprised between the gate region (109; 209) and the drain electrode, and the projecting region (124; 145) extending from and under the planar portion, inside the cavity, toward the wafer.