A memory device (100, 300), comprising: a substrate; a bottom select gate disposed over the substrate; a plurality of word lines (62d-62m) positioned over the BSG with a staircase configuration; a plurality of insulating layers (60, 60a-60q) disposed between the substrate, the BSG, and the plurality of word lines (62d-62m); one or more first dielectric trenches (26, 28) formed in the BSG and extending in a length direction of the substrate and into the substrate to separate the BSG into a plurality of sub-BSGs (62a-1, 62a-2, 62a-3, 62p-1, 62p-2, 62p-3), wherein the word lines (62d-62m) are not separated by the dielectric trenches (26; 28); one or more common source regions (52, 52a, 52b, 52c) formed over the substrate and extending in the length direction of the substrate, wherein the one or more common source regions extend through the BSG, the plurality of word lines (62d-62m), and the plurality of insulating layers (60, 60a-60q); a plurality of channel structures (30, 32, 38) formed over the substrate along a height direction of the substrate that is perpendicular to the substrate, wherein each of the plurality of channel structure passes through the BSG, the plurality of word lines (62d-62m), the TSG, and the plurality of insulating layers (60, 60a-60q), wherein the one or more second dielectric trenches (56, 58) and the one or more common source regions (52, 52a, 52b, 52c) are alternatively disposed in the width direction of the substrate so that a plurality of channel structures (30, 32, 38) are disposed therebetween, wherein the 3D-NAND memory device is divided into a plurality of sub-block (SUB-BLK 1-3) by the first/second trenches (26, 28, 56, 58), wherein the second sub-block (SUB-BLK 2) has a larger size than the first sub-block (SUB-BLK 1) and the third sub-block (SUB-BLK 3); and one or more dummy BSGs (62b-62c, 62n-62o) that are formed between the plurality of word lines (62d-62m) and the BSG, separated by the one or more first dielectric trenches (26, 28) into a plurality of dummy sub-BSGs (62a-1, 62a-2, 62a-3, 62p-1, 62p-2, 62p-3), and spaced apart from the plurality of word lines (62d-62m) and the BSG by the plurality of insulating layer (60, 60a-60q). a substrate; a bottom select gate disposed over the substrate; a plurality of word lines (62d-62m) positioned over the BSG with a staircase configuration; a plurality of insulating layers (60, 60a-60q) disposed between the substrate, the BSG, and the plurality of word lines (62d-62m); one or more first dielectric trenches (26, 28) formed in the BSG and extending in a length direction of the substrate and into the substrate to separate the BSG into a plurality of sub-BSGs (62a-1, 62a-2, 62a-3, 62p-1, 62p-2, 62p-3), wherein the word lines (62d-62m) are not separated by the dielectric trenches (26; 28); one or more common source regions (52, 52a, 52b, 52c) formed over the substrate and extending in the length direction of the substrate, wherein the one or more common source regions extend through the BSG, the plurality of word lines (62d-62m), and the plurality of insulating layers (60, 60a-60q); a plurality of channel structures (30, 32, 38) formed over the substrate along a height direction of the substrate that is perpendicular to the substrate, wherein each of the plurality of channel structure passes through the BSG, the plurality of word lines (62d-62m), the TSG, and the plurality of insulating layers (60, 60a-60q), wherein the one or more second dielectric trenches (56, 58) and the one or more common source regions (52, 52a, 52b, 52c) are alternatively disposed in the width direction of the substrate so that a plurality of channel structures (30, 32, 38) are disposed therebetween, wherein the 3D-NAND memory device is divided into a plurality of sub-block (SUB-BLK 1-3) by the first/second trenches (26, 28, 56, 58), wherein the second sub-block (SUB-BLK 2) has a larger size than the first sub-block (SUB-BLK 1) and the third sub-block (SUB-BLK 3); and one or more dummy BSGs (62b-62c, 62n-62o) that are formed between the plurality of word lines (62d-62m) and the BSG, separated by the one or more first dielectric trenches (26, 28) into a plurality of dummy sub-BSGs (62a-1, 62a-2, 62a-3, 62p-1, 62p-2, 62p-3), and spaced apart from the plurality of word lines (62d-62m) and the BSG by the plurality of insulating layer (60, 60a-60q).