A method for generating virtual memory pre-fetch requests for a virtual memory and a multiple port memory management unit, MMU, circuit (114, 214), the method comprising: monitoring by a translation lookaside buffer, TLB, pre-fetch circuit, virtual memory access requests sent to a particular port (124, 126, 128) of the MMU circuit (114, 214); detecting satisfaction of at least one trigger condition that is based upon the virtual memory access requests; generating, in response to the satisfaction of the trigger condition, virtual memory pre-fetch requests by the TLB pre-fetch circuit; transmitting the virtual memory pre-fetch requests to the MMU circuit (114, 214) using the particular port (124, 126, 128); in response to each virtual memory pre-fetch request, generating a first physical access request for a page table entry by the MMU circuit, storing the page table entry in a respective translation lookaside buffer associated with the particular port, and generating a second physical access request by the MMU circuit for a physical address corresponding to a virtual address of the virtual memory pre-fetch request; monitoring, by a translation lookaside buffer, TLB, pre-fetch filter circuit (108, 204), physical access requests from the MMU circuit (114, 214) for physical addresses corresponding to the virtual memory pre-fetch requests; and preventing, by the TLB pre-fetch filter circuit (116, 118, 120), each second physical access request corresponding to one of the virtual memory pre-fetch requests from reaching a memory. monitoring by a translation lookaside buffer, TLB, pre-fetch circuit, virtual memory access requests sent to a particular port (124, 126, 128) of the MMU circuit (114, 214); detecting satisfaction of at least one trigger condition that is based upon the virtual memory access requests; generating, in response to the satisfaction of the trigger condition, virtual memory pre-fetch requests by the TLB pre-fetch circuit; transmitting the virtual memory pre-fetch requests to the MMU circuit (114, 214) using the particular port (124, 126, 128); in response to each virtual memory pre-fetch request, generating a first physical access request for a page table entry by the MMU circuit, storing the page table entry in a respective translation lookaside buffer associated with the particular port, and generating a second physical access request by the MMU circuit for a physical address corresponding to a virtual address of the virtual memory pre-fetch request; generating a first physical access request for a page table entry by the MMU circuit, storing the page table entry in a respective translation lookaside buffer associated with the particular port, and generating a second physical access request by the MMU circuit for a physical address corresponding to a virtual address of the virtual memory pre-fetch request; monitoring, by a translation lookaside buffer, TLB, pre-fetch filter circuit (108, 204), physical access requests from the MMU circuit (114, 214) for physical addresses corresponding to the virtual memory pre-fetch requests; and preventing, by the TLB pre-fetch filter circuit (116, 118, 120), each second physical access request corresponding to one of the virtual memory pre-fetch requests from reaching a memory.