An array substrate, having a plurality of first bottom-gate type thin film transistors each of which comprising a metal oxide active layer and a plurality of second bottom-gate type thin film transistors each of which comprising a silicon active layer; characterized in that the array substrate comprises: a base substrate; a gate electrode layer on the base substrate and comprising a plurality of first gate electrodes respectively for the plurality of first bottom-gate type thin film transistors and a plurality of second gate electrodes respectively for the plurality of second bottom-gate type thin film transistors; a gate insulating layer on a side of the gate electrode layer distal to the base substrate; a metal oxide layer comprising a plurality of metal oxide active layers respectively for the plurality of first bottom-gate type thin film transistors, each of the plurality of metal oxide active layers on a side of the gate insulating layer distal to one of the plurality of first gate electrodes; and a polysilicon layer comprising a plurality of polycrystalline silicon active layers respectively for the plurality of second bottom-gate type thin film transistors, each of the plurality of polycrystalline silicon active layers on a side of the gate insulating layer distal to one of the plurality of second gate electrodes; a first insulating layer on a side of the polysilicon layer distal to the gate insulating layer; and a second insulating layer on a side of the metal oxide layer distal to the first insulating layer; wherein the first insulating layer is between the polysilicon layer and the metal oxide layer; the array substrate further comprises a source-drain electrode layer comprising a plurality of first source electrodes, a plurality of first drain electrodes, a plurality of second source electrodes, and a plurality of second drain electrodes; each of the plurality of metal oxide active layers is electrically connected to one of the plurality of first source electrodes and one of the plurality of first drain electrodes through vias extending through the second insulating layer; and each of the plurality of polycrystalline silicon active layers is electrically connected to one of the plurality of second source electrodes and one of the plurality of second drain electrodes through vias extending through the first insulating layer and the second insulating layer; the array substrate further comprises a passivation layer on a side of the source-drain electrode layer distal to the second insulating layer; a first electrode layer on a side of the passivation layer distal to the source-drain electrode layer; and a second electrode layer on a side of the first electrode layer distal to the base substrate; wherein the first electrode layer and the second electrode layer are two different layers selected from a pixel electrode layer and a common electrode layer. a base substrate; a gate electrode layer on the base substrate and comprising a plurality of first gate electrodes respectively for the plurality of first bottom-gate type thin film transistors and a plurality of second gate electrodes respectively for the plurality of second bottom-gate type thin film transistors; a gate insulating layer on a side of the gate electrode layer distal to the base substrate; a metal oxide layer comprising a plurality of metal oxide active layers respectively for the plurality of first bottom-gate type thin film transistors, each of the plurality of metal oxide active layers on a side of the gate insulating layer distal to one of the plurality of first gate electrodes; and a polysilicon layer comprising a plurality of polycrystalline silicon active layers respectively for the plurality of second bottom-gate type thin film transistors, each of the plurality of polycrystalline silicon active layers on a side of the gate insulating layer distal to one of the plurality of second gate electrodes; a first insulating layer on a side of the polysilicon layer distal to the gate insulating layer; and a second insulating layer on a side of the metal oxide layer distal to the first insulating layer; wherein the first insulating layer is between the polysilicon layer and the metal oxide layer; the array substrate further comprises a source-drain electrode layer comprising a plurality of first source electrodes, a plurality of first drain electrodes, a plurality of second source electrodes, and a plurality of second drain electrodes; each of the plurality of metal oxide active layers is electrically connected to one of the plurality of first source electrodes and one of the plurality of first drain electrodes through vias extending through the second insulating layer; and each of the plurality of polycrystalline silicon active layers is electrically connected to one of the plurality of second source electrodes and one of the plurality of second drain electrodes through vias extending through the first insulating layer and the second insulating layer; the array substrate further comprises a passivation layer on a side of the source-drain electrode layer distal to the second insulating layer; a first electrode layer on a side of the passivation layer distal to the source-drain electrode layer; and a second electrode layer on a side of the first electrode layer distal to the base substrate; wherein the first electrode layer and the second electrode layer are two different layers selected from a pixel electrode layer and a common electrode layer.