A power management apparatus configured to receive temperature data from a temperature sensor of an image sensor including an SRAM, said power management apparatus comprising: a power management unit comprising: a plurality of storage devices, wherein each storage device stores a different predetermined threshold temperature value; and a plurality of compare circuits, each compare circuit coupled to the temperature sensor and configured to: compare the temperature data with one of the threshold temperature values; and transmit a signal corresponding to a result of the comparison; an application processor unit coupled to the power management unit and responsive to the transmitted signal from any compare circuit from the plurality of compare circuits, wherein the application processor unit implements a predetermined power management scheme, based on the transmitted signal from any compare circuit from the plurality of compare circuits, to control: a timing circuit coupled to the application processor unit and responsive to the implemented power management scheme, wherein the timing circuit increases or decreases a readout time of the image sensor according to the selected power management scheme; characterized in that the application processor unit controls the SRAM, wherein the SRAM comprises a plurality of SRAM bit cells, wherein the SRAM is coupled to the application processor unit and responsive to the implemented power management scheme, and wherein the SRAM bit cells enter at least one of a leakage mitigation state and a standby state according to the selected power management scheme. a power management unit comprising: a plurality of storage devices, wherein each storage device stores a different predetermined threshold temperature value; and a plurality of compare circuits, each compare circuit coupled to the temperature sensor and configured to: compare the temperature data with one of the threshold temperature values; and transmit a signal corresponding to a result of the comparison; a plurality of storage devices, wherein each storage device stores a different predetermined threshold temperature value; and a plurality of compare circuits, each compare circuit coupled to the temperature sensor and configured to: compare the temperature data with one of the threshold temperature values; and transmit a signal corresponding to a result of the comparison; compare the temperature data with one of the threshold temperature values; and transmit a signal corresponding to a result of the comparison; an application processor unit coupled to the power management unit and responsive to the transmitted signal from any compare circuit from the plurality of compare circuits, wherein the application processor unit implements a predetermined power management scheme, based on the transmitted signal from any compare circuit from the plurality of compare circuits, to control: a timing circuit coupled to the application processor unit and responsive to the implemented power management scheme, wherein the timing circuit increases or decreases a readout time of the image sensor according to the selected power management scheme; characterized in that the application processor unit controls the SRAM, wherein the SRAM comprises a plurality of SRAM bit cells, wherein the SRAM is coupled to the application processor unit and responsive to the implemented power management scheme, and wherein the SRAM bit cells enter at least one of a leakage mitigation state and a standby state according to the selected power management scheme. a timing circuit coupled to the application processor unit and responsive to the implemented power management scheme, wherein the timing circuit increases or decreases a readout time of the image sensor according to the selected power management scheme; characterized in that the application processor unit controls the SRAM, wherein the SRAM comprises a plurality of SRAM bit cells, wherein the SRAM is coupled to the application processor unit and responsive to the implemented power management scheme, and wherein the SRAM bit cells enter at least one of a leakage mitigation state and a standby state according to the selected power management scheme.