An insulated gate power semiconductor device, comprises in an order from a first main side towards a second main side opposite to the 5 first main side: a source layer of a first conductivity type, wherein the first conductivity type is either n-type or p-type; a base layer of a second conductivity type, wherein the second conductivity type is different from the first conductivity type and wherein the base layer is in direct contact with the source layer to form a first pn junction; an enhancement layer of the first conductivity type which is in direct contact with the base layer to form a second pn junction; and a drift layer of the first conductivity type; the insulated gate power semiconductor device further comprising two neighbouring trench gate electrodes arranged at the first main side and extending in a direction towards the second main side, each of the two trench gate electrodes having an electrically conductive gate layer, which is separated from the source layer, the base layer, the enhancement layer and the drift layer by a gate insulating layer to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes, the insulated gate power semiconductor device further comprising a protection layer of the second conductivity type arranged below the enhancement layer wherein at least a portion of the protection layer is arranged in an area between the two neighbouring trench gate electrodes, wherein the protection layer is separated from the gate insulating layer by a channel layer of the first conductivity type extending along the gate insulating layer characterized in that the protection layer extends from the area between the two neighbouring trench gate electrodes to a region below the neighbouring trench gate electrodes, so that in an orthogonal projection onto 30 a plane parallel to the first main side, the protection layer overlaps with the two neighbouring trench gate electrodes. a source layer of a first conductivity type, wherein the first conductivity type is either n-type or p-type; a base layer of a second conductivity type, wherein the second conductivity type is different from the first conductivity type and wherein the base layer is in direct contact with the source layer to form a first pn junction; an enhancement layer of the first conductivity type which is in direct contact with the base layer to form a second pn junction; and a drift layer of the first conductivity type; the insulated gate power semiconductor device further comprising two neighbouring trench gate electrodes arranged at the first main side and extending in a direction towards the second main side, each of the two trench gate electrodes having an electrically conductive gate layer, which is separated from the source layer, the base layer, the enhancement layer and the drift layer by a gate insulating layer to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes, the insulated gate power semiconductor device further comprising a protection layer of the second conductivity type arranged below the enhancement layer wherein at least a portion of the protection layer is arranged in an area between the two neighbouring trench gate electrodes, wherein the protection layer is separated from the gate insulating layer by a channel layer of the first conductivity type extending along the gate insulating layer characterized in that the protection layer extends from the area between the two neighbouring trench gate electrodes to a region below the neighbouring trench gate electrodes, so that in an orthogonal projection onto 30 a plane parallel to the first main side, the protection layer overlaps with the two neighbouring trench gate electrodes.