A neural network computation circuit that includes a non-volatile semiconductor memory and is configured to output output data of a first logical value or a second logical value, based on a result of a multiply-accumulate operation between input data (x 0 to x n) of the first logical value or the second logical value and connection weight coefficients (w 0 to w n), respectively, corresponding to the input data (x 0 to x n), the neural network computation circuit comprising: a plurality of word lines (WLO to WLn); a first data line; a second data line; a third data line; a fourth data line; a plurality of computation units (PU0 to PU n), wherein each of the plurality of computation units (PU0 to PU n) includes a series connection of a corresponding first non-volatile semiconductor memory element and a corresponding first cell transistor, and a series connection of a corresponding second non-volatile semiconductor memory element and a corresponding second cell transistor, the corresponding first non-volatile semiconductor memory element having one end connected to the first data line, the corresponding first cell transistor having one end connected to the second data line, the corresponding second non-volatile semiconductor memory element having one end connected to the third data line, the corresponding second cell transistor having one end connected to the fourth data line; a word line selection circuit that is configured to place the plurality of word lines (WLO to WLn) in a selection state or a non-selection state according to the input data; and wherein the neural network computation circuit is configured to store each of the connection weight coefficients (w 0 to w n) in the corresponding first non-volatile semiconductor memory element and the corresponding second non-volatile semiconductor memory element of the corresponding computation unit (PU0 to PU n), characterized in that in each of the plurality of computation units (PU0 to PU n), the corresponding first cell transistor has a gate connected to a corresponding one (WL i) of the plurality of word lines (WLO to WLn) and the corresponding second cell transistor has a gate connected to the corresponding one (WL i) of plurality of word lines (WLO to WLn); and, the neural network computation circuit further includes a determination circuit that is configured to, when a neural network computational operation is performed, determine a magnitude relationship between current values (I pi I ni) flowing in the first data line and the third data line, to output as the output data the first logical value or the second logical value, the neural network computation circuit being such that when the neural network computational operation is performed the first data line and the third data line are connected to the determination circuit and the second data line and the fourth data line are connected to ground. a plurality of word lines (WLO to WLn); a first data line; a second data line; a third data line; a fourth data line; a plurality of computation units (PU0 to PU n), wherein each of the plurality of computation units (PU0 to PU n) includes a series connection of a corresponding first non-volatile semiconductor memory element and a corresponding first cell transistor, and a series connection of a corresponding second non-volatile semiconductor memory element and a corresponding second cell transistor, the corresponding first non-volatile semiconductor memory element having one end connected to the first data line, the corresponding first cell transistor having one end connected to the second data line, the corresponding second non-volatile semiconductor memory element having one end connected to the third data line, the corresponding second cell transistor having one end connected to the fourth data line; a word line selection circuit that is configured to place the plurality of word lines (WLO to WLn) in a selection state or a non-selection state according to the input data; and wherein the neural network computation circuit is configured to store each of the connection weight coefficients (w 0 to w n) in the corresponding first non-volatile semiconductor memory element and the corresponding second non-volatile semiconductor memory element of the corresponding computation unit (PU0 to PU n), characterized in that in each of the plurality of computation units (PU0 to PU n), the corresponding first cell transistor has a gate connected to a corresponding one (WL i) of the plurality of word lines (WLO to WLn) and the corresponding second cell transistor has a gate connected to the corresponding one (WL i) of plurality of word lines (WLO to WLn); and, the neural network computation circuit further includes a determination circuit that is configured to, when a neural network computational operation is performed, determine a magnitude relationship between current values (I pi I ni) flowing in the first data line and the third data line, to output as the output data the first logical value or the second logical value, the neural network computation circuit being such that when the neural network computational operation is performed the first data line and the third data line are connected to the determination circuit and the second data line and the fourth data line are connected to ground.