A relaxation oscillator with an aging effect reduction technique, comprising: - a comparator having a first input node and a second input node, wherein a reference signal (VRP, VRN) is applied to at least one of the first and the second input node (CP1, CP2) of the comparator, - at least one capacitor being connected to at least one of the first and the second input node (CP1, CP2) of the comparator, - a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11,..., SW8) being controlled during different operational cycles of the relaxation oscillator, - wherein the plurality of controllable switches (SW11,..., SW8, SW111,..., SW180) are controlled during one of the operational cycles of the relaxation oscillator such that a charging current to charge the at least one capacitor (C, C1, C2) is generated and flows through at least a first one of the plurality of transistors, and a reference current to provide the reference signal (VRP, VRN) is generated and flows through at least a second one of the transistors, - wherein the plurality of controllable switches (SW11,..., SW8) are controlled during a subsequent one of the operational cycles of the relaxation oscillator such that a discharging current to discharge the at least one capacitor is generated and flows through at least a third one of the plurality of transistors, and the reference current to provide the reference signal (VRP, VRN) is generated and flows through at least a fourth one of the transistors, - wherein the first and the second transistor (M1, M2) are swapped to be part of a respective charging current path to provide the charging current, and the third and fourth transistor (M3, M4) are swapped to be part of a first and second reference current path to provide the reference current during two different charging cycles (OC2, OC4) of the operational cycles, and - wherein the third and fourth transistor (M3, M4) are swapped to be part of a respective discharging current path to provide the discharging current, and the first and second transistors (M1, M2) are swapped to be part of a third and fourth reference current path to provide the reference current during two different discharging cycles (OC1, OC3) of the operational cycles. - a comparator having a first input node and a second input node, wherein a reference signal (VRP, VRN) is applied to at least one of the first and the second input node (CP1, CP2) of the comparator, - at least one capacitor being connected to at least one of the first and the second input node (CP1, CP2) of the comparator, - a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11,..., SW8) being controlled during different operational cycles of the relaxation oscillator, - wherein the plurality of controllable switches (SW11,..., SW8, SW111,..., SW180) are controlled during one of the operational cycles of the relaxation oscillator such that a charging current to charge the at least one capacitor (C, C1, C2) is generated and flows through at least a first one of the plurality of transistors, and a reference current to provide the reference signal (VRP, VRN) is generated and flows through at least a second one of the transistors, - wherein the plurality of controllable switches (SW11,..., SW8) are controlled during a subsequent one of the operational cycles of the relaxation oscillator such that a discharging current to discharge the at least one capacitor is generated and flows through at least a third one of the plurality of transistors, and the reference current to provide the reference signal (VRP, VRN) is generated and flows through at least a fourth one of the transistors, - wherein the first and the second transistor (M1, M2) are swapped to be part of a respective charging current path to provide the charging current, and the third and fourth transistor (M3, M4) are swapped to be part of a first and second reference current path to provide the reference current during two different charging cycles (OC2, OC4) of the operational cycles, and - wherein the third and fourth transistor (M3, M4) are swapped to be part of a respective discharging current path to provide the discharging current, and the first and second transistors (M1, M2) are swapped to be part of a third and fourth reference current path to provide the reference current during two different discharging cycles (OC1, OC3) of the operational cycles.