A semiconductor device having a power-on reset circuit, the power-on reset circuit comprising: a first node for supplying a ground voltage; a second node for supplying a power supply voltage; a third node; a fourth node; a fifth node; a sixth node that is connected to the first node; a first bipolar transistor having an emitter that is connected to the sixth node and a collector that is connected to the fourth node; a second bipolar transistor having an emitter that is connected to the sixth node and having a collector that is connected to the fifth node, and being configured so that N bipolar transistors are connected in parallel; a comparator having an inverting input terminal that is connected to the fifth node, a non-inverting input terminal that is connected to the fourth node and to a base of the second bipolar transistor, and an output terminal; a first resistance element connected at one end to the third node and at the other end to the fourth node to generate a first current (I 1) having a positive temperature characteristic in which a current value increases as temperature rises; a second resistance element connected at one end to the third node and the base of the first bipolar transistor and at the other end to the sixth mode to generate a second current (I 2) having a negative temperature characteristic in which a current value decreases as temperature rises; a third resistance element connected at one end to the third node and at the other end to the fifth node to generate a third current (I 3) having the positive temperature characteristic, the first and third resistance elements (14, 17) having a same resistance value; and a fourth resistance element connected at one end to the second node and at the other end to the third node so as to carry a fourth current that is a total current of the first current (I 1), second current (I 2), and third current (I 3), wherein the power-on reset circuit is configured so that the output of the comparator is reversed when the first current (I 1) and the third current (I 3) are equal to each other, and wherein the semiconductor device further comprises: a PMOS transistor configured to output a high level of the power-on reset circuit, the output terminal of the comparator being connected to a gate of the PMOS transistor, a source of the PMOS transistor being connected to the second node; and a fifth resistance element connected at one end to a drain of the PMOS transistor and at the other end to the first node, and being configured to output a low level of the power-on reset circuit. a first node for supplying a ground voltage; a second node for supplying a power supply voltage; a third node; a fourth node; a fifth node; a sixth node that is connected to the first node; a first bipolar transistor having an emitter that is connected to the sixth node and a collector that is connected to the fourth node; a second bipolar transistor having an emitter that is connected to the sixth node and having a collector that is connected to the fifth node, and being configured so that N bipolar transistors are connected in parallel; a comparator having an inverting input terminal that is connected to the fifth node, a non-inverting input terminal that is connected to the fourth node and to a base of the second bipolar transistor, and an output terminal; a first resistance element connected at one end to the third node and at the other end to the fourth node to generate a first current (I 1) having a positive temperature characteristic in which a current value increases as temperature rises; a second resistance element connected at one end to the third node and the base of the first bipolar transistor and at the other end to the sixth mode to generate a second current (I 2) having a negative temperature characteristic in which a current value decreases as temperature rises; a third resistance element connected at one end to the third node and at the other end to the fifth node to generate a third current (I 3) having the positive temperature characteristic, the first and third resistance elements (14, 17) having a same resistance value; and a fourth resistance element connected at one end to the second node and at the other end to the third node so as to carry a fourth current that is a total current of the first current (I 1), second current (I 2), and third current (I 3), wherein the power-on reset circuit is configured so that the output of the comparator is reversed when the first current (I 1) and the third current (I 3) are equal to each other, and wherein the semiconductor device further comprises: a PMOS transistor configured to output a high level of the power-on reset circuit, the output terminal of the comparator being connected to a gate of the PMOS transistor, a source of the PMOS transistor being connected to the second node; and a fifth resistance element connected at one end to a drain of the PMOS transistor and at the other end to the first node, and being configured to output a low level of the power-on reset circuit.