A processor comprising: decoding circuitry to decode an instruction, wherein the instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, wherein each index of the plurality of indices maps to one unique data element position of the first input register; and execution circuitry to execute the decoded instruction, wherein the execution includes to: identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register, wherein: the instruction is executed by two or more computing units (1970, 1972), each of the two or more computing units (1970, 1972) executing a portion of the data element values; the two or more computing units (1970, 1972) are synchronized in performing the one or more reduction operations, and the instruction further specifies a location that stores a value indicating whether the two or more computing units (1970, 1972) are synchronized, wherein the instruction further specifies a second input register containing another plurality of data element values, and a second index register containing another plurality of indices, each index of the another plurality of indices mapping to one unique data element position of the second input register, and wherein the one or more reduction operations are performed on the data element values of the first and second input registers based on indices of the first and second index registers. decoding circuitry to decode an instruction, wherein the instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, wherein each index of the plurality of indices maps to one unique data element position of the first input register; and execution circuitry to execute the decoded instruction, wherein the execution includes to: identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register, identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register, wherein: the instruction is executed by two or more computing units (1970, 1972), each of the two or more computing units (1970, 1972) executing a portion of the data element values; the two or more computing units (1970, 1972) are synchronized in performing the one or more reduction operations, and the instruction further specifies a location that stores a value indicating whether the two or more computing units (1970, 1972) are synchronized, the instruction is executed by two or more computing units (1970, 1972), each of the two or more computing units (1970, 1972) executing a portion of the data element values; the two or more computing units (1970, 1972) are synchronized in performing the one or more reduction operations, and the instruction further specifies a location that stores a value indicating whether the two or more computing units (1970, 1972) are synchronized, wherein the instruction further specifies a second input register containing another plurality of data element values, and a second index register containing another plurality of indices, each index of the another plurality of indices mapping to one unique data element position of the second input register, and wherein the one or more reduction operations are performed on the data element values of the first and second input registers based on indices of the first and second index registers.