A device comprising: an integrated circuit having input terminals; internal circuitry (140, 160, 163); a clock circuit on the integrated circuit, the clock circuit being configured to provide a unique internal clock signal (INT CLK) to the internal circuitry (140, 160, 163), the clock circuit having clock inputs electrically connected to a plurality of the input terminals, and the clock circuit being configurable to produce the internal clock signal using a single input terminal or multiple input terminals of the plurality of input terminals in response to a configuration parameter, the multiple input terminals comprising the single input terminal and another input terminal, the single input terminal being used for compatibility with an external single phase clock interface, the multiple input terminals being used for compatibility with an external multi phase clock interface; and a clock configuration store (149, 225) configured to provide the configuration parameter, wherein the clock circuit includes - a first sub-circuit (213A, 233A) configured to produce a first clock signal using the single input terminal of the plurality of input terminals, - a second sub-circuit (213B, 233B) configured to produce a second clock signal using the single input terminal and the another input terminal, and - a selection circuit (220, 240), responsive to the configuration parameter, configured to select one of the first and second sub-circuits to provide the first or second clock signal as the internal clock signal (INT CLK), wherein the first sub-circuit and the second sub-circuit include circuitry to produce the first clock signal and second clock signal in a common format used by the internal circuitry, wherein the first sub-circuit comprises a single phase clock buffer, and the second sub-circuit comprises a two-phase clock buffer, wherein the single phase clock buffer and the two-phase clock buffer include the circuitry to produce the first clock signal and the second clock signal in the common format used by the internal circuitry, and wherein the common format matches a format required by the internal circuitry and is one of a single phase clock provided on a single signal line being provided to the internal circuit, a differential format, a two-phase clock format and a multiphase clock format. an integrated circuit having input terminals; internal circuitry (140, 160, 163); a clock circuit on the integrated circuit, the clock circuit being configured to provide a unique internal clock signal (INT CLK) to the internal circuitry (140, 160, 163), the clock circuit having clock inputs electrically connected to a plurality of the input terminals, and the clock circuit being configurable to produce the internal clock signal using a single input terminal or multiple input terminals of the plurality of input terminals in response to a configuration parameter, the multiple input terminals comprising the single input terminal and another input terminal, the single input terminal being used for compatibility with an external single phase clock interface, the multiple input terminals being used for compatibility with an external multi phase clock interface; and a clock configuration store (149, 225) configured to provide the configuration parameter, wherein the clock circuit includes - a first sub-circuit (213A, 233A) configured to produce a first clock signal using the single input terminal of the plurality of input terminals, - a second sub-circuit (213B, 233B) configured to produce a second clock signal using the single input terminal and the another input terminal, and - a selection circuit (220, 240), responsive to the configuration parameter, configured to select one of the first and second sub-circuits to provide the first or second clock signal as the internal clock signal (INT CLK), wherein the first sub-circuit and the second sub-circuit include circuitry to produce the first clock signal and second clock signal in a common format used by the internal circuitry, - a first sub-circuit (213A, 233A) configured to produce a first clock signal using the single input terminal of the plurality of input terminals, - a second sub-circuit (213B, 233B) configured to produce a second clock signal using the single input terminal and the another input terminal, and - a selection circuit (220, 240), responsive to the configuration parameter, configured to select one of the first and second sub-circuits to provide the first or second clock signal as the internal clock signal (INT CLK), wherein the first sub-circuit and the second sub-circuit include circuitry to produce the first clock signal and second clock signal in a common format used by the internal circuitry, wherein the first sub-circuit comprises a single phase clock buffer, and the second sub-circuit comprises a two-phase clock buffer, wherein the single phase clock buffer and the two-phase clock buffer include the circuitry to produce the first clock signal and the second clock signal in the common format used by the internal circuitry, and wherein the common format matches a format required by the internal circuitry and is one of a single phase clock provided on a single signal line being provided to the internal circuit, a differential format, a two-phase clock format and a multiphase clock format.