An organic light emitting display comprising: a display panel having a plurality of pixels; a gate drive circuit that drives n scan lines (SL1,... SL(n), n being a natural number) and n emission lines (EL1,..., EL(n)) on the display panel; and a data drive circuit that drives data lines on the display panel, each of the pixels arranged in a jth row (1<j≤n) comprising: a driving transistor having a gate electrode connected to a node A, a source electrode connected to a node B, and a drain electrode connected to a node C, and the driving transistor controlling a driving current applied to an organic light emitting diode (OLED); a first transistor that is connected between the data lines and the node B; a second transistor that is connected between the node A and a high-level driving voltage input terminal (ELVDD); a third transistor that is connected to the node B and the organic light emitting diode (OLED); a fourth transistor that is connected to the node C and the high-level driving voltage input terminal; a fifth transistor that is connected to the node A and the node C; a sixth transistor that is connected between a node D and an initial voltage input terminal (Vini), the node D located between the third transistor and the organic light emitting diode (OLED); and a capacitor (Cst) that is connected to the node A and the node D; wherein the gate of the second transistor is connected to a scan line (SL(j-1)) of a (j-1)th row of pixels; the gates of the third and fourth transistors (T3, T4) are connected to the emission line (EM(j)) of the jth row of pixels; the gates of the first and fifth transistors (T1, T5) are connected to the scan line (SL(j)) of the jth row of pixels; the gate of the sixth transistor is connected either to the scan line (SL(j)) of the jth row of pixels or to the scan line (SL(j-1)) of the (j-1)th row of pixels; and a cathode of the organic light emitting diode (OLED) is connected to a low-level driving voltage input terminal (ELVSS). a display panel having a plurality of pixels; a gate drive circuit that drives n scan lines (SL1,... SL(n), n being a natural number) and n emission lines (EL1,..., EL(n)) on the display panel; and a data drive circuit that drives data lines on the display panel, each of the pixels arranged in a jth row (1<j≤n) comprising: a driving transistor having a gate electrode connected to a node A, a source electrode connected to a node B, and a drain electrode connected to a node C, and the driving transistor controlling a driving current applied to an organic light emitting diode (OLED); a first transistor that is connected between the data lines and the node B; a second transistor that is connected between the node A and a high-level driving voltage input terminal (ELVDD); a third transistor that is connected to the node B and the organic light emitting diode (OLED); a fourth transistor that is connected to the node C and the high-level driving voltage input terminal; a fifth transistor that is connected to the node A and the node C; a sixth transistor that is connected between a node D and an initial voltage input terminal (Vini), the node D located between the third transistor and the organic light emitting diode (OLED); and a capacitor (Cst) that is connected to the node A and the node D; a driving transistor having a gate electrode connected to a node A, a source electrode connected to a node B, and a drain electrode connected to a node C, and the driving transistor controlling a driving current applied to an organic light emitting diode (OLED); a first transistor that is connected between the data lines and the node B; a second transistor that is connected between the node A and a high-level driving voltage input terminal (ELVDD); a third transistor that is connected to the node B and the organic light emitting diode (OLED); a fourth transistor that is connected to the node C and the high-level driving voltage input terminal; a fifth transistor that is connected to the node A and the node C; a sixth transistor that is connected between a node D and an initial voltage input terminal (Vini), the node D located between the third transistor and the organic light emitting diode (OLED); and a capacitor (Cst) that is connected to the node A and the node D; wherein the gate of the second transistor is connected to a scan line (SL(j-1)) of a (j-1)th row of pixels; the gates of the third and fourth transistors (T3, T4) are connected to the emission line (EM(j)) of the jth row of pixels; the gates of the first and fifth transistors (T1, T5) are connected to the scan line (SL(j)) of the jth row of pixels; the gate of the sixth transistor is connected either to the scan line (SL(j)) of the jth row of pixels or to the scan line (SL(j-1)) of the (j-1)th row of pixels; and a cathode of the organic light emitting diode (OLED) is connected to a low-level driving voltage input terminal (ELVSS).