A storage cell comprising: a bit line, a magnetic tunnel junction, and four access transistors (11, 12, 13, 14); sources of the access transistors (11, 12, 13, 14) being electrically connected to a first end of the magnetic tunnel junction; a second end of the magnetic tunnel junction being all electrically connected to the bit line; and the bit line extending along a first direction; and active regions corresponding to the access transistors (11, 12, 13, 14) being isolated from each other; each active region of each access transistor of the storage cell including a source, a drain and a channel region, the source and the drain being located on two opposite sides of the channel region respectively, each access transistor further including a gate; long-side extension directions of the active regions corresponding to the access transistors (11, 12, 13, 14) being the same, and a first angle θ being formed between the long-side extension directions of the active regions and the first direction; wherein the angle θ ≠ n ∗ π 2, n ≥ 0, n being a natural number, wherein the four access transistors (11, 12, 13, 14) comprise a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor; a long side of an active region of the first access transistor is disposed opposite to a long side of an active region of the second access transistor, and an active region of the third access transistor and an active region of the fourth access transistor are located between the active region of the first access transistor and the active region of the second access transistor; and a short side of the active region of the third access transistor is disposed opposite in a direction along the extension direction of the active regions to a short side of the active region of the fourth access transistor. sources of the access transistors (11, 12, 13, 14) being electrically connected to a first end of the magnetic tunnel junction; a second end of the magnetic tunnel junction being all electrically connected to the bit line; and the bit line extending along a first direction; and active regions corresponding to the access transistors (11, 12, 13, 14) being isolated from each other; each active region of each access transistor of the storage cell including a source, a drain and a channel region, the source and the drain being located on two opposite sides of the channel region respectively, each access transistor further including a gate; long-side extension directions of the active regions corresponding to the access transistors (11, 12, 13, 14) being the same, and a first angle θ being formed between the long-side extension directions of the active regions and the first direction; wherein the angle θ ≠ n ∗ π 2, n ≥ 0, n being a natural number, wherein the four access transistors (11, 12, 13, 14) comprise a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor; a long side of an active region of the first access transistor is disposed opposite to a long side of an active region of the second access transistor, and an active region of the third access transistor and an active region of the fourth access transistor are located between the active region of the first access transistor and the active region of the second access transistor; and a short side of the active region of the third access transistor is disposed opposite in a direction along the extension direction of the active regions to a short side of the active region of the fourth access transistor.