A shift register circuit comprising: a first transistor, a control electrode of the first transistor being coupled to a first clock signal terminal, a first electrode of the first transistor being coupled to a first voltage terminal, and a second electrode of the first transistor being coupled to a second denoising control node (PD-ox-i); a first capacitor, a first terminal of the first capacitor being coupled to a second clock signal terminal, and a second terminal of the first capacitor being coupled to the second denoising control node (PD-ox-i); a second transistor, a control electrode of the second transistor being coupled to the second denoising control node (PD-ox-i), a first electrode of the second transistor being coupled to a first denoising control node (PD-ox), and a second electrode of the second transistor being coupled to the second denoising control node (PD-ox-i); a second capacitor, a first terminal of the second capacitor being coupled to a first signal terminal, and a second terminal of the second capacitor being coupled to the first denoising control node (PD-ox); a sixth transistor, a control electrode of the sixth transistor being coupled to the first denoising control node (PD-ox), a first electrode of the sixth transistor being coupled to the first voltage terminal, and a second electrode of the sixth transistor being coupled to a scan signal output terminal (Oput); a third transistor, a control electrode of the third transistor being coupled to a cascade signal output terminal, a first electrode of the third transistor being coupled to a second signal terminal, and a second electrode of the third transistor being coupled to the second denoising control node (PD-ox-i); a fourth transistor, a control electrode of the fourth transistor being coupled to the cascade signal output terminal, a first electrode of the fourth transistor being coupled to the second signal terminal, and a second electrode of the fourth transistor being coupled to the first denoising control node (PD-ox), and a fifteenth transistor, a control electrode of the fifteenth transistor coupled to a third input terminal, a first electrode of the fifteenth transistor being coupled to a fourth input terminal, and a second electrode of the fifteenth transistor being coupled to the scan signal output terminal (Oput). a first transistor, a control electrode of the first transistor being coupled to a first clock signal terminal, a first electrode of the first transistor being coupled to a first voltage terminal, and a second electrode of the first transistor being coupled to a second denoising control node (PD-ox-i); a first capacitor, a first terminal of the first capacitor being coupled to a second clock signal terminal, and a second terminal of the first capacitor being coupled to the second denoising control node (PD-ox-i); a second transistor, a control electrode of the second transistor being coupled to the second denoising control node (PD-ox-i), a first electrode of the second transistor being coupled to a first denoising control node (PD-ox), and a second electrode of the second transistor being coupled to the second denoising control node (PD-ox-i); a second capacitor, a first terminal of the second capacitor being coupled to a first signal terminal, and a second terminal of the second capacitor being coupled to the first denoising control node (PD-ox); a sixth transistor, a control electrode of the sixth transistor being coupled to the first denoising control node (PD-ox), a first electrode of the sixth transistor being coupled to the first voltage terminal, and a second electrode of the sixth transistor being coupled to a scan signal output terminal (Oput); a third transistor, a control electrode of the third transistor being coupled to a cascade signal output terminal, a first electrode of the third transistor being coupled to a second signal terminal, and a second electrode of the third transistor being coupled to the second denoising control node (PD-ox-i); a fourth transistor, a control electrode of the fourth transistor being coupled to the cascade signal output terminal, a first electrode of the fourth transistor being coupled to the second signal terminal, and a second electrode of the fourth transistor being coupled to the first denoising control node (PD-ox), and a fifteenth transistor, a control electrode of the fifteenth transistor coupled to a third input terminal, a first electrode of the fifteenth transistor being coupled to a fourth input terminal, and a second electrode of the fifteenth transistor being coupled to the scan signal output terminal (Oput).