A trench gate MOS semiconductor device comprising: a second-conductivity-type floating region that is provided in a surface layer of one main surface of a first-conductivity-type semiconductor substrate which is a drift layer; a plurality of trenches arranged in a parallel pattern that reach a predetermined depth from the surface of the first-conductivity-type semiconductor substrate; a second-conductivity-type base region that is formed in a surface layer of a portion of the first-conductivity-type semiconductor substrate which is interposed between the plurality of trenches and is separated from the second-conductivity-type floating region by the trench; a first-conductivity-type emitter region that is formed in a surface layer of the second-conductivity-type base region so as to come into contact with the trench; wherein the first-conductivity-type is an n-type and the second-conductivity-type is a p-type, or the first-conductivity-type is a p-type and the second-conductivity-type is an n-type; an emitter electrode that comes into contact with the second-conductivity-type base region and the first-conductivity-type emitter region and covers the second-conductivity-type floating region, with an interlayer insulating film interposed therebetween; and a first conductive polysilicon electrode and a second conductive polysilicon electrode that are formed in the trench along both side surfaces of the trench so as to be separated from each other and are connected to different electrodes; characterized by a cavity which is surrounded by an insulating film and is entirely interposed between the first conductive polysilicon electrode and the second conductive polysilicon electrode. a second-conductivity-type floating region that is provided in a surface layer of one main surface of a first-conductivity-type semiconductor substrate which is a drift layer; a plurality of trenches arranged in a parallel pattern that reach a predetermined depth from the surface of the first-conductivity-type semiconductor substrate; a second-conductivity-type base region that is formed in a surface layer of a portion of the first-conductivity-type semiconductor substrate which is interposed between the plurality of trenches and is separated from the second-conductivity-type floating region by the trench; a first-conductivity-type emitter region that is formed in a surface layer of the second-conductivity-type base region so as to come into contact with the trench; wherein the first-conductivity-type is an n-type and the second-conductivity-type is a p-type, or the first-conductivity-type is a p-type and the second-conductivity-type is an n-type; an emitter electrode that comes into contact with the second-conductivity-type base region and the first-conductivity-type emitter region and covers the second-conductivity-type floating region, with an interlayer insulating film interposed therebetween; and a first conductive polysilicon electrode and a second conductive polysilicon electrode that are formed in the trench along both side surfaces of the trench so as to be separated from each other and are connected to different electrodes; a cavity which is surrounded by an insulating film and is entirely interposed between the first conductive polysilicon electrode and the second conductive polysilicon electrode.