A pipelined analog-to-digital converter, ADC, for converting a signal input (Vin) into a digital value, said ADC comprising a plurality of converter stages (252-1 252-2, 252-3) that are cascaded in series, each converter stage including a sample and hold module that samples and holds the analog signal from the prior stage, the first converter stage receiving said input signal (Vin) as an input for its sample and hold module; each converter stage further comprising: an analog to digital converter module for quantizing the analog signal provided by the sample and hold module of the respective converter stage in respect to a reference voltage (Vref), a digital to analog converter module (258, 300) comprising: an amplifier having an input and an output; N capacitances (C 1, C 2, C 3, C 4) that are connected in parallel and having substantially the same value and that include first ends that are selectively connected with ground, wherein N is an integer greater than 1, characterized in that N switches that connect second ends of said N capacitances (C 1, C 2, C 3, C 4) to said analog signal during a sampling phase, and selectively connect one of said second ends of said N capacitances (C 1, C 2, C 3, C 4) to said output of said amplifier, and the others of said second ends of said N capacitances to either ground or said reference voltage (Vref) during a residue amplification phase, wherein the number of second ends that are connected to ground and second ends that are connected to said reference voltage (Vref) depends on a quantization result provided by said analog to digital converter module of the respective stage, wherein if the ratio between the analog signal provided by the sample and hold module of the respective stage and the reference voltage (Vref) is between 0 and 1/N, connecting all second ends of the other capacitances to ground, and wherein if said ratio is between (N-1)/N and 1 connecting all second ends of all other capacitances to said reference voltage (Vref). an analog to digital converter module for quantizing the analog signal provided by the sample and hold module of the respective converter stage in respect to a reference voltage (Vref), a digital to analog converter module (258, 300) comprising: an amplifier having an input and an output; N capacitances (C 1, C 2, C 3, C 4) that are connected in parallel and having substantially the same value and that include first ends that are selectively connected with ground, wherein N is an integer greater than 1, characterized in that N switches that connect second ends of said N capacitances (C 1, C 2, C 3, C 4) to said analog signal during a sampling phase, and selectively connect one of said second ends of said N capacitances (C 1, C 2, C 3, C 4) to said output of said amplifier, and the others of said second ends of said N capacitances to either ground or said reference voltage (Vref) during a residue amplification phase, wherein the number of second ends that are connected to ground and second ends that are connected to said reference voltage (Vref) depends on a quantization result provided by said analog to digital converter module of the respective stage, wherein if the ratio between the analog signal provided by the sample and hold module of the respective stage and the reference voltage (Vref) is between 0 and 1/N, connecting all second ends of the other capacitances to ground, and wherein if said ratio is between (N-1)/N and 1 connecting all second ends of all other capacitances to said reference voltage (Vref). an amplifier having an input and an output; N capacitances (C 1, C 2, C 3, C 4) that are connected in parallel and having substantially the same value and that include first ends that are selectively connected with ground, wherein N is an integer greater than 1, characterized in that N switches that connect second ends of said N capacitances (C 1, C 2, C 3, C 4) to said analog signal during a sampling phase, and selectively connect one of said second ends of said N capacitances (C 1, C 2, C 3, C 4) to said output of said amplifier, and the others of said second ends of said N capacitances to either ground or said reference voltage (Vref) during a residue amplification phase, wherein the number of second ends that are connected to ground and second ends that are connected to said reference voltage (Vref) depends on a quantization result provided by said analog to digital converter module of the respective stage, wherein if the ratio between the analog signal provided by the sample and hold module of the respective stage and the reference voltage (Vref) is between 0 and 1/N, connecting all second ends of the other capacitances to ground, and wherein if said ratio is between (N-1)/N and 1 connecting all second ends of all other capacitances to said reference voltage (Vref).