A hearing instrument comprising an integrated semiconductor circuit wherein said integrated semiconductor circuit comprises: - a control and processing circuit comprising: a first audio input channel for receipt of a first audio signal, - a signal processor for receipt and processing of the first audio signal for generating a compensated microphone signal according to a hearing loss of a user; - an output amplifier for receipt of the compensated microphone signal and generation of an amplified or buffered output signal for application to a miniature receiver or loudspeaker of the hearing instrument; characterized in that the integrated semiconductor circuit further comprises: - a clock signal grid for distributing a clock signal (Clk) to one or more logic circuit regions, - a first logic circuit region powered by a positive DC supply voltage (V DD) and a negative DC supply voltage (V CC); - said first logic circuit region comprising: - a first regional clock network for supplying a first regional clock signal (R-Clk) to one or more digital logic circuits of the first logic circuit region, - a clock gating circuit configured to derive the first regional clock signal (R-Clk) from the clock signal (Clk) and selectively apply and interrupt the first regional clock signal (R-Clk) in accordance with a state select signal (En) of the first logic circuit region, - a first back bias voltage grid connected to respective bodies of PMOS transistors of the one or more digital logic circuits and a second back bias voltage grid connected to respective bodies of NMOS transistors of the one or more digital logic circuits, - a controllable back bias voltage generator configured to: - adjust a first back bias voltage (V BP) of the first back bias voltage grid between a first level and a second level in accordance with the state select signal (En); and - adjust a second back bias voltage (V BN) of the second back bias voltage grid between a first level and a second level in accordance with the state select signal (En). - a control and processing circuit comprising: a first audio input channel for receipt of a first audio signal, - a signal processor for receipt and processing of the first audio signal for generating a compensated microphone signal according to a hearing loss of a user; - an output amplifier for receipt of the compensated microphone signal and generation of an amplified or buffered output signal for application to a miniature receiver or loudspeaker of the hearing instrument; - a clock signal grid for distributing a clock signal (Clk) to one or more logic circuit regions, - a first logic circuit region powered by a positive DC supply voltage (V DD) and a negative DC supply voltage (V CC); - said first logic circuit region comprising: - a first regional clock network for supplying a first regional clock signal (R-Clk) to one or more digital logic circuits of the first logic circuit region, - a clock gating circuit configured to derive the first regional clock signal (R-Clk) from the clock signal (Clk) and selectively apply and interrupt the first regional clock signal (R-Clk) in accordance with a state select signal (En) of the first logic circuit region, - a first back bias voltage grid connected to respective bodies of PMOS transistors of the one or more digital logic circuits and a second back bias voltage grid connected to respective bodies of NMOS transistors of the one or more digital logic circuits, - a controllable back bias voltage generator configured to: - adjust a first back bias voltage (V BP) of the first back bias voltage grid between a first level and a second level in accordance with the state select signal (En); and - adjust a second back bias voltage (V BN) of the second back bias voltage grid between a first level and a second level in accordance with the state select signal (En). - a first regional clock network for supplying a first regional clock signal (R-Clk) to one or more digital logic circuits of the first logic circuit region, - a clock gating circuit configured to derive the first regional clock signal (R-Clk) from the clock signal (Clk) and selectively apply and interrupt the first regional clock signal (R-Clk) in accordance with a state select signal (En) of the first logic circuit region, - a first back bias voltage grid connected to respective bodies of PMOS transistors of the one or more digital logic circuits and a second back bias voltage grid connected to respective bodies of NMOS transistors of the one or more digital logic circuits, - a controllable back bias voltage generator configured to: - adjust a first back bias voltage (V BP) of the first back bias voltage grid between a first level and a second level in accordance with the state select signal (En); and - adjust a second back bias voltage (V BN) of the second back bias voltage grid between a first level and a second level in accordance with the state select signal (En). - adjust a first back bias voltage (V BP) of the first back bias voltage grid between a first level and a second level in accordance with the state select signal (En); and - adjust a second back bias voltage (V BN) of the second back bias voltage grid between a first level and a second level in accordance with the state select signal (En).