A method of providing a routed design of an integrated circuit and fabricating an integrated circuit according to the routed design, the method comprising using a processor to execute the steps of: performing an initial placement, a virtual routing, and a lower-effort actual routing for a design, wherein the virtual routing is an estimated routing performed based on the initial placement, and wherein the lower-effort actual routing provides more optimizations than the virtual routing; comparing net delay characteristics of nets of the virtual routing with net delay characteristics of nets of the lower-effort actual routing to identify nets having at least a predetermined miscorrelation; defining patterns based on one or more common factors existing in the identified nets having at least the predetermined miscorrelation, wherein the one or more common factors include net length and number of fanouts; assigning scaling factors and net routing constraints to the defined patterns, wherein assigning scaling factors includes setting, based on user input values for each scaling factor, at least one of minimum horizontal capacitance, minimum horizontal resistance, maximum horizontal capacitance, maximum horizontal resistance, minimum vertical capacitance, minimum vertical resistance, maximum vertical capacitance, and maximum vertical resistance for a net, wherein the net routing constraints include at least one of a non-default routing rule and a routing layer constraint, wherein the non-default routing rule specifies at least one of double width nets, double spacing between nets, a tapering rule and/or a number of via cuts, and wherein the routing layer constraint includes assigning all nets with a length above a predetermined threshold to a predefined layer or above; applying the scaling factors and net routing constraints assigned to the defined patterns to nets of the design matching the defined patterns; optimizing placement and performing a higher-effort actual routing of the design using the net routing constraints applied to the nets of the design matching the defined patterns, the higher-effort actual routing providing more optimizations than the lower-effort actual routing, wherein net delay characteristics of nets of the higher-effort actual routing have improved correlation with net delay characteristics of nets of the virtual routing when compared with net delay characteristics of nets of the lower-effort actual routing; and outputting a routed design based on the higher-effort actual routing of the design to provide an optimized circuit design; and the method further comprising controlling an integrated circuit fabrication system to: tape out a routed design of an integrated circuit according to the output routed design; and fabricate an integrated circuit according to the routed design. performing an initial placement, a virtual routing, and a lower-effort actual routing for a design, wherein the virtual routing is an estimated routing performed based on the initial placement, and wherein the lower-effort actual routing provides more optimizations than the virtual routing; comparing net delay characteristics of nets of the virtual routing with net delay characteristics of nets of the lower-effort actual routing to identify nets having at least a predetermined miscorrelation; defining patterns based on one or more common factors existing in the identified nets having at least the predetermined miscorrelation, wherein the one or more common factors include net length and number of fanouts; assigning scaling factors and net routing constraints to the defined patterns, wherein assigning scaling factors includes setting, based on user input values for each scaling factor, at least one of minimum horizontal capacitance, minimum horizontal resistance, maximum horizontal capacitance, maximum horizontal resistance, minimum vertical capacitance, minimum vertical resistance, maximum vertical capacitance, and maximum vertical resistance for a net, wherein the net routing constraints include at least one of a non-default routing rule and a routing layer constraint, wherein the non-default routing rule specifies at least one of double width nets, double spacing between nets, a tapering rule and/or a number of via cuts, and wherein the routing layer constraint includes assigning all nets with a length above a predetermined threshold to a predefined layer or above; applying the scaling factors and net routing constraints assigned to the defined patterns to nets of the design matching the defined patterns; optimizing placement and performing a higher-effort actual routing of the design using the net routing constraints applied to the nets of the design matching the defined patterns, the higher-effort actual routing providing more optimizations than the lower-effort actual routing, wherein net delay characteristics of nets of the higher-effort actual routing have improved correlation with net delay characteristics of nets of the virtual routing when compared with net delay characteristics of nets of the lower-effort actual routing; and outputting a routed design based on the higher-effort actual routing of the design to provide an optimized circuit design; and tape out a routed design of an integrated circuit according to the output routed design; and fabricate an integrated circuit according to the routed design.