Method for operating a drive system comprising a plurality of, in particular more than two, inverters (31, 32, 33, 34) and a data bus, wherein a respective electric motor (M1, M2, M3, M4, Mn) is fed from the AC-side terminal of the respective inverter (31, 32, 33, 34), wherein the DC-side terminals of the respective inverters (31, 32, 33, 34) are connected in parallel with one another, and this parallel connection is connected to the DC-side terminal of a rectifier, in particular a controllable and/or regenerative rectifier, in particular by means of conductor rails, wherein the respective inverter (31, 32, 33, 34) comprises respective semiconductor switches which are actuated according to a respective pulse width modulation, wherein the inverters (31, 32, 33, 34) are configured as bus subscribers of a data bus, to which a module configured as master is also connected, in particular wherein the module comprises the rectifier, wherein, in a first method step, in particular during initialization or start-up of the drive system, a respective bus address is assigned to each inverter (31, 32, 33, 34), and thereafter, in a second method step, there is specified to each inverter (31, 32, 33, 34) the polarity of its pulse width modulation, in particular its pulse width modulation method, wherein the polarity of the pulse width modulation of a first of the inverters (31, 32, 33, 34) differs from the polarity of the pulse width modulation of a second of the inverters (31, 32, 33, 34), in particular such that the pulse width modulation of the actuation signals for the controllable semiconductor switches of the first of the inverters (31, 32, 33, 34) is implemented in a manner clocked anti-synchronously to the pulse width modulation of the actuation signals for the controllable semiconductor switches of the second of the inverters (31, 32, 33, 34), characterized in that for address assignment, a respective inverter (31, 32, 33, 34) supplies to a downstream inverter (31, 32, 33, 34) a voltage signal by which the respective downstream inverter (31, 32, 33, 34) is signaled to adopt the address contained in the chronologically next broadcast telegram from the master as its own bus address and to supply a further voltage signal to a further inverter (31, 32, 33, 34) if such an inverter is present, and, if not, to adjust the polarity of its pulse width modulation to the polarity information contained in the broadcast telegram. wherein a respective electric motor (M1, M2, M3, M4, Mn) is fed from the AC-side terminal of the respective inverter (31, 32, 33, 34), wherein the DC-side terminals of the respective inverters (31, 32, 33, 34) are connected in parallel with one another, and this parallel connection is connected to the DC-side terminal of a rectifier, in particular a controllable and/or regenerative rectifier, in particular by means of conductor rails, wherein the respective inverter (31, 32, 33, 34) comprises respective semiconductor switches which are actuated according to a respective pulse width modulation, wherein the inverters (31, 32, 33, 34) are configured as bus subscribers of a data bus, to which a module configured as master is also connected, in particular wherein the module comprises the rectifier, wherein, in a first method step, in particular during initialization or start-up of the drive system, a respective bus address is assigned to each inverter (31, 32, 33, 34), and thereafter, in a second method step, there is specified to each inverter (31, 32, 33, 34) the polarity of its pulse width modulation, in particular its pulse width modulation method, wherein the polarity of the pulse width modulation of a first of the inverters (31, 32, 33, 34) differs from the polarity of the pulse width modulation of a second of the inverters (31, 32, 33, 34), in particular such that the pulse width modulation of the actuation signals for the controllable semiconductor switches of the first of the inverters (31, 32, 33, 34) is implemented in a manner clocked anti-synchronously to the pulse width modulation of the actuation signals for the controllable semiconductor switches of the second of the inverters (31, 32, 33, 34), characterized in that for address assignment, a respective inverter (31, 32, 33, 34) supplies to a downstream inverter (31, 32, 33, 34) a voltage signal by which the respective downstream inverter (31, 32, 33, 34) is signaled to adopt the address contained in the chronologically next broadcast telegram from the master as its own bus address and to supply a further voltage signal to a further inverter (31, 32, 33, 34) if such an inverter is present, and, if not, to adjust the polarity of its pulse width modulation to the polarity information contained in the broadcast telegram.