A memory array comprising a first bit line, a first inverted bit line (/BL), a first word line, a first isolation line, a first antifuse control line, a second antifuse control line and a first one time programming memory cell, wherein the first one time programming memory cell comprises: a first selecting circuit connected with the first bit line, the first inverted bit line (/BL)and the first word line; a first isolation circuit connected with the first isolation control line; a first antifuse storing circuit connected with the first antifuse control line, the first isolation circuit and the first selecting circuit; and a second antifuse storing circuit connected with the second antifuse control line, the first isolation circuit and the first selecting circuit, characterized in that during a program cycle, a select voltage is provided to the first word line, a ground voltage is provided to the first bit line and the first inverted bit line (/BL), an on voltage is provided to the first isolation control line, and a program voltage is provided to the first antifuse control line and the second antifuse control line, wherein the first antifuse storing circuit and the second antifuse storing circuit are connected to each other by the first isolation circuit in response to the on voltage, the first selecting circuit provides the ground voltage to the first antifuse storing circuit and the second antifuse storing circuit, and the program voltage is applied to both of the first antifuse storing circuit and the second antifuse storing circuit, so that a storing state of the first antifuse storing circuit or the second antifuse storing circuit is changed, wherein during a read cycle, the select voltage is provided to the first word line, the ground voltage is provided to the first bit line and the first inverted bit line (/BL), a read voltage is provided to the first antifuse control line and the second antifuse storing circuit, and an off voltage is provided to the first isolation control line, so that the first antifuse storing circuit and the second antifuse storing circuit are isolated by the first isolation circuit in response to the off voltage, the first antifuse storing circuit generates a first read current to the first bit line and the second antifuse storing circuit generates a second read current to the first inverted bit line (/BL), wherein one bit of a random code for a physically unclonable function technology is realized according to the first read current of the first antifuse storing circuit. a first selecting circuit connected with the first bit line, the first inverted bit line (/BL)and the first word line; a first isolation circuit connected with the first isolation control line; a first antifuse storing circuit connected with the first antifuse control line, the first isolation circuit and the first selecting circuit; and a second antifuse storing circuit connected with the second antifuse control line, the first isolation circuit and the first selecting circuit, characterized in that during a program cycle, a select voltage is provided to the first word line, a ground voltage is provided to the first bit line and the first inverted bit line (/BL), an on voltage is provided to the first isolation control line, and a program voltage is provided to the first antifuse control line and the second antifuse control line, wherein the first antifuse storing circuit and the second antifuse storing circuit are connected to each other by the first isolation circuit in response to the on voltage, the first selecting circuit provides the ground voltage to the first antifuse storing circuit and the second antifuse storing circuit, and the program voltage is applied to both of the first antifuse storing circuit and the second antifuse storing circuit, so that a storing state of the first antifuse storing circuit or the second antifuse storing circuit is changed, wherein during a read cycle, the select voltage is provided to the first word line, the ground voltage is provided to the first bit line and the first inverted bit line (/BL), a read voltage is provided to the first antifuse control line and the second antifuse storing circuit, and an off voltage is provided to the first isolation control line, so that the first antifuse storing circuit and the second antifuse storing circuit are isolated by the first isolation circuit in response to the off voltage, the first antifuse storing circuit generates a first read current to the first bit line and the second antifuse storing circuit generates a second read current to the first inverted bit line (/BL), wherein one bit of a random code for a physically unclonable function technology is realized according to the first read current of the first antifuse storing circuit.