A method comprising: receiving a first plurality of input signals at a first plurality of logic gates (510,610) and a second plurality of logic gates (520, 620), wherein the first plurality of logic gates and the second plurality of logic gates are associated with a symmetric configuration; generating, by the first plurality of logic gates (510, 610), a first output at a first value based on a first portion of the first plurality of input signals that are received by the first plurality of logic gates (510, 610); generating, by the second plurality of logic gates (520, 620), a second output at the first value based on a second portion of the first plurality of input signals; receiving, after the first plurality of input signals, a second plurality of input signals at the first plurality of logic gates (510, 610) and the second plurality of logic gates (520, 620); generating, by the first plurality of logic gates (510, 610), a subsequent first output at a particular value based on a first portion of the second plurality of input signals that are received by the first plurality of logic gates (510, 610); and generating, by the second plurality of logic gates (520, 620), a subsequent second output based on a second portion of the second plurality of input signals that are received by the second plurality of logic gates (520, 620), wherein a value of the subsequent second output is complementary to the particular value of the subsequent first output, wherein the first plurality of input signals are received at a first time and correspond to the first output and the second output being a pre-charge value of zero or one, and wherein the second plurality of input signals are received at a second time after the first time and correspond to one of the subsequent first output or the subsequent second output being a value of one and the other of the subsequent first output or the subsequent second output being a value of zero. receiving a first plurality of input signals at a first plurality of logic gates (510,610) and a second plurality of logic gates (520, 620), wherein the first plurality of logic gates and the second plurality of logic gates are associated with a symmetric configuration; generating, by the first plurality of logic gates (510, 610), a first output at a first value based on a first portion of the first plurality of input signals that are received by the first plurality of logic gates (510, 610); generating, by the second plurality of logic gates (520, 620), a second output at the first value based on a second portion of the first plurality of input signals; receiving, after the first plurality of input signals, a second plurality of input signals at the first plurality of logic gates (510, 610) and the second plurality of logic gates (520, 620); generating, by the first plurality of logic gates (510, 610), a subsequent first output at a particular value based on a first portion of the second plurality of input signals that are received by the first plurality of logic gates (510, 610); and generating, by the second plurality of logic gates (520, 620), a subsequent second output based on a second portion of the second plurality of input signals that are received by the second plurality of logic gates (520, 620), wherein a value of the subsequent second output is complementary to the particular value of the subsequent first output, wherein the first plurality of input signals are received at a first time and correspond to the first output and the second output being a pre-charge value of zero or one, and wherein the second plurality of input signals are received at a second time after the first time and correspond to one of the subsequent first output or the subsequent second output being a value of one and the other of the subsequent first output or the subsequent second output being a value of zero.