A NAND architecture non-volatile memory device, comprising: a NAND memory array (104; 200) having a plurality of non-volatile memory cells arranged in a plurality of NAND strings; and circuitry for control and/or access of the plurality of non-volatile memory cells of the NAND memory array; wherein the NAND architecture non-volatile memory device is adapted to sense a threshold voltage of a selected memory cell of a NAND memory cell string of the NAND memory array (104; 200) by, coupling the NAND string to a bit line and a source line, applying an elevated source voltage, Vsource, greater than or equal to a supply voltage Vcc, to the source line, applying a pass voltage, Vpass, to one or more word lines coupled to control gates on one or more unselected memory cells of the NAND string, and applying a read gate voltage, Vg, to a word line coupled to a control gate of the selected memory cell; and wherein the NAND architecture non-volatile memory device is adapted to sample the threshold voltage expressed on the bit line with a sample and hold circuit coupled to the bit line, the memory device being characterised by the sample and hold circuit comprising an amplifier coupled to an I/O bus through a first switch and a bit line program inhibit circuit through a second switch; a first capacitor, configured to sample the threshold voltage, coupled to a first input of the amplifier and to the bit line through a third switch; a second capacitor, configured to store a target analog voltage, coupled to a second input of the amplifier through a fourth switch and to the I/O bus through a fifth switch; and a sixth switch coupled in parallel with the amplifier; wherein the amplifier is configured to output a comparison of the target analog voltage with the threshold voltage to the bit line program inhibit circuit when the sixth switch is open and the second switch is closed and the amplifier is further configured to act as a unity gain amplifier to output the threshold voltage to the I/O bus when both the sixth switch and the first switch are closed. a NAND memory array (104; 200) having a plurality of non-volatile memory cells arranged in a plurality of NAND strings; and circuitry for control and/or access of the plurality of non-volatile memory cells of the NAND memory array; wherein the NAND architecture non-volatile memory device is adapted to sense a threshold voltage of a selected memory cell of a NAND memory cell string of the NAND memory array (104; 200) by, coupling the NAND string to a bit line and a source line, applying an elevated source voltage, Vsource, greater than or equal to a supply voltage Vcc, to the source line, applying a pass voltage, Vpass, to one or more word lines coupled to control gates on one or more unselected memory cells of the NAND string, and applying a read gate voltage, Vg, to a word line coupled to a control gate of the selected memory cell; and coupling the NAND string to a bit line and a source line, applying an elevated source voltage, Vsource, greater than or equal to a supply voltage Vcc, to the source line, applying a pass voltage, Vpass, to one or more word lines coupled to control gates on one or more unselected memory cells of the NAND string, and applying a read gate voltage, Vg, to a word line coupled to a control gate of the selected memory cell; and wherein the NAND architecture non-volatile memory device is adapted to sample the threshold voltage expressed on the bit line with a sample and hold circuit coupled to the bit line, the memory device being characterised by the sample and hold circuit comprising an amplifier coupled to an I/O bus through a first switch and a bit line program inhibit circuit through a second switch; a first capacitor, configured to sample the threshold voltage, coupled to a first input of the amplifier and to the bit line through a third switch; a second capacitor, configured to store a target analog voltage, coupled to a second input of the amplifier through a fourth switch and to the I/O bus through a fifth switch; and a sixth switch coupled in parallel with the amplifier; an amplifier coupled to an I/O bus through a first switch and a bit line program inhibit circuit through a second switch; a first capacitor, configured to sample the threshold voltage, coupled to a first input of the amplifier and to the bit line through a third switch; a second capacitor, configured to store a target analog voltage, coupled to a second input of the amplifier through a fourth switch and to the I/O bus through a fifth switch; and a sixth switch coupled in parallel with the amplifier; wherein the amplifier is configured to output a comparison of the target analog voltage with the threshold voltage to the bit line program inhibit circuit when the sixth switch is open and the second switch is closed and the amplifier is further configured to act as a unity gain amplifier to output the threshold voltage to the I/O bus when both the sixth switch and the first switch are closed.