A liquid crystal display panel (200, 300, 400, 500, 600, 700) comprising: a first substrate plate; a plurality of gate lines (GL(x), GL(x+1)) disposed on the first substrate plate; a plurality of data lines (DL(y), DL(y+1)) disposed on the first substrate plate, and substantially perpendicular to the gate lines (GL(x), GL(x+1)), the gate lines (GL(x), GL(x+1)) and the data lines (DL(y), DL(y+1)) cooperatively defining a plurality of pixel regions, each pixel region comprising at least a main display region and a sub display region; a dielectric layer (22, 26) positioned on the gate lines (GL(x), GL(x+1)) and the data lines (DL(y), DL(y+1)); a plurality of first pixel electrodes positioned in the main display region and on the dielectric layer (22, 26), each first pixel electrode electrically connecting to the corresponding gate line (GL(x), GL(x+1)) and data line (DL(y), DL(y+1)), and each first pixel electrode being separated from the adjacent data line (DL(y), DL(y+1)) and thereby forming a gap therebetween; a plurality of second pixel electrodes positioned in the sub display region and on the dielectric layer(22, 26), each second pixel electrode electrically connecting to the corresponding gate line (GL(x), GL(x+1)) and data line (DL(y), DL(y+1)); a second substrate plate (30, 38) positioned opposite to the first substrate plate; and a liquid crystal layer (22, LC) positioned between the first substrate plate and the second substrate plate (30, 38); characterized by each second pixel electrode partially overlapping the adjacent data line (DL(y), DL(y+1)) and thereby forming an overlap width, wherein an operating voltage of the main display region is larger than that of the sub display region. a first substrate plate; a plurality of gate lines (GL(x), GL(x+1)) disposed on the first substrate plate; a plurality of data lines (DL(y), DL(y+1)) disposed on the first substrate plate, and substantially perpendicular to the gate lines (GL(x), GL(x+1)), the gate lines (GL(x), GL(x+1)) and the data lines (DL(y), DL(y+1)) cooperatively defining a plurality of pixel regions, each pixel region comprising at least a main display region and a sub display region; a dielectric layer (22, 26) positioned on the gate lines (GL(x), GL(x+1)) and the data lines (DL(y), DL(y+1)); a plurality of first pixel electrodes positioned in the main display region and on the dielectric layer (22, 26), each first pixel electrode electrically connecting to the corresponding gate line (GL(x), GL(x+1)) and data line (DL(y), DL(y+1)), and each first pixel electrode being separated from the adjacent data line (DL(y), DL(y+1)) and thereby forming a gap therebetween; a plurality of second pixel electrodes positioned in the sub display region and on the dielectric layer(22, 26), each second pixel electrode electrically connecting to the corresponding gate line (GL(x), GL(x+1)) and data line (DL(y), DL(y+1)); a second substrate plate (30, 38) positioned opposite to the first substrate plate; and a liquid crystal layer (22, LC) positioned between the first substrate plate and the second substrate plate (30, 38); characterized by each second pixel electrode partially overlapping the adjacent data line (DL(y), DL(y+1)) and thereby forming an overlap width, wherein an operating voltage of the main display region is larger than that of the sub display region.