An access device for a Static or Dynamic Random-Access Memory cell (1100, 2100), wherein said access device is positioned between said Static or Dynamic Random-Access Memory cell (1100, 2100) and a memory transmission interface, and is arranged to write a bit value into said Static or Dynamic Random-Access Memory cell (1100, 2100), or read a bit value from said Static or Dynamic Random-Access Memory cell (1100, 2100), characterized by a first data node, a first control node (CHd), a first controlled transistor, and a trigger (301, 201); said trigger (301, 201) comprises a level switcher, a first input node (Goad), a first output node (Width), a first and a second NOT gate (Not71, Not72), and an OR gate; wherein said first input node (Goad) connects to an output of a tri-state gate, and an input of said tri-state gate connects to a Bit-to-Cell input node, and an enable input of said tri-state gate connects to a Cell-Write input node (CWr), and said first output node (Width) connects to a Bit-to-Data output node via a third NOT gate, said first control node (CHd) connects to the gate terminal of said first controlled transistor (M41-151), said first data node connects or couples to the drain terminal of said first controlled transistor, said first input node (Goad) connects to said first data node, and the source terminal of said first controlled transistor connects to ground; further comprising a second controlled PMOS transistor if the Static or Dynamic Random-Access Memory cell (1100, 2100) is a 3T1R/3T1D/3T1C SRAM cell, wherein the gate terminal of said second controlled PMOS transistor connects to a second output node (pull) of said trigger (301, 201), the drain terminal of said second controlled PMOS transistor connects to said first data node and the source terminal of said second controlled PMOS transistor connects to a supply voltage (Vdd); wherein said trigger (301, 201) is configured to take a signal input to said first input node (Goad) as a trigger signal to generate an output voltage of rail-to-rail on said first output node (Width) when a voltage level on said first input node (Goad) changes; said level switcher comprises an action node (act), a poise node (Poise), and a second tri-state gate; said poise node (Poise) connects to an input connective point and an output connective point of said second tri-state gate, and said action node (act) connects to an enable input of said second tri-state gate via a fourth NOT gate; said action node (act) connects to said first input node (Goad), said poise node (Poise) connects to an input connective point of said first NOT gate, said poise node (Poise) connects or couples to an output connective point of said OR gate, and said poise node (Poise) and said output connective point of said OR gate (Or71,) constitute a wired-logic; said wired-logic is a wired-AND; the coupling between said poise node (Poise) and said output connective point of said OR gate is a delay element, and wherein said first input node (Goad) connects to a first input connective point of said OR gate and an output connective point of said first NOT gate connects to a second input connective point of said OR gate and to said first output node (Width) via said second NOT gate; a signal on said action node (act) controls said poise node (Poise) to constitute said wired-logic with said output connective point of said OR gate. further comprising a second controlled PMOS transistor if the Static or Dynamic Random-Access Memory cell (1100, 2100) is a 3T1R/3T1D/3T1C SRAM cell, wherein the gate terminal of said second controlled PMOS transistor connects to a second output node (pull) of said trigger (301, 201), the drain terminal of said second controlled PMOS transistor connects to said first data node and the source terminal of said second controlled PMOS transistor connects to a supply voltage (Vdd); wherein said trigger (301, 201) is configured to take a signal input to said first input node (Goad) as a trigger signal to generate an output voltage of rail-to-rail on said first output node (Width) when a voltage level on said first input node (Goad) changes; said level switcher comprises an action node (act), a poise node (Poise), and a second tri-state gate; said poise node (Poise) connects to an input connective point and an output connective point of said second tri-state gate, and said action node (act) connects to an enable input of said second tri-state gate via a fourth NOT gate; said action node (act) connects to said first input node (Goad), said poise node (Poise) connects to an input connective point of said first NOT gate, said poise node (Poise) connects or couples to an output connective point of said OR gate, and said poise node (Poise) and said output connective point of said OR gate (Or71,) constitute a wired-logic; said wired-logic is a wired-AND; the coupling between said poise node (Poise) and said output connective point of said OR gate is a delay element, and wherein said first input node (Goad) connects to a first input connective point of said OR gate and an output connective point of said first NOT gate connects to a second input connective point of said OR gate and to said first output node (Width) via said second NOT gate; a signal on said action node (act) controls said poise node (Poise) to constitute said wired-logic with said output connective point of said OR gate.