A high-voltage field effect transistor (100, 200, 300, 400) comprising: a first semiconductor material (105, 205, 305, 405), a second semiconductor material (110, 210, 310, 410), and a heterojunction (115, 215, 315, 415), wherein the heterojunction is disposed between the first semiconductor material and the second semiconductor material; a plurality of composite passivation layers (199, 299, 399, 499), wherein a first composite passivation layer in the plurality of composite passivation layers includes a first insulation layer (170, 270, 370, 470) and a first passivation layer (165, 265, 365, 465), wherein a second composite passivation layer in the plurality of composite passivation layers includes a second insulation layer (192, 292, 392, 492) and a second passivation layer (175, 275, 375, 475), wherein the first and second insulation layers have a wider bandgap than the first and second passivation layers and wherein the second passivation layer is disposed between the first insulation layer and the second insulation layer; a gate dielectric (155, 255, 355, 455) disposed between the first passivation layer and the second semiconductor material; a gate electrode (135, 235, 335, 435) disposed between the gate dielectric and the first passivation layer; a first gate field plate (140, 240, 340, 440) disposed between the first passivation layer and the second passivation layer, wherein the first gate field plate is coupled to the gate electrode (135, 235, 335, 435); a source electrode (125, 225, 325, 425) and a drain electrode (130, 230, 330, 430), wherein the source electrode and drain electrode are coupled to the second semiconductor material; and a source field plate (145, 245, 345, 445), wherein the source field plate is coupled to the source electrode. a first semiconductor material (105, 205, 305, 405), a second semiconductor material (110, 210, 310, 410), and a heterojunction (115, 215, 315, 415), wherein the heterojunction is disposed between the first semiconductor material and the second semiconductor material; a plurality of composite passivation layers (199, 299, 399, 499), wherein a first composite passivation layer in the plurality of composite passivation layers includes a first insulation layer (170, 270, 370, 470) and a first passivation layer (165, 265, 365, 465), wherein a second composite passivation layer in the plurality of composite passivation layers includes a second insulation layer (192, 292, 392, 492) and a second passivation layer (175, 275, 375, 475), wherein the first and second insulation layers have a wider bandgap than the first and second passivation layers and wherein the second passivation layer is disposed between the first insulation layer and the second insulation layer; a gate dielectric (155, 255, 355, 455) disposed between the first passivation layer and the second semiconductor material; a gate electrode (135, 235, 335, 435) disposed between the gate dielectric and the first passivation layer; a first gate field plate (140, 240, 340, 440) disposed between the first passivation layer and the second passivation layer, wherein the first gate field plate is coupled to the gate electrode (135, 235, 335, 435); a source electrode (125, 225, 325, 425) and a drain electrode (130, 230, 330, 430), wherein the source electrode and drain electrode are coupled to the second semiconductor material; and a source field plate (145, 245, 345, 445), wherein the source field plate is coupled to the source electrode.