A gate drive circuit of a display device, comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal (OUT_PUT), a logic turn-on input terminal, a logic turn-on output terminal (NEXT_STV), a control module, a first gating module and a second gating module; the control module is connected to the high level terminal, the first clock terminal, the second clock terminal, the logic turn-on input terminal, the first gating module and the second gating module; the first gating module is connected to the low level terminal and the gate output terminal (OUT PUT); the second gating module is connected to the low level terminal and the logic turn-on output terminal (NEXT_STV); a logic turn-on output terminal (NEXT_STV) of a present unit circuit is connected with a logic turn-on input terminal of a unit circuit having an interval of one stage with the present unit circuit; the gate output terminal (OUT PUT) is connected to a gate line; wherein the control module comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, an eighth transistor, a first capacitor and a second capacitor; a gate of the first transistor is connected to the first clock terminal, a source of the first transistor is connected to the logic turn-on input terminal, a drain of the first transistor is connected to a gate of the third transistor; a gate and a source of the second transistor are connected to the first clock terminal, a drain of the second transistor is connected to a source of the third transistor; a drain of the third transistor is connected to the high level terminal; a gate of the fourth transistor is connected to the source of the third transistor, a source of the fourth transistor is connected to a drain of the fifth transistor, a drain of the fourth transistor is connected to the high level terminal, the source of the fourth transistor is connected to the first gating module for controlling the first gating module; a gate of the fifth transistor is connected to the drain of the first transistor, a source of the fifth transistor is connected to the second clock terminal; a gate of the eighth transistor is connected to the second clock terminal, a source of the eighth transistor is connected to the second gating module for controlling the second gating module, a drain of the eighth transistor is connected to the source of the fourth transistor; a first terminal of the first capacitor is connected to the high level terminal, a second terminal of the first capacitor is connected to the gate of the fourth transistor; a first terminal of the second capacitor is connected to the drain of the fifth transistor, a second terminal of the second capacitor is connected to the gate of the fifth transistor; the control module is configured, based on the first clock terminal, the second clock terminal, and the logic turn-on input terminal, to control the first gating module to gate a high level signal from the high level terminal to the gate output terminal (OUT_PUT); or, gate a low level signal from the low level terminal to the gate output terminal (OUT PUT); the control module is also configured, based on the first clock terminal, the second clock terminal, and the logic turn-on input terminal, to control the second gating module, such that: only when the first clock terminal is in an effective time sequence state, the second gating module gates a low level signal from the low level terminal to the logic turn-on output terminal (NEXT_STV), the low level signal then being transmitted to the logic turn-on input terminal of the unit circuit having an interval of one stage with the present unit circuit, to turn on interlaced output; in other time sequence state, the second gating module gates a high level signal from the high level terminal to the logic turn-on output terminal (NEXT_STV).