A data processing device comprising: a padding means configured to pad control data (K sig, L1) with dummy data resulting in post-padding control data (K bch) to adjust a data length of the post-padding control data (K bch) to a target data length of a BCH error correction encoding, the control data (K sig, L1) being necessary for demodulation,; a scrambling means configured to scramble the post-padding control data (K bch) resulting in scrambled post-padding control data (K bch (s)); a replacement means configured to generate replacement data (K bch (r)) by replacing scrambled dummy data in the scrambled post-padding control data (K bch (s)) with the dummy data; and an error correction encoding means configured to perform the BCH error correction encoding on the replacement data (K bch (r)), thereby attaining a BCH code (K ldpc), and to supply the BCH code (K ldpc) to a LDPC error correction encoding means, wherein the LDPC correction encoding means is configured to determine LDPC code parity bits for the BCH code (K ldpc) to be subjected to the LDPC error correction encoding, and to add the LDPC code parity bits to the BCH code (K ldpc) to be subjected to the LDPC error correction encoding, to obtain a LDPC code (N ldpc), and wherein the data processing device further comprises a shortening means configured to perform shortening by deleting the dummy data from the LDPC code (N ldpc) and puncturing the parity bits of the LDPC code (N ldpc). a padding means configured to pad control data (K sig, L1) with dummy data resulting in post-padding control data (K bch) to adjust a data length of the post-padding control data (K bch) to a target data length of a BCH error correction encoding, the control data (K sig, L1) being necessary for demodulation,; a scrambling means configured to scramble the post-padding control data (K bch) resulting in scrambled post-padding control data (K bch (s)); a replacement means configured to generate replacement data (K bch (r)) by replacing scrambled dummy data in the scrambled post-padding control data (K bch (s)) with the dummy data; and an error correction encoding means configured to perform the BCH error correction encoding on the replacement data (K bch (r)), thereby attaining a BCH code (K ldpc), and to supply the BCH code (K ldpc) to a LDPC error correction encoding means, to perform the BCH error correction encoding on the replacement data (K bch (r)), thereby attaining a BCH code (K ldpc), and to supply the BCH code (K ldpc) to a LDPC error correction encoding means, wherein the LDPC correction encoding means is configured to determine LDPC code parity bits for the BCH code (K ldpc) to be subjected to the LDPC error correction encoding, and to add the LDPC code parity bits to the BCH code (K ldpc) to be subjected to the LDPC error correction encoding, to obtain a LDPC code (N ldpc), and to determine LDPC code parity bits for the BCH code (K ldpc) to be subjected to the LDPC error correction encoding, and to add the LDPC code parity bits to the BCH code (K ldpc) to be subjected to the LDPC error correction encoding, to obtain a LDPC code (N ldpc), and wherein the data processing device further comprises a shortening means configured to perform shortening by deleting the dummy data from the LDPC code (N ldpc) and puncturing the parity bits of the LDPC code (N ldpc).