A voltage measurement device for measuring an output voltage of a battery assembly in which a plurality of cells (P1 - P55) are connected in series so as to output a desired voltage, the voltage measurement device comprising: voltage addition sections that are respectively provided for the plurality of cells (P1 - P55), wherein the voltage addition sections are adapted to add a predetermined voltage value to output voltages of the cells (P1 - P55); voltage detection sections (21-1 - 21-5) that are provided for respective blocks (61-1 - 61-5), wherein the voltage detection sections (21-1 - 21-5) are adapted to detect addition voltages which are output voltages of the voltage addition sections corresponding to the cells (P1 - P55) of the individual blocks (61-1 - 61-5), and wherein the cells (P1 - P55) are sectioned into the blocks (61-1 - 61-5) each being constituted by at least one cell (P1 - P55); A/D converting sections that are provided for the individual voltage detection sections (21-1 - 21-5), wherein the A/D converting sections are adapted to digitize analog voltage signals of the addition voltages detected by the voltage detection sections (21-1 - 21-5); and a control section that is connected through communication lines among the voltage detection sections (21-1 - 21-5) respectively, wherein the control section is adapted to output voltage measurement request signals to the voltage detection sections (21-1 - 21-5) respectively, and to acquire the addition voltages detected by the voltage detection sections (21-1 - 21-5) respectively, to subtract the predetermined voltage value from the acquired addition voltages, and to provide voltage values after the subtractions, as the output voltages of the cells (P1 - P55); characterized in that the voltage addition sections respectively include: first inverting amplification circuits (45a - 45d) adapted to amplify a voltage across a positive electrode terminals and negative electrode terminals of the cells (P1 - P55) and to output the amplified voltages; buffers (46a - 46d) which are disposed on output sides of the first inverting amplification circuits; and second inverting amplification circuits (47a - 47d) adapted to invert polarities by adding the predetermined voltage value to output signals of the buffers. voltage addition sections that are respectively provided for the plurality of cells (P1 - P55), wherein the voltage addition sections are adapted to add a predetermined voltage value to output voltages of the cells (P1 - P55); voltage detection sections (21-1 - 21-5) that are provided for respective blocks (61-1 - 61-5), wherein the voltage detection sections (21-1 - 21-5) are adapted to detect addition voltages which are output voltages of the voltage addition sections corresponding to the cells (P1 - P55) of the individual blocks (61-1 - 61-5), and wherein the cells (P1 - P55) are sectioned into the blocks (61-1 - 61-5) each being constituted by at least one cell (P1 - P55); A/D converting sections that are provided for the individual voltage detection sections (21-1 - 21-5), wherein the A/D converting sections are adapted to digitize analog voltage signals of the addition voltages detected by the voltage detection sections (21-1 - 21-5); and a control section that is connected through communication lines among the voltage detection sections (21-1 - 21-5) respectively, wherein the control section is adapted to output voltage measurement request signals to the voltage detection sections (21-1 - 21-5) respectively, and to acquire the addition voltages detected by the voltage detection sections (21-1 - 21-5) respectively, to subtract the predetermined voltage value from the acquired addition voltages, and to provide voltage values after the subtractions, as the output voltages of the cells (P1 - P55); characterized in that the voltage addition sections respectively include: first inverting amplification circuits (45a - 45d) adapted to amplify a voltage across a positive electrode terminals and negative electrode terminals of the cells (P1 - P55) and to output the amplified voltages; buffers (46a - 46d) which are disposed on output sides of the first inverting amplification circuits; and second inverting amplification circuits (47a - 47d) adapted to invert polarities by adding the predetermined voltage value to output signals of the buffers. first inverting amplification circuits (45a - 45d) adapted to amplify a voltage across a positive electrode terminals and negative electrode terminals of the cells (P1 - P55) and to output the amplified voltages; buffers (46a - 46d) which are disposed on output sides of the first inverting amplification circuits; and second inverting amplification circuits (47a - 47d) adapted to invert polarities by adding the predetermined voltage value to output signals of the buffers.