A circuit for establishing a bias current, comprising: a mixer operable to receive a drive voltage and at least a portion of the bias current, wherein the drive voltage comprises a first voltage signal and a second voltage signal one-hundred-eighty degrees out of phase with the first voltage signal; an amplifier coupled to the mixer and operable to receive at least a portion of the bias current; a bias resistor coupled to the amplifier at a node, wherein a bias voltage exists at the node; a comparator coupled to the node and operable to compare the bias voltage with a reference voltage, the comparator further operable to generate an output signal based at least in part upon the comparison; and a drive circuit operable to generate the drive voltage in response to the output signal such that the bias voltage substantially equals the reference voltage thereby establishing the bias current wherein the mixer comprises: a first transistor having a first terminal coupled to the first voltage signal, a second terminal, and a third terminal; a second transistor having a first terminal, coupled to the second voltage signal, a second terminal, and a third terminal coupled to the third terminal of the first transistor and further coupled to a first load resistor; a third transistor having a first terminal coupled to the first terminal of the second transistor and the second voltage signal, a second terminal coupled to the second terminal of the first transistor, and a third terminal; and a fourth transistor having a first terminal coupled to the first terminal of the first transistor and the first voltage signal, a second terminal coupled to the second terminal of the second transistor, and a third terminal coupled to the third terminal of the third transistor and further coupled to a second load resistor. a mixer operable to receive a drive voltage and at least a portion of the bias current, wherein the drive voltage comprises a first voltage signal and a second voltage signal one-hundred-eighty degrees out of phase with the first voltage signal; an amplifier coupled to the mixer and operable to receive at least a portion of the bias current; a bias resistor coupled to the amplifier at a node, wherein a bias voltage exists at the node; a comparator coupled to the node and operable to compare the bias voltage with a reference voltage, the comparator further operable to generate an output signal based at least in part upon the comparison; and a drive circuit operable to generate the drive voltage in response to the output signal such that the bias voltage substantially equals the reference voltage thereby establishing the bias current wherein the mixer comprises: a first transistor having a first terminal coupled to the first voltage signal, a second terminal, and a third terminal; a second transistor having a first terminal, coupled to the second voltage signal, a second terminal, and a third terminal coupled to the third terminal of the first transistor and further coupled to a first load resistor; a third transistor having a first terminal coupled to the first terminal of the second transistor and the second voltage signal, a second terminal coupled to the second terminal of the first transistor, and a third terminal; and a fourth transistor having a first terminal coupled to the first terminal of the first transistor and the first voltage signal, a second terminal coupled to the second terminal of the second transistor, and a third terminal coupled to the third terminal of the third transistor and further coupled to a second load resistor. a first transistor having a first terminal coupled to the first voltage signal, a second terminal, and a third terminal; a second transistor having a first terminal, coupled to the second voltage signal, a second terminal, and a third terminal coupled to the third terminal of the first transistor and further coupled to a first load resistor; a third transistor having a first terminal coupled to the first terminal of the second transistor and the second voltage signal, a second terminal coupled to the second terminal of the first transistor, and a third terminal; and a fourth transistor having a first terminal coupled to the first terminal of the first transistor and the first voltage signal, a second terminal coupled to the second terminal of the second transistor, and a third terminal coupled to the third terminal of the third transistor and further coupled to a second load resistor.