An apparatus comprising: a digital to analog converter module for receiving an input digital signal having a first data rate and associated with a first frequency and for receiving a clock signal as a synchronization signal having a second frequency that is higher than the first frequency, the DAC module comprising: an up-sampling circuit for generating a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a second data rate that is higher than the first data rate; a first DAC cell for generating a first analog signal based on the first digital signal, the first DAC cell being synchronized to the synchronization signal; a second DAC cell for generating a second analog signal based on a second digital signal, the second DAC cell being synchronized to the synchronization signal; and an adder for summing the first and second analog signals and generating a third analog signal; wherein the first DAC cell comprises a first latch unit for latching the first digital signal, the second DAC cell comprises a second latch unit for latching the second digital signal, wherein timing of latching the first digital signal by the first latch unit and timing of latching the second digital signal by the second latch unit are controlled by said synchronization signal; and the first DAC cell and the second DAC cell each comprises a respective current steering circuit for steering currents from a respective current source based on the respective first and second digital signals to generate the first and second analog signals; characterised in that the up-sampling circuit comprises a multiplexer that receives the input digital signal and a zero value signal at said second frequency, and alternately outputs the digital signal and the zero value signal as the first digital signal. wherein the DAC module further comprises a delay circuit for delaying the first digital signal by a time period to generate the second digital signal, wherein said time period is one clock cycle of the clock signal. a digital to analog converter module for receiving an input digital signal having a first data rate and associated with a first frequency and for receiving a clock signal as a synchronization signal having a second frequency that is higher than the first frequency, the DAC module comprising: an up-sampling circuit for generating a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a second data rate that is higher than the first data rate; a first DAC cell for generating a first analog signal based on the first digital signal, the first DAC cell being synchronized to the synchronization signal; a second DAC cell for generating a second analog signal based on a second digital signal, the second DAC cell being synchronized to the synchronization signal; and an adder for summing the first and second analog signals and generating a third analog signal; wherein an up-sampling circuit for generating a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a second data rate that is higher than the first data rate; a first DAC cell for generating a first analog signal based on the first digital signal, the first DAC cell being synchronized to the synchronization signal; a second DAC cell for generating a second analog signal based on a second digital signal, the second DAC cell being synchronized to the synchronization signal; and an adder for summing the first and second analog signals and generating a third analog signal; wherein the first DAC cell comprises a first latch unit for latching the first digital signal, the second DAC cell comprises a second latch unit for latching the second digital signal, wherein timing of latching the first digital signal by the first latch unit and timing of latching the second digital signal by the second latch unit are controlled by said synchronization signal; and the first DAC cell and the second DAC cell each comprises a respective current steering circuit for steering currents from a respective current source based on the respective first and second digital signals to generate the first and second analog signals; characterised in that the up-sampling circuit comprises a multiplexer that receives the input digital signal and a zero value signal at said second frequency, and alternately outputs the digital signal and the zero value signal as the first digital signal. wherein the DAC module further comprises a delay circuit for delaying the first digital signal by a time period to generate the second digital signal, wherein said time period is one clock cycle of the clock signal.