A gate driving circuit for a display circuit comprising a plurality of pixels arranged in rows and columns, said gate driving circuit comprising at least two stages, the first stage of the driving circuit having a first GOA unit (S/R2-0) and the remaining stage or stages of the gate driving circuit each having a first GOA unit (S/R2-1, S/R2-n) and a second GOA unit (S/R1-1, S/R1-n), each of said first and second GOA units comprising a signal input terminal (INPUT), a first output terminal, a reset terminal (RESET) and a second output terminal (COUT); wherein the signal input terminal of the first GOA unit (S/R2-0) of the first stage is adapted to have input thereto a first frame start signal, and the reset terminal thereof is connected to the second output terminal of the first GOA unit (S/R2-1) of the second stage; the signal input terminal of the second GOA unit (S/R1-1) of the second stage is adapted to have input thereto a second frame start signal; the reset terminal of the second GOA unit (S/R1-2) of the second stage is connected to the second output terminal of the first GOA unit (S/R2-1) of the first stage; the second output terminal of the first GOA unit (S/R1-2) of the second stage is connected to a first logic OR unit and is adapted to output a first pulse signal to the logic OR unit; the first output terminal of the first GOA unit (S/R2-2) of the second stage is connected to said first logic OR unit and is adapted to output a second pulse signal to said first logic OR unit; wherein for an n-th stage of the gate driving circuit where n is a positive integer greater than 2, then: the reset terminal of the first GOA unit (S/R2-n) of the n-th stage is connected to the second output terminal of the first GOA unit of the n+1th stage, and the signal input terminal of the first GOA unit (S/R2-n) of the n-th stage is connected to the second output terminal of the first GOA unit (S/R2-n-1) of the n-1th stage; the reset terminal of the second GOA unit (S/R1-n) of the n-th stage is connected to the second output terminal of the first GOA unit (S/R2-n-1) of the n-1th stage; the signal input terminal of the second GOA unit (S/R1-n) of the n-th stage is connected to the second output terminal of the second GOA unit (S/R1-n-1) of the n-1th stage; the first output terminal of the second GOA unit (S/R1-n) of the n-th stage is connected to an n-1th logic OR unit and is adapted to output a first pulse signal to the n-1th logic OR unit; the first output terminal of the first GOA unit (S/R2-n) of the n-th stage is connected to the n-1th logic OR unit and adapted to output a second pulse signal to said n-1th logic OR unit; and the n-1th logic OR unit is adapted to output a first gate driving signal to a pixel unit in a n-1th row of said display circuit. the reset terminal of the first GOA unit (S/R2-n) of the n-th stage is connected to the second output terminal of the first GOA unit of the n+1th stage, and the signal input terminal of the first GOA unit (S/R2-n) of the n-th stage is connected to the second output terminal of the first GOA unit (S/R2-n-1) of the n-1th stage; the reset terminal of the second GOA unit (S/R1-n) of the n-th stage is connected to the second output terminal of the first GOA unit (S/R2-n-1) of the n-1th stage; the signal input terminal of the second GOA unit (S/R1-n) of the n-th stage is connected to the second output terminal of the second GOA unit (S/R1-n-1) of the n-1th stage; the first output terminal of the second GOA unit (S/R1-n) of the n-th stage is connected to an n-1th logic OR unit and is adapted to output a first pulse signal to the n-1th logic OR unit; the first output terminal of the first GOA unit (S/R2-n) of the n-th stage is connected to the n-1th logic OR unit and adapted to output a second pulse signal to said n-1th logic OR unit; and the n-1th logic OR unit is adapted to output a first gate driving signal to a pixel unit in a n-1th row of said display circuit.