A microprocessor, comprising: condition flags; an instruction translator, configured to receive a conditional load instruction that specifies a condition, a destination register, a base register, an offset source, and a memory addressing mode, wherein the instruction instructs the microprocessor to load data from a memory location into the destination register only if the condition flags satisfy the condition, wherein the offset source specifies whether the offset is an immediate value or a value in an offset register, wherein the addressing mode specifies whether or not the base register is updated when the condition flags satisfy the condition; wherein the instruction translator is configured to translate the conditional load instruction into a number of microinstructions, wherein the number of microinstructions varies as a function of the offset source and the addressing mode; and an out-of-order execution pipeline, configured to execute the microinstructions to generate results specified by the instruction; and wherein the addressing mode specifies that the base register is updated, wherein the number of microinstructions is at least two, wherein the at least two microinstructions comprise: a first microinstruction, wherein to execute the first microinstruction an execution unit of the execution pipeline is configured to receive a previous value of the destination register and generate a result that is the data loaded from the memory location if the condition flags satisfy the condition but is the previous value of the destination register if the condition flags do not satisfy the condition; and a second microinstruction, wherein to execute the second microinstruction an execution unit of the execution pipeline is configured to receive the previous value of the base register and generate a result that is a memory address based on the offset and previous base register value if the condition flags satisfy the condition but is the previous base register value if the condition flags do not satisfy the condition; wherein the previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in order previous writer of the destination register with respect to the first microinstruction; and wherein the previous value of the base register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the base register with respect to the second microinstruction. condition flags; an instruction translator, configured to receive a conditional load instruction that specifies a condition, a destination register, a base register, an offset source, and a memory addressing mode, wherein the instruction instructs the microprocessor to load data from a memory location into the destination register only if the condition flags satisfy the condition, wherein the offset source specifies whether the offset is an immediate value or a value in an offset register, wherein the addressing mode specifies whether or not the base register is updated when the condition flags satisfy the condition; wherein the instruction translator is configured to translate the conditional load instruction into a number of microinstructions, wherein the number of microinstructions varies as a function of the offset source and the addressing mode; and an out-of-order execution pipeline, configured to execute the microinstructions to generate results specified by the instruction; and a first microinstruction, wherein to execute the first microinstruction an execution unit of the execution pipeline is configured to receive a previous value of the destination register and generate a result that is the data loaded from the memory location if the condition flags satisfy the condition but is the previous value of the destination register if the condition flags do not satisfy the condition; and a second microinstruction, wherein to execute the second microinstruction an execution unit of the execution pipeline is configured to receive the previous value of the base register and generate a result that is a memory address based on the offset and previous base register value if the condition flags satisfy the condition but is the previous base register value if the condition flags do not satisfy the condition;