An apparatus comprising: a processor; and a memory storing machine readable instructions that when executed by the processor cause the processor to: ascertain a request associated with a memory address range of computer memory, wherein the memory address range is assigned to a specified performance tier of a plurality of specified performance tiers; ascertain a performance value associated with a performance attribute of the memory address range; determine, based on the ascertained performance value, a weight value; increment, based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range; determine, based on an analysis of the count value associated with the counter, whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers; and based on a determination that the memory address range is to be assigned to the different specified performance tier, assign the memory address range to the different specified performance tier; wherein the machine readable instructions to determine, based on the ascertained performance value, the weight value, and increment, based on the ascertained request and the determined weight value, the count value associated with the counter associated with the memory address range, when executed by the processor cause the processor to: determine, based on the ascertained performance value, the weight value by proportionally increasing or decreasing a base weight value according to an increase or decrease in the performance value from a base performance value; determine a count value increment increase or decrease by multiplying the determined weight value and a base count value increment associated with the counter associated with the memory address range; and increment, based on the ascertained request, the count value by the determined count value increment increase or decrease. a processor; and a memory storing machine readable instructions that when executed by the processor cause the processor to: ascertain a request associated with a memory address range of computer memory, wherein the memory address range is assigned to a specified performance tier of a plurality of specified performance tiers; ascertain a performance value associated with a performance attribute of the memory address range; determine, based on the ascertained performance value, a weight value; increment, based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range; determine, based on an analysis of the count value associated with the counter, whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers; and based on a determination that the memory address range is to be assigned to the different specified performance tier, assign the memory address range to the different specified performance tier; ascertain a request associated with a memory address range of computer memory, wherein the memory address range is assigned to a specified performance tier of a plurality of specified performance tiers; ascertain a performance value associated with a performance attribute of the memory address range; determine, based on the ascertained performance value, a weight value; increment, based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range; determine, based on an analysis of the count value associated with the counter, whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers; and based on a determination that the memory address range is to be assigned to the different specified performance tier, assign the memory address range to the different specified performance tier; wherein the machine readable instructions to determine, based on the ascertained performance value, the weight value, and increment, based on the ascertained request and the determined weight value, the count value associated with the counter associated with the memory address range, when executed by the processor cause the processor to: determine, based on the ascertained performance value, the weight value by proportionally increasing or decreasing a base weight value according to an increase or decrease in the performance value from a base performance value; determine a count value increment increase or decrease by multiplying the determined weight value and a base count value increment associated with the counter associated with the memory address range; and increment, based on the ascertained request, the count value by the determined count value increment increase or decrease. determine, based on the ascertained performance value, the weight value by proportionally increasing or decreasing a base weight value according to an increase or decrease in the performance value from a base performance value; determine a count value increment increase or decrease by multiplying the determined weight value and a base count value increment associated with the counter associated with the memory address range; and increment, based on the ascertained request, the count value by the determined count value increment increase or decrease.