A single-ended switched-capacitor gain stage circuit comprising: an input node connected to receive an input voltage (Vin); first and second reference voltage input nodes connected to receive first and second reference voltages (Vrefp, Vrefm); an operational amplifier including a first amplifier input, a second amplifier input, and an amplifier output for outputting a residue voltage; an input sampling circuit comprising a first and second sampling switched capacitors (C1, C2), wherein the input sampling circuit is configured to: during a sampling phase, connect the input node to first terminals of the first and second sampling switched capacitors (C1, C2), connect second terminals of the first and second sampling switched capacitors (C1, C2) to an input common mode voltage (Vcmi) node, and during a gain phase, connect the second terminals of the first and second sampling switched capacitors (C1, C2) to the first amplifier input, connect the first terminal of the second sampling switched capacitor to the amplifier output, connect the first terminal of the first sampling switched capacitor to the first reference voltage (Vrefp) input node when the input voltage is above a high threshold voltage, to the second reference voltage (Vrefm) input node when the input voltage is below a low threshold voltage and to the input common mode voltage node when the input voltage is between the low and the high threshold voltages; and a common-mode reference voltage generation circuit comprising first and second additional switched capacitors (C3, C4), wherein the common-mode reference voltage generation circuit is configured to: during the sampling phase, reset the first and second additional switched capacitors (C3, C4) and during the gain phase, couple the first and second reference voltage input nodes to the first amplifier input by means of the first and second additional sampling switched capacitor (C3, C4) respectively when the input voltage is between the low and the high threshold voltages, thereby generating a common-mode reference voltage at the first amplifier input. an input node connected to receive an input voltage (Vin); first and second reference voltage input nodes connected to receive first and second reference voltages (Vrefp, Vrefm); an operational amplifier including a first amplifier input, a second amplifier input, and an amplifier output for outputting a residue voltage; an input sampling circuit comprising a first and second sampling switched capacitors (C1, C2), wherein the input sampling circuit is configured to: during a sampling phase, connect the input node to first terminals of the first and second sampling switched capacitors (C1, C2), connect second terminals of the first and second sampling switched capacitors (C1, C2) to an input common mode voltage (Vcmi) node, and during a gain phase, connect the second terminals of the first and second sampling switched capacitors (C1, C2) to the first amplifier input, connect the first terminal of the second sampling switched capacitor to the amplifier output, connect the first terminal of the first sampling switched capacitor to the first reference voltage (Vrefp) input node when the input voltage is above a high threshold voltage, to the second reference voltage (Vrefm) input node when the input voltage is below a low threshold voltage and to the input common mode voltage node when the input voltage is between the low and the high threshold voltages; and a common-mode reference voltage generation circuit comprising first and second additional switched capacitors (C3, C4), wherein the common-mode reference voltage generation circuit is configured to: during a sampling phase, connect the input node to first terminals of the first and second sampling switched capacitors (C1, C2), connect second terminals of the first and second sampling switched capacitors (C1, C2) to an input common mode voltage (Vcmi) node, and during a gain phase, connect the second terminals of the first and second sampling switched capacitors (C1, C2) to the first amplifier input, connect the first terminal of the second sampling switched capacitor to the amplifier output, connect the first terminal of the first sampling switched capacitor to the first reference voltage (Vrefp) input node when the input voltage is above a high threshold voltage, to the second reference voltage (Vrefm) input node when the input voltage is below a low threshold voltage and to the input common mode voltage node when the input voltage is between the low and the high threshold voltages; and a common-mode reference voltage generation circuit comprising first and second additional switched capacitors (C3, C4), wherein the common-mode reference voltage generation circuit is configured to: during the sampling phase, reset the first and second additional switched capacitors (C3, C4) and during the gain phase, couple the first and second reference voltage input nodes to the first amplifier input by means of the first and second additional sampling switched capacitor (C3, C4) respectively when the input voltage is between the low and the high threshold voltages, thereby generating a common-mode reference voltage at the first amplifier input.