A computer-implemented method for performing an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, the method comprising: receiving a 3D-IC die description, wherein the 3D-IC die description comprises a through-silicon via die, wherein the TSV die further includes: a front-side layer stack which includes a top metal layer; a back-side layer stack which includes at least one back-side metal layer; a double-sided substrate which is disposed between the front-side layer stack and the back-side layer stack; and a TSV which passes through the double-sided substrate, and which electrically couples the front-side layer stack with the back-side layer stack; transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description, and wherein said transforming involves transforming the TSV die into one or more 2D-IC die descriptions, wherein said transforming the TSV die into one or more 2D-IC die descriptions includes: creating a virtual front-side layer stack corresponding to the back-side layer stack, wherein the virtual front-side layer stack is created on top of the front-side layer stack of the TSV die; removing the back-side layer stack, thereby transforming the double-sided substrate into a single-sided substrate; creating a virtual substrate shield layer which is a conductor layer disposed between the virtual front-side layer stack and the top metal layer of the front-side layer stack, coupling the TSV to the virtual front-side layer stack while decoupling the TSV from the single-sided substrate, wherein the TSV passes through the virtual substrate shield layer; for each 2D-IC die description in the set of 2D-IC die descriptions, performing an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description. receiving a 3D-IC die description, wherein the 3D-IC die description comprises a through-silicon via die, wherein the TSV die further includes: a front-side layer stack which includes a top metal layer; a back-side layer stack which includes at least one back-side metal layer; a double-sided substrate which is disposed between the front-side layer stack and the back-side layer stack; and a TSV which passes through the double-sided substrate, and which electrically couples the front-side layer stack with the back-side layer stack; a front-side layer stack which includes a top metal layer; a back-side layer stack which includes at least one back-side metal layer; a double-sided substrate which is disposed between the front-side layer stack and the back-side layer stack; and a TSV which passes through the double-sided substrate, and which electrically couples the front-side layer stack with the back-side layer stack; transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description, and wherein said transforming involves transforming the TSV die into one or more 2D-IC die descriptions, wherein said transforming the TSV die into one or more 2D-IC die descriptions includes: creating a virtual front-side layer stack corresponding to the back-side layer stack, wherein the virtual front-side layer stack is created on top of the front-side layer stack of the TSV die; removing the back-side layer stack, thereby transforming the double-sided substrate into a single-sided substrate; creating a virtual substrate shield layer which is a conductor layer disposed between the virtual front-side layer stack and the top metal layer of the front-side layer stack, coupling the TSV to the virtual front-side layer stack while decoupling the TSV from the single-sided substrate, wherein the TSV passes through the virtual substrate shield layer; for each 2D-IC die description in the set of 2D-IC die descriptions, performing an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description. creating a virtual front-side layer stack corresponding to the back-side layer stack, wherein the virtual front-side layer stack is created on top of the front-side layer stack of the TSV die; removing the back-side layer stack, thereby transforming the double-sided substrate into a single-sided substrate; creating a virtual substrate shield layer which is a conductor layer disposed between the virtual front-side layer stack and the top metal layer of the front-side layer stack, coupling the TSV to the virtual front-side layer stack while decoupling the TSV from the single-sided substrate, wherein the TSV passes through the virtual substrate shield layer; for each 2D-IC die description in the set of 2D-IC die descriptions, performing an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.