An over-current protection system for a GOA circuit, comprising a power management chip, a level-shift chip electrically connecting with the power management chip, the level-shift chip electrically connecting with a GOA circuit, characterized in that: the level-shift chip comprising an over-current protection module; the over-current protection module comprising a current comparator, an AND gate circuit, a rising edge pulse delay circuit, a power supply, a voltage comparator, a first switch and a second switch, and a capacitor; a positive-phase input terminal of the current comparator acquiring a current (Isense) on the wiring of the clock signal in the GOA circuit, the reverse-phase input terminal of the current comparator receiving a reference current (Iref); a first input terminal of the AND gate circuit electrically connecting with an output terminal of the current comparator, a second input terminal of the AND gate circuit electrically connecting with an output terminal of the rising edge pulse delay circuit; an input terminal of the rising edge pulse delay circuit receiving a clock-signal control signal (HSDRV); one terminal of the capacitor electrically connecting with a first node and the other terminal of the capacitor grounding; one terminal of the first switch electrically connecting with the power supply, the other terminal of the first switch electrically connecting with the first node, and a control terminal of the first switch electrically connecting with an output terminal of the AND gate circuit; one terminal of the second switch electrically connecting with the first node, the other terminal of the second switch grounding, and a control terminal of the second switch receiving a start signal of the GOA circuit; a reverse-phase input terminal of the voltage comparator electrically connecting with the first node, a positive-phase input terminal of the voltage comparator receiving a reference voltage (Vref), and a output terminal of the voltage comparator electrically connecting with the power management chip; wherein a voltage level of the clock-signal control signal (HSDRV) corresponds to a voltage level of the clock signal in the GOA circuit; the power supply management chip supplies power to the GOA circuit via the level-shift chip; when a potential of the first node is higher than the reference voltage (Vref), the voltage comparator outputs an over-current protection control signal to the power supply management chip to control the power management chip to stop supplying power to the GOA circuit, to perform an over-current protection of the GOA circuit. the level-shift chip comprising an over-current protection module; the over-current protection module comprising a current comparator, an AND gate circuit, a rising edge pulse delay circuit, a power supply, a voltage comparator, a first switch and a second switch, and a capacitor; a positive-phase input terminal of the current comparator acquiring a current (Isense) on the wiring of the clock signal in the GOA circuit, the reverse-phase input terminal of the current comparator receiving a reference current (Iref); a first input terminal of the AND gate circuit electrically connecting with an output terminal of the current comparator, a second input terminal of the AND gate circuit electrically connecting with an output terminal of the rising edge pulse delay circuit; an input terminal of the rising edge pulse delay circuit receiving a clock-signal control signal (HSDRV); one terminal of the capacitor electrically connecting with a first node and the other terminal of the capacitor grounding; one terminal of the first switch electrically connecting with the power supply, the other terminal of the first switch electrically connecting with the first node, and a control terminal of the first switch electrically connecting with an output terminal of the AND gate circuit; one terminal of the second switch electrically connecting with the first node, the other terminal of the second switch grounding, and a control terminal of the second switch receiving a start signal of the GOA circuit; a reverse-phase input terminal of the voltage comparator electrically connecting with the first node, a positive-phase input terminal of the voltage comparator receiving a reference voltage (Vref), and a output terminal of the voltage comparator electrically connecting with the power management chip; wherein a voltage level of the clock-signal control signal (HSDRV) corresponds to a voltage level of the clock signal in the GOA circuit; the power supply management chip supplies power to the GOA circuit via the level-shift chip; when a potential of the first node is higher than the reference voltage (Vref), the voltage comparator outputs an over-current protection control signal to the power supply management chip to control the power management chip to stop supplying power to the GOA circuit, to perform an over-current protection of the GOA circuit.