A method involving a high-side transistor and a low-side transistor, wherein a source of the high-side transistor is coupled to a drain of the low-side transistor at a node, wherein a diode is disposed in parallel with the high-side transistor, the method comprising: (a) receiving a high-side driver digital control signal, wherein the high-side driver digital control signal has a first digital logic value; (b) in response to receiving the high-side driver digital control signal of the first digital logic value in (a) driving a high-side, HS, gate signal onto a gate of the high-side transistor such that the high-side transistor is controlled to be off; (c) determining that a current flow through the diode rises and exceeds a threshold current, wherein the determining of (c) occurs when the high-side driver digital control signal is at the first digital logic value; (d) in response to the determining of (c) driving the HS gate signal onto the gate of the high-side transistor such that the high-side transistor turns on; (e) receiving a low-side driver digital control signal, wherein the low-side driver digital control signal has the first digital logic value; (f) detecting that the low-side driver digital control signal transitions from the first digital logic value to a second digital logic value, wherein the low-side driver digital control signal transitions from the first digital logic value to the second digital logic value in (f) after the determining of (c); (g) in response to the detecting of (f) driving the HS gate signal onto the gate of the high-side transistor such that the high-side transistor is turned off; (h) determining that a gate-to-source voltage of the high-side transistor has dropped below a threshold voltage, wherein the gate-to-source voltage of the high-side transistor drops below the threshold voltage in (h) in response to the driving of the HS gate signal in (g); (i) in response to the determining of (h) driving a low-side, LS, gate signal onto a gate of the low-side transistor such that the low side transistor is controlled to turn on; and (j) driving the LS gate signal onto the gate of the low-side transistor such that the low side transistor remains on as long as the low-side driver digital control signal remains at the second digital logic value, wherein the high-side driver digital control signal remains at the first digital logic value and does not transition digital values to a second digital logic value at any time during steps (c) through (j). (a) receiving a high-side driver digital control signal, wherein the high-side driver digital control signal has a first digital logic value; (b) in response to receiving the high-side driver digital control signal of the first digital logic value in (a) driving a high-side, HS, gate signal onto a gate of the high-side transistor such that the high-side transistor is controlled to be off; (c) determining that a current flow through the diode rises and exceeds a threshold current, wherein the determining of (c) occurs when the high-side driver digital control signal is at the first digital logic value; (d) in response to the determining of (c) driving the HS gate signal onto the gate of the high-side transistor such that the high-side transistor turns on; (e) receiving a low-side driver digital control signal, wherein the low-side driver digital control signal has the first digital logic value; (f) detecting that the low-side driver digital control signal transitions from the first digital logic value to a second digital logic value, wherein the low-side driver digital control signal transitions from the first digital logic value to the second digital logic value in (f) after the determining of (c); (g) in response to the detecting of (f) driving the HS gate signal onto the gate of the high-side transistor such that the high-side transistor is turned off; (h) determining that a gate-to-source voltage of the high-side transistor has dropped below a threshold voltage, wherein the gate-to-source voltage of the high-side transistor drops below the threshold voltage in (h) in response to the driving of the HS gate signal in (g); (i) in response to the determining of (h) driving a low-side, LS, gate signal onto a gate of the low-side transistor such that the low side transistor is controlled to turn on; and (j) driving the LS gate signal onto the gate of the low-side transistor such that the low side transistor remains on as long as the low-side driver digital control signal remains at the second digital logic value, wherein the high-side driver digital control signal remains at the first digital logic value and does not transition digital values to a second digital logic value at any time during steps (c) through (j).