A processing circuit configured to process input signals from a capacitive transducer structure including a first capacitor and a second capacitor, the processing circuit including a current-to-voltage converter; one or more successive gain stage circuits; a reference voltage generator; wherein the current-to-voltage converter is configured to receive from the capacitive transducer structure a first input signal and a second input signal: the current-to-voltage converter includes: a first input node configured to receive from the capacitive transducer structure the first input signal that corresponds to a first variable capacitance generated by the first capacitor in response to a detected activity; and a second input node configured to receive from the capacitive transducer structure the second input signal that corresponds to a second variable capacitance generated by the second capacitor in response to the detected activity; wherein the first variable capacitance and the second variable capacitance are differentially detected capacitances; wherein the current-to-voltage converter is configured to output to a first gain stage of the gain stage circuits, and to the reference voltage generator a first voltage signal that corresponds to the first input signal, and a second voltage signal that corresponds to the second input signal; the gain stages include circuitry configured to generate from the first voltage signal and the second voltage signal an amplified output signal that is proportional to the difference of the first variable capacitance and the second variable capacitance; the reference voltage generator includes circuitry configured to generate from the first voltage signal and the second voltage signal a common mode output signal that is proportional to the sum of the first variable capacitance and the second variable capacitance; the circuitry of the reference voltage generator is configured to operate synchronized to the timing of the gain stages; the circuitry of the reference voltage generator includes feedback capacitors, timing of reset of the feedback capacitors being arranged to follow timing of the last gain stage; the processing circuit includes dividing circuitry configured to receive from the gain stages the amplified output signal and from the reference voltage generator the common mode output signal and generate a digital signal that corresponds to a quotient of the amplified output signal and the common mode output signal. the current-to-voltage converter includes: a first input node configured to receive from the capacitive transducer structure the first input signal that corresponds to a first variable capacitance generated by the first capacitor in response to a detected activity; and a second input node configured to receive from the capacitive transducer structure the second input signal that corresponds to a second variable capacitance generated by the second capacitor in response to the detected activity; wherein the first variable capacitance and the second variable capacitance are differentially detected capacitances; wherein the current-to-voltage converter is configured to output to a first gain stage of the gain stage circuits, and to the reference voltage generator a first voltage signal that corresponds to the first input signal, and a second voltage signal that corresponds to the second input signal; a first input node configured to receive from the capacitive transducer structure the first input signal that corresponds to a first variable capacitance generated by the first capacitor in response to a detected activity; and a second input node configured to receive from the capacitive transducer structure the second input signal that corresponds to a second variable capacitance generated by the second capacitor in response to the detected activity; wherein the first variable capacitance and the second variable capacitance are differentially detected capacitances; wherein the current-to-voltage converter is configured to output to a first gain stage of the gain stage circuits, and to the reference voltage generator a first voltage signal that corresponds to the first input signal, and a second voltage signal that corresponds to the second input signal; the gain stages include circuitry configured to generate from the first voltage signal and the second voltage signal an amplified output signal that is proportional to the difference of the first variable capacitance and the second variable capacitance; the reference voltage generator includes circuitry configured to generate from the first voltage signal and the second voltage signal a common mode output signal that is proportional to the sum of the first variable capacitance and the second variable capacitance; the circuitry of the reference voltage generator is configured to operate synchronized to the timing of the gain stages; the circuitry of the reference voltage generator includes feedback capacitors, timing of reset of the feedback capacitors being arranged to follow timing of the last gain stage; the processing circuit includes dividing circuitry configured to receive from the gain stages the amplified output signal and from the reference voltage generator the common mode output signal and generate a digital signal that corresponds to a quotient of the amplified output signal and the common mode output signal.