An organic light-emitting display device comprising a plurality of pixels arranged in a matrix form and a plurality of lines each configured to supply a signal for driving each pixel, wherein each pixel includes a thin-film transistor (210; 230) including an active layer having a first area (213; 238) and a second area (218; 232), which are configured as conductors, and a gate electrode, and wherein at least one of the first area and the second area is directly connected to a corresponding line among the plurality of lines, and wherein each pixel further includes a capacitor (Cst) including: a shield layer located on a substrate; a lower electrode configured to overlap the shield layer with a buffer layer interposed therebetween, the lower electrode being directly connected to the shield layer through a first contact hole and being formed of the first area of the active layer, which is configured as a conductor; an intermediate electrode configured to overlap the active layer with a gate insulation layer and an interlayer insulation layer interposed therebetween; and an upper electrode configured to overlap the intermediate electrode with a planarization layer interposed therebetween, and wherein the thin-film transistor is a driving transistor, wherein the driving transistor further includes a connection electrode configured to come into contact with the first area through a second contact hole, the connection electrode is connected to a pixel electrode through a third contact hole, and the second area is directly connected to a power line, which supplies a drive voltage to the pixel and is arranged in a vertical direction, among the plurality of lines through a fourth contact hole, and wherein the second area of the driving transistor includes a first electrode portion integrally formed with a channel area of the driving transistor and a first extension portion configured to extend from the first electrode portion so as to be connected to the power line, and wherein the first electrode portion of the driving transistor of a first pixel of the plurality of pixels extends from the channel area of the driving transistor of the first pixel and is directly connected to the first electrode portion of the driving transistor of a second pixel of the plurality of pixels, the second pixel neighboring the first pixel, wherein the first extension portion of the driving transistor of the first pixel directly contacts the first electrode portion of the driving transistor of the first pixel and the first electrode portion of the driving transistor of the second pixel and is connected to the power line. wherein each pixel includes a thin-film transistor (210; 230) including an active layer having a first area (213; 238) and a second area (218; 232), which are configured as conductors, and a gate electrode, and wherein at least one of the first area and the second area is directly connected to a corresponding line among the plurality of lines, and wherein each pixel further includes a capacitor (Cst) including: a shield layer located on a substrate; a lower electrode configured to overlap the shield layer with a buffer layer interposed therebetween, the lower electrode being directly connected to the shield layer through a first contact hole and being formed of the first area of the active layer, which is configured as a conductor; an intermediate electrode configured to overlap the active layer with a gate insulation layer and an interlayer insulation layer interposed therebetween; and an upper electrode configured to overlap the intermediate electrode with a planarization layer interposed therebetween, and a shield layer located on a substrate; a lower electrode configured to overlap the shield layer with a buffer layer interposed therebetween, the lower electrode being directly connected to the shield layer through a first contact hole and being formed of the first area of the active layer, which is configured as a conductor; an intermediate electrode configured to overlap the active layer with a gate insulation layer and an interlayer insulation layer interposed therebetween; and an upper electrode configured to overlap the intermediate electrode with a planarization layer interposed therebetween, and wherein the thin-film transistor is a driving transistor, wherein the driving transistor further includes a connection electrode configured to come into contact with the first area through a second contact hole, the connection electrode is connected to a pixel electrode through a third contact hole, and the second area is directly connected to a power line, which supplies a drive voltage to the pixel and is arranged in a vertical direction, among the plurality of lines through a fourth contact hole, and wherein the second area of the driving transistor includes a first electrode portion integrally formed with a channel area of the driving transistor and a first extension portion configured to extend from the first electrode portion so as to be connected to the power line, and wherein the first electrode portion of the driving transistor of a first pixel of the plurality of pixels extends from the channel area of the driving transistor of the first pixel and is directly connected to the first electrode portion of the driving transistor of a second pixel of the plurality of pixels, the second pixel neighboring the first pixel, wherein the first extension portion of the driving transistor of the first pixel directly contacts the first electrode portion of the driving transistor of the first pixel and the first electrode portion of the driving transistor of the second pixel and is connected to the power line.