A computing system, comprising: at least one central processing unit; one or more central processing unit caches; a main memory comprising a plurality of locations, wherein each location of the plurality of locations maps to a set in the one or more central processing unit caches, wherein a first subset of locations (204-1, 224-1, 244-1) of the plurality of locations are partitioned for one or more threads of a first application and assigned to non-contiguous memory locations of the main memory based on a respective set of one or more sets in the one or more central processing unit caches to which each location is mapped; and a first input/output, I/O, device configured to store data in a second subset of locations (204-2, 224-2, 244-2) of the plurality of locations that are different from the first subset of locations (204-1, 224-1, 244-1) partitioned for the one or more threads of the first application, wherein the second subset of locations (204-2, 224-2, 244-2) are non-contiguous memory locations of the main memory that are separated in address space according to a predefined pattern, characterised in that the first I/O device is either configured to retrieve, prior to each time the first I/O device inputs data to the main memory in order to determine where to store the I/O data, the predefined pattern that is stored in the main memory as linked-list descriptors that include pointers indicating where data is to be written next, or configured to determine the predefined pattern either from an I/O configuration interface or based on information stored in a set of registers of the first I/O device. at least one central processing unit; one or more central processing unit caches; a main memory comprising a plurality of locations, wherein each location of the plurality of locations maps to a set in the one or more central processing unit caches, wherein a first subset of locations (204-1, 224-1, 244-1) of the plurality of locations are partitioned for one or more threads of a first application and assigned to non-contiguous memory locations of the main memory based on a respective set of one or more sets in the one or more central processing unit caches to which each location is mapped; and a first input/output, I/O, device configured to store data in a second subset of locations (204-2, 224-2, 244-2) of the plurality of locations that are different from the first subset of locations (204-1, 224-1, 244-1) partitioned for the one or more threads of the first application, wherein the second subset of locations (204-2, 224-2, 244-2) are non-contiguous memory locations of the main memory that are separated in address space according to a predefined pattern, characterised in that the first I/O device is either configured to retrieve, prior to each time the first I/O device inputs data to the main memory in order to determine where to store the I/O data, the predefined pattern that is stored in the main memory as linked-list descriptors that include pointers indicating where data is to be written next, or configured to determine the predefined pattern either from an I/O configuration interface or based on information stored in a set of registers of the first I/O device.