A method of calibrating a time-to-digital converter, hereafter abbreviated TDC, comprising first and second delay paths (510a, 510b), wherein the second delay path comprises - a first set of inverters (514b - 514n) coupled in series and configured to receive a second input signal (Sinb), and - a set of flip-flops (516a - 516n) each coupled to a respective one of the first set of inverters and configured to receive a second reference signal and provide a set of output signals (D21.. D2N), wherein each inverter of the first set of inverters delays its input signal by one inverter delay, Tinv; the method comprising: adjusting delay of a first reference signal for the first delay path until the first reference signal is time-aligned with a first input signal (Sin) for the first delay path, and recording this delay as a delay W1; and adjusting delay of the, second reference signal for the second delay path until the second reference signal is time-aligned with the second input signal (Sinb) for the second delay path, and recording this delay as a delay W2, further adjusting the delay of the second reference signal until an output of the first inverter of the first set of inverters is time-aligned with the second input signal (Sinb) to obtain a one additional inverter delay W2full for the second reference signal; determining a half inverter delay, W2half, for the second reference signal based on the delay W2 plus the difference between the delay W2 and the delay W2full to obtain one additional inverter delay for the second reference signal, W2, to time align the second reference signal with the second input signal; and configuring the TDC to delay the first reference signal by the delay W1 and the second reference signal by the delay W2half such that the second reference signal is time-aligned by one half inverter delay relative to the first reference signal. - a first set of inverters (514b - 514n) coupled in series and configured to receive a second input signal (Sinb), and - a set of flip-flops (516a - 516n) each coupled to a respective one of the first set of inverters and configured to receive a second reference signal and provide a set of output signals (D21.. D2N), wherein each inverter of the first set of inverters delays its input signal by one inverter delay, Tinv; the method comprising: adjusting delay of a first reference signal for the first delay path until the first reference signal is time-aligned with a first input signal (Sin) for the first delay path, and recording this delay as a delay W1; and adjusting delay of the, second reference signal for the second delay path until the second reference signal is time-aligned with the second input signal (Sinb) for the second delay path, and recording this delay as a delay W2, further adjusting the delay of the second reference signal until an output of the first inverter of the first set of inverters is time-aligned with the second input signal (Sinb) to obtain a one additional inverter delay W2full for the second reference signal; determining a half inverter delay, W2half, for the second reference signal based on the delay W2 plus the difference between the delay W2 and the delay W2full to obtain one additional inverter delay for the second reference signal, W2, to time align the second reference signal with the second input signal; and configuring the TDC to delay the first reference signal by the delay W1 and the second reference signal by the delay W2half such that the second reference signal is time-aligned by one half inverter delay relative to the first reference signal. adjusting delay of a first reference signal for the first delay path until the first reference signal is time-aligned with a first input signal (Sin) for the first delay path, and recording this delay as a delay W1; and adjusting delay of the, second reference signal for the second delay path until the second reference signal is time-aligned with the second input signal (Sinb) for the second delay path, and recording this delay as a delay W2, further adjusting the delay of the second reference signal until an output of the first inverter of the first set of inverters is time-aligned with the second input signal (Sinb) to obtain a one additional inverter delay W2full for the second reference signal; determining a half inverter delay, W2half, for the second reference signal based on the delay W2 plus the difference between the delay W2 and the delay W2full to obtain one additional inverter delay for the second reference signal, W2, to time align the second reference signal with the second input signal; and configuring the TDC to delay the first reference signal by the delay W1 and the second reference signal by the delay W2half such that the second reference signal is time-aligned by one half inverter delay relative to the first reference signal.