A memory, comprising: first (300_U, 301_U) and second (300_D, 301_D) arrays of non-volatile re-programmable memory elements, a row of sensing circuits disposed between first and second arrays, a set of global bit lines; wherein said first (300_U, 301_U) and second (300_D, 301_D) arrays each comprises: memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes (101, 103),...) stacked in the z-direction; and a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; wherein a selected row of re-programmable memory elements (M, 200) in each array is accessible by a selected word line and a selected row of local bit lines at a plurality of crossing with the selected word line; characterized by providing a reference row (301_U, 301_D) of non-volatile reprogrammable memory elements in each of the first and second arrays for storing a value associated a location of the word line at each crossing so as to provide a reference adjustment to compensate the location due to finite resistance along the word line; the set of global bit lines traversing said first and second arrays along the y-direction and said row of sensing circuits, each global bit line having in-line first and second segments, the first segment of the global bit line for switchably coupling a respective local bit line of a selected row of local bit lines in said first array to a respective sensing circuit in said row of sensing circuits, and the second segment for simultaneously switchably coupling a respective local bit line of a selected row of local bit lines in said second array to a respective sensing circuit in said row of sensing circuits. first (300_U, 301_U) and second (300_D, 301_D) arrays of non-volatile re-programmable memory elements, a row of sensing circuits disposed between first and second arrays, a set of global bit lines; wherein said first (300_U, 301_U) and second (300_D, 301_D) arrays each comprises: memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes (101, 103),...) stacked in the z-direction; and a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; wherein memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes (101, 103),...) stacked in the z-direction; and a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; a selected row of re-programmable memory elements (M, 200) in each array is accessible by a selected word line and a selected row of local bit lines at a plurality of crossing with the selected word line; characterized by providing a reference row (301_U, 301_D) of non-volatile reprogrammable memory elements in each of the first and second arrays for storing a value associated a location of the word line at each crossing so as to provide a reference adjustment to compensate the location due to finite resistance along the word line; the set of global bit lines traversing said first and second arrays along the y-direction and said row of sensing circuits, each global bit line having in-line first and second segments, the first segment of the global bit line for switchably coupling a respective local bit line of a selected row of local bit lines in said first array to a respective sensing circuit in said row of sensing circuits, and the second segment for simultaneously switchably coupling a respective local bit line of a selected row of local bit lines in said second array to a respective sensing circuit in said row of sensing circuits.