A clamping circuit comprising: a rate amplifier configured to receive an output from a device transitioning between at least two levels; and two switching devices (200, 201) configured to receive an output from the rate amplifier, the two switching devices in respective feedback loops of the rate amplifier, wherein switching of the two switching devices causes the rate amplifier to amplify with high linearity in a desired operating range and to clamp outputs received from the transitioning device that are outside the desired operating range to respective fixed levels, characterised in that: a first switching device of the two switching devices is an NPN bipolar junction transistor, wherein a collector of the NPN bipolar junction transistor is directly connected to an inverting input of the rate amplifier; and a second switching device of the two switching devices is a PNP bipolar junction transistor, wherein a collector of the PNP bipolar junction transistor is directly connected to the inverting input of the rate amplifier; the clamping circuit further comprising: a positive voltage source; a first diode; a second diode, wherein an output of the positive voltage source, and anode of the first diode, and a cathode of the second diode are connected to a base of the PNP bipolar junction transistor; a negative voltage source; a third diode; and a fourth diode, wherein an output of the negative voltage source, an anode of the third diode, and a cathode of the fourth diode are connected to a base of the NPN bipolar junction transistor. a rate amplifier configured to receive an output from a device transitioning between at least two levels; and two switching devices (200, 201) configured to receive an output from the rate amplifier, the two switching devices in respective feedback loops of the rate amplifier, wherein switching of the two switching devices causes the rate amplifier to amplify with high linearity in a desired operating range and to clamp outputs received from the transitioning device that are outside the desired operating range to respective fixed levels, characterised in that: a first switching device of the two switching devices is an NPN bipolar junction transistor, wherein a collector of the NPN bipolar junction transistor is directly connected to an inverting input of the rate amplifier; and a second switching device of the two switching devices is a PNP bipolar junction transistor, wherein a collector of the PNP bipolar junction transistor is directly connected to the inverting input of the rate amplifier; the clamping circuit further comprising: a positive voltage source; a first diode; a second diode, wherein an output of the positive voltage source, and anode of the first diode, and a cathode of the second diode are connected to a base of the PNP bipolar junction transistor; a negative voltage source; a third diode; and a fourth diode, wherein an output of the negative voltage source, an anode of the third diode, and a cathode of the fourth diode are connected to a base of the NPN bipolar junction transistor. a first switching device of the two switching devices is an NPN bipolar junction transistor, wherein a collector of the NPN bipolar junction transistor is directly connected to an inverting input of the rate amplifier; and a second switching device of the two switching devices is a PNP bipolar junction transistor, wherein a collector of the PNP bipolar junction transistor is directly connected to the inverting input of the rate amplifier; the clamping circuit further comprising: a positive voltage source; a first diode; a second diode, wherein an output of the positive voltage source, and anode of the first diode, and a cathode of the second diode are connected to a base of the PNP bipolar junction transistor; a negative voltage source; a third diode; and a fourth diode, wherein an output of the negative voltage source, an anode of the third diode, and a cathode of the fourth diode are connected to a base of the NPN bipolar junction transistor. a positive voltage source; a first diode; a second diode, wherein an output of the positive voltage source, and anode of the first diode, and a cathode of the second diode are connected to a base of the PNP bipolar junction transistor; a negative voltage source; a third diode; and a fourth diode, wherein an output of the negative voltage source, an anode of the third diode, and a cathode of the fourth diode are connected to a base of the NPN bipolar junction transistor.