A data interface comprising: an electrostatic discharge circuit; and a charge transmitting circuit, connected to a binding wire through the electrostatic discharge circuit, wherein the charge transmitting circuit comprises a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire; wherein the charge transmitting circuit further comprises: a first MOS transistor, a second MOS transistor and a third MOS transistor; wherein a source of the first MOS transistor is configured to receive a power supply voltage, a drain of the first MOS transistor is connected to the ground through the first capacitor, a gate of the first MOS transistor is configured to receive a first control signal, the drain of the first MOS transistor is connected to a source of the second MOS transistor, a drain of the second MOS transistor is configured to output the first voltage signal, a gate of the second MOS transistor is configured to receive the first control signal, and the drain of the second MOS transistor is connected to the ground through the third MOS transistor, and a gate of the third MOS transistor is configured to receive a second control signal. an electrostatic discharge circuit; and a charge transmitting circuit, connected to a binding wire through the electrostatic discharge circuit, wherein the charge transmitting circuit comprises a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire; wherein the charge transmitting circuit further comprises: a first MOS transistor, a second MOS transistor and a third MOS transistor; wherein a source of the first MOS transistor is configured to receive a power supply voltage, a drain of the first MOS transistor is connected to the ground through the first capacitor, a gate of the first MOS transistor is configured to receive a first control signal, the drain of the first MOS transistor is connected to a source of the second MOS transistor, a drain of the second MOS transistor is configured to output the first voltage signal, a gate of the second MOS transistor is configured to receive the first control signal, and the drain of the second MOS transistor is connected to the ground through the third MOS transistor, and a gate of the third MOS transistor is configured to receive a second control signal. a first MOS transistor, a second MOS transistor and a third MOS transistor; wherein a source of the first MOS transistor is configured to receive a power supply voltage, a drain of the first MOS transistor is connected to the ground through the first capacitor, a gate of the first MOS transistor is configured to receive a first control signal, the drain of the first MOS transistor is connected to a source of the second MOS transistor, a drain of the second MOS transistor is configured to output the first voltage signal, a gate of the second MOS transistor is configured to receive the first control signal, and the drain of the second MOS transistor is connected to the ground through the third MOS transistor, and a gate of the third MOS transistor is configured to receive a second control signal.