A method of manufacturing a floating gate semiconductor memory device, the method comprising: - providing a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising: - a semiconductor base layer, - on and in contact with said base layer: a dielectric layer, - on and in contact with said dielectric layer: a monocrystalline semiconductor top layer, - providing at least two trenches (121,122,123) in the semiconductor-on-insulator substrate, the trenches extending through the semiconductor top layer, the dielectric layer and partially through the semiconductor base layer, thereby forming at least one elevated structure, the elevated structure comprising: - a base portion, which is part of the base substrate, - on and in contact with said base portion: a dielectric portion, which is part of the dielectric layer, - on and in contact with said dielectric portion, a monocrystalline semiconductor top portion, which is part of the semiconductor top layer; - providing isolation regions at the bottom of each of said trenches; - providing a gate dielectric layer at least at the sidewall surfaces of the elevated structure(s), by a thermal oxidation of the sidewall surfaces of the top portion of the elevated structure(s); - providing a conductive layer over the elevated structure(s) and the gate dielectric layer, to thereby form at least one floating gate semiconductor memory device, said gate dielectric region acting as the interpoly dielectric layer, said dielectric portion acting as the tunnel dielectric layer, said semiconductor top portion acting as the floating gate and said conductive layer acting as the control gate. - providing a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising: - a semiconductor base layer, - on and in contact with said base layer: a dielectric layer, - on and in contact with said dielectric layer: a monocrystalline semiconductor top layer, - a semiconductor base layer, - on and in contact with said base layer: a dielectric layer, - on and in contact with said dielectric layer: a monocrystalline semiconductor top layer, - providing at least two trenches (121,122,123) in the semiconductor-on-insulator substrate, the trenches extending through the semiconductor top layer, the dielectric layer and partially through the semiconductor base layer, thereby forming at least one elevated structure, the elevated structure comprising: - a base portion, which is part of the base substrate, - on and in contact with said base portion: a dielectric portion, which is part of the dielectric layer, - on and in contact with said dielectric portion, a monocrystalline semiconductor top portion, which is part of the semiconductor top layer; - a base portion, which is part of the base substrate, - on and in contact with said base portion: a dielectric portion, which is part of the dielectric layer, - on and in contact with said dielectric portion, a monocrystalline semiconductor top portion, which is part of the semiconductor top layer; - providing isolation regions at the bottom of each of said trenches; - providing a gate dielectric layer at least at the sidewall surfaces of the elevated structure(s), by a thermal oxidation of the sidewall surfaces of the top portion of the elevated structure(s); - providing a conductive layer over the elevated structure(s) and the gate dielectric layer, to thereby form at least one floating gate semiconductor memory device, said gate dielectric region acting as the interpoly dielectric layer, said dielectric portion acting as the tunnel dielectric layer, said semiconductor top portion acting as the floating gate and said conductive layer acting as the control gate.