A method of forming a device with a piezoresistor, comprising: providing a silicon on insulator substrate (102;200), the SOI substrate (102; 200) including an SOI handle layer (104; 202), a buried oxide layer (106; 204), and an SOI active layer (108; 206); etching a trench (110; 230) in the SOI active layer (102; 206) to form a vertical wall defining an anchor area (116; 224), a proof mass area (146; 228; 226), and a tether area extending between the anchor area (116; 224) and the proof mass area (146; 228); implanting a central conductive trace (138; 242) in the SOI active layer (108;206), the location of the implanted central conductive trace (138; 242) selected such that after the trench (110; 230) etching, the central conductive trace (138; 242) extends from the proof mass area (146; 228) along the tether area (130; 226) to the anchor area (116; 224); the method characterized in that it comprises: growing an epitaxial layer having piezoresistive properties on the vertical wall; removing the epitaxial piezoresistor layer from the vertical wall portions of the anchor area (116: 224) and the proof mass area (146; 228); and separating the vertical wall from the SOI handle layer (104; 202) that extends along a horizontal plane by removing portions of the buried oxide layer (106; 204) to release the tether area (130; 226) and the proof mass area (146; 228) from the SOI handle layer (104:, 202) so that the anchor area (116; 224) supports the tether area (130; 226), and the tether area (116:, 224) with the piezoresistor laver is movable with respect to the underlying layer within the horizontal plane, and the proof mass area (146:, 228) is supported by the tether area (116; 224). providing a silicon on insulator substrate (102;200), the SOI substrate (102; 200) including an SOI handle layer (104; 202), a buried oxide layer (106; 204), and an SOI active layer (108; 206); etching a trench (110; 230) in the SOI active layer (102; 206) to form a vertical wall defining an anchor area (116; 224), a proof mass area (146; 228; 226), and a tether area extending between the anchor area (116; 224) and the proof mass area (146; 228); implanting a central conductive trace (138; 242) in the SOI active layer (108;206), the location of the implanted central conductive trace (138; 242) selected such that after the trench (110; 230) etching, the central conductive trace (138; 242) extends from the proof mass area (146; 228) along the tether area (130; 226) to the anchor area (116; 224); the method characterized in that it comprises: growing an epitaxial layer having piezoresistive properties on the vertical wall; removing the epitaxial piezoresistor layer from the vertical wall portions of the anchor area (116: 224) and the proof mass area (146; 228); and separating the vertical wall from the SOI handle layer (104; 202) that extends along a horizontal plane by removing portions of the buried oxide layer (106; 204) to release the tether area (130; 226) and the proof mass area (146; 228) from the SOI handle layer (104:, 202) so that the anchor area (116; 224) supports the tether area (130; 226), and the tether area (116:, 224) with the piezoresistor laver is movable with respect to the underlying layer within the horizontal plane, and the proof mass area (146:, 228) is supported by the tether area (116; 224). growing an epitaxial layer having piezoresistive properties on the vertical wall; removing the epitaxial piezoresistor layer from the vertical wall portions of the anchor area (116: 224) and the proof mass area (146; 228); and separating the vertical wall from the SOI handle layer (104; 202) that extends along a horizontal plane by removing portions of the buried oxide layer (106; 204) to release the tether area (130; 226) and the proof mass area (146; 228) from the SOI handle layer (104:, 202) so that the anchor area (116; 224) supports the tether area (130; 226), and the tether area (116:, 224) with the piezoresistor laver is movable with respect to the underlying layer within the horizontal plane, and the proof mass area (146:, 228) is supported by the tether area (116; 224).