A bidirectional data exchange circuit including: - a buffer including: - a first set of terminals (A1... A8) and a second set of terminals (B1... B8) the terminals of which are matched pairwise for a bidirectional data exchange between two matched terminals of both sets; - a transfer direction input between two matched terminals from an input to an output, the input being placed at a high impedance state in the absence of voltage on these terminals; - an input (42; 142) for controlling the transfer direction; characterized in that it includes: - a logic gate (50; 150) for which: - the output is connected to the transfer direction input of the buffer; - an input is connected to the input for controlling the transfer direction (42; 142), this input being further connected to a first reference potential (V cc; 0) through a resistor (52; 152); and - the other input is connected to a terminal (A1; B1) of the buffer and to the first reference potential (V cc; 0) through a resistor (54; 154); - the terminal (B1; A1) of the buffer matched with the terminal (A1; B1) of the buffer to which is connected the other input of the logic gate (50; 150) being connected to a second reference potential (0; V cc) through a resistor (56; 156); and in that the first and second reference potentials and the nature of the logic gate (50; 150) are such that, after a first transfer direction control of the buffer in one direction, the two matched terminals (A1; B1) reserved for the control module force the logic gate (50; 150) into a predetermined state independent of the value of the signal on the direction control input (42; 142). - a buffer including: - a first set of terminals (A1... A8) and a second set of terminals (B1... B8) the terminals of which are matched pairwise for a bidirectional data exchange between two matched terminals of both sets; - a transfer direction input between two matched terminals from an input to an output, the input being placed at a high impedance state in the absence of voltage on these terminals; - a first set of terminals (A1... A8) and a second set of terminals (B1... B8) the terminals of which are matched pairwise for a bidirectional data exchange between two matched terminals of both sets; - a transfer direction input between two matched terminals from an input to an output, the input being placed at a high impedance state in the absence of voltage on these terminals; - an input (42; 142) for controlling the transfer direction; - a logic gate (50; 150) for which: - the output is connected to the transfer direction input of the buffer; - an input is connected to the input for controlling the transfer direction (42; 142), this input being further connected to a first reference potential (V cc; 0) through a resistor (52; 152); and - the other input is connected to a terminal (A1; B1) of the buffer and to the first reference potential (V cc; 0) through a resistor (54; 154); - the output is connected to the transfer direction input of the buffer; - an input is connected to the input for controlling the transfer direction (42; 142), this input being further connected to a first reference potential (V cc; 0) through a resistor (52; 152); and - the other input is connected to a terminal (A1; B1) of the buffer and to the first reference potential (V cc; 0) through a resistor (54; 154); - the terminal (B1; A1) of the buffer matched with the terminal (A1; B1) of the buffer to which is connected the other input of the logic gate (50; 150) being connected to a second reference potential (0; V cc) through a resistor (56; 156);