An integrated circuit comprising: programmable/configurable logic circuitry having a periphery, the programmable/configurable logic circuitry including: a plurality of logic tiles (00, 10), arranged in an array, wherein each logic tile includes a plurality of I/O arranged in a common I/O layout on the perimeter thereof, wherein each I/O of the I/O layout is configurable as i) an external I/O to connect to and communicate with circuitry external to the programmable/configurable logic circuitry, ii) a memory I/O to directly connect to memory disposed adjacent thereto, or iii) an unused I/O, and wherein each logic tile further includes interconnect I/O to connect to an interconnect network via a plurality of multiplexers, wherein the plurality of logic tiles includes: a first logic tile having A) a perimeter including i) a first portion of the perimeter which forms at least a portion of the periphery of the programmable/configurable logic circuitry, wherein external I/O, capable of directly connecting to and communicating with circuitry external to the programmable/configurable logic circuitry, is disposed on the first portion of the perimeter, and ii) a second portion of the perimeter which is interior to the periphery of the programmable/configurable logic circuitry, wherein memory I/O of the first logic tile is disposed on the second portion of the perimeter thereof to directly connect to memory disposed adjacent thereto, and B) circuitry, electrically coupled to the memory I/O, configurable to send data, address and control signals to interface with and access data in the memory via the memory I/O, and a second logic tile having a perimeter including i) a first portion of the perimeter and ii) a second portion of the perimeter which a) is interior to the periphery of the programmable/configurable logic circuitry and b) opposes the second portion of the perimeter of the first logic tile; and a first array of block memory, located between and adjacent to the second portion of the perimeter of the first logic tile and the second portion of the perimeter of the second logic tile, wherein the first array of block memory is electrically and point-to-point connected to the memory I/O disposed on the second portion of the perimeter of the first logic tile; and wherein the circuitry of the first logic tile is configured to send data, address and control signals to interface with and access data in the first array of block memory via the memory I/O disposed on the second portion of the perimeter of the first logic tile in operation of the programmable/configurable logic circuitry. a first logic tile having A) a perimeter including i) a first portion of the perimeter which forms at least a portion of the periphery of the programmable/configurable logic circuitry, wherein external I/O, capable of directly connecting to and communicating with circuitry external to the programmable/configurable logic circuitry, is disposed on the first portion of the perimeter, and ii) a second portion of the perimeter which is interior to the periphery of the programmable/configurable logic circuitry, wherein memory I/O of the first logic tile is disposed on the second portion of the perimeter thereof to directly connect to memory disposed adjacent thereto, and B) circuitry, electrically coupled to the memory I/O, configurable to send data, address and control signals to interface with and access data in the memory via the memory I/O, and a second logic tile having a perimeter including i) a first portion of the perimeter and ii) a second portion of the perimeter which a) is interior to the periphery of the programmable/configurable logic circuitry and b) opposes the second portion of the perimeter of the first logic tile; and a first array of block memory, located between and adjacent to the second portion of the perimeter of the first logic tile and the second portion of the perimeter of the second logic tile, wherein the first array of block memory is electrically and point-to-point connected to the memory I/O disposed on the second portion of the perimeter of the first logic tile; and wherein the circuitry of the first logic tile is configured to send data, address and control signals to interface with and access data in the first array of block memory via the memory I/O disposed on the second portion of the perimeter of the first logic tile in operation of the programmable/configurable logic circuitry.