A memory device (400, 500) comprising: a magnetic layer including a plurality of magnetic random access memory (MRAM) cells (302a, 302b, 302c, 302d); a first conductive layer (440, 540) including a conductive portion electrically connected to at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d), and a field line (318a, 318b, 318c, 318d) configured to write data to the at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d); a layer including a strap (406a, 406b) connecting MRAM cells included in the plurality of MRAM cells (302a, 302b, 302c, 302d); and a second conductive layer (442, 542) including a conductive interconnect (412a, 412b, 512) electrically connected to the at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d), wherein the magnetic layer is disposed between the first conductive layer (440, 540) and the second conductive layer (442, 542); characterized in that: at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d) is directly attached to the second conductive layer and the strap (406a, 406b); the memory device further comprises a third conductive layer including a bit line electrically connected to the at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d); the second conductive layer is disposed between the magnetic layer and the third conductive layer; and a via extends from the third conductive layer to the second conductive layer. a magnetic layer including a plurality of magnetic random access memory (MRAM) cells (302a, 302b, 302c, 302d); a first conductive layer (440, 540) including a conductive portion electrically connected to at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d), and a field line (318a, 318b, 318c, 318d) configured to write data to the at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d); a layer including a strap (406a, 406b) connecting MRAM cells included in the plurality of MRAM cells (302a, 302b, 302c, 302d); and a second conductive layer (442, 542) including a conductive interconnect (412a, 412b, 512) electrically connected to the at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d), wherein the magnetic layer is disposed between the first conductive layer (440, 540) and the second conductive layer (442, 542); characterized in that: at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d) is directly attached to the second conductive layer and the strap (406a, 406b); the memory device further comprises a third conductive layer including a bit line electrically connected to the at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d); the second conductive layer is disposed between the magnetic layer and the third conductive layer; and a via extends from the third conductive layer to the second conductive layer. at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d) is directly attached to the second conductive layer and the strap (406a, 406b); the memory device further comprises a third conductive layer including a bit line electrically connected to the at least one of the plurality of MRAM cells (302a, 302b, 302c, 302d); the second conductive layer is disposed between the magnetic layer and the third conductive layer; and a via extends from the third conductive layer to the second conductive layer.