A semiconductor memory device including: a first semiconductor memory and a second semiconductor memory, the second semiconductor memory is a cache of the first semiconductor memory, wherein said semiconductor memory device is accessible from outside by a host device (11 a) executing at least a management program to access the semiconductor memory device on logical memory addresses comprising at least a first address region and a second address region, the first address region being set in one-to-one correspondence with a logical address region (40_000-40_3FF) of the first semiconductor memory, at least part of the second semiconductor memory, which corresponds to a cache region, being mapped to the first address region, and wherein the semiconductor memory device further comprises a control circuit for judging internal state of the second semiconductor memory and for controlling data transfer between the first semiconductor memory and the second semiconductor memory by accessing the second address region, correspondence information stored in said control circuit being accessible on the second address region, said correspondence information indicating which region of the first semiconductor memory is stored in which region of the second semiconductor memory, said control circuit being responsive to predetermined information being written to the second address region from the host device, to transfer corresponding desired block region data in the first semiconductor memory to the cache region and to notify completion of the transfer to the host device when the transfer is completed, and when the first address region is accessed from the host device, the corresponding region of the first semiconductor memory is accessed via the cache region, said cache region being determined based on the correspondence information. a first semiconductor memory and a second semiconductor memory, the second semiconductor memory is a cache of the first semiconductor memory, wherein said semiconductor memory device is accessible from outside by a host device (11 a) executing at least a management program to access the semiconductor memory device on logical memory addresses comprising at least a first address region and a second address region, the first address region being set in one-to-one correspondence with a logical address region (40_000-40_3FF) of the first semiconductor memory, at least part of the second semiconductor memory, which corresponds to a cache region, being mapped to the first address region, and wherein the semiconductor memory device further comprises a control circuit for judging internal state of the second semiconductor memory and for controlling data transfer between the first semiconductor memory and the second semiconductor memory by accessing the second address region, correspondence information stored in said control circuit being accessible on the second address region, said correspondence information indicating which region of the first semiconductor memory is stored in which region of the second semiconductor memory, said control circuit being responsive to predetermined information being written to the second address region from the host device, to transfer corresponding desired block region data in the first semiconductor memory to the cache region and to notify completion of the transfer to the host device when the transfer is completed, and when the first address region is accessed from the host device, the corresponding region of the first semiconductor memory is accessed via the cache region, said cache region being determined based on the correspondence information.