A memory device, comprising: a plurality of memory cells configured in rows and columns on a semiconductor substrate, wherein each of the memory cells includes: source and drain regions formed in the substrate and defining a channel region of the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a control gate disposed over and insulated from a second portion of the channel region; a plurality of word lines each electrically connecting together the control gates for one of the rows of the memory cells; a plurality of bit lines each electrically connecting together the drain regions for one of the columns of the memory cells; a plurality of first sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns of the memory cells; a plurality of second sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns of the memory cells, wherein the first plurality of the columns is different from the second plurality of the columns, and the first sub source lines are electrically isolated from the source regions of the memory cells in the second plurality of the columns, and the second sub source lines are electrically isolated from the source regions of the memory cells in the first plurality of the columns; a first source line and a second source line; a plurality of first select transistors each connected between one of the first sub source lines and the first source line; a plurality of second select transistors each connected between one of the second sub source lines and the second source line; a plurality of third select transistors each connected between one of first sub source lines and the first source line, wherein for each one of the first sub source lines, one of the first select transistors and one of the third select transistors are connected between the one first sub source line and the first source line; a plurality of fourth select transistors each connected between one of second sub source lines and the second source line, wherein for each one of the second sub source lines, one of the second select transistors and one of the fourth select transistors are connected between the one second sub source line and the second source line; a plurality of select transistor lines each connected to a gate of one of the first select transistors and a gate of one of the second select transistors. a plurality of memory cells configured in rows and columns on a semiconductor substrate, wherein each of the memory cells includes: source and drain regions formed in the substrate and defining a channel region of the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a control gate disposed over and insulated from a second portion of the channel region; source and drain regions formed in the substrate and defining a channel region of the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a control gate disposed over and insulated from a second portion of the channel region; a plurality of word lines each electrically connecting together the control gates for one of the rows of the memory cells; a plurality of bit lines each electrically connecting together the drain regions for one of the columns of the memory cells; a plurality of first sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns of the memory cells; a plurality of second sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns of the memory cells, wherein the first plurality of the columns is different from the second plurality of the columns, and the first sub source lines are electrically isolated from the source regions of the memory cells in the second plurality of the columns, and the second sub source lines are electrically isolated from the source regions of the memory cells in the first plurality of the columns; a first source line and a second source line; a plurality of first select transistors each connected between one of the first sub source lines and the first source line; a plurality of second select transistors each connected between one of the second sub source lines and the second source line; a plurality of third select transistors each connected between one of first sub source lines and the first source line, wherein for each one of the first sub source lines, one of the first select transistors and one of the third select transistors are connected between the one first sub source line and the first source line; a plurality of fourth select transistors each connected between one of second sub source lines and the second source line, wherein for each one of the second sub source lines, one of the second select transistors and one of the fourth select transistors are connected between the one second sub source line and the second source line; a plurality of select transistor lines each connected to a gate of one of the first select transistors and a gate of one of the second select transistors.