A semiconductor package comprising: a semiconductor chip; an external connection member on the semiconductor chip; and a dielectric film between the semiconductor chip and the external connection member, wherein the semiconductor chip includes: a substrate; a front-end-of-line structure (FEOL) on the substrate; and a back-end-of-line structure (BEOL) on the front-end-of-line structure, wherein the back-end-of-line structure includes: a plurality of metal layers stacked on the front-end-of-line structure, an uppermost metal layer (Mt) of the metal layers including a pad therein; a first dielectric layer on the uppermost metal layer, the first dielectric layer including a contact hole that vertically overlaps the pad; a redistribution line on the first dielectric layer, the redistribution line including a contact part (CNTP) in the contact hole and electrically connected to the pad, a pad part (PADP), and a line part (LINP) that electrically connects the contact part to the pad part; and an upper dielectric layer on the redistribution line, wherein the upper dielectric layer includes: a first opening that vertically overlaps the contact part; and a second opening that vertically overlaps the pad part, wherein the external connection member includes an under-bump pattern electrically connected through the second opening to the pad part, wherein the contact part includes a dent in an upper portion thereof, wherein the first opening vertically overlaps the dent, wherein the dielectric film is on the upper dielectric layer of the back-end-of-line structure (BEOL) and includes a dielectric film recess in a top surface of the dielectric film, and wherein the dielectric film recess vertically overlaps the dent; characterized in that a lower portion of the under-bump pattern includes a first sidewall and a second sidewall that are opposite to each other, the lower portion of the under-bump pattern being in the second opening, wherein the first sidewall is in contact with a sidewall of the upper dielectric layer, and wherein the second sidewall is spaced apart from the upper dielectric layer by the dielectric film. a semiconductor chip; an external connection member on the semiconductor chip; and a dielectric film between the semiconductor chip and the external connection member, wherein the semiconductor chip includes: a substrate; a front-end-of-line structure (FEOL) on the substrate; and a back-end-of-line structure (BEOL) on the front-end-of-line structure, a substrate; a front-end-of-line structure (FEOL) on the substrate; and a back-end-of-line structure (BEOL) on the front-end-of-line structure, wherein the back-end-of-line structure includes: a plurality of metal layers stacked on the front-end-of-line structure, an uppermost metal layer (Mt) of the metal layers including a pad therein; a first dielectric layer on the uppermost metal layer, the first dielectric layer including a contact hole that vertically overlaps the pad; a redistribution line on the first dielectric layer, the redistribution line including a contact part (CNTP) in the contact hole and electrically connected to the pad, a pad part (PADP), and a line part (LINP) that electrically connects the contact part to the pad part; and an upper dielectric layer on the redistribution line, a plurality of metal layers stacked on the front-end-of-line structure, an uppermost metal layer (Mt) of the metal layers including a pad therein; a first dielectric layer on the uppermost metal layer, the first dielectric layer including a contact hole that vertically overlaps the pad; a redistribution line on the first dielectric layer, the redistribution line including a contact part (CNTP) in the contact hole and electrically connected to the pad, a pad part (PADP), and a line part (LINP) that electrically connects the contact part to the pad part; and an upper dielectric layer on the redistribution line, wherein the upper dielectric layer includes: a first opening that vertically overlaps the contact part; and a second opening that vertically overlaps the pad part, a first opening that vertically overlaps the contact part; and a second opening that vertically overlaps the pad part, wherein the external connection member includes an under-bump pattern electrically connected through the second opening to the pad part, wherein the contact part includes a dent in an upper portion thereof, wherein the first opening vertically overlaps the dent, wherein the dielectric film is on the upper dielectric layer of the back-end-of-line structure (BEOL) and includes a dielectric film recess in a top surface of the dielectric film, and wherein the dielectric film recess vertically overlaps the dent; characterized in that a lower portion of the under-bump pattern includes a first sidewall and a second sidewall that are opposite to each other, the lower portion of the under-bump pattern being in the second opening, wherein the first sidewall is in contact with a sidewall of the upper dielectric layer, and wherein the second sidewall is spaced apart from the upper dielectric layer by the dielectric film.