A memory structure, comprising: a semiconductor substrate having a substantially planar surface and including circuitry formed therein for supporting a memory circuit; a plurality of active columns (430L, 430R) of semiconducting material formed above the semiconductor substrate, each active column extending along a first direction orthogonal to the planar surface of semiconductor substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped regions, wherein the first and second heavily doped regions extend vertically and respectively form a vertical bit line and source line, further wherein the active columns are arranged in a two-dimensional array having rows of the active columns extending along a second direction and rows of active columns extending along a third direction, the second direction and the third direction each being parallel to the planar surface of the semiconductor substrate; charge-trapping material provided over one or more surfaces of each active columns; and a plurality of stacks of conductors (WL 0 -WL 31), with each stack of conductors being provided between two rows of the active columns that extend lengthwise along the third direction, such that each active column, the charge-trapping material and each stack of conductors together form a plurality of variable-threshold thin film transistors (416L, 416R) provided along the first direction, each variable-threshold thin film transistor comprising (i) an associated one of the conductors in the stack of conductors, providing a word line and serving as a gate terminal of the variable-threshold thin film transistor; (ii) a portion of the lightly doped region of the active column, serving as a channel of the variable-threshold thin film transistor; (iii) the charge-trapping material between the portion of the lightly doped region and the associated conductor; and (iv) the first and second heavily doped regions of the active column, respectively providing a bit line and a source line, and respectively serving as a drain and a source terminals of the variable-threshold thin film transistor. a semiconductor substrate having a substantially planar surface and including circuitry formed therein for supporting a memory circuit; a plurality of active columns (430L, 430R) of semiconducting material formed above the semiconductor substrate, each active column extending along a first direction orthogonal to the planar surface of semiconductor substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped regions, wherein the first and second heavily doped regions extend vertically and respectively form a vertical bit line and source line, further wherein the active columns are arranged in a two-dimensional array having rows of the active columns extending along a second direction and rows of active columns extending along a third direction, the second direction and the third direction each being parallel to the planar surface of the semiconductor substrate; charge-trapping material provided over one or more surfaces of each active columns; and a plurality of stacks of conductors (WL 0 -WL 31), with each stack of conductors being provided between two rows of the active columns that extend lengthwise along the third direction, such that each active column, the charge-trapping material and each stack of conductors together form a plurality of variable-threshold thin film transistors (416L, 416R) provided along the first direction, each variable-threshold thin film transistor comprising (i) an associated one of the conductors in the stack of conductors, providing a word line and serving as a gate terminal of the variable-threshold thin film transistor; (ii) a portion of the lightly doped region of the active column, serving as a channel of the variable-threshold thin film transistor; (iii) the charge-trapping material between the portion of the lightly doped region and the associated conductor; and (iv) the first and second heavily doped regions of the active column, respectively providing a bit line and a source line, and respectively serving as a drain and a source terminals of the variable-threshold thin film transistor.