A display device, comprising: a plurality of subpixels, each comprising a thin-film transistor, the thin film-transistor comprising: an active layer comprising a p+ or n+ doped source region, a p+ or n+ doped drain region, and a first channel region and a second channel region disposed in this order between the p+ or n+ doped source region and p+ or n+ doped the drain region and separated from each other by a connection pattern as a conducting region; a first gate electrode disposed on an area of one surface of the active layer; a second gate electrode disposed on an area of the other surface of the active layer so as to correspond to the first channel region; and a third gate electrode disposed on an area of the other surface of the active layer so as to correspond to the second channel region, wherein the first gate electrode is located under the active layer, and the second gate electrode and the third gate electrode are located over the active layer, wherein the display device is configured to apply a first gate voltage to the first gate electrode, to apply a back bias voltage (Bbias) to the second gate electrode, and to apply a second gate voltage to the third gate electrode, characterized in that the back bias voltage (Bbias) is a constant voltage, wherein an absolute value of the back bias voltage (Bbias) is lower than an absolute value of the first gate voltage and an absolute value of the second gate voltage, and one of both boundaries of the first gate electrode adjacent to the p+ or n+ doped drain region is located inwardly from a boundary between the p+ or n+ doped drain region and the second channel region and the second channel region extends beyond the one boundary of the first gate electrode so as to have a portion adjacent to the p+ or n+ doped drain region that does not overlap with the first gate electrode. an active layer comprising a p+ or n+ doped source region, a p+ or n+ doped drain region, and a first channel region and a second channel region disposed in this order between the p+ or n+ doped source region and p+ or n+ doped the drain region and separated from each other by a connection pattern as a conducting region; a first gate electrode disposed on an area of one surface of the active layer; a second gate electrode disposed on an area of the other surface of the active layer so as to correspond to the first channel region; and a third gate electrode disposed on an area of the other surface of the active layer so as to correspond to the second channel region, wherein the first gate electrode is located under the active layer, and the second gate electrode and the third gate electrode are located over the active layer, wherein the display device is configured to apply a first gate voltage to the first gate electrode, to apply a back bias voltage (Bbias) to the second gate electrode, and to apply a second gate voltage to the third gate electrode, characterized in that the back bias voltage (Bbias) is a constant voltage, wherein an absolute value of the back bias voltage (Bbias) is lower than an absolute value of the first gate voltage and an absolute value of the second gate voltage, and one of both boundaries of the first gate electrode adjacent to the p+ or n+ doped drain region is located inwardly from a boundary between the p+ or n+ doped drain region and the second channel region and the second channel region extends beyond the one boundary of the first gate electrode so as to have a portion adjacent to the p+ or n+ doped drain region that does not overlap with the first gate electrode.