A processing system comprising: - a bus system; - a processing unit connected to said bus system; - a non-volatile memory configured to store at least one firmware (BL, FW) to be executed by said processing unit; - a co-processor connected to said bus system, wherein said co-processor comprises a register interface comprising a plurality of registers (REG0..REGn) and a processing circuit configured to perform at least one processing operation as a function of data stored in said plurality of registers (REG0..REGn), wherein said plurality of registers (REG0..REGn) comprise a first set of registers configured to store a first set of configuration information and a second set of registers configured to store a second set of configuration information; wherein said register interface comprises: - a bus interface configured to monitor write requests transmitted via said bus system to said register interface, wherein said write requests comprise a target address and data to be written (W_DATA), wherein with each register of said plurality of registers (REG0..REGn) is associated a respective address, wherein said bus interface is configured to set for each register of said plurality of registers (REG0..REGn) a respective register selection signal (WR_REG0..WR_REGn) when the target address of a write request corresponds to the address associated with the respective register, wherein each register is configured to store said data to be written (W_DATA) when the respective register selection signal (WR_REG0..WR_REGn) is set; and - a cyclic redundancy check calculation circuit configured to compute a cyclic redundancy check value (CRC_INT) at least as a function of the data to be written (W_DATA) to said first set of registers; characterized in that said register interface comprises a masking circuit configured to: - monitor said register selection signals (WR_REG0..WR_REGn) associated with the registers of said first set of registers in order to determine the sequence of registers to which data has been stored; - compare said sequence of registers with a reference sequence (REF_SEQ); - when said comparison indicates that said sequence of registers corresponds to said reference sequence (REF_SEQ), providing said computed cyclic redundancy check value (CRC_INT) to said bus interface; and - when said comparison indicates that said sequence of registers does not correspond to said reference sequence, providing a value being independent from said computed cyclic redundancy check value (CRC_INT) to said bus interface. - a bus system; - a processing unit connected to said bus system; - a non-volatile memory configured to store at least one firmware (BL, FW) to be executed by said processing unit; - a co-processor connected to said bus system, wherein said co-processor comprises a register interface comprising a plurality of registers (REG0..REGn) and a processing circuit configured to perform at least one processing operation as a function of data stored in said plurality of registers (REG0..REGn), wherein said plurality of registers (REG0..REGn) comprise a first set of registers configured to store a first set of configuration information and a second set of registers configured to store a second set of configuration information; - a bus interface configured to monitor write requests transmitted via said bus system to said register interface, wherein said write requests comprise a target address and data to be written (W_DATA), wherein with each register of said plurality of registers (REG0..REGn) is associated a respective address, wherein said bus interface is configured to set for each register of said plurality of registers (REG0..REGn) a respective register selection signal (WR_REG0..WR_REGn) when the target address of a write request corresponds to the address associated with the respective register, wherein each register is configured to store said data to be written (W_DATA) when the respective register selection signal (WR_REG0..WR_REGn) is set; and - a cyclic redundancy check calculation circuit configured to compute a cyclic redundancy check value (CRC_INT) at least as a function of the data to be written (W_DATA) to said first set of registers; - monitor said register selection signals (WR_REG0..WR_REGn) associated with the registers of said first set of registers in order to determine the sequence of registers to which data has been stored; - compare said sequence of registers with a reference sequence (REF_SEQ); - when said comparison indicates that said sequence of registers corresponds to said reference sequence (REF_SEQ), providing said computed cyclic redundancy check value (CRC_INT) to said bus interface; and - when said comparison indicates that said sequence of registers does not correspond to said reference sequence, providing a value being independent from said computed cyclic redundancy check value (CRC_INT) to said bus interface.