A circuit having a frequency band of interest, the circuit including a current mirror circuit, the current mirror circuit comprising: a first bias transistor having a source connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor; a current source connected to the drain and the gate of the first bias transistor, the current source being configured to generate a predetermined first output current; a sample and hold circuit having an input connected to the gate of the first bias transistor and including a switch having an input terminal and an output terminal, the input terminal being operatively connected to the gate of the first bias transistor; and a capacitor operatively connected to the output terminal of the switch and the voltage source, the output terminal of the switch being connected to the gate of a second transistor; the second transistor having a source connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit; and a controller operatively connected to the sample and hold circuit, the controller being configured to operate the sample and hold circuit at a predetermined sampling frequency and duty ratio to attenuate bias noise from the first bias transistor in a second output current from the drain of the second transistor; wherein the switch is a switch transistor and the controller is a clock signal generator that generates clock signal pulses (172A, 172B) at the predetermined frequency and duty cycle to open and close the switch transistor with the clock signal pulses at the predetermined frequency and duty ratio so as to charge the capacitor to the same voltage level as the gate of the first bias transistor when the switch is closed and for keeping the switch open during the remainder of each clock cycle, the clock signal pulses (172A, 172B) being sufficiently long that the capacitor retains the charged voltages level during the remainder of eac h duty cycle; and wherein the sample and hold circuit is configured as an ideal sampler followed by a zero-order hold circuit operating with a sine transfer function so as to produce notches in the frequency response where the bias noise is attenuated in and around the predetermined sampling frequency where the bias transistor noise is attenuated in and around the sampling frequency and harmonics thereof while the bias noise increases at different frequencies due to aliasing in the sample and hold circuit due to its sampling frequency; characterized in that the predetermined sampling frequency is selected to be the same as the frequency band of interest. a first bias transistor having a source connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor; a current source connected to the drain and the gate of the first bias transistor, the current source being configured to generate a predetermined first output current; a sample and hold circuit having an input connected to the gate of the first bias transistor and including a switch having an input terminal and an output terminal, the input terminal being operatively connected to the gate of the first bias transistor; and a capacitor operatively connected to the output terminal of the switch and the voltage source, the output terminal of the switch being connected to the gate of a second transistor; the second transistor having a source connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit; and a controller operatively connected to the sample and hold circuit, the controller being configured to operate the sample and hold circuit at a predetermined sampling frequency and duty ratio to attenuate bias noise from the first bias transistor in a second output current from the drain of the second transistor; wherein the switch is a switch transistor and the controller is a clock signal generator that generates clock signal pulses (172A, 172B) at the predetermined frequency and duty cycle to open and close the switch transistor with the clock signal pulses at the predetermined frequency and duty ratio so as to charge the capacitor to the same voltage level as the gate of the first bias transistor when the switch is closed and for keeping the switch open during the remainder of each clock cycle, the clock signal pulses (172A, 172B) being sufficiently long that the capacitor retains the charged voltages level during the remainder of eac h duty cycle; and wherein the sample and hold circuit is configured as an ideal sampler followed by a zero-order hold circuit operating with a sine transfer function so as to produce notches in the frequency response where the bias noise is attenuated in and around the predetermined sampling frequency where the bias transistor noise is attenuated in and around the sampling frequency and harmonics thereof while the bias noise increases at different frequencies due to aliasing in the sample and hold circuit due to its sampling frequency; characterized in that the predetermined sampling frequency is selected to be the same as the frequency band of interest.