An equalizer circuit, comprising a dual reference voltage generator, a first input buffer circuit, a second input buffer circuit and a selecting and sampling circuit, wherein two different reference voltages output by the dual reference voltage generator serve as input reference voltages of the first input buffer circuit and the second input buffer circuit, respectively; the first input buffer circuit and the second input buffer circuit are respectively connected to the selecting and sampling circuit; the selecting and sampling circuit is configured to select, according to data previously output by the equalizer circuit, whether to perform data sampling on a data signal output by the first input buffer circuit or a data signal output by the second input buffer circuit, and take sampled data as data currently output by the equalizer circuit; and the dual reference voltage generator is configured to receive an original code, a first code and a second code, generates a first reference voltage according to received original code and first code, and generate a second reference voltage according to received original code and second code, the first reference voltage being different from the second reference voltage, characterized in that, the dual reference voltage generator comprises: a first processing circuit, a second processing circuit, a first selector, a second selector, a first output buffer circuit, a second output buffer circuit and a voltage divider circuit, wherein two input terminals of the first processing circuit are configured to respectively receive the first code and the original code, and an output terminal of the first processing circuit is connected to a control terminal of the first selector; two input terminals of the second processing circuit are configured to respectively receive the second code and the original code, and an output terminal of the second processing circuit is connected to a control terminal of the second selector; one or more output terminals of the voltage divider circuit are respectively connected to one or more input terminals of the first selector and one or more input terminals of the second selector; and an output terminal of the first selector is connected to an input terminal of the first output buffer circuit, an output terminal of the second selector is connected to an input terminal of the second output buffer circuit, the first reference voltage is output from an output terminal of the first output buffer circuit, and the second reference voltage is output from an output terminal of the second output buffer circuit. wherein two different reference voltages output by the dual reference voltage generator serve as input reference voltages of the first input buffer circuit and the second input buffer circuit, respectively; the first input buffer circuit and the second input buffer circuit are respectively connected to the selecting and sampling circuit; the selecting and sampling circuit is configured to select, according to data previously output by the equalizer circuit, whether to perform data sampling on a data signal output by the first input buffer circuit or a data signal output by the second input buffer circuit, and take sampled data as data currently output by the equalizer circuit; and the dual reference voltage generator is configured to receive an original code, a first code and a second code, generates a first reference voltage according to received original code and first code, and generate a second reference voltage according to received original code and second code, the first reference voltage being different from the second reference voltage, characterized in that, the dual reference voltage generator comprises: a first processing circuit, a second processing circuit, a first selector, a second selector, a first output buffer circuit, a second output buffer circuit and a voltage divider circuit, wherein two input terminals of the first processing circuit are configured to respectively receive the first code and the original code, and an output terminal of the first processing circuit is connected to a control terminal of the first selector; two input terminals of the second processing circuit are configured to respectively receive the second code and the original code, and an output terminal of the second processing circuit is connected to a control terminal of the second selector; one or more output terminals of the voltage divider circuit are respectively connected to one or more input terminals of the first selector and one or more input terminals of the second selector; and an output terminal of the first selector is connected to an input terminal of the first output buffer circuit, an output terminal of the second selector is connected to an input terminal of the second output buffer circuit, the first reference voltage is output from an output terminal of the first output buffer circuit, and the second reference voltage is output from an output terminal of the second output buffer circuit.