A computing device comprising: a plurality of vector processors, wherein one of the plurality of vector processors is configured to execute an instruction that operates on a first array of values; a hardware accelerator configured to perform a filtering operation on a second array of values; a memory fabric comprising a plurality of memory slices and an interconnect system having a first interface and a second interface, wherein the first interface is configured to couple the plurality of vector processors to the plurality of memory slices and wherein the second interface is configured to couple the hardware accelerator to the plurality of memory slices; and a host processor configured to cause the memory fabric to provide the first array of values to the one of the plurality of vector processors via the first interface and to provide the second array of values to the hardware accelerator via the second interface, thereby enabling the one of the plurality of vector processors to process the first array of values in accordance with the instruction and enabling the hardware accelerator to process the second array of values in accordance with the filtering operation; and a peripheral device coupled to a plurality of input / output (I/O) pins, wherein the peripheral device is configured to provide a communication channel between at least one of the plurality of vector processors and an external device, wherein the peripheral device comprises an emulation module that is configured to cause the peripheral device to emulate a functionality of a plurality of standard protocol interfaces via a common set of the I/O pins. a plurality of vector processors, wherein one of the plurality of vector processors is configured to execute an instruction that operates on a first array of values; a hardware accelerator configured to perform a filtering operation on a second array of values; a memory fabric comprising a plurality of memory slices and an interconnect system having a first interface and a second interface, wherein the first interface is configured to couple the plurality of vector processors to the plurality of memory slices and wherein the second interface is configured to couple the hardware accelerator to the plurality of memory slices; and a host processor configured to cause the memory fabric to provide the first array of values to the one of the plurality of vector processors via the first interface and to provide the second array of values to the hardware accelerator via the second interface, thereby enabling the one of the plurality of vector processors to process the first array of values in accordance with the instruction and enabling the hardware accelerator to process the second array of values in accordance with the filtering operation; and a peripheral device coupled to a plurality of input / output (I/O) pins, wherein the peripheral device is configured to provide a communication channel between at least one of the plurality of vector processors and an external device, wherein the peripheral device comprises an emulation module that is configured to cause the peripheral device to emulate a functionality of a plurality of standard protocol interfaces via a common set of the I/O pins.