A non-volatile memory cell, comprising: a MOS capacitor coupling device comprising: a first terminal configured to receive a control line signal; and a second terminal; a read floating gate transistor comprising: a first terminal; a control terminal coupled to the second terminal of the coupling device; and a second terminal; a first read selection transistor comprising: a first terminal coupled to the second terminal of the read transistor; a control terminal configured to receive a word line signal; and a second terminal configured to receive a bit line signal; a second read selection transistor comprising: a first terminal configured to receive a read source line signal; a control terminal configured to receive a read select gate signal; and a second terminal coupled to the first terminal of the read transistor; a MOS capacitor erase device comprising: a first terminal configured to receive an erase line signal; and a second terminal coupled to the second terminal of the coupling device; a program floating gate transistor comprising: a first terminal; and a control terminal coupled to the second terminal of the coupling device; and a program selection transistor comprising: a first terminal configured to receive a program source line signal; a control terminal configured to receive a program select gate signal wherein during a program inhibition operation of the non-volatile memory cell, the program selection transistor is turned OFF; and a second terminal coupled to the first terminal of the program transistor; wherein the second terminal of the MOS capacitor coupling device, the control terminal of the read floating gate transistor, the control terminal of the program floating gate transistor, and the second terminal of the MOS capacitor erase device are coupled to a common floating gate. a MOS capacitor coupling device comprising: a first terminal configured to receive a control line signal; and a second terminal; a first terminal configured to receive a control line signal; and a second terminal; a read floating gate transistor comprising: a first terminal; a control terminal coupled to the second terminal of the coupling device; and a second terminal; a first terminal; a control terminal coupled to the second terminal of the coupling device; and a second terminal; a first read selection transistor comprising: a first terminal coupled to the second terminal of the read transistor; a control terminal configured to receive a word line signal; and a second terminal configured to receive a bit line signal; a first terminal coupled to the second terminal of the read transistor; a control terminal configured to receive a word line signal; and a second terminal configured to receive a bit line signal; a second read selection transistor comprising: a first terminal configured to receive a read source line signal; a control terminal configured to receive a read select gate signal; and a second terminal coupled to the first terminal of the read transistor; a first terminal configured to receive a read source line signal; a control terminal configured to receive a read select gate signal; and a second terminal coupled to the first terminal of the read transistor; a MOS capacitor erase device comprising: a first terminal configured to receive an erase line signal; and a second terminal coupled to the second terminal of the coupling device; a first terminal configured to receive an erase line signal; and a second terminal coupled to the second terminal of the coupling device; a program floating gate transistor comprising: a first terminal; and a control terminal coupled to the second terminal of the coupling device; and a first terminal; and a control terminal coupled to the second terminal of the coupling device; and a program selection transistor comprising: a first terminal configured to receive a program source line signal; a control terminal configured to receive a program select gate signal wherein during a program inhibition operation of the non-volatile memory cell, the program selection transistor is turned OFF; and a second terminal coupled to the first terminal of the program transistor; a first terminal configured to receive a program source line signal; a control terminal configured to receive a program select gate signal wherein during a program inhibition operation of the non-volatile memory cell, the program selection transistor is turned OFF; and a second terminal coupled to the first terminal of the program transistor; wherein the second terminal of the MOS capacitor coupling device, the control terminal of the read floating gate transistor, the control terminal of the program floating gate transistor, and the second terminal of the MOS capacitor erase device are coupled to a common floating gate.