A device that evaluates similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the device adapted to detect use of untested cells, obsolete cells, or changes to cells and comprising: [a] at least one processor and memory; [b] a parser running on the processor, that parses a first file and a second file that contain design data representing aspects of a design for a physical circuit and creates one or more syntax trees in the memory for each of the first file and the second file; [c] normalizer logic running on the processor and cooperating with the parser that organizes the syntax trees to produce canonical forms, wherein the normalizer logic includes: a partitioning module that partitions each of the first file and the second file into at least one header and, depending on rules of a design language used to encode the respective file, into multiple cells of design data and organizes the syntax trees to represent the header and cell partitions, wherein the header includes global information about a file and the cell partitions contain cell views being functional, physical and/or electrical representations of individual design units of the physical circuit; and a canonical forming module that interprets the syntax trees to produce canonical forms of the design data by normalizing the design data by one or more of merging and re-fracturing polygons within a cell, semantic analysis of the syntax tree, eliminating whitespace, segregating comments from program code, sorting tokens or the branches of the syntax tree, classifying tokens or branches of the syntax tree as functional or nonfunctional design data, dividing data within the cell partition between cell header and cell body data, and/or reordering corner points of a polygon; [d] a digester module running on the processor that receives the canonical forms for at least selected partitions, calculates at least one digest per selected partition from the canonical forms using a hash function that returns a bit code and stores the digests in the memory; [e] a comparer module running on the processor that receives and compares the bit codes of the digests of the first file and the second file; and [f] a reporter module running on the processor and coupled to the comparer that summarizes at least some results of comparing the digests. [a] at least one processor and memory; [b] a parser running on the processor, that parses a first file and a second file that contain design data representing aspects of a design for a physical circuit and creates one or more syntax trees in the memory for each of the first file and the second file; [c] normalizer logic running on the processor and cooperating with the parser that organizes the syntax trees to produce canonical forms, wherein the normalizer logic includes: a partitioning module that partitions each of the first file and the second file into at least one header and, depending on rules of a design language used to encode the respective file, into multiple cells of design data and organizes the syntax trees to represent the header and cell partitions, wherein the header includes global information about a file and the cell partitions contain cell views being functional, physical and/or electrical representations of individual design units of the physical circuit; and a canonical forming module that interprets the syntax trees to produce canonical forms of the design data by normalizing the design data by one or more of merging and re-fracturing polygons within a cell, semantic analysis of the syntax tree, eliminating whitespace, segregating comments from program code, sorting tokens or the branches of the syntax tree, classifying tokens or branches of the syntax tree as functional or nonfunctional design data, dividing data within the cell partition between cell header and cell body data, and/or reordering corner points of a polygon; a partitioning module that partitions each of the first file and the second file into at least one header and, depending on rules of a design language used to encode the respective file, into multiple cells of design data and organizes the syntax trees to represent the header and cell partitions, wherein the header includes global information about a file and the cell partitions contain cell views being functional, physical and/or electrical representations of individual design units of the physical circuit; and a canonical forming module that interprets the syntax trees to produce canonical forms of the design data by normalizing the design data by one or more of merging and re-fracturing polygons within a cell, semantic analysis of the syntax tree, eliminating whitespace, segregating comments from program code, sorting tokens or the branches of the syntax tree, classifying tokens or branches of the syntax tree as functional or nonfunctional design data, dividing data within the cell partition between cell header and cell body data, and/or reordering corner points of a polygon; [d] a digester module running on the processor that receives the canonical forms for at least selected partitions, calculates at least one digest per selected partition from the canonical forms using a hash function that returns a bit code and stores the digests in the memory; [e] a comparer module running on the processor that receives and compares the bit codes of the digests of the first file and the second file; and [f] a reporter module running on the processor and coupled to the comparer that summarizes at least some results of comparing the digests.