A phase-detector circuit, comprising: a plurality of phase comparators (PD_A, PD_B, PD_C, and PD_D) which detects a phase difference between received data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase, wherein the phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-difference time and a predetermined delay time; characterised in that the phase-detector circuit further comprises: a reset-signal generator which receives a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates a reset signal having a predetermined phase difference angle according to each clock signal; and a plurality of OR circuits (12 to 15) in which each of a logical addition of the signal for the up signal output from the predetermined phase comparator and the signal for the up signal output from another predetermined phase comparator is generated as one of a plurality of up signals, wherein the plurality of phase comparators (PD_A, PD_B, PD_C, and PD_D) comprises a plurality of flip-flops (FF11A-FF15A) configured to receive received data, a predetermined clock signal, and a reset signal to generate signals for an up/down signal for a phase synchronization; and each of the phase comparators (PD_A, PD_B, PD_C, and PD_D) generates the up signal so as to have a pulse width including a time difference between a transition edge of the received data and a falling edge of the reset signal, and when the up signal has such a pulse width, the phase comparator (PD_A, PD_B, PD_C, and PD_D) generates the down signal so as to have a pulse width including a time difference between a rising edge of the received data and the falling edge of the reset signal. a plurality of phase comparators (PD_A, PD_B, PD_C, and PD_D) which detects a phase difference between received data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase, wherein the phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-difference time and a predetermined delay time; characterised in that the phase-detector circuit further comprises: a reset-signal generator which receives a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates a reset signal having a predetermined phase difference angle according to each clock signal; and a plurality of OR circuits (12 to 15) in which each of a logical addition of the signal for the up signal output from the predetermined phase comparator and the signal for the up signal output from another predetermined phase comparator is generated as one of a plurality of up signals, wherein the plurality of phase comparators (PD_A, PD_B, PD_C, and PD_D) comprises a plurality of flip-flops (FF11A-FF15A) configured to receive received data, a predetermined clock signal, and a reset signal to generate signals for an up/down signal for a phase synchronization; and each of the phase comparators (PD_A, PD_B, PD_C, and PD_D) generates the up signal so as to have a pulse width including a time difference between a transition edge of the received data and a falling edge of the reset signal, and when the up signal has such a pulse width, the phase comparator (PD_A, PD_B, PD_C, and PD_D) generates the down signal so as to have a pulse width including a time difference between a rising edge of the received data and the falling edge of the reset signal. a reset-signal generator which receives a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates a reset signal having a predetermined phase difference angle according to each clock signal; and a plurality of OR circuits (12 to 15) in which each of a logical addition of the signal for the up signal output from the predetermined phase comparator and the signal for the up signal output from another predetermined phase comparator is generated as one of a plurality of up signals, wherein the plurality of phase comparators (PD_A, PD_B, PD_C, and PD_D) comprises a plurality of flip-flops (FF11A-FF15A) configured to receive received data, a predetermined clock signal, and a reset signal to generate signals for an up/down signal for a phase synchronization; and each of the phase comparators (PD_A, PD_B, PD_C, and PD_D) generates the up signal so as to have a pulse width including a time difference between a transition edge of the received data and a falling edge of the reset signal, and when the up signal has such a pulse width, the phase comparator (PD_A, PD_B, PD_C, and PD_D) generates the down signal so as to have a pulse width including a time difference between a rising edge of the received data and the falling edge of the reset signal.