A method of estimating frequency synchronization accuracy between a first clock in a slave device and a second clock in a master device, the devices being connected over a network, the method including the steps of: receiving, at the slave device, timing messages sent at a regular interval from the master device, the timing messages having timestamps from the second clock; deriving, in the slave device, using said timing messages, a corrected clock which is an adjusted version of the first clock and which is synchronized to the second clock; estimating the average progression of the corrected clock for each interval between sending of said timing messages over a plurality of said intervals; and estimating the synchronisation accuracy from the ratio of the interval to the average progression of the corrected clock; wherein the synchronization accuracy is estimated as A cc = Δ ⁢ T Δ R n ̅ − 1, wherein A cc is the accuracy, Δ T is the interval, and Δ R n is the average progression of the corrected clock at time n, and wherein the corrected clock is derived using a digital phase-locked loop by: initializing a counter on arrival of the first of said timing messages in the slave device; and repeatedly: incrementing the counter with the output of a phase accumulator driven by an oscillator in the slave device; comparing the phase of the timestamps in the timing messages arriving at the slave device with the value of the counter to calculate an error signal; filtering the error signal to produce a control signal; and controlling the frequency of the phase accumulator using said control signal to synchronise the frequency of the output of the phase accumulator with the frequency of the second clock. receiving, at the slave device, timing messages sent at a regular interval from the master device, the timing messages having timestamps from the second clock; deriving, in the slave device, using said timing messages, a corrected clock which is an adjusted version of the first clock and which is synchronized to the second clock; estimating the average progression of the corrected clock for each interval between sending of said timing messages over a plurality of said intervals; and estimating the synchronisation accuracy from the ratio of the interval to the average progression of the corrected clock; wherein the synchronization accuracy is estimated as A cc = Δ ⁢ T Δ R n ̅ − 1, wherein A cc is the accuracy, Δ T is the interval, and Δ R n is the average progression of the corrected clock at time n, and wherein the corrected clock is derived using a digital phase-locked loop by: initializing a counter on arrival of the first of said timing messages in the slave device; and repeatedly: incrementing the counter with the output of a phase accumulator driven by an oscillator in the slave device; comparing the phase of the timestamps in the timing messages arriving at the slave device with the value of the counter to calculate an error signal; filtering the error signal to produce a control signal; and controlling the frequency of the phase accumulator using said control signal to synchronise the frequency of the output of the phase accumulator with the frequency of the second clock. initializing a counter on arrival of the first of said timing messages in the slave device; and repeatedly: incrementing the counter with the output of a phase accumulator driven by an oscillator in the slave device; comparing the phase of the timestamps in the timing messages arriving at the slave device with the value of the counter to calculate an error signal; filtering the error signal to produce a control signal; and controlling the frequency of the phase accumulator using said control signal to synchronise the frequency of the output of the phase accumulator with the frequency of the second clock. incrementing the counter with the output of a phase accumulator driven by an oscillator in the slave device; comparing the phase of the timestamps in the timing messages arriving at the slave device with the value of the counter to calculate an error signal; filtering the error signal to produce a control signal; and controlling the frequency of the phase accumulator using said control signal to synchronise the frequency of the output of the phase accumulator with the frequency of the second clock.