A method for comparing data patterns, comprising: performing, by a controller using a primary latch and a secondary latch (408-1, 408-2, 409-1, and 409-2), a particular number of operations, wherein the particular number of operations includes logical operations and wherein the particular number of operations is based on a number of data units of a target data pattern to: compare, in a sensing circuitry (150, 750, 950) comprising a sense amplifier (206, 406, 606, 706, 906) and a compute component (231, 331, 431, 731, 931) coupled to the sense line (205, 305, 405, 605, 705, 905), wherein the sense amplifier comprises the primary latch and the compute component comprises the secondary latch: a first data unit of the target data pattern to a first data unit of a stored data pattern, the first data unit of the target data pattern having a first data value, and wherein the first data unit of the stored data pattern and the first data unit of the target data pattern have a same data unit position, wherein the first data units of the target data pattern and the stored data pattern are compared by: storing the first data value in the compute component (231, 331, 431, 731, 931); and logically ORing a data value of the first data unit of the stored data pattern with the first data value stored in the compute component (231, 331, 431, 731, 931) and store a result of the logical OR operation in the compute component (231, 331, 431, 731, 931); a second data unit of the target data pattern to a second data unit of the stored data pattern, the second data unit of the target data pattern having a second data value, and wherein the second data unit of the stored data pattern and the second data unit of the target data pattern have a same data unit position, wherein the second data units of the target data pattern and the stored data pattern are compared by: inverting the result of the logical OR operation stored in the compute component (231, 331, 431, 731, 931); and logically ANDing the inverted result of the logical OR operation with a data value of the second data unit of the stored data pattern and store a result of the logical AND operation in the compute component (231, 331, 431, 731, 931); and determining, by the controller using the primary latch and the secondary latch, whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array (130, 201, 301, 430, 730) via an input/output (I/O) line (234, 634). a first data unit of the target data pattern to a first data unit of a stored data pattern, the first data unit of the target data pattern having a first data value, and wherein the first data unit of the stored data pattern and the first data unit of the target data pattern have a same data unit position, wherein the first data units of the target data pattern and the stored data pattern are compared by: storing the first data value in the compute component (231, 331, 431, 731, 931); and logically ORing a data value of the first data unit of the stored data pattern with the first data value stored in the compute component (231, 331, 431, 731, 931) and store a result of the logical OR operation in the compute component (231, 331, 431, 731, 931); storing the first data value in the compute component (231, 331, 431, 731, 931); and logically ORing a data value of the first data unit of the stored data pattern with the first data value stored in the compute component (231, 331, 431, 731, 931) and store a result of the logical OR operation in the compute component (231, 331, 431, 731, 931); a second data unit of the target data pattern to a second data unit of the stored data pattern, the second data unit of the target data pattern having a second data value, and wherein the second data unit of the stored data pattern and the second data unit of the target data pattern have a same data unit position, wherein the second data units of the target data pattern and the stored data pattern are compared by: inverting the result of the logical OR operation stored in the compute component (231, 331, 431, 731, 931); and logically ANDing the inverted result of the logical OR operation with a data value of the second data unit of the stored data pattern and store a result of the logical AND operation in the compute component (231, 331, 431, 731, 931); and inverting the result of the logical OR operation stored in the compute component (231, 331, 431, 731, 931); and logically ANDing the inverted result of the logical OR operation with a data value of the second data unit of the stored data pattern and store a result of the logical AND operation in the compute component (231, 331, 431, 731, 931); and determining, by the controller using the primary latch and the secondary latch, whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array (130, 201, 301, 430, 730) via an input/output (I/O) line (234, 634).