A solid-state imaging apparatus comprising (a) a pixel region including a plurality of pixels arranged in a matrix including a plurality of columns of the pixels, wherein each pixel performs photoelectric conversion and outputs an analog signal, (b) a plurality of analog-to-digital converters, wherein each analog-to-digital converter converts the analog signal output by one of the pixels included in one of the columns of the pixels into a digital signal, and each analog-to-digitalconverter is provided in correspondence to a different one of the columns of the pixels, (c) a plurality of digital memories arranged in a plurality of blocks of two or more digital memories, wherein each digital memory holds the digital signal converted by a different one of the analog-to-digital converters, and each of the two or more digital memories is provided in correspondence to a different one of the analog-to-digital converters, (d) a plurality of block digital output lines, wherein each block digital output line is coupled to a different one of the blocks of the digital memories, wherein the digital signal held in a particular digital memory is output through the corresponding block digital output line, and (e) a plurality of buffer circuits, wherein each buffer circuit buffers a digital signal from a corresponding one of the block digital output lines, characterized in that (f) the solid-state imaging apparatus further comprises a plurality of block selecting units, wherein each block selecting unit is provided in correspondence to a different one of the blocks of the digital memories, and wherein a first block selecting unit of the plurality of block selecting units is configured to selectively output a digital signal from a corresponding one of the block digital output lines, a second block selecting unit of the plurality of block selecting units is configured to selectively output the digital signal output from the first block selecting unit and a digital signal output from a corresponding one of the block digital output lines, and a third block selecting unit of the plurality of block selecting units is configured to selectively output the digital signal output from the second block selecting unit and a digital signal output from a corresponding one of the block digital output lines, and (g) each of the buffer circuits is connected between one of the plurality of block digital output lines and one of the plurality of block selecting units, or at the output of one of the plurality of block selecting units. (a) a pixel region including a plurality of pixels arranged in a matrix including a plurality of columns of the pixels, wherein each pixel performs photoelectric conversion and outputs an analog signal, (b) a plurality of analog-to-digital converters, wherein each analog-to-digital converter converts the analog signal output by one of the pixels included in one of the columns of the pixels into a digital signal, and each analog-to-digitalconverter is provided in correspondence to a different one of the columns of the pixels, (c) a plurality of digital memories arranged in a plurality of blocks of two or more digital memories, wherein each digital memory holds the digital signal converted by a different one of the analog-to-digital converters, and each of the two or more digital memories is provided in correspondence to a different one of the analog-to-digital converters, (d) a plurality of block digital output lines, wherein each block digital output line is coupled to a different one of the blocks of the digital memories, wherein the digital signal held in a particular digital memory is output through the corresponding block digital output line, and (e) a plurality of buffer circuits, wherein each buffer circuit buffers a digital signal from a corresponding one of the block digital output lines, characterized in that (f) the solid-state imaging apparatus further comprises a plurality of block selecting units, wherein each block selecting unit is provided in correspondence to a different one of the blocks of the digital memories, and wherein a first block selecting unit of the plurality of block selecting units is configured to selectively output a digital signal from a corresponding one of the block digital output lines, a second block selecting unit of the plurality of block selecting units is configured to selectively output the digital signal output from the first block selecting unit and a digital signal output from a corresponding one of the block digital output lines, and a third block selecting unit of the plurality of block selecting units is configured to selectively output the digital signal output from the second block selecting unit and a digital signal output from a corresponding one of the block digital output lines, and (g) each of the buffer circuits is connected between one of the plurality of block digital output lines and one of the plurality of block selecting units, or at the output of one of the plurality of block selecting units.