A vertical semiconductor device, comprising: a semiconductor body comprising a first surface, a second surface opposite to the first surface in a vertical direction, an edge termination region, and an active region arranged adjacent to the edge termination region in a horizontal direction; a plurality of transistor cells at least partly integrated in the active region, each transistor cell comprising a source region, a body region, a drift region separated from the source region by the body region, and a gate electrode dielectrically insulated from the body region; a first semiconductor layer of a first doping type arranged between the drift regions and the second surface in the edge termination region and in the active region; and a buffer region arranged in the first semiconductor layer and comprising a first section extending in the horizontal direction into the edge termination region, and a second section extending in the horizontal direction into the active region, wherein the second section has a width (b 62) in the horizontal direction which is at least twice the width (s 1) and less than twenty times the width (s 1) of a first pitch, wherein the buffer region either has a second doping type complementary to the first doping type, or has the first doping type and a doping concentration lower than a doping concentration of the first semiconductor layer, wherein each of the plurality of transistor cells further comprises a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in the vertical direction, and wherein the width (s 1) of a first pitch equals a distance between the central planes of two successive compensation regions. a semiconductor body comprising a first surface, a second surface opposite to the first surface in a vertical direction, an edge termination region, and an active region arranged adjacent to the edge termination region in a horizontal direction; a plurality of transistor cells at least partly integrated in the active region, each transistor cell comprising a source region, a body region, a drift region separated from the source region by the body region, and a gate electrode dielectrically insulated from the body region; a first semiconductor layer of a first doping type arranged between the drift regions and the second surface in the edge termination region and in the active region; and a buffer region arranged in the first semiconductor layer and comprising a first section extending in the horizontal direction into the edge termination region, and a second section extending in the horizontal direction into the active region, wherein the second section has a width (b 62) in the horizontal direction which is at least twice the width (s 1) and less than twenty times the width (s 1) of a first pitch, wherein the buffer region either has a second doping type complementary to the first doping type, or has the first doping type and a doping concentration lower than a doping concentration of the first semiconductor layer, wherein each of the plurality of transistor cells further comprises a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in the vertical direction, and wherein the width (s 1) of a first pitch equals a distance between the central planes of two successive compensation regions.