A clock generation apparatus comprising: a delay line circuit (440; 440a; 440b) configured to select, as an input signal to a delay path, a fed back portion of a delay clock signal (CK_D) at an output of the delay path, the selection being based on a selection signal, and thereby generate the delay clock signal (CK_D); a switch configured to switch, based on a switch control signal (C_SW), a first voltage or a second voltage to the delay line circuit (440; 440a; 440b) for operation thereof, wherein the first voltage further provides power to the pulse generator, and the second voltage is generated based on a phase difference between the reference clock signal (CK_R) and the delay clock signal (CK_D); and a controller configured to generate the switch control signal (C_SW) based on a frequency of the delay clock signal (CK_D) so that the first voltage is provided to the delay line circuit (440; 440a; 440b) in a coarse tuning period (P_COA) and the second voltage is provided to the delay line circuit (440; 440a; 440b) in a fine tuning period (P_FIN), characterized in that the clock generation apparatus further comprises: a pulse generator configured to generate a pulse signal and the selection signal using a reference clock signal (CK_R), wherein the pulse generator is configured to generate the pulse signal including a first pulse synchronized to an edge of the reference clock signal (CK_R), and to generate the selection signal activated during a time period that includes the first pulse, and wherein the delay line circuit (440; 440a; 440b) is configured to select as the input signal to the delay path the pulse signal or the fed back portion of the delay clock signal (CK_D). a delay line circuit (440; 440a; 440b) configured to select, as an input signal to a delay path, a fed back portion of a delay clock signal (CK_D) at an output of the delay path, the selection being based on a selection signal, and thereby generate the delay clock signal (CK_D); a switch configured to switch, based on a switch control signal (C_SW), a first voltage or a second voltage to the delay line circuit (440; 440a; 440b) for operation thereof, wherein the first voltage further provides power to the pulse generator, and the second voltage is generated based on a phase difference between the reference clock signal (CK_R) and the delay clock signal (CK_D); and a controller configured to generate the switch control signal (C_SW) based on a frequency of the delay clock signal (CK_D) so that the first voltage is provided to the delay line circuit (440; 440a; 440b) in a coarse tuning period (P_COA) and the second voltage is provided to the delay line circuit (440; 440a; 440b) in a fine tuning period (P_FIN), characterized in that the clock generation apparatus further comprises: a pulse generator configured to generate a pulse signal and the selection signal using a reference clock signal (CK_R), wherein the pulse generator is configured to generate the pulse signal including a first pulse synchronized to an edge of the reference clock signal (CK_R), and to generate the selection signal activated during a time period that includes the first pulse, and wherein the delay line circuit (440; 440a; 440b) is configured to select as the input signal to the delay path the pulse signal or the fed back portion of the delay clock signal (CK_D). a pulse generator configured to generate a pulse signal and the selection signal using a reference clock signal (CK_R), wherein the pulse generator is configured to generate the pulse signal including a first pulse synchronized to an edge of the reference clock signal (CK_R), and to generate the selection signal activated during a time period that includes the first pulse, and wherein the delay line circuit (440; 440a; 440b) is configured to select as the input signal to the delay path the pulse signal or the fed back portion of the delay clock signal (CK_D).