A wafer-scale x-ray detector comprising: a seamless silicon substrate (120,220,320); a first plurality of pixel pads (132,232,332) and a first plurality of pin pads (134,234,334) on a first surface of the seamless silicon substrate, insulated from the seamless silicon substrate by an insulating layer (130,230,330), the first plurality of pin pads (134,234,334) surrounding the first plurality of the pixel pads (132,232,332), to define a first chip region; a second plurality of pixel pads (132, 232, 332) and a second plurality of pin pads (134, 234, 334) on the first surface of the seamless silicon substrate, insulated from the seamless silicon substrate by the insulating layer, the second plurality of pin pads (134, 234, 334) surrounding the second plurality of the pixel pads (132, 232, 332), to define a second chip region, a photoconductor layer (160,260,360) for irradiation by x-rays arranged on the first and second pluralities of pixel pads and the first and second pluralities of pin pads; a plurality of pixel electrodes (150,250,350) between the photoconductor layer (160,260,360) and the first and second pluralities of pixel pads (132, 232, 332) and between the photoconductor layer and the first and second pluralities of pin pads (134, 234, 334), a printed circuit substrate (110,310) on a second surface of the seamless silicon substrate; and a common electrode (170,370) on the photoconductor layer, and a redistribution layer (140, 240, 340) between the pixel electrodes and the pluralities of pixel pads, wherein the redistribution layer electrically connects the first and second pluralities of pixel pads (132, 232, 332) to the plurality of pixel electrodes (150, 250, 350), respectively, wherein the seamless silicon substrate (120,330) includes a plurality of first via holes (135,335) and a plurality of via contacts (139,339) in the plurality of the first holes (135,335), and the first and second pluralities of pin pads are electrically connected to the printed circuit substrate through corresponding via contacts; and the first plurality of the pin pads (134,234,334) is electrically connected to the first plurality of pixel pads (132,232,332), respectively, and the second plurality of the pin pads (134, 234, 334) is electrically connected to the second plurality of pixel pads (132, 232, 332), respectively. a seamless silicon substrate (120,220,320); a first plurality of pixel pads (132,232,332) and a first plurality of pin pads (134,234,334) on a first surface of the seamless silicon substrate, insulated from the seamless silicon substrate by an insulating layer (130,230,330), the first plurality of pin pads (134,234,334) surrounding the first plurality of the pixel pads (132,232,332), to define a first chip region; a second plurality of pixel pads (132, 232, 332) and a second plurality of pin pads (134, 234, 334) on the first surface of the seamless silicon substrate, insulated from the seamless silicon substrate by the insulating layer, the second plurality of pin pads (134, 234, 334) surrounding the second plurality of the pixel pads (132, 232, 332), to define a second chip region, a photoconductor layer (160,260,360) for irradiation by x-rays arranged on the first and second pluralities of pixel pads and the first and second pluralities of pin pads; a plurality of pixel electrodes (150,250,350) between the photoconductor layer (160,260,360) and the first and second pluralities of pixel pads (132, 232, 332) and between the photoconductor layer and the first and second pluralities of pin pads (134, 234, 334), a printed circuit substrate (110,310) on a second surface of the seamless silicon substrate; and a common electrode (170,370) on the photoconductor layer, and a redistribution layer (140, 240, 340) between the pixel electrodes and the pluralities of pixel pads, wherein the redistribution layer electrically connects the first and second pluralities of pixel pads (132, 232, 332) to the plurality of pixel electrodes (150, 250, 350), respectively, wherein the seamless silicon substrate (120,330) includes a plurality of first via holes (135,335) and a plurality of via contacts (139,339) in the plurality of the first holes (135,335), and the first and second pluralities of pin pads are electrically connected to the printed circuit substrate through corresponding via contacts; and the first plurality of the pin pads (134,234,334) is electrically connected to the first plurality of pixel pads (132,232,332), respectively, and the second plurality of the pin pads (134, 234, 334) is electrically connected to the second plurality of pixel pads (132, 232, 332), respectively.