An electrostatic discharge, ESD, protection device, comprising: a substrate structure comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first doped region and a second doped region having different conductivity types, the first doped region comprising a first portion of the semiconductor substrate and a first region of the first fin, the second doped region comprising a second portion of the semiconductor substrate, a second region of the first fin adjacent to the first region of the first fin, and the second fin; a first gate structure on a surface portion of the first region of the first fin and a surface portion of the second region of the first fin, the first gate structure comprising: an interface layer on the surface portion of the first region of the first fin and the surface portion of the second region of the first fin; a spacer on the first fin and adjacent the interface layer; a high-k dielectric layer on the interface layer and on opposite inner sidewalls of the spacer; a first work-function adjusting layer on a first portion of the high-k dielectric layer that is on the surface portion of the first region of the first fin; a second work-function adjusting layer on the first work-function adjusting layer and on a second portion of the high-k dielectric layer that is on the surface portion of the second region of the first fin; and a gate on the second work-function adjusting layer; and a first highly doped region in the first region and having a same conductivity type as a conductivity type of the first doped region and a doping concentration higher than a doping concentration of the first doped region; and a second highly doped region in the second fin and having a same conductivity type as a conductivity type of the second doped region and a doping concentration higher than a doping concentration of the second doped region. a substrate structure comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first doped region and a second doped region having different conductivity types, the first doped region comprising a first portion of the semiconductor substrate and a first region of the first fin, the second doped region comprising a second portion of the semiconductor substrate, a second region of the first fin adjacent to the first region of the first fin, and the second fin; a first gate structure on a surface portion of the first region of the first fin and a surface portion of the second region of the first fin, the first gate structure comprising: an interface layer on the surface portion of the first region of the first fin and the surface portion of the second region of the first fin; a spacer on the first fin and adjacent the interface layer; a high-k dielectric layer on the interface layer and on opposite inner sidewalls of the spacer; a first work-function adjusting layer on a first portion of the high-k dielectric layer that is on the surface portion of the first region of the first fin; a second work-function adjusting layer on the first work-function adjusting layer and on a second portion of the high-k dielectric layer that is on the surface portion of the second region of the first fin; and a gate on the second work-function adjusting layer; and a first highly doped region in the first region and having a same conductivity type as a conductivity type of the first doped region and a doping concentration higher than a doping concentration of the first doped region; and a second highly doped region in the second fin and having a same conductivity type as a conductivity type of the second doped region and a doping concentration higher than a doping concentration of the second doped region. an interface layer on the surface portion of the first region of the first fin and the surface portion of the second region of the first fin; a spacer on the first fin and adjacent the interface layer; a high-k dielectric layer on the interface layer and on opposite inner sidewalls of the spacer; a first work-function adjusting layer on a first portion of the high-k dielectric layer that is on the surface portion of the first region of the first fin; a second work-function adjusting layer on the first work-function adjusting layer and on a second portion of the high-k dielectric layer that is on the surface portion of the second region of the first fin; and a gate on the second work-function adjusting layer; and a first highly doped region in the first region and having a same conductivity type as a conductivity type of the first doped region and a doping concentration higher than a doping concentration of the first doped region; and a second highly doped region in the second fin and having a same conductivity type as a conductivity type of the second doped region and a doping concentration higher than a doping concentration of the second doped region.