A test circuit, comprising: a signal processing module, which is configured to receive a pulse signal to be tested and output a processing signal under the control of a control signal; a sampling module, which is connected to an output terminal of the signal processing module and is configured to receive the processing signal and generate a sampling signal according to the processing signal; wherein the first sampling pulse and the second sampling pulse have a pulse width difference, and the pulse width difference is equal to a pulse width of the pulse signal; characterized in that, wherein the processing signal is the pulse signal or the inverted pulse signal in time division, and the signal processing module is configured to invert a first pulse in the timing sequence in the pulse signal and not invert the remaining pulses in response to a control signal; the sampling signal includes a first sampling pulse and a second sampling pulse, and the sampling module is configured to generate the first sampling pulse and the second sampling pulse in response to rising edges or falling edges of the processing signal; wherein the sampling module is configured to generate the first sampling pulse in response to the different edge of the first two pulses in the pulse signal at time sequence, and to generate the second sampling pulse in response to the same edges of the last two pulses in the pulse signal at time sequence; wherein the sampling module comprises a first temporary, a first inverter and a second inverter, a clock driving terminal of the first temporary is connected to the output terminals of the signal processing module, an input terminal of the first inverter is connected to an output terminal of the first temporary, an output terminal of the first inverter is connected to an input terminal of the first temporary, an input terminal of the second inverter is connected to the output terminal of the first inverter, and an output terminal of the second inverter is configured to output the sampling signal. a signal processing module, which is configured to receive a pulse signal to be tested and output a processing signal under the control of a control signal; a sampling module, which is connected to an output terminal of the signal processing module and is configured to receive the processing signal and generate a sampling signal according to the processing signal; wherein the first sampling pulse and the second sampling pulse have a pulse width difference, and the pulse width difference is equal to a pulse width of the pulse signal; characterized in that, wherein the processing signal is the pulse signal or the inverted pulse signal in time division, and the signal processing module is configured to invert a first pulse in the timing sequence in the pulse signal and not invert the remaining pulses in response to a control signal; the sampling signal includes a first sampling pulse and a second sampling pulse, and the sampling module is configured to generate the first sampling pulse and the second sampling pulse in response to rising edges or falling edges of the processing signal; wherein the sampling module is configured to generate the first sampling pulse in response to the different edge of the first two pulses in the pulse signal at time sequence, and to generate the second sampling pulse in response to the same edges of the last two pulses in the pulse signal at time sequence; wherein the sampling module comprises a first temporary, a first inverter and a second inverter, a clock driving terminal of the first temporary is connected to the output terminals of the signal processing module, an input terminal of the first inverter is connected to an output terminal of the first temporary, an output terminal of the first inverter is connected to an input terminal of the first temporary, an input terminal of the second inverter is connected to the output terminal of the first inverter, and an output terminal of the second inverter is configured to output the sampling signal.