A polyphase filter, comprising: a first fixed resistor, which has one end connected to a first input terminal, and another end connected to a first output terminal; a first variable resistor, which has one end connected to the first input terminal, and another end connected to a second output terminal; a second fixed resistor, which has one end connected to a second input terminal, and another end connected to a third output terminal; a second variable resistor, which has one end connected to the second input terminal, and another end connected to a fourth output terminal; a first variable capacitor, which has one end connected to the second input terminal, and another end connected to the first output terminal; a second variable capacitor, which has one end connected to the first input terminal, and another end connected to the second output terminal; a third variable capacitor, which has one end connected to the first input terminal, and another end connected to the third output terminal; and a fourth variable capacitor, which has one end connected to the second input terminal, and another end connected to the fourth output terminal, the first variable resistor and the second variable resistor having resistance values that are equal to each other, the resistance values being set so as to correct an amplitude error between orthogonal signals of outputs of the first output terminal to the fourth output terminal, the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor having capacitance values that are equal to one another, the capacitance values being set so as to correct a phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal. a first fixed resistor, which has one end connected to a first input terminal, and another end connected to a first output terminal; a first variable resistor, which has one end connected to the first input terminal, and another end connected to a second output terminal; a second fixed resistor, which has one end connected to a second input terminal, and another end connected to a third output terminal; a second variable resistor, which has one end connected to the second input terminal, and another end connected to a fourth output terminal; a first variable capacitor, which has one end connected to the second input terminal, and another end connected to the first output terminal; a second variable capacitor, which has one end connected to the first input terminal, and another end connected to the second output terminal; a third variable capacitor, which has one end connected to the first input terminal, and another end connected to the third output terminal; and a fourth variable capacitor, which has one end connected to the second input terminal, and another end connected to the fourth output terminal, the first variable resistor and the second variable resistor having resistance values that are equal to each other, the resistance values being set so as to correct an amplitude error between orthogonal signals of outputs of the first output terminal to the fourth output terminal, the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor having capacitance values that are equal to one another, the capacitance values being set so as to correct a phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal. the first variable resistor and the second variable resistor having resistance values that are equal to each other, the resistance values being set so as to correct an amplitude error between orthogonal signals of outputs of the first output terminal to the fourth output terminal, the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor having capacitance values that are equal to one another, the capacitance values being set so as to correct a phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal.