An apparatus, comprising: a first junction isolated clamp circuit coupled between a first power circuit and a signal node, the first power circuit to provide a first reference voltage, and the first clamp circuit to direct energy from the signal node to the first power circuit in response to a transient event resulting in a voltage at the signal node being lower than a second reference voltage, wherein the first junction isolated clamp circuit comprises: a first NPN transistor having a collector connected to the first power circuit and an emitter coupled to the signal node; a second NPN transistor having an emitter connected to the first power circuit and a base and a collector connected to a base of the first NPN transistor; and a second junction isolated clamp circuit coupled between a second power circuit and the signal node, the second junction isolated clamp circuit comprising a third NPN junction isolated transistor, a collector terminal of the third NPN junction isolated transistor to be prevented from having a lower voltage than the second reference voltage, the second power circuit to provide the second reference voltage, the second reference voltage to be a lower voltage than the first reference voltage, and the second clamp circuit to direct energy from the signal node to the second power circuit in response to a transient event resulting in the voltage at the signal node being higher than the first reference voltage; wherein the second junction isolated clamp comprises: the third NPN transistor having an emitter connected to the second power circuit; a diode having an anode coupled to the signal node and a cathode connected to the collector of the third NPN transistor; a fourth NPN transistor having an emitter connected to the anode of the diode and a base and a collector connected to a base of the third NPN transistor. a first junction isolated clamp circuit coupled between a first power circuit and a signal node, the first power circuit to provide a first reference voltage, and the first clamp circuit to direct energy from the signal node to the first power circuit in response to a transient event resulting in a voltage at the signal node being lower than a second reference voltage, wherein the first junction isolated clamp circuit comprises: a first NPN transistor having a collector connected to the first power circuit and an emitter coupled to the signal node; a second NPN transistor having an emitter connected to the first power circuit and a base and a collector connected to a base of the first NPN transistor; and a first NPN transistor having a collector connected to the first power circuit and an emitter coupled to the signal node; a second NPN transistor having an emitter connected to the first power circuit and a base and a collector connected to a base of the first NPN transistor; and a second junction isolated clamp circuit coupled between a second power circuit and the signal node, the second junction isolated clamp circuit comprising a third NPN junction isolated transistor, a collector terminal of the third NPN junction isolated transistor to be prevented from having a lower voltage than the second reference voltage, the second power circuit to provide the second reference voltage, the second reference voltage to be a lower voltage than the first reference voltage, and the second clamp circuit to direct energy from the signal node to the second power circuit in response to a transient event resulting in the voltage at the signal node being higher than the first reference voltage; wherein the second junction isolated clamp comprises: the third NPN transistor having an emitter connected to the second power circuit; a diode having an anode coupled to the signal node and a cathode connected to the collector of the third NPN transistor; a fourth NPN transistor having an emitter connected to the anode of the diode and a base and a collector connected to a base of the third NPN transistor. the third NPN transistor having an emitter connected to the second power circuit; a diode having an anode coupled to the signal node and a cathode connected to the collector of the third NPN transistor; a fourth NPN transistor having an emitter connected to the anode of the diode and a base and a collector connected to a base of the third NPN transistor.