A method for forming a three-dimensional memory device, comprising: forming an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes an alternating stack of a first dielectric layer and a second dielectric layer that is different from first dielectric layer, wherein the plurality of first dielectric layers and second dielectric layers are extended in a lateral direction that is parallel to the surface of the substrate; forming two structure strengthen plugs (60, 460) in an upper portion of the alternating dielectric stack, forming a plurality of channel structures in the alternating dielectric stack, wherein forming the multiple channel structures includes forming multiple channel holes penetrating the alternating dielectric stack; forming a plurality of gate line slits in the alternating dielectric stack, transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit, wherein a Gate Line Slit structure is formed in each slit to divide the memory array into multiple memory fingers, forming a top selective gate cut (10, 310) in an upper portion of the alternating dielectric stack, wherein the top selective gate cut (10, 310) is located in the middle of the memory finger to separate the memory finger into two equal parts, wherein the top selective gate cut (10, 310) is formed in an upper portion of the alternating dielectric stack and extends along a WL direction, and the structure strengthen plug (60, 460) is formed on each side of the TSG cut (10, 310) in the upper portion of the alternating dielectric stack and in that the top selective gate cut (10, 310) and the structure strengthen plug (60, 460) are formed simultaneously in a single process, wherein the top selective gate cut (10, 310) and the two structure strengthen plugs (60, 460) are formed from an insulating material, characterised in that each structure strengthen plug (60, 460) is formed to have a narrow support body and two enlarged connecting portions (63, 463); each gate line slit is formed to expose a sidewall of one enlarged connecting portion (63, 463) of a corresponding structure strengthen plug (60, 460); the gate line slit structure is formed including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug (60, 460). forming an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes an alternating stack of a first dielectric layer and a second dielectric layer that is different from first dielectric layer, wherein the plurality of first dielectric layers and second dielectric layers are extended in a lateral direction that is parallel to the surface of the substrate; forming two structure strengthen plugs (60, 460) in an upper portion of the alternating dielectric stack, forming a plurality of channel structures in the alternating dielectric stack, wherein forming the multiple channel structures includes forming multiple channel holes penetrating the alternating dielectric stack; forming a plurality of gate line slits in the alternating dielectric stack, transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit, wherein a Gate Line Slit structure is formed in each slit to divide the memory array into multiple memory fingers, forming a top selective gate cut (10, 310) in an upper portion of the alternating dielectric stack, wherein the top selective gate cut (10, 310) is located in the middle of the memory finger to separate the memory finger into two equal parts, wherein the top selective gate cut (10, 310) is formed in an upper portion of the alternating dielectric stack and extends along a WL direction, and the structure strengthen plug (60, 460) is formed on each side of the TSG cut (10, 310) in the upper portion of the alternating dielectric stack and in that the top selective gate cut (10, 310) and the structure strengthen plug (60, 460) are formed simultaneously in a single process, wherein the top selective gate cut (10, 310) and the two structure strengthen plugs (60, 460) are formed from an insulating material,