An integrated circuit, comprising: a first differential pair of transistors (418, 420); a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of the first differential pair of transistors (418, 420); a second high-pass filter having an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors (418, 420), the second signal a complementary signal of the first signal; a second differential pair of transistors (430, 432) having control electrodes coupled to a first voltage supply terminal; a first variable load resistor and a first inductor connected in series between the first voltage supply terminal and a first one of the second differential pair of transistors (430, 432); a second variable load resistor and a second inductor connected in series between the first voltage supply terminal and a second one of the second differential pair of transistors (430, 432); a low-pass filter coupled between the first differential pair of transistors (418, 420) and the second differential pair of transistors (430, 432); and an output resistor coupled between first current electrodes of the second differential pair of transistors (430, 432), wherein the low-pass filter comprises first and second variable capacitors (422, 424) and third and fourth inductors (426, 428) connected between the first and second differential pair of transistors (418, 420, 430, 432), a first terminal of the first variable capacitor connected to a first terminal of the third inductor and a second current electrode of a first one of the first differential pair of transistors, a second terminal of the third inductor connected to a first terminal of the second variable capacitor and a first current electrode of a first one of the second differential pair of transistors, a second terminal of the first variable capacitor connected to a first terminal of the fourth inductor and a second current electrode of a second one of the first differential pair of transistors, a second terminal of the fourth inductor connected to a second terminal of the second variable capacitor and a first current electrode of a second one of the second differential pair of transistors (430, 432). a first differential pair of transistors (418, 420); a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of the first differential pair of transistors (418, 420); a second high-pass filter having an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors (418, 420), the second signal a complementary signal of the first signal; a second differential pair of transistors (430, 432) having control electrodes coupled to a first voltage supply terminal; a first variable load resistor and a first inductor connected in series between the first voltage supply terminal and a first one of the second differential pair of transistors (430, 432); a second variable load resistor and a second inductor connected in series between the first voltage supply terminal and a second one of the second differential pair of transistors (430, 432); a low-pass filter coupled between the first differential pair of transistors (418, 420) and the second differential pair of transistors (430, 432); and an output resistor coupled between first current electrodes of the second differential pair of transistors (430, 432), wherein the low-pass filter comprises first and second variable capacitors (422, 424) and third and fourth inductors (426, 428) connected between the first and second differential pair of transistors (418, 420, 430, 432), a first terminal of the first variable capacitor connected to a first terminal of the third inductor and a second current electrode of a first one of the first differential pair of transistors, a second terminal of the third inductor connected to a first terminal of the second variable capacitor and a first current electrode of a first one of the second differential pair of transistors, a second terminal of the first variable capacitor connected to a first terminal of the fourth inductor and a second current electrode of a second one of the first differential pair of transistors, a second terminal of the fourth inductor connected to a second terminal of the second variable capacitor and a first current electrode of a second one of the second differential pair of transistors (430, 432).