A memory device (400, 500), comprising: an array (100, 440, 540) of memory cells (111-1,..., 111-N); and control circuitry (442, 542) having sense circuitry (444, 544) coupled to the array (100, 440, 540) and an error correction code, hence forth the termed ECC, decoder, wherein the control circuitry (442, 542) is configured to: determine changes in threshold voltages (Vts) associated with the memory cells (111-1,..., 111-N); and adjust the sense circuitry (444, 544) based on the determined changes; and wherein the sense circuitry (444, 544) is configured to sense a state of the memory cells (111-1,..., 111-N) using a first voltage; the ECC decoder is configured to perform an error correction operation on the sensed state; the sense circuitry (444, 544) is configured to sense a state of the memory cells (111-1,..., 111-N) using a second voltage if the error correction operation results in a failure; the control circuitry (442, 542) is configured to determine a voltage least likely to result in a failure of the error correction operation on the state sensed using the first voltage; and the sense circuitry (444, 544) is configured to use the determined voltage as the first voltage characterized in that the control circuitry (442, 542) is configured: to determine the changes in threshold voltages (Vts) and adjust the sense circuitry without using a reference cell; and the control circuitry (442, 542) is configured to use a quantity of memory cells (111-1,..., 111-N) pogrammed to a particular state and a quantity of programming and sensing operations previously performed on the memory cells (111 -1,..., 111-N) to determine the voltage least likely to result in a failure of the error correction operation. an array (100, 440, 540) of memory cells (111-1,..., 111-N); and control circuitry (442, 542) having sense circuitry (444, 544) coupled to the array (100, 440, 540) and an error correction code, hence forth the termed ECC, decoder, wherein the control circuitry (442, 542) is configured to: determine changes in threshold voltages (Vts) associated with the memory cells (111-1,..., 111-N); and adjust the sense circuitry (444, 544) based on the determined changes; and determine changes in threshold voltages (Vts) associated with the memory cells (111-1,..., 111-N); and adjust the sense circuitry (444, 544) based on the determined changes; and wherein the sense circuitry (444, 544) is configured to sense a state of the memory cells (111-1,..., 111-N) using a first voltage; the ECC decoder is configured to perform an error correction operation on the sensed state; the sense circuitry (444, 544) is configured to sense a state of the memory cells (111-1,..., 111-N) using a second voltage if the error correction operation results in a failure; the control circuitry (442, 542) is configured to determine a voltage least likely to result in a failure of the error correction operation on the state sensed using the first voltage; and the sense circuitry (444, 544) is configured to use the determined voltage as the first voltage characterized in that the control circuitry (442, 542) is configured: to determine the changes in threshold voltages (Vts) and adjust the sense circuitry without using a reference cell; and the control circuitry (442, 542) is configured to use a quantity of memory cells (111-1,..., 111-N) pogrammed to a particular state and a quantity of programming and sensing operations previously performed on the memory cells (111 -1,..., 111-N) to determine the voltage least likely to result in a failure of the error correction operation. to determine the changes in threshold voltages (Vts) and adjust the sense circuitry without using a reference cell; and the control circuitry (442, 542) is configured to use a quantity of memory cells (111-1,..., 111-N) pogrammed to a particular state and a quantity of programming and sensing operations previously performed on the memory cells (111 -1,..., 111-N) to determine the voltage least likely to result in a failure of the error correction operation.