A silicon carbide semiconductor device (200, 200P) having a plane layout including a central portion and an outer edge portion that surrounds said central portion and that constitutes an outer edge, the silicon carbide semiconductor device comprising: a silicon carbide film having a first main surface and a second main surface opposite to said first main surface in a thickness direction, said silicon carbide film having a first layer portion that constitutes said first main surface and a second layer portion that constitutes said second main surface, said first and second layer portions having an interface IF separated from said first and second main surfaces between said first and second layer portion, said first layer portion including a first breakdown voltage holding layer having a first conductivity type, an outer edge embedded region being provided at said interface in said first layer portion and having a second conductivity type, said second layer portion including a second breakdown voltage holding layer that constitutes said interface and that has said first conductivity type, said first and second breakdown voltage holding layers constituting a breakdown voltage holding region in which said outer edge embedded region is embedded, said second layer portion being provided with semiconductor elements configured to control current from said first main surface through said interface to said second main surface, said first layer portion having a central section and an outer edge section, said central section facing said semiconductor elements in said central portion in the thickness direction, said outer edge section facing said semiconductor elements in said outer edge portion in the thickness direction, said outer edge embedded region being provided in said outer edge section in said first layer portion, said first layer portion including a relaxation region that is surrounded by said outer edge embedded region at said interface, that has at least a portion included in said central portion, and that has said second conductivity type, said outer edge embedded region including a junction terminal region that is in contact with said relaxation region and that has an impurity concentration lower than an impurity concentration of said relaxation region; a first electrode facing said first main surface in each of said central portion and said outer edge portion; and a second electrode in contact with said second main surface in each of said central portion and said outer edge portion, said junction terminal region facing said semiconductor elements in the thickness direction. a silicon carbide film having a first main surface and a second main surface opposite to said first main surface in a thickness direction, said silicon carbide film having a first layer portion that constitutes said first main surface and a second layer portion that constitutes said second main surface, said first and second layer portions having an interface IF separated from said first and second main surfaces between said first and second layer portion, said first layer portion including a first breakdown voltage holding layer having a first conductivity type, an outer edge embedded region being provided at said interface in said first layer portion and having a second conductivity type, said second layer portion including a second breakdown voltage holding layer that constitutes said interface and that has said first conductivity type, said first and second breakdown voltage holding layers constituting a breakdown voltage holding region in which said outer edge embedded region is embedded, said second layer portion being provided with semiconductor elements configured to control current from said first main surface through said interface to said second main surface, said first layer portion having a central section and an outer edge section, said central section facing said semiconductor elements in said central portion in the thickness direction, said outer edge section facing said semiconductor elements in said outer edge portion in the thickness direction, said outer edge embedded region being provided in said outer edge section in said first layer portion, said first layer portion including a relaxation region that is surrounded by said outer edge embedded region at said interface, that has at least a portion included in said central portion, and that has said second conductivity type, said outer edge embedded region including a junction terminal region that is in contact with said relaxation region and that has an impurity concentration lower than an impurity concentration of said relaxation region; a first electrode facing said first main surface in each of said central portion and said outer edge portion; and a second electrode in contact with said second main surface in each of said central portion and said outer edge portion, said junction terminal region facing said semiconductor elements in the thickness direction.