A method for decoupling common mode and differential loop bandwidth adjustment of a circuit, the method comprising: increasing, with a capacitive element, a net capacitance of the circuit in a common mode, wherein the capacitive element comprises: a pair of cross-coupled capacitors coupled to differential nodes of the circuit; and a pair of negative gain buffers coupled to respective capacitors; and wherein the capacitance of the capacitive element is increased to a positive capacitance to stabilize a common mode feedback loop of the circuit in a common mode; and further comprising negating, with the capacitive element, at least a portion of parasitic capacitance of the circuit in a differential mode; wherein each of the negative gain buffers comprises: a first transistor comprising: a source electrode; a drain electrode; and a gate electrode coupled to the drain electrode; and a plurality of second transistors coupled in parallel, each of the second transistors comprising: a drain electrode coupled to the source electrode of the first transistor; a source electrode coupled to ground; and a gate electrode, wherein the negating and the increasing comprise tuning the negative gain buffers of the capacitive element by providing a signal to the gate of one or more selected second transistors. increasing, with a capacitive element, a net capacitance of the circuit in a common mode, wherein the capacitive element comprises: a pair of cross-coupled capacitors coupled to differential nodes of the circuit; and a pair of negative gain buffers coupled to respective capacitors; and a pair of cross-coupled capacitors coupled to differential nodes of the circuit; and a pair of negative gain buffers coupled to respective capacitors; and wherein the capacitance of the capacitive element is increased to a positive capacitance to stabilize a common mode feedback loop of the circuit in a common mode; and further comprising negating, with the capacitive element, at least a portion of parasitic capacitance of the circuit in a differential mode; wherein each of the negative gain buffers comprises: a first transistor comprising: a source electrode; a drain electrode; and a gate electrode coupled to the drain electrode; and a plurality of second transistors coupled in parallel, each of the second transistors comprising: a drain electrode coupled to the source electrode of the first transistor; a source electrode coupled to ground; and a gate electrode, wherein the negating and the increasing comprise tuning the negative gain buffers of the capacitive element by providing a signal to the gate of one or more selected second transistors. a first transistor comprising: a source electrode; a drain electrode; and a gate electrode coupled to the drain electrode; and a source electrode; a drain electrode; and a gate electrode coupled to the drain electrode; and a plurality of second transistors coupled in parallel, each of the second transistors comprising: a drain electrode coupled to the source electrode of the first transistor; a source electrode coupled to ground; and a gate electrode, a drain electrode coupled to the source electrode of the first transistor; a source electrode coupled to ground; and a gate electrode, wherein the negating and the increasing comprise tuning the negative gain buffers of the capacitive element by providing a signal to the gate of one or more selected second transistors.