A charge pump circuit comprising: a substrate; a first pump unit (100_1) of a plurality of pump units, comprising a first capacitor connected to a first node and a first p-type transistor having a drain connected to the first node, a source is connected to a source voltage, a gate is connected to a switch signal provided as a control signal, and a body of the first p-type transistor is connected to a body voltage, the first pump unit (100_1) configured to generate a first node voltage by using a clock signal; and a second pump unit (100_n) comprising a second capacitor (Cn), a second transistor (PTn), and a third transistor, the second pump unit (100_n) configured to generate a negative output voltage by using the first node voltage, wherein a first terminal of the second capacitor (Cn) is connected to a node (Nn-1) of the previous pump unit of the plurality of pump units, and a second terminal of the second capacitor (Cn) is connected to a second node (Nn), the second transistor is P-type transistor a drain of which is connected to the second node (Nn), a source of the second transistor is connected to a source voltage (VSn), a gate is connected to a switch signal provided as a control signal, and a body of the second p-type transistor is connected to a body voltage (VBn), and the third transistor is an n-type transistor having a drain connected to the second node (Nn), a body of the third transistor is connected to second node (Nn), a gate of the third transistor is connected to a switch signal provided as a control signal, a source is connected to an output terminal OP and is arranged to output an output voltage VOUT in response to the switch signal; wherein the first, second and third transistors are formed in wells in a first surface of the substrate; wherein the clock signal and the first node voltage are each toggled between a low-level voltage and a high-level voltage, wherein the charge pump circuit is configured such that: a magnitude of an absolute value of the negative output voltage is greater than a magnitude of an absolute value of the high-level voltage of the clock signal, and further comprising an isolation layer formed through the substrate and extending from the first surface to a second surface of the substrate opposing the first surface, the isolation layer configured to electrically isolate a body of the third transistor from a body of the second transistor. a substrate; a first pump unit (100_1) of a plurality of pump units, comprising a first capacitor connected to a first node and a first p-type transistor having a drain connected to the first node, a source is connected to a source voltage, a gate is connected to a switch signal provided as a control signal, and a body of the first p-type transistor is connected to a body voltage, the first pump unit (100_1) configured to generate a first node voltage by using a clock signal; and a second pump unit (100_n) comprising a second capacitor (Cn), a second transistor (PTn), and a third transistor, the second pump unit (100_n) configured to generate a negative output voltage by using the first node voltage, wherein a first terminal of the second capacitor (Cn) is connected to a node (Nn-1) of the previous pump unit of the plurality of pump units, and a second terminal of the second capacitor (Cn) is connected to a second node (Nn), the second transistor is P-type transistor a drain of which is connected to the second node (Nn), a source of the second transistor is connected to a source voltage (VSn), a gate is connected to a switch signal provided as a control signal, and a body of the second p-type transistor is connected to a body voltage (VBn), and the third transistor is an n-type transistor having a drain connected to the second node (Nn), a body of the third transistor is connected to second node (Nn), a gate of the third transistor is connected to a switch signal provided as a control signal, a source is connected to an output terminal OP and is arranged to output an output voltage VOUT in response to the switch signal; wherein the first, second and third transistors are formed in wells in a first surface of the substrate; wherein the clock signal and the first node voltage are each toggled between a low-level voltage and a high-level voltage, wherein the charge pump circuit is configured such that: a magnitude of an absolute value of the negative output voltage is greater than a magnitude of an absolute value of the high-level voltage of the clock signal, and further comprising an isolation layer formed through the substrate and extending from the first surface to a second surface of the substrate opposing the first surface, the isolation layer configured to electrically isolate a body of the third transistor from a body of the second transistor. a magnitude of an absolute value of the negative output voltage is greater than a magnitude of an absolute value of the high-level voltage of the clock signal, and further comprising an isolation layer formed through the substrate and extending from the first surface to a second surface of the substrate opposing the first surface, the isolation layer configured to electrically isolate a body of the third transistor from a body of the second transistor.