A test method comprising: providing a test structure having a substrate having a to-be-tested region and a peripheral region surrounding the to-be-tested region, the to-be-tested region having at least one fin, the peripheral region having at least one fin, the at least one fin in the to-be-tested region being parallel to the at least one fin in the peripheral region, and the at least one fin in the to-be-tested region extends into the peripheral region; at least one first gate structure covering side and top surfaces of the at least one fin in the to-be-tested region; a plurality of parallel second gate structures covering side and top surfaces of the at least one fin in the peripheral region, and the second gate structures being parallel to the first gate structure; source/drain regions formed in portions of the fins between adjacent second gate structures and portions of the fins between the at least one first gate structure and adjacent second gate structures; an insulation layer covering portions of side surfaces of the fins; a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region, the plurality of first conductive structures crossing over at least two fins, and the plurality of first conductive structures being on surfaces of source/drain regions of at least two fins; wherein: a first gate structure and a source region at one side of the first gate structure and a corresponding drain region at another side of the first gate structure form a first transistor; a second gate structure and a source region at one side of the second gate structure and a corresponding drain region at another side of the second gate structure form a second transistor; the to-be-tested region has at least one first transistor; and the peripheral region has a plurality of second transistors; turning on the at least one first transistor; performing temperature tests on the plurality of second transistors with pre-determined time intervals to obtain temperatures of the channel regions of the plurality of second transistors; obtaining correlations between the temperatures and time, wherein a current and a voltage of a plurality of second transistors subsequently formed in the peripheral region are subsequently tested, thereby obtaining the temperatures of the channel regions of the plurality of second transistors in the peripheral region. providing a test structure having a substrate having a to-be-tested region and a peripheral region surrounding the to-be-tested region, the to-be-tested region having at least one fin, the peripheral region having at least one fin, the at least one fin in the to-be-tested region being parallel to the at least one fin in the peripheral region, and the at least one fin in the to-be-tested region extends into the peripheral region; at least one first gate structure covering side and top surfaces of the at least one fin in the to-be-tested region; a plurality of parallel second gate structures covering side and top surfaces of the at least one fin in the peripheral region, and the second gate structures being parallel to the first gate structure; source/drain regions formed in portions of the fins between adjacent second gate structures and portions of the fins between the at least one first gate structure and adjacent second gate structures; an insulation layer covering portions of side surfaces of the fins; a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region, the plurality of first conductive structures crossing over at least two fins, and the plurality of first conductive structures being on surfaces of source/drain regions of at least two fins; wherein: a first gate structure and a source region at one side of the first gate structure and a corresponding drain region at another side of the first gate structure form a first transistor; a second gate structure and a source region at one side of the second gate structure and a corresponding drain region at another side of the second gate structure form a second transistor; the to-be-tested region has at least one first transistor; and the peripheral region has a plurality of second transistors; a first gate structure and a source region at one side of the first gate structure and a corresponding drain region at another side of the first gate structure form a first transistor; a second gate structure and a source region at one side of the second gate structure and a corresponding drain region at another side of the second gate structure form a second transistor; the to-be-tested region has at least one first transistor; and the peripheral region has a plurality of second transistors; turning on the at least one first transistor; performing temperature tests on the plurality of second transistors with pre-determined time intervals to obtain temperatures of the channel regions of the plurality of second transistors; obtaining correlations between the temperatures and time, wherein a current and a voltage of a plurality of second transistors subsequently formed in the peripheral region are subsequently tested, thereby obtaining the temperatures of the channel regions of the plurality of second transistors in the peripheral region.