A stackup of a plurality of display pixels, the stackup comprising: a plurality of gate lines; a plurality of data lines, the plurality of data lines being electrically insulated from the plurality of gate lines; a first, second and third region each having circuit elements of the display pixels (515, 517), the third region disposed between the first and second regions, and wherein circuit elements of the display pixels (515, 517) in the first region are electrically connected together in a first direction by a first plurality of first line portions and the circuit elements of the display pixels (515, 517) in the first region are electrically connected together in a second direction by a first plurality of second line portions, circuit elements of the display pixels (515, 517) in the second region are electrically connected together in the first direction by a second plurality of first line portions and the circuit elements of the display pixels (515, 517) in the second region are electrically connected together in the second direction by a second plurality of second line portions, and the first plurality of first line portions and the first plurality of second line portions, and the second plurality of first line portions and the second plurality of second line portions, are electrically insulated from the plurality of gate lines and the plurality of data lines; wherein at least one conductive pathway (613, 615) connects circuit elements of the first region to circuit elements of the second region, wherein the at least one conductive pathway (613, 615) runs through one or more display pixels of the third region without electrically connecting to the circuit elements of the third region; and wherein a plurality of display pixels disposed along the first direction in the first region are contact pixels that include contact points that electrically connect the circuit elements of each of the contact pixels with the at least one conductive pathway (613, 615). a plurality of gate lines; a plurality of data lines, the plurality of data lines being electrically insulated from the plurality of gate lines; a first, second and third region each having circuit elements of the display pixels (515, 517), the third region disposed between the first and second regions, and wherein circuit elements of the display pixels (515, 517) in the first region are electrically connected together in a first direction by a first plurality of first line portions and the circuit elements of the display pixels (515, 517) in the first region are electrically connected together in a second direction by a first plurality of second line portions, circuit elements of the display pixels (515, 517) in the second region are electrically connected together in the first direction by a second plurality of first line portions and the circuit elements of the display pixels (515, 517) in the second region are electrically connected together in the second direction by a second plurality of second line portions, and the first plurality of first line portions and the first plurality of second line portions, and the second plurality of first line portions and the second plurality of second line portions, are electrically insulated from the plurality of gate lines and the plurality of data lines; wherein at least one conductive pathway (613, 615) connects circuit elements of the first region to circuit elements of the second region, wherein the at least one conductive pathway (613, 615) runs through one or more display pixels of the third region without electrically connecting to the circuit elements of the third region; and wherein a plurality of display pixels disposed along the first direction in the first region are contact pixels that include contact points that electrically connect the circuit elements of each of the contact pixels with the at least one conductive pathway (613, 615).