A method for manufacturing a III-nitride device comprising: a) providing a substrate, being a thinned silicon wafer, thinned from an initial thickness to a reduced thickness; b) forming a stack of active layers (2, 3, 4, 5) on the substrate, each of said active layers comprising a III-nitride material, an underlayer of the stack being a buffer layer, an active-layer-stack/substrate interface being defined as the transition between the stack (2, 3, 4, 5) and the substrate; c) forming a source, a gate and a drain contact on the stack of active layers (2, 3, 4, 5), wherein a gate, a source and a drain region of the substrate are projections of respectively the gate, the source and the drain contact in the substrate; and d) forming a trench in the substrate from a backside of the substrate, said backside being opposite to the side of substrate that is in contact with the stack of active layers (2, 3, 4, 5), up to the underlayer of the stack of active layers (2, 3, 4, 5), the trench completely surrounding the drain region, such that the active-layer-stack/substrate interface is interrupted around the drain region and the drain region is electrically isolated from the gate and source regions across the active-layer-stack/substrate interface, and being positioned in between an edge of the gate region towards the drain region and an edge of the drain region towards the gate region, and having a width such that the drain region of the substrate is substantially made of the silicon, wherein the trench has a width smaller than or equal to the distance between the edge of the gate region towards the drain and the edge of the drain region towards the gate region, wherein the trench has a width greater than or equal to the thickness of the stack of active layers (2, 3, 4, 5), and wherein the trench has a width between 2 μm and 10 μm and an aspect ratio between 10 and 50. a) providing a substrate, being a thinned silicon wafer, thinned from an initial thickness to a reduced thickness; b) forming a stack of active layers (2, 3, 4, 5) on the substrate, each of said active layers comprising a III-nitride material, an underlayer of the stack being a buffer layer, an active-layer-stack/substrate interface being defined as the transition between the stack (2, 3, 4, 5) and the substrate; c) forming a source, a gate and a drain contact on the stack of active layers (2, 3, 4, 5), wherein a gate, a source and a drain region of the substrate are projections of respectively the gate, the source and the drain contact in the substrate; and d) forming a trench in the substrate from a backside of the substrate, said backside being opposite to the side of substrate that is in contact with the stack of active layers (2, 3, 4, 5), up to the underlayer of the stack of active layers (2, 3, 4, 5), the trench completely surrounding the drain region, such that the active-layer-stack/substrate interface is interrupted around the drain region and the drain region is electrically isolated from the gate and source regions across the active-layer-stack/substrate interface, and being positioned in between an edge of the gate region towards the drain region and an edge of the drain region towards the gate region, and having a width such that the drain region of the substrate is substantially made of the silicon, wherein the trench has a width smaller than or equal to the distance between the edge of the gate region towards the drain and the edge of the drain region towards the gate region, wherein the trench has a width greater than or equal to the thickness of the stack of active layers (2, 3, 4, 5), and wherein the trench has a width between 2 μm and 10 μm and an aspect ratio between 10 and 50.