A display device comprising: a substrate, pixels, scan lines, data lines, power supply lines, a power supply routing line, a scan routing line, first link lines, second link lines, first auxiliary link lines, second auxiliary link lines, a first insulating layer, a second insulating layer, a gate insulating layer, a buffer layer, which are disposed on the substrate, wherein the pixels are formed in a free form active area of the substrate, the pixels being located at the crossing of the scan lines and the data lines, and connected to respective power supply lines, wherein the power supply lines in the free form active area have different lengths and are connected to different numbers of pixels depending on their positions; wherein the power supply routing line to which a power supply voltage can be applied and the scan routing line to which scan pulses can be applied are formed in a bezel area of the substrate which is outside the active area; wherein the first and second link lines (LNL1, LNL2) are disposed in the bezel area and are configured to connect the power supply routing line to the power supply lines so as to transmit the power supply voltage from the power supply routing line to the power supply lines, wherein each of the first link lines comprises one end connected to the power supply routing line and the other end connected to one of the power supply lines, wherein the second link lines interconnect the first link lines, wherein each of the first auxiliary link lines comprises one end connected to the power supply routing line and the other end connected to one of the second link lines, wherein each of the second auxiliary link lines comprises one end that is connected to one of the power supply lines and the other end that is connected to one of the second link lines, wherein the first insulating layer is disposed on the scan routing line; the first link lines, the first auxiliary link lines and the second auxiliary link lines are disposed between the first insulating layer and the second insulating layer; and the power supply routing line, the power supply lines, and the second link lines are formed on a same layer disposed on the second insulating layer, and wherein the power supply routing line is connected to the first link lines via contact holes penetrated into the second insulating layer, the power supply lines are connected to the first link lines and to the second auxiliary link lines via contact holes penetrated into the second insulating layer, and the second link lines are connected to the first link lines and to the second auxiliary link lines via contact holes penetrated into the second insulating layer. a substrate, pixels, scan lines, data lines, power supply lines, a power supply routing line, a scan routing line, first link lines, second link lines, first auxiliary link lines, second auxiliary link lines, a first insulating layer, a second insulating layer, a gate insulating layer, a buffer layer, which are disposed on the substrate, wherein the pixels are formed in a free form active area of the substrate, the pixels being located at the crossing of the scan lines and the data lines, and connected to respective power supply lines, wherein the power supply lines in the free form active area have different lengths and are connected to different numbers of pixels depending on their positions; wherein the power supply routing line to which a power supply voltage can be applied and the scan routing line to which scan pulses can be applied are formed in a bezel area of the substrate which is outside the active area; wherein the first and second link lines (LNL1, LNL2) are disposed in the bezel area and are configured to connect the power supply routing line to the power supply lines so as to transmit the power supply voltage from the power supply routing line to the power supply lines, wherein each of the first link lines comprises one end connected to the power supply routing line and the other end connected to one of the power supply lines, wherein the second link lines interconnect the first link lines, wherein each of the first auxiliary link lines comprises one end connected to the power supply routing line and the other end connected to one of the second link lines, wherein each of the second auxiliary link lines comprises one end that is connected to one of the power supply lines and the other end that is connected to one of the second link lines, wherein the first insulating layer is disposed on the scan routing line; the first link lines, the first auxiliary link lines and the second auxiliary link lines are disposed between the first insulating layer and the second insulating layer; and the power supply routing line, the power supply lines, and the second link lines are formed on a same layer disposed on the second insulating layer, and wherein the power supply routing line is connected to the first link lines via contact holes penetrated into the second insulating layer, the power supply lines are connected to the first link lines and to the second auxiliary link lines via contact holes penetrated into the second insulating layer, and the second link lines are connected to the first link lines and to the second auxiliary link lines via contact holes penetrated into the second insulating layer.