A latch circuit for receiving and latching data in response to an input scanning signal comprising: a first latch control line receiving a first drive clock (φAC1); a second latch control line receiving a second drive clock (φAC2); an input transistor being of a first conductivity type having a gate, a first and second electrodes, the first electrode of the input transistor receiving a data signal corresponding to data "0" or data "1" in response to the scanning signal supplied to the gate of the input transistor; a first capacitor retaining a voltage of the data signal received by the input transistor, the first capacitor being connected between the second electrode of the input transistor and the first latch control line; a first transistor having a gate, a first and second electrodes, the first transistor of the first conductivity type, the first electrode of the first transistor being connected to the first latch control line and the gate of the first transistor being connected to the second electrode of the input transistor; a second transistor having a gate, a first and second electrodes, the second transistor being of the first conductivity type, the gate of the second transistor being connected to the second electrode of the first transistor and the first electrode of the second transistor being connected to the second latch control line; a third transistor having a gate, a first and second electrodes, the third transistor being of the first conductivity type, the gate of the third transistor being connected to the second electrode of the first transistor, the first electrode of the third transistor being connected to the second electrode of the second transistor, and the second electrode of the third transistor being connected to an output terminal; a second capacitor connected between the second electrode of the first transistor and the second electrode of the second transistor; and a diode connected between the second electrode of the first transistor and the first latch control line. a first latch control line receiving a first drive clock (φAC1); a second latch control line receiving a second drive clock (φAC2); an input transistor being of a first conductivity type having a gate, a first and second electrodes, the first electrode of the input transistor receiving a data signal corresponding to data "0" or data "1" in response to the scanning signal supplied to the gate of the input transistor; a first capacitor retaining a voltage of the data signal received by the input transistor, the first capacitor being connected between the second electrode of the input transistor and the first latch control line; a first transistor having a gate, a first and second electrodes, the first transistor of the first conductivity type, the first electrode of the first transistor being connected to the first latch control line and the gate of the first transistor being connected to the second electrode of the input transistor; a second transistor having a gate, a first and second electrodes, the second transistor being of the first conductivity type, the gate of the second transistor being connected to the second electrode of the first transistor and the first electrode of the second transistor being connected to the second latch control line; a third transistor having a gate, a first and second electrodes, the third transistor being of the first conductivity type, the gate of the third transistor being connected to the second electrode of the first transistor, the first electrode of the third transistor being connected to the second electrode of the second transistor, and the second electrode of the third transistor being connected to an output terminal; a second capacitor connected between the second electrode of the first transistor and the second electrode of the second transistor; and a diode connected between the second electrode of the first transistor and the first latch control line.