An apparatus comprising circuitry having: a data input receiving portion adapted to receive input data (d1-d6) in parallel responsive to a first clock signal (oclkdiv_b) running at a first rate; a data output transmitting portion adapted to serially transmit output data (serial output 1) from the circuitry responsive to a second clock signal (oclk_b) running at a second rate synchronized to and different from the first rate; a load signal generator including a counter adapted to count responsive to the second clock signal (oclk_b) and outputs a count value, and the load generator is configured to generate a load signal in response to an occurrence of a number of cycles of the second clock signal (oclk_b), the load signal causing the transmitting portion to receive data from the receiving portion; and an error detection portion that includes: a storage element adapted to store a comparison value, a comparator coupled to the storage element and to the counter, the comparator configured to compare bits of the count value to the comparison value, and a capture portion coupled to the comparator and configured to capture output of the comparator at each cycle of the first clock signal (oclkdiv_b), wherein the error detection portion is configured to generate an error detected signal in response to the captured output of the comparator indicating the count value and comparison value are different; and a control circuit coupled to receive the error detected signal and to the programmable load generator, the control circuit configured to control resending of parallel data words from at least the last three cycles from the data input receiving portion to the data output transmitting portion in response to the error detected signal. a data input receiving portion adapted to receive input data (d1-d6) in parallel responsive to a first clock signal (oclkdiv_b) running at a first rate; a data output transmitting portion adapted to serially transmit output data (serial output 1) from the circuitry responsive to a second clock signal (oclk_b) running at a second rate synchronized to and different from the first rate; a load signal generator including a counter adapted to count responsive to the second clock signal (oclk_b) and outputs a count value, and the load generator is configured to generate a load signal in response to an occurrence of a number of cycles of the second clock signal (oclk_b), the load signal causing the transmitting portion to receive data from the receiving portion; and an error detection portion that includes: a storage element adapted to store a comparison value, a comparator coupled to the storage element and to the counter, the comparator configured to compare bits of the count value to the comparison value, and a capture portion coupled to the comparator and configured to capture output of the comparator at each cycle of the first clock signal (oclkdiv_b), wherein the error detection portion is configured to generate an error detected signal in response to the captured output of the comparator indicating the count value and comparison value are different; and a storage element adapted to store a comparison value, a comparator coupled to the storage element and to the counter, the comparator configured to compare bits of the count value to the comparison value, and a capture portion coupled to the comparator and configured to capture output of the comparator at each cycle of the first clock signal (oclkdiv_b), wherein the error detection portion is configured to generate an error detected signal in response to the captured output of the comparator indicating the count value and comparison value are different; and a control circuit coupled to receive the error detected signal and to the programmable load generator, the control circuit configured to control resending of parallel data words from at least the last three cycles from the data input receiving portion to the data output transmitting portion in response to the error detected signal.