A system (70, 150) for dynamic calibration of current sense for switching converters comprising: a first one (1 10a), a second one (1 10b) and a third one of a plurality of current sense channels configured to multiply a respective transistor voltage sensed across a respective transistor (72, 78, 152) by a gain to generate a respective calibration voltage across a respective resistor (124a, 124b, 184), wherein the gain is determined by a gain coefficient (126, 186), and each respective transistor (72, 78, 152) has a matching temperature coefficient and a respective gate (100, 102, 158), the respective transistor of the first one (1 10a) of the current sense channels connected between a voltage supply and a phase node, the respective calibration resistor connected to an output by a respective switch during a first phase, and the respective gate biased to a first voltage during the first phase, the respective transistor of the second one (1 10b) of the current sense channels connected between the phase node and a ground, the respective calibration resistor connected to the output by a respective switch during a second phase not overlapping in time with the first phase, and the respective gate biased to the first voltage during the second phase, the respective transistor of the third one of the current sense channels connected between a Zero Temperature Coefficient ZTC current source and the ground, and the respective gate biased to the first voltage; a comparator configured to compare the respective calibration voltage of the third sense channel to a target voltage to generate an error voltage; and an Analog to Digital Converter configured to convert the error voltage into the gain coefficient (126, 186), thereby minimizing the error voltage and a difference between the target voltage and each respective calibration voltage, wherein each of the current sense channels (110a, 110b, 170) comprises a transconductance amplifier (112a, 112b, 172) configured to sense the respective transistor voltage, a Multiplying Digital to Analog Converter (118a, 118b, 178), configured to multiply an amplifier output current (114a, 114b, 174) of the transconductance amplifier by the gain coefficient (126, 186) to provide a calibration current (120a, 120b, 180), and the calibration resistor (124b, 124b, 184) is configured to sink the calibration current (120a, 120b, 180) to generate the calibration voltage. a first one (1 10a), a second one (1 10b) and a third one of a plurality of current sense channels configured to multiply a respective transistor voltage sensed across a respective transistor (72, 78, 152) by a gain to generate a respective calibration voltage across a respective resistor (124a, 124b, 184), wherein the gain is determined by a gain coefficient (126, 186), and each respective transistor (72, 78, 152) has a matching temperature coefficient and a respective gate (100, 102, 158), the respective transistor of the first one (1 10a) of the current sense channels connected between a voltage supply and a phase node, the respective calibration resistor connected to an output by a respective switch during a first phase, and the respective gate biased to a first voltage during the first phase, the respective transistor of the second one (1 10b) of the current sense channels connected between the phase node and a ground, the respective calibration resistor connected to the output by a respective switch during a second phase not overlapping in time with the first phase, and the respective gate biased to the first voltage during the second phase, the respective transistor of the third one of the current sense channels connected between a Zero Temperature Coefficient ZTC current source and the ground, and the respective gate biased to the first voltage; a comparator configured to compare the respective calibration voltage of the third sense channel to a target voltage to generate an error voltage; and an Analog to Digital Converter configured to convert the error voltage into the gain coefficient (126, 186), thereby minimizing the error voltage and a difference between the target voltage and each respective calibration voltage, wherein each of the current sense channels (110a, 110b, 170) comprises a transconductance amplifier (112a, 112b, 172) configured to sense the respective transistor voltage, a Multiplying Digital to Analog Converter (118a, 118b, 178), configured to multiply an amplifier output current (114a, 114b, 174) of the transconductance amplifier by the gain coefficient (126, 186) to provide a calibration current (120a, 120b, 180), and the calibration resistor (124b, 124b, 184) is configured to sink the calibration current (120a, 120b, 180) to generate the calibration voltage.