A hardware register on a chip, comprising: a first register set (122, 124, 128) capable of storing a value triple, the value triple comprising a set of data; a packet_id signal signifying membership in a group of the stored set of data relative to a previous set of data and a subsequent set of data; and a valid signal signifying a validity of the stored set of data; a second register set (132, 134, 138) capable of storing another value triple, the other value triple comprising a set of data; a packet_id signal signifying membership in a group of the stored set of data relative to a previous set of data and a subsequent set of data; and a valid signal signifying a validity of the stored set of data; a first device effecting an OR function having: a first input coupled to a negated signal of the valid signal stored in the first register set; a second input coupled to an out_accept signal indicating an ability of a receiving object that is connected to an output of the register to accept data, and an output which generates an update input signal; an additional register structured to store the update input signal and to generate an update output signal that is delayed from the update input signal by one cycle; a second device effecting an OR function having: a first input coupled to a negated signal of the valid signal stored in the second register set, a second input coupled to the update output signal, and an output which generates an in_accept signal indicating the hardware register can receive data; a first set of one or more logic elements structured to cause, when the in_accept signal is asserted, a new value triple from a main input to the hardware register to be loaded into the second register set; and a second set of one or more logic elements (142, 144, 148) structured to cause, when the update input signal is asserted and the in_accept signal is de-asserted, the value triple presently stored in the second register set to be loaded into the first register set, and when the update input signal is asserted and the in_accept signal is asserted, a new value triple from a main input to the hardware register to be loaded into the first register set. a first register set (122, 124, 128) capable of storing a value triple, the value triple comprising a set of data; a packet_id signal signifying membership in a group of the stored set of data relative to a previous set of data and a subsequent set of data; and a valid signal signifying a validity of the stored set of data; a second register set (132, 134, 138) capable of storing another value triple, the other value triple comprising a set of data; a packet_id signal signifying membership in a group of the stored set of data relative to a previous set of data and a subsequent set of data; and a valid signal signifying a validity of the stored set of data; a first device effecting an OR function having: a first input coupled to a negated signal of the valid signal stored in the first register set; a second input coupled to an out_accept signal indicating an ability of a receiving object that is connected to an output of the register to accept data, and an output which generates an update input signal; an additional register structured to store the update input signal and to generate an update output signal that is delayed from the update input signal by one cycle; a second device effecting an OR function having: a first input coupled to a negated signal of the valid signal stored in the second register set, a second input coupled to the update output signal, and an output which generates an in_accept signal indicating the hardware register can receive data; a first set of one or more logic elements structured to cause, when the in_accept signal is asserted, a new value triple from a main input to the hardware register to be loaded into the second register set; and a second set of one or more logic elements (142, 144, 148) structured to cause, when the update input signal is asserted and the in_accept signal is de-asserted, the value triple presently stored in the second register set to be loaded into the first register set, and when the update input signal is asserted and the in_accept signal is asserted, a new value triple from a main input to the hardware register to be loaded into the first register set.