A capacitor, wherein the capacitor comprises: a semiconductor substrate; a layered structure provided above the semiconductor substrate and comprising n-layer conductive layers (1201, 1202, 1203, 1204, 1205) and m-layer dielectric layer(s) (1211, 1212, 1213, 1214, 1215), wherein in the layered structure, an order of the m-layer dielectric layer(s) (1211, 1212, 1213, 1214, 1215) is an ascending order of distances to the semiconductor substrate, and an order of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) is an ascending order of distances to the semiconductor substrate, two adjacent conductive layers of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) are electrically isolated by a dielectric layer of the m-layer dielectric layer(s) (1211, 1212, 1213, 1214, 1215), an i-th conductive layer (1201, 1202, 1203, 1204) of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) is provided with at least one isolation trench (11, 12, 13, 14) penetrating the i-th conductive layer (1201, 1202, 1203, 1204), the i-th conductive layer (1201, 1202, 1203, 1204) is divided into at least two conductive regions electrically isolated from each other by the at least one isolation trench of the i-th conductive layer (1201, 1202, 1203, 1204), the (i+1)-th conductive layer of the n-layer conductive layers is provided above the i-th conductive layer and in the at least one isolation trench of the i-th conductive layer, isolation trenches (11, 13, 15) in odd-numbered conductive layers (1201, 1203, 1205) have a first overlap region in a vertical direction, isolation trenches (12, 14) in even-numbered conductive layers (1202, 1204) have a second overlap region in the vertical direction, and the first overlap region is not overlapping the second overlap region, wherein m, n, and i are positive integers, n≥2, and 1≤i≤n-1; at least one first external electrode being electrically connected to all odd-numbered conductive layer(s) (1201, 1203, 1205) of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) through a first conductive via structure, wherein the first conductive via structure is provided in the second overlap region; and at least one second external electrode being electrically connected to all even-numbered conductive layer(s) (1202, 1204) of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) through a second conductive via structure, wherein the second conductive via structure being provided in the first overlap region. a semiconductor substrate; a layered structure provided above the semiconductor substrate and comprising n-layer conductive layers (1201, 1202, 1203, 1204, 1205) and m-layer dielectric layer(s) (1211, 1212, 1213, 1214, 1215), wherein in the layered structure, an order of the m-layer dielectric layer(s) (1211, 1212, 1213, 1214, 1215) is an ascending order of distances to the semiconductor substrate, and an order of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) is an ascending order of distances to the semiconductor substrate, two adjacent conductive layers of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) are electrically isolated by a dielectric layer of the m-layer dielectric layer(s) (1211, 1212, 1213, 1214, 1215), an i-th conductive layer (1201, 1202, 1203, 1204) of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) is provided with at least one isolation trench (11, 12, 13, 14) penetrating the i-th conductive layer (1201, 1202, 1203, 1204), the i-th conductive layer (1201, 1202, 1203, 1204) is divided into at least two conductive regions electrically isolated from each other by the at least one isolation trench of the i-th conductive layer (1201, 1202, 1203, 1204), the (i+1)-th conductive layer of the n-layer conductive layers is provided above the i-th conductive layer and in the at least one isolation trench of the i-th conductive layer, isolation trenches (11, 13, 15) in odd-numbered conductive layers (1201, 1203, 1205) have a first overlap region in a vertical direction, isolation trenches (12, 14) in even-numbered conductive layers (1202, 1204) have a second overlap region in the vertical direction, and the first overlap region is not overlapping the second overlap region, wherein m, n, and i are positive integers, n≥2, and 1≤i≤n-1; at least one first external electrode being electrically connected to all odd-numbered conductive layer(s) (1201, 1203, 1205) of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) through a first conductive via structure, wherein the first conductive via structure is provided in the second overlap region; and at least one second external electrode being electrically connected to all even-numbered conductive layer(s) (1202, 1204) of the n-layer conductive layers (1201, 1202, 1203, 1204, 1205) through a second conductive via structure, wherein the second conductive via structure being provided in the first overlap region.