Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a first plurality of buffers (20, 40) connected in series along a first clock path having a first input node and a first output node, each of the first plurality of buffers (20, 40) having an input terminal and an output terminal, each input terminal of the buffers of the first plurality of buffers (20, 40) being connected to the first clock path via a corresponding AC coupling capacitor at that input terminal, and the first clock path including the first plurality of buffers (20, 40) and their corresponding AC coupling capacitors configured to receive a first input clock signal at the first input node and output a first output clock signal at the first output node, the first output clock signal having a first output duty cycle; a second plurality of buffers (120, 140) connected in series along a second clock path having a second input node and a second output node, each of the second plurality of buffers (120, 140) having an input terminal and an output terminal, each input terminal of the buffers of the second plurality of buffers (120, 140) being connected to the second clock path via a corresponding AC coupling capacitor at that input terminal, and the second clock path including the second plurality of buffers (120, 140) and their corresponding AC coupling capacitors configured to receive a second input clock signal at the second input node and output a second output clock signal at the second output node, the second output clock signal having a second output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the first plurality of buffers (20, 40) and each of the second plurality of buffers (120, 140), wherein the control circuitry is configured to: obtain a first measurement signal indicative of the first output duty cycle and a second measurement signal indicative of the second output duty cycle; and control the DC bias signals applied to the respective input terminals of the buffers of the first plurality of buffers (20, 40) and of the second plurality of buffers (120, 140), based on a difference between the first and second measurement signals, so as to bring the first and second output duty cycles towards or to one another. a first plurality of buffers (20, 40) connected in series along a first clock path having a first input node and a first output node, each of the first plurality of buffers (20, 40) having an input terminal and an output terminal, each input terminal of the buffers of the first plurality of buffers (20, 40) being connected to the first clock path via a corresponding AC coupling capacitor at that input terminal, and the first clock path including the first plurality of buffers (20, 40) and their corresponding AC coupling capacitors configured to receive a first input clock signal at the first input node and output a first output clock signal at the first output node, the first output clock signal having a first output duty cycle; a second plurality of buffers (120, 140) connected in series along a second clock path having a second input node and a second output node, each of the second plurality of buffers (120, 140) having an input terminal and an output terminal, each input terminal of the buffers of the second plurality of buffers (120, 140) being connected to the second clock path via a corresponding AC coupling capacitor at that input terminal, and the second clock path including the second plurality of buffers (120, 140) and their corresponding AC coupling capacitors configured to receive a second input clock signal at the second input node and output a second output clock signal at the second output node, the second output clock signal having a second output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the first plurality of buffers (20, 40) and each of the second plurality of buffers (120, 140), wherein the control circuitry is configured to: obtain a first measurement signal indicative of the first output duty cycle and a second measurement signal indicative of the second output duty cycle; and control the DC bias signals applied to the respective input terminals of the buffers of the first plurality of buffers (20, 40) and of the second plurality of buffers (120, 140), based on a difference between the first and second measurement signals, so as to bring the first and second output duty cycles towards or to one another. obtain a first measurement signal indicative of the first output duty cycle and a second measurement signal indicative of the second output duty cycle; and control the DC bias signals applied to the respective input terminals of the buffers of the first plurality of buffers (20, 40) and of the second plurality of buffers (120, 140), based on a difference between the first and second measurement signals, so as to bring the first and second output duty cycles towards or to one another.