A device comprising: an address decoding logic component operable to output an enable signal based on an address signal; x bit registers (104, 106, 212, 214, 216, 218, 220, 222) including a first portion and a second portion, each of the x bit registers being operable to store one of x stored bits of data, respectively, the first portion having 0 th through ( x /2 - 1) th bit registers, (104, 106, 212, 214) the second portion having ( x /2) th through ( x -1) th bit registers; (216, 218, 220, 222) x /2 write lines, (410, 412, 414, 416) each of which is operable to provide one of x/2 new bits of data into a corresponding one of the bit registers in the first portion, respectively; x /2 read lines, each of which is operable to output one of the stored bits of data from a corresponding one of the bit registers in the first portion, respectively; x /2 functional components, (204, 206, 208, 210) each of which is operable to provide a modified enable signal to a corresponding one of the bit registers in the first portion, respectively; and a masking component operable to generate x /2 masking signals and to provide one of the x /2 masking signals to a corresponding one the functional components, respectively; wherein each modified enable signal is based on the enable signal and a corresponding masking signal; wherein each of the bit registers in the first portion is operable to modify a stored bit therein, respectively, based on the corresponding modified enable signal, respectively, and wherein x is an integer greater than or equal to 2, wherein each functional component includes an AND gate arranged to receive one of the x /2 masking signals and the enable signal and is operable to output a Boolean AND of the received one of the x /2 masking signals and the enable signal, and further comprising: x /2 additional write lines, (418, 420, 422, 424) each of which is operable to provide one of x /2 additional new bits of data into a corresponding one of the bit registers in the second portion, respectively; wherein the masking component includes x /2 masking lines, (418, 420, 422, 424) each of which is connected to one of the x/2 additional write lines, and each of the x/2 additional write lines is operable to provide a corresponding additional new bit of data to one of the functional components, respectively. an address decoding logic component operable to output an enable signal based on an address signal; x bit registers (104, 106, 212, 214, 216, 218, 220, 222) including a first portion and a second portion, each of the x bit registers being operable to store one of x stored bits of data, respectively, the first portion having 0 th through ( x /2 - 1) th bit registers, (104, 106, 212, 214) the second portion having ( x /2) th through ( x -1) th bit registers; (216, 218, 220, 222) x /2 write lines, (410, 412, 414, 416) each of which is operable to provide one of x/2 new bits of data into a corresponding one of the bit registers in the first portion, respectively; x /2 read lines, each of which is operable to output one of the stored bits of data from a corresponding one of the bit registers in the first portion, respectively; x /2 functional components, (204, 206, 208, 210) each of which is operable to provide a modified enable signal to a corresponding one of the bit registers in the first portion, respectively; and a masking component operable to generate x /2 masking signals and to provide one of the x /2 masking signals to a corresponding one the functional components, respectively; wherein each modified enable signal is based on the enable signal and a corresponding masking signal; wherein each of the bit registers in the first portion is operable to modify a stored bit therein, respectively, based on the corresponding modified enable signal, respectively, and wherein x is an integer greater than or equal to 2, wherein each functional component includes an AND gate arranged to receive one of the x /2 masking signals and the enable signal and is operable to output a Boolean AND of the received one of the x /2 masking signals and the enable signal, and further comprising: x /2 additional write lines, (418, 420, 422, 424) each of which is operable to provide one of x /2 additional new bits of data into a corresponding one of the bit registers in the second portion, respectively; wherein the masking component includes x /2 masking lines, (418, 420, 422, 424) each of which is connected to one of the x/2 additional write lines, and each of the x/2 additional write lines is operable to provide a corresponding additional new bit of data to one of the functional components, respectively.