A method of a master device reading from or writing to a plurality of slave devices connected to a communications bus having a common data line, each slave device having an associated slave device address, the method comprising: providing each of the slave devices with a virtual device address different from any of the slave device addresses; initiating, by the master device, a communication on the bus by signaling a start of the communication via a start symbol immediately followed by the virtual device address on the data line; the slave devices detecting the start of the communication and the virtual device address and, in response, identifying a register from a plurality of registers in that slave device associated with the virtual device address, wherein that slave device stores an association between a respective virtual register address for the virtual device address and the identified register in that slave device, and wherein said identifying a register from a plurality of registers in that slave device comprises reading the association to identify the register, and, each slave device, in sequence, performing a bus read/write operation with regard to its identified register in a respective predetermined time slot within the communication on the data line; and terminating, by the master, the communication by signaling an end of the communication, wherein providing each of the slave devices with the virtual device address comprises the master writing the virtual device address and the respective virtual register address to a designated register in that slave device, and wherein: initiating further includes the master device signaling, following the virtual device address, a virtual device register address on the data line, each slave device contains aliasing data that maps a slave device register address in that slave device to the respective virtual device register address, and identifying a register in that slave device associated with the virtual device address comprises one of the slave devices determining that the virtual device register address on the data line corresponds to the respective virtual device register address mapped to that slave devices' slave device register address, and wherein: the virtual device register addresses are sequential, and each slave device, in sequence, performing a bus read/write operation comprises performing the bus read/write operation in order of the sequence of virtual device register addresses starting with the virtual device register address signaled by the master device on the data line. providing each of the slave devices with a virtual device address different from any of the slave device addresses; initiating, by the master device, a communication on the bus by signaling a start of the communication via a start symbol immediately followed by the virtual device address on the data line; the slave devices detecting the start of the communication and the virtual device address and, in response, identifying a register from a plurality of registers in that slave device associated with the virtual device address, wherein that slave device stores an association between a respective virtual register address for the virtual device address and the identified register in that slave device, and wherein said identifying a register from a plurality of registers in that slave device comprises reading the association to identify the register, and, each slave device, in sequence, performing a bus read/write operation with regard to its identified register in a respective predetermined time slot within the communication on the data line; and identifying a register from a plurality of registers in that slave device associated with the virtual device address, wherein that slave device stores an association between a respective virtual register address for the virtual device address and the identified register in that slave device, and wherein said identifying a register from a plurality of registers in that slave device comprises reading the association to identify the register, and, each slave device, in sequence, performing a bus read/write operation with regard to its identified register in a respective predetermined time slot within the communication on the data line; and terminating, by the master, the communication by signaling an end of the communication, wherein providing each of the slave devices with the virtual device address comprises the master writing the virtual device address and the respective virtual register address to a designated register in that slave device, and wherein: initiating further includes the master device signaling, following the virtual device address, a virtual device register address on the data line, each slave device contains aliasing data that maps a slave device register address in that slave device to the respective virtual device register address, and identifying a register in that slave device associated with the virtual device address comprises one of the slave devices determining that the virtual device register address on the data line corresponds to the respective virtual device register address mapped to that slave devices' slave device register address, and wherein: the virtual device register addresses are sequential, and each slave device, in sequence, performing a bus read/write operation comprises performing the bus read/write operation in order of the sequence of virtual device register addresses starting with the virtual device register address signaled by the master device on the data line.