A method for forming a 3D memory device, comprising: forming an alternating dielectric stack in a contact region on a substrate, the alternating dielectric stack comprising a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked in a vertical direction that is perpendicular to a surface of the substrate; forming a plurality of contact holes (1201, 1201', 1201", 1202, 1202', 1203) with various depths vertically extending in the alternating dielectric stack, the depths of the plurality of contact holes (1201, 1201', 1201", 1202, 1202', 1203) being gradually increased from a first boundary of the contact region toward a second boundary of the contact region; forming a sacrificial-filling layer to fill the contact holes (1201, 1201', 1201", 1202, 1202', 1203); forming a plurality of dummy channel holes penetrating the alternating dielectric stack in the contact region; forming a plurality of channel holes penetrating the alternating dielectric stack in a core array region of the substrate after forming the sacrificial-filling layer, wherein the plurality of channel holes and the plurality of dummy channel holes are formed simultaneously; filling the dummy channel holes with a dielectric material to form supporters, filling the channel holes with composite layers to form memory strings; characterized by replacing the sacrificial layers and the sacrificial-filling layer with conductive layers (164, 168) so as to form a plurality of gate lines (W1, W2, W3) and a plurality of contacts (CT1, CT2, CT3) at the same time; and forming a gate line slit, GLS, in the core array region, wherein the gate line slit vertically extends through the alternating dielectric stack to the substrate. forming an alternating dielectric stack in a contact region on a substrate, the alternating dielectric stack comprising a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked in a vertical direction that is perpendicular to a surface of the substrate; forming a plurality of contact holes (1201, 1201', 1201", 1202, 1202', 1203) with various depths vertically extending in the alternating dielectric stack, the depths of the plurality of contact holes (1201, 1201', 1201", 1202, 1202', 1203) being gradually increased from a first boundary of the contact region toward a second boundary of the contact region; forming a sacrificial-filling layer to fill the contact holes (1201, 1201', 1201", 1202, 1202', 1203); forming a plurality of dummy channel holes penetrating the alternating dielectric stack in the contact region; forming a plurality of channel holes penetrating the alternating dielectric stack in a core array region of the substrate after forming the sacrificial-filling layer, wherein the plurality of channel holes and the plurality of dummy channel holes are formed simultaneously; filling the dummy channel holes with a dielectric material to form supporters, filling the channel holes with composite layers to form memory strings; characterized by replacing the sacrificial layers and the sacrificial-filling layer with conductive layers (164, 168) so as to form a plurality of gate lines (W1, W2, W3) and a plurality of contacts (CT1, CT2, CT3) at the same time; and forming a gate line slit, GLS, in the core array region, wherein the gate line slit vertically extends through the alternating dielectric stack to the substrate.