A system comprising: a memory device configured to sense values of stored data using a reference trim during memory read operations, said memory device being further configured for using the reference trim for adjusting a reference value used for determining whether the stored data correspond to a high data value associated with data "1" or a low data value associated with data "0"; and a memory built-in self-test system configured to prompt the memory device to perform a plurality of the memory read operations with multiple test values for the reference trim, determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data, the system being characterized in that the memory built-in self-test system comprises a trim feedback circuit which is configured to iteratively select the test values for the reference trim using a binary search based, at least in part, on the failures of the memory device to correctly sense the stored data, the trim feedback circuit comprising: a trim mask to receive a trim failure result and to generate a trim bit value based on said trim failure result, wherein said trim bit value corresponds to a bit of a final reference trim for a data type being read from the memory device as part of the binary search; a selection circuit to store the trim bit value to a read zero boundary register or a read one boundary register based on the data type being read from the memory device; a trim aggregator which is configured to merge a reference trim value from the read zero boundary register and the read one boundary register into an aggregate reference trim value; a selection circuit to select a value of the reference trim in between the aggregate reference trim value from the trim aggregator and the trim bit value from the trim mask in response to a final trim signal; and a trim register to store the value of the reference trim from the selection circuit and to provide it to the memory device for use during the memory read operations. a memory device configured to sense values of stored data using a reference trim during memory read operations, said memory device being further configured for using the reference trim for adjusting a reference value used for determining whether the stored data correspond to a high data value associated with data "1" or a low data value associated with data "0"; and a memory built-in self-test system configured to prompt the memory device to perform a plurality of the memory read operations with multiple test values for the reference trim, determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data, the system being characterized in that the memory built-in self-test system comprises a trim feedback circuit which is configured to iteratively select the test values for the reference trim using a binary search based, at least in part, on the failures of the memory device to correctly sense the stored data, the trim feedback circuit comprising: a trim mask to receive a trim failure result and to generate a trim bit value based on said trim failure result, wherein said trim bit value corresponds to a bit of a final reference trim for a data type being read from the memory device as part of the binary search; a selection circuit to store the trim bit value to a read zero boundary register or a read one boundary register based on the data type being read from the memory device; a trim aggregator which is configured to merge a reference trim value from the read zero boundary register and the read one boundary register into an aggregate reference trim value; a selection circuit to select a value of the reference trim in between the aggregate reference trim value from the trim aggregator and the trim bit value from the trim mask in response to a final trim signal; and a trim register to store the value of the reference trim from the selection circuit and to provide it to the memory device for use during the memory read operations. a trim mask to receive a trim failure result and to generate a trim bit value based on said trim failure result, wherein said trim bit value corresponds to a bit of a final reference trim for a data type being read from the memory device as part of the binary search; a selection circuit to store the trim bit value to a read zero boundary register or a read one boundary register based on the data type being read from the memory device; a trim aggregator which is configured to merge a reference trim value from the read zero boundary register and the read one boundary register into an aggregate reference trim value; a selection circuit to select a value of the reference trim in between the aggregate reference trim value from the trim aggregator and the trim bit value from the trim mask in response to a final trim signal; and a trim register to store the value of the reference trim from the selection circuit and to provide it to the memory device for use during the memory read operations.