A digital-to-analog converter, DAC, comprising: first and second switches; a current source (502, 602) configured to push current to a first output (514, 516, 614, 616) through the first switch based on a first signal and a second output (514, 516, 614, 616) through the second switch based on a second signal; and a switch driver configured to receive a data signal and a clock signal, the switch driver comprising a latch and a positive feedback circuitry, the latch comprising a first output node (312a, 412a) for outputting the first signal and a second output node (312b, 412b) for outputting the second signal, the positive feedback circuitry comprising a first inverter having an input coupled to the first output node and an output coupled to the second output node, and a second inverter having an input coupled to the second output node and an output coupled to the first output node; wherein the first and second inverters are coupled to a ground voltage only through a single transistor being a first n-type transistor of the positive feedback circuitry, the first and second output nodes are coupled to a supply voltage only through the inverters of the positive feedback circuitry and through a first p-type transistor of the latch and a second p-type transistor of the latch, respectively, the first and second output nodes are further coupled to an internal node of the latch only through a second n-type transistor of the latch and a third n-type transistor of the latch, respectively, and the internal node is coupled to the ground voltage only through a fourth n-type transistor of the latch, wherein a gate terminal of the first p-type transistor, a gate terminal of the second p-type transistor, a gate terminal of the first n-type transistor and a gate terminal of the fourth n-type transistor are configured to receive the clock signal, wherein the first and second p-type transistors are on when the clock signal is low defining a latch reset phase, and are off when the clock signal is high, wherein the first and fourth n-type transistors are off when the clock signal is low such that the positive feedback circuitry does not burn current during the reset phase, and are on when the clock signal is high, and wherein a gate terminal of the second n-type transistor and a gate terminal of the third n-type transistor are configured to receive the data signal and an inverted version of the data signal, respectively. first and second switches; a current source (502, 602) configured to push current to a first output (514, 516, 614, 616) through the first switch based on a first signal and a second output (514, 516, 614, 616) through the second switch based on a second signal; and a switch driver configured to receive a data signal and a clock signal, the switch driver comprising a latch and a positive feedback circuitry, the latch comprising a first output node (312a, 412a) for outputting the first signal and a second output node (312b, 412b) for outputting the second signal, the positive feedback circuitry comprising a first inverter having an input coupled to the first output node and an output coupled to the second output node, and a second inverter having an input coupled to the second output node and an output coupled to the first output node; wherein the first and second inverters are coupled to a ground voltage only through a single transistor being a first n-type transistor of the positive feedback circuitry, the first and second output nodes are coupled to a supply voltage only through the inverters of the positive feedback circuitry and through a first p-type transistor of the latch and a second p-type transistor of the latch, respectively, the first and second output nodes are further coupled to an internal node of the latch only through a second n-type transistor of the latch and a third n-type transistor of the latch, respectively, and the internal node is coupled to the ground voltage only through a fourth n-type transistor of the latch, wherein a gate terminal of the first p-type transistor, a gate terminal of the second p-type transistor, a gate terminal of the first n-type transistor and a gate terminal of the fourth n-type transistor are configured to receive the clock signal, wherein the first and second p-type transistors are on when the clock signal is low defining a latch reset phase, and are off when the clock signal is high, wherein the first and fourth n-type transistors are off when the clock signal is low such that the positive feedback circuitry does not burn current during the reset phase, and are on when the clock signal is high, and wherein a gate terminal of the second n-type transistor and a gate terminal of the third n-type transistor are configured to receive the data signal and an inverted version of the data signal, respectively.