A device for performing accelerated elliptic curve, EC, point multiplication, comprising - one or more computational blocks for performing a field multiplication, a field addition, field subtraction or a field squaring; - addressable registers; - a bus for data exchange between the blocks and the registers; and - a controller, which is configured to control operation of the computational blocks, the registers and the bus in determining an EC point multiplication result by performing iterations of a main loop operation sequence that comprises - in accordance with an implemented field multiplication algorithm: a sequential calculation of partial products derived from input multiplicands, and an accumulation of the partial products in an internal accumulation register of the computational block for determining the field product of the input multiplicands; and in - read and write accesses to the registers associated with calculating field multiplications, field additions, and/or field subtractions, and/or or field squarings of the respective operands; wherein the controller is further configured to determine for each of the iterations of the main loop operation sequence a respective set of respective dummy clock cycle positions, and to control the computational blocks to perform a partial multiplication of zero-operands in dummy clock cycles corresponding to the respective determined set of respective dummy clock cycle positions for the respective main loop iteration, wherein, for any of the sets that has two or more dummy clock cycle positions within the same main loop iteration, each two of the dummy clock cycle positions are separated from each other by at least one clock cycle of performing a partial multiplication of non-zero operands, and wherein at least two of the sets of the dummy clock cycle positions differ from each other. - one or more computational blocks for performing a field multiplication, a field addition, field subtraction or a field squaring; - addressable registers; - a bus for data exchange between the blocks and the registers; and - a controller, which is configured to control operation of the computational blocks, the registers and the bus in determining an EC point multiplication result by performing iterations of a main loop operation sequence that comprises - in accordance with an implemented field multiplication algorithm: a sequential calculation of partial products derived from input multiplicands, and an accumulation of the partial products in an internal accumulation register of the computational block for determining the field product of the input multiplicands; and in - read and write accesses to the registers associated with calculating field multiplications, field additions, and/or field subtractions, and/or or field squarings of the respective operands; - in accordance with an implemented field multiplication algorithm: a sequential calculation of partial products derived from input multiplicands, and an accumulation of the partial products in an internal accumulation register of the computational block for determining the field product of the input multiplicands; and in - read and write accesses to the registers associated with calculating field multiplications, field additions, and/or field subtractions, and/or or field squarings of the respective operands; wherein the controller is further configured to determine for each of the iterations of the main loop operation sequence a respective set of respective dummy clock cycle positions, and to control the computational blocks to perform a partial multiplication of zero-operands in dummy clock cycles corresponding to the respective determined set of respective dummy clock cycle positions for the respective main loop iteration, wherein, for any of the sets that has two or more dummy clock cycle positions within the same main loop iteration, each two of the dummy clock cycle positions are separated from each other by at least one clock cycle of performing a partial multiplication of non-zero operands, and wherein at least two of the sets of the dummy clock cycle positions differ from each other.