A III-nitride power semiconductor package comprising: a substrate; a III-nitride power semiconductor device (100, 200) including a first high electron mobility transistor (HEMT) (230, 240) comprising: a first III-nitride layer; a second III-nitride layer forming a heterojunction with said first III-nitride layer; a field nitride layer and a gate nitride on said second III-nitride layer; a gate metal on said gate nitride; a plurality of interconnect metal layers (130b, 130c, 130d, 130e) including a top metal layer and a bottom metal layer on said second III-nitride layer, said bottom metal layer including a source contact, a drain contact, and a gate contact on said gate metal; a plurality of vias (132a, 132b, 132c, 132d) interconnecting said plurality of interconnect metal layers (130b, 130c, 130d, 130e) through a plurality of dielectric layers (112a, 112b, 112c) to connect said source contact, said drain contact, and said gate contact to said top metal layer, and, a solderable front metal (140a, 140b) on said top metal layer, said solderable front metal (140a, 140b) comprising spaced elongated digits; solder bars (404, 406) running substantially parallel with said solderable front metal (140a, 140b), said spaced elongated digits being configured for external circuit connection through said solder bars, wherein said solderable front metal (140a, 140b) is coupled to said substrate through said solder bars (404, 406). a substrate; a III-nitride power semiconductor device (100, 200) including a first high electron mobility transistor (HEMT) (230, 240) comprising: a first III-nitride layer; a second III-nitride layer forming a heterojunction with said first III-nitride layer; a field nitride layer and a gate nitride on said second III-nitride layer; a gate metal on said gate nitride; a plurality of interconnect metal layers (130b, 130c, 130d, 130e) including a top metal layer and a bottom metal layer on said second III-nitride layer, said bottom metal layer including a source contact, a drain contact, and a gate contact on said gate metal; a plurality of vias (132a, 132b, 132c, 132d) interconnecting said plurality of interconnect metal layers (130b, 130c, 130d, 130e) through a plurality of dielectric layers (112a, 112b, 112c) to connect said source contact, said drain contact, and said gate contact to said top metal layer, and, a solderable front metal (140a, 140b) on said top metal layer, said solderable front metal (140a, 140b) comprising spaced elongated digits; a first III-nitride layer; a second III-nitride layer forming a heterojunction with said first III-nitride layer; a field nitride layer and a gate nitride on said second III-nitride layer; a gate metal on said gate nitride; a plurality of interconnect metal layers (130b, 130c, 130d, 130e) including a top metal layer and a bottom metal layer on said second III-nitride layer, said bottom metal layer including a source contact, a drain contact, and a gate contact on said gate metal; a plurality of vias (132a, 132b, 132c, 132d) interconnecting said plurality of interconnect metal layers (130b, 130c, 130d, 130e) through a plurality of dielectric layers (112a, 112b, 112c) to connect said source contact, said drain contact, and said gate contact to said top metal layer, and, a solderable front metal (140a, 140b) on said top metal layer, said solderable front metal (140a, 140b) comprising spaced elongated digits; solder bars (404, 406) running substantially parallel with said solderable front metal (140a, 140b), said spaced elongated digits being configured for external circuit connection through said solder bars, wherein said solderable front metal (140a, 140b) is coupled to said substrate through said solder bars (404, 406).