A method of making a TFT substrate for an electronic device, the method comprising: providing a glass substrate, wherein the glass substrate is a soda lime glass substrate; sputter depositing, at low or room temperature, an oxide semiconductor blanket layer, directly or indirectly, on the glass substrate; depositing a gate insulator blanket layer, directly or indirectly, on the oxide semiconductor blanket layer; depositing a gate metal blanket layer, directly or indirectly, on the gate insulator blanket layer; applying a mask over one or more portions of the gate metal blanket layer so as to define one or more corresponding masked areas and one or more corresponding unmasked areas; removing portions of the gate metal blanket layer and portions of the gate insulator blanket layer at or proximate to the one or more unmasked areas; increasing conductivity of the oxide semiconductor layer at or proximate to the one or more unmasked areas; disposing a passivation layer across substantially the entire substrate; patterning the passivation layer so as to define source and drain contact holes (34, 36); and depositing a layer for source and drain connections (38, 40); wherein the substrate with the layers formed thereon is annealed at a temperature of 200 to 250 degrees C following deposition of the source and drain connections, and wherein prior to the annealing, process temperatures do not exceed 150 degrees C. providing a glass substrate, wherein the glass substrate is a soda lime glass substrate; sputter depositing, at low or room temperature, an oxide semiconductor blanket layer, directly or indirectly, on the glass substrate; depositing a gate insulator blanket layer, directly or indirectly, on the oxide semiconductor blanket layer; depositing a gate metal blanket layer, directly or indirectly, on the gate insulator blanket layer; applying a mask over one or more portions of the gate metal blanket layer so as to define one or more corresponding masked areas and one or more corresponding unmasked areas; removing portions of the gate metal blanket layer and portions of the gate insulator blanket layer at or proximate to the one or more unmasked areas; increasing conductivity of the oxide semiconductor layer at or proximate to the one or more unmasked areas; disposing a passivation layer across substantially the entire substrate; patterning the passivation layer so as to define source and drain contact holes (34, 36); and depositing a layer for source and drain connections (38, 40); wherein the substrate with the layers formed thereon is annealed at a temperature of 200 to 250 degrees C following deposition of the source and drain connections, and wherein prior to the annealing, process temperatures do not exceed 150 degrees C. sputter depositing, at low or room temperature, an oxide semiconductor blanket layer, directly or indirectly, on the glass substrate; depositing a gate insulator blanket layer, directly or indirectly, on the oxide semiconductor blanket layer; depositing a gate metal blanket layer, directly or indirectly, on the gate insulator blanket layer; applying a mask over one or more portions of the gate metal blanket layer so as to define one or more corresponding masked areas and one or more corresponding unmasked areas; removing portions of the gate metal blanket layer and portions of the gate insulator blanket layer at or proximate to the one or more unmasked areas; increasing conductivity of the oxide semiconductor layer at or proximate to the one or more unmasked areas; disposing a passivation layer across substantially the entire substrate; patterning the passivation layer so as to define source and drain contact holes (34, 36); and depositing a layer for source and drain connections (38, 40); wherein the substrate with the layers formed thereon is annealed at a temperature of 200 to 250 degrees C following deposition of the source and drain connections, and wherein prior to the annealing, process temperatures do not exceed 150 degrees C.