A memory device comprising: a resistor (155; 355) coupled between a power supply voltage and a terminal; and a plurality of chips (135, 140, 145, 150; 335, 340, 345, 350), wherein each chip comprises: a terminal coupled to the resistor; a calibration circuit configured to determine whether the resistor is available for impedance calibration based, at least in part, on timing information, wherein the timing information of the chip includes a binary code unique to the corresponding chip of the plurality of chips and having a fixed duration common to the plurality of chips, wherein the binary code includes a combination of at least one first period in a first logic state and at least one second period in a second logic state unique to the chip; and wherein the calibration circuit comprises: a driver circuit coupled to the terminal; and an arbiter circuit configured to: enable the driver circuit to change the voltage of the terminal to the second logic state in the at least one second period and further configured to disable the driver circuit to change the voltage of the terminal to the first logic state in the at least one first period before determining whether the resistor is available for impedance calibration, based on the binary code; and determine that the resistor is available for impedance calibration when the voltage of the terminal is at the first logic state in the at least one first period or when the voltage of the terminal is at the second logic state in the at least one second period. a resistor (155; 355) coupled between a power supply voltage and a terminal; and a plurality of chips (135, 140, 145, 150; 335, 340, 345, 350), wherein each chip comprises: a terminal coupled to the resistor; a calibration circuit configured to determine whether the resistor is available for impedance calibration based, at least in part, on timing information, wherein the timing information of the chip includes a binary code unique to the corresponding chip of the plurality of chips and having a fixed duration common to the plurality of chips, wherein the binary code includes a combination of at least one first period in a first logic state and at least one second period in a second logic state unique to the chip; and a terminal coupled to the resistor; a calibration circuit configured to determine whether the resistor is available for impedance calibration based, at least in part, on timing information, wherein the timing information of the chip includes a binary code unique to the corresponding chip of the plurality of chips and having a fixed duration common to the plurality of chips, wherein the binary code includes a combination of at least one first period in a first logic state and at least one second period in a second logic state unique to the chip; and wherein the calibration circuit comprises: a driver circuit coupled to the terminal; and an arbiter circuit configured to: enable the driver circuit to change the voltage of the terminal to the second logic state in the at least one second period and further configured to disable the driver circuit to change the voltage of the terminal to the first logic state in the at least one first period before determining whether the resistor is available for impedance calibration, based on the binary code; and determine that the resistor is available for impedance calibration when the voltage of the terminal is at the first logic state in the at least one first period or when the voltage of the terminal is at the second logic state in the at least one second period. a driver circuit coupled to the terminal; and an arbiter circuit configured to: enable the driver circuit to change the voltage of the terminal to the second logic state in the at least one second period and further configured to disable the driver circuit to change the voltage of the terminal to the first logic state in the at least one first period before determining whether the resistor is available for impedance calibration, based on the binary code; and determine that the resistor is available for impedance calibration when the voltage of the terminal is at the first logic state in the at least one first period or when the voltage of the terminal is at the second logic state in the at least one second period. enable the driver circuit to change the voltage of the terminal to the second logic state in the at least one second period and further configured to disable the driver circuit to change the voltage of the terminal to the first logic state in the at least one first period before determining whether the resistor is available for impedance calibration, based on the binary code; and determine that the resistor is available for impedance calibration when the voltage of the terminal is at the first logic state in the at least one first period or when the voltage of the terminal is at the second logic state in the at least one second period.