A microcontroller comprising: - a central processing unit; - a programmable logic device having inputs receiving external input signals from first external pins (210; I x) and having outputs coupled with second external pins (280; IO x); - an interrupt control unit generating an interrupt signal fed to said CPU, wherein - said programmable logic device comprises an AND array receiving said input signals, wherein the AND array comprises a plurality of subsets of output lines, a plurality of programmable input/output macrocells, wherein each programmable input/output macrocell comprises an OR gate coupled with one of said subsets of output lines of said AND array, wherein an output of the OR gate is coupled with an input of a Flip-Flop, and comprises a multiplexer for selecting an output signal of the OR gate or the Flip-Flop and further comprises a controllable driver (275, 355) coupled between an output of the multiplexer and an associated second external pin; and and wherein each input/output macrocell is programmable to generate an output signal in dependence on at least one signal generated by the associated subset of the AND array and further programmable to provide said AND array with a feedback signal derived from an output signal of said multiplexer; and wherein the interrupt control unit is configured to receive a plurality of said input signals through said first external pins (210; I x) and a plurality of said output signals through said second external pins (280; IO x), wherein said interrupt control unit is further configurable to mask said input signals and said output signals. - a central processing unit; - a programmable logic device having inputs receiving external input signals from first external pins (210; I x) and having outputs coupled with second external pins (280; IO x); - an interrupt control unit generating an interrupt signal fed to said CPU, wherein - said programmable logic device comprises an AND array receiving said input signals, wherein the AND array comprises a plurality of subsets of output lines, a plurality of programmable input/output macrocells, wherein each programmable input/output macrocell comprises an OR gate coupled with one of said subsets of output lines of said AND array, wherein an output of the OR gate is coupled with an input of a Flip-Flop, and comprises a multiplexer for selecting an output signal of the OR gate or the Flip-Flop and further comprises a controllable driver (275, 355) coupled between an output of the multiplexer and an associated second external pin; and and wherein each input/output macrocell is programmable to generate an output signal in dependence on at least one signal generated by the associated subset of the AND array and further programmable to provide said AND array with a feedback signal derived from an output signal of said multiplexer; and an AND array receiving said input signals, wherein the AND array comprises a plurality of subsets of output lines, a plurality of programmable input/output macrocells, wherein each programmable input/output macrocell comprises an OR gate coupled with one of said subsets of output lines of said AND array, wherein an output of the OR gate is coupled with an input of a Flip-Flop, and comprises a multiplexer for selecting an output signal of the OR gate or the Flip-Flop and further comprises a controllable driver (275, 355) coupled between an output of the multiplexer and an associated second external pin; and and wherein each input/output macrocell is programmable to generate an output signal in dependence on at least one signal generated by the associated subset of the AND array and further programmable to provide said AND array with a feedback signal derived from an output signal of said multiplexer; and