A solid-state image pickup apparatus comprising: a pixel unit which is formed on a substrate having a first substrate surface side on which light is incident and a second substrate surface side on which elements are formed and in which a plurality of pixel cells, which are separated by an element separation layer from adjacent pixel groups that have one pixel cell or a plurality of pixel cells as units, are disposed in a matrix; a plurality of first driving lines (LDRN1) disposed corresponding to row arrays of the pixel cells; a second driving line (LDRN2) that is shared between pixel cells on two adjacent rows; a signal line (LSGN) disposed corresponding to a column array of the pixel cells and divided into a first signal line and a second signal line; a signal read processing system processing a read signal of the pixel cells that have been read on the signal line; and a switching unit connecting the first signal line and the second signal line to a power source (SVDD) or the signal read processing system, wherein the pixel cells receive light from the first substrate surface side, include a photoelectric conversion function for the received light and a charge accumulation function, and have a transistor that detects accumulated charge by way of the charge accumulation function and has a threshold modulation function formed therein, the transistor includes a function as a read transistor, a function as a reset transistor, and a function as a select transistor, and has a source (SCNT), a drain (DCNT) and a gate electrode (GCNT) formed on a channel forming region between the source and the drain, the drain or the source is shared between two pixel cells that are adjacent in the row direction of the pixel cells, the source or the drain of one of the pixel cells is connected to the first signal line, and the source or the drain of another of the pixel cells is connected to the second signal line, the gate electrodes of the transistors of the pixel cells are connected to the corresponding first driving lines, and the shared drain or source of two pixel cells that are adjacent in the row direction is connected to a corresponding second driving line. a pixel unit which is formed on a substrate having a first substrate surface side on which light is incident and a second substrate surface side on which elements are formed and in which a plurality of pixel cells, which are separated by an element separation layer from adjacent pixel groups that have one pixel cell or a plurality of pixel cells as units, are disposed in a matrix; a plurality of first driving lines (LDRN1) disposed corresponding to row arrays of the pixel cells; a second driving line (LDRN2) that is shared between pixel cells on two adjacent rows; a signal line (LSGN) disposed corresponding to a column array of the pixel cells and divided into a first signal line and a second signal line; a signal read processing system processing a read signal of the pixel cells that have been read on the signal line; and a switching unit connecting the first signal line and the second signal line to a power source (SVDD) or the signal read processing system, wherein the pixel cells receive light from the first substrate surface side, include a photoelectric conversion function for the received light and a charge accumulation function, and have a transistor that detects accumulated charge by way of the charge accumulation function and has a threshold modulation function formed therein, the transistor includes a function as a read transistor, a function as a reset transistor, and a function as a select transistor, and has a source (SCNT), a drain (DCNT) and a gate electrode (GCNT) formed on a channel forming region between the source and the drain, the drain or the source is shared between two pixel cells that are adjacent in the row direction of the pixel cells, the source or the drain of one of the pixel cells is connected to the first signal line, and the source or the drain of another of the pixel cells is connected to the second signal line, the gate electrodes of the transistors of the pixel cells are connected to the corresponding first driving lines, and the shared drain or source of two pixel cells that are adjacent in the row direction is connected to a corresponding second driving line.