A circuit (100, 200) to extend signal comparison voltage range, the circuit comprising: a latching circuit; a comparator configured to provide an output to the latching circuit responsive to common-mode input signals, the comparator coupled to the latching circuit and to a dynamic node having a dynamic voltage; and a clocked boost circuit coupled to the dynamic node having the dynamic voltage and configured to extend a supply voltage range of the comparator via biasing the dynamic node, which has the dynamic voltage, wherein the clocked boost circuit includes: an inverter coupled between a voltage supply and ground, wherein the inverter is responsive to a clock signal and wherein an output of the inverter is coupled to the first terminal of a capacitor, wherein a second terminal of the capacitor is coupled to the dynamic node; and a switch responsive to an inverted clock signal and configured to selectively couple the second terminal of the capacitor to ground; and wherein the dynamic node having the dynamic voltage provides a ground reference of the comparator; and wherein the comparator comprises: a first transistor coupled to the dynamic node having the dynamic voltage and responsive to a first input signal; and a second transistor coupled to the dynamic node having the dynamic voltage and responsive to a second input signal, wherein an output of the comparator indicates whether a first discharge rate through the first transistor to the ground reference exceeds a second discharge rate through the second transistor to the ground reference; wherein the latching circuit comprises a pre-charge circuit coupled to the comparator such that the pre-charge circuit charges first and second pre-charge nodes to a pre-charge level during a reset phase, said first and second pre-charge nodes being coupled to the drain terminals of the first and second transistors, respectively, and forming the output of the comparator; and wherein the latching circuit further comprises a pair of cross-coupled inverters, each cross-coupled inverter comprising a first PMOS transistor and a first NMOS transistor connected in series in a CMOS inverter configuration and a third PMOS transistor coupled in series between said first PMOS and NMOS transistors, a gate of said third PMOS transistor coupled to a corresponding pre-charge node. a latching circuit; a comparator configured to provide an output to the latching circuit responsive to common-mode input signals, the comparator coupled to the latching circuit and to a dynamic node having a dynamic voltage; and a clocked boost circuit coupled to the dynamic node having the dynamic voltage and configured to extend a supply voltage range of the comparator via biasing the dynamic node, which has the dynamic voltage, wherein the clocked boost circuit includes: an inverter coupled between a voltage supply and ground, wherein the inverter is responsive to a clock signal and wherein an output of the inverter is coupled to the first terminal of a capacitor, wherein a second terminal of the capacitor is coupled to the dynamic node; and a switch responsive to an inverted clock signal and configured to selectively couple the second terminal of the capacitor to ground; and an inverter coupled between a voltage supply and ground, wherein the inverter is responsive to a clock signal and wherein an output of the inverter is coupled to the first terminal of a capacitor, wherein a second terminal of the capacitor is coupled to the dynamic node; and a switch responsive to an inverted clock signal and configured to selectively couple the second terminal of the capacitor to ground; and a first transistor coupled to the dynamic node having the dynamic voltage and responsive to a first input signal; and a second transistor coupled to the dynamic node having the dynamic voltage and responsive to a second input signal, wherein an output of the comparator indicates whether a first discharge rate through the first transistor to the ground reference exceeds a second discharge rate through the second transistor to the ground reference;