Photonic chip lying essentially in a plane called the "plane of the chip", this photonic chip comprising: - a substrate having an upper face and a lower face that are parallel to the plane of the chip, this substrate comprising, between the upper and lower faces: • an interconnection layer of thickness larger than 50 μm, this interconnection layer being devoid of optical components, • an optical layer (38; 202) bonded, at a bonding interface, to the interconnection layer, • at least one optical component (70, 72; 256) buried in the interior of the optical layer (38; 202), • an electrical terminal chosen from the group consisting of an electrical contact (74; 212; 264) embedded in the interior of the optical layer (38; 202), this embedded electrical contact being that of the optical component or of an electronic component, and of an electrical track (106, 108; 276, 280) produced on the upper face of the substrate, - electrical connection pads produced on the lower face of the substrate, each of these pads being able to be electrically connected by way of a solder bump to another carrier, - a primary via extending through the interconnection layer from the lower face in order to electrically connect one of the connection pads to the electrical terminal, this primary via having a diameter larger than or equal to 10 μm, characterized in that: - the thickness of the optical layer (38; 202) is smaller than 15 μm, - the primary via extends through the interconnection layer solely between the lower face and the bonding interface so that the primary via does not extend into the interior of the optical layer (38; 202), and - the photonic chip comprises a secondary via (100, 102, 130; 204; 252, 254, 258) that extends the primary via into the interior of the optical layer in order to electrically connect the primary via to the electrical terminal, this secondary via extending in the interior of the optical layer (38; 202) from the bonding interface to the electrical terminal, the maximum diameter of this secondary via being smaller than 3 μm. - a substrate having an upper face and a lower face that are parallel to the plane of the chip, this substrate comprising, between the upper and lower faces: • an interconnection layer of thickness larger than 50 μm, this interconnection layer being devoid of optical components, • an optical layer (38; 202) bonded, at a bonding interface, to the interconnection layer, • at least one optical component (70, 72; 256) buried in the interior of the optical layer (38; 202), • an electrical terminal chosen from the group consisting of an electrical contact (74; 212; 264) embedded in the interior of the optical layer (38; 202), this embedded electrical contact being that of the optical component or of an electronic component, and of an electrical track (106, 108; 276, 280) produced on the upper face of the substrate, • an interconnection layer of thickness larger than 50 μm, this interconnection layer being devoid of optical components, • an optical layer (38; 202) bonded, at a bonding interface, to the interconnection layer, • at least one optical component (70, 72; 256) buried in the interior of the optical layer (38; 202), • an electrical terminal chosen from the group consisting of an electrical contact (74; 212; 264) embedded in the interior of the optical layer (38; 202), this embedded electrical contact being that of the optical component or of an electronic component, and of an electrical track (106, 108; 276, 280) produced on the upper face of the substrate, - electrical connection pads produced on the lower face of the substrate, each of these pads being able to be electrically connected by way of a solder bump to another carrier, - a primary via extending through the interconnection layer from the lower face in order to electrically connect one of the connection pads to the electrical terminal, this primary via having a diameter larger than or equal to 10 μm, - the thickness of the optical layer (38; 202) is smaller than 15 μm, - the primary via extends through the interconnection layer solely between the lower face and the bonding interface so that the primary via does not extend into the interior of the optical layer (38; 202), and - the photonic chip comprises a secondary via (100, 102, 130; 204; 252, 254, 258) that extends the primary via into the interior of the optical layer in order to electrically connect the primary via to the electrical terminal, this secondary via extending in the interior of the optical layer (38; 202) from the bonding interface to the electrical terminal, the maximum diameter of this secondary via being smaller than 3 μm.