An apparatus comprising: a group of data cells; and a reference cell coupled to the group of data cells, wherein the reference cell comprises: a first magnetic tunnel junction, MTJ, cell comprising a first MTJ element and a first transistor, a second MTJ cell comprising a second MTJ element and a second transistor, wherein the first MTJ element and the second MTJ element are connected to a first common node; wherein the first transistor is connected in series between the first MTJ element and a second common node, and the second transistor is connected in series between the second MTJ element and the second common node; a third MTJ cell comprising a third MTJ element and a third transistor,a fourth MTJ cell comprising a fourth MTJ element and a fourth transistor, wherein the third MTJ element and the fourth MTJ element are connected to the second common node; wherein the third transistor is connected in series between the third MTJ element and a third common node, and the fourth transistor is connected in series between the fourth MTJ element and the third common node;wherein each gate of the first, second, third and fourth transistors is coupled to a distinct word line (106, 108, 110, 112);wherein each of the four transistors (126, 230, 232, 234) is configured to enable read access to the corresponding MTJ element (124, 202, 204, 206); and wherein the first, second, third and fourth MTJ elements store the same logic state. a group of data cells; and a reference cell coupled to the group of data cells, wherein the reference cell comprises: a first magnetic tunnel junction, MTJ, cell comprising a first MTJ element and a first transistor, a second MTJ cell comprising a second MTJ element and a second transistor, wherein the first MTJ element and the second MTJ element are connected to a first common node; wherein the first transistor is connected in series between the first MTJ element and a second common node, and the second transistor is connected in series between the second MTJ element and the second common node; a third MTJ cell comprising a third MTJ element and a third transistor,a fourth MTJ cell comprising a fourth MTJ element and a fourth transistor, wherein the third MTJ element and the fourth MTJ element are connected to the second common node; wherein the third transistor is connected in series between the third MTJ element and a third common node, and the fourth transistor is connected in series between the fourth MTJ element and the third common node;wherein each gate of the first, second, third and fourth transistors is coupled to a distinct word line (106, 108, 110, 112);wherein each of the four transistors (126, 230, 232, 234) is configured to enable read access to the corresponding MTJ element (124, 202, 204, 206); and wherein the first, second, third and fourth MTJ elements store the same logic state. a first magnetic tunnel junction, MTJ, cell comprising a first MTJ element and a first transistor, a second MTJ cell comprising a second MTJ element and a second transistor, wherein the first MTJ element and the second MTJ element are connected to a first common node; wherein the first transistor is connected in series between the first MTJ element and a second common node, and the second transistor is connected in series between the second MTJ element and the second common node; a third MTJ cell comprising a third MTJ element and a third transistor,a fourth MTJ cell comprising a fourth MTJ element and a fourth transistor, wherein the third MTJ element and the fourth MTJ element are connected to the second common node; wherein the third transistor is connected in series between the third MTJ element and a third common node, and the fourth transistor is connected in series between the fourth MTJ element and the third common node;wherein each gate of the first, second, third and fourth transistors is coupled to a distinct word line (106, 108, 110, 112);wherein each of the four transistors (126, 230, 232, 234) is configured to enable read access to the corresponding MTJ element (124, 202, 204, 206); and wherein the first, second, third and fourth MTJ elements store the same logic state.