A cache (30, 130) comprising: means (38,40) for storing a plurality of data blocks; and characterised by: means for selectively changing a line width for the cache, the means for selectively changing a line width comprising a width unit for storing a currently selected line width, the width unit comprising a width register for storing the currently selected line width; the cache being adapted to store, for each data block of the plurality of data blocks, a value representing the line width stored in the width register when each data block was written, so that it can be determined with which line width the data block was written; means for providing a main memory address to the cache; an address unit for generating a lookup (37, 137), the lookup based on the main memory address and the currently selected line width; means for transferring data from at least one of the plurality of data blocks using the main memory address and the lookup; and the cache being operable to manage one or more data blocks of the plurality of data blocks in one or more ways as a single data block, based on the currently selected line width and the value stored for each data block. means (38,40) for storing a plurality of data blocks; and characterised by: means for selectively changing a line width for the cache, the means for selectively changing a line width comprising a width unit for storing a currently selected line width, the width unit comprising a width register for storing the currently selected line width; the cache being adapted to store, for each data block of the plurality of data blocks, a value representing the line width stored in the width register when each data block was written, so that it can be determined with which line width the data block was written; means for providing a main memory address to the cache; an address unit for generating a lookup (37, 137), the lookup based on the main memory address and the currently selected line width; means for transferring data from at least one of the plurality of data blocks using the main memory address and the lookup; and the cache being operable to manage one or more data blocks of the plurality of data blocks in one or more ways as a single data block, based on the currently selected line width and the value stored for each data block. means for selectively changing a line width for the cache, the means for selectively changing a line width comprising a width unit for storing a currently selected line width, the width unit comprising a width register for storing the currently selected line width; the cache being adapted to store, for each data block of the plurality of data blocks, a value representing the line width stored in the width register when each data block was written, so that it can be determined with which line width the data block was written; means for providing a main memory address to the cache; an address unit for generating a lookup (37, 137), the lookup based on the main memory address and the currently selected line width; means for transferring data from at least one of the plurality of data blocks using the main memory address and the lookup; and the cache being operable to manage one or more data blocks of the plurality of data blocks in one or more ways as a single data block, based on the currently selected line width and the value stored for each data block.