A thin film transistor for a display apparatus, the TFT (100; 500) comprising: an active layer (110; 510; 570) disposed on a substrate; a first gate electrode (120; 520; 560) disposed on a side of the active layer opposite to the side facing the substrate to overlap the active layer, the first gate electrode having a plurality of lines (520a, 520b; 560a, 560b); a gate insulator (150; 550) disposed between the active layer and the first gate electrode and over parts of the active layer (110; 510; 570) not overlapping the first gate electrode (120; 520; 560); and a source electrode (130; 530) and a drain electrode (140; 540) respectively disposed at both ends of the active layer and in parallel to a direction of the plurality of lines of the first gate electrode (120; 520; 560), wherein a plurality of groups of electrical contacts are disposed between the active layer (110; 510; 570) and the source electrode (130; 530), and between the active layer (110; 510; 570) and the drain electrode (140; 540), respectively, such that areas free of contacts are disposed between the groups of electrical contacts, wherein the active layer (110; 510: 570) comprises: a plurality of channel areas (112; 512; 572) disposed between the source electrode (130; 530) and the drain electrode (140; 540) in areas where the electrical contacts to the active layer (110; 510; 570) are formed; one or more dummy areas (114; 514; 574), a length of each of the one or more dummy areas extending from an edge of a corresponding channel area (112; 512; 572) to a side where no adjacent channel area (112; 512; 572) is disposed; and a plurality of link areas (116; 516; 576) disposed between the plurality of channel areas (112; 512; 572) to connect the plurality of channel areas in one pattern, characterized in that the active layer (110; 510; 570) extends over the first gate electrode (120; 520; 560) in the direction of the plurality of lines of the first gate electrode (120; 520; 560). an active layer (110; 510; 570) disposed on a substrate; a first gate electrode (120; 520; 560) disposed on a side of the active layer opposite to the side facing the substrate to overlap the active layer, the first gate electrode having a plurality of lines (520a, 520b; 560a, 560b); a gate insulator (150; 550) disposed between the active layer and the first gate electrode and over parts of the active layer (110; 510; 570) not overlapping the first gate electrode (120; 520; 560); and a source electrode (130; 530) and a drain electrode (140; 540) respectively disposed at both ends of the active layer and in parallel to a direction of the plurality of lines of the first gate electrode (120; 520; 560), wherein a plurality of groups of electrical contacts are disposed between the active layer (110; 510; 570) and the source electrode (130; 530), and between the active layer (110; 510; 570) and the drain electrode (140; 540), respectively, such that areas free of contacts are disposed between the groups of electrical contacts, wherein the active layer (110; 510: 570) comprises: a plurality of channel areas (112; 512; 572) disposed between the source electrode (130; 530) and the drain electrode (140; 540) in areas where the electrical contacts to the active layer (110; 510; 570) are formed; one or more dummy areas (114; 514; 574), a length of each of the one or more dummy areas extending from an edge of a corresponding channel area (112; 512; 572) to a side where no adjacent channel area (112; 512; 572) is disposed; and a plurality of link areas (116; 516; 576) disposed between the plurality of channel areas (112; 512; 572) to connect the plurality of channel areas in one pattern, characterized in that a plurality of channel areas (112; 512; 572) disposed between the source electrode (130; 530) and the drain electrode (140; 540) in areas where the electrical contacts to the active layer (110; 510; 570) are formed; one or more dummy areas (114; 514; 574), a length of each of the one or more dummy areas extending from an edge of a corresponding channel area (112; 512; 572) to a side where no adjacent channel area (112; 512; 572) is disposed; and a plurality of link areas (116; 516; 576) disposed between the plurality of channel areas (112; 512; 572) to connect the plurality of channel areas in one pattern, characterized in that