A computational storage device comprising: a non-volatile memory device; and a storage controller (CTRL) configured to control the non-volatile memory device, the storage controller (CTRL) comprising: a computation engine configured to execute an internal application (APP_i) for issuing an internal input/output (I/O) through an internal file system (FS_i) for organizing the internal I/O, and an internal driver (DR_i) generating an internal command (CMD_i) based on the organized internal I/O; a host interface block configured to receive a host command (CMD_h) from an external host driver (DR_h) of an external host device, to receive the internal command (CMD_i) from the computation engine, and to individually process the received host command (CMD_h) and the received internal command (CMD_i); a flash translation layer configured to perform an address mapping operation based on a result of the processing of the host interface block; a memory interface block configured to control the non-volatile memory device based on the address mapping operation of the flash translation layer; and a system bus, wherein the computation engine, the host interface block, the flash translation layer, and the memory interface block communicate with each other through the system bus, wherein the host interface block is configured to communicate with the external host device based on a first interface and to communicate with the computation engine based on a second interface, and wherein the first interface is a non-volatile memory express, NVMe, interface, and the second interface is an interface which is implemented by virtualizing the NVMe interface on the system bus. a non-volatile memory device; and a storage controller (CTRL) configured to control the non-volatile memory device, the storage controller (CTRL) comprising: a computation engine configured to execute an internal application (APP_i) for issuing an internal input/output (I/O) through an internal file system (FS_i) for organizing the internal I/O, and an internal driver (DR_i) generating an internal command (CMD_i) based on the organized internal I/O; a host interface block configured to receive a host command (CMD_h) from an external host driver (DR_h) of an external host device, to receive the internal command (CMD_i) from the computation engine, and to individually process the received host command (CMD_h) and the received internal command (CMD_i); a flash translation layer configured to perform an address mapping operation based on a result of the processing of the host interface block; a memory interface block configured to control the non-volatile memory device based on the address mapping operation of the flash translation layer; and a system bus, wherein the computation engine, the host interface block, the flash translation layer, and the memory interface block communicate with each other through the system bus, wherein the host interface block is configured to communicate with the external host device based on a first interface and to communicate with the computation engine based on a second interface, and wherein the first interface is a non-volatile memory express, NVMe, interface, and the second interface is an interface which is implemented by virtualizing the NVMe interface on the system bus. a computation engine configured to execute an internal application (APP_i) for issuing an internal input/output (I/O) through an internal file system (FS_i) for organizing the internal I/O, and an internal driver (DR_i) generating an internal command (CMD_i) based on the organized internal I/O; a host interface block configured to receive a host command (CMD_h) from an external host driver (DR_h) of an external host device, to receive the internal command (CMD_i) from the computation engine, and to individually process the received host command (CMD_h) and the received internal command (CMD_i); a flash translation layer configured to perform an address mapping operation based on a result of the processing of the host interface block; a memory interface block configured to control the non-volatile memory device based on the address mapping operation of the flash translation layer; and a system bus, wherein the computation engine, the host interface block, the flash translation layer, and the memory interface block communicate with each other through the system bus, wherein the host interface block is configured to communicate with the external host device based on a first interface and to communicate with the computation engine based on a second interface, and wherein the first interface is a non-volatile memory express, NVMe, interface, and the second interface is an interface which is implemented by virtualizing the NVMe interface on the system bus.