A method of forming a memory device, comprising: providing a semiconductor substrate having a memory region that is P type, a first logic region that is P type and a second logic region that is N type; forming a pair of spaced apart floating gates in the memory region; forming a pair of control gates in the memory region, wherein each control gate has a first portion adjacent to one of the floating gates and a second portion that extends up and over one of the floating gates; forming a first logic gate in the first logic region; forming a second logic gate in the second logic region; forming a first photo resist that covers the second logic region and portions of the substrate adjacent to the control gates in the memory region, but not the first logic region and not a portion of the substrate between the pair of floating gates; performing a first implantation that is an N type implantation that forms a source region in the substrate between the pair of floating gates, a source region in the substrate adjacent a first side of the first logic gate, and a drain region in the substrate adjacent a second side of the first logic gate opposite the first side of the first logic gate; removing the first photo resist; forming a second photo resist that covers the first logic region and the memory region, but not the second logic region; performing a second implantation that is an P type implantation that forms a source region in the substrate adjacent a first side of the second logic gate and a drain region in the substrate adjacent a second side of the second logic gate opposite the first side of the second logic gate; removing the second photo resist; forming a third photo resist that covers the second logic region, but not the memory region and not the first logic region; performing a third implantation that is an N+ type implantation that forms drain regions in the substrate adjacent the control gates; wherein the third implantation enhances the source region in the memory region and enhances the source region and the drain region adjacent the first logic gate; removing the third photo resist; forming a fourth photo resist that covers the first logic region and the memory region, but not the second logic region; performing a fourth implantation that is an P+ type implantation that enhances the source region in the substrate adjacent the first side of the second logic gate and enhances the drain region in the substrate adjacent the second side of the second logic gate. providing a semiconductor substrate having a memory region that is P type, a first logic region that is P type and a second logic region that is N type; forming a pair of spaced apart floating gates in the memory region; forming a pair of control gates in the memory region, wherein each control gate has a first portion adjacent to one of the floating gates and a second portion that extends up and over one of the floating gates; forming a first logic gate in the first logic region; forming a second logic gate in the second logic region; forming a first photo resist that covers the second logic region and portions of the substrate adjacent to the control gates in the memory region, but not the first logic region and not a portion of the substrate between the pair of floating gates; performing a first implantation that is an N type implantation that forms a source region in the substrate between the pair of floating gates, a source region in the substrate adjacent a first side of the first logic gate, and a drain region in the substrate adjacent a second side of the first logic gate opposite the first side of the first logic gate; removing the first photo resist; forming a second photo resist that covers the first logic region and the memory region, but not the second logic region; performing a second implantation that is an P type implantation that forms a source region in the substrate adjacent a first side of the second logic gate and a drain region in the substrate adjacent a second side of the second logic gate opposite the first side of the second logic gate; removing the second photo resist; forming a third photo resist that covers the second logic region, but not the memory region and not the first logic region; performing a third implantation that is an N+ type implantation that forms drain regions in the substrate adjacent the control gates; wherein the third implantation enhances the source region in the memory region and enhances the source region and the drain region adjacent the first logic gate; removing the third photo resist; forming a fourth photo resist that covers the first logic region and the memory region, but not the second logic region; performing a fourth implantation that is an P+ type implantation that enhances the source region in the substrate adjacent the first side of the second logic gate and enhances the drain region in the substrate adjacent the second side of the second logic gate.