A semiconductor memory device, comprising: a memory cell array including plural first lines, plural second lines intersecting said first lines, and plural memory cells provided at the intersections of said plural first lines and said plural second lines and operative to store data in accordance with different resistance states; and a write circuit operative to execute a write operation to a data-write-targeted, selected memory cell of said plural memory cells, said memory cell having a set operation for changing said resistance state from the first resistance state to the second resistance state on application of a set voltage of the first polarity between said first and second lines, and a reset operation for changing said resistance state from the second resistance state to the first resistance state on application of a reset voltage of the second polarity between said first and second lines, the second polarity being opposite in polarity to the first polarity, and said write circuit, on execution of said write operation, executing a first step of applying a voltage across said first and second lines connected to said selected memory cell, and a different voltage across said first and second lines connected to a data-write-untargeted, unselected memory cell of said plural memory cells and, after execution of said first step, executing a second step of applying a voltage, required for data write, across said first and second lines connected to said selected memory cell, and bringing at least one of said first and second lines connected to said unselected memory cell into the floating state, wherein the potentials on said first and second lines connected to said selected memory cell are denoted with U1 and V1, respectively, and the potentials on said first and second lines connected to said unselected memory cell are denoted with U and V, respectively, said write circuit, on said write operation for subjecting said memory cell to set operation, executes said first step on condition that V - U > V1 - U1, or said write circuit, on said write operation for subjecting said memory cell to reset operation, executes said first step on condition that V1 - U1 > V - U. a memory cell array including plural first lines, plural second lines intersecting said first lines, and plural memory cells provided at the intersections of said plural first lines and said plural second lines and operative to store data in accordance with different resistance states; and a write circuit operative to execute a write operation to a data-write-targeted, selected memory cell of said plural memory cells, said memory cell having a set operation for changing said resistance state from the first resistance state to the second resistance state on application of a set voltage of the first polarity between said first and second lines, and a reset operation for changing said resistance state from the second resistance state to the first resistance state on application of a reset voltage of the second polarity between said first and second lines, the second polarity being opposite in polarity to the first polarity, and said write circuit, on execution of said write operation, executing a first step of applying a voltage across said first and second lines connected to said selected memory cell, and a different voltage across said first and second lines connected to a data-write-untargeted, unselected memory cell of said plural memory cells and, after execution of said first step, executing a second step of applying a voltage, required for data write, across said first and second lines connected to said selected memory cell, and bringing at least one of said first and second lines connected to said unselected memory cell into the floating state, wherein the potentials on said first and second lines connected to said selected memory cell are denoted with U1 and V1, respectively, and the potentials on said first and second lines connected to said unselected memory cell are denoted with U and V, respectively, said write circuit, on said write operation for subjecting said memory cell to set operation, executes said first step on condition that V - U > V1 - U1, or said write circuit, on said write operation for subjecting said memory cell to reset operation, executes said first step on condition that V1 - U1 > V - U.