A parallel processing unit (100, 600, 900) comprising: a counter block (102, 106) comprising a plurality of counters, the plurality of counters comprising a group of low latency counters associated with low latency data hazards; a plurality of queues (110, 610, 910), each queue (110, 610, 910) preceding one instruction pipeline of a plurality of instruction pipelines and in communication with the counter block (102, 106); an instruction decoder (104, 604, 904) configured to: decode a received instruction; in response to determining the decoded instruction is a primary instruction from which at least one other instruction is dependent on, cause a value of a counter of the plurality of counters of the counter block (102, 106) associated with the primary instruction to be adjusted to indicate that there is a hazard related to the primary instruction; and forward the decoded instruction to one of the plurality of queues (110, 610, 910); and monitor logic configured to monitor the plurality of instruction pipelines, and in response to detecting that an instruction pipeline has resolved a hazard related to a primary instruction, cause the value of the counter associated with the primary instruction to be adjusted to indicate that the hazard related to the primary instruction has been resolved; wherein each queue (110, 610, 910) is configured to, in response to receiving a secondary instruction that is dependent on one or more primary instructions, stall execution of the secondary instruction by the associated instruction pipeline if a low latency counter of the plurality of counters of the counter block (102, 106) associated with a primary instruction from which the secondary instruction depends indicates that there is a hazard related to that primary instruction; wherein a low latency data hazard is a data hazard in which the primary instruction of the data hazard is to be executed by an instruction pipeline of the plurality of instruction pipelines with a throughput above, or equal to, a predetermined threshold. a counter block (102, 106) comprising a plurality of counters, the plurality of counters comprising a group of low latency counters associated with low latency data hazards; a plurality of queues (110, 610, 910), each queue (110, 610, 910) preceding one instruction pipeline of a plurality of instruction pipelines and in communication with the counter block (102, 106); an instruction decoder (104, 604, 904) configured to: decode a received instruction; in response to determining the decoded instruction is a primary instruction from which at least one other instruction is dependent on, cause a value of a counter of the plurality of counters of the counter block (102, 106) associated with the primary instruction to be adjusted to indicate that there is a hazard related to the primary instruction; and forward the decoded instruction to one of the plurality of queues (110, 610, 910); and decode a received instruction; in response to determining the decoded instruction is a primary instruction from which at least one other instruction is dependent on, cause a value of a counter of the plurality of counters of the counter block (102, 106) associated with the primary instruction to be adjusted to indicate that there is a hazard related to the primary instruction; and forward the decoded instruction to one of the plurality of queues (110, 610, 910); and monitor logic configured to monitor the plurality of instruction pipelines, and in response to detecting that an instruction pipeline has resolved a hazard related to a primary instruction, cause the value of the counter associated with the primary instruction to be adjusted to indicate that the hazard related to the primary instruction has been resolved; wherein each queue (110, 610, 910) is configured to, in response to receiving a secondary instruction that is dependent on one or more primary instructions, stall execution of the secondary instruction by the associated instruction pipeline if a low latency counter of the plurality of counters of the counter block (102, 106) associated with a primary instruction from which the secondary instruction depends indicates that there is a hazard related to that primary instruction; wherein a low latency data hazard is a data hazard in which the primary instruction of the data hazard is to be executed by an instruction pipeline of the plurality of instruction pipelines with a throughput above, or equal to, a predetermined threshold.