A voltage regulator circuit, comprising: an input node configured to receive an input supply voltage ( V CC); an output node configured to produce a regulated output voltage ( V REG); a first feedback network (R1, 412, 414) configured to produce a feedback signal indicative of said regulated output voltage ( V REG), and compare said feedback signal to a reference signal (VREF) to produce a first pulsed control signal ( COMP_OUT), wherein the first pulsed control signal ( COMP_OUT) is asserted in response to the reference signal ( VREF) being higher than the feedback signal and de-asserted in response to the reference signal ( VREF) being lower than the feedback signal, whereby a time-averaged value of said first pulsed control signal (COMP_OUT) is a function of the difference between said reference signal (VREF) and said feedback signal; a second feedback network (R2, 418, 420) configured to produce a threshold signal indicative of said input supply voltage ( V CC), and compare said regulated output voltage ( V REG) to said threshold signal to produce a second control signal ( VCC_EN), wherein the second control signal ( VCC_EN) is asserted in response to the threshold signal being higher than the regulated output voltage ( V REG) and de-asserted in response to the threshold signal being lower than the regulated output voltage ( V REG); a charge pump circuit configured to produce a supply voltage ( V BL_SUPPLY) higher than said input supply voltage ( V CC), wherein the charge pump circuit is enabled ( PMP_EN) in response to said second control signal ( VCC_EN) being de-asserted and is clocked by said first pulsed control signal ( COMP_OUT), whereby the value of said supply voltage ( V BL_SUPPLY) is a function of said first pulsed control signal ( COMP_OUT); a first pass element arranged between the input node and the output node, wherein the first pass element is enabled in response to said second control signal ( VCC_EN) being asserted and is selectively activated to connect the input node to the output node in response to said first pulsed control signal (COMP_OUT) being asserted; and a second pass element arranged between the output of said charge pump circuit and the output node, wherein the second pass element is selectively activated to connect the output of the charge pump circuit to the output node in response to said second control signal ( VCC_EN) being de-asserted. an input node configured to receive an input supply voltage ( V CC); an output node configured to produce a regulated output voltage ( V REG); a first feedback network (R1, 412, 414) configured to produce a feedback signal indicative of said regulated output voltage ( V REG), and compare said feedback signal to a reference signal (VREF) to produce a first pulsed control signal ( COMP_OUT), wherein the first pulsed control signal ( COMP_OUT) is asserted in response to the reference signal ( VREF) being higher than the feedback signal and de-asserted in response to the reference signal ( VREF) being lower than the feedback signal, whereby a time-averaged value of said first pulsed control signal (COMP_OUT) is a function of the difference between said reference signal (VREF) and said feedback signal; a second feedback network (R2, 418, 420) configured to produce a threshold signal indicative of said input supply voltage ( V CC), and compare said regulated output voltage ( V REG) to said threshold signal to produce a second control signal ( VCC_EN), wherein the second control signal ( VCC_EN) is asserted in response to the threshold signal being higher than the regulated output voltage ( V REG) and de-asserted in response to the threshold signal being lower than the regulated output voltage ( V REG); a charge pump circuit configured to produce a supply voltage ( V BL_SUPPLY) higher than said input supply voltage ( V CC), wherein the charge pump circuit is enabled ( PMP_EN) in response to said second control signal ( VCC_EN) being de-asserted and is clocked by said first pulsed control signal ( COMP_OUT), whereby the value of said supply voltage ( V BL_SUPPLY) is a function of said first pulsed control signal ( COMP_OUT); a first pass element arranged between the input node and the output node, wherein the first pass element is enabled in response to said second control signal ( VCC_EN) being asserted and is selectively activated to connect the input node to the output node in response to said first pulsed control signal (COMP_OUT) being asserted; and a second pass element arranged between the output of said charge pump circuit and the output node, wherein the second pass element is selectively activated to connect the output of the charge pump circuit to the output node in response to said second control signal ( VCC_EN) being de-asserted.