An ion-sensitive circuit, comprising: a charge-accumulation device to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, including: a first charge control electrode, above a first electrode semiconductor region, to control entry of charge into a gate semiconductor region in response to a first control signal applied to the first electrode; and an electrically floating gate structure above the gate semiconductor region and below an ion-sensitive passivation surface configured to receive the fluid; a second charge control electrode, above a second electrode semiconductor region, to control transmission of the plurality of charge packets out of the gate semiconductor region and into a drain diffusion region in response to a second control signal applied to the second electrode; and the drain diffusion region to receive the plurality of charge packets from the gate semiconductor region via the second electrode semiconductor region, at least one control and readout transistor to generate an output voltage as a function of the accumulated plurality of charge packets at the drain diffusion region of the charge accumulation device, wherein the output voltage is representative of the ion concentration of the solution and wherein the at least one control and readout transistor includes: a reset transistor connected to the drain diffusion region of the charge accumulation device, to a row control line and to a column control line; and a readout transistor connected to the drain diffusion region of the charge accumulation device, to a source diffusion region of the charge accumulation device, to the column control line and to a column data line. a charge-accumulation device to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, including: a first charge control electrode, above a first electrode semiconductor region, to control entry of charge into a gate semiconductor region in response to a first control signal applied to the first electrode; and an electrically floating gate structure above the gate semiconductor region and below an ion-sensitive passivation surface configured to receive the fluid; a second charge control electrode, above a second electrode semiconductor region, to control transmission of the plurality of charge packets out of the gate semiconductor region and into a drain diffusion region in response to a second control signal applied to the second electrode; and the drain diffusion region to receive the plurality of charge packets from the gate semiconductor region via the second electrode semiconductor region, a first charge control electrode, above a first electrode semiconductor region, to control entry of charge into a gate semiconductor region in response to a first control signal applied to the first electrode; and an electrically floating gate structure above the gate semiconductor region and below an ion-sensitive passivation surface configured to receive the fluid; a second charge control electrode, above a second electrode semiconductor region, to control transmission of the plurality of charge packets out of the gate semiconductor region and into a drain diffusion region in response to a second control signal applied to the second electrode; and at least one control and readout transistor to generate an output voltage as a function of the accumulated plurality of charge packets at the drain diffusion region of the charge accumulation device, wherein the output voltage is representative of the ion concentration of the solution and wherein the at least one control and readout transistor includes: a reset transistor connected to the drain diffusion region of the charge accumulation device, to a row control line and to a column control line; and a readout transistor connected to the drain diffusion region of the charge accumulation device, to a source diffusion region of the charge accumulation device, to the column control line and to a column data line. a reset transistor connected to the drain diffusion region of the charge accumulation device, to a row control line and to a column control line; and a readout transistor connected to the drain diffusion region of the charge accumulation device, to a source diffusion region of the charge accumulation device, to the column control line and to a column data line.