A circuit for generating a plurality of oscillating signals with different phases, wherein: a frequency divider, configured for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal, wherein a phase difference between the input signals is 180 degrees; a first delay chain (130_1) comprising a plurality of first delay cells (210_1-210_6) connected in series, configured for receiving the first frequency-divided input signal; a second delay chain (130_2) comprising a plurality of second delay cells (220_1-220_6) connected in series, configured for receiving the second frequency-divided input signal; and a calibration circuit, coupled to the first delay chain (130_1) and the second delay chain(130_2), configured to generate, according to at least two outputs of the first delay chain (130_1), a first digital calibration signal (ctrl_1) to control the delay amounts of the delay cells within the first delay chain to make the phase difference between said outputs of the two delay cells of the first delay chain close to 180 degrees and to generate, according to at least two outputs of the second delay chain (130_2), a second digital calibration signal (ctrl_2) to control the delay amounts of the delay cells within the second delay chain to make the phase difference between said outputs of the two delay cells of the second delay chain close to 180 degrees; wherein output signals of a portion of the first delay cells (210_1-210_6) and the second delay cells (220_1-220_6) serve as the plurality of oscillating signals with different phases, wherein the plurality of oscillating signals are an in-phase signal, a quadrature signal, an inverted in-phase signal and an inverted quadrature signal, wherein the output signals of two of the first delay cells (210_1-210_6) serve as two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal, and the output signals of two of the second delay cells (220_1-220_6) serve as the other two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal and the calibration circuit is configured to calibrate the delay amounts of the delay cells (210_1-210_6) to make the phases of the output signals to be accurate. a frequency divider, configured for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal, wherein a phase difference between the input signals is 180 degrees; a first delay chain (130_1) comprising a plurality of first delay cells (210_1-210_6) connected in series, configured for receiving the first frequency-divided input signal; a second delay chain (130_2) comprising a plurality of second delay cells (220_1-220_6) connected in series, configured for receiving the second frequency-divided input signal; and a calibration circuit, coupled to the first delay chain (130_1) and the second delay chain(130_2), configured to generate, according to at least two outputs of the first delay chain (130_1), a first digital calibration signal (ctrl_1) to control the delay amounts of the delay cells within the first delay chain to make the phase difference between said outputs of the two delay cells of the first delay chain close to 180 degrees and to generate, according to at least two outputs of the second delay chain (130_2), a second digital calibration signal (ctrl_2) to control the delay amounts of the delay cells within the second delay chain to make the phase difference between said outputs of the two delay cells of the second delay chain close to 180 degrees; wherein output signals of a portion of the first delay cells (210_1-210_6) and the second delay cells (220_1-220_6) serve as the plurality of oscillating signals with different phases, wherein the plurality of oscillating signals are an in-phase signal, a quadrature signal, an inverted in-phase signal and an inverted quadrature signal, wherein the output signals of two of the first delay cells (210_1-210_6) serve as two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal, and the output signals of two of the second delay cells (220_1-220_6) serve as the other two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal and the calibration circuit is configured to calibrate the delay amounts of the delay cells (210_1-210_6) to make the phases of the output signals to be accurate.