An electrostatic discharge protection device (100; 200; 300; 400), comprising: a substrate structure comprising: a semiconductor substrate; a plurality of fins on the semiconductor substrate and comprising a first fin and a second fin; a first doped region and a second doped region laterally adjacent to each other and having different conductivity types, wherein: the first doped region comprises a first portion of the semiconductor substrate and a first region of the first fin on the first portion of the semiconductor substrate, the second doped region comprises a second portion of the semiconductor substrate, a second region of the first fin on the second portion of the semiconductor substrate, and the second fin on the second doped region; a first gate structure on a portion of a first region of the first fin and on a portion of a second region of the first fin; a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration of the first highly doped region being higher than a dopant concentration of the first doped region; and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration of the second highly doped region being higher than a dopant concentration of the second doped region. a substrate structure comprising: a semiconductor substrate; a plurality of fins on the semiconductor substrate and comprising a first fin and a second fin; a semiconductor substrate; a plurality of fins on the semiconductor substrate and comprising a first fin and a second fin; a first doped region and a second doped region laterally adjacent to each other and having different conductivity types, wherein: the first doped region comprises a first portion of the semiconductor substrate and a first region of the first fin on the first portion of the semiconductor substrate, the second doped region comprises a second portion of the semiconductor substrate, a second region of the first fin on the second portion of the semiconductor substrate, and the second fin on the second doped region; a first gate structure on a portion of a first region of the first fin and on a portion of a second region of the first fin; a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration of the first highly doped region being higher than a dopant concentration of the first doped region; and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration of the second highly doped region being higher than a dopant concentration of the second doped region. the first doped region comprises a first portion of the semiconductor substrate and a first region of the first fin on the first portion of the semiconductor substrate, the second doped region comprises a second portion of the semiconductor substrate, a second region of the first fin on the second portion of the semiconductor substrate, and the second fin on the second doped region; a first gate structure on a portion of a first region of the first fin and on a portion of a second region of the first fin; a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration of the first highly doped region being higher than a dopant concentration of the first doped region; and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration of the second highly doped region being higher than a dopant concentration of the second doped region.