A method of operating a memory device, wherein the memory device includes an n-type substrate and a plurality of p-MOS enhancement mode memory cells formed thereon, each memory cell including a control gate, a source region, a drain region, a channel region defined between the source and drain regions (204, 206), a trapping layer provided above the channel region, a first insulating layer provided between the trapping layer and the channel region, and a second insulating layer provided between the trapping layer and the control gate, wherein the control gate corresponds to a word line, the source region corresponds to a first bit line, and the drain region corresponds to a second bit line, and wherein each memory cell includes a first bit portion and a second bit portion each for storing one bit of information, the method comprising: resetting a selected memory cell, including applying a first negative bias to the word line of the selected memory cell, and applying a ground bias to both the first bit line and the second bit line, characterized in that first and second tunneling processes take place, wherein in the first tunneling process, electrons tunnel from the control gate of the selected memory cell, through the second insulating layer of the selected memory cell, into the trapping layer of the selected memory cell, and in the second tunneling process, electrons tunnel out of the trapping layer of the selected memory cell, through the first insulating layer of the selected memory cell, into the channel region of the selected memory cell, wherein the threshold voltage V th of the selected memory cell is changed from a negative value to a positive value by the resetting of said memory cell; and programming the first bit portion of the selected memory cell, including applying a first positive bias to the word line of the selected memory cell, applying a second negative bias to the first bit line of the selected memory cell, and applying a ground bias to the second bit line of the selected memory cell. resetting a selected memory cell, including applying a first negative bias to the word line of the selected memory cell, and applying a ground bias to both the first bit line and the second bit line, characterized in that first and second tunneling processes take place, wherein in the first tunneling process, electrons tunnel from the control gate of the selected memory cell, through the second insulating layer of the selected memory cell, into the trapping layer of the selected memory cell, and in the second tunneling process, electrons tunnel out of the trapping layer of the selected memory cell, through the first insulating layer of the selected memory cell, into the channel region of the selected memory cell, wherein the threshold voltage V th of the selected memory cell is changed from a negative value to a positive value by the resetting of said memory cell; and programming the first bit portion of the selected memory cell, including applying a first positive bias to the word line of the selected memory cell, applying a second negative bias to the first bit line of the selected memory cell, and applying a ground bias to the second bit line of the selected memory cell.