A decision feedback equalization, DFE, circuit comprising: a current integrating summer, CIS, circuit coupled to a data node (208a, 208b, 208c, 208d), the CIS circuit to generate a data signal at the data node based on an input data signal and a clock signal; and a plurality of correction circuits (202a, 202b, 202c, 202d) coupled to the data node to provide respective correction signals to the data node based on a prior bit of the input data signal, wherein the correction circuit is to provide the respective correction signals for a time period that is less than one unit interval, UI, of the clock signal, wherein a correction circuit of the plurality of correction circuits includes: a current source; an access transistor coupled between the current source and the data node, wherein the access transistor is responsive to a control signal to conductively couple the current source to the data node for the time period; and wherein the data node is a first data node and the data signal is a first data signal, and wherein the DFE circuit further includes a second data node to receive a second data signal that forms a differential pair with the first data signal, and wherein the correction circuit further includes: a first data transistor coupled between the access transistor and the first data node to selectively pass a first correction signal of the respective correction signals to the first node when the prior bit of the data signal has a first value; and a second data transistor coupled between the access transistor and the second data node to selectively pass a second correction signal of the respective correction signals to the second node when the prior bit of the data signal has a second value. a current integrating summer, CIS, circuit coupled to a data node (208a, 208b, 208c, 208d), the CIS circuit to generate a data signal at the data node based on an input data signal and a clock signal; and a plurality of correction circuits (202a, 202b, 202c, 202d) coupled to the data node to provide respective correction signals to the data node based on a prior bit of the input data signal, wherein the correction circuit is to provide the respective correction signals for a time period that is less than one unit interval, UI, of the clock signal, wherein a correction circuit of the plurality of correction circuits includes: a current source; an access transistor coupled between the current source and the data node, wherein the access transistor is responsive to a control signal to conductively couple the current source to the data node for the time period; a current source; an access transistor coupled between the current source and the data node, wherein the access transistor is responsive to a control signal to conductively couple the current source to the data node for the time period; and wherein the data node is a first data node and the data signal is a first data signal, and wherein the DFE circuit further includes a second data node to receive a second data signal that forms a differential pair with the first data signal, and wherein the correction circuit further includes: a first data transistor coupled between the access transistor and the first data node to selectively pass a first correction signal of the respective correction signals to the first node when the prior bit of the data signal has a first value; and a second data transistor coupled between the access transistor and the second data node to selectively pass a second correction signal of the respective correction signals to the second node when the prior bit of the data signal has a second value. a first data transistor coupled between the access transistor and the first data node to selectively pass a first correction signal of the respective correction signals to the first node when the prior bit of the data signal has a first value; and a second data transistor coupled between the access transistor and the second data node to selectively pass a second correction signal of the respective correction signals to the second node when the prior bit of the data signal has a second value.