A mixed-radix carry-lookahead adder, comprising the following: an initial carry-lookahead stage having one or more elements configured to receive a plurality of input bits and create initial propagate and generate signals for each bit and further compute an XOR of the inputs that is forwarded to a final carry-lookahead stage; a first intermediate carry-lookahead stage having one or more elements of a specified radix configured to receive the propagate and generate signals from the initial carry-lookahead stage and calculate its own propagate and generate output signals based thereon; a second intermediate carry-lookahead stage having one or more elements of a specified radix that is different than the radix of the first intermediate carry-lookahead stage, configured to receive the propagate and generate output signals from the first intermediate carry-lookahead stage and calculate its own generate output signal based thereon, wherein the elements of the initial carry-lookahead stage, the elements of the first intermediate carry-lookahead stage, and the elements of the second intermediate carry-lookahead stage are arranged such that each of the propagate and generate output signals passes through a minimal number of passive transmission lines; and a final carry-lookahead stage comprising an XOR logic gate configured to receive the generate output from the second intermediate carry-lookahead stage and XOR the generate output received from the second intermediate carry-lookahead stage with the computed XOR signal forwarded from the initial carry-lookahead stage to produce a sum of the plurality of input bits. an initial carry-lookahead stage having one or more elements configured to receive a plurality of input bits and create initial propagate and generate signals for each bit and further compute an XOR of the inputs that is forwarded to a final carry-lookahead stage; a first intermediate carry-lookahead stage having one or more elements of a specified radix configured to receive the propagate and generate signals from the initial carry-lookahead stage and calculate its own propagate and generate output signals based thereon; a second intermediate carry-lookahead stage having one or more elements of a specified radix that is different than the radix of the first intermediate carry-lookahead stage, configured to receive the propagate and generate output signals from the first intermediate carry-lookahead stage and calculate its own generate output signal based thereon, wherein the elements of the initial carry-lookahead stage, the elements of the first intermediate carry-lookahead stage, and the elements of the second intermediate carry-lookahead stage are arranged such that each of the propagate and generate output signals passes through a minimal number of passive transmission lines; and a final carry-lookahead stage comprising an XOR logic gate configured to receive the generate output from the second intermediate carry-lookahead stage and XOR the generate output received from the second intermediate carry-lookahead stage with the computed XOR signal forwarded from the initial carry-lookahead stage to produce a sum of the plurality of input bits.