An input-output, I/O, receiver, comprising: a receiving terminal, coupled with an external voltage signal; a first NMOS transistor, having a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage; a reformation circuit, configured to sharpen the rising edge and the falling edge of a voltage signal transmitted from a drain electrode of the first NMOS transistor; and a compensation unit, including a first PMOS transistor, a second PMOS transistor, a second NMOS transistor and a third NMOS transistor, the compensation unit configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor, whereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage; wherein: a source electrode of the first PMOS transistor is coupled with the first power supply voltage and a gate electrode of the first PMOS transistor is coupled with the receiving terminal; a drain electrode of the second NMOS transistor is coupled with a drain electrode of the first PMOS transistor, a gate electrode of the second NMOS transistor is coupled with the drain electrode of the first NMOS transistor, and a source electrode of the second NMOS transistor is connected to ground; and a drain electrode of the third NMOS transistor is coupled with the drain electrode of the second PMOS transistor and the drain electrode of the first NMOS transistor, a gate electrode of the third NMOS transistor is coupled with the drain electrode of the first PMOS transistor, and a source electrode of the third NMOS transistor is grounded. a receiving terminal, coupled with an external voltage signal; a first NMOS transistor, having a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage; a reformation circuit, configured to sharpen the rising edge and the falling edge of a voltage signal transmitted from a drain electrode of the first NMOS transistor; and a compensation unit, including a first PMOS transistor, a second PMOS transistor, a second NMOS transistor and a third NMOS transistor, the compensation unit configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor, whereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage; wherein: a source electrode of the first PMOS transistor is coupled with the first power supply voltage and a gate electrode of the first PMOS transistor is coupled with the receiving terminal; a drain electrode of the second NMOS transistor is coupled with a drain electrode of the first PMOS transistor, a gate electrode of the second NMOS transistor is coupled with the drain electrode of the first NMOS transistor, and a source electrode of the second NMOS transistor is connected to ground; and a drain electrode of the third NMOS transistor is coupled with the drain electrode of the second PMOS transistor and the drain electrode of the first NMOS transistor, a gate electrode of the third NMOS transistor is coupled with the drain electrode of the first PMOS transistor, and a source electrode of the third NMOS transistor is grounded. a source electrode of the first PMOS transistor is coupled with the first power supply voltage and a gate electrode of the first PMOS transistor is coupled with the receiving terminal; a drain electrode of the second NMOS transistor is coupled with a drain electrode of the first PMOS transistor, a gate electrode of the second NMOS transistor is coupled with the drain electrode of the first NMOS transistor, and a source electrode of the second NMOS transistor is connected to ground; and a drain electrode of the third NMOS transistor is coupled with the drain electrode of the second PMOS transistor and the drain electrode of the first NMOS transistor, a gate electrode of the third NMOS transistor is coupled with the drain electrode of the first PMOS transistor, and a source electrode of the third NMOS transistor is grounded.