A hardware tessellation unit comprising: an initial patch selection logic block comprising: (i) a first input configured to receive patch data for a plurality of initial patches, (ii) a second input arranged to receive an ID, wherein the ID is a primitive or vertex ID, (iii) hardware logic arranged to select a patch data for one of the initial patches based on one or more bits of the ID, and (iv) an output configured to output the selected patch data; a sub-division logic block comprising: (i) an input configured to receive patch data, (ii) hardware logic arranged to sub-divide the initial patch or sub-patch for which patch data is received, and (iii) an output configured to output patch data for each of the sub-patches formed by the sub-division; a sub-patch selection logic block comprising: (i) a first input configured to receive patch data for a plurality of sub-patches formed by sub-division in the sub-division logic block, (ii) a second input configured to receive an ID, (iii) hardware logic arranged to select patch data for one of the sub-patches based on one or more bits of the ID, and (iv) an output configured to output the selected patch data; an order flip logic block comprising: (i) an input configured to receive patch data for the plurality of sub-patches from the sub-division logic block, (ii) an output configured to output patch data for the plurality of sub-patches to the sub-patch selection logic block, and (iii) hardware logic arranged to control the order in which patch data for the plurality of sub-patches is output via the output based on one or more stored values; and an end of ID logic block comprising: (i) a first input configured to receive patch data for an initial patch from the initial patch selection logic block, (ii) a second input arranged to receive patch data for the selected sub-patches from the sub-patch selection logic block, (iii) hardware logic arranged to determine, from an ID for the patch or sub-patch, whether the initial patch or sub-patch is to be sub-divided, (iv) a first output configured to output the patch data in response to determining that the initial patch or sub-patch is to be sub-divided, wherein the patch data output by the first output is the patch data received by the input of the sub-division logic block, and (v) a second output configured to output the patch data in response to determining that the initial patch or sub-patch is not to be sub-divided. an initial patch selection logic block comprising: (i) a first input configured to receive patch data for a plurality of initial patches, (ii) a second input arranged to receive an ID, wherein the ID is a primitive or vertex ID, (iii) hardware logic arranged to select a patch data for one of the initial patches based on one or more bits of the ID, and (iv) an output configured to output the selected patch data; a sub-division logic block comprising: (i) an input configured to receive patch data, (ii) hardware logic arranged to sub-divide the initial patch or sub-patch for which patch data is received, and (iii) an output configured to output patch data for each of the sub-patches formed by the sub-division; a sub-patch selection logic block comprising: (i) a first input configured to receive patch data for a plurality of sub-patches formed by sub-division in the sub-division logic block, (ii) a second input configured to receive an ID, (iii) hardware logic arranged to select patch data for one of the sub-patches based on one or more bits of the ID, and (iv) an output configured to output the selected patch data; an order flip logic block comprising: (i) an input configured to receive patch data for the plurality of sub-patches from the sub-division logic block, (ii) an output configured to output patch data for the plurality of sub-patches to the sub-patch selection logic block, and (iii) hardware logic arranged to control the order in which patch data for the plurality of sub-patches is output via the output based on one or more stored values; and an end of ID logic block comprising: (i) a first input configured to receive patch data for an initial patch from the initial patch selection logic block, (ii) a second input arranged to receive patch data for the selected sub-patches from the sub-patch selection logic block, (iii) hardware logic arranged to determine, from an ID for the patch or sub-patch, whether the initial patch or sub-patch is to be sub-divided, (iv) a first output configured to output the patch data in response to determining that the initial patch or sub-patch is to be sub-divided, wherein the patch data output by the first output is the patch data received by the input of the sub-division logic block, and (v) a second output configured to output the patch data in response to determining that the initial patch or sub-patch is not to be sub-divided.