A display panel, comprising: a base substrate, provided with a plurality of sub-pixels (spx), at least one of the plurality of sub-pixels (spx) comprising a pixel circuit, wherein the pixel circuit comprises a driving transistor, an oxide transistor and a storage capacitor; a silicon semiconductor layer, on the base substrate, the silicon semiconductor layer comprising an active silicon layer of the driving transistor; a first conducting layer, at a side, facing away from the base substrate, of the silicon semiconductor layer, the first conducting layer comprising a gate electrode (CC2a) of the driving transistor; oxide semiconductor layer, at a side, facing away from the base substrate, of the first conducting layer, the oxide semiconductor layer comprising an active oxide layer of the oxide transistor; a second conducting layer, at the side, facing away from the base substrate, of the first conducting layer, the second conducting layer comprising a storage conducting part (CC1a); a third conducting layer, at a side, facing away from the base substrate, of the second conducting layer, the third conducting layer comprising a first power line part (Vdd) and a second connection part, the first power line part (Vdd) being spaced from the second connection part; wherein in a same sub-pixel (spx), a second electrode of the oxide transistor is electrically connected to the gate electrode (CC2a) of the driving transistor through the second connection part, and the first power line part (Vdd) is electrically connected to the storage conducting part (CC1a); a fourth conducting layer, at a side, facing away from the base substrate, of the third conducting layer, the fourth conducting layer comprising a second power line part; wherein in the same sub-pixel (spx), the first power line part (Vdd) is electrically connected to the second power line part; wherein in the same sub-pixel (spx), an orthographic projection of the second power line part on the base substrate covers an orthographic projection of the second connection part on the base substrate; the orthographic projection of the second power line part on the base substrate exceeds edges of two sides, in a second direction, of an orthographic projection of the gate electrode (CC2a) of the driving transistor on the base substrate, and exceeds edges of two sides, in the second direction, of an orthographic projection of the storage conducting part (CC1a) on the base substrate. a base substrate, provided with a plurality of sub-pixels (spx), at least one of the plurality of sub-pixels (spx) comprising a pixel circuit, wherein the pixel circuit comprises a driving transistor, an oxide transistor and a storage capacitor; a silicon semiconductor layer, on the base substrate, the silicon semiconductor layer comprising an active silicon layer of the driving transistor; a first conducting layer, at a side, facing away from the base substrate, of the silicon semiconductor layer, the first conducting layer comprising a gate electrode (CC2a) of the driving transistor; oxide semiconductor layer, at a side, facing away from the base substrate, of the first conducting layer, the oxide semiconductor layer comprising an active oxide layer of the oxide transistor; a second conducting layer, at the side, facing away from the base substrate, of the first conducting layer, the second conducting layer comprising a storage conducting part (CC1a); a third conducting layer, at a side, facing away from the base substrate, of the second conducting layer, the third conducting layer comprising a first power line part (Vdd) and a second connection part, the first power line part (Vdd) being spaced from the second connection part; wherein in a same sub-pixel (spx), a second electrode of the oxide transistor is electrically connected to the gate electrode (CC2a) of the driving transistor through the second connection part, and the first power line part (Vdd) is electrically connected to the storage conducting part (CC1a); a fourth conducting layer, at a side, facing away from the base substrate, of the third conducting layer, the fourth conducting layer comprising a second power line part; wherein in the same sub-pixel (spx), the first power line part (Vdd) is electrically connected to the second power line part; wherein in the same sub-pixel (spx), an orthographic projection of the second power line part on the base substrate covers an orthographic projection of the second connection part on the base substrate; the orthographic projection of the second power line part on the base substrate exceeds edges of two sides, in a second direction, of an orthographic projection of the gate electrode (CC2a) of the driving transistor on the base substrate, and exceeds edges of two sides, in the second direction, of an orthographic projection of the storage conducting part (CC1a) on the base substrate.