Method for manufacturing at least one interconnection element between different component levels in an integrated circuit provided with several superposed levels (N 1, N 2) of electronic components, the method including the following steps of: a) forming, on a lower level (N 1) provided with one or several connection areas and at least one first component (T 1) made at least partially in a first semiconducting layer, at least one block comprising a second semiconducting layer in which at least one channel region of at least one transistor (T 21) in an upper level (N 2) can be at least partially formed and an insulating layer (33, 294) can be formed between the first semiconducting layer and the second semiconducting layer; b) forming a lateral insulating area in contact with a lateral face of the block such that the lateral insulating area is supported of a first connection area on the lower level, the lateral insulating area being formed from at least a first dielectric layer based on a first dielectric material and at least a second dielectric layer based on a second dielectric material that can be selectively etched relative to the first dielectric material, the first dielectric layer being placed in contact with the second semiconducting layer and being coated with the second dielectric layer; then forming an encapsulation layer around the lateral insulating area; c) removing a portion of the lateral insulating area so as to form at least one hole provided with a bottom exposing said first connection area, the removed portion being a portion of the second dielectric layer selectively etched relative to the first dielectric layer so as to maintain the first dielectric material between the first hole and the second semiconducting layer, the encapsulation layer being based on a material able to resist selecting etching of the second dielectric material; d) filling the hole with a conducting material, the conducting material being placed so as to form at least one interconnection element between an electrode of the transistor (T 21) and said first connection area, the electrode being a gate electrode of the transistor. a) forming, on a lower level (N 1) provided with one or several connection areas and at least one first component (T 1) made at least partially in a first semiconducting layer, at least one block comprising a second semiconducting layer in which at least one channel region of at least one transistor (T 21) in an upper level (N 2) can be at least partially formed and an insulating layer (33, 294) can be formed between the first semiconducting layer and the second semiconducting layer; b) forming a lateral insulating area in contact with a lateral face of the block such that the lateral insulating area is supported of a first connection area on the lower level, the lateral insulating area being formed from at least a first dielectric layer based on a first dielectric material and at least a second dielectric layer based on a second dielectric material that can be selectively etched relative to the first dielectric material, the first dielectric layer being placed in contact with the second semiconducting layer and being coated with the second dielectric layer; then forming an encapsulation layer around the lateral insulating area; c) removing a portion of the lateral insulating area so as to form at least one hole provided with a bottom exposing said first connection area, the removed portion being a portion of the second dielectric layer selectively etched relative to the first dielectric layer so as to maintain the first dielectric material between the first hole and the second semiconducting layer, the encapsulation layer being based on a material able to resist selecting etching of the second dielectric material; d) filling the hole with a conducting material, the conducting material being placed so as to form at least one interconnection element between an electrode of the transistor (T 21) and said first connection area, the electrode being a gate electrode of the transistor.