An apparatus comprising: processing circuitry to perform data processing; instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing; and a plurality of vector registers to store vector operands comprising a plurality of data elements; in which: the instruction decoding circuitry is responsive to a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, at least the destination vector register and the carry source vector register each specifying operands comprising at least one pair of data elements, each pair comprising a first data element and a second data element, to control the processing circuitry, for each pair of data elements of the destination vector register, to: update the first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from the second data element of a corresponding pair of data elements of the carry source vector register; and update the second data element of the pair of data elements of the destination vector register with a value corresponding to a carry output of said addition; wherein each data element comprises 2 N bits, and the second source data value comprises 2 N bits, where N is an integer. processing circuitry to perform data processing; instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing; and a plurality of vector registers to store vector operands comprising a plurality of data elements; in which: the instruction decoding circuitry is responsive to a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, at least the destination vector register and the carry source vector register each specifying operands comprising at least one pair of data elements, each pair comprising a first data element and a second data element, to control the processing circuitry, for each pair of data elements of the destination vector register, to: update the first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from the second data element of a corresponding pair of data elements of the carry source vector register; and update the second data element of the pair of data elements of the destination vector register with a value corresponding to a carry output of said addition; wherein each data element comprises 2 N bits, and the second source data value comprises 2 N bits, where N is an integer. the instruction decoding circuitry is responsive to a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, at least the destination vector register and the carry source vector register each specifying operands comprising at least one pair of data elements, each pair comprising a first data element and a second data element, to control the processing circuitry, for each pair of data elements of the destination vector register, to: update the first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from the second data element of a corresponding pair of data elements of the carry source vector register; and update the second data element of the pair of data elements of the destination vector register with a value corresponding to a carry output of said addition; update the first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from the second data element of a corresponding pair of data elements of the carry source vector register; and update the second data element of the pair of data elements of the destination vector register with a value corresponding to a carry output of said addition; wherein each data element comprises 2 N bits, and the second source data value comprises 2 N bits, where N is an integer.