A method of forming a non-planar semiconductor device comprising: forming a semiconductor body on an insulating layer, said semiconductor body having a top surface opposite a bottom surface and a pair of laterally opposite sidewalls above an insulating substrate; forming a sacrificial gate electrode over the top surface and laterally opposite sidewalls of the semiconductor body; doping the semiconductor body on opposite sides of the sacrificial gate electrode with impurities to form a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode; forming dielectric sidewall spacers along opposite sidewalls of the sacrificial gate electrode; forming silicon onto the exposed top surface and sidewalls of the semiconductor body; placing dopants in the semiconductor body and the silicon; forming silicide on the silicon formed on the semiconductor body; forming a dielectric layer over the substrate; planarizing the dielectric layer until the top surface of the dielectric layer is planar with the sacrificial gate electrode and the top surface of the sacrificial gate electrode is exposed; removing the sacrificial gate electrode to expose the channel region of the semiconductor body; removing a portion of the insulating layer from beneath the channel region of the semiconductor body; forming a gate dielectric on said top surface of said semiconductor body, on said laterally opposite sidewalls of said semiconductor body, and on the portion of the exposed bottom surface of the semiconductor body; and forming a gate electrode on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body and subadjacent to said gate dielectric formed on at least a portion of the bottom surface of the semiconductor body. forming a semiconductor body on an insulating layer, said semiconductor body having a top surface opposite a bottom surface and a pair of laterally opposite sidewalls above an insulating substrate; forming a sacrificial gate electrode over the top surface and laterally opposite sidewalls of the semiconductor body; doping the semiconductor body on opposite sides of the sacrificial gate electrode with impurities to form a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode; forming dielectric sidewall spacers along opposite sidewalls of the sacrificial gate electrode; forming silicon onto the exposed top surface and sidewalls of the semiconductor body; placing dopants in the semiconductor body and the silicon; forming silicide on the silicon formed on the semiconductor body; forming a dielectric layer over the substrate; planarizing the dielectric layer until the top surface of the dielectric layer is planar with the sacrificial gate electrode and the top surface of the sacrificial gate electrode is exposed; removing the sacrificial gate electrode to expose the channel region of the semiconductor body; removing a portion of the insulating layer from beneath the channel region of the semiconductor body; forming a gate dielectric on said top surface of said semiconductor body, on said laterally opposite sidewalls of said semiconductor body, and on the portion of the exposed bottom surface of the semiconductor body; and forming a gate electrode on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body and subadjacent to said gate dielectric formed on at least a portion of the bottom surface of the semiconductor body.