A test system (100, 200) connectable to an external printed circuit board, PCB, tester (104, 204), the test system (100, 200) comprising: a printed circuit board, "PCB" (102, 202); a plurality of integrated circuits, "ICs" (106, 108, 110, 206, 208, 210) mounted on the PCB (102, 202); and a link circuit (144, 244); wherein the plurality of ICs comprise a first IC (106, 206), and a second IC (110, 210); wherein the first IC (106, 206) of the plurality of ICs comprises: a first test circuit having a first test access port, "TAP" controller (114, 214); and wherein the second IC (110, 210) of the plurality of ICs comprises: a second test circuit having a second TAP controller (134, 234); and an embedded tester (142, 242) having a test data output coupled to a test data input of the first TAP controller by way of the link circuit (144, 244), wherein the link circuit comprises a resistor, in the range of 1k ohms to 10k ohms, having a first terminal coupled at the test data output and a second terminal coupled at the test data input of the first TAP controller, wherein, when the external PCB tester is not connected to the test system: link circuit is configured to allow transfer of a test data output, TDO, signal from the test data output of the second IC to a test data input, TDI, of the TAP controller of the first IC; the embedded tester configured to provide test control signals to the first TAP controller and the second TAP controller; and wherein, when the external PCB tester is connected to the test system: the test data output, TDO, signal from the second IC is configured to be provided to the external PCB tester; the outputs of the embedded tester are configured to be in a high impedance state, thereby allowing test control signal lines to be driven unimpeded by the external PCB tester; and the test data input, TDI, of the TAP controller of the first IC is configured to receive a serial data stream from the external PCB tester. a printed circuit board, "PCB" (102, 202); a plurality of integrated circuits, "ICs" (106, 108, 110, 206, 208, 210) mounted on the PCB (102, 202); and a link circuit (144, 244); wherein the plurality of ICs comprise a first IC (106, 206), and a second IC (110, 210); wherein the first IC (106, 206) of the plurality of ICs comprises: a first test circuit having a first test access port, "TAP" controller (114, 214); and wherein the second IC (110, 210) of the plurality of ICs comprises: a second test circuit having a second TAP controller (134, 234); and an embedded tester (142, 242) having a test data output coupled to a test data input of the first TAP controller by way of the link circuit (144, 244), a second test circuit having a second TAP controller (134, 234); and an embedded tester (142, 242) having a test data output coupled to a test data input of the first TAP controller by way of the link circuit (144, 244), wherein the link circuit comprises a resistor, in the range of 1k ohms to 10k ohms, having a first terminal coupled at the test data output and a second terminal coupled at the test data input of the first TAP controller, wherein, when the external PCB tester is not connected to the test system: link circuit is configured to allow transfer of a test data output, TDO, signal from the test data output of the second IC to a test data input, TDI, of the TAP controller of the first IC; the embedded tester configured to provide test control signals to the first TAP controller and the second TAP controller; and link circuit is configured to allow transfer of a test data output, TDO, signal from the test data output of the second IC to a test data input, TDI, of the TAP controller of the first IC; the embedded tester configured to provide test control signals to the first TAP controller and the second TAP controller; and wherein, when the external PCB tester is connected to the test system: the test data output, TDO, signal from the second IC is configured to be provided to the external PCB tester; the outputs of the embedded tester are configured to be in a high impedance state, thereby allowing test control signal lines to be driven unimpeded by the external PCB tester; and the test data input, TDI, of the TAP controller of the first IC is configured to receive a serial data stream from the external PCB tester. the test data output, TDO, signal from the second IC is configured to be provided to the external PCB tester; the outputs of the embedded tester are configured to be in a high impedance state, thereby allowing test control signal lines to be driven unimpeded by the external PCB tester; and the test data input, TDI, of the TAP controller of the first IC is configured to receive a serial data stream from the external PCB tester.