A method of processing a task by a multi-processing computer system having a main processing unit and a plurality of sub-processing units (102B-D) having a common instruction architecture and a respective memory, the method comprising: providing instructions defining a task for execution by a sub-processing unit stored in addressable memory of that sub-processing unit, wherein the instructions comprise a jump instruction to a target routine, a return instruction within the target routine, and a subsequent instruction to be executed after the target routine is executed, providing a first base value for a first sub-processing unit related to the addresses at which the instructions are stored by the first sub-processing unit, processing the jump instruction at the first sub-processing unit by determining a return value based on the base value and address of the jump instruction, storing the return value, determining the address of the target instruction based on a parameter value and base value, and jumping to the address of the target routine, moving execution of the task to a second sub-processing unit during execution of the task; changing the addresses at which the instructions are stored from an address space of the first sub-processing unit by moving the instructions to a different memory location in an address space of the second sub-processing unit and storing a second base value for the second sub-processing unit related to the changed addresses, after the addresses of the instruction are changed, processing the return instruction at the second sub-processing unit by determining the address of the subsequent instruction based on the return value and the second base value and jumping to the address; and preventing said step of changing the addresses at which the instructions are stored during the step of processing the jump instruction. providing instructions defining a task for execution by a sub-processing unit stored in addressable memory of that sub-processing unit, wherein the instructions comprise a jump instruction to a target routine, a return instruction within the target routine, and a subsequent instruction to be executed after the target routine is executed, providing a first base value for a first sub-processing unit related to the addresses at which the instructions are stored by the first sub-processing unit, processing the jump instruction at the first sub-processing unit by determining a return value based on the base value and address of the jump instruction, storing the return value, determining the address of the target instruction based on a parameter value and base value, and jumping to the address of the target routine, moving execution of the task to a second sub-processing unit during execution of the task; changing the addresses at which the instructions are stored from an address space of the first sub-processing unit by moving the instructions to a different memory location in an address space of the second sub-processing unit and storing a second base value for the second sub-processing unit related to the changed addresses, after the addresses of the instruction are changed, processing the return instruction at the second sub-processing unit by determining the address of the subsequent instruction based on the return value and the second base value and jumping to the address; and preventing said step of changing the addresses at which the instructions are stored during the step of processing the jump instruction.