An apparatus comprising: instruction decoder circuitry to decode instructions; and data processing circuitry to selectively apply vector processing operations specified by the instructions to input data vectors comprising a plurality of input data items at respective positions in the input data vectors, wherein the instruction decoder circuitry is responsive to a vector interleaving instruction specifying a first source register, a second source register, and a destination register to generate control signals to control the data processing circuitry to carry out a vector interleaving process to: retrieve a first set of input data items from the first source register; retrieve a second set of input data items from the second source register; perform a data processing operation on at least selected input data item pairs taken from the first and second set of input data items to generate a set of result data items, wherein the selected input data item pairs taken from the first and second set of input data items comprise diagonal input data item pairs formed of alternating input data items in the first source register paired with alternating input data items in the second source register; and store the set of result data items as a result data vector in the destination register, wherein the set of result data items are stored in a set of alternating positions in the destination data vector. instruction decoder circuitry to decode instructions; and data processing circuitry to selectively apply vector processing operations specified by the instructions to input data vectors comprising a plurality of input data items at respective positions in the input data vectors, wherein the instruction decoder circuitry is responsive to a vector interleaving instruction specifying a first source register, a second source register, and a destination register to generate control signals to control the data processing circuitry to carry out a vector interleaving process to: retrieve a first set of input data items from the first source register; retrieve a second set of input data items from the second source register; perform a data processing operation on at least selected input data item pairs taken from the first and second set of input data items to generate a set of result data items, wherein the selected input data item pairs taken from the first and second set of input data items comprise diagonal input data item pairs formed of alternating input data items in the first source register paired with alternating input data items in the second source register; and store the set of result data items as a result data vector in the destination register, wherein the set of result data items are stored in a set of alternating positions in the destination data vector. retrieve a first set of input data items from the first source register; retrieve a second set of input data items from the second source register; perform a data processing operation on at least selected input data item pairs taken from the first and second set of input data items to generate a set of result data items, wherein the selected input data item pairs taken from the first and second set of input data items comprise diagonal input data item pairs formed of alternating input data items in the first source register paired with alternating input data items in the second source register; and store the set of result data items as a result data vector in the destination register, wherein the set of result data items are stored in a set of alternating positions in the destination data vector.