An analog neural memory system (1900, 2000, 2300, 2400) comprising: an array of non-volatile memory cells (1901, 1902, 1905, 1906), wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines and the cells in the second plurality of columns of cells are dummy cells (1905, 1906) serving as source line pull down cells, and each row of cells in the array is coupled to a source line (SL0, SL1); a set of dummy bit line switches (1904a, 1904b, 1904c, 1904d, 2001, 2002) arranged on a first end of the array, each of the set of dummy bit line switches coupled to one of the dummy bit lines in the plurality of dummy bitlines; and a set of bit line switches (1903a, 1903b, 1903c, 1903d, 2003) arranged on a second end of the array opposite the first end of the array, each of the set of bit line switches coupled to one of the bit lines in the plurality of bit lines; the analog neural memory system being further configured to, during a read operation of a selected cell (1901, 1902) in the first plurality of columns of cells, pass a current through a path formed by a bit line switch of the set of bit line switches (1903a, 1903b, 1903c, 1903d, 2003) coupled to the bit line connected to the selected cell, by said bit line, by said selected cell, by a source line, by a dummy cell serving as source line pull down cell, by a dummy bit line, and by a dummy bit line switch of the set of dummy bit line switches (1904a, 1904b, 1904c, 1904d, 2001, 2002). an array of non-volatile memory cells (1901, 1902, 1905, 1906), wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines and the cells in the second plurality of columns of cells are dummy cells (1905, 1906) serving as source line pull down cells, and each row of cells in the array is coupled to a source line (SL0, SL1); a set of dummy bit line switches (1904a, 1904b, 1904c, 1904d, 2001, 2002) arranged on a first end of the array, each of the set of dummy bit line switches coupled to one of the dummy bit lines in the plurality of dummy bitlines; and a set of bit line switches (1903a, 1903b, 1903c, 1903d, 2003) arranged on a second end of the array opposite the first end of the array, each of the set of bit line switches coupled to one of the bit lines in the plurality of bit lines; the analog neural memory system being further configured to, during a read operation of a selected cell (1901, 1902) in the first plurality of columns of cells, pass a current through a path formed by a bit line switch of the set of bit line switches (1903a, 1903b, 1903c, 1903d, 2003) coupled to the bit line connected to the selected cell, by said bit line, by said selected cell, by a source line, by a dummy cell serving as source line pull down cell, by a dummy bit line, and by a dummy bit line switch of the set of dummy bit line switches (1904a, 1904b, 1904c, 1904d, 2001, 2002).