A circuit comprising: a comparator (120, 400, 510) to generate a clamp output signal by monitoring an output voltage (VOUT) and a single reference voltage (VREF) that sets a clamp voltage threshold for the output voltage (VOUT), wherein the clamp output signal is employed to limit the output voltage (VOUT) from exceeding the clamp voltage threshold; a first switch to supply the single reference voltage (VREF) to the comparator (120, 400, 510), the first switch forms a portion of an intrinsic delay circuit (110, 410, 520) with a first feedback path in the comparator (120, 400, 510) to mitigate ripple in the output voltage (VOUT); and a second switch coupled to an input voltage and a second feedback path in the comparator (120, 400, 510), the second switch forms another portion of the intrinsic delay circuit (110, 410, 520) with the first switch, the first feedback path, and the second feedback path in the comparator (120, 400, 510) to further mitigate ripple in the output voltage (VOUT), wherein a second feedback signal of the second feedback path is the inverted first feedback signal of the first feedback path; a power switching circuit (150, 550) to switch the input voltage to the output voltage (VOUT) in response to a gate control signal; the first switch comprising: a first drain connected to the single reference voltage; a first source coupled to a first differential input of the comparator (120, 400, 510); and a first gate that receives the first feedback signal from a first output of the comparator (120, 400, 510), the first gate enabling the first switch to supply the reference voltage to the first differential input of the comparator (120, 400, 510), and the second switch configured to operate with the first switch, the second switch comprising: a second drain coupled to the input voltage; a second source coupled to the first source of the first switch and to the first differential input of the comparator (120, 400, 510); and a second gate that receives the second feedback signal from a second output of the comparator (120, 400, 510), wherein the first switch, the first feedback signal, the second switch, and the second feedback signal form the intrinsic delay circuit (110, 410, 520) in the comparator (120, 400, 510) to mitigate ripple in the output voltage (VOUT). a comparator (120, 400, 510) to generate a clamp output signal by monitoring an output voltage (VOUT) and a single reference voltage (VREF) that sets a clamp voltage threshold for the output voltage (VOUT), wherein the clamp output signal is employed to limit the output voltage (VOUT) from exceeding the clamp voltage threshold; a first switch to supply the single reference voltage (VREF) to the comparator (120, 400, 510), the first switch forms a portion of an intrinsic delay circuit (110, 410, 520) with a first feedback path in the comparator (120, 400, 510) to mitigate ripple in the output voltage (VOUT); and a second switch coupled to an input voltage and a second feedback path in the comparator (120, 400, 510), the second switch forms another portion of the intrinsic delay circuit (110, 410, 520) with the first switch, the first feedback path, and the second feedback path in the comparator (120, 400, 510) to further mitigate ripple in the output voltage (VOUT), wherein a second feedback signal of the second feedback path is the inverted first feedback signal of the first feedback path; a power switching circuit (150, 550) to switch the input voltage to the output voltage (VOUT) in response to a gate control signal; the first switch comprising: a first drain connected to the single reference voltage; a first source coupled to a first differential input of the comparator (120, 400, 510); and a first gate that receives the first feedback signal from a first output of the comparator (120, 400, 510), the first gate enabling the first switch to supply the reference voltage to the first differential input of the comparator (120, 400, 510), and a first drain connected to the single reference voltage; a first source coupled to a first differential input of the comparator (120, 400, 510); and a first gate that receives the first feedback signal from a first output of the comparator (120, 400, 510), the first gate enabling the first switch to supply the reference voltage to the first differential input of the comparator (120, 400, 510), and the second switch configured to operate with the first switch, the second switch comprising: a second drain coupled to the input voltage; a second source coupled to the first source of the first switch and to the first differential input of the comparator (120, 400, 510); and a second gate that receives the second feedback signal from a second output of the comparator (120, 400, 510), wherein the first switch, the first feedback signal, the second switch, and the second feedback signal form the intrinsic delay circuit (110, 410, 520) in the comparator (120, 400, 510) to mitigate ripple in the output voltage (VOUT). a second drain coupled to the input voltage; a second source coupled to the first source of the first switch and to the first differential input of the comparator (120, 400, 510); and a second gate that receives the second feedback signal from a second output of the comparator (120, 400, 510), wherein the first switch, the first feedback signal, the second switch, and the second feedback signal form the intrinsic delay circuit (110, 410, 520) in the comparator (120, 400, 510) to mitigate ripple in the output voltage (VOUT).