A turbo decoder circuit for performing a turbo decoding process to recover a frame of data symbols from a received signal comprising one or more parity and/or systematic soft decision values for each data symbol of the frame, the data symbols of the frame having been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver to interleave the data symbols between the upper and lower convolutional encoders, the turbo decoder circuit comprising a clock, configurable network circuitry which is configured to interleave soft decision values, an upper decoder comprising a plurality of upper processing elements associated with the upper convolutional encoder, each of the processing elements of the upper decoder being configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper convolutional encoder, to perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols, and to provide the extrinsic soft decision values to the configurable network circuitry, at least one of the processing elements of the upper decoder being configured to perform the calculations for a window associated with a different number of the trellis stages to at least one other of the processing elements of the upper decoder, and a lower decoder comprising a plurality of lower processing elements associated with the lower convolutional encoder, each of the processing elements of the lower decoder being configured, during the series of the consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the lower convolutional encoder, to perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols, and to provide the extrinsic soft decision values to the configurable network circuitry, at least one of the processing elements of the lower decoder being configured to perform the calculations for a window associated with a different number of the trellis stages to at least one other of the processing elements of the lower decoder, wherein the configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder, the interleaving performed by the configurable network circuitry controlled by the network controller being in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle, wherein the processing elements for each of the upper decoder and the lower decoder are configured to read the a priori soft decision values from memory and to write extrinsic soft decision values to memory after the calculations are performed, and the configurable network circuitry is configured to read the extrinsic soft decision values from memory and to write a priori soft decision values to memory, and the reading of one or more of the extrinsic soft decision values by the configurable network in accordance with the predetermined schedule is delayed by one or more clock cycles relative to the writing of the one or more extrinsic soft decision values by the processing elements, or the processing elements for each of the upper decoder and the lower decoder are configured to read the a priori soft decision values from memory and to write extrinsic soft decision values to memory after the calculations are performed, and the configurable network circuitry is configured to read the extrinsic soft decision values from memory and to write a priori soft decision values to memory, and at least one of the reading of one or more of the extrinsic soft decision values by the configurable network in accordance with the predetermined schedule or the writing of the one or more extrinsic soft decision values by the processing elements is skipped.