A microprocessor comprising: an execution unit configured to operate on instructions and data; a cache memory subsystem coupled to said execution unit; wherein said cache memory subsystem includes: a cache memory including a plurality of independently accessible storage blocks (220A, 220B.... 220N); a plurality of independently accessible tag units (210A, 210B.... 210N) coupled to said plurality of storage blocks and configured to store a plurality of tags each including an address tag value; and a plurality of cache buses coupled to convey a plurality of cache access requests to each of said plurality of storage blocks; characterized in that: in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible; said plurality of storage blocks are accessed asynchronously with respect to said plurality of tag units; and said plurality of tag units operate synchronously with the rest of the microprocessor. an execution unit configured to operate on instructions and data; a cache memory subsystem coupled to said execution unit; wherein said cache memory subsystem includes: a cache memory including a plurality of independently accessible storage blocks (220A, 220B.... 220N); a plurality of independently accessible tag units (210A, 210B.... 210N) coupled to said plurality of storage blocks and configured to store a plurality of tags each including an address tag value; and a plurality of cache buses coupled to convey a plurality of cache access requests to each of said plurality of storage blocks; characterized in that: in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible; said plurality of storage blocks are accessed asynchronously with respect to said plurality of tag units; and said plurality of tag units operate synchronously with the rest of the microprocessor. a cache memory including a plurality of independently accessible storage blocks (220A, 220B.... 220N); a plurality of independently accessible tag units (210A, 210B.... 210N) coupled to said plurality of storage blocks and configured to store a plurality of tags each including an address tag value; and a plurality of cache buses coupled to convey a plurality of cache access requests to each of said plurality of storage blocks; characterized in that: in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible; said plurality of storage blocks are accessed asynchronously with respect to said plurality of tag units; and said plurality of tag units operate synchronously with the rest of the microprocessor. in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible; said plurality of storage blocks are accessed asynchronously with respect to said plurality of tag units; and said plurality of tag units operate synchronously with the rest of the microprocessor.