A gate driving circuit of a display panel, adapted to drive gate lines arranged in the display panel, wherein the gate driving circuit of the display panel comprises a shift register, a plurality of gate enable units and an integrated circuit, the shift register comprises at least two stages of shift register units, a gate signal output terminal of each shift register unit is connected with an input terminal of one of the gate enable unit, an output terminal of the gate enable unit is connected with a gate line, the gate enable unit further comprises an enable signal input terminal, and the gate enable unit is adapted to control, by an enable signal received at the enable signal input terminal, whether to transfer the gate signal outputted from the gate signal output terminal of the shift register unit to the gate line; the integrated circuit adapted to supply an enable signal to the gate enable unit; wherein the integrated circuit comprises a comparison circuit adapted to compare image information of all pixel points in the same row of adjacent frames of images to be displayed on the display panel and to output a comparison result as the enable signal to the enable signal input terminal of the gate enable unit; wherein in the case that the image information of all pixel points in the same row of adjacent frames of the image is the same, the gate signal outputted from the gate signal output terminal of the shift register unit is not transferred to the gate line according to the enable signal; in the case that the image information of at least one pixel point in the same row of adjacent frames of the image is different, the gate signal outputted from the gate signal output terminal of the shift register unit is transferred to the gate line according to the enable signal; wherein the integrated circuit further comprises: a gating circuit adapted to supply a clock signal to each stage of the shift register unit; a reset circuit adapted to supply a reset signal to each stage of the shift register unit; and a first trigger circuit adapted to supply a first trigger signal to the first stage of the shift register unit, wherein the first trigger signal is adapted to trigger an operation of the first stage of the shift register unit; wherein the gating circuit is adapted to supply different clock signals to respective stages of the shift register units according to the comparison result of the comparison circuit; wherein in the case that the image information of all pixel points in the same row of adjacent frames of the image is the same, the gating circuit is adapted to supply a first clock signal (CK1, CKB1) to the respective stages of the shift register units; in the case that the image information of at least one pixel point in the same row of adjacent frames of the image is different, the gating circuit is adapted to supply a second clock signal (CK2, CKB2) to the respective stages of the shift register units, and a frequency of the first clock signal is higher than a frequency of the second clock signal. wherein the integrated circuit comprises a comparison circuit adapted to compare image information of all pixel points in the same row of adjacent frames of images to be displayed on the display panel and to output a comparison result as the enable signal to the enable signal input terminal of the gate enable unit; wherein in the case that the image information of all pixel points in the same row of adjacent frames of the image is the same, the gate signal outputted from the gate signal output terminal of the shift register unit is not transferred to the gate line according to the enable signal; in the case that the image information of at least one pixel point in the same row of adjacent frames of the image is different, the gate signal outputted from the gate signal output terminal of the shift register unit is transferred to the gate line according to the enable signal; a gating circuit adapted to supply a clock signal to each stage of the shift register unit; a reset circuit adapted to supply a reset signal to each stage of the shift register unit; and a first trigger circuit adapted to supply a first trigger signal to the first stage of the shift register unit, wherein the first trigger signal is adapted to trigger an operation of the first stage of the shift register unit; wherein the gating circuit is adapted to supply different clock signals to respective stages of the shift register units according to the comparison result of the comparison circuit; wherein in the case that the image information of all pixel points in the same row of adjacent frames of the image is the same, the gating circuit is adapted to supply a first clock signal (CK1, CKB1) to the respective stages of the shift register units; in the case that the image information of at least one pixel point in the same row of adjacent frames of the image is different, the gating circuit is adapted to supply a second clock signal (CK2, CKB2) to the respective stages of the shift register units, and a frequency of the first clock signal is higher than a frequency of the second clock signal.