A lateral bipolar power semiconductor transistor comprising: a contact region of a first conductivity type located within a first semiconductor region of a second, opposite conductivity type; a source region of the second conductivity type located within a second semiconductor region of the first conductivity type; a lateral drift region of the second conductivity type placed between the first semiconductor region and the second semiconductor region, the lateral drift region configured to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor; a gate placed above and in direct contact to the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region of the second conductivity type and to thereby control flow of charge within the lateral drift region; a first floating semiconductor region of the first conductivity type located laterally spaced with respect to the contact region, located within the first semiconductor region, and having a higher doping concentration than the first semiconductor region of the second conductivity type; a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, located within the first semiconductor region, and having a higher doping concentration than the first semiconductor region of the second conductivity type, a floating electrode placed above and in direct contact with the first and second floating semiconductor regions; the lateral bipolar power semiconductor transistor characterised by: a third floating semiconductor region having the second conductivity type located laterally adjacent the contact region and the first floating semiconductor region, and the floating electrode is placed above and in direct contact with the third floating semiconductor regions. a contact region of a first conductivity type located within a first semiconductor region of a second, opposite conductivity type; a source region of the second conductivity type located within a second semiconductor region of the first conductivity type; a lateral drift region of the second conductivity type placed between the first semiconductor region and the second semiconductor region, the lateral drift region configured to be depleted of mobile carriers at breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor; a gate placed above and in direct contact to the second semiconductor region, the gate to control charge in a channel region between the lateral drift region and the source region of the second conductivity type and to thereby control flow of charge within the lateral drift region; a first floating semiconductor region of the first conductivity type located laterally spaced with respect to the contact region, located within the first semiconductor region, and having a higher doping concentration than the first semiconductor region of the second conductivity type; a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, located within the first semiconductor region, and having a higher doping concentration than the first semiconductor region of the second conductivity type, a floating electrode placed above and in direct contact with the first and second floating semiconductor regions; the lateral bipolar power semiconductor transistor characterised by: a third floating semiconductor region having the second conductivity type located laterally adjacent the contact region and the first floating semiconductor region, and the floating electrode is placed above and in direct contact with the third floating semiconductor regions. a third floating semiconductor region having the second conductivity type located laterally adjacent the contact region and the first floating semiconductor region, and the floating electrode is placed above and in direct contact with the third floating semiconductor regions.