A pixel (10, 11, 12, 13, 14) comprising: a light emitting element; a first transistor connected between a first node and a second node and which is configured to generate a driving current flowing from a first power line to a second power line and flowing through the light emitting element, wherein the first power line is configured to supply a first power supply voltage, and the second power line is configured to supply a second power supply voltage; a second transistor connected between a data line (Dj) and the first node and which is configured to be turned on in response to a fourth scan signal supplied to a fourth scan line (S4i); a third transistor connected between the second node and a third node and which is configured to be turned on in response to a second scan signal supplied to a second scan line (S2i), wherein the third node is connected to a gate electrode of the first transistor; a fourth transistor connected between the second node and a third power line configured to supply a third power supply voltage (Vint1), and which is configured to be turned on in response to a first scan signal supplied to a first scan line (S1i); a fifth transistor connected between the first node and a fourth node and which is configured to be turned on in response to a third scan signal supplied to a third scan line (S3i); a sixth transistor connected between the first power line and the first node and which is configured to be turned off in response to a first emission control signal supplied to a first emission control line (E1i); a storage capacitor (Cst) connected between the third node and the fourth node; and a first capacitor connected between the first power line and the fourth node, characterized in that the third transistor and the fifth transistor are n-type oxide semiconductor transistors and the first transistor, the second transistor, and the fourth transistor are p-type polysilicon semiconductor transistors. a light emitting element; a first transistor connected between a first node and a second node and which is configured to generate a driving current flowing from a first power line to a second power line and flowing through the light emitting element, wherein the first power line is configured to supply a first power supply voltage, and the second power line is configured to supply a second power supply voltage; a second transistor connected between a data line (Dj) and the first node and which is configured to be turned on in response to a fourth scan signal supplied to a fourth scan line (S4i); a third transistor connected between the second node and a third node and which is configured to be turned on in response to a second scan signal supplied to a second scan line (S2i), wherein the third node is connected to a gate electrode of the first transistor; a fourth transistor connected between the second node and a third power line configured to supply a third power supply voltage (Vint1), and which is configured to be turned on in response to a first scan signal supplied to a first scan line (S1i); a fifth transistor connected between the first node and a fourth node and which is configured to be turned on in response to a third scan signal supplied to a third scan line (S3i); a sixth transistor connected between the first power line and the first node and which is configured to be turned off in response to a first emission control signal supplied to a first emission control line (E1i); a storage capacitor (Cst) connected between the third node and the fourth node; and a first capacitor connected between the first power line and the fourth node, characterized in that the third transistor and the fifth transistor are n-type oxide semiconductor transistors and the first transistor, the second transistor, and the fourth transistor are p-type polysilicon semiconductor transistors.