A multi-gate lateral-diffused-metal-oxide-semiconductor, LDMOS, device comprising: a semiconductor-on-insulator, SOI, support structure on or over which are located at least one substantially symmetrical internal LDMOS region having two source regions (452, 453) arranged symmetrically on opposite sides of a single drain region, and at least one asymmetric edge-proximate LDMOS region having a single source region only; and a deep-trench isolation, DTI, wall extending into the support structure and substantially terminating the at least one edge-proximate LDMOS region; wherein the at least one asymmetric edge-proximate LDMOS region comprises: a first drain region of a first conductivity type proximate an upper surface; said single source region located laterally on the side of the first drain region opposite to the DTI; a doped semiconductor, SC, buried layer, BL, region proximate the DTI wall, underlying a portion of the at least one asymmetric edge-proximate LDMOS region, and of a second conductivity type opposite the first conductivity type, the first drain region being formed in a well drift region of the first conductivity type underlying the first drain region; and a second well region of the second conductivity type, underlying the well drift region, wherein the BL region underlies the second well region proximate the DTI wall; wherein the at least one substantially symmetrical internal LDMOS region comprises: said single drain region proximate the upper surface and being of the first conductivity type; a first source region of said two source regions; and a second source region of said two source regions, wherein the first source region and the second source region are located on laterally opposite sides of the single drain region; said single drain region being formed in a further well drift region of the first conductivity type underlying the single drain region; and a further second well region of the second conductivity type, underlying the further well drift region; no BL region underlying the further second well region. a semiconductor-on-insulator, SOI, support structure on or over which are located at least one substantially symmetrical internal LDMOS region having two source regions (452, 453) arranged symmetrically on opposite sides of a single drain region, and at least one asymmetric edge-proximate LDMOS region having a single source region only; and a deep-trench isolation, DTI, wall extending into the support structure and substantially terminating the at least one edge-proximate LDMOS region; wherein the at least one asymmetric edge-proximate LDMOS region comprises: a first drain region of a first conductivity type proximate an upper surface; said single source region located laterally on the side of the first drain region opposite to the DTI; a doped semiconductor, SC, buried layer, BL, region proximate the DTI wall, underlying a portion of the at least one asymmetric edge-proximate LDMOS region, and of a second conductivity type opposite the first conductivity type, the first drain region being formed in a well drift region of the first conductivity type underlying the first drain region; and a second well region of the second conductivity type, underlying the well drift region, wherein the BL region underlies the second well region proximate the DTI wall; a first drain region of a first conductivity type proximate an upper surface; said single source region located laterally on the side of the first drain region opposite to the DTI; a doped semiconductor, SC, buried layer, BL, region proximate the DTI wall, underlying a portion of the at least one asymmetric edge-proximate LDMOS region, and of a second conductivity type opposite the first conductivity type, the first drain region being formed in a well drift region of the first conductivity type underlying the first drain region; and a second well region of the second conductivity type, underlying the well drift region, wherein the BL region underlies the second well region proximate the DTI wall; wherein the at least one substantially symmetrical internal LDMOS region comprises: said single drain region proximate the upper surface and being of the first conductivity type; a first source region of said two source regions; and a second source region of said two source regions, wherein the first source region and the second source region are located on laterally opposite sides of the single drain region; said single drain region being formed in a further well drift region of the first conductivity type underlying the single drain region; and a further second well region of the second conductivity type, underlying the further well drift region; no BL region underlying the further second well region. said single drain region proximate the upper surface and being of the first conductivity type; a first source region of said two source regions; and a second source region of said two source regions, wherein the first source region and the second source region are located on laterally opposite sides of the single drain region; said single drain region being formed in a further well drift region of the first conductivity type underlying the single drain region; and a further second well region of the second conductivity type, underlying the further well drift region; no BL region underlying the further second well region.