An apparatus for generating synchronized clock signals, comprising: a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal; and a plurality of second circuits (130-1,..., 130-N) forming a series of second circuits, each of the plurality of second circuits (130-1,..., 130-N) comprising a respective synchronization circuit (140-1,..., 140-N) configured to receive the first clock signal, wherein the synchronization circuit of the first one of the series of second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal, wherein the synchronization circuits of the other ones of the series of second circuits are configured to receive the respective replica of the second clock signal (103-1,..., 103-N-1) generated by the respective preceding second circuit in the series of second circuits and to resample the respectively received replica of the second clock signal (103-1,..., 103-N-1) based on the first clock signal in order to generate a respective replica of the second clock signal that is in phase with the second clock signal, characterised in that the first circuit further comprises a second clock divider circuit configured to receive the second clock signal and to generate a third clock signal by frequency dividing the second clock signal, wherein each of the series of second circuits comprises a respective second synchronization circuit (160-1,..., 160-N) configured to receive the respective replica of the second clock signal (103-1,..., 103-N) generated locally at the respective second circuit, wherein the second synchronization circuit of the first one of the series of second circuits is configured to receive the third clock signal from the first circuit and to resample the third clock signal based on the replica of the second clock signal generated locally at the first one of the series of second circuits in order to generate a replica of the third clock signal that is in phase with the third clock signal, and wherein the second synchronization circuits of the other ones of the series of second circuits are configured to receive the respective replica of the third clock signal (105-1,..., 105-N-1) generated by the respective preceding second circuit in the series of second circuits and to resample the respectively received replica of the third clock signal (105-1,..., 105-N-1) based on the respective replica of the second clock signal generated locally at the respective second circuit in order to generate a respective replica of the third clock signal that is in phase with the third clock signal. a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal; and a plurality of second circuits (130-1,..., 130-N) forming a series of second circuits, each of the plurality of second circuits (130-1,..., 130-N) comprising a respective synchronization circuit (140-1,..., 140-N) configured to receive the first clock signal, wherein the synchronization circuit of the first one of the series of second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal, wherein the synchronization circuits of the other ones of the series of second circuits are configured to receive the respective replica of the second clock signal (103-1,..., 103-N-1) generated by the respective preceding second circuit in the series of second circuits and to resample the respectively received replica of the second clock signal (103-1,..., 103-N-1) based on the first clock signal in order to generate a respective replica of the second clock signal that is in phase with the second clock signal, characterised in that the first circuit further comprises a second clock divider circuit configured to receive the second clock signal and to generate a third clock signal by frequency dividing the second clock signal, wherein each of the series of second circuits comprises a respective second synchronization circuit (160-1,..., 160-N) configured to receive the respective replica of the second clock signal (103-1,..., 103-N) generated locally at the respective second circuit, wherein the second synchronization circuit of the first one of the series of second circuits is configured to receive the third clock signal from the first circuit and to resample the third clock signal based on the replica of the second clock signal generated locally at the first one of the series of second circuits in order to generate a replica of the third clock signal that is in phase with the third clock signal, and wherein the second synchronization circuits of the other ones of the series of second circuits are configured to receive the respective replica of the third clock signal (105-1,..., 105-N-1) generated by the respective preceding second circuit in the series of second circuits and to resample the respectively received replica of the third clock signal (105-1,..., 105-N-1) based on the respective replica of the second clock signal generated locally at the respective second circuit in order to generate a respective replica of the third clock signal that is in phase with the third clock signal.