A power supply system, comprising: a plurality of power supply modules (104a, 104b, 104c) having respective power outputs coupled in parallel; each of the plurality of power supply modules (104a, 104b, 104c) having a pulse width modulation controller for controlling the power output thereof through PWM, wherein a duty cycle of the PWM is controlled by the controller; each one of the controllers is coupled to a load share bus and comprises a digital load share counter (224; 464), wherein each of the controllers is configured to monitor logic levels on the LSB, a one of the controllers is configured to assert a load share signal on the LSB, when the asserted load share signal on the LSB is detected, remaining ones of the controllers are configured to start their respective digital load share counters (224; 464) and are further configured to assert their load share signals on the LSB, and when the load share signal on the LSB is de-asserted the respective digital load share counters (224; 464) are configured to stop; wherein each one of the controllers is configured to determine a respective time value of their digital load share counters (224; 464) representing a maximum percent power value being supplied by a one of the plurality of power supply modules (104a, 104b, 104c); each one of the controllers is further configured to compare the respective time value to a percent power value derived from a current duty cycle value; each one of the controllers is further configured to increase its output power when the maximum percent power value is greater than the percent power values supplied by the respective one of the plurality of power supply modules (104a, 104b, 104c); and each one of the controllers is further configured to reduce its output power when the maximum percent power value is substantially the same as a percent power value supplied by a one of the plurality of power supply modules (104a, 104b, 104c). a plurality of power supply modules (104a, 104b, 104c) having respective power outputs coupled in parallel; each of the plurality of power supply modules (104a, 104b, 104c) having a pulse width modulation controller for controlling the power output thereof through PWM, wherein a duty cycle of the PWM is controlled by the controller; each one of the controllers is coupled to a load share bus and comprises a digital load share counter (224; 464), wherein each of the controllers is configured to monitor logic levels on the LSB, a one of the controllers is configured to assert a load share signal on the LSB, when the asserted load share signal on the LSB is detected, remaining ones of the controllers are configured to start their respective digital load share counters (224; 464) and are further configured to assert their load share signals on the LSB, and when the load share signal on the LSB is de-asserted the respective digital load share counters (224; 464) are configured to stop; wherein each one of the controllers is configured to determine a respective time value of their digital load share counters (224; 464) representing a maximum percent power value being supplied by a one of the plurality of power supply modules (104a, 104b, 104c); each one of the controllers is further configured to compare the respective time value to a percent power value derived from a current duty cycle value; each one of the controllers is further configured to increase its output power when the maximum percent power value is greater than the percent power values supplied by the respective one of the plurality of power supply modules (104a, 104b, 104c); and each one of the controllers is further configured to reduce its output power when the maximum percent power value is substantially the same as a percent power value supplied by a one of the plurality of power supply modules (104a, 104b, 104c).