A system (100, 200, 300) comprising: a pulsed power amplifier (212, 350) controlled by a bias signal (Vg, PA Gate Drive Signal) and configurec to draw a power supply current (Id) from a power amplifier supply, wherein the power amplifier is operable to receive pulse waveforms and to generate corresponding amplified pulse waveforms, the power amplifier operable to draw a quiescent current from the power amplifier supply if the bias signal (Vg) is enabled but no pulse waveform is received; a measurement circuit (230, 356) configured to measure the power supply current provided to the power amplifier by the power amplifier supply; a comparison circuit (232, 327) configured to compare the power supply current measurement to a reference quiescent current value (Vref, 340) and generate a comparison circuit output (ID_LOW) as a logic signal indicative of the comparison of the power supply current measurement to the reference quiescent current value; and a bias controller (240, 310) coupled to the comparison circuit and configured to control a timing (BIAS_ON) of the bias signal such that the bias signal is synchronized with the pulse waveforms, and further configured to control a pulse width modulated signal (PA_PWM, 344) controlling a level of the bias signal, the bias signal being configured to control the power supply current provided to the power amplifier, wherein the bias controller is further configured to: enable the bias signal for a duration of the power amplifier receiving and amplifying each pulse waveform, and also enable the bias signal before each pulse waveform, so that the bias signal is enabled minimally longer than the pulse waveform, to allow the measurement circuit to measure the quiescent current and to allow the comparison circuit to generate the comparison circuit output; and adjust the level of the bias signal, the adjusting comprising incrementing the pulse width modulated signal if the comparison circuit output is logic true and/or decrementing the pulse width modulated signal if the comparison circuit output is logic false; wherein the bias controller is further configured to disable the bias signal during operational time between pulse waveforms to reduce power drawn by the power amplifier. a pulsed power amplifier (212, 350) controlled by a bias signal (Vg, PA Gate Drive Signal) and configurec to draw a power supply current (Id) from a power amplifier supply, wherein the power amplifier is operable to receive pulse waveforms and to generate corresponding amplified pulse waveforms, the power amplifier operable to draw a quiescent current from the power amplifier supply if the bias signal (Vg) is enabled but no pulse waveform is received; a measurement circuit (230, 356) configured to measure the power supply current provided to the power amplifier by the power amplifier supply; a comparison circuit (232, 327) configured to compare the power supply current measurement to a reference quiescent current value (Vref, 340) and generate a comparison circuit output (ID_LOW) as a logic signal indicative of the comparison of the power supply current measurement to the reference quiescent current value; and a bias controller (240, 310) coupled to the comparison circuit and configured to control a timing (BIAS_ON) of the bias signal such that the bias signal is synchronized with the pulse waveforms, and further configured to control a pulse width modulated signal (PA_PWM, 344) controlling a level of the bias signal, the bias signal being configured to control the power supply current provided to the power amplifier, wherein the bias controller is further configured to: enable the bias signal for a duration of the power amplifier receiving and amplifying each pulse waveform, and also enable the bias signal before each pulse waveform, so that the bias signal is enabled minimally longer than the pulse waveform, to allow the measurement circuit to measure the quiescent current and to allow the comparison circuit to generate the comparison circuit output; and adjust the level of the bias signal, the adjusting comprising incrementing the pulse width modulated signal if the comparison circuit output is logic true and/or decrementing the pulse width modulated signal if the comparison circuit output is logic false; wherein the bias controller is further configured to disable the bias signal during operational time between pulse waveforms to reduce power drawn by the power amplifier. enable the bias signal for a duration of the power amplifier receiving and amplifying each pulse waveform, and also enable the bias signal before each pulse waveform, so that the bias signal is enabled minimally longer than the pulse waveform, to allow the measurement circuit to measure the quiescent current and to allow the comparison circuit to generate the comparison circuit output; and adjust the level of the bias signal, the adjusting comprising incrementing the pulse width modulated signal if the comparison circuit output is logic true and/or decrementing the pulse width modulated signal if the comparison circuit output is logic false; wherein the bias controller is further configured to disable the bias signal during operational time between pulse waveforms to reduce power drawn by the power amplifier.