A manufacture method of a thin film transistor, comprising: patterning a wire layer in an optical lithography process to form a source electrode (210A, 402A) and a drain electrode (210B, 402B), which are spaced apart from each other, and patterning a semiconductor layer in another optical lithography process to form an active layer (214, 403), the semiconductor layer being formed on the patterned wire layer, characterised in that, patterning of the wire layer and patterning of the semiconductor layer are conducted with a same mask for exposing and a same exposure machine, the mask comprises a source region for forming the source electrode (210A, 402A), a drain region for forming the drain electrode (210B, 402B), and a slit provided between the source region and the drain region, and a width of the slit is smaller than the resolution of the exposure machine for patterning of the wire layer and patterning of the semiconductor layer, patterning of the wire layer is conducted by using the exposure machine and the mask with a first exposure amount larger than a normal exposure amount to make photoresist corresponding to the slit of the mask fully exposed during formation of the source electrode (210A, 402A) and the drain electrode (210B, 402B), so that the source electrode (210A, 402A) and the drain electrode (210B, 402B) spaced apart from each other are formed; patterning of the semiconductor layer is conducted by using the exposure machine and the mask with a second exposure amount smaller than the first exposure amount to make photoresist corresponding to the slit of the mask not fully exposed during formation of the active layer (214, 403), so that the active layer (214, 403) is formed on the source electrode (210A, 402A) and the drain electrode (210B, 402B) spaced apart from each other are formed. patterning a wire layer in an optical lithography process to form a source electrode (210A, 402A) and a drain electrode (210B, 402B), which are spaced apart from each other, and patterning a semiconductor layer in another optical lithography process to form an active layer (214, 403), the semiconductor layer being formed on the patterned wire layer, characterised in that, patterning of the wire layer and patterning of the semiconductor layer are conducted with a same mask for exposing and a same exposure machine, the mask comprises a source region for forming the source electrode (210A, 402A), a drain region for forming the drain electrode (210B, 402B), and a slit provided between the source region and the drain region, and a width of the slit is smaller than the resolution of the exposure machine for patterning of the wire layer and patterning of the semiconductor layer, patterning of the wire layer is conducted by using the exposure machine and the mask with a first exposure amount larger than a normal exposure amount to make photoresist corresponding to the slit of the mask fully exposed during formation of the source electrode (210A, 402A) and the drain electrode (210B, 402B), so that the source electrode (210A, 402A) and the drain electrode (210B, 402B) spaced apart from each other are formed; patterning of the semiconductor layer is conducted by using the exposure machine and the mask with a second exposure amount smaller than the first exposure amount to make photoresist corresponding to the slit of the mask not fully exposed during formation of the active layer (214, 403), so that the active layer (214, 403) is formed on the source electrode (210A, 402A) and the drain electrode (210B, 402B) spaced apart from each other are formed.