A three-dimensional, 3D, NAND memory device (100, 500), comprising: - an alternating layer stack disposed on a substrate, the alternating layer stack comprising: - a first region including an alternating dielectric stack comprising a plurality of dielectric layer pairs, and - second regions, each second region including an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs; - a barrier structure (224, 324, 424, 516) extending vertically through the alternating layer stack, wherein the at least one barrier structure (224, 324, 424, 516) separates the at least one first region enclosed laterally by at least the barrier structure (224, 324, 424, 516) from the second region; - a plurality of through array contacts (326, 526) in the first region, each through array contact (326, 526) extending vertically through the alternating dielectric stack, wherein at least one of the plurality of through array contacts (326, 526) is electrically connected with at least one peripheral circuit and is surrounded by the barrier structure (224, 324, 424, 516); and - a plurality of slit structures (214, 314, 414, 416, 514) each extending vertically through the alternating conductor/dielectric stack (560, 580) and laterally along a word line direction to divide the alternating conductor/dielectric stack (560, 580) into a plurality of memory fingers (242, 246, 342, 442, 444), wherein the barrier structure (224, 324, 424, 514) extends along the word line direction and is between two slits structures (214, 314, 414, 416, 514) in the plurality of slit structures (214, 314, 414, 416, 514), wherein the barrier structure (224, 324, 424, 516) is sandwiched between two of the second regions in a bit line direction being orthogonal to the word line direction. - an alternating layer stack disposed on a substrate, the alternating layer stack comprising: - a first region including an alternating dielectric stack comprising a plurality of dielectric layer pairs, and - second regions, each second region including an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs; - a barrier structure (224, 324, 424, 516) extending vertically through the alternating layer stack, wherein the at least one barrier structure (224, 324, 424, 516) separates the at least one first region enclosed laterally by at least the barrier structure (224, 324, 424, 516) from the second region; - a plurality of through array contacts (326, 526) in the first region, each through array contact (326, 526) extending vertically through the alternating dielectric stack, wherein at least one of the plurality of through array contacts (326, 526) is electrically connected with at least one peripheral circuit and is surrounded by the barrier structure (224, 324, 424, 516); and - a plurality of slit structures (214, 314, 414, 416, 514) each extending vertically through the alternating conductor/dielectric stack (560, 580) and laterally along a word line direction to divide the alternating conductor/dielectric stack (560, 580) into a plurality of memory fingers (242, 246, 342, 442, 444), wherein the barrier structure (224, 324, 424, 514) extends along the word line direction and is between two slits structures (214, 314, 414, 416, 514) in the plurality of slit structures (214, 314, 414, 416, 514), wherein the barrier structure (224, 324, 424, 516) is sandwiched between two of the second regions in a bit line direction being orthogonal to the word line direction.