A computer-implemented method comprising: receiving a request to implement a convolutional neural network on a special-purpose hardware circuit, and receiving and processing neural network inputs using the neural network by causing the hardware circuit to execute instructions, the neural network comprising a first convolutional neural network layer having a stride that is greater than one, the hardware circuit being an integrated circuit for performing neural network computations and including a matrix computation unit (120; 312) adapted to perform vector-matrix multiplications in hardware and a vector computation unit (140; 314; 602) that includes pooling circuitry adapted to perform pooling on outputs of the matrix computation unit (120; 312) in hardware; and in response, generating the instructions that when executed by the hardware circuit cause the hardware circuit to, during processing of an input tensor by the neural network, generate a layer output tensor that is equivalent to an output of the first convolutional neural network layer by performing operations comprising: the matrix computation unit (120; 312) processing the input tensor to the first convolutional neural network layer using a second convolutional neural network layer that has a stride that is equal to one but is otherwise equivalent to the first convolutional neural network layer to generate a first tensor; the vector computation unit (140; 314; 602) zeroing out elements of the first tensor that would not have been generated if the second convolutional neural network layer had the stride of the first convolutional neural network layer to generate a second tensor; and the pooling circuitry of the vector computation unit (140; 314; 602) performing max pooling on the second tensor to generate the layer output tensor, wherein the vector computation unit (140; 314; 602) zeroing out elements of the first tensor comprises: the vector computation unit (140; 314; 602) performing element-wise multiplication of a masking tensor and the first tensor to generate the second tensor, wherein the masking tensor comprises (i) zeros at each element position of the masking tensor that corresponds to an element of the first tensor that would not have been generated if the second convolutional neural network layer had the stride of the first convolutional neural network layer, and (ii) ones at each other element position of the masking tensor. receiving a request to implement a convolutional neural network on a special-purpose hardware circuit, and receiving and processing neural network inputs using the neural network by causing the hardware circuit to execute instructions, the neural network comprising a first convolutional neural network layer having a stride that is greater than one, the hardware circuit being an integrated circuit for performing neural network computations and including a matrix computation unit (120; 312) adapted to perform vector-matrix multiplications in hardware and a vector computation unit (140; 314; 602) that includes pooling circuitry adapted to perform pooling on outputs of the matrix computation unit (120; 312) in hardware; and in response, generating the instructions that when executed by the hardware circuit cause the hardware circuit to, during processing of an input tensor by the neural network, generate a layer output tensor that is equivalent to an output of the first convolutional neural network layer by performing operations comprising: the matrix computation unit (120; 312) processing the input tensor to the first convolutional neural network layer using a second convolutional neural network layer that has a stride that is equal to one but is otherwise equivalent to the first convolutional neural network layer to generate a first tensor; the vector computation unit (140; 314; 602) zeroing out elements of the first tensor that would not have been generated if the second convolutional neural network layer had the stride of the first convolutional neural network layer to generate a second tensor; and the pooling circuitry of the vector computation unit (140; 314; 602) performing max pooling on the second tensor to generate the layer output tensor, the matrix computation unit (120; 312) processing the input tensor to the first convolutional neural network layer using a second convolutional neural network layer that has a stride that is equal to one but is otherwise equivalent to the first convolutional neural network layer to generate a first tensor; the vector computation unit (140; 314; 602) zeroing out elements of the first tensor that would not have been generated if the second convolutional neural network layer had the stride of the first convolutional neural network layer to generate a second tensor; and the pooling circuitry of the vector computation unit (140; 314; 602) performing max pooling on the second tensor to generate the layer output tensor, wherein the vector computation unit (140; 314; 602) zeroing out elements of the first tensor comprises: the vector computation unit (140; 314; 602) performing element-wise multiplication of a masking tensor and the first tensor to generate the second tensor, wherein the masking tensor comprises (i) zeros at each element position of the masking tensor that corresponds to an element of the first tensor that would not have been generated if the second convolutional neural network layer had the stride of the first convolutional neural network layer, and (ii) ones at each other element position of the masking tensor.