An optical receiver comprising a photodiode and a transimpedance amplifier, TIA, circuit both integrated onto an integrated circuit, and comprising an input terminal and an output terminal, a ground, and a rail Vdd, and the TIA further comprising: an odd number of at least three inverting amplifier stages (A1, A2, A3, A4, A5) linked in series between the input terminal and the output terminal, said inverting amplifier stages including a first inverting amplifier stage having an input connected to the input terminal, a second inverting amplifier stage, and a final inverting amplifier stage having an output connected to the output terminal, and the first and second inverting amplifier stages each having a MOS transistor (M1, M2) with a source, a gate, a drain or a bipolar transistor with an emitter, a base, and a collector and a load circuit (R1, R2) connected to the drain or collector, wherein said load circuit is either a resistor load or a current source load or a combination of a resistor load and a current source load, wherein the input of said first inverting amplifier stage is the gate or base of the transistor of said first inverting amplifier stage, and the output of said first inverting amplifier stage is the drain or collector of the transistor of said first inverting amplifier stage, wherein the input of said second inverting amplifier stage is the gate or base of the transistor of said second inverting amplifier stage, and the output of said second inverting amplifier stage is the drain or collector of the transistor of said second inverting amplifier stage, a transimpedance feedback circuit coupled (Rf) between the output of the final inverting amplifier stage and the input terminal, wherein a first reference voltage source is connected to the source or emitter of the transistor of the first inverting amplifier stage, and a second reference voltage source is connected to the source or emitter of the transistor of the second inverting amplifier stage, wherein said first and second reference voltage sources each comprises a voltage regulator, and either: the anode of said photodiode is connected to ground and its cathode is connected to the input terminal and the first and second inverting stage amplifier transistors (M1, M2) are NMOS or NPN transistors, or: the cathode of said photodiode is connected to the rail Vdd and its anode is connected to the input terminal and the first and second inverting stage amplifier transistors (M1, M2) are PMOS or PNP transistors. wherein said load circuit is either a resistor load or a current source load or a combination of a resistor load and a current source load, wherein the input of said first inverting amplifier stage is the gate or base of the transistor of said first inverting amplifier stage, and the output of said first inverting amplifier stage is the drain or collector of the transistor of said first inverting amplifier stage, wherein the input of said second inverting amplifier stage is the gate or base of the transistor of said second inverting amplifier stage, and the output of said second inverting amplifier stage is the drain or collector of the transistor of said second inverting amplifier stage, a transimpedance feedback circuit coupled (Rf) between the output of the final inverting amplifier stage and the input terminal, wherein a first reference voltage source is connected to the source or emitter of the transistor of the first inverting amplifier stage, and a second reference voltage source is connected to the source or emitter of the transistor of the second inverting amplifier stage, wherein said first and second reference voltage sources each comprises a voltage regulator, and either: the anode of said photodiode is connected to ground and its cathode is connected to the input terminal and the first and second inverting stage amplifier transistors (M1, M2) are NMOS or NPN transistors, or: the cathode of said photodiode is connected to the rail Vdd and its anode is connected to the input terminal and the first and second inverting stage amplifier transistors (M1, M2) are PMOS or PNP transistors.