An apparatus, comprising: a plurality of signal lines including a pair of complementary bit line signal lines (230a, 230b), a first word line signal line and a second word line signal line; a supply line being coupled to a voltage or current power supply, or being a ground supply line; and a bitcell configured to store a bit state, said bitcell including a common node and first and second complementary resistance state storage cells (68a, 68b), each resistance state storage cell having an input coupled to the common node and an output coupled to a complementary bit line signal line, each complementary resistance state storage cell having a storage cell switch transistor (69a, 69b) having an input coupled to the first word line signal line, and a resistance state ferromagnetic device (70a, 70b) coupled in series with the storage cell switch transistor of the complementary resistance state storage cell and having a resistance state complementary to a resistance state of the resistance state ferromagnetic device of the complementary resistance state storage cell, and a supply switch transistor having an input coupled to the second word line signal line and configured to couple the common node to the supply line when activated, wherein the bitcell is configured to be read by driving first and second complementary currents from the supply line via the supply switch transistor through first and second complementary resistance state storage cells (68a, 68b), respectively, and sensing complementary bit state signals on the pair of first and second complementary bit line signal lines; and wherein the bitcell is configured to be written to with the supply switch transistor of the bitcell remaining inactive to decouple the common node from the supply line. a plurality of signal lines including a pair of complementary bit line signal lines (230a, 230b), a first word line signal line and a second word line signal line; a supply line being coupled to a voltage or current power supply, or being a ground supply line; and a bitcell configured to store a bit state, said bitcell including a common node and first and second complementary resistance state storage cells (68a, 68b), each resistance state storage cell having an input coupled to the common node and an output coupled to a complementary bit line signal line, each complementary resistance state storage cell having a storage cell switch transistor (69a, 69b) having an input coupled to the first word line signal line, and a resistance state ferromagnetic device (70a, 70b) coupled in series with the storage cell switch transistor of the complementary resistance state storage cell and having a resistance state complementary to a resistance state of the resistance state ferromagnetic device of the complementary resistance state storage cell, and a supply switch transistor having an input coupled to the second word line signal line and configured to couple the common node to the supply line when activated, wherein the bitcell is configured to be read by driving first and second complementary currents from the supply line via the supply switch transistor through first and second complementary resistance state storage cells (68a, 68b), respectively, and sensing complementary bit state signals on the pair of first and second complementary bit line signal lines; and wherein the bitcell is configured to be written to with the supply switch transistor of the bitcell remaining inactive to decouple the common node from the supply line.