An imaging sensor comprising: a plurality of substrates (310, 311); a pixel array; and a plurality of supporting circuits; a plurality of pixel read buses and circuit input read buses, wherein each pixel read bus and each circuit input read bus are aligned; and a plurality of interconnects; wherein a first substrate of the plurality of substrates (310, 311) comprises the pixel array; wherein the plurality of supporting circuits are disposed on a second, subsequent supporting substrate that is disposed remotely relative to said first substrate; wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array; and wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged; wherein the pixel array comprises a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as one pixel in width and a plurality of pixels in length with one pixel read bus per pixel column; and wherein at least one interconnect provides an electrical connection between each pixel read bus and a corresponding single circuit input read bus; wherein the interconnect is placed anywhere along a path of the superimposed pixel read bus and the circuit input read bus; wherein the second, subsequent supporting substrate comprises a plurality of circuit columns which comprise a plurality of readout supporting circuits with one circuit input read bus per circuit column, characterized in that an area of each of the plurality of pixel columns is the same as an area occupied by the circuit column that corresponds with that corresponding pixel column. a plurality of substrates (310, 311); a pixel array; and a plurality of supporting circuits; a plurality of pixel read buses and circuit input read buses, wherein each pixel read bus and each circuit input read bus are aligned; and a plurality of interconnects; wherein a first substrate of the plurality of substrates (310, 311) comprises the pixel array; wherein the plurality of supporting circuits are disposed on a second, subsequent supporting substrate that is disposed remotely relative to said first substrate; wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array; and wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged; wherein the pixel array comprises a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as one pixel in width and a plurality of pixels in length with one pixel read bus per pixel column; and wherein at least one interconnect provides an electrical connection between each pixel read bus and a corresponding single circuit input read bus; wherein the interconnect is placed anywhere along a path of the superimposed pixel read bus and the circuit input read bus; wherein the second, subsequent supporting substrate comprises a plurality of circuit columns which comprise a plurality of readout supporting circuits with one circuit input read bus per circuit column, characterized in that an area of each of the plurality of pixel columns is the same as an area occupied by the circuit column that corresponds with that corresponding pixel column.