A method of reading a memory device having rows and columns of memory cells formed on a substrate of semiconductor material having a first conductivity type: wherein each of the memory cells comprises: spaced apart first and second regions formed in the substrate and having a second conductivity type different than the first conductivity type, wherein a channel region of the substrate is disposed between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, a select gate disposed over and insulated from a second portion of the channel region, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the first region; wherein the memory device further comprises: a plurality of word lines each electrically connecting together a row of the select gates, a plurality of bit lines each electrically connecting together a column of the second regions, a plurality of source lines each electrically connecting together a row of the first regions, a plurality of control gate lines each electrically connecting together a row of the control gates, and a plurality of erase gate lines each electrically connecting together a row of the erase gates; wherein the method of reading the memory device comprises: applying a positive voltage to one of the word lines which is associated with a target memory cell; and applying a positive voltage to one of the bit lines which is associated with the target memory cell, and applying a zero voltage to all the other bit lines, and wherein the method of reading the memory device is characterized by: applying a negative voltage to all the other word lines; and applying a zero voltage to one of the source lines which is associated with the target memory cell, and applying a positive voltage to all the other source lines. wherein each of the memory cells comprises: spaced apart first and second regions formed in the substrate and having a second conductivity type different than the first conductivity type, wherein a channel region of the substrate is disposed between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, a select gate disposed over and insulated from a second portion of the channel region, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the first region; spaced apart first and second regions formed in the substrate and having a second conductivity type different than the first conductivity type, wherein a channel region of the substrate is disposed between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, a select gate disposed over and insulated from a second portion of the channel region, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the first region; wherein the memory device further comprises: a plurality of word lines each electrically connecting together a row of the select gates, a plurality of bit lines each electrically connecting together a column of the second regions, a plurality of source lines each electrically connecting together a row of the first regions, a plurality of control gate lines each electrically connecting together a row of the control gates, and a plurality of erase gate lines each electrically connecting together a row of the erase gates; a plurality of word lines each electrically connecting together a row of the select gates, a plurality of bit lines each electrically connecting together a column of the second regions, a plurality of source lines each electrically connecting together a row of the first regions, a plurality of control gate lines each electrically connecting together a row of the control gates, and a plurality of erase gate lines each electrically connecting together a row of the erase gates; wherein the method of reading the memory device comprises: applying a positive voltage to one of the word lines which is associated with a target memory cell; and applying a positive voltage to one of the bit lines which is associated with the target memory cell, and applying a zero voltage to all the other bit lines, and applying a positive voltage to one of the word lines which is associated with a target memory cell; and applying a positive voltage to one of the bit lines which is associated with the target memory cell, and applying a zero voltage to all the other bit lines, and wherein the method of reading the memory device is characterized by: applying a negative voltage to all the other word lines; and applying a zero voltage to one of the source lines which is associated with the target memory cell, and applying a positive voltage to all the other source lines. applying a negative voltage to all the other word lines; and applying a zero voltage to one of the source lines which is associated with the target memory cell, and applying a positive voltage to all the other source lines.