A computer apparatus for descrambling data received from a host system, via a memory controller on the host system comprising means for: solving for an unknown scramble sequence, based on which data is scrambled by the host system by XOR'ing the data with the scramble sequence, wherein the scramble sequence is based on a bitwise XOR of a set of independent vectors where each address bit corresponds to a vector, and wherein the means for solving for the unknown scramble sequence includes: means for instructing the host system to write a zero data pattern to address zero to generate a first scrambled data value; means for storing the first scrambled data value as one of the scramble generator vectors; and means for, for each one signal in the set of address signals, - setting only the one signal to "1" value while other signals in the set of address signals are set to "0" value, - writing a zero data pattern to an address corresponding to the address signals to generate a second scrambled data value, - performing a bitwise XOR operation of the first scrambled data value and the second scrambled data value to generate a scramble generator vector associated with the one of the address signals, and - storing the scramble generator vector associated with the one of the address signals; and means for performing a bitwise XOR operation of the scramble sequence and the data. solving for an unknown scramble sequence, based on which data is scrambled by the host system by XOR'ing the data with the scramble sequence, wherein the scramble sequence is based on a bitwise XOR of a set of independent vectors where each address bit corresponds to a vector, and wherein the means for solving for the unknown scramble sequence includes: means for instructing the host system to write a zero data pattern to address zero to generate a first scrambled data value; means for storing the first scrambled data value as one of the scramble generator vectors; and means for, for each one signal in the set of address signals, - setting only the one signal to "1" value while other signals in the set of address signals are set to "0" value, - writing a zero data pattern to an address corresponding to the address signals to generate a second scrambled data value, - performing a bitwise XOR operation of the first scrambled data value and the second scrambled data value to generate a scramble generator vector associated with the one of the address signals, and - storing the scramble generator vector associated with the one of the address signals; means for instructing the host system to write a zero data pattern to address zero to generate a first scrambled data value; means for storing the first scrambled data value as one of the scramble generator vectors; and means for, for each one signal in the set of address signals, - setting only the one signal to "1" value while other signals in the set of address signals are set to "0" value, - writing a zero data pattern to an address corresponding to the address signals to generate a second scrambled data value, - performing a bitwise XOR operation of the first scrambled data value and the second scrambled data value to generate a scramble generator vector associated with the one of the address signals, and - storing the scramble generator vector associated with the one of the address signals; - setting only the one signal to "1" value while other signals in the set of address signals are set to "0" value, - writing a zero data pattern to an address corresponding to the address signals to generate a second scrambled data value, - performing a bitwise XOR operation of the first scrambled data value and the second scrambled data value to generate a scramble generator vector associated with the one of the address signals, and - storing the scramble generator vector associated with the one of the address signals; and means for performing a bitwise XOR operation of the scramble sequence and the data.