A sub-system, comprising: an interface circuit in communication with a plurality of physical DRAM memory circuits (1904A, 1904B, 1904N) and a system, the interface circuit operable to interface the physical DRAM memory circuits (1904A, 1904B, 1904N) and the system and autonomously performing a power management operation during a command operation period associated with one or more commands directed to at least a portion of the physical DRAM memory circuits (1904A, 1904B, 1904N), wherein the power management operation is initiated by the interface circuit autonomously, wherein autonomously refers to the ability of the interface circuit to perform the power management operation without necessarily requiring the receipt of an associated power management command from the system, and wherein the interface circuit is further operable to interface the physical DRAM memory circuits to electrically and/or logically resemble at least one larger capacity virtual DRAM memory circuit, wherein the power management operation is performed in association with only a portion, that is identified by the interface circuit as not being accessed by the system, of the physical DRAM memory circuits, wherein the power management operation includes a power saving operation, wherein the power saving operation is a power down operation, and wherein a first command operation period of the virtual DRAM memory circuit is used to accommodate the power management operation by making the first command operation period of the virtual DRAM memory circuit longer than a second command operation period of the physical DRAM memory circuits. an interface circuit in communication with a plurality of physical DRAM memory circuits (1904A, 1904B, 1904N) and a system, the interface circuit operable to interface the physical DRAM memory circuits (1904A, 1904B, 1904N) and the system and autonomously performing a power management operation during a command operation period associated with one or more commands directed to at least a portion of the physical DRAM memory circuits (1904A, 1904B, 1904N), wherein the power management operation is initiated by the interface circuit autonomously, wherein autonomously refers to the ability of the interface circuit to perform the power management operation without necessarily requiring the receipt of an associated power management command from the system, and wherein the interface circuit is further operable to interface the physical DRAM memory circuits to electrically and/or logically resemble at least one larger capacity virtual DRAM memory circuit, wherein the power management operation is performed in association with only a portion, that is identified by the interface circuit as not being accessed by the system, of the physical DRAM memory circuits, wherein the power management operation includes a power saving operation, wherein the power saving operation is a power down operation, and wherein a first command operation period of the virtual DRAM memory circuit is used to accommodate the power management operation by making the first command operation period of the virtual DRAM memory circuit longer than a second command operation period of the physical DRAM memory circuits.