A solar cell, comprising: a substrate (20, 30, 40); an emitter (211, 311), a first passivation film, an antireflection film and a first electrode that are sequentially disposed on an upper surface of the substrate (20, 30, 40); a tunneling layer (221, 321, 421), a retardation layer (222, 322, 422), a field passivation layer (223, 323, 423), a second passivation film and a second electrode that are sequentially disposed on a lower surface of the substrate (20, 30, 40); wherein the retardation layer (222, 322, 422) is configured to retard a migration of a doped ion in the field passivation layer (223, 323, 423) to the substrate (20, 30, 40), and the retardation layer (222, 322, 422) includes: a first retardation sub-layer (222a, 322a, 422a), wherein an orthographic projection of the first retardation sub-layer (222a, 322a, 422a) overlaps with an orthographic projection of the second electrode in a direction perpendicular to the surface of the substrate (20, 30, 40), and a second retardation sub-layer (222b, 322b, 422b), wherein an orthographic projection of the second retardation sub-layer (222b, 322b, 422b) misaligns with the orthographic projection of the second electrode in the direction perpendicular to the surface of the substrate (20, 30, 40), and at least the second retardation sub-layer (222b, 322b, 422b) is configured as an intrinsic semiconductor layer; wherein a thickness of the first retardation sub-layer (222a, 322a, 422a) is smaller than a thickness of the second retardation sub-layer (222b, 322b, 422b) in the direction perpendicular to the lower surface of the substrate (20, 30, 40), and a material of the substrate (20, 30, 40) is a semiconductor. a substrate (20, 30, 40); an emitter (211, 311), a first passivation film, an antireflection film and a first electrode that are sequentially disposed on an upper surface of the substrate (20, 30, 40); a tunneling layer (221, 321, 421), a retardation layer (222, 322, 422), a field passivation layer (223, 323, 423), a second passivation film and a second electrode that are sequentially disposed on a lower surface of the substrate (20, 30, 40); wherein the retardation layer (222, 322, 422) is configured to retard a migration of a doped ion in the field passivation layer (223, 323, 423) to the substrate (20, 30, 40), and the retardation layer (222, 322, 422) includes: a first retardation sub-layer (222a, 322a, 422a), wherein an orthographic projection of the first retardation sub-layer (222a, 322a, 422a) overlaps with an orthographic projection of the second electrode in a direction perpendicular to the surface of the substrate (20, 30, 40), and a second retardation sub-layer (222b, 322b, 422b), wherein an orthographic projection of the second retardation sub-layer (222b, 322b, 422b) misaligns with the orthographic projection of the second electrode in the direction perpendicular to the surface of the substrate (20, 30, 40), and at least the second retardation sub-layer (222b, 322b, 422b) is configured as an intrinsic semiconductor layer; a first retardation sub-layer (222a, 322a, 422a), wherein an orthographic projection of the first retardation sub-layer (222a, 322a, 422a) overlaps with an orthographic projection of the second electrode in a direction perpendicular to the surface of the substrate (20, 30, 40), and a second retardation sub-layer (222b, 322b, 422b), wherein an orthographic projection of the second retardation sub-layer (222b, 322b, 422b) misaligns with the orthographic projection of the second electrode in the direction perpendicular to the surface of the substrate (20, 30, 40), and at least the second retardation sub-layer (222b, 322b, 422b) is configured as an intrinsic semiconductor layer; wherein a thickness of the first retardation sub-layer (222a, 322a, 422a) is smaller than a thickness of the second retardation sub-layer (222b, 322b, 422b) in the direction perpendicular to the lower surface of the substrate (20, 30, 40), and a material of the substrate (20, 30, 40) is a semiconductor.