A X-stage digital-to-analog converter, DAC for converting an N bit digital value to an analog signal, with N,X being integers greater than one, said X-stage DAC comprising: a first capacitive DAC stage that comprises: M first capacitances (C 4, C 3, C 2, C 1) that are connected in parallel and that have first ends and second ends, with M being an integer greater than one; and M first switches (SW MSB) that first, during a sampling phase, connect a selected one of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) to a common node at a same time that remaining ones of said second ends of said M first capacitances (C 4, C 3, C 2, C 1) are connected to one of a voltage reference and a ground, and that second, during an integrating phase subsequent to said sampling phase, connect said selected one of said second ends of said M first capacitances to said ground at a same time that said remaining ones of said second ends of said M first capacitances are connected to said ground; a first amplifier having an input and an output, wherein capacitance values of said M first capacitances (C 4, C 3, C 2, C 1) are substantially equal; and wherein said first ends are connected to said input of said amplifier and disconnected from said ground during said integrating phase, and wherein said first ends are connected to said ground and disconnected from said input of said first amplifier during said sampling phase; and a second capacitive DAC stage comprising M second switches (SW LSB) and a second amplifier, wherein the second amplifier having the output connected to the common node of the first stage, wherein the N/X MSB bits of the N bit digital value are allocated to the M first switches (SW MSB) of the first DAC stage and each respective N/X bits of the N bit digital value are allocated to M switches of each respective further stage, and the N/X LSB bits of the N bit digital value are allocated to the M switches (SW LSB) of the last DAC tage, a control module for controlling said switches (SW MSB, SW LSB) of said X stages, and wherein second ends of capacitances of said second capacitive DAC stage are connected in feedback to the output of the second amplifier during the sampling phase of the first capacitive DAC stage. a first capacitive DAC stage that comprises: M first capacitances (C 4, C 3, C 2, C 1) that are connected in parallel and that have first ends and second ends, with M being an integer greater than one; and M first switches (SW MSB) that first, during a sampling phase, connect a selected one of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) to a common node at a same time that remaining ones of said second ends of said M first capacitances (C 4, C 3, C 2, C 1) are connected to one of a voltage reference and a ground, and that second, during an integrating phase subsequent to said sampling phase, connect said selected one of said second ends of said M first capacitances to said ground at a same time that said remaining ones of said second ends of said M first capacitances are connected to said ground; M first capacitances (C 4, C 3, C 2, C 1) that are connected in parallel and that have first ends and second ends, with M being an integer greater than one; and M first switches (SW MSB) that first, during a sampling phase, connect a selected one of said second ends of said N first capacitances (C 4, C 3, C 2, C 1) to a common node at a same time that remaining ones of said second ends of said M first capacitances (C 4, C 3, C 2, C 1) are connected to one of a voltage reference and a ground, and that second, during an integrating phase subsequent to said sampling phase, connect said selected one of said second ends of said M first capacitances to said ground at a same time that said remaining ones of said second ends of said M first capacitances are connected to said ground; a first amplifier having an input and an output, wherein capacitance values of said M first capacitances (C 4, C 3, C 2, C 1) are substantially equal; and wherein said first ends are connected to said input of said amplifier and disconnected from said ground during said integrating phase, and wherein said first ends are connected to said ground and disconnected from said input of said first amplifier during said sampling phase; and a second capacitive DAC stage comprising M second switches (SW LSB) and a second amplifier, wherein the second amplifier having the output connected to the common node of the first stage, wherein the N/X MSB bits of the N bit digital value are allocated to the M first switches (SW MSB) of the first DAC stage and each respective N/X bits of the N bit digital value are allocated to M switches of each respective further stage, and the N/X LSB bits of the N bit digital value are allocated to the M switches (SW LSB) of the last DAC tage, a control module for controlling said switches (SW MSB, SW LSB) of said X stages, and wherein second ends of capacitances of said second capacitive DAC stage are connected in feedback to the output of the second amplifier during the sampling phase of the first capacitive DAC stage.