A switch (204, 304) comprising: a channel path comprising a first MOS transistor (212, 312) and a second MOS transistor (214, 314) arranged in a back to back configuration with a common source terminal (218, 318) and a common gate terminal (220, 320), wherein a drain terminal of the first MOS transistor defines a first terminal of the channel path and a drain terminal of the second MOS transistor defines a second terminal of the channel path; and control circuitry comprising: a third MOS transistor (216, 316) comprising: a gate terminal coupled to the common source terminal (218, 318); a source terminal coupled to the common gate terminal (220, 320) by only one drive resistor (222, 322); and a drain terminal coupled to a first reference voltage terminal (227, 327); a first current source (225, 325) coupled between the first reference voltage terminal (227, 327) and the common gate terminal (220, 320) and configured to provide a first current; a second current source (224, 324) coupled between the source terminal of the third MOS transistor (216, 316) and a second reference voltage terminal (229, 329), and configured to provide a second current greater than the first current; and a first switching arrangement (230, 330) configured to selectively enable and disable the first current source (225, 325); and a second switching arrangement (234, 334) configured to selectively couple the common source terminal (218, 318) to the second reference voltage terminal (229, 329). a channel path comprising a first MOS transistor (212, 312) and a second MOS transistor (214, 314) arranged in a back to back configuration with a common source terminal (218, 318) and a common gate terminal (220, 320), wherein a drain terminal of the first MOS transistor defines a first terminal of the channel path and a drain terminal of the second MOS transistor defines a second terminal of the channel path; and control circuitry comprising: a third MOS transistor (216, 316) comprising: a gate terminal coupled to the common source terminal (218, 318); a source terminal coupled to the common gate terminal (220, 320) by only one drive resistor (222, 322); and a drain terminal coupled to a first reference voltage terminal (227, 327); a first current source (225, 325) coupled between the first reference voltage terminal (227, 327) and the common gate terminal (220, 320) and configured to provide a first current; a second current source (224, 324) coupled between the source terminal of the third MOS transistor (216, 316) and a second reference voltage terminal (229, 329), and configured to provide a second current greater than the first current; and a first switching arrangement (230, 330) configured to selectively enable and disable the first current source (225, 325); and a second switching arrangement (234, 334) configured to selectively couple the common source terminal (218, 318) to the second reference voltage terminal (229, 329). a third MOS transistor (216, 316) comprising: a gate terminal coupled to the common source terminal (218, 318); a source terminal coupled to the common gate terminal (220, 320) by only one drive resistor (222, 322); and a drain terminal coupled to a first reference voltage terminal (227, 327); a gate terminal coupled to the common source terminal (218, 318); a source terminal coupled to the common gate terminal (220, 320) by only one drive resistor (222, 322); and a drain terminal coupled to a first reference voltage terminal (227, 327); a first current source (225, 325) coupled between the first reference voltage terminal (227, 327) and the common gate terminal (220, 320) and configured to provide a first current; a second current source (224, 324) coupled between the source terminal of the third MOS transistor (216, 316) and a second reference voltage terminal (229, 329), and configured to provide a second current greater than the first current; and a first switching arrangement (230, 330) configured to selectively enable and disable the first current source (225, 325); and a second switching arrangement (234, 334) configured to selectively couple the common source terminal (218, 318) to the second reference voltage terminal (229, 329).