A cell voltage balancing converter system (102, 200) operable to couple to a series of cells (V9-V12, 204-210), the cell voltage balancing converter system comprising: a group of cell interface circuits comprising: a first cell interface circuit (228, 358) operable to couple to a first cell (V12, 204) in the series of cells, and comprising a first balancing bus port (246, 350, 352) operable to couple to a first balancing bus for providing a balancing current between the cell voltage balancing converter system and a second cell voltage balancing converter system; an even number of inner cell interface circuits (230, 232, 360, 362) operable to couple to an even number of cells (206, 208) in the series of cells; and a last cell interface circuit (234, 364) operable to couple to a last cell (V9, 210) in the series of cells, and comprising a second balancing bus port (248, 354, 356) operable to couple to a second balancing bus for providing a balancing current between the cell voltage balancing converter system and a third cell voltage balancing converter system; a balancing transformer (238, 400) coupled to the cell interface circuits, and further coupled to a third balancing bus port (236, 418, 420) operable to couple to the second balancing bus and a fourth balancing bus port (240, 422, 424) operable to couple to a third balancing bus, wherein the balancing transformer is operable to balance voltage across the series of cells; and a gate drive transformer (242, 500) coupled to the cell interface circuits, and operable to receive a clock drive signal and drive a first half of the cell interface circuits (228/232, 358/362) at a first phase of the clock drive signal and drive a second half (230/234, 360/364) of the cell interface circuits at a second phase of the clock drive signal such that two adjacent circuits of the interface circuits are activated with opposite phase. a group of cell interface circuits comprising: a first cell interface circuit (228, 358) operable to couple to a first cell (V12, 204) in the series of cells, and comprising a first balancing bus port (246, 350, 352) operable to couple to a first balancing bus for providing a balancing current between the cell voltage balancing converter system and a second cell voltage balancing converter system; an even number of inner cell interface circuits (230, 232, 360, 362) operable to couple to an even number of cells (206, 208) in the series of cells; and a last cell interface circuit (234, 364) operable to couple to a last cell (V9, 210) in the series of cells, and comprising a second balancing bus port (248, 354, 356) operable to couple to a second balancing bus for providing a balancing current between the cell voltage balancing converter system and a third cell voltage balancing converter system; a first cell interface circuit (228, 358) operable to couple to a first cell (V12, 204) in the series of cells, and comprising a first balancing bus port (246, 350, 352) operable to couple to a first balancing bus for providing a balancing current between the cell voltage balancing converter system and a second cell voltage balancing converter system; an even number of inner cell interface circuits (230, 232, 360, 362) operable to couple to an even number of cells (206, 208) in the series of cells; and a last cell interface circuit (234, 364) operable to couple to a last cell (V9, 210) in the series of cells, and comprising a second balancing bus port (248, 354, 356) operable to couple to a second balancing bus for providing a balancing current between the cell voltage balancing converter system and a third cell voltage balancing converter system; a balancing transformer (238, 400) coupled to the cell interface circuits, and further coupled to a third balancing bus port (236, 418, 420) operable to couple to the second balancing bus and a fourth balancing bus port (240, 422, 424) operable to couple to a third balancing bus, wherein the balancing transformer is operable to balance voltage across the series of cells; and a gate drive transformer (242, 500) coupled to the cell interface circuits, and operable to receive a clock drive signal and drive a first half of the cell interface circuits (228/232, 358/362) at a first phase of the clock drive signal and drive a second half (230/234, 360/364) of the cell interface circuits at a second phase of the clock drive signal such that two adjacent circuits of the interface circuits are activated with opposite phase.