A clock distribution device, the clock distribution device comprising: - a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges, wherein the stacked clock driver circuit comprises a plurality of stacked driver circuits (112, 114) configured to generate output clock signals that swing between the different voltage ranges; and - a load circuit comprising a plurality of load networks of different semiconductor types, wherein each of the load networks is configured to be driven by one of the output clock signals, wherein the stacked driver circuits comprise: - a first-half driver circuit configured to receive a first input clock signal that swings between a voltage threshold and one half of the voltage threshold and to generate a first output clock signal that swings between the voltage threshold and one half of the voltage threshold; and - a second-half driver circuit connected to the first-half driver circuit configured to receive a second input clock signal that swings between one half of the voltage threshold and zero and to generate a second output clock signal that swings between one half of the voltage threshold and zero, - wherein the stacked clock drive circuit is further so configured that the charge recycling comprises that charge from one half (112, 114) of the stacked clock driver circuit is reused to charge the other half (112, 114) of the stacked clock driver circuit. - a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges, wherein the stacked clock driver circuit comprises a plurality of stacked driver circuits (112, 114) configured to generate output clock signals that swing between the different voltage ranges; and - a load circuit comprising a plurality of load networks of different semiconductor types, wherein each of the load networks is configured to be driven by one of the output clock signals, wherein the stacked driver circuits comprise: - a first-half driver circuit configured to receive a first input clock signal that swings between a voltage threshold and one half of the voltage threshold and to generate a first output clock signal that swings between the voltage threshold and one half of the voltage threshold; and - a second-half driver circuit connected to the first-half driver circuit configured to receive a second input clock signal that swings between one half of the voltage threshold and zero and to generate a second output clock signal that swings between one half of the voltage threshold and zero, - a first-half driver circuit configured to receive a first input clock signal that swings between a voltage threshold and one half of the voltage threshold and to generate a first output clock signal that swings between the voltage threshold and one half of the voltage threshold; and - a second-half driver circuit connected to the first-half driver circuit configured to receive a second input clock signal that swings between one half of the voltage threshold and zero and to generate a second output clock signal that swings between one half of the voltage threshold and zero, - wherein the stacked clock drive circuit is further so configured that the charge recycling comprises that charge from one half (112, 114) of the stacked clock driver circuit is reused to charge the other half (112, 114) of the stacked clock driver circuit.