A hardware tessellation unit comprising a patch stack, a sub-division decision logic block, a sub-division logic block and an order flip logic block, wherein: the patch stack is arranged to store patch data describing one or more initial patches and a plurality of sub-patches and to output the patch data, via an output according to a first-in-last-out scheme, the patch stack comprising a first input configured to receive patch data describing initial patches and a second input configured to receive patch data describing sub-patches; the sub-division decision logic block comprises: (i) an input configured to receive patch data from the patch stack, (ii) hardware logic arranged to determine, from the patch data, whether the initial patch or sub-patch for which patch data is received is to be sub-divided, (iii) a first output configured to output the patch data to the sub-division logic block in response to determining that the initial patch or sub-patch is to be sub-divided, and (iv) a second output configured to output the patch data in response to determining that the initial patch or sub-patch is not to be sub-divided; the sub-division logic block comprises: (i) an input configured to receive patch data from the sub-division decision logic block, (ii) hardware logic arranged to sub-divide the initial patch or sub-patch for which patch data is received, and (iii) an output configured to output patch data for each of the sub-patches formed by the sub-division to the patch stack; and the order flip logic block comprises: (i) an input configured to receive sub-patch data from the sub-division logic block, (ii) an output, and (iii) hardware logic arranged to control the order in which sub-patch data is output via the output based on one or more stored values. the patch stack is arranged to store patch data describing one or more initial patches and a plurality of sub-patches and to output the patch data, via an output according to a first-in-last-out scheme, the patch stack comprising a first input configured to receive patch data describing initial patches and a second input configured to receive patch data describing sub-patches; the sub-division decision logic block comprises: (i) an input configured to receive patch data from the patch stack, (ii) hardware logic arranged to determine, from the patch data, whether the initial patch or sub-patch for which patch data is received is to be sub-divided, (iii) a first output configured to output the patch data to the sub-division logic block in response to determining that the initial patch or sub-patch is to be sub-divided, and (iv) a second output configured to output the patch data in response to determining that the initial patch or sub-patch is not to be sub-divided; the sub-division logic block comprises: (i) an input configured to receive patch data from the sub-division decision logic block, (ii) hardware logic arranged to sub-divide the initial patch or sub-patch for which patch data is received, and (iii) an output configured to output patch data for each of the sub-patches formed by the sub-division to the patch stack; and the order flip logic block comprises: (i) an input configured to receive sub-patch data from the sub-division logic block, (ii) an output, and (iii) hardware logic arranged to control the order in which sub-patch data is output via the output based on one or more stored values.