A non-transparent bridge circuit for communicating information in a PCIe network comprising a plurality of switches (801, 802, 803, 804, 805) and a plurality of end-point devices (381, 382, 383, 384, 385, 387, 388, 389, 391, 392, 393, 394, 395, 398, 399), the non-transparent bridge circuit comprising: a first network connection connected to a first switch in a first tree branch of the PCIe network and a second network connection connected to a second switch in a second tree branch of the PCIe network, wherein the non-transparent bridge circuit is assigned a first range of addresses with respect to the first switch and a second range of addresses with respect to the second switch; a processing circuit; and a memory that stores information for the processing circuit; the processing circuit being configured to: receive a first data packet from the first switch (389, 327), the first data packet includes a first payload portion and a first destination address that is within the first range of addresses assigned to the non-transparent bridge; translate the first destination address to a first translated destination address, wherein the first translated destination address belongs to an endpoint device in the second tree branch and connected to the second switch; generate a first modified data packet including the first payload portion and the first translated destination address; and forward the first modified data packet to the second switch for delivery to the endpoint device (381, 382, 383, 384, 385, 387, 388, 389, 391, 392, 393, 394, 395, 398, 399) in the second tree branch. a first network connection connected to a first switch in a first tree branch of the PCIe network and a second network connection connected to a second switch in a second tree branch of the PCIe network, wherein the non-transparent bridge circuit is assigned a first range of addresses with respect to the first switch and a second range of addresses with respect to the second switch; a processing circuit; and a memory that stores information for the processing circuit; the processing circuit being configured to: receive a first data packet from the first switch (389, 327), the first data packet includes a first payload portion and a first destination address that is within the first range of addresses assigned to the non-transparent bridge; translate the first destination address to a first translated destination address, wherein the first translated destination address belongs to an endpoint device in the second tree branch and connected to the second switch; generate a first modified data packet including the first payload portion and the first translated destination address; and forward the first modified data packet to the second switch for delivery to the endpoint device (381, 382, 383, 384, 385, 387, 388, 389, 391, 392, 393, 394, 395, 398, 399) in the second tree branch. receive a first data packet from the first switch (389, 327), the first data packet includes a first payload portion and a first destination address that is within the first range of addresses assigned to the non-transparent bridge; translate the first destination address to a first translated destination address, wherein the first translated destination address belongs to an endpoint device in the second tree branch and connected to the second switch; generate a first modified data packet including the first payload portion and the first translated destination address; and forward the first modified data packet to the second switch for delivery to the endpoint device (381, 382, 383, 384, 385, 387, 388, 389, 391, 392, 393, 394, 395, 398, 399) in the second tree branch.