A method of instruction processing, the method comprising: identifying a load instruction in an instruction sequence executable by a processor as a first occurrence of a qualified load instruction which will encounter a miss in a last-level cache of a cache hierarchy associated with the processor, wherein identifying the load instruction as a first occurrence of the qualified load instruction comprises determining that a number of cycles that the load instruction is waiting for load data in a load queue of the processor is greater than a number of cycles which will be incurred in servicing the load instruction from the last-level cache if there is a hit in the last-level cache for the load data; storing, in a commit buffer,information pertaining to the first occurrence of the qualified load instruction and shadow instructions which follow the qualified load instruction; upon detecting a second occurrence of the qualified load instruction in one of the shadow instructions, constructing an instruction slice from the information in the commit buffer, wherein the instruction slice comprises the second occurrence of the qualified load instruction, shadow instructions of the first occurrence of the qualified load instruction and the first occurrence of the load instruction, to form a slice payload, wherein the slice payload comprises live-in register information and program order information for the instruction slice; pre-executing the instruction slice based on the slice payload to determine an address from which data is to be fetched for executing a third occurrence of the qualified load instruction; and prefetching the data from the address for the third occurrence of the qualified load instruction. identifying a load instruction in an instruction sequence executable by a processor as a first occurrence of a qualified load instruction which will encounter a miss in a last-level cache of a cache hierarchy associated with the processor, wherein identifying the load instruction as a first occurrence of the qualified load instruction comprises determining that a number of cycles that the load instruction is waiting for load data in a load queue of the processor is greater than a number of cycles which will be incurred in servicing the load instruction from the last-level cache if there is a hit in the last-level cache for the load data; storing, in a commit buffer,information pertaining to the first occurrence of the qualified load instruction and shadow instructions which follow the qualified load instruction; upon detecting a second occurrence of the qualified load instruction in one of the shadow instructions, constructing an instruction slice from the information in the commit buffer, wherein the instruction slice comprises the second occurrence of the qualified load instruction, shadow instructions of the first occurrence of the qualified load instruction and the first occurrence of the load instruction, to form a slice payload, wherein the slice payload comprises live-in register information and program order information for the instruction slice; pre-executing the instruction slice based on the slice payload to determine an address from which data is to be fetched for executing a third occurrence of the qualified load instruction; and prefetching the data from the address for the third occurrence of the qualified load instruction.