A method of processing pixel values by pixel processing circuitry comprising: during first and second read phases: - asserting, by a ramp converter (210-i) of the pixel processing circuitry, a first control signal (VC i) for a duration based on a pixel value (ΔV PIXi) read via a column line of a pixel array; and - asserting, by another ramp converter (210-j) of the pixel processing circuitry, a second control signal (VC j) for a duration based on another pixel value (ΔV PIXi) read via another column line of said pixel array; during said first read phase, generating a first digital value as a function of at least said pixel values by controlling, by a first counter control circuit of the pixel processing circuitry based on at least said first and second control signals during said first read phase and on a first set of increment rates, the rate that a first counter (220-i) is incremented, said first set of increment rates defining an increment rate for each of a plurality of states of the first and second control signals; and during said second read phase, generating a second digital value as a function of at least said pixel values by controlling, by said first counter control circuit based on at least said first and second control signals during said second read phase and on a second set of increment rates, the rate that said first counter (220-i) is incremented, said second set of increment rates defining an increment rate for each of a plurality of states of the first and second control signals, wherein said first set of increment rates is different from said second set of increment rates. during first and second read phases: - asserting, by a ramp converter (210-i) of the pixel processing circuitry, a first control signal (VC i) for a duration based on a pixel value (ΔV PIXi) read via a column line of a pixel array; and - asserting, by another ramp converter (210-j) of the pixel processing circuitry, a second control signal (VC j) for a duration based on another pixel value (ΔV PIXi) read via another column line of said pixel array; - asserting, by a ramp converter (210-i) of the pixel processing circuitry, a first control signal (VC i) for a duration based on a pixel value (ΔV PIXi) read via a column line of a pixel array; and - asserting, by another ramp converter (210-j) of the pixel processing circuitry, a second control signal (VC j) for a duration based on another pixel value (ΔV PIXi) read via another column line of said pixel array; during said first read phase, generating a first digital value as a function of at least said pixel values by controlling, by a first counter control circuit of the pixel processing circuitry based on at least said first and second control signals during said first read phase and on a first set of increment rates, the rate that a first counter (220-i) is incremented, said first set of increment rates defining an increment rate for each of a plurality of states of the first and second control signals; and during said second read phase, generating a second digital value as a function of at least said pixel values by controlling, by said first counter control circuit based on at least said first and second control signals during said second read phase and on a second set of increment rates, the rate that said first counter (220-i) is incremented, said second set of increment rates defining an increment rate for each of a plurality of states of the first and second control signals, wherein said first set of increment rates is different from said second set of increment rates.