A successive approximation register, SAR, analog-to-digital converter, ADC, (200, 300), comprising: a sample-and-hold circuit (210, 304) configured to capture an input analog signal and generate a hold sample of the input analog signal; a digital-to-analog converter, DAC, (220, 312) configured to generate an iterative sample corresponding to a digital code; a comparator (230, 308) configured to compare the hold sample and the iterative sample and generate a decision signal based on the comparison; a successive approximation register configured to update the digital code for each iteration based on the decision signal and supply an updated digital code to the DAC; an error detection circuit configured to detect an error condition; and a controller (260, 326) configured to cease iteration operation if the error condition is detected, wherein the successive approximation register includes: an iteration register for storing the digital code; a look-up table for generating a weight to be either added to, and subtracted from, the digital code stored in the integration register to generate digital code candidates; and a multiplexer for outputting one of the digital code candidates to the DAC (220, 312) based on the decision signal, wherein the output from the multiplexer is sent to the iteration register, wherein the error detection circuit includes: candidate registers (332, 334) for storing the digital code candidates; and logic equivalence circuits (338, 340) for determining whether a digital code output from the iteration register is same as one of the digital code candidates for each iteration, wherein the controller (260, 326) is configured to cease the iteration operation if the digital code output from the iteration register is not same as any one of the digital code candidates. a sample-and-hold circuit (210, 304) configured to capture an input analog signal and generate a hold sample of the input analog signal; a digital-to-analog converter, DAC, (220, 312) configured to generate an iterative sample corresponding to a digital code; a comparator (230, 308) configured to compare the hold sample and the iterative sample and generate a decision signal based on the comparison; a successive approximation register configured to update the digital code for each iteration based on the decision signal and supply an updated digital code to the DAC; an error detection circuit configured to detect an error condition; and a controller (260, 326) configured to cease iteration operation if the error condition is detected, wherein the successive approximation register includes: an iteration register for storing the digital code; a look-up table for generating a weight to be either added to, and subtracted from, the digital code stored in the integration register to generate digital code candidates; and a multiplexer for outputting one of the digital code candidates to the DAC (220, 312) based on the decision signal, wherein the output from the multiplexer is sent to the iteration register, an iteration register for storing the digital code; a look-up table for generating a weight to be either added to, and subtracted from, the digital code stored in the integration register to generate digital code candidates; and a multiplexer for outputting one of the digital code candidates to the DAC (220, 312) based on the decision signal, wherein the output from the multiplexer is sent to the iteration register, wherein the error detection circuit includes: candidate registers (332, 334) for storing the digital code candidates; and logic equivalence circuits (338, 340) for determining whether a digital code output from the iteration register is same as one of the digital code candidates for each iteration, wherein the controller (260, 326) is configured to cease the iteration operation if the digital code output from the iteration register is not same as any one of the digital code candidates. candidate registers (332, 334) for storing the digital code candidates; and logic equivalence circuits (338, 340) for determining whether a digital code output from the iteration register is same as one of the digital code candidates for each iteration, wherein the controller (260, 326) is configured to cease the iteration operation if the digital code output from the iteration register is not same as any one of the digital code candidates.