Decision feedback equalizer, DFE, circuitry for operating on a serial data signal (u(n)), the DFE circuitry comprising: circuitry for digitizing a source signal (y(n)) to produce an output signal (y d (n)) of the DFE circuitry; circuitry for delaying the digitized serial data output signal (y d (n)) of the DFE circuitry by passing that signal successively through a plurality of delay circuit elements (60-1, 60-2, 60-3, 60-4,...) so that, at any given time, each of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...) outputs one respective previous bit from the serial data output signal (y d (n)) of the DFE circuitry; circuitry (70-1, 70-2, 70-3,...) for applying a respective scaling factor to an output signal of each of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...) to produce a respective feedback signal; circuitry (40, 40') for combining the serial data signal (u(n)) with the feedback signals to produce the source signal (y(n)); characterized by circuitry (230-1, 230,-2, 230,-3,...) for multiplying an algebraic sign (e^[n]) of an error signal (e[n]) in the digitized output signal of the DFE circuitry with the output signal of a respective one of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...) to produce a respective product signal, wherein the error signal (e[n]) is obtained by comparing the output signal (yd(n)) of the DFE circuitry to the source signal (y(n)); and circuitry (240-1, 240-2, 240-3,...) for integrating over time a respective one of the product signals to produce a respective time-integrated product signal that is used as a respective scaling factor (C1, C2, C3,...) by said circuitry (70-1, 70-2, 70-3,...) for applying a respective scaling factor to the output signal of each of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...). circuitry for digitizing a source signal (y(n)) to produce an output signal (y d (n)) of the DFE circuitry; circuitry for delaying the digitized serial data output signal (y d (n)) of the DFE circuitry by passing that signal successively through a plurality of delay circuit elements (60-1, 60-2, 60-3, 60-4,...) so that, at any given time, each of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...) outputs one respective previous bit from the serial data output signal (y d (n)) of the DFE circuitry; circuitry (70-1, 70-2, 70-3,...) for applying a respective scaling factor to an output signal of each of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...) to produce a respective feedback signal; circuitry (40, 40') for combining the serial data signal (u(n)) with the feedback signals to produce the source signal (y(n)); characterized by circuitry (230-1, 230,-2, 230,-3,...) for multiplying an algebraic sign (e^[n]) of an error signal (e[n]) in the digitized output signal of the DFE circuitry with the output signal of a respective one of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...) to produce a respective product signal, wherein the error signal (e[n]) is obtained by comparing the output signal (yd(n)) of the DFE circuitry to the source signal (y(n)); and circuitry (240-1, 240-2, 240-3,...) for integrating over time a respective one of the product signals to produce a respective time-integrated product signal that is used as a respective scaling factor (C1, C2, C3,...) by said circuitry (70-1, 70-2, 70-3,...) for applying a respective scaling factor to the output signal of each of the delay circuit elements (60-1, 60-2, 60-3, 60-4,...).