A solid state imaging device comprising: a controlling circuit configured to output a right pulse signal (S R) and a left pulse signal (S L); photo-detection means for detecting a background light; a background light elimination circuit configured to output a potential control voltage corresponding to the size of output of the background light detected by the photo-detection means; an imaging region including a plurality of pixels; and a light source for emitting pulse light (L P) in synchronization with the right pulse signal and the left pulse signal, wherein the pulse light reflected (L D) by a surface of a target is incident on the pixels, each of the pixels comprising: a light-sensitive area provided in a semiconductor substrate; right and left first accumulation regions (AR, AL) provided in the semiconductor substrate; right and left first gate electrodes (TX1, TX2) provided on the semiconductor substrate and configured to receive the right pulse signal and the left pulse signal so that potentials between the light-sensitive area and the right and left first accumulation regions (AR, AL) alternately ramp; right and left second accumulation regions (FDR, FDL; BR, BL) provided in the semiconductor substrate, each of the second accumulation regions (FDR, r FDL; BR, BL) being a floating diffusion region; and right and left second gate electrodes (IGR, IGL) that are provided on the semiconductor substrate and are configured to receive the potential control voltage so as to control the height of right and left first potential barriers r (φ IGR, φ IGL) interposed between the right first accumulation region and the right second accumulation region, and the left first accumulation region and the left second accumulation region, respectively, wherein the height of the first potential barriers is increased as a higher output of a background light is detected by the photo-detection means to decrease the amount of carriers flowing into the second accumulation regions from the first accumulation regions after the second accumulation regions are set at a floating level by connecting the second accumulation regions to a power supply potential, and wherein the light-sensitive area serves also as the photo-detection means, the solid state imaging device further comprising control means that outputs an application potential to the second right and left gate electrodes (IGR, IGL) according to an output of the light-sensitive area, and the solid state imaging device being configured to detect the background light in a background light detection period preceding a pulse detection period. a controlling circuit configured to output a right pulse signal (S R) and a left pulse signal (S L); photo-detection means for detecting a background light; a background light elimination circuit configured to output a potential control voltage corresponding to the size of output of the background light detected by the photo-detection means; an imaging region including a plurality of pixels; and a light source for emitting pulse light (L P) in synchronization with the right pulse signal and the left pulse signal, wherein the pulse light reflected (L D) by a surface of a target is incident on the pixels, a light-sensitive area provided in a semiconductor substrate; right and left first accumulation regions (AR, AL) provided in the semiconductor substrate; right and left first gate electrodes (TX1, TX2) provided on the semiconductor substrate and configured to receive the right pulse signal and the left pulse signal so that potentials between the light-sensitive area and the right and left first accumulation regions (AR, AL) alternately ramp; right and left second accumulation regions (FDR, FDL; BR, BL) provided in the semiconductor substrate, each of the second accumulation regions (FDR, r FDL; BR, BL) being a floating diffusion region; and right and left second gate electrodes (IGR, IGL) that are provided on the semiconductor substrate and are configured to receive the potential control voltage so as to control the height of right and left first potential barriers r (φ IGR, φ IGL) interposed between the right first accumulation region and the right second accumulation region, and the left first accumulation region and the left second accumulation region, respectively,