A multi-series battery control system, comprising: battery cell groups (GB1 - GBN) each having a plurality of serially connected battery cells (BC1 - BC4); a plurality of integrated circuits (3A - 3N) each disposed in correspondence to one of the battery cell groups; and a battery control device that exchanges signals with the integrated circuits, wherein: the integrated circuits are in a sequential order connected by a transmission path (52, 54), wherein a signal output from the battery control device is sequentially input and output from an integrated circuit having the first position to an integrated circuit having the last position in said connection order and the signal output from the integrated circuit at the last position is transmitted to the battery control device; and each integrated circuit includes an address setting means that is adapted to (a) receiving a message unique to the integrated circuit different from messages sent to other integrated circuits, and characterised by (b) writing over an initialized address in said integrated circuit with the received unique message and (c) altering the message to a message with which an initialized address of the following integrated circuit in said connection order cannot be overwritten in a step assigned with an ordinal number matching the position of the integrated circuit with regard to the connection order; and addresses of the integrated circuits are individually set in sequence as operation in the step is executed sequentially at each of the integrated circuits. battery cell groups (GB1 - GBN) each having a plurality of serially connected battery cells (BC1 - BC4); a plurality of integrated circuits (3A - 3N) each disposed in correspondence to one of the battery cell groups; and a battery control device that exchanges signals with the integrated circuits, wherein: the integrated circuits are in a sequential order connected by a transmission path (52, 54), wherein a signal output from the battery control device is sequentially input and output from an integrated circuit having the first position to an integrated circuit having the last position in said connection order and the signal output from the integrated circuit at the last position is transmitted to the battery control device; and each integrated circuit includes an address setting means that is adapted to (a) receiving a message unique to the integrated circuit different from messages sent to other integrated circuits, and characterised by (b) writing over an initialized address in said integrated circuit with the received unique message and (c) altering the message to a message with which an initialized address of the following integrated circuit in said connection order cannot be overwritten in a step assigned with an ordinal number matching the position of the integrated circuit with regard to the connection order; and addresses of the integrated circuits are individually set in sequence as operation in the step is executed sequentially at each of the integrated circuits. the integrated circuits are in a sequential order connected by a transmission path (52, 54), wherein a signal output from the battery control device is sequentially input and output from an integrated circuit having the first position to an integrated circuit having the last position in said connection order and the signal output from the integrated circuit at the last position is transmitted to the battery control device; and each integrated circuit includes an address setting means that is adapted to (a) receiving a message unique to the integrated circuit different from messages sent to other integrated circuits, and characterised by (b) writing over an initialized address in said integrated circuit with the received unique message and (c) altering the message to a message with which an initialized address of the following integrated circuit in said connection order cannot be overwritten in a step assigned with an ordinal number matching the position of the integrated circuit with regard to the connection order; and (a) receiving a message unique to the integrated circuit different from messages sent to other integrated circuits, and characterised by (b) writing over an initialized address in said integrated circuit with the received unique message and (c) altering the message to a message with which an initialized address of the following integrated circuit in said connection order cannot be overwritten in a step assigned with an ordinal number matching the position of the integrated circuit with regard to the connection order; and addresses of the integrated circuits are individually set in sequence as operation in the step is executed sequentially at each of the integrated circuits.