A level shifter circuit configured to receive an input signal in a first voltage domain by a differential input circuit and shift the input signal to a second voltage domain, the circuit comprising: a cancellation stage coupled to the differential input circuit, the cancellation stage comprising a first transistor coupled to a first current mirror (72, 74), the differential input circuit comprising a second transistor and third transistor, wherein the first transistor, the second transistor and the third transistor are connected at their source terminals and wherein the first current mirror is configured to mirror a current at a drain terminal of the first transistor onto a first node, FLYN, coupled to the drain terminal of the second transistor and a second node, FLYP, coupled to a drain terminal of the third transistor, wherein the cancellation stage is configured to: sense a first common-mode current generated through the drain terminal of the second transistor and the drain terminal of the third transistor of the differential input circuit in response to a transition of a switching node from a first voltage level to a second voltage level, wherein the transition of the switching node is caused by a transition of the input signal from a first logic state to a second logic state; generate a second common-mode current through the drain terminal of the first transistor, mirror the generated second common-mode current using the first current mirror (72, 74) onto the first node, FLYN, and the second node, FLYP, and thereby combine the second common-mode current with the first common-mode current to provide a reduced common-mode current, and; a gain stage coupled to the cancellation stage, wherein the gain stage is configured to receive a differential-mode current and the reduced common-mode current, wherein the gain stage has a common-mode current gain of less than one and wherein the gain stage comprises a second current mirror circuit cross-coupled to a third current mirror circuit (84, 80, 78), wherein a drain of a diode-connected transistor of the second current mirror (76, 88, 90) is coupled to the first node, FLYN, a drain of the diode-connected transistor of the third current mirror is coupled to the second node FLYP; and an output stage configured to receive both the differential-mode current and the common-mode output current from the gain stage and generate a representation of the input signal shifted to the second voltage domain. a cancellation stage coupled to the differential input circuit, the cancellation stage comprising a first transistor coupled to a first current mirror (72, 74), the differential input circuit comprising a second transistor and third transistor, wherein the first transistor, the second transistor and the third transistor are connected at their source terminals and wherein the first current mirror is configured to mirror a current at a drain terminal of the first transistor onto a first node, FLYN, coupled to the drain terminal of the second transistor and a second node, FLYP, coupled to a drain terminal of the third transistor, wherein the cancellation stage is configured to: sense a first common-mode current generated through the drain terminal of the second transistor and the drain terminal of the third transistor of the differential input circuit in response to a transition of a switching node from a first voltage level to a second voltage level, wherein the transition of the switching node is caused by a transition of the input signal from a first logic state to a second logic state; generate a second common-mode current through the drain terminal of the first transistor, mirror the generated second common-mode current using the first current mirror (72, 74) onto the first node, FLYN, and the second node, FLYP, and thereby combine the second common-mode current with the first common-mode current to provide a reduced common-mode current, and; sense a first common-mode current generated through the drain terminal of the second transistor and the drain terminal of the third transistor of the differential input circuit in response to a transition of a switching node from a first voltage level to a second voltage level, wherein the transition of the switching node is caused by a transition of the input signal from a first logic state to a second logic state; generate a second common-mode current through the drain terminal of the first transistor, mirror the generated second common-mode current using the first current mirror (72, 74) onto the first node, FLYN, and the second node, FLYP, and thereby combine the second common-mode current with the first common-mode current to provide a reduced common-mode current, and; a gain stage coupled to the cancellation stage, wherein the gain stage is configured to receive a differential-mode current and the reduced common-mode current, wherein the gain stage has a common-mode current gain of less than one and wherein the gain stage comprises a second current mirror circuit cross-coupled to a third current mirror circuit (84, 80, 78), wherein a drain of a diode-connected transistor of the second current mirror (76, 88, 90) is coupled to the first node, FLYN, a drain of the diode-connected transistor of the third current mirror is coupled to the second node FLYP; and an output stage configured to receive both the differential-mode current and the common-mode output current from the gain stage and generate a representation of the input signal shifted to the second voltage domain.