A method, comprising: determining, at a processor (204, 304), an electrical connection of an off-board device (236, 308) to program an on-board secure element, the processor and on-board secure element being in communication with one another via a communication bus; the method being characterized by: configuring one or more switches (228a, 228b, 228c, 328a, 328b, 328c) on the communication bus and external to the processor to replace the processor with the off-board device (236, 308) as a master to the on-board secure element (208, 312) thereby enabling the off-board device (236, 308) to begin programming the on-board secure element (208, 312); shorting a clock of the off-board device (236, 308) with a clock of the on-board secure element (208, 312); enabling the off-board device (236, 308) and the on-board secure element (208, 312) to have access to a data line on the communication bus; excluding the processor (204, 304) from using the data line while the off-board device (236, 308) and on-board secure element (208, 312) have access to the data line; monitoring, by the processor (204, 304), a first reset value controlled by the off-board device (236, 308); and updating a second reset value in accordance with the monitored first reset value, the second reset value being transmitted to the on-board secure element (208, 312). determining, at a processor (204, 304), an electrical connection of an off-board device (236, 308) to program an on-board secure element, the processor and on-board secure element being in communication with one another via a communication bus; the method being characterized by: configuring one or more switches (228a, 228b, 228c, 328a, 328b, 328c) on the communication bus and external to the processor to replace the processor with the off-board device (236, 308) as a master to the on-board secure element (208, 312) thereby enabling the off-board device (236, 308) to begin programming the on-board secure element (208, 312); shorting a clock of the off-board device (236, 308) with a clock of the on-board secure element (208, 312); enabling the off-board device (236, 308) and the on-board secure element (208, 312) to have access to a data line on the communication bus; excluding the processor (204, 304) from using the data line while the off-board device (236, 308) and on-board secure element (208, 312) have access to the data line; monitoring, by the processor (204, 304), a first reset value controlled by the off-board device (236, 308); and updating a second reset value in accordance with the monitored first reset value, the second reset value being transmitted to the on-board secure element (208, 312). configuring one or more switches (228a, 228b, 228c, 328a, 328b, 328c) on the communication bus and external to the processor to replace the processor with the off-board device (236, 308) as a master to the on-board secure element (208, 312) thereby enabling the off-board device (236, 308) to begin programming the on-board secure element (208, 312); shorting a clock of the off-board device (236, 308) with a clock of the on-board secure element (208, 312); enabling the off-board device (236, 308) and the on-board secure element (208, 312) to have access to a data line on the communication bus; excluding the processor (204, 304) from using the data line while the off-board device (236, 308) and on-board secure element (208, 312) have access to the data line; monitoring, by the processor (204, 304), a first reset value controlled by the off-board device (236, 308); and updating a second reset value in accordance with the monitored first reset value, the second reset value being transmitted to the on-board secure element (208, 312).