Apparatus for processing data comprising: processing circuitry configured to perform data processing operations, said data processing operations including data access operations; a cache memory configured to store data items to be accessed by said data access operations; coherency control circuitry configured to control coherency between said data items stored within said cache memory and one or more other copies of said data items stored outside said cache memory; a data access buffer configured to buffer a plurality of data accesses to respective data items stored within said cache memory; and access control circuitry responsive to coherency statuses managed by the coherency control circuitry in respect of a plurality of data items subject to respective data access operations to be performed together atomically as an atomic set of data accesses to ensure said coherency statuses for said plurality of data items permit all of said atomic set of data accesses to be performed within said cache memory before said atomic set of data accesses are commenced and performed together atomically; in which the access control circuitry is configured to: determine, in response to the coherency statuses, whether the coherency statuses managed by the coherency control circuitry in respect of the plurality of data items permit all of said atomic set of data accesses to be performed within said cache memory; wherein, before said atomic set of data accesses are commenced and performed together atomically, in absence of the coherency statuses managed by the coherency control circuitry in respect of the plurality of data items permitting all of said atomic set of data accesses to be performed within said cache memory, the coherency control circuitry is configured to request copies of said respective data items with updated coherency statuses that permit all of said atomic set of data accesses to be performed within said cache memory. processing circuitry configured to perform data processing operations, said data processing operations including data access operations; a cache memory configured to store data items to be accessed by said data access operations; coherency control circuitry configured to control coherency between said data items stored within said cache memory and one or more other copies of said data items stored outside said cache memory; a data access buffer configured to buffer a plurality of data accesses to respective data items stored within said cache memory; and access control circuitry responsive to coherency statuses managed by the coherency control circuitry in respect of a plurality of data items subject to respective data access operations to be performed together atomically as an atomic set of data accesses to ensure said coherency statuses for said plurality of data items permit all of said atomic set of data accesses to be performed within said cache memory before said atomic set of data accesses are commenced and performed together atomically; in which the access control circuitry is configured to: determine, in response to the coherency statuses, whether the coherency statuses managed by the coherency control circuitry in respect of the plurality of data items permit all of said atomic set of data accesses to be performed within said cache memory; wherein, before said atomic set of data accesses are commenced and performed together atomically, in absence of the coherency statuses managed by the coherency control circuitry in respect of the plurality of data items permitting all of said atomic set of data accesses to be performed within said cache memory, the coherency control circuitry is configured to request copies of said respective data items with updated coherency statuses that permit all of said atomic set of data accesses to be performed within said cache memory.