A data storage system for a host device having a low power mode and a high power mode, the data storage system comprising: a nonvolatile semiconductor memory interface; a low power, LP, nonvolatile memory that includes a LP hard disk drive, HDD, wherein the LP HDD is configured to communicate with the host device via the nonvolatile semiconductor memory interface; a high power, HP, nonvolatile memory that includes a HP HDD and is configured to communicate with the host device via the nonvolatile semiconductor memory interface; and a drive control module configured to communicate with the semiconductor memory interface, with the LP nonvolatile memory and the HP nonvolatile memory, wherein the drive control module is configured to selectively operate one of the LP nonvolatile memory and the HP nonvolatile memory, wherein the nonvolatile semiconductor memory interface comprises a buffer, a buffer manager, configured to control the buffer, and an interface controller configured to communicate with the buffer manager and perform host command interpretation and data flow control between the host device and the buffer manager, wherein the interface controller comprises: a flash register in communication with a bus, the bus being connected between a line cache and the interface controller, wherein the line cache is connected to a flash memory configured to store firmware code and wherein the flash register is configured to store commands programmed by the host device, a flash controller in communication with the flash register and configured to communicate with a host semiconductor memory interface of the host device, and a flash first-in-first-out wrapper in communication with the flash controller and configured to generate control signals for transferring buffer data to and receiving the buffer data from the buffer manager, wherein a data flow direction of a first-in-first-out buffer in the flash first-in-first-out wrapper is based on the commands stored in the flash register. a nonvolatile semiconductor memory interface; a low power, LP, nonvolatile memory that includes a LP hard disk drive, HDD, wherein the LP HDD is configured to communicate with the host device via the nonvolatile semiconductor memory interface; a high power, HP, nonvolatile memory that includes a HP HDD and is configured to communicate with the host device via the nonvolatile semiconductor memory interface; and a drive control module configured to communicate with the semiconductor memory interface, with the LP nonvolatile memory and the HP nonvolatile memory, wherein the drive control module is configured to selectively operate one of the LP nonvolatile memory and the HP nonvolatile memory, wherein the nonvolatile semiconductor memory interface comprises a buffer, a buffer manager, configured to control the buffer, and an interface controller configured to communicate with the buffer manager and perform host command interpretation and data flow control between the host device and the buffer manager, wherein the interface controller comprises: a flash register in communication with a bus, the bus being connected between a line cache and the interface controller, wherein the line cache is connected to a flash memory configured to store firmware code and wherein the flash register is configured to store commands programmed by the host device, a flash controller in communication with the flash register and configured to communicate with a host semiconductor memory interface of the host device, and a flash first-in-first-out wrapper in communication with the flash controller and configured to generate control signals for transferring buffer data to and receiving the buffer data from the buffer manager, wherein a data flow direction of a first-in-first-out buffer in the flash first-in-first-out wrapper is based on the commands stored in the flash register. a flash register in communication with a bus, the bus being connected between a line cache and the interface controller, wherein the line cache is connected to a flash memory configured to store firmware code and wherein the flash register is configured to store commands programmed by the host device, a flash controller in communication with the flash register and configured to communicate with a host semiconductor memory interface of the host device, and a flash first-in-first-out wrapper in communication with the flash controller and configured to generate control signals for transferring buffer data to and receiving the buffer data from the buffer manager, wherein a data flow direction of a first-in-first-out buffer in the flash first-in-first-out wrapper is based on the commands stored in the flash register.