A semiconductor device comprising: a memory mat including: a plurality of memory cells; a sense amplifier connected to at least one memory cell selected from the plurality of memory cells; a first switch connected via a sense amplifier ground power supply wiring (L_sn) to the sense amplifier and made an ON state when the sense amplifier is operated; a second switch connected via a sense amplifier power supply wiring (L_sp) to the sense amplifier and made an ON state when the sense amplifier is operated; a fourth switch connected via the sense amplifier power supply wiring (L_sp) to the sense amplifier and made an ON state when the sense amplifier is operated; a fourth power supply wiring (L_ss) connected to the first switch; a fifth power supply wiring (Li_dd) connected to the fourth switch; and a sixth power supply wiring (Li_od) connected to the second switch, a first power supply wiring arranged outside the memory mat for supplying a ground voltage (Vss) to the memory mat, the first power supply wiring being connected to the fourth power supply wiring (L_ss); a second power supply wiring (L_dd) arranged outside the memory mat for supplying a first power supply voltage (Vdd) to the memory mat, the second power supply wiring (L_dd) being connected to the fifth power supply wiring (Li_dd); a third power supply wiring (L_od) arranged outside the memory mat for supplying a second power supply voltage (Vod) to the memory mat, the third power supply wiring (L_od) being connected to the sixth power supply wiring (Li_od), the second power supply voltage (Vod) being higher than the first power supply voltage (Vdd); and a third switch arranged outside the memory mat and connected between the second power supply wiring (L_dd) and the third power supply wiring (L_od), wherein the third switch is made an ON state when the sense amplifier is operated, and wherein the third switch is made an OFF state when an operation margin of the sense amplifier is small, and the third switch is made the ON state when the operation margin is not small. a memory mat including: a plurality of memory cells; a sense amplifier connected to at least one memory cell selected from the plurality of memory cells; a first switch connected via a sense amplifier ground power supply wiring (L_sn) to the sense amplifier and made an ON state when the sense amplifier is operated; a second switch connected via a sense amplifier power supply wiring (L_sp) to the sense amplifier and made an ON state when the sense amplifier is operated; a fourth switch connected via the sense amplifier power supply wiring (L_sp) to the sense amplifier and made an ON state when the sense amplifier is operated; a fourth power supply wiring (L_ss) connected to the first switch; a fifth power supply wiring (Li_dd) connected to the fourth switch; and a sixth power supply wiring (Li_od) connected to the second switch, a plurality of memory cells; a sense amplifier connected to at least one memory cell selected from the plurality of memory cells; a first switch connected via a sense amplifier ground power supply wiring (L_sn) to the sense amplifier and made an ON state when the sense amplifier is operated; a second switch connected via a sense amplifier power supply wiring (L_sp) to the sense amplifier and made an ON state when the sense amplifier is operated; a fourth switch connected via the sense amplifier power supply wiring (L_sp) to the sense amplifier and made an ON state when the sense amplifier is operated; a fourth power supply wiring (L_ss) connected to the first switch; a fifth power supply wiring (Li_dd) connected to the fourth switch; and a sixth power supply wiring (Li_od) connected to the second switch, a first power supply wiring arranged outside the memory mat for supplying a ground voltage (Vss) to the memory mat, the first power supply wiring being connected to the fourth power supply wiring (L_ss); a second power supply wiring (L_dd) arranged outside the memory mat for supplying a first power supply voltage (Vdd) to the memory mat, the second power supply wiring (L_dd) being connected to the fifth power supply wiring (Li_dd); a third power supply wiring (L_od) arranged outside the memory mat for supplying a second power supply voltage (Vod) to the memory mat, the third power supply wiring (L_od) being connected to the sixth power supply wiring (Li_od), the second power supply voltage (Vod) being higher than the first power supply voltage (Vdd); and a third switch arranged outside the memory mat and connected between the second power supply wiring (L_dd) and the third power supply wiring (L_od), wherein the third switch is made an ON state when the sense amplifier is operated, and wherein the third switch is made an OFF state when an operation margin of the sense amplifier is small, and the third switch is made the ON state when the operation margin is not small.