An input/output common grounding transformer configured to be connected between a power supply and a load, and composed of a front stage circuit and a rear stage circuit directly connected to the front stage circuit, the transformer comprising: as the front stage circuit, a switch series unit composed of a plurality of switches, as many as a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply, under a condition that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total, one of the points at the both ends is regarded as a ground node, and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and lead the odd nodes to a first output port (Px), the second electrical path being configured to combine even nodes and lead the even nodes to a second output port (Py), the capacitors of the first electrical path and the second electrical path being present so as to correspond in total to at least m-1 nodes excluding the ground node, and a ground electrical path being configured to connect the ground node directly to the first output port (Px) without an interposed capacitor; as the rear stage circuit, an element series unit composed of a pair of semiconductor elements (D11, D12) that are connected in series to each other and are configured perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being connected to the first output port (Px) and to a grounded end of the load to thereby make a common ground throughout the transformer while the other end of the element series unit being connected to the second output port (Py), and inductors (L1, L2) provided on a third electrical path and a fourth electrical path, respectively, the third electrical path being configured to lead a non-grounded end of the element series unit to the grounded end of the load, the fourth electrical path being configured to lead a mutual connection point of the pair of semiconductor elements to a non-grounded end of the load; and a control section configured to control ON/OFF operations of the switches. as the front stage circuit, a switch series unit composed of a plurality of switches, as many as a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply, under a condition that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total, one of the points at the both ends is regarded as a ground node, and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and lead the odd nodes to a first output port (Px), the second electrical path being configured to combine even nodes and lead the even nodes to a second output port (Py), the capacitors of the first electrical path and the second electrical path being present so as to correspond in total to at least m-1 nodes excluding the ground node, and a ground electrical path being configured to connect the ground node directly to the first output port (Px) without an interposed capacitor; as the rear stage circuit, an element series unit composed of a pair of semiconductor elements (D11, D12) that are connected in series to each other and are configured perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being connected to the first output port (Px) and to a grounded end of the load to thereby make a common ground throughout the transformer while the other end of the element series unit being connected to the second output port (Py), and inductors (L1, L2) provided on a third electrical path and a fourth electrical path, respectively, the third electrical path being configured to lead a non-grounded end of the element series unit to the grounded end of the load, the fourth electrical path being configured to lead a mutual connection point of the pair of semiconductor elements to a non-grounded end of the load; and a control section configured to control ON/OFF operations of the switches.