A sensor circuit for measuring a physical quantity, wherein the sensor circuit comprises at least one sensing composition (2; 2 p, 2 n) comprising: a variable resistor (R S; R Sp, R Sn) having a resistance depending on the physical quantity; a first amplifier arrangement (3; 3 p, 3 n) for outputting an output signal (V out; V outp, V outn) based on the resistance of the variable resistor (R S; R Sp, R Sn), wherein the first amplifier arrangement (3; 3 p, 3 n) comprises one field-effect transistor or a plurality of field-effect transistors (MN 1, MN 3; MN 2,MN 4) in a telescopic cascode configuration or a plurality of field-effect transistors (MN 1, MP 3; MN 2,MP 4) in a folded cascode configuration, wherein the first amplifier arrangement (3; 3 p, 3 n) comprises an outer source terminal (S*) and an outer drain terminal (D*), wherein a first terminal of the variable resistor (R S; R Sp, R Sn), is connected to the outer source terminal (S*) of the first amplifier arrangement (3; 3 p, 3 n), such that the field-effect transistor (MN; MN 1; MN 2) having the outer source terminal (S*) and the variable resistor (R S; R Sp, R Sn) form a series circuit; a feedback arrangement (4; 4 p, 4 n) for feedbacking at least a part of the output signal (V out; V outp, V outn) of the first amplifier arrangement (3; 3 p, 3 n), which is obtained at the outer drain terminal (D*) of the amplifier arrangement (3; 3 p, 3 n), to at least one gate terminal of the field-effect transistors (MN; MN 1, MN 3; MN 2,MN 4) of the amplifier arrangement (3; 3 p, 3 n), wherein the feedback arrangement (4; 4 p, 4 n) comprises at least one passive or active electronic component (Z b; Z bp, Z bn; R bp, C bp, R bn, C bn), which connects the outer drain terminal (D*) of the amplifier arrangement (3; 3 p, 3 n) to the gate terminal of the field-effect transistor (MN; MN 1, (MN 3); MN 2,(MN 4)) having the outer source terminal (S*); and a first current source (5; 5 p, 5 n) for biasing the series circuit of the field-effect transistor (MN; MN 1, MN 3; MN 2,MN 4) having the outer source terminal (S*)and the variable resistor (R S; R Sp, R Sn). a variable resistor (R S; R Sp, R Sn) having a resistance depending on the physical quantity; a first amplifier arrangement (3; 3 p, 3 n) for outputting an output signal (V out; V outp, V outn) based on the resistance of the variable resistor (R S; R Sp, R Sn), wherein the first amplifier arrangement (3; 3 p, 3 n) comprises one field-effect transistor or a plurality of field-effect transistors (MN 1, MN 3; MN 2,MN 4) in a telescopic cascode configuration or a plurality of field-effect transistors (MN 1, MP 3; MN 2,MP 4) in a folded cascode configuration, wherein the first amplifier arrangement (3; 3 p, 3 n) comprises an outer source terminal (S*) and an outer drain terminal (D*), wherein a first terminal of the variable resistor (R S; R Sp, R Sn), is connected to the outer source terminal (S*) of the first amplifier arrangement (3; 3 p, 3 n), such that the field-effect transistor (MN; MN 1; MN 2) having the outer source terminal (S*) and the variable resistor (R S; R Sp, R Sn) form a series circuit; a feedback arrangement (4; 4 p, 4 n) for feedbacking at least a part of the output signal (V out; V outp, V outn) of the first amplifier arrangement (3; 3 p, 3 n), which is obtained at the outer drain terminal (D*) of the amplifier arrangement (3; 3 p, 3 n), to at least one gate terminal of the field-effect transistors (MN; MN 1, MN 3; MN 2,MN 4) of the amplifier arrangement (3; 3 p, 3 n), wherein the feedback arrangement (4; 4 p, 4 n) comprises at least one passive or active electronic component (Z b; Z bp, Z bn; R bp, C bp, R bn, C bn), which connects the outer drain terminal (D*) of the amplifier arrangement (3; 3 p, 3 n) to the gate terminal of the field-effect transistor (MN; MN 1, (MN 3); MN 2,(MN 4)) having the outer source terminal (S*); and a first current source (5; 5 p, 5 n) for biasing the series circuit of the field-effect transistor (MN; MN 1, MN 3; MN 2,MN 4) having the outer source terminal (S*)and the variable resistor (R S; R Sp, R Sn).