Method for estimating bandwidth mismatch in a time-interleaved A/D converter comprising a plurality of channels, each channel comprising sampling means for sampling a reference analog input voltage signal (V ref), an array of capacitors connected in parallel and a quantizer arranged for converting said sampled input voltage at first terminals of said capacitors into a digital code, the method comprising - setting second terminals of said capacitors of said plurality of channels to a first state and sampling said reference analog input voltage signal on said capacitors, whereby said reference analog input voltage signal is applied via a first switchable path at first terminals of said capacitors, the method characterised in that it further comprises: - setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff) at said first terminals, - applying said reference analog input voltage signal to said first terminals of said capacitors via a second switchable path, said second path having a given impedance being higher than a known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal, - quantizing said non-zero settling error, thereby obtaining an estimate of the non-zero settling error in each channel of said plurality, - comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch. - setting second terminals of said capacitors of said plurality of channels to a first state and sampling said reference analog input voltage signal on said capacitors, whereby said reference analog input voltage signal is applied via a first switchable path at first terminals of said capacitors, the method characterised in that it further comprises: - setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff) at said first terminals, - applying said reference analog input voltage signal to said first terminals of said capacitors via a second switchable path, said second path having a given impedance being higher than a known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal, - quantizing said non-zero settling error, thereby obtaining an estimate of the non-zero settling error in each channel of said plurality, - comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch. - setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff) at said first terminals, - applying said reference analog input voltage signal to said first terminals of said capacitors via a second switchable path, said second path having a given impedance being higher than a known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal, - quantizing said non-zero settling error, thereby obtaining an estimate of the non-zero settling error in each channel of said plurality, - comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch.