An interface between a master and one or more slave modules comprising: a master; a slave having a set of addressable registers including egress mailbox registers, ingress mailbox registers, and indirect access address registers; a direct memory access, DMA, engine coupled to the master by a first bus and to the slave by a second bus, with the second bus comprising: a set of bi-directional data lines for transmitting data between the slave and the DMA engine, a set of master address lines for transmitting address data from the DMA engine to the slave, a master data strobe for strobing data, a master read/write signal for indicating whether data is to be read from or written to the slave, a set of slave select signals for selecting one of a plurality of slaves connected to the second bus, a slave wait signal asserted by a slave to delay a data transfer, a slave reset signal, a clock output signal, and a clock input signal; where the DMA engine is configured to: perform direct data transfers to the slave by asserting a slave select signal to the slave and transferring data over the set of bi-directional data lines to the slave egress or ingress data registers; and to perform indirect data transfers to slave memory by writing address data over the set of bi-directional data lines to the indirect address register of the slave; and where the slave is configured to utilize its own memory map and the address data to transfer data between a location indicated by the address data and the DMA engine. a master; a slave having a set of addressable registers including egress mailbox registers, ingress mailbox registers, and indirect access address registers; a direct memory access, DMA, engine coupled to the master by a first bus and to the slave by a second bus, with the second bus comprising: a set of bi-directional data lines for transmitting data between the slave and the DMA engine, a set of master address lines for transmitting address data from the DMA engine to the slave, a master data strobe for strobing data, a master read/write signal for indicating whether data is to be read from or written to the slave, a set of slave select signals for selecting one of a plurality of slaves connected to the second bus, a slave wait signal asserted by a slave to delay a data transfer, a slave reset signal, a clock output signal, and a clock input signal; a set of bi-directional data lines for transmitting data between the slave and the DMA engine, a set of master address lines for transmitting address data from the DMA engine to the slave, a master data strobe for strobing data, a master read/write signal for indicating whether data is to be read from or written to the slave, a set of slave select signals for selecting one of a plurality of slaves connected to the second bus, a slave wait signal asserted by a slave to delay a data transfer, a slave reset signal, a clock output signal, and a clock input signal; where the DMA engine is configured to: perform direct data transfers to the slave by asserting a slave select signal to the slave and transferring data over the set of bi-directional data lines to the slave egress or ingress data registers; and to perform indirect data transfers to slave memory by writing address data over the set of bi-directional data lines to the indirect address register of the slave; and where the slave is configured to utilize its own memory map and the address data to transfer data between a location indicated by the address data and the DMA engine. perform direct data transfers to the slave by asserting a slave select signal to the slave and transferring data over the set of bi-directional data lines to the slave egress or ingress data registers; and to perform indirect data transfers to slave memory by writing address data over the set of bi-directional data lines to the indirect address register of the slave; and where the slave is configured to utilize its own memory map and the address data to transfer data between a location indicated by the address data and the DMA engine.