A method for configuring computer storage architectures during a boot operation of a system comprising a bus and a bus clock in communication with the bus, the method comprising, for each of a plurality of groups of lanes of a bus in the system: detecting, by the system, whether a device implementing a first bus interface protocol is coupled to the bus through a connector; programming, by the system, the bus clock to be turned off in response to detecting that no device implementing the first bus interface protocol is coupled to the bus through the connector; reprogramming (109; 137), by the system after programming the bus clock to be off, an Input/Output, IO, buffer connected to the bus in accordance with a second bus interface protocol to connect to a device implementing the second bus interface protocol; detecting, by the system after reprogramming the buffer, whether a device implementing the second bus interface protocol is coupled to the bus through the connector; and initializing, by the system, the device implementing the second bus interface protocol in response to detecting that the device implementing the second bus interface protocol is coupled to the bus through the connector; determining whether the device implementing the first bus interface protocol is a storage device implementing a logical device interface protocol in response to detecting that the device implementing the first bus interface protocol is coupled to the bus in the system through the connector; and initializing the storage device in response to determining that the device implementing the first bus interface protocol also implements a logical device interface protocol, after initializing the storage device in response to determining that the device implementing the first bus interface protocol also implements a logical device interface protocol, reprogramming any unused high speed 10, HSIO, buffers of the buffer to cause the connector to implement the second bus interface protocol, wherein the first bus interface protocol comprises a Peripheral Component Interconnect Express, PCIe, bus interface protocol, wherein the second bus interface protocol comprises a Serial Advanced Technology Attachment, SATA, bus interface protocol, and wherein the logical device interface protocol comprises a Non-Volatile Memory Express, NVMe, logical device bus interface protocol. detecting, by the system, whether a device implementing a first bus interface protocol is coupled to the bus through a connector; programming, by the system, the bus clock to be turned off in response to detecting that no device implementing the first bus interface protocol is coupled to the bus through the connector; reprogramming (109; 137), by the system after programming the bus clock to be off, an Input/Output, IO, buffer connected to the bus in accordance with a second bus interface protocol to connect to a device implementing the second bus interface protocol; detecting, by the system after reprogramming the buffer, whether a device implementing the second bus interface protocol is coupled to the bus through the connector; and initializing, by the system, the device implementing the second bus interface protocol in response to detecting that the device implementing the second bus interface protocol is coupled to the bus through the connector; determining whether the device implementing the first bus interface protocol is a storage device implementing a logical device interface protocol in response to detecting that the device implementing the first bus interface protocol is coupled to the bus in the system through the connector; and initializing the storage device in response to determining that the device implementing the first bus interface protocol also implements a logical device interface protocol,