An apparatus comprising: first and second full voltage level shifters (220a, 220b) configured to receive self-clocked true and complement data input signals, respectively, in a first voltage domain and generate respective voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain; first and second complementary metal oxide semiconductor, CMOS, circuits configured to generate voltage level shifted self-clocked tristated true and complement output signals in the second voltage domain based on the voltage level shifted self-clocked intermediate true and complement signals; and a clamp circuit in the second voltage domain comprising: a first NOR gate with the voltage level shifted self-clocked intermediate true signal and a clamp signal as inputs, with an output of the first NOR gate coupled to a gate of a second n-channel MOS, NMOS, device of the second CMOS circuit and an inverse of the output of the first NOR gate coupled to a gate of a first p-channel MOS, PMOS, device of the first CMOS circuit; and a second NOR gate with the voltage level shifted self-clocked intermediate complement signal and the clamp signal as inputs, with an output of the second NOR gate coupled to a gate of a first n-channel MOS, NMOS, device of the first CMOS circuit and an inverse of the output of the second NOR gate coupled to a gate of a second p-channel MOS, PMOS device of the second CMOS circuit, wherein the clamp circuit is configured to float the voltage level shifted self-clocked tristated true and complement output signals (210b,201a) when the clamp signal is high. first and second full voltage level shifters (220a, 220b) configured to receive self-clocked true and complement data input signals, respectively, in a first voltage domain and generate respective voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain; first and second complementary metal oxide semiconductor, CMOS, circuits configured to generate voltage level shifted self-clocked tristated true and complement output signals in the second voltage domain based on the voltage level shifted self-clocked intermediate true and complement signals; and a clamp circuit in the second voltage domain comprising: a first NOR gate with the voltage level shifted self-clocked intermediate true signal and a clamp signal as inputs, with an output of the first NOR gate coupled to a gate of a second n-channel MOS, NMOS, device of the second CMOS circuit and an inverse of the output of the first NOR gate coupled to a gate of a first p-channel MOS, PMOS, device of the first CMOS circuit; and a second NOR gate with the voltage level shifted self-clocked intermediate complement signal and the clamp signal as inputs, with an output of the second NOR gate coupled to a gate of a first n-channel MOS, NMOS, device of the first CMOS circuit and an inverse of the output of the second NOR gate coupled to a gate of a second p-channel MOS, PMOS device of the second CMOS circuit, a first NOR gate with the voltage level shifted self-clocked intermediate true signal and a clamp signal as inputs, with an output of the first NOR gate coupled to a gate of a second n-channel MOS, NMOS, device of the second CMOS circuit and an inverse of the output of the first NOR gate coupled to a gate of a first p-channel MOS, PMOS, device of the first CMOS circuit; and a second NOR gate with the voltage level shifted self-clocked intermediate complement signal and the clamp signal as inputs, with an output of the second NOR gate coupled to a gate of a first n-channel MOS, NMOS, device of the first CMOS circuit and an inverse of the output of the second NOR gate coupled to a gate of a second p-channel MOS, PMOS device of the second CMOS circuit, wherein the clamp circuit is configured to float the voltage level shifted self-clocked tristated true and complement output signals (210b,201a) when the clamp signal is high.