A method (500, 501, 600, 601) for forming a three-dimensional, 3D, memory device (100, 200), comprising: forming a peripheral circuit (108, 208, 352) on a first substrate; subsequently forming a sacrificial layer (304, 312, 404) on a substrate (101, 201), a P-type doped semiconductor layer (220, 406) having an N-well (221, 407) on the sacrificial layer (304, 312, 404), and a dielectric stack (308, 408) on the P-type doped semiconductor layer (220, 406), wherein the dielectric stack comprises interleaved a stack of dielectric layers (118, 218, 428) and a stack of sacrificial layers (304, 312, 404); forming a channel structure (124, 224, 314, 414) extending vertically through the dielectric stack (308, 408) and the P-type doped semiconductor layer (220, 406), wherein forming the channel structure (124, 224, 314, 414) comprises: etching a channel hole extending vertically through the dielectric stack (308, 408) and the P-type doped semiconductor layer (220, 406), stopping at the sacrificial layer (304, 312, 404); and subsequently depositing a memory film (126, 226) and a semiconductor channel (128, 228, 318, 418) along a sidewall of the channel hole; replacing the sacrificial layers (304, 312, 404) of the dielectric stack (308, 408) to obtain a memory stack (114, 214, 330, 430), wherein the memory stack (114, 214, 330, 430) comprises interleaved a stack dielectric layers (118, 218, 428) and a stack conductive layers (116, 216, 328, 428), such that the channel structure (124, 224, 314, 414) extends vertically through the memory stack (114, 214, 330, 430) and the P-type doped semiconductor layer (220, 406); and bonding the first substrate and the substrate in a face-to-face manner, such that the memory stack (114, 214, 330, 430) is above the peripheral circuit (108, 208, 352); removing the substrate (101, 201) and the sacrificial layer (304, 312, 404) to expose an end of the channel structure (124, 224, 314, 414); and replacing part of the channel structure (124, 224, 314, 414) abutting the P-type doped semiconductor layer (220, 406) with a semiconductor plug (122, 222, 359, 459). forming a peripheral circuit (108, 208, 352) on a first substrate; subsequently forming a sacrificial layer (304, 312, 404) on a substrate (101, 201), a P-type doped semiconductor layer (220, 406) having an N-well (221, 407) on the sacrificial layer (304, 312, 404), and a dielectric stack (308, 408) on the P-type doped semiconductor layer (220, 406), wherein the dielectric stack comprises interleaved a stack of dielectric layers (118, 218, 428) and a stack of sacrificial layers (304, 312, 404); forming a channel structure (124, 224, 314, 414) extending vertically through the dielectric stack (308, 408) and the P-type doped semiconductor layer (220, 406), wherein forming the channel structure (124, 224, 314, 414) comprises: etching a channel hole extending vertically through the dielectric stack (308, 408) and the P-type doped semiconductor layer (220, 406), stopping at the sacrificial layer (304, 312, 404); and subsequently depositing a memory film (126, 226) and a semiconductor channel (128, 228, 318, 418) along a sidewall of the channel hole; replacing the sacrificial layers (304, 312, 404) of the dielectric stack (308, 408) to obtain a memory stack (114, 214, 330, 430), wherein the memory stack (114, 214, 330, 430) comprises interleaved a stack dielectric layers (118, 218, 428) and a stack conductive layers (116, 216, 328, 428), such that the channel structure (124, 224, 314, 414) extends vertically through the memory stack (114, 214, 330, 430) and the P-type doped semiconductor layer (220, 406); and bonding the first substrate and the substrate in a face-to-face manner, such that the memory stack (114, 214, 330, 430) is above the peripheral circuit (108, 208, 352); removing the substrate (101, 201) and the sacrificial layer (304, 312, 404) to expose an end of the channel structure (124, 224, 314, 414); and replacing part of the channel structure (124, 224, 314, 414) abutting the P-type doped semiconductor layer (220, 406) with a semiconductor plug (122, 222, 359, 459). etching a channel hole extending vertically through the dielectric stack (308, 408) and the P-type doped semiconductor layer (220, 406), stopping at the sacrificial layer (304, 312, 404); and subsequently depositing a memory film (126, 226) and a semiconductor channel (128, 228, 318, 418) along a sidewall of the channel hole; replacing the sacrificial layers (304, 312, 404) of the dielectric stack (308, 408) to obtain a memory stack (114, 214, 330, 430), wherein the memory stack (114, 214, 330, 430) comprises interleaved a stack dielectric layers (118, 218, 428) and a stack conductive layers (116, 216, 328, 428), such that the channel structure (124, 224, 314, 414) extends vertically through the memory stack (114, 214, 330, 430) and the P-type doped semiconductor layer (220, 406); and bonding the first substrate and the substrate in a face-to-face manner, such that the memory stack (114, 214, 330, 430) is above the peripheral circuit (108, 208, 352); removing the substrate (101, 201) and the sacrificial layer (304, 312, 404) to expose an end of the channel structure (124, 224, 314, 414); and replacing part of the channel structure (124, 224, 314, 414) abutting the P-type doped semiconductor layer (220, 406) with a semiconductor plug (122, 222, 359, 459).