A processor (100, 200) comprising: - an instruction memory for storing instructions at corresponding instruction memory addresses, each instruction being a data structure that references operands and opcode; - an instruction memory controller for controlling access to the instruction memory; - an evaluation unit for triggering the instruction memory controller to receive instruction data from the instruction memory, evaluating operand and execution dependencies for the operands and the opcode of the instruction data, determining source register identifiers for source data for the operands of the instruction data and destination register identifiers for instruction results generated by execution of the instruction data, and evaluating resource requirements for the execution of the instruction data, wherein the evaluation unit comprises a scoreboard unit configured to track resource and data availability for the opcode of the instruction data, and wherein the evaluation unit is configured to hold the instruction data having an execution dependency and releasing the instruction data when no said execution dependency requirement remains; - an execution unit for dispatching the instruction data to computational resources for execution when the source data for the operands is ready or available and the resources specified by the resource requirements are ready or available; - a termination unit for terminating the execution of the instruction when speculation is resolved and triggering transfer of the instruction results from temporary registers to the destination register; - registers and a data memory for loading the source data required for the operands to execute the instruction data and receiving the instruction results generated by the execution of the instruction data; and - a data memory controller for controlling access to the data memory for the source data and reading from and writing to the data memory based on the opcode of the instruction data and the instruction results. characterized in that the instructions stored in the instruction memory comprise Non Operation instructions, NOPs, for resolving pipeline hazards; wherein the scoreboard unit terminates Non Operation instructions immediately and does not send them to the execution unit for dispatching. - an instruction memory for storing instructions at corresponding instruction memory addresses, each instruction being a data structure that references operands and opcode; - an instruction memory controller for controlling access to the instruction memory; - an evaluation unit for triggering the instruction memory controller to receive instruction data from the instruction memory, evaluating operand and execution dependencies for the operands and the opcode of the instruction data, determining source register identifiers for source data for the operands of the instruction data and destination register identifiers for instruction results generated by execution of the instruction data, and evaluating resource requirements for the execution of the instruction data, wherein the evaluation unit comprises a scoreboard unit configured to track resource and data availability for the opcode of the instruction data, and wherein the evaluation unit is configured to hold the instruction data having an execution dependency and releasing the instruction data when no said execution dependency requirement remains; - an execution unit for dispatching the instruction data to computational resources for execution when the source data for the operands is ready or available and the resources specified by the resource requirements are ready or available; - a termination unit for terminating the execution of the instruction when speculation is resolved and triggering transfer of the instruction results from temporary registers to the destination register; - registers and a data memory for loading the source data required for the operands to execute the instruction data and receiving the instruction results generated by the execution of the instruction data; and - a data memory controller for controlling access to the data memory for the source data and reading from and writing to the data memory based on the opcode of the instruction data and the instruction results.