A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate (9, 10); an array of memory stack structures extending through the alternating stack (32,46) and arranged as rows that extend along a first horizontal direction with a first pitch and are spaced along a second horizontal direction with a second pitch for each pair of neighboring rows, wherein each of the memory stack structures comprises a vertical semiconductor channel, a memory film and a gate dielectric that overlies a top surface of the memory film; drain select gate electrodes (252, 254) laterally surrounding respective rows of the gate dielectrics; and a drain select level isolation strip comprising a dielectric material located between a neighboring pair of the drain select gate electrodes (252, 254); wherein one of the drain select gate electrodes (252, 254) comprises a strip electrode portion including a pair of lengthwise sidewalls that generally extend along the first horizontal direction, and a plurality of cylindrical electrode portions that laterally surround a respective one of the gate dielectrics; wherein the gate dielectric contacts a top surface of the memory film; wherein the memory film and the gate dielectric directly contact an outer sidewall of the vertical semiconductor channel; and wherein the gate dielectric contacts an inner sidewall of a respective one of the plurality of cylindrical electrode portions; wherein the drain select level isolation strip comprises two rows of cylindrical openings therethrough, wherein each of the cylindrical openings laterally surrounds a respective one of a subset of the gate dielectrics that is arranged in two rows that extend along the first horizontal direction; characterized in that a first subset of the cylindrical electrode portions underlies overhanging portions of the drain select level isolation strip and has sidewalls that are vertically coincident with sidewalls of the overhanging portions of the drain select level isolation strip; and a second subset of the cylindrical electrode portions underlies tubular dielectric spacers and has sidewalls that are vertically coincident with sidewalls of the tubular dielectric spacers. an alternating stack of insulating layers and electrically conductive layers located over a substrate (9, 10); an array of memory stack structures extending through the alternating stack (32,46) and arranged as rows that extend along a first horizontal direction with a first pitch and are spaced along a second horizontal direction with a second pitch for each pair of neighboring rows, wherein each of the memory stack structures comprises a vertical semiconductor channel, a memory film and a gate dielectric that overlies a top surface of the memory film; drain select gate electrodes (252, 254) laterally surrounding respective rows of the gate dielectrics; and a drain select level isolation strip comprising a dielectric material located between a neighboring pair of the drain select gate electrodes (252, 254); wherein one of the drain select gate electrodes (252, 254) comprises a strip electrode portion including a pair of lengthwise sidewalls that generally extend along the first horizontal direction, and a plurality of cylindrical electrode portions that laterally surround a respective one of the gate dielectrics; wherein the gate dielectric contacts a top surface of the memory film; wherein the memory film and the gate dielectric directly contact an outer sidewall of the vertical semiconductor channel; and wherein the gate dielectric contacts an inner sidewall of a respective one of the plurality of cylindrical electrode portions; wherein the drain select level isolation strip comprises two rows of cylindrical openings therethrough, wherein each of the cylindrical openings laterally surrounds a respective one of a subset of the gate dielectrics that is arranged in two rows that extend along the first horizontal direction; characterized in that a first subset of the cylindrical electrode portions underlies overhanging portions of the drain select level isolation strip and has sidewalls that are vertically coincident with sidewalls of the overhanging portions of the drain select level isolation strip; and a second subset of the cylindrical electrode portions underlies tubular dielectric spacers and has sidewalls that are vertically coincident with sidewalls of the tubular dielectric spacers.