A method comprising: forming a first stress-inducing layer above a first transistor formed above a substrate, said first stress-inducing layer generating a first type of strain in a channel region of said first transistor; forming a first interlayer dielectric material above said first stress-inducing layer disposed above said first transistor, wherein an average thickness of said first interlayer dielectric material is greater than a thickness of said first stress-inducing layer; forming a second stress-inducing layer above said first interlayer dielectric material disposed above said first transistor, said second stress-inducing layer generating said first type of strain in said channel region of said first transistor; forming said first stress-inducing layer above a second transistor; selectively removing said first stress-inducing layer from above said second transistor; forming a different stress-inducing layer above said second transistor, said different stress-inducing layer generating a second type of strain in said second transistor that differs from said first type of strain; forming a second interlayer dielectric material above said second stress-inducing layer; and forming a contact opening in said first and second interlayer dielectric materials using said first and second stress-inducing layers as etch stop layers; and wherein said first stress-inducing layer, said second stress-inducing layer and said different stress-inducing layer are formed by a first deposition technique having a first gap-filling capability and at least said first interlayer dielectric material is formed by a second deposition technique having a second gap-filling capability that is higher than said first gap-filling capability. forming a first stress-inducing layer above a first transistor formed above a substrate, said first stress-inducing layer generating a first type of strain in a channel region of said first transistor; forming a first interlayer dielectric material above said first stress-inducing layer disposed above said first transistor, wherein an average thickness of said first interlayer dielectric material is greater than a thickness of said first stress-inducing layer; forming a second stress-inducing layer above said first interlayer dielectric material disposed above said first transistor, said second stress-inducing layer generating said first type of strain in said channel region of said first transistor; forming said first stress-inducing layer above a second transistor; selectively removing said first stress-inducing layer from above said second transistor; forming a different stress-inducing layer above said second transistor, said different stress-inducing layer generating a second type of strain in said second transistor that differs from said first type of strain; forming a second interlayer dielectric material above said second stress-inducing layer; and forming a contact opening in said first and second interlayer dielectric materials using said first and second stress-inducing layers as etch stop layers; and wherein said first stress-inducing layer, said second stress-inducing layer and said different stress-inducing layer are formed by a first deposition technique having a first gap-filling capability and at least said first interlayer dielectric material is formed by a second deposition technique having a second gap-filling capability that is higher than said first gap-filling capability.