A method of processing a silicon wafer (100, 150; 200, 250), comprising: providing a flash memory region (101, 151; 201, 251) in the silicon wafer (100, 150; 200, 250); providing complementary metal-oxide-semiconductor device (104, 106, 154, 156; 204, 206, 254, 256) in the flash memory region; and providing a heterojunction bipolar transistor (158, 160; 280, 282) comprising apolysilicon external base (170, 172; 270, 272) and an epitaxial silicon germanium layer on the silicon wafer (100, 150; 200, 250); wherein providing the flash memory region (100, 151; 201, 251) and providing the heterojunction bipolar transistor (158, 160; 280, 282) comprises a step of depositing a single polysilicon layer common to both the flash memory region (100, 151; 201, 251) and the bipolar transistor (158, 160; 280, 282), and wherein providing the heterojunction bipolar transistor (158, 150; 280, 282) further comprises providing a vertical NPN bipolar transistor (158; 258) and a vertical PNP bipolar transistor (160; 260), and the step of depositing the single polysilicon layer further comprises a first polysilicon layer depositing step common to both the complementary metal-oxide-semiconductor device in the flash memory region (101,151; 201, 251) and the vertical NPN bipolar transistor (158; 258), and a second polysilicon layer depositing step common to both the flash memory region (101, 151; 201, 251) and the vertical PNP bipolar transistor (160; 260). providing a flash memory region (101, 151; 201, 251) in the silicon wafer (100, 150; 200, 250); providing complementary metal-oxide-semiconductor device (104, 106, 154, 156; 204, 206, 254, 256) in the flash memory region; and providing a heterojunction bipolar transistor (158, 160; 280, 282) comprising apolysilicon external base (170, 172; 270, 272) and an epitaxial silicon germanium layer on the silicon wafer (100, 150; 200, 250); wherein providing the flash memory region (100, 151; 201, 251) and providing the heterojunction bipolar transistor (158, 160; 280, 282) comprises a step of depositing a single polysilicon layer common to both the flash memory region (100, 151; 201, 251) and the bipolar transistor (158, 160; 280, 282), and wherein providing the heterojunction bipolar transistor (158, 150; 280, 282) further comprises providing a vertical NPN bipolar transistor (158; 258) and a vertical PNP bipolar transistor (160; 260), and the step of depositing the single polysilicon layer further comprises a first polysilicon layer depositing step common to both the complementary metal-oxide-semiconductor device in the flash memory region (101,151; 201, 251) and the vertical NPN bipolar transistor (158; 258), and a second polysilicon layer depositing step common to both the flash memory region (101, 151; 201, 251) and the vertical PNP bipolar transistor (160; 260). a first polysilicon layer depositing step common to both the complementary metal-oxide-semiconductor device in the flash memory region (101,151; 201, 251) and the vertical NPN bipolar transistor (158; 258), and a second polysilicon layer depositing step common to both the flash memory region (101, 151; 201, 251) and the vertical PNP bipolar transistor (160; 260).