A battery pack monitoring system, comprising: a master microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the master microprocessor operably coupled to a communication bus; a first microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the first microprocessor operably coupled to the communication bus; a second microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the second microprocessor operably coupled to the communication bus; a first over-voltage protection circuit electrically coupled between the output port of the master microprocessor and the input port of the first microprocessor; a second over-voltage protection circuit electrically coupled between the output port of the first microprocessor and the input port of the second microprocessor; the master microprocessor configured to output a first signal from the output port thereof to induce the input port of the first microprocessor to have a first low logic voltage, the master microprocessor further configured to send a message having a first binary ID from the communication bus port thereof through the communication bus after outputting the first signal; the first microprocessor configured to receive the first binary ID at the communication bus port thereof and to store the first binary ID in a non-volatile memory of the first microprocessor when the input port of the first microprocessor has the first low logic voltage the first microprocessor further configured to send a confirmation message from the communication bus port thereof through the communication bus to the communication bus port of the master microprocessor after storing the first binary ID in the non-volatile memory of the first microprocessor; the first microprocessor further configured to output a second signal from the output port thereof to induce the input port of the second microprocessor to have a second low logic voltage after the input port of the first microprocessor has the first low logic voltage; the master microprocessor further configured to send a message having a second binary ID from the communication bus port thereof through the communication bus after receiving the confirmation message from the first microprocessor; and the second microprocessor configured to receive the second binary ID at the communication bus port thereof and to store the second binary ID in a non-volatile memory of the second microprocessor when the input port of the second microprocessor has the second low logic voltage. a master microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the master microprocessor operably coupled to a communication bus; a first microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the first microprocessor operably coupled to the communication bus; a second microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the second microprocessor operably coupled to the communication bus; a first over-voltage protection circuit electrically coupled between the output port of the master microprocessor and the input port of the first microprocessor; a second over-voltage protection circuit electrically coupled between the output port of the first microprocessor and the input port of the second microprocessor; the master microprocessor configured to output a first signal from the output port thereof to induce the input port of the first microprocessor to have a first low logic voltage, the master microprocessor further configured to send a message having a first binary ID from the communication bus port thereof through the communication bus after outputting the first signal; the first microprocessor configured to receive the first binary ID at the communication bus port thereof and to store the first binary ID in a non-volatile memory of the first microprocessor when the input port of the first microprocessor has the first low logic voltage the first microprocessor further configured to send a confirmation message from the communication bus port thereof through the communication bus to the communication bus port of the master microprocessor after storing the first binary ID in the non-volatile memory of the first microprocessor; the first microprocessor further configured to output a second signal from the output port thereof to induce the input port of the second microprocessor to have a second low logic voltage after the input port of the first microprocessor has the first low logic voltage; the master microprocessor further configured to send a message having a second binary ID from the communication bus port thereof through the communication bus after receiving the confirmation message from the first microprocessor; and the second microprocessor configured to receive the second binary ID at the communication bus port thereof and to store the second binary ID in a non-volatile memory of the second microprocessor when the input port of the second microprocessor has the second low logic voltage.