A digital-to-analog converter having at least a set of current sources, a respective pair of differential branches with two transistors (T1, T2) connected to each current source, a register activated at a clock frequency F and receiving a digital data element to be converted, the register controlling the transistors of the pairs of branches to switch the currents from the current sources individually into one or other of the differential branches of each pair as a function of the value of the digital data element to be converted, and two resistive loads (R1, R2) receiving the currents of the differential branches to produce a differential output electrical signal whose analog value represents the digital data element to be converted, the converter also having a switching circuit interposed between the differential branches and the resistive loads, the switching circuit comprising a first switching circuit (Q1a, Q1b, Q2a, Q2b) suitable either for enabling transmission toward the resistive loads of the currents of the differential branches or for diverting said currents away from the resistive loads, characterized in that: - the first switching circuit is configured to establish diverting periodically at the clock frequency, followed by an enabling operation, the duty cycle between the enabling time and the clock period being in the range from 0.7 to 0.95, - the switching circuit further comprises a second switching stage (Q'1a, Q'1b, Q'2a, Q'2b) suitable for allowing either a direct link or a cross link between the differential branches and the resistive loads, and means suitable for: providing signals (RSH, RSHb) to the first switching stage to control the enabling and diverting of the currents, providing signals (Rf, RFb)) to the second switching stage to connect the differential branches to the resistive loads directly during a first half of the enabling time and in a crossed manner during the second half of the enabling time, so as to reverse the sign of the electrical output signal between the two halves of this time. - the first switching circuit is configured to establish diverting periodically at the clock frequency, followed by an enabling operation, the duty cycle between the enabling time and the clock period being in the range from 0.7 to 0.95, - the switching circuit further comprises a second switching stage (Q'1a, Q'1b, Q'2a, Q'2b) suitable for allowing either a direct link or a cross link between the differential branches and the resistive loads, and means suitable for: providing signals (RSH, RSHb) to the first switching stage to control the enabling and diverting of the currents, providing signals (Rf, RFb)) to the second switching stage to connect the differential branches to the resistive loads directly during a first half of the enabling time and in a crossed manner during the second half of the enabling time, so as to reverse the sign of the electrical output signal between the two halves of this time. providing signals (RSH, RSHb) to the first switching stage to control the enabling and diverting of the currents, providing signals (Rf, RFb)) to the second switching stage to connect the differential branches to the resistive loads directly during a first half of the enabling time and in a crossed manner during the second half of the enabling time, so as to reverse the sign of the electrical output signal between the two halves of this time.