An integrated circuit, comprising: an input/output also called I/O bank comprising a plurality of byte clock groups; wherein each of the plurality of byte clock groups comprises a phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data; wherein each byte clock group further comprises: an output first-in-first-out also called FIFO memory within the I/O bank comprising at least two asynchronously clocked ports, wherein an input port of the output FIFO memory is clocked at a first operating frequency and an output port of the output FIFO is clocked by the phaser at a second operating frequency higher than the first operating frequency corresponding to the source synchronous device; and an input FIFO memory within the I/O bank comprising at least two asynchronously clocked ports, wherein an output port of the input FIFO memory is clocked at the first operating frequency and an input port of the input FIFO memory is clocked by the phaser at the second operating frequency; a plurality of input serializer/deserializers also called SERDES within the I/O bank configured to deserialize data received from the source synchronous device and provide the deserialized data to the input port of the input FIFO memory; and a plurality of output SERDES within the I/O bank configured to serialize data received from the output port of the output FIFO memory to be output to the source synchronous device, wherein the phaser within each of the plurality of byte clock groups is configured to provide clock signals at the second operating frequency to each of the plurality of input SERDES and each of the plurality of output SERDES of the byte clock group. an input/output also called I/O bank comprising a plurality of byte clock groups; wherein each of the plurality of byte clock groups comprises a phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data; wherein each byte clock group further comprises: an output first-in-first-out also called FIFO memory within the I/O bank comprising at least two asynchronously clocked ports, wherein an input port of the output FIFO memory is clocked at a first operating frequency and an output port of the output FIFO is clocked by the phaser at a second operating frequency higher than the first operating frequency corresponding to the source synchronous device; and an input FIFO memory within the I/O bank comprising at least two asynchronously clocked ports, wherein an output port of the input FIFO memory is clocked at the first operating frequency and an input port of the input FIFO memory is clocked by the phaser at the second operating frequency; a plurality of input serializer/deserializers also called SERDES within the I/O bank configured to deserialize data received from the source synchronous device and provide the deserialized data to the input port of the input FIFO memory; and a plurality of output SERDES within the I/O bank configured to serialize data received from the output port of the output FIFO memory to be output to the source synchronous device, wherein the phaser within each of the plurality of byte clock groups is configured to provide clock signals at the second operating frequency to each of the plurality of input SERDES and each of the plurality of output SERDES of the byte clock group. an output first-in-first-out also called FIFO memory within the I/O bank comprising at least two asynchronously clocked ports, wherein an input port of the output FIFO memory is clocked at a first operating frequency and an output port of the output FIFO is clocked by the phaser at a second operating frequency higher than the first operating frequency corresponding to the source synchronous device; and an input FIFO memory within the I/O bank comprising at least two asynchronously clocked ports, wherein an output port of the input FIFO memory is clocked at the first operating frequency and an input port of the input FIFO memory is clocked by the phaser at the second operating frequency; a plurality of input serializer/deserializers also called SERDES within the I/O bank configured to deserialize data received from the source synchronous device and provide the deserialized data to the input port of the input FIFO memory; and a plurality of output SERDES within the I/O bank configured to serialize data received from the output port of the output FIFO memory to be output to the source synchronous device, wherein the phaser within each of the plurality of byte clock groups is configured to provide clock signals at the second operating frequency to each of the plurality of input SERDES and each of the plurality of output SERDES of the byte clock group.