A nonvolatile latch circuit comprising: a first element; a second element; a first transistor; a second transistor; a third transistor; and a capacitor, wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal, wherein one of a source and a drain of the first transistor is electrically connected to the second wiring and the other of the source and the drain of the first transistor is electrically connected to one of the electrodes of the capacitor, the nonvolatile latch circuit being characterized in that a channel formation region of the first transistor includes an oxide semiconductor, and the other of the source and the drain of the first transistor is electrically connected to the one of electrodes of the capacitor, a gate of the second transistor, and a gate of the third transistor, one of a source and a drain of the second transistor is electrically connected to the first wiring and wherein the other of the source and drain of the second transistor is electrically connected to a low-level power source voltage, one of a source and a drain of the third transistor is electrically connected to the first wiring and wherein the other of the source and drain of the third transistor is electrically connected to a high-level power source voltage, the other electrode of the capacitor is configured to be supplied with a potential (Vc), and the second transistor and the third transistor form an inverter. a first element; a second element; a first transistor; a second transistor; a third transistor; and a capacitor, wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal, wherein one of a source and a drain of the first transistor is electrically connected to the second wiring and the other of the source and the drain of the first transistor is electrically connected to one of the electrodes of the capacitor, the nonvolatile latch circuit being characterized in that a channel formation region of the first transistor includes an oxide semiconductor, and the other of the source and the drain of the first transistor is electrically connected to the one of electrodes of the capacitor, a gate of the second transistor, and a gate of the third transistor, one of a source and a drain of the second transistor is electrically connected to the first wiring and wherein the other of the source and drain of the second transistor is electrically connected to a low-level power source voltage, one of a source and a drain of the third transistor is electrically connected to the first wiring and wherein the other of the source and drain of the third transistor is electrically connected to a high-level power source voltage, the other electrode of the capacitor is configured to be supplied with a potential (Vc), and the second transistor and the third transistor form an inverter.