An enhanced Doherty amplifier comprising: • a power splitter (32, 32A, and 32B) configured to receive an input signal and split the input signal into a carrier signal provided at a carrier splitter output and a peaking signal provided at a peaking splitter output; • a Doherty combining node (40, 40A, and 40B); • a carrier path comprising: • a carrier power amplifier circuitry (36, 36A, and 36B); • a carrier input network (34, 34A, and 34B) coupled between the carrier splitter output and the carrier power amplifier circuitry; and • a carrier output network (38, 38A, and 38B) coupled with the carrier power amplifier circuitry and the Doherty combining node; and • a peaking path comprising: • peaking power amplifier circuitry (46, 46A, and 46B); • a peaking input network (44, 44A, and 44B) coupled between the peaking splitter output and the peaking power amplifier circuitry; and • a peaking output network (48, 48A, and 48B) coupled with the peaking power amplifier circuitry and the Doherty combining node; • wherein the carrier and peaking input networks are each configured to impose phase shifts causing the peaking signal to lag the carrier signal by approximately 90 degrees when the carrier and peaking signals are respectively presented to the carrier and peaking power amplifier circuitries and the carrier and peaking output networks are each configured to respectively impose carrier and peaking phase offsets compensating the respective phase offset of the input network causing the peaking and carrier signals to arrive at the Doherty combining node for reactive combining to generate an output signal. • a power splitter (32, 32A, and 32B) configured to receive an input signal and split the input signal into a carrier signal provided at a carrier splitter output and a peaking signal provided at a peaking splitter output; • a Doherty combining node (40, 40A, and 40B); • a carrier path comprising: • a carrier power amplifier circuitry (36, 36A, and 36B); • a carrier input network (34, 34A, and 34B) coupled between the carrier splitter output and the carrier power amplifier circuitry; and • a carrier output network (38, 38A, and 38B) coupled with the carrier power amplifier circuitry and the Doherty combining node; and • a carrier power amplifier circuitry (36, 36A, and 36B); • a carrier input network (34, 34A, and 34B) coupled between the carrier splitter output and the carrier power amplifier circuitry; and • a carrier output network (38, 38A, and 38B) coupled with the carrier power amplifier circuitry and the Doherty combining node; and • a peaking path comprising: • peaking power amplifier circuitry (46, 46A, and 46B); • a peaking input network (44, 44A, and 44B) coupled between the peaking splitter output and the peaking power amplifier circuitry; and • a peaking output network (48, 48A, and 48B) coupled with the peaking power amplifier circuitry and the Doherty combining node; • peaking power amplifier circuitry (46, 46A, and 46B); • a peaking input network (44, 44A, and 44B) coupled between the peaking splitter output and the peaking power amplifier circuitry; and • a peaking output network (48, 48A, and 48B) coupled with the peaking power amplifier circuitry and the Doherty combining node; • wherein the carrier and peaking input networks are each configured to impose phase shifts causing the peaking signal to lag the carrier signal by approximately 90 degrees when the carrier and peaking signals are respectively presented to the carrier and peaking power amplifier circuitries and the carrier and peaking output networks are each configured to respectively impose carrier and peaking phase offsets compensating the respective phase offset of the input network causing the peaking and carrier signals to arrive at the Doherty combining node for reactive combining to generate an output signal.