Data processing apparatus comprising: a single instruction multiple data register file, wherein each register of the single instruction multiple data register file has a bit width of m bits; and single instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; wherein said single instruction multiple data processing circuitry is configured to be controlled by a further program instruction to perform a further processing operation upon a vector data value comprising a sequence of data words held within an input operand register of said single instruction multiple data register file to produce an output operand stored within an output operand register of said single instruction multiple data register file, said output operand having a first portion with a value dependent upon all data words within said sequence of data words, said further program instruction is a program instruction supporting a secure hash algorithm that controls said single instruction multiple data processing circuitry to generate an intermediate hash value as said output operand in dependence upon said sequence of data words forming said vector data value, said program instruction supporting a secure hash algorithm performs an iterative processing operation consuming successive words of said sequence of data words and at least portions of intermediate hash values produced in response to a previous instance of said program instruction supporting a secure hash algorithm to generate said intermediate hash value; the further program instruction is of a triadic RISC instruction form, for generating an intermediate hash value having a bit width h > m; and the further program instruction specifies, as input registers: two registers of the single instruction multiple data register file for storing the portions of intermediate hash values produced in response to a previous instance of said program instruction, one of these two input registers being used as said output operand register for storing at least part of said generated intermediate hash value as said output operand; and a third register as an input operand register storing the sequence of data words. a single instruction multiple data register file, wherein each register of the single instruction multiple data register file has a bit width of m bits; and single instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; wherein said single instruction multiple data processing circuitry is configured to be controlled by a further program instruction to perform a further processing operation upon a vector data value comprising a sequence of data words held within an input operand register of said single instruction multiple data register file to produce an output operand stored within an output operand register of said single instruction multiple data register file, said output operand having a first portion with a value dependent upon all data words within said sequence of data words, said further program instruction is a program instruction supporting a secure hash algorithm that controls said single instruction multiple data processing circuitry to generate an intermediate hash value as said output operand in dependence upon said sequence of data words forming said vector data value, said program instruction supporting a secure hash algorithm performs an iterative processing operation consuming successive words of said sequence of data words and at least portions of intermediate hash values produced in response to a previous instance of said program instruction supporting a secure hash algorithm to generate said intermediate hash value; the further program instruction is of a triadic RISC instruction form, for generating an intermediate hash value having a bit width h > m; and the further program instruction specifies, as input registers: two registers of the single instruction multiple data register file for storing the portions of intermediate hash values produced in response to a previous instance of said program instruction, one of these two input registers being used as said output operand register for storing at least part of said generated intermediate hash value as said output operand; and a third register as an input operand register storing the sequence of data words. two registers of the single instruction multiple data register file for storing the portions of intermediate hash values produced in response to a previous instance of said program instruction, one of these two input registers being used as said output operand register for storing at least part of said generated intermediate hash value as said output operand; and a third register as an input operand register storing the sequence of data words.