Interconnect circuitry for a data processing apparatus, said interconnect circuitry being configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device (20, 22, 24, 26); at least one output for outputting transaction requests to said at least one recipient device (30, 32, 34, 36); at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry (70, 76) for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; characterised in that said control circuitry comprises a response signal generator (80, 82), said response signal generator being responsive to receipt of at least some of said barrier transaction requests to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further. at least one input for receiving transaction requests from said at least one initiator device (20, 22, 24, 26); at least one output for outputting transaction requests to said at least one recipient device (30, 32, 34, 36); at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry (70, 76) for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; characterised in that said control circuitry comprises a response signal generator (80, 82), said response signal generator being responsive to receipt of at least some of said barrier transaction requests to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further.