An electronic system, comprising: a processor, and a flash memory device coupled to the processor, wherein the flash memory device includes: a flash memory array having a plurality of flash memory cells with a silicon-on-insulator structure (410, 411); and control circuitry for decoding signals provided by the processor to control the data read, data write, and data erase, operations of the memory array; each flash memory cell of the flash memory array comprising: a drain region comprising a first doped material formed in the silicon-on-insulator; a source region comprising the first doped material formed in the silicon-on-insulator; a body region located between the drain region and the source region; a control gate formed above and substantially between the drain and source regions (401, 402); and a charge storage region formed above and between the source region and the drain region, and located between said control gate and the body region; characterised in that: each flash memory cell has an extractor contact (501, 502), of second doped material, coupled to the body region; and the extractor contact (501, 502) is configured to receive a voltage to reverse bias the extractor contact (501, 502) during an erase operation of the flash memory cell, and to remove minority carriers from the body region when the extractor contact (501, 502) is reverse biased. a processor, and a flash memory device coupled to the processor, wherein the flash memory device includes: a flash memory array having a plurality of flash memory cells with a silicon-on-insulator structure (410, 411); and control circuitry for decoding signals provided by the processor to control the data read, data write, and data erase, operations of the memory array; a flash memory array having a plurality of flash memory cells with a silicon-on-insulator structure (410, 411); and control circuitry for decoding signals provided by the processor to control the data read, data write, and data erase, operations of the memory array; each flash memory cell of the flash memory array comprising: a drain region comprising a first doped material formed in the silicon-on-insulator; a source region comprising the first doped material formed in the silicon-on-insulator; a body region located between the drain region and the source region; a control gate formed above and substantially between the drain and source regions (401, 402); and a charge storage region formed above and between the source region and the drain region, and located between said control gate and the body region; a drain region comprising a first doped material formed in the silicon-on-insulator; a source region comprising the first doped material formed in the silicon-on-insulator; a body region located between the drain region and the source region; a control gate formed above and substantially between the drain and source regions (401, 402); and a charge storage region formed above and between the source region and the drain region, and located between said control gate and the body region; characterised in that: each flash memory cell has an extractor contact (501, 502), of second doped material, coupled to the body region; and the extractor contact (501, 502) is configured to receive a voltage to reverse bias the extractor contact (501, 502) during an erase operation of the flash memory cell, and to remove minority carriers from the body region when the extractor contact (501, 502) is reverse biased. each flash memory cell has an extractor contact (501, 502), of second doped material, coupled to the body region; and the extractor contact (501, 502) is configured to receive a voltage to reverse bias the extractor contact (501, 502) during an erase operation of the flash memory cell, and to remove minority carriers from the body region when the extractor contact (501, 502) is reverse biased.