A memory, comprising: two or more ports, each port of the two or more ports comprising one or more regions of memory and control circuitry for controlling access to the one or more regions of memory; wherein the control circuitry of a first port of the two or more ports is configured to receive a first command from an external control bus that is external to the memory; characterised in that the control circuitry of the first port is configured to forward the first command to a first input of the control circuitry of one or more additional ports of the two or more ports through an interport control bus coupled between the control circuitry of the first port and the control circuitry of the one or more additional ports, wherein the control circuitry of each of the one or more additional ports is separate from the control circuitry of the first port; wherein the control circuitry of the one or more additional ports is configured to select whether to respond to the first command forwarded from the control circuitry of the first port or to a second command to be received at a second input of the control circuitry of the one or more additional ports; and wherein the control circuitry of the first port is configured to process the first command, wherein the control circuitry of the one or more additional ports is configured to process the first command, when the control circuitry of the one or more additional ports selects to respond to the first command forwarded to the first input from the control circuitry of the first port, and wherein the control circuitry of the first port and the control circuitry of the one or more additional ports are further configured, when the control circuitry of the one or more additional ports selects to respond to the first command forwarded from the control circuitry of the first port, to concurrently access regions of memory of the first port and the one or more additional ports. two or more ports, each port of the two or more ports comprising one or more regions of memory and control circuitry for controlling access to the one or more regions of memory; wherein the control circuitry of a first port of the two or more ports is configured to receive a first command from an external control bus that is external to the memory; characterised in that the control circuitry of the first port is configured to forward the first command to a first input of the control circuitry of one or more additional ports of the two or more ports through an interport control bus coupled between the control circuitry of the first port and the control circuitry of the one or more additional ports, wherein the control circuitry of each of the one or more additional ports is separate from the control circuitry of the first port; wherein the control circuitry of the one or more additional ports is configured to select whether to respond to the first command forwarded from the control circuitry of the first port or to a second command to be received at a second input of the control circuitry of the one or more additional ports; and wherein the control circuitry of the first port is configured to process the first command, wherein the control circuitry of the one or more additional ports is configured to process the first command, when the control circuitry of the one or more additional ports selects to respond to the first command forwarded to the first input from the control circuitry of the first port, and wherein the control circuitry of the first port and the control circuitry of the one or more additional ports are further configured, when the control circuitry of the one or more additional ports selects to respond to the first command forwarded from the control circuitry of the first port, to concurrently access regions of memory of the first port and the one or more additional ports. wherein the control circuitry of a first port of the two or more ports is configured to receive a first command from an external control bus that is external to the memory; characterised in that the control circuitry of the first port is configured to forward the first command to a first input of the control circuitry of one or more additional ports of the two or more ports through an interport control bus coupled between the control circuitry of the first port and the control circuitry of the one or more additional ports, wherein the control circuitry of each of the one or more additional ports is separate from the control circuitry of the first port; wherein the control circuitry of the one or more additional ports is configured to select whether to respond to the first command forwarded from the control circuitry of the first port or to a second command to be received at a second input of the control circuitry of the one or more additional ports; and wherein the control circuitry of the first port is configured to process the first command, wherein the control circuitry of the one or more additional ports is configured to process the first command, when the control circuitry of the one or more additional ports selects to respond to the first command forwarded to the first input from the control circuitry of the first port, and wherein the control circuitry of the first port and the control circuitry of the one or more additional ports are further configured, when the control circuitry of the one or more additional ports selects to respond to the first command forwarded from the control circuitry of the first port, to concurrently access regions of memory of the first port and the one or more additional ports.