A power semiconductor device comprising: a substrate layer having a first conductivity type; a body layer provided on the substrate layer and having a second conductivity type, which is different from the first conductivity type; a source layer provided on the body layer and having the first conductivity type; an electrically conductive gate layer penetrating through the body layer, a gate insulation layer electrically insulating the gate layer from the substrate layer, from the body layer and from the source layer; wherein the power semiconductor device includes a plurality of vertical field effect transistor cells, wherein the plurality of vertical field effect transistor cells are arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction (x), wherein in each vertical field effect transistor cell a body region of the body layer is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other and from a top surface opposite to the substrate layer and connecting the two lateral surfaces, the gate layer being separated from the body region by the gate insulation layer, wherein in each row of vertical field effect transistor cells the body regions are separated from each other in the first direction (x) by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction (x), wherein the first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction (x), wherein, in a vertical projection onto a plane parallel to a main surface of the substrate layer, in each row of vertical field effect transistor cells, the first gate regions and the second gate regions form a continuous gate strip extending with its longitudinal axis in the first direction (x), wherein a source electrode is formed on the source layer to form a first ohmic contact to the source layer between each pair of adjacent gate strips, and characterized in that, the source layer is in direct contact with each body region at lateral interfaces extending in the vertical direction z and in the first horizontal direction x at the two ends of each body region in the second horizontal direction y orthogonal to the first horizontal direction x, and the source layer does not extend onto the top surface of the body region such that the whole top surface of the body region facing away from the substrate layer is in direct contact with the gate insulation layer. a substrate layer having a first conductivity type; a body layer provided on the substrate layer and having a second conductivity type, which is different from the first conductivity type; a source layer provided on the body layer and having the first conductivity type; an electrically conductive gate layer penetrating through the body layer, a gate insulation layer electrically insulating the gate layer from the substrate layer, from the body layer and from the source layer; wherein the power semiconductor device includes a plurality of vertical field effect transistor cells, wherein the plurality of vertical field effect transistor cells are arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction (x), wherein in each vertical field effect transistor cell a body region of the body layer is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other and from a top surface opposite to the substrate layer and connecting the two lateral surfaces, the gate layer being separated from the body region by the gate insulation layer, wherein in each row of vertical field effect transistor cells the body regions are separated from each other in the first direction (x) by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction (x), wherein the first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction (x), wherein, in a vertical projection onto a plane parallel to a main surface of the substrate layer, in each row of vertical field effect transistor cells, the first gate regions and the second gate regions form a continuous gate strip extending with its longitudinal axis in the first direction (x), wherein a source electrode is formed on the source layer to form a first ohmic contact to the source layer between each pair of adjacent gate strips, and characterized in that, the source layer is in direct contact with each body region at lateral interfaces extending in the vertical direction z and in the first horizontal direction x at the two ends of each body region in the second horizontal direction y orthogonal to the first horizontal direction x, and the source layer does not extend onto the top surface of the body region such that the whole top surface of the body region facing away from the substrate layer is in direct contact with the gate insulation layer.