A computing device comprising: a memory with a wide data path, wherein the memory is a stacked High Bandwidth Memory and the width of the wide data path is 1024-bits; and a network interface controller, NIC, communicatively coupled to the memory, the NIC comprising: host interface circuitry; port circuitry configured to receive a data packet from a medium, the data packet includes a plurality of data segments; ingress buffer configured to buffer the received data packet; and packet processing circuitry configured to inspect the headers in a first data segment in the plurality of data segments of the data packet to determine whether to either: stream the other data segments in the plurality of data segments of the data packet directly from the port circuitry via the ingress buffer to the host interface circuitry, or store the first data segment and the other data segments in the plurality of data segments of the data packet in the memory to enable operations associated with Deep Packet Inspection, DPI, to be performed by the packet processing circuitry on the first data segment and the other data segments in the plurality of data segments of the data packet. a memory with a wide data path, wherein the memory is a stacked High Bandwidth Memory and the width of the wide data path is 1024-bits; and a network interface controller, NIC, communicatively coupled to the memory, the NIC comprising: host interface circuitry; port circuitry configured to receive a data packet from a medium, the data packet includes a plurality of data segments; ingress buffer configured to buffer the received data packet; and packet processing circuitry configured to inspect the headers in a first data segment in the plurality of data segments of the data packet to determine whether to either: stream the other data segments in the plurality of data segments of the data packet directly from the port circuitry via the ingress buffer to the host interface circuitry, or store the first data segment and the other data segments in the plurality of data segments of the data packet in the memory to enable operations associated with Deep Packet Inspection, DPI, to be performed by the packet processing circuitry on the first data segment and the other data segments in the plurality of data segments of the data packet. host interface circuitry; port circuitry configured to receive a data packet from a medium, the data packet includes a plurality of data segments; ingress buffer configured to buffer the received data packet; and packet processing circuitry configured to inspect the headers in a first data segment in the plurality of data segments of the data packet to determine whether to either: stream the other data segments in the plurality of data segments of the data packet directly from the port circuitry via the ingress buffer to the host interface circuitry, or store the first data segment and the other data segments in the plurality of data segments of the data packet in the memory to enable operations associated with Deep Packet Inspection, DPI, to be performed by the packet processing circuitry on the first data segment and the other data segments in the plurality of data segments of the data packet.