A gate driving circuit comprising: a first gate output buffer circuit (G-BUF1) comprising a first pull-up transistor and a first pull-down transistor; and a control circuit configured to control a voltage of a Q node connected to a gate node of the first pull-up transistor and a voltage of a QB node connected to a gate node of the first pull-down transistor; wherein, the first pull-up transistor is connected between a first clock signal input node (Nclk1) and a first gate output node (Nout1), the first pull-down transistor is connected between the first gate output node (Nout1) and a first low-level voltage node (Nvss1), the control circuit comprises: a first transistor connected between a first driving voltage node (Nvdd1) and the QB node; two second transistors (T5q, T5qa) connected in series between the QB node and a second low level voltage node (Nvss2); a third transistor (T4h) connected between a connection node of the two second transistors (T5q, T5qa) and the first driving voltage node (Nvdd1); a fourth transistor (T41, T41a) connected between a gate node of the first transistor and the first driving voltage node (Nvdd1); and two fifth transistors (T4q, T4qa) connected in series between the gate node of the first transistor and the second low level voltage node (Nvss2), and a connection node of the two fifth transistors (T4q, T4qa) is electrically connected to a source node or a drain node of the third transistor (T4h), wherein said source node or said drain node of the third transistor (T4h) is connected to the connection node of the two second transistors (T5q, T5qa) and the connection node of the two fifth transistors (T4q, T4qa), wherein the third transistor (T4h) has a gate node connected to the QB node. a first gate output buffer circuit (G-BUF1) comprising a first pull-up transistor and a first pull-down transistor; and a control circuit configured to control a voltage of a Q node connected to a gate node of the first pull-up transistor and a voltage of a QB node connected to a gate node of the first pull-down transistor; wherein, the first pull-up transistor is connected between a first clock signal input node (Nclk1) and a first gate output node (Nout1), the first pull-down transistor is connected between the first gate output node (Nout1) and a first low-level voltage node (Nvss1), the control circuit comprises: a first transistor connected between a first driving voltage node (Nvdd1) and the QB node; two second transistors (T5q, T5qa) connected in series between the QB node and a second low level voltage node (Nvss2); a third transistor (T4h) connected between a connection node of the two second transistors (T5q, T5qa) and the first driving voltage node (Nvdd1); a fourth transistor (T41, T41a) connected between a gate node of the first transistor and the first driving voltage node (Nvdd1); and two fifth transistors (T4q, T4qa) connected in series between the gate node of the first transistor and the second low level voltage node (Nvss2), and a first transistor connected between a first driving voltage node (Nvdd1) and the QB node; two second transistors (T5q, T5qa) connected in series between the QB node and a second low level voltage node (Nvss2); a third transistor (T4h) connected between a connection node of the two second transistors (T5q, T5qa) and the first driving voltage node (Nvdd1); a fourth transistor (T41, T41a) connected between a gate node of the first transistor and the first driving voltage node (Nvdd1); and two fifth transistors (T4q, T4qa) connected in series between the gate node of the first transistor and the second low level voltage node (Nvss2), and a connection node of the two fifth transistors (T4q, T4qa) is electrically connected to a source node or a drain node of the third transistor (T4h), wherein said source node or said drain node of the third transistor (T4h) is connected to the connection node of the two second transistors (T5q, T5qa) and the connection node of the two fifth transistors (T4q, T4qa), wherein the third transistor (T4h) has a gate node connected to the QB node.