A processor comprising: fetch circuitry to fetch a plurality of instructions; decode circuitry (1303, 1403) to decode the plurality of fetched instructions; and execution circuitry, responsive to the plurality of decoded instructions to: identify first and second decoded instructions belonging to a chain of instructions; select a path comprising first and second processing engines (PEs) to execute the first and second decoded instructions; and route a result of the first decoded instruction from the first PE to the second PE to be used by the second PE to perform the second decoded instruction; characterized in that the instructions each having source (2504, 2505, 2506) and destination tile specifiers to specify respective source and destination tiles, a tile representing a 2-dimensional data structure in a portion of storage having data elements arranged in rows and columns; the path is a SIMD path and dynamically selected and configured; the destination tile specifier of the first decoded instruction is set aside and the result of the first decoded instruction is instead routed from the first PE to the second PE; and the execution circuitry is to set a dirty bit in a tile configuration of the specified destination tile of the first instruction when setting aside the destination tile specifier of the first decoded instruction, and to cause a fault if the dirty tile is read by a subsequent instruction. fetch circuitry to fetch a plurality of instructions; decode circuitry (1303, 1403) to decode the plurality of fetched instructions; and execution circuitry, responsive to the plurality of decoded instructions to: identify first and second decoded instructions belonging to a chain of instructions; select a path comprising first and second processing engines (PEs) to execute the first and second decoded instructions; and route a result of the first decoded instruction from the first PE to the second PE to be used by the second PE to perform the second decoded instruction; characterized in that the instructions each having source (2504, 2505, 2506) and destination tile specifiers to specify respective source and destination tiles, a tile representing a 2-dimensional data structure in a portion of storage having data elements arranged in rows and columns; the path is a SIMD path and dynamically selected and configured; the destination tile specifier of the first decoded instruction is set aside and the result of the first decoded instruction is instead routed from the first PE to the second PE; and the execution circuitry is to set a dirty bit in a tile configuration of the specified destination tile of the first instruction when setting aside the destination tile specifier of the first decoded instruction, and to cause a fault if the dirty tile is read by a subsequent instruction. identify first and second decoded instructions belonging to a chain of instructions; select a path comprising first and second processing engines (PEs) to execute the first and second decoded instructions; and route a result of the first decoded instruction from the first PE to the second PE to be used by the second PE to perform the second decoded instruction; characterized in that the instructions each having source (2504, 2505, 2506) and destination tile specifiers to specify respective source and destination tiles, a tile representing a 2-dimensional data structure in a portion of storage having data elements arranged in rows and columns; the path is a SIMD path and dynamically selected and configured; the destination tile specifier of the first decoded instruction is set aside and the result of the first decoded instruction is instead routed from the first PE to the second PE; and the execution circuitry is to set a dirty bit in a tile configuration of the specified destination tile of the first instruction when setting aside the destination tile specifier of the first decoded instruction, and to cause a fault if the dirty tile is read by a subsequent instruction.