A global positioning system device comprising: a frequency converter that receives a plurality of GPS signals; and a synchronization holding circuit that holds specific of the plurality of GPS signals, wherein the synchronization holding circuit comprises a plurality of PLL circuits, one for each of a plurality of synchronization-holding channels, wherein each PLL circuit has mixers (104, 105) receiving a signal from the frequency converter and taking out an I component respectively a Q component from that signal, succeeding low pass filters (106,107) filtering out a difference in the I component respectively in the Q component and a carrier NCO connected to an output of a demultiplexer unit; and a multiplexer unit (115, 116) that receives the plurality of signals at the outputs of the low pass filters (106,107) of the plurality of PLL circuits, and that sequentially selects, in a time-division manner, each one of the plurality of signals, at least one phase difference detector that receives each selected signal from the multiplexer unit (115, 116), a number of the at least one phase difference detectors being less than a number of the plurality of channels, at least one demultiplexer unit that is connected to an output of the corresponding phase difference detector and that sequentially selects the carrier NCO of a PLL circuit of the plurality of PLL circuits in a time-division manner. a frequency converter that receives a plurality of GPS signals; and a synchronization holding circuit that holds specific of the plurality of GPS signals, wherein the synchronization holding circuit comprises a plurality of PLL circuits, one for each of a plurality of synchronization-holding channels, wherein each PLL circuit has mixers (104, 105) receiving a signal from the frequency converter and taking out an I component respectively a Q component from that signal, succeeding low pass filters (106,107) filtering out a difference in the I component respectively in the Q component and a carrier NCO connected to an output of a demultiplexer unit; and a multiplexer unit (115, 116) that receives the plurality of signals at the outputs of the low pass filters (106,107) of the plurality of PLL circuits, and that sequentially selects, in a time-division manner, each one of the plurality of signals, at least one phase difference detector that receives each selected signal from the multiplexer unit (115, 116), a number of the at least one phase difference detectors being less than a number of the plurality of channels, at least one demultiplexer unit that is connected to an output of the corresponding phase difference detector and that sequentially selects the carrier NCO of a PLL circuit of the plurality of PLL circuits in a time-division manner. a plurality of PLL circuits, one for each of a plurality of synchronization-holding channels, wherein each PLL circuit has mixers (104, 105) receiving a signal from the frequency converter and taking out an I component respectively a Q component from that signal, succeeding low pass filters (106,107) filtering out a difference in the I component respectively in the Q component and a carrier NCO connected to an output of a demultiplexer unit; and a multiplexer unit (115, 116) that receives the plurality of signals at the outputs of the low pass filters (106,107) of the plurality of PLL circuits, and that sequentially selects, in a time-division manner, each one of the plurality of signals, at least one phase difference detector that receives each selected signal from the multiplexer unit (115, 116), a number of the at least one phase difference detectors being less than a number of the plurality of channels, at least one demultiplexer unit that is connected to an output of the corresponding phase difference detector and that sequentially selects the carrier NCO of a PLL circuit of the plurality of PLL circuits in a time-division manner.