An integrated print cartridge comprising an ink reservoir, a fluid-jet die, a flexible cable, conductive pads, and an integrated circuit, the integrated circuit comprising: at least one memory bank, each memory bank of the at least one memory bank comprising two memory matrices (210, 215); and one shift register based multiplexing signal generator; wherein the shift-register based multiplexing signal generator is interposed between and spatially separates the two memory matrices (210, 215); wherein each of the two memory matrices (210, 215) comprises multiple rows and a double amount of columns to rows; and wherein the shift-register based multiplexing signal generator comprises a group of eight electrical connection output lines from a column select, wherein the group of eight electrical connection output lines branches out into two groups of eight electrical connection lines running perpendicular to the group of eight electrical connection output lines and wherein this group of eight electrical connection output lines connects to corresponding column select inputs on the two memory matrices, and wherein the shift register based multiplexing signal generator comprises two separate groups of four electrical row select connection output lines that connect to corresponding row select inputs on the two memory matrices (210, 215), wherein the two separate groups of four electrical row select connection output lines run in opposite directions and run in parallel to the two groups of eight electrical connection lines and to the shift-register based multiplexing signal generator and the memory matrices (210, 215), and wherein the two separate groups of four electrical row select connection output lines take up the same amount of space and lie the same distance from the two memory matrices (210, 215) and the shift register based multiplexing signal generator, wherein there is a double amount of the column select inputs to an amount of the row select inputs for each memory matrix of the two memory matrices. at least one memory bank, each memory bank of the at least one memory bank comprising two memory matrices (210, 215); and one shift register based multiplexing signal generator; wherein the shift-register based multiplexing signal generator is interposed between and spatially separates the two memory matrices (210, 215); wherein each of the two memory matrices (210, 215) comprises multiple rows and a double amount of columns to rows; and wherein the shift-register based multiplexing signal generator comprises a group of eight electrical connection output lines from a column select, wherein the group of eight electrical connection output lines branches out into two groups of eight electrical connection lines running perpendicular to the group of eight electrical connection output lines and wherein this group of eight electrical connection output lines connects to corresponding column select inputs on the two memory matrices, and wherein the shift register based multiplexing signal generator comprises two separate groups of four electrical row select connection output lines that connect to corresponding row select inputs on the two memory matrices (210, 215), wherein the two separate groups of four electrical row select connection output lines run in opposite directions and run in parallel to the two groups of eight electrical connection lines and to the shift-register based multiplexing signal generator and the memory matrices (210, 215), and wherein the two separate groups of four electrical row select connection output lines take up the same amount of space and lie the same distance from the two memory matrices (210, 215) and the shift register based multiplexing signal generator, wherein there is a double amount of the column select inputs to an amount of the row select inputs for each memory matrix of the two memory matrices.