A nonvolatile memory device comprising: a memory cell array including a plurality of memory cells; an address decoder configured to decode a row address and a column address from an address signal; a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array according to the decoded row address; a second voltage generator configured to generate a bit line operating voltage of the memory cell array according to the decoded column address; a page buffer circuit (140, 320) configured to activate according to the bit line operating voltage and to store data to be stored in or read from at least one memory cell; and a temperature unit configured to determine, from a temperature range table storing a plurality of selection signals mapped to each of a plurality of temperatures ranges, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of at least one of the first or second voltage generator based on a selection signal mapped to the determined temperature range characterized in that the page buffer circuit includes: a precharge circuit comprising at least one transistor controlled by a bit line setup signal output from a control circuit; and a shutoff circuit comprising at least one transistor controlled by a bit line shutoff signal, wherein the second voltage generator includes a bit line shutoff signal generator configured to adjust a voltage level of the bit line shutoff signal according to an output of the temperature unit. a memory cell array including a plurality of memory cells; an address decoder configured to decode a row address and a column address from an address signal; a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array according to the decoded row address; a second voltage generator configured to generate a bit line operating voltage of the memory cell array according to the decoded column address; a page buffer circuit (140, 320) configured to activate according to the bit line operating voltage and to store data to be stored in or read from at least one memory cell; and a temperature unit configured to determine, from a temperature range table storing a plurality of selection signals mapped to each of a plurality of temperatures ranges, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of at least one of the first or second voltage generator based on a selection signal mapped to the determined temperature range characterized in that the page buffer circuit includes: a precharge circuit comprising at least one transistor controlled by a bit line setup signal output from a control circuit; and a shutoff circuit comprising at least one transistor controlled by a bit line shutoff signal, wherein the second voltage generator includes a bit line shutoff signal generator configured to adjust a voltage level of the bit line shutoff signal according to an output of the temperature unit. a precharge circuit comprising at least one transistor controlled by a bit line setup signal output from a control circuit; and a shutoff circuit comprising at least one transistor controlled by a bit line shutoff signal, wherein the second voltage generator includes a bit line shutoff signal generator configured to adjust a voltage level of the bit line shutoff signal according to an output of the temperature unit.