A solid-state power controller system comprising: a power source connected to a plurality of solid-state power controller channels (3, 6, 9, 12), said plurality of solid state power controller channels comprising a first output channel and a second output channel; a first solid-state power controller comprising a main switching FET and a first sharing control FET, wherein the first sharing control FET is coupled in series along the first output channel; a second solid-state power controller comprising a second sharing control FET, wherein the second sharing control FET is coupled in series along the second output channel; and a controller in electrical communication with the first solid-state power controller and the second solid-state power controller; a sense resistor coupled in series with the first output channel; a balance resistor coupled in parallel with the first sharing control FET, wherein the main switching FET is coupled in series with the first sharing control FET and the balance resistor, and the controller is configured to direct the operation of a gate of the first sharing control FET and a gate of the second sharing control FET via one or more control algorithms, and wherein the first sharing control FET is in an OFF state while the first solid-state power controller is toggled to an ON state and directs sharing control for in-rush currents through the balancing resistor, wherein a control loop algorithm is configured to toggle the first sharing control FET to an ON status and operate the first sharing control FET in a linear region during normal ON operation of the first solid-state power controller. a power source connected to a plurality of solid-state power controller channels (3, 6, 9, 12), said plurality of solid state power controller channels comprising a first output channel and a second output channel; a first solid-state power controller comprising a main switching FET and a first sharing control FET, wherein the first sharing control FET is coupled in series along the first output channel; a second solid-state power controller comprising a second sharing control FET, wherein the second sharing control FET is coupled in series along the second output channel; and a controller in electrical communication with the first solid-state power controller and the second solid-state power controller; a sense resistor coupled in series with the first output channel; a balance resistor coupled in parallel with the first sharing control FET, wherein the main switching FET is coupled in series with the first sharing control FET and the balance resistor, and the controller is configured to direct the operation of a gate of the first sharing control FET and a gate of the second sharing control FET via one or more control algorithms, and wherein the first sharing control FET is in an OFF state while the first solid-state power controller is toggled to an ON state and directs sharing control for in-rush currents through the balancing resistor, wherein a control loop algorithm is configured to toggle the first sharing control FET to an ON status and operate the first sharing control FET in a linear region during normal ON operation of the first solid-state power controller.