A radio frequency, RF, switching circuit comprising: one or more field effect transistor, FET, switches (21, 61, 62, 63) comprising a first FET switch; and an adaptive switch bias circuit (22, 52, 72, 81, 91) configured to control a gate voltage and a channel voltage of the first FET switch, wherein the adaptive switch bias circuit is configured to receive a switch enable signal, wherein the adaptive switch bias circuit is configured to bias the first FET switch with a turn-on voltage to turn on the first FET switch when the switch enable signal is in a first state, and wherein the adaptive switch bias circuit is configured to bias the first FET switch with a turn-off voltage to turn off the first FET switch when the switch enable signal is in a second state, wherein the adaptive switch bias circuit is configured to be powered by a power high supply voltage and a power low supply voltage, and wherein the adaptive switch bias circuit is configured to control a magnitude of the turn-on voltage and a magnitude of the turn-off voltage based on a voltage difference between the power high supply voltage and the power low supply voltage; wherein the adaptive switch bias circuit comprises: a supply dependent voltage generation circuit (53, 73) configured to receive the power high supply voltage and to generate a dependent voltage that changes in relation to a voltage level of the power high supply voltage, wherein the supply dependent voltage generation circuit is configured to generate a voltage drop; and a voltage divider (54, 74) configured to generate a bias voltage for the first FET switch based on a voltage difference between the dependent voltage and the power low supply voltage. the supply dependent voltage generation circuit (53, 73) comprises a subtraction circuit configured to generate the dependent voltage by subtracting a predetermined amount of voltage from the power high supply voltage, characterised in that the supply dependent voltage generation circuit (53, 73) further comprises a bandgap voltage reference circuit configured to generate the predetermined amount of voltage, wherein the predetermined amount of voltage comprises a bandgap reference voltage. one or more field effect transistor, FET, switches (21, 61, 62, 63) comprising a first FET switch; and an adaptive switch bias circuit (22, 52, 72, 81, 91) configured to control a gate voltage and a channel voltage of the first FET switch, wherein the adaptive switch bias circuit is configured to receive a switch enable signal, wherein the adaptive switch bias circuit is configured to bias the first FET switch with a turn-on voltage to turn on the first FET switch when the switch enable signal is in a first state, and wherein the adaptive switch bias circuit is configured to bias the first FET switch with a turn-off voltage to turn off the first FET switch when the switch enable signal is in a second state, wherein the adaptive switch bias circuit is configured to be powered by a power high supply voltage and a power low supply voltage, and wherein the adaptive switch bias circuit is configured to control a magnitude of the turn-on voltage and a magnitude of the turn-off voltage based on a voltage difference between the power high supply voltage and the power low supply voltage; wherein the adaptive switch bias circuit comprises: a supply dependent voltage generation circuit (53, 73) configured to receive the power high supply voltage and to generate a dependent voltage that changes in relation to a voltage level of the power high supply voltage, wherein the supply dependent voltage generation circuit is configured to generate a voltage drop; and a voltage divider (54, 74) configured to generate a bias voltage for the first FET switch based on a voltage difference between the dependent voltage and the power low supply voltage. the supply dependent voltage generation circuit (53, 73) comprises a subtraction circuit configured to generate the dependent voltage by subtracting a predetermined amount of voltage from the power high supply voltage, characterised in that the supply dependent voltage generation circuit (53, 73) further comprises a bandgap voltage reference circuit configured to generate the predetermined amount of voltage, wherein the predetermined amount of voltage comprises a bandgap reference voltage. a supply dependent voltage generation circuit (53, 73) configured to receive the power high supply voltage and to generate a dependent voltage that changes in relation to a voltage level of the power high supply voltage, wherein the supply dependent voltage generation circuit is configured to generate a voltage drop; and a voltage divider (54, 74) configured to generate a bias voltage for the first FET switch based on a voltage difference between the dependent voltage and the power low supply voltage. the supply dependent voltage generation circuit (53, 73) comprises a subtraction circuit configured to generate the dependent voltage by subtracting a predetermined amount of voltage from the power high supply voltage, characterised in that the supply dependent voltage generation circuit (53, 73) further comprises a bandgap voltage reference circuit configured to generate the predetermined amount of voltage, wherein the predetermined amount of voltage comprises a bandgap reference voltage.