A method of forming a wafer level package comprising: providing a silicon wafer having a plurality of integrated circuits formed thereon, with a dice area formed between each of the integrated circuits and each integrated circuit having a plurality of die pads formed thereon; adhering a pre-formed base polymer laminate layer to the top surface of the silicon wafer using an adhesive; forming a plurality of vias through the base polymer laminate layer at positions corresponding to the die pads on the wafer; forming a plurality of metal interconnects on the base polymer laminate layer such that each of the plurality of metal interconnects extends down through a respective via of the first plurality of vias to electrically connect to a respective die pad; applying at least one additional pre-formed polymer laminate layer to the base polymer laminate layer and the metal interconnects; forming an additional plurality of vias through each of the at least one additional polymer laminate layer at positions corresponding to the metal interconnects of the polymer laminate layer positioned immediately therebelow; forming an additional plurality of metal interconnects on each of the at least one additional polymer laminate layer such that each of the plurality of metal interconnects extend down through a respective via of the additional plurality of vias into electrical contact with the metal interconnects on the polymer laminate layer (16, 32) positioned immediately therebelow; attaching a plurality of input/output (I/O) connections to the metal interconnects directly on a topmost polymer laminate layer; and singulating the silicon wafer into a plurality of wafer level packages, each wafer level package including a portion of the plurality of metal interconnects and a portion of the plurality of I/O connections thereon. providing a silicon wafer having a plurality of integrated circuits formed thereon, with a dice area formed between each of the integrated circuits and each integrated circuit having a plurality of die pads formed thereon; adhering a pre-formed base polymer laminate layer to the top surface of the silicon wafer using an adhesive; forming a plurality of vias through the base polymer laminate layer at positions corresponding to the die pads on the wafer; forming a plurality of metal interconnects on the base polymer laminate layer such that each of the plurality of metal interconnects extends down through a respective via of the first plurality of vias to electrically connect to a respective die pad; applying at least one additional pre-formed polymer laminate layer to the base polymer laminate layer and the metal interconnects; forming an additional plurality of vias through each of the at least one additional polymer laminate layer at positions corresponding to the metal interconnects of the polymer laminate layer positioned immediately therebelow; forming an additional plurality of metal interconnects on each of the at least one additional polymer laminate layer such that each of the plurality of metal interconnects extend down through a respective via of the additional plurality of vias into electrical contact with the metal interconnects on the polymer laminate layer (16, 32) positioned immediately therebelow; attaching a plurality of input/output (I/O) connections to the metal interconnects directly on a topmost polymer laminate layer; and singulating the silicon wafer into a plurality of wafer level packages, each wafer level package including a portion of the plurality of metal interconnects and a portion of the plurality of I/O connections thereon.