A method for forming a semiconductor device, the method comprising: forming on a substrate a set of parallel gate patterns across a plurality of parallel active semiconductor patterns extending along the substrate, the set of gate patterns comprising: an active gate pattern formed between a drain-side region and a source-side region, and a first and a second dummy gate pattern (210, 220), forming a metal drain contact in the drain-side region, wherein the first and second dummy gate patterns (210, 220) are formed in a ballast region located in the drain-side region between the metal drain contact and the active gate pattern, wherein the first dummy gate pattern comprises a number of first dummy gate regions defining a respective dummy gate and a number of first gate cut regions alternating the first dummy gate regions and in which a dummy gate is absent, wherein each first dummy gate region extends across a respective first subset of the active semiconductor patterns and each first gate cut region extends across a respective second subset of the active semiconductor patterns, and wherein the second dummy gate pattern is formed between the first dummy gate pattern and the active gate pattern and comprises a number of second dummy gate regions defining a respective dummy gate and a number of second gate cut regions alternating the second dummy gate regions and in which a dummy gate is absent, wherein each second dummy gate region extends across a respective one of the second subsets of the active semiconductor patterns and each second gate cut region extends across a respective one of the first subsets of the active semiconductor patterns, wherein the active semiconductor patterns are un-doped or doped with a first type of dopant and the method further comprises doping the active semiconductor patterns in the drain-side region with a second type of dopant while using the first and second dummy gate patterns (210, 220) as a mask to counteract doping of the active semiconductor patterns with the second type of dopant in said dummy gate regions, and forming a metal interconnect structure connecting each of the active semiconductor patterns of the second subset to at least one of the active semiconductor patterns of the first subset in a region between the first and the second dummy gate patterns. forming on a substrate a set of parallel gate patterns across a plurality of parallel active semiconductor patterns extending along the substrate, the set of gate patterns comprising: an active gate pattern formed between a drain-side region and a source-side region, and a first and a second dummy gate pattern (210, 220), forming a metal drain contact in the drain-side region, wherein the first and second dummy gate patterns (210, 220) are formed in a ballast region located in the drain-side region between the metal drain contact and the active gate pattern, wherein the first dummy gate pattern comprises a number of first dummy gate regions defining a respective dummy gate and a number of first gate cut regions alternating the first dummy gate regions and in which a dummy gate is absent, wherein each first dummy gate region extends across a respective first subset of the active semiconductor patterns and each first gate cut region extends across a respective second subset of the active semiconductor patterns, and wherein the second dummy gate pattern is formed between the first dummy gate pattern and the active gate pattern and comprises a number of second dummy gate regions defining a respective dummy gate and a number of second gate cut regions alternating the second dummy gate regions and in which a dummy gate is absent, wherein each second dummy gate region extends across a respective one of the second subsets of the active semiconductor patterns and each second gate cut region extends across a respective one of the first subsets of the active semiconductor patterns, wherein the active semiconductor patterns are un-doped or doped with a first type of dopant and the method further comprises doping the active semiconductor patterns in the drain-side region with a second type of dopant while using the first and second dummy gate patterns (210, 220) as a mask to counteract doping of the active semiconductor patterns with the second type of dopant in said dummy gate regions, and forming a metal interconnect structure connecting each of the active semiconductor patterns of the second subset to at least one of the active semiconductor patterns of the first subset in a region between the first and the second dummy gate patterns.