A split gate semiconductor device comprising: a source region; a drain region; and a trench gate formed within a trench, said trench gate comprising: a first layer comprising an oxide layer and a first dielectric layer, wherein said oxide layer is along the bottom surface and sidewall surfaces of said trench, and wherein said first dielectric layer is over said oxide layer; a first gate electrode region formed over said first dielectric layer, wherein the height from the bottom surface of the trench of said first layer is less than the height of said first gate electrode region; a second dielectric layer formed over said first layer and said first gate electrode region, wherein the same material is present throughout the second dielectric layer; formed over a gate oxide layer formed over said second dielectric layer and along the sidewall surfaces of said trench, wherein the boundary between said gate oxide layer and said second dielectric layer is concave relative to said second dielectric layer and convex relative to said gate oxide layer, wherein said boundary extends across the entire width of said trench and meets the sidewall surfaces of said trench; and a second gate electrode region formed over said gate oxide layer. a source region; a drain region; and a trench gate formed within a trench, said trench gate comprising: a first layer comprising an oxide layer and a first dielectric layer, wherein said oxide layer is along the bottom surface and sidewall surfaces of said trench, and wherein said first dielectric layer is over said oxide layer; a first gate electrode region formed over said first dielectric layer, wherein the height from the bottom surface of the trench of said first layer is less than the height of said first gate electrode region; a second dielectric layer formed over said first layer and said first gate electrode region, wherein the same material is present throughout the second dielectric layer; formed over a gate oxide layer formed over said second dielectric layer and along the sidewall surfaces of said trench, wherein the boundary between said gate oxide layer and said second dielectric layer is concave relative to said second dielectric layer and convex relative to said gate oxide layer, wherein said boundary extends across the entire width of said trench and meets the sidewall surfaces of said trench; and a second gate electrode region formed over said gate oxide layer. a first layer comprising an oxide layer and a first dielectric layer, wherein said oxide layer is along the bottom surface and sidewall surfaces of said trench, and wherein said first dielectric layer is over said oxide layer; a first gate electrode region formed over said first dielectric layer, wherein the height from the bottom surface of the trench of said first layer is less than the height of said first gate electrode region; a second dielectric layer formed over said first layer and said first gate electrode region, wherein the same material is present throughout the second dielectric layer; formed over a gate oxide layer formed over said second dielectric layer and along the sidewall surfaces of said trench, wherein the boundary between said gate oxide layer and said second dielectric layer is concave relative to said second dielectric layer and convex relative to said gate oxide layer, wherein said boundary extends across the entire width of said trench and meets the sidewall surfaces of said trench; and a second gate electrode region formed over said gate oxide layer.