Method for operating a pixel sensor cell wherein the pixel sensor cell comprises, - a photodiode for generating photoelectrons; - a first transfer transistor coupling the photodiode with an intermediate node and configured to be controlled by a first control signal (TX 1); - a reset transistor configured to receive a reset signal and to selectively couple a supplied reset voltage to the intermediate node; - a gain reducing capacitance (C HD) applied on the intermediate node; - a second transfer transistor coupling the intermediate node with a sense node and configured to be controlled by a second control signal (TX 2); - an output buffer coupled with the sense node and configured to amplify a potential on the sense node, and the method comprises the steps of: - accumulating photoelectrons in the photodiode during a predetermined integration time; - in a first phase, coupling the intermediate node with the sense node by means of the second transfer transistor and controlling the first transfer transistor to provide a charge threshold for accumulated photoelectrons so that only excess photoelectrons are allowed to pass to the intermediate node, wherein the potential generated by the excess photoelectrons is read out as an HDS sampling output signal (V HDS), wherein after the first phase a first reset potential (VRST1) is loaded on the sense node and a second reset potential (V RST2) which is in a range between a pin voltage (V pin) of the photodiode and the first reset potential (VRST1) is loaded on the intermediate node, wherein the pin voltage (V Pin) is the voltage inside the photodiode when it is completely emptied from electrons; - in a second phase, controlling the second transfer transistor to set a threshold of the second transfer transistor to a potential where the second transfer transistor isolates the intermediate node and the sense node and which is equal or higher than the potential of the intermediate node, and reading out the potential on the sense node as a reference sampling output signal, controlling the first transfer transistor to lower the threshold between the photodiode and the intermediate node and reading out the potential on the sense node as an LLS sampling output signal (V LLS), wherein a cell output is determined depending on the LLS sampling output signal (V LLS) and the HDS sampling output signal (V HDS) and the reference sampling output signal. - a photodiode for generating photoelectrons; - a first transfer transistor coupling the photodiode with an intermediate node and configured to be controlled by a first control signal (TX 1); - a reset transistor configured to receive a reset signal and to selectively couple a supplied reset voltage to the intermediate node; - a gain reducing capacitance (C HD) applied on the intermediate node; - a second transfer transistor coupling the intermediate node with a sense node and configured to be controlled by a second control signal (TX 2); - an output buffer coupled with the sense node and configured to amplify a potential on the sense node, and the method comprises the steps of: - accumulating photoelectrons in the photodiode during a predetermined integration time; - in a first phase, coupling the intermediate node with the sense node by means of the second transfer transistor and controlling the first transfer transistor to provide a charge threshold for accumulated photoelectrons so that only excess photoelectrons are allowed to pass to the intermediate node, wherein the potential generated by the excess photoelectrons is read out as an HDS sampling output signal (V HDS), wherein after the first phase a first reset potential (VRST1) is loaded on the sense node and a second reset potential (V RST2) which is in a range between a pin voltage (V pin) of the photodiode and the first reset potential (VRST1) is loaded on the intermediate node, wherein the pin voltage (V Pin) is the voltage inside the photodiode when it is completely emptied from electrons; - in a second phase, controlling the second transfer transistor to set a - accumulating photoelectrons in the photodiode during a predetermined integration time; - in a first phase, coupling the intermediate node with the sense node by means of the second transfer transistor and controlling the first transfer transistor to provide a charge threshold for accumulated photoelectrons so that only excess photoelectrons are allowed to pass to the intermediate node, wherein the potential generated by the excess photoelectrons is read out as an HDS sampling output signal (V HDS), wherein after the first phase a first reset potential (VRST1) is loaded on the sense node and a second reset potential (V RST2) which is in a range between a pin voltage (V pin) of the photodiode and the first reset potential (VRST1) is loaded on the intermediate node, wherein the pin voltage (V Pin) is the voltage inside the photodiode when it is completely emptied from electrons; - in a second phase, controlling the second transfer transistor to set a threshold of the second transfer transistor to a potential where the second transfer transistor isolates the intermediate node and the sense node and which is equal or higher than the potential of the intermediate node, and reading out the potential on the sense node as a reference sampling output signal, controlling the first transfer transistor to lower the threshold between the photodiode and the intermediate node and reading out the potential on the sense node as an LLS sampling output signal (V LLS), wherein a cell output is determined depending on the LLS sampling output signal (V LLS) and the HDS sampling output signal (V HDS) and the reference sampling output signal.