A switch-mode power supply (SMPS), comprising: at least one power switch (316; 318) coupled to a voltage source; a power inductor coupled to the at least one power switch (316; 318); a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage output (V OUT) of the SMPS; at least one driver coupled to the at least one power switch (316; 318); a pulse width modulation generator (326; 458) having at least one output coupled to and controlling the at least one driver, the at least one output of the PWM generator (326; 458) providing at least one PWM signal comprising a plurality of pulses; a digital processor having a memory, the digital processor is coupled to and provides operating parameters to the PWM generator (326; 458) during operation thereof; characterized by a voltage comparison circuit for comparing the regulated output voltage (V OUT) to a reference voltage (V REF), wherein the voltage comparison circuit has an error signal output representative of a difference between the regulated output voltage (V OUT) and the reference voltage (V REF); a comparator having a first input coupled to the error signal output from the voltage comparison circuit, a second input coupled to a ramp signal (I SENSE; V RAMP), and an output coupled to an input of the PWM generator (326; 458); a PWM averaging filter (328; 468), wherein the PWM averaging filter (328; 468) receives the PWM signal and produces an analog signal representative of a relative efficiency thereof; and an analog-to-digital converter having an analog input coupled to the PWM averaging filter (328; 468) for receiving the analog signal representative of the relative efficiency of the PWM signal, and a digital output coupled to the digital processor having the memory; wherein the digital processor is designated for storing in the memory digital efficiency values from the digital output of the analog-to-digital converter and wherein the digital processor optimizes operation of the SMPS by adjusting operating parameters of the PWM generator (326; 458) by using the stored digital efficiency values to provide the at least one PWM signal that produces a highest relative efficiency of the SMPS. at least one power switch (316; 318) coupled to a voltage source; a power inductor coupled to the at least one power switch (316; 318); a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage output (V OUT) of the SMPS; at least one driver coupled to the at least one power switch (316; 318); a pulse width modulation generator (326; 458) having at least one output coupled to and controlling the at least one driver, the at least one output of the PWM generator (326; 458) providing at least one PWM signal comprising a plurality of pulses; a digital processor having a memory, the digital processor is coupled to and provides operating parameters to the PWM generator (326; 458) during operation thereof; characterized by a voltage comparison circuit for comparing the regulated output voltage (V OUT) to a reference voltage (V REF), wherein the voltage comparison circuit has an error signal output representative of a difference between the regulated output voltage (V OUT) and the reference voltage (V REF); a comparator having a first input coupled to the error signal output from the voltage comparison circuit, a second input coupled to a ramp signal (I SENSE; V RAMP), and an output coupled to an input of the PWM generator (326; 458); a PWM averaging filter (328; 468), wherein the PWM averaging filter (328; 468) receives the PWM signal and produces an analog signal representative of a relative efficiency thereof; and an analog-to-digital converter having an analog input coupled to the PWM averaging filter (328; 468) for receiving the analog signal representative of the relative efficiency of the PWM signal, and a digital output coupled to the digital processor having the memory; wherein the digital processor is designated for storing in the memory digital efficiency values from the digital output of the analog-to-digital converter and wherein the digital processor optimizes operation of the SMPS by adjusting operating parameters of the PWM generator (326; 458) by using the stored digital efficiency values to provide the at least one PWM signal that produces a highest relative efficiency of the SMPS.