A semiconductor device (100, 200, 300, 400, 500, 600, 700), comprising: a stack of layers (150, 650, 750) comprising a common source layer (140, 240, 340, 640, 740), gate layers and insulating layers disposed on a substrate (101, 601, 701), the gate layers and insulating layers 154) being stacked alternatingly; an array of channel structures (131, 631, 731) formed in an array region, each channel structure (131, 631, 731) extending through the stack of layers (150, 650, 750) forming a stack of transistors in a series configuration, each the channel structure (131, 631, 731) comprising a channel layer that is conductively connected with the common source layer (140, 240, 340, 640, 740), the common source layer (140, 240, 340, 640, 740) extending over the array region and a staircase region (120, 220, 320, 420, 520, 620); a contact structure (160, 161, 171, 660, 760) disposed in the staircase region (120, 220, 320, 420, 520, 620), the contact structure (160, 161, 171, 660, 760) forming a conductive connection with the common source layer (140, 240, 340, 640, 740), wherein the common source layer (140, 240, 340, 640, 740) comprises a source layer and a high conductive layer, wherein the high conductive layer is disposed between the source layer and the bottom most insulating layer, wherein the high conductive layer comprises at least one of metal, metal compound or metal silicide, wherein the source layer comprises a silicon layer; a gate line cut structure (180, 680, 780) with a bottom high conductive layer in conductive connection and in direct contact with the high conductive layer, wherein the bottom high conductive layer comprises a different material than the high conductive layer, wherein the gate line cut structure (180, 680, 780) comprises an upper insulating portion that is above the bottom high conductive layer; and vertical memory cell strings (130, 630) formed as arrays in the respective channel structures (131, 631, 731) in the array region, wherein the high conductive layer extends in the array region and forms an array common source, ACS. a stack of layers (150, 650, 750) comprising a common source layer (140, 240, 340, 640, 740), gate layers and insulating layers disposed on a substrate (101, 601, 701), the gate layers and insulating layers 154) being stacked alternatingly; an array of channel structures (131, 631, 731) formed in an array region, each channel structure (131, 631, 731) extending through the stack of layers (150, 650, 750) forming a stack of transistors in a series configuration, each the channel structure (131, 631, 731) comprising a channel layer that is conductively connected with the common source layer (140, 240, 340, 640, 740), the common source layer (140, 240, 340, 640, 740) extending over the array region and a staircase region (120, 220, 320, 420, 520, 620); a contact structure (160, 161, 171, 660, 760) disposed in the staircase region (120, 220, 320, 420, 520, 620), the contact structure (160, 161, 171, 660, 760) forming a conductive connection with the common source layer (140, 240, 340, 640, 740), wherein the common source layer (140, 240, 340, 640, 740) comprises a source layer and a high conductive layer, wherein the high conductive layer is disposed between the source layer and the bottom most insulating layer, wherein the high conductive layer comprises at least one of metal, metal compound or metal silicide, wherein the source layer comprises a silicon layer; a gate line cut structure (180, 680, 780) with a bottom high conductive layer in conductive connection and in direct contact with the high conductive layer, wherein the bottom high conductive layer comprises a different material than the high conductive layer, wherein the gate line cut structure (180, 680, 780) comprises an upper insulating portion that is above the bottom high conductive layer; and vertical memory cell strings (130, 630) formed as arrays in the respective channel structures (131, 631, 731) in the array region, wherein the high conductive layer extends in the array region and forms an array common source, ACS.