A method of forming a portion of a gate all around nanowire device comprising: forming a stack of alternating layers of epitaxial silicon-germanium (102, 102') and epitaxial silicon (104, 104') on a substrate, the stack comprising a plurality of epitaxial silicon-germanium layers (102, 102') and a plurality of epitaxial silicon layers (104, 104'); patterning said stack to form a plurality of fin structures separated by trenches, the patterning comprising etching said stack; forming a plurality of spacers across and on the plurality of fin structures; forming a sacrificial gate electrode between the plurality of spacers and around portions of the plurality of fin structures located between the spacers, removing a portion of each of the plurality of fin structures from the substrate, the portion not being located between the spacers, to expose a respective plurality of source/drain regions on the substrate, the plurality of source/drain regions being adjacent to the plurality of spacers; forming an epitaxial source/drain structure in each of the plurality of source/drain regions; removing the sacrificial gate electrode from between the plurality of spacers; removing the plurality of epitaxial silicon layers or the plurality of epitaxial silicon germanium layers from the plurality of fin structures disposed between the plurality of spacers to form a plurality of silicon-germanium nanowire structures (104, 104') or a plurality of silicon nanowire structures (102, 102') respectively; depositing a gate dielectric material around each of the plurality of silicon-germanium nanowire structures (104, 104') or around each of the plurality of silicon nanowires structures (102, 102'); and forming a gate electrode material around the gate dielectric material, wherein the gate electrode material surrounds the plurality of silicon-germanium nanowire structures (104, 104'), or the plurality of silicon nanowires structures (102, 102'), and fills a gap between the plurality of germanium nanowire structures (104, 104') or between the plurality of silicon nanowire structures (102, 102'). forming a stack of alternating layers of epitaxial silicon-germanium (102, 102') and epitaxial silicon (104, 104') on a substrate, the stack comprising a plurality of epitaxial silicon-germanium layers (102, 102') and a plurality of epitaxial silicon layers (104, 104'); patterning said stack to form a plurality of fin structures separated by trenches, the patterning comprising etching said stack; forming a plurality of spacers across and on the plurality of fin structures; forming a sacrificial gate electrode between the plurality of spacers and around portions of the plurality of fin structures located between the spacers, removing a portion of each of the plurality of fin structures from the substrate, the portion not being located between the spacers, to expose a respective plurality of source/drain regions on the substrate, the plurality of source/drain regions being adjacent to the plurality of spacers; forming an epitaxial source/drain structure in each of the plurality of source/drain regions; removing the sacrificial gate electrode from between the plurality of spacers; removing the plurality of epitaxial silicon layers or the plurality of epitaxial silicon germanium layers from the plurality of fin structures disposed between the plurality of spacers to form a plurality of silicon-germanium nanowire structures (104, 104') or a plurality of silicon nanowire structures (102, 102') respectively; depositing a gate dielectric material around each of the plurality of silicon-germanium nanowire structures (104, 104') or around each of the plurality of silicon nanowires structures (102, 102'); and forming a gate electrode material around the gate dielectric material, wherein the gate electrode material surrounds the plurality of silicon-germanium nanowire structures (104, 104'), or the plurality of silicon nanowires structures (102, 102'), and fills a gap between the plurality of germanium nanowire structures (104, 104') or between the plurality of silicon nanowire structures (102, 102').