A dynamic random access memory, DRAM, cache management circuit, communicatively coupled to a DRAM cache that is part of a high-bandwidth memory and being further communicatively coupled to a system memory DRAM, wherein: the DRAM cache is configured to cache memory lines (114 - 114) from the system memory DRAM; the system memory DRAM is configured to store a master table for storing cache indicators (118 - 118) for memory lines in the system memory, wherein a cache indicator indicates whether a corresponding memory line is stored in the DRAM cache; the DRAM cache management circuit comprising a DRAM cache indicator cache configured to cache a plurality of DRAM cache indicators read from the master table in the system memory DRAM, wherein: the DRAM cache management circuit is configured to: receive a memory read request comprising a read address specifying a memory address from which to retrieve data; determine whether the read address is found in the DRAM cache indicator cache; responsive to determining that the read address is not found in the DRAM cache indicator cache, read data at the read address in the system memory DRAM; and responsive to determining that the read address is found in the DRAM cache indicator cache: determine, based on the DRAM cache indicator cache, whether the read address is found in the DRAM cache; responsive to determining that the read address is not found in the DRAM cache, read data at the read address in the system memory DRAM; and responsive to determining that the read address is found in the DRAM cache, read data for the read address from the DRAM cache. the DRAM cache is configured to cache memory lines (114 - 114) from the system memory DRAM; the system memory DRAM is configured to store a master table for storing cache indicators (118 - 118) for memory lines in the system memory, wherein a cache indicator indicates whether a corresponding memory line is stored in the DRAM cache; the DRAM cache management circuit comprising a DRAM cache indicator cache configured to cache a plurality of DRAM cache indicators read from the master table in the system memory DRAM, wherein: the DRAM cache management circuit is configured to: receive a memory read request comprising a read address specifying a memory address from which to retrieve data; determine whether the read address is found in the DRAM cache indicator cache; responsive to determining that the read address is not found in the DRAM cache indicator cache, read data at the read address in the system memory DRAM; and responsive to determining that the read address is found in the DRAM cache indicator cache: determine, based on the DRAM cache indicator cache, whether the read address is found in the DRAM cache; responsive to determining that the read address is not found in the DRAM cache, read data at the read address in the system memory DRAM; and responsive to determining that the read address is found in the DRAM cache, read data for the read address from the DRAM cache. receive a memory read request comprising a read address specifying a memory address from which to retrieve data; determine whether the read address is found in the DRAM cache indicator cache; responsive to determining that the read address is not found in the DRAM cache indicator cache, read data at the read address in the system memory DRAM; and responsive to determining that the read address is found in the DRAM cache indicator cache: determine, based on the DRAM cache indicator cache, whether the read address is found in the DRAM cache; responsive to determining that the read address is not found in the DRAM cache, read data at the read address in the system memory DRAM; and responsive to determining that the read address is found in the DRAM cache, read data for the read address from the DRAM cache. determine, based on the DRAM cache indicator cache, whether the read address is found in the DRAM cache; responsive to determining that the read address is not found in the DRAM cache, read data at the read address in the system memory DRAM; and responsive to determining that the read address is found in the DRAM cache, read data for the read address from the DRAM cache.