A display device comprising: a scan line and a signal line intersecting with each other over a substrate; a pixel portion in which pixel electrodes are arranged in matrix; and a protective circuit provided over the substrate and in a region outside the pixel portion, the protective circuit connecting the scan line and a common wiring, wherein the pixel portion comprises a thin film transistor in which a channel formation region is formed in an oxide semiconductor layer, wherein the protective circuit includes a first non-linear element and a second non-linear element, wherein the first non-linear element comprises: a first gate electrode connected to the scan line; a first oxide semiconductor layer formed over the first gate electrode with a gate insulating film interposed therebetween; a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer (115a, 115b) and a second oxide semiconductor layer (114, 114a, 114b) and whose end portions overlap with the first gate electrode; and wherein the second non-linear element comprises: a second gate electrode connected to the common wiring; a third oxide semiconductor layer over the second gate electrode with the gate insulating film interposed therebetween; a third wiring layer and a fourth wiring layer each of which is formed by stacking a conductive layer and a fourth oxide semiconductor layer; and wherein the first wiring layer is in contact with the first oxide semiconductor layer and the common wiring; wherein the second wiring layer is in contact with the first oxide semiconductor layer and the scan line formed with the same layer as the first gate electrode; wherein the third wiring layer is in contact with the third oxide semiconductor layer and the common wiring; characterized in that the scan line formed using the same layer as the first gate electrode and the first wiring layer of the first non-linear element are directly connected through a contact hole provided in the gate insulating film such that a number of interfaces formed for connection is reduced to be one. a scan line and a signal line intersecting with each other over a substrate; a pixel portion in which pixel electrodes are arranged in matrix; and a protective circuit provided over the substrate and in a region outside the pixel portion, the protective circuit connecting the scan line and a common wiring, wherein the pixel portion comprises a thin film transistor in which a channel formation region is formed in an oxide semiconductor layer, wherein the protective circuit includes a first non-linear element and a second non-linear element, wherein the first non-linear element comprises: a first gate electrode connected to the scan line; a first oxide semiconductor layer formed over the first gate electrode with a gate insulating film interposed therebetween; a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer (115a, 115b) and a second oxide semiconductor layer (114, 114a, 114b) and whose end portions overlap with the first gate electrode; and a first gate electrode connected to the scan line; a first oxide semiconductor layer formed over the first gate electrode with a gate insulating film interposed therebetween; a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer (115a, 115b) and a second oxide semiconductor layer (114, 114a, 114b) and whose end portions overlap with the first gate electrode; and wherein the second non-linear element comprises: a second gate electrode connected to the common wiring; a third oxide semiconductor layer over the second gate electrode with the gate insulating film interposed therebetween; a third wiring layer and a fourth wiring layer each of which is formed by stacking a conductive layer and a fourth oxide semiconductor layer; and a second gate electrode connected to the common wiring; a third oxide semiconductor layer over the second gate electrode with the gate insulating film interposed therebetween; a third wiring layer and a fourth wiring layer each of which is formed by stacking a conductive layer and a fourth oxide semiconductor layer; and wherein the first wiring layer is in contact with the first oxide semiconductor layer and the common wiring; wherein the second wiring layer is in contact with the first oxide semiconductor layer and the scan line formed with the same layer as the first gate electrode; wherein the third wiring layer is in contact with the third oxide semiconductor layer and the common wiring; characterized in that the scan line formed using the same layer as the first gate electrode and the first wiring layer of the first non-linear element are directly connected through a contact hole provided in the gate insulating film such that a number of interfaces formed for connection is reduced to be one.