A White Light Emitting Diode, WLED, driver, comprising a boost converter, a controller, and N channels, wherein N is a positive integer that is greater than 1, and each channel comprises a current sink, CS, module,, wherein each CS module is configured to drive a corresponding WLED string, and each CS module comprises an error amplifier EA, a negative-metal-oxide-semiconductor NMOS transistor, and a feedback resistor, wherein each CS module further comprises N gate switches (V G1,...,VG N) and N feedback switches (V FB1,...,V FBN), the boost converter is configured to regulate an output voltage of the WLED driver according to a maximum quantity of WLEDs in a WLED string corresponding to any channel; for each CS module, one end of each of N gate switches (V G1,...,V GN) is connected to an output end of the error amplifier, another end of each of the N gate switches (V G1,...,V GN) is connected to a respective gate of the NMOS transistor of the respective CS module, one end of each of the N feedback switches (V FB1,...,V FBN) is connected to a negative input end of the error amplifier, another end of each of the N feedback switches (V FB1,...,V FBN) is connected to a positive input end of the respective feedback resistor of the respective CS module, and each CS module is configured to determine an intensity of a current flowing through its WLED string; and the control circuit is configured to generate a clock signal group Φ group, and control switching actions of each of the gate and feedback switches on a time-division basis according to the clock control signal group Φ group, so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis; wherein the clock signal group Φ group = (Φ 1, Φ 2,..., Φ N), the clock control signal group Φ group comprises N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φ i+j has a delay of j × T N in comparison with Φ i, and T is a clock period of each phase clock. the boost converter is configured to regulate an output voltage of the WLED driver according to a maximum quantity of WLEDs in a WLED string corresponding to any channel; for each CS module, one end of each of N gate switches (V G1,...,V GN) is connected to an output end of the error amplifier, another end of each of the N gate switches (V G1,...,V GN) is connected to a respective gate of the NMOS transistor of the respective CS module, one end of each of the N feedback switches (V FB1,...,V FBN) is connected to a negative input end of the error amplifier, another end of each of the N feedback switches (V FB1,...,V FBN) is connected to a positive input end of the respective feedback resistor of the respective CS module, and each CS module is configured to determine an intensity of a current flowing through its WLED string; and the control circuit is configured to generate a clock signal group Φ group, and control switching actions of each of the gate and feedback switches on a time-division basis according to the clock control signal group Φ group, so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis; wherein the clock signal group Φ group = (Φ 1, Φ 2,..., Φ N), the clock control signal group Φ group comprises N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φ i+j has a delay of j × T N in comparison with Φ i, and T is a clock period of each phase clock.