A gate driver circuit usable in a liquid crystal display, comprising: (a) a gate IC internal circuit for generating a scanning signal; and (b) a gate IC output buffer circuit for modifying said scanning signal according to a linear function and for providing said modified scanning signal to a gate line loading circuit of the liquid crystal display, said gate IC output buffer having a set of circuit components comprising: i) a PMOS transistor having a source line coupled to a VGG voltage, a gate line connected to said gate IC internal circuit, and a drain line connected to said gate line loading circuit of the liquid crystal display; ii) a first NMOS transistor having a source line coupled to a VEE voltage, a gate line connected to said gate IC internal circuit, and a drain line connected to said drain line of said PMOS transistor; and iii) a second NMOS transistor having a source line connected to a >VEE voltage (>VEE), a gate line connected to said gate IC internal circuit, and a drain line connected to said drain line of said PMOS transistor, wherein said gate IC output buffer circuit is configured such that when said scanning signal falls, the second NMOS transistor is turned on for discharging of said scanning signal at a first current for a period of time, and the first NMOS transistor is subsequently turned on for discharging of said scanning signal at a second current greater than the first current, so as to modify the falling edge of said scanning signal according to a linear function that defines a waveform shape for said modified scanning signal. (a) a gate IC internal circuit for generating a scanning signal; and (b) a gate IC output buffer circuit for modifying said scanning signal according to a linear function and for providing said modified scanning signal to a gate line loading circuit of the liquid crystal display, said gate IC output buffer having a set of circuit components comprising: i) a PMOS transistor having a source line coupled to a VGG voltage, a gate line connected to said gate IC internal circuit, and a drain line connected to said gate line loading circuit of the liquid crystal display; ii) a first NMOS transistor having a source line coupled to a VEE voltage, a gate line connected to said gate IC internal circuit, and a drain line connected to said drain line of said PMOS transistor; and iii) a second NMOS transistor having a source line connected to a >VEE voltage (>VEE), a gate line connected to said gate IC internal circuit, and a drain line connected to said drain line of said PMOS transistor, wherein said gate IC output buffer circuit is configured such that when said scanning signal falls, the second NMOS transistor is turned on for discharging of said scanning signal at a first current for a period of time, and the first NMOS transistor is subsequently turned on for discharging of said scanning signal at a second current greater than the first current, so as to modify the falling edge of said scanning signal according to a linear function that defines a waveform shape for said modified scanning signal. i) a PMOS transistor having a source line coupled to a VGG voltage, a gate line connected to said gate IC internal circuit, and a drain line connected to said gate line loading circuit of the liquid crystal display; ii) a first NMOS transistor having a source line coupled to a VEE voltage, a gate line connected to said gate IC internal circuit, and a drain line connected to said drain line of said PMOS transistor; and iii) a second NMOS transistor having a source line connected to a >VEE voltage (>VEE), a gate line connected to said gate IC internal circuit, and a drain line connected to said drain line of said PMOS transistor, wherein said gate IC output buffer circuit is configured such that when said scanning signal falls, the second NMOS transistor is turned on for discharging of said scanning signal at a first current for a period of time, and the first NMOS transistor is subsequently turned