A processor, comprising: a front end to receive an instruction; a decoder to decode the instruction; a core to execute the instruction, including: a first logic to retrieve a first index value from an array of indices, wherein the array of indices is to be located at an index base address in a memory based on a first parameter for the instruction; a second logic to compute a first element address, the first element address to identify from where a first data element is to be prefetched from the memory based on: the first index value; and a data base address for a group of data element locations in the memory, the data base address based on a second parameter for the instruction; and a third logic to prefetch the first data element with the first element address; a fourth logic to write the first data element to a cache (1822, 1824); a retirement unit to retire the instruction; a fifth logic to retrieve a second index value from the array of indices, wherein: the second index value is to be located at the lowest-order position within the array of indices or the second index value is to precede the first index value within the array of indices by a fixed distance; a sixth logic to compute a second element address, the second element address to identify from where a second data element is to be gathered from the memory based on: the second index value; and the data base address; and a seventh logic to retrieve the second data element with the second element address; an eighth logic to store the second data element to a destination vector register identified by a third parameter of the instruction, wherein the second data element is to be stored to the lowest-order position in the destination vector register; and a ninth logic to determine the fixed distance. a front end to receive an instruction; a decoder to decode the instruction; a core to execute the instruction, including: a first logic to retrieve a first index value from an array of indices, wherein the array of indices is to be located at an index base address in a memory based on a first parameter for the instruction; a second logic to compute a first element address, the first element address to identify from where a first data element is to be prefetched from the memory based on: the first index value; and a data base address for a group of data element locations in the memory, the data base address based on a second parameter for the instruction; and a third logic to prefetch the first data element with the first element address; a fourth logic to write the first data element to a cache (1822, 1824); a first logic to retrieve a first index value from an array of indices, wherein the array of indices is to be located at an index base address in a memory based on a first parameter for the instruction; a second logic to compute a first element address, the first element address to identify from where a first data element is to be prefetched from the memory based on: the first index value; and a data base address for a group of data element locations in the memory, the data base address based on a second parameter for the instruction; and the first index value; and a data base address for a group of data element locations in the memory, the data base address based on a second parameter for the instruction; and a third logic to prefetch the first data element with the first element address; a fourth logic to write the first data element to a cache (1822, 1824); a retirement unit to retire the instruction; a fifth logic to retrieve a second index value from the array of indices, wherein: the second index value is to be located at the lowest-order position within the array of indices or the second index value is to precede the first index value within the array of indices by a fixed distance; a sixth logic to compute a second element address, the second element address to identify from where a second data element is to be gathered from the memory based on: the second index value; and the data base address; and the second index value; and the data base address; and a seventh logic to retrieve the second data element with the second element address; an eighth logic to store the second data element to a destination vector register identified by a third parameter of the instruction, wherein the second data element is to be stored to the lowest-order position in the destination vector register; and a ninth logic to determine the fixed distance.