A circuitry system comprising a first and a synchronous second clock domain (A, B) of a streaming data bus system that employs a handshake-type transfer protocol, characterized in that the circuitry system further comprises a clock domain separation device connected into the streaming data link between the first and said second clock domains to connect the two clock domains (A, B) and to enable the clock in the clock domains to be switched on and off independently from each other while maintaining data integrity of the streaming data, said device comprising: a control logic having a sink interface for receiving control signals from and returning control signals to a data source arranged in said first clock domain, a source interface for transmitting control signals to and receiving control signals from a data sink arranged in said second clock domain, and a system clock input, a data output buffer, an auxiliary input buffer, and a multiplexer, wherein said control logic is connected to each of said data output buffer, auxiliary input buffer, and multiplexer, and wherein: the auxiliary input buffer and the multiplexer each have a data input connected to the same data line to receive a data stream from said data source of the first clock domain, a data output of the auxiliary input buffer is connected to a second data input of the multiplexer, a data output of the multiplexer is connected to the data output buffer, a data output of said data output buffer is connected to a data output line to transmit data to said data sink of the second clock domain, and wherein the clock domain separation device introduces a latency of one clock cycle in forward and backward transfer directions. a control logic having a sink interface for receiving control signals from and returning control signals to a data source arranged in said first clock domain, a source interface for transmitting control signals to and receiving control signals from a data sink arranged in said second clock domain, and a system clock input, a data output buffer, an auxiliary input buffer, and a multiplexer, wherein said control logic is connected to each of said data output buffer, auxiliary input buffer, and multiplexer, and wherein: the auxiliary input buffer and the multiplexer each have a data input connected to the same data line to receive a data stream from said data source of the first clock domain, a data output of the auxiliary input buffer is connected to a second data input of the multiplexer, a data output of the multiplexer is connected to the data output buffer, a data output of said data output buffer is connected to a data output line to transmit data to said data sink of the second clock domain, and wherein the clock domain separation device introduces a latency of one clock cycle in forward and backward transfer directions. the auxiliary input buffer and the multiplexer each have a data input connected to the same data line to receive a data stream from said data source of the first clock domain, a data output of the auxiliary input buffer is connected to a second data input of the multiplexer, a data output of the multiplexer is connected to the data output buffer, a data output of said data output buffer is connected to a data output line to transmit data to said data sink of the second clock domain, and wherein the clock domain separation device introduces a latency of one clock cycle in forward and backward transfer directions.