An electrically erasable programmable nonvolatile memory cell comprising: a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate; a channel region between the first substrate region and the bottom portion of the trench region, the channel region having: a first channel portion adjacent to the first substrate region; a second channel portion adjacent to the first channel portion and the trench region; and a third channel portion adjacent to the second channel portion and comprising the sidewall portion of the trench region; an electrically conductive control gate insulated from and disposed over the first channel portion but not over the second and third channel portions; an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, the floating gate having: a first floating gate portion disposed inside the trench; and a second floating gate portion longer than the first floating gate portion, disposed above the trench and extending away from the trench, the second floating gate portion being electrically connected to the first floating gate portion on a first end and having a tip on a second end; an insulation region disposed over the second channel portion between the control gate and the second floating gate portion; an electrically conductive source line electrically connected to the trench region, the source line extending away from the substrate and forming a first capacitive coupling with the floating gate; a dielectric layer between the floating gate and the source line; and an electrically conductive erase gate insulated from and disposed over the tip of the second floating gate portion. a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate; a channel region between the first substrate region and the bottom portion of the trench region, the channel region having: a first channel portion adjacent to the first substrate region; a second channel portion adjacent to the first channel portion and the trench region; and a third channel portion adjacent to the second channel portion and comprising the sidewall portion of the trench region; a first channel portion adjacent to the first substrate region; a second channel portion adjacent to the first channel portion and the trench region; and a third channel portion adjacent to the second channel portion and comprising the sidewall portion of the trench region; an electrically conductive control gate insulated from and disposed over the first channel portion but not over the second and third channel portions; an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, the floating gate having: a first floating gate portion disposed inside the trench; and a second floating gate portion longer than the first floating gate portion, disposed above the trench and extending away from the trench, the second floating gate portion being electrically connected to the first floating gate portion on a first end and having a tip on a second end; a first floating gate portion disposed inside the trench; and a second floating gate portion longer than the first floating gate portion, disposed above the trench and extending away from the trench, the second floating gate portion being electrically connected to the first floating gate portion on a first end and having a tip on a second end; an insulation region disposed over the second channel portion between the control gate and the second floating gate portion; an electrically conductive source line electrically connected to the trench region, the source line extending away from the substrate and forming a first capacitive coupling with the floating gate; a dielectric layer between the floating gate and the source line; and an electrically conductive erase gate insulated from and disposed over the tip of the second floating gate portion.