An infrared imaging system comprising: an infrared imaging sensor configured to provide infrared image data comprising a plurality of pixels; and a main electronics block configured to receive the infrared image data, the main electronics block comprising: a plurality of vector processors (206 -206(n)), each configured to operate on multiple pixels in parallel, wherein each of the plurality of vector processors (206 -206(n)) comprises vector functional units configured to selectably provide a number of lanes for processing the multiple pixels; a plurality of local memories communicatively coupled to the plurality of vector processors (206 -206(n)), the plurality of local memories being addressable and accessible by the plurality of vector processors (206 -206(n)) to store and access at least a portion of the infrared image data comprising the multiple pixels; and a general-purpose processor configured to enable, disable, or control the plurality of vector processors (206 -206(n)); wherein the multiple pixels operated on by at least one of the plurality of vector processors (206 -206(n)) are selected from the plurality of pixels of the infrared image data; wherein a first vector processor (206) of the plurality of vector processors (206 -206(n)) is configured to execute a first set of vector instructions on the multiple pixels accessed from the plurality of local memories to perform one or more operations of a video processing chain for the infrared image data, wherein the first set of vector instructions associated with the first vector processor (206) includes instructions for performing gain and offset correction; and wherein a second vector processor (206) of the plurality of vector processors (206 -206(n)) is configured to execute a second set of vector instructions on the multiple pixels previously processed by the first vector processor (206) and accessed from the plurality of local memories to perform one or more operations of video analytics for the infrared data, the second set of vector instructions being different from the first set of vector instructions. an infrared imaging sensor configured to provide infrared image data comprising a plurality of pixels; and a main electronics block configured to receive the infrared image data, the main electronics block comprising: a plurality of vector processors (206 -206(n)), each configured to operate on multiple pixels in parallel, wherein each of the plurality of vector processors (206 -206(n)) comprises vector functional units configured to selectably provide a number of lanes for processing the multiple pixels; a plurality of local memories communicatively coupled to the plurality of vector processors (206 -206(n)), the plurality of local memories being addressable and accessible by the plurality of vector processors (206 -206(n)) to store and access at least a portion of the infrared image data comprising the multiple pixels; and a general-purpose processor configured to enable, disable, or control the plurality of vector processors (206 -206(n)); a plurality of vector processors (206 -206(n)), each configured to operate on multiple pixels in parallel, wherein each of the plurality of vector processors (206 -206(n)) comprises vector functional units configured to selectably provide a number of lanes for processing the multiple pixels; a plurality of local memories communicatively coupled to the plurality of vector processors (206 -206(n)), the plurality of local memories being addressable and accessible by the plurality of vector processors (206 -206(n)) to store and access at least a portion of the infrared image data comprising the multiple pixels; and a general-purpose processor configured to enable, disable, or control the plurality of vector processors (206 -206(n)); wherein the multiple pixels operated on by at least one of the plurality of vector processors (206 -206(n)) are selected from the plurality of pixels of the infrared image data; wherein a first vector processor (206) of the plurality of vector processors (206 -206(n)) is configured to execute a first set of vector instructions on the multiple pixels accessed from the plurality of local memories to perform one or more operations of a video processing chain for the infrared image data, wherein the first set of vector instructions associated with the first vector processor (206) includes instructions for performing gain and offset correction; and wherein a second vector processor (206) of the plurality of vector processors (206 -206(n)) is configured to execute a second set of vector instructions on the multiple pixels previously processed by the first vector processor (206) and accessed from the plurality of local memories to perform one or more operations of video analytics for the infrared data, the second set of vector instructions being different from the first set of vector instructions.