An error-handling method, the error-handling method being applicable to a data storage device, the data storage device comprising a non-volatile memory and a memory controller arranged to control the access of the NV memory, the NV memory comprising at least one NV memory element (122, 122-1, 122-2,...,122-N), the at least one NV memory element (122, 122-1, 122-2,...,122-N) comprising a plurality of blocks, characterized in that the error-handling method comprises: uploading an error-handling program to a buffer memory equipped with error correction code protection capability, wherein the buffer memory is positioned in the memory controller; in response to at least one error occurring during NV memory access, interrupting execution of a current NV memory access procedure and activating an interruption service; executing the error-handling program on the buffer memory; disabling a transmission interface circuit, wherein the transmission interface circuit is positioned in the memory controller, and is arranged to perform communications with a host device; resetting the at least one NV memory element (122, 122-1, 122-2,...,122-N) and at least one hardware engine positioned in a control logic circuit wherein the control logic circuit is positioned in the memory controller, the hardware engine being one of an ECC engine of an ECC circuit or a flash engine of a flash controller; performing cache rearrangement regarding a data cache within the data storage device, comprising: when the memory controller determines at least a write command has been received from the host device for which corresponding data has not been written to the NV memory, allocating cache space of the data cache corresponding to a total number of received write commands; and when the memory controller determines data of the write commands received from the host device has not been totally buffered into the data cache, resynchronizing the data cache by moving a cache head of the data cache according to buffered data of the write commands; programming the rearranged cache data into the at least one NV memory element (122, 122-1, 122-2,...,122-N) to perform data recovery; and through activating a watchdog module in the memory controller, activating the transmission interface circuit and relinking with the host device, completing soft reset to make the data storage device operate normally again. uploading an error-handling program to a buffer memory equipped with error correction code protection capability, wherein the buffer memory is positioned in the memory controller; in response to at least one error occurring during NV memory access, interrupting execution of a current NV memory access procedure and activating an interruption service; executing the error-handling program on the buffer memory; disabling a transmission interface circuit, wherein the transmission interface circuit is positioned in the memory controller, and is arranged to perform communications with a host device; resetting the at least one NV memory element (122, 122-1, 122-2,...,122-N) and at least one hardware engine positioned in a control logic circuit wherein the control logic circuit is positioned in the memory controller, the hardware engine being one of an ECC engine of an ECC circuit or a flash engine of a flash controller; performing cache rearrangement regarding a data cache within the data storage device, comprising: when the memory controller determines at least a write command has been received from the host device for which corresponding data has not been written to the NV memory, allocating cache space of the data cache corresponding to a total number of received write commands; and when the memory controller determines data of the write commands received from the host device has not been totally buffered into the data cache, resynchronizing the data cache by moving a cache head of the data cache according to buffered data of the write commands; when the memory controller determines at least a write command has been received from the host device for which corresponding data has not been written to the NV memory, allocating cache space of the data cache corresponding to a total number of received write commands; and when the memory controller determines data of the write commands received from the host device has not been totally buffered into the data cache, resynchronizing the data cache by moving a cache head of the data cache according to buffered data of the write commands; programming the rearranged cache data into the at least one NV memory element (122, 122-1, 122-2,...,122-N) to perform data recovery; and through activating a watchdog module in the memory controller, activating the transmission interface circuit and relinking with the host device, completing soft reset to make the data storage device operate normally again.