A memory device comprising: a memory array including memory cells to store memory data; a memory controller operatively coupled to the memory array and including: a prefetch buffer; a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, wherein the read address buffer is an M memory register buffer, wherein M is a positive integer; and logic circuitry configured to: store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer; omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer; preserve read addresses stored in N memory registers of the M memory registers, wherein N is a positive integer less than M; and preserve a read address in one of the N memory registers until a read address is received that is continuous to the preserved read address. wherein the logic circuitry is configured to flush the preserved read address when the read address that is continuous to the read prefetch address is received, or a read address continuous to the preserved read address is not received within P read requests of a read request corresponding to the preserved read address, wherein P is a positive integer greater than M. a memory array including memory cells to store memory data; a memory controller operatively coupled to the memory array and including: a prefetch buffer; a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, wherein the read address buffer is an M memory register buffer, wherein M is a positive integer; and logic circuitry configured to: store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer; omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer; preserve read addresses stored in N memory registers of the M memory registers, wherein N is a positive integer less than M; and preserve a read address in one of the N memory registers until a read address is received that is continuous to the preserved read address. wherein the logic circuitry is configured to flush the preserved read address when the read address that is continuous to the read prefetch address is received, or a read address continuous to the preserved read address is not received within P read requests of a read request corresponding to the preserved read address, wherein P is a positive integer greater than M. a prefetch buffer; a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, wherein the read address buffer is an M memory register buffer, wherein M is a positive integer; and logic circuitry configured to: store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer; omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer; preserve read addresses stored in N memory registers of the M memory registers, wherein N is a positive integer less than M; and preserve a read address in one of the N memory registers until a read address is received that is continuous to the preserved read address. wherein the logic circuitry is configured to flush the preserved read address when the read address that is continuous to the read prefetch address is received, or a read address continuous to the preserved read address is not received within P read requests of a read request corresponding to the preserved read address, wherein P is a positive integer greater than M. store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer; omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer; preserve read addresses stored in N memory registers of the M memory registers, wherein N is a positive integer less than M; and preserve a read address in one of the N memory registers until a read address is received that is continuous to the preserved read address. wherein the logic circuitry is configured to flush the preserved read address when the read address that is continuous to the read prefetch address is received, or a read address continuous to the preserved read address is not received within P read requests of a read request corresponding to the preserved read address, wherein P is a positive integer greater than M.