A level shift circuit comprising: a first series circuit wherein a first resistor (Rpar1) in a semiconductor substrate, a first switching element connected to an input terminal for inputting a first level shift input signal, and a first level shift output terminal for outputting a first level shift output signal are connected in series; a second series circuit wherein a second resistor (Rpar2) in a semiconductor substrate, a second switching element connected to an input terminal for inputting a second level shift input signal, and a second level shift output terminal for outputting a second level shift output signal are connected in series; and a first feedback transistor connected in parallel to the first resistor (Rpar1) and a second feedback transistor connected in parallel to the second resistor (Rpar2), wherein the gate of the first feedback transistor is connected to the second level shift output terminal, and the gate of the second feedback transistor is connected to the first level shift output terminal, characterized by rise detector circuits (321, 322), connected to the first series circuit and second series circuit and into which are input the first level shift output signal and second level shift output signal output from the first series circuit and second series circuit respectively, that are configured to compare the rising potential of the first level shift output signal and second level shift output signal with a predetermined threshold value, and to output a first output signal and second output signal, which are pulse outputs of a constant duration, when the threshold value is exceeded; a third switching element connected in parallel to the first resistor (Rpar1), wherein the source terminal of the third switching element is connected to a power source potential, the drain terminal of the third switching element is connected to the first level shift output terminal, and the gate terminal of the third switching element is connected to the rise detector circuits (321, 322); and a fourth switching element connected in parallel to the second resistor (Rpar2), wherein the source terminal of the fourth switching element is connected to a power source potential, the drain terminal of the fourth switching element is connected to the second level shift output terminal, and the gate terminal of the fourth switching element is connected to the rise detector circuits (321, 322), wherein the third switching element is turned on by the first output signal from the rise detector circuits (321, 322), and the fourth switching element is turned on by the second output signal from the rise detector circuits (321, 322). a first series circuit wherein a first resistor (Rpar1) in a semiconductor substrate, a first switching element connected to an input terminal for inputting a first level shift input signal, and a first level shift output terminal for outputting a first level shift output signal are connected in series; a second series circuit wherein a second resistor (Rpar2) in a semiconductor substrate, a second switching element connected to an input terminal for inputting a second level shift input signal, and a second level shift output terminal for outputting a second level shift output signal are connected in series; and a first feedback transistor connected in parallel to the first resistor (Rpar1) and a second feedback transistor connected in parallel to the second resistor (Rpar2), wherein the gate of the first feedback transistor is connected to the second level shift output terminal, and the gate of the second feedback transistor is connected to the first level shift output terminal, characterized by rise detector circuits (321, 322), connected to the first series circuit and second series circuit and into which are input the first level shift output signal and second level shift output signal output from the first series circuit and second series circuit respectively, that are configured to compare the rising potential of the first level shift output signal and second level shift output signal with a predetermined threshold value, and to output a first output signal and second output signal, which are pulse outputs of a constant duration, when the threshold value is exceeded; a third switching element connected in parallel to the first resistor (Rpar1), wherein the source terminal of the third switching element is connected to a power source potential, the drain terminal of the third switching element is connected to the first level shift output terminal, and the gate terminal of the third switching element is connected to the rise detector circuits (321, 322); and a fourth switching element connected in parallel to the second resistor (Rpar2), wherein the source terminal of the fourth switching element is connected to a power source potential, the drain terminal of the fourth switching element is connected to the second level shift output terminal, and the gate terminal of the fourth switching element is connected to the rise detector circuits (321, 322), wherein the third switching element is turned on by the first output signal from the rise detector circuits (321, 322), and the fourth switching element is turned on by the second output signal from the rise detector circuits (321, 322).