A method for retiming an integrated circuit design in an electronic design automation environment, comprising: performing a timing analysis for one or more paths in the integrated circuit design to obtain delay times for a signal propagating along the paths; selecting a path based on the delay times obtained, the path selected having a delay time that fails a timing constraint, the path selected originating at a source sequential element and ending at a destination sequential element, the path selected further comprising two or more logic instances (40,44); determining a retiming location along the path selected where one of the source sequential element or the destination sequential element can be repositioned in order to satisfy the timing constraint, the retiming location being at least two logic instances (40,44) from the one of the source sequential element or the destination sequential element, wherein the act of determining the retiming location comprises determining whether one or more additional sequential elements need to be repositioned to the retiming location or to one or more additional retiming locations in order to maintain circuit functionality by: performing at least one forward trace from one or more output pins of a logic instance across which the one of the source sequential element or the destination sequential element can be repositioned, and performing at least one backward trace from one or more input pins of the logic instance across which the one of the source sequential element or the destination sequential element can be repositioned; relaxing architectural or structural constraints of the one of the source sequential element or the destination sequential element, wherein the act of relaxing architectural or structural constraints comprises separating one or more control signals from the one of the source sequential element or the destination sequential element; and updating a design database of the integrated circuit design to reposition the one of the source sequential element or the destination sequential element to the retiming location. performing a timing analysis for one or more paths in the integrated circuit design to obtain delay times for a signal propagating along the paths; selecting a path based on the delay times obtained, the path selected having a delay time that fails a timing constraint, the path selected originating at a source sequential element and ending at a destination sequential element, the path selected further comprising two or more logic instances (40,44); determining a retiming location along the path selected where one of the source sequential element or the destination sequential element can be repositioned in order to satisfy the timing constraint, the retiming location being at least two logic instances (40,44) from the one of the source sequential element or the destination sequential element, wherein the act of determining the retiming location comprises determining whether one or more additional sequential elements need to be repositioned to the retiming location or to one or more additional retiming locations in order to maintain circuit functionality by: performing at least one forward trace from one or more output pins of a logic instance across which the one of the source sequential element or the destination sequential element can be repositioned, and performing at least one backward trace from one or more input pins of the logic instance across which the one of the source sequential element or the destination sequential element can be repositioned; performing at least one forward trace from one or more output pins of a logic instance across which the one of the source sequential element or the destination sequential element can be repositioned, and performing at least one backward trace from one or more input pins of the logic instance across which the one of the source sequential element or the destination sequential element can be repositioned; relaxing architectural or structural constraints of the one of the source sequential element or the destination sequential element, wherein the act of relaxing architectural or structural constraints comprises separating one or more control signals from the one of the source sequential element or the destination sequential element; and updating a design database of the integrated circuit design to reposition the one of the source sequential element or the destination sequential element to the retiming location.