An apparatus comprising: a memory comprising a fractional delay filter, FDF, module, a single adaptive fractionally spaced equalizer, AFSE, module and a block formation module; and a processor coupled to the memory, wherein the memory includes instructions that when executed by the processor cause the apparatus to perform the following: receive, by the FDF module, an incoming signal at a sampling rate that is greater than a symbol rate associated with the incoming signal; replicate, by the FDF module, M data streams from the incoming signal; apply, by the FDF module, a fractional delay for each data stream of M-1 data streams of the M data streams; and perform, by the single AFSE module, an adaptive equalization on M streams of data blocks formed, by the block formation module, from each data stream of the M data streams, wherein the fractional delay is applied to the data streams independently of the adaptive equalization, and wherein the adaptive equalization implements taps spaced at a fraction of a symbol interval associated with the incoming signal, and wherein the fractional delay is applied for each data stream of the M-1 data streams of the M data streams before the adaptive equalization is performed on the M streams of data blocks generated from each data stream of the M data streams; wherein the sampling rate is equal to α/T, wherein α is a rational number that has a range that is greater than one and less than two, and wherein T represents the symbol interval for the incoming signal; wherein α is equal to N/M, wherein N represents a number of input samples received in the incoming signal that correspond to M transmitted symbols; wherein the single AFSE module sequentially processes each of the incoming data blocks from the block formation module at a rate 1/T. a memory comprising a fractional delay filter, FDF, module, a single adaptive fractionally spaced equalizer, AFSE, module and a block formation module; and a processor coupled to the memory, wherein the memory includes instructions that when executed by the processor cause the apparatus to perform the following: receive, by the FDF module, an incoming signal at a sampling rate that is greater than a symbol rate associated with the incoming signal; replicate, by the FDF module, M data streams from the incoming signal; apply, by the FDF module, a fractional delay for each data stream of M-1 data streams of the M data streams; and perform, by the single AFSE module, an adaptive equalization on M streams of data blocks formed, by the block formation module, from each data stream of the M data streams, receive, by the FDF module, an incoming signal at a sampling rate that is greater than a symbol rate associated with the incoming signal; replicate, by the FDF module, M data streams from the incoming signal; apply, by the FDF module, a fractional delay for each data stream of M-1 data streams of the M data streams; and perform, by the single AFSE module, an adaptive equalization on M streams of data blocks formed, by the block formation module, from each data stream of the M data streams, wherein the fractional delay is applied to the data streams independently of the adaptive equalization, and wherein the adaptive equalization implements taps spaced at a fraction of a symbol interval associated with the incoming signal, and wherein the fractional delay is applied for each data stream of the M-1 data streams of the M data streams before the adaptive equalization is performed on the M streams of data blocks generated from each data stream of the M data streams; wherein the sampling rate is equal to α/T, wherein α is a rational number that has a range that is greater than one and less than two, and wherein T represents the symbol interval for the incoming signal; wherein α is equal to N/M, wherein N represents a number of input samples received in the incoming signal that correspond to M transmitted symbols; wherein the single AFSE module sequentially processes each of the incoming data blocks from the block formation module at a rate 1/T.