An apparatus (100/200) having a memory controller, the memory controller comprising: a host interface for receiving memory access requests, said memory access requests including access addresses; a memory interface for providing memory accesses to a memory system; an address decoder (522/610) coupled to said host interface for programmably mapping said access addresses to selected ones of a plurality of regions, wherein said address decoder (522/610) is programmable to map said access addresses to a first region having a non-power-of-two size using a primary decoder receiving said access addresses and having a first power-of-two size and a secondary decoder receiving said access addresses and having a second power-of-two size different from said first power-of-two size, and provides a first region mapping signal in response; a command queue coupled to said address decoder (522/610) for storing said memory access requests and region mapping signals; and an arbiter for picking said memory access requests from said command queue based on a plurality of criteria, said plurality of criteria evaluated based in part on said region mapping signals, and providing corresponding memory accesses to said memory interface in response, characterised in that: said address decoder (522/610) comprises a plurality of region decoders, wherein for each region decoder: said primary decoder is for receiving said access addresses and providing a primary region select signal, wherein said primary decoder has a first base address and a first power-of-two size; said secondary decoder is for receiving said access addresses and providing a secondary region select signal, wherein said secondary decoder has a second base address and a second power-of-two size; and a region decoder further comprises a logic circuit for activating a corresponding region mapping signal in response to an activation of at least one of said primary region select signal and said secondary region select signal. a host interface for receiving memory access requests, said memory access requests including access addresses; a memory interface for providing memory accesses to a memory system; an address decoder (522/610) coupled to said host interface for programmably mapping said access addresses to selected ones of a plurality of regions, wherein said address decoder (522/610) is programmable to map said access addresses to a first region having a non-power-of-two size using a primary decoder receiving said access addresses and having a first power-of-two size and a secondary decoder receiving said access addresses and having a second power-of-two size different from said first power-of-two size, and provides a first region mapping signal in response; a command queue coupled to said address decoder (522/610) for storing said memory access requests and region mapping signals; and an arbiter for picking said memory access requests from said command queue based on a plurality of criteria, said plurality of criteria evaluated based in part on said region mapping signals, and providing corresponding memory accesses to said memory interface in response, characterised in that: said address decoder (522/610) comprises a plurality of region decoders, wherein for each region decoder: said primary decoder is for receiving said access addresses and providing a primary region select signal, wherein said primary decoder has a first base address and a first power-of-two size; said secondary decoder is for receiving said access addresses and providing a secondary region select signal, wherein said secondary decoder has a second base address and a second power-of-two size; and a region decoder further comprises a logic circuit for activating a corresponding region mapping signal in response to an activation of at least one of said primary region select signal and said secondary region select signal. said primary decoder is for receiving said access addresses and providing a primary region select signal, wherein said primary decoder has a first base address and a first power-of-two size; said secondary decoder is for receiving said access addresses and providing a secondary region select signal, wherein said secondary decoder has a second base address and a second power-of-two size; and a region decoder further comprises a logic circuit for activating a corresponding region mapping signal in response to an activation of at least one of said primary region select signal and said secondary region select signal.