A semiconductor device, comprising: a semiconductor substrate (LR, 1S); a semiconductor layer disposed above the semiconductor substrate (LR, 1S), the semiconductor layer including a first region and a second region which surrounds the first region; a plurality of first conductivity type first pillars and a plurality of second pillars of a second conductivity type which is a reverse conductivity type of the first conductivity type formed in the semiconductor layer in the first region; a semiconductor element (GE, SR) formed over the semiconductor layer in the first region; and a plurality of third pillars of the first conductivity type and a plurality of fourth pillars of the second conductivity type formed in the semiconductor layer in the second region, wherein the semiconductor substrate (LR, 1S) is of the second conductivity type, wherein the first pillars and the second pillars are alternately arranged, and wherein the third pillars and the fourth pillars are alternately arranged, wherein each of the first pillars is arranged in a respective first ditch formed in the semiconductor layer, the first ditch being extended to an upper surface of the semiconductor substrate (LR, 1S), and wherein each of the third pillars is arranged in a respective second ditch formed in the semiconductor layer, the second ditch being extended to the upper surface of the semiconductor substrate (LR, 1S), the first ditch and the second ditch having the same depth, wherein, in the first region only, in a lower part of the first region of the semiconductor layer, a counter doped semiconductor region having an impurity of the second conductivity type is provided, the lower part being extended from the upper surface of the semiconductor substrate (LR, 1S) in a thickness direction toward the semiconductor element (GE, SR), and wherein an effective concentration of an impurity of the first conductivity type of the first pillars in the counter doped semiconductor region is lower than a concentration of an impurity of the first conductivity type of the first pillars in a part, other than the lower part in which the counter doped semiconductor region is provided. a semiconductor substrate (LR, 1S); a semiconductor layer disposed above the semiconductor substrate (LR, 1S), the semiconductor layer including a first region and a second region which surrounds the first region; a plurality of first conductivity type first pillars and a plurality of second pillars of a second conductivity type which is a reverse conductivity type of the first conductivity type formed in the semiconductor layer in the first region; a semiconductor element (GE, SR) formed over the semiconductor layer in the first region; and a plurality of third pillars of the first conductivity type and a plurality of fourth pillars of the second conductivity type formed in the semiconductor layer in the second region, wherein the semiconductor substrate (LR, 1S) is of the second conductivity type, wherein the first pillars and the second pillars are alternately arranged, and wherein the third pillars and the fourth pillars are alternately arranged, wherein each of the first pillars is arranged in a respective first ditch formed in the semiconductor layer, the first ditch being extended to an upper surface of the semiconductor substrate (LR, 1S), and wherein each of the third pillars is arranged in a respective second ditch formed in the semiconductor layer, the second ditch being extended to the upper surface of the semiconductor substrate (LR, 1S), the first ditch and the second ditch having the same depth, wherein, in the first region only, in a lower part of the first region of the semiconductor layer, a counter doped semiconductor region having an impurity of the second conductivity type is provided, the lower part being extended from the upper surface of the semiconductor substrate (LR, 1S) in a thickness direction toward the semiconductor element (GE, SR), and wherein an effective concentration of an impurity of the first conductivity type of the first pillars in the counter doped semiconductor region is lower than a concentration of an impurity of the first conductivity type of the first pillars in a part, other than the lower part in which the counter doped semiconductor region is provided.