An array of single-level polysilicon EEPROM memory cells arranged in a plurality of rows and columns on a substrate, the array comprising: row and column driver circuits (520, 530) operable to select one or more rows and columns of memory cells, respectively, to apply a programming voltage comprising first and second half-write voltages (VPP1, VPP2) associated with the row and column driver circuits (520, 530), respectively, to the selected memory cells associated with the selected rows and columns, and to apply one of the first and second half-write voltages (VPP1, VPP2) or less to the remaining unselected memory cells of the array during a program or erase operation; the EEPROM memory cells comprising: a MOS floating-gate transistor having a drain region connected to a column-source select line, for selecting and programming or erasing a first one of a column of selected memory cells; a tunneling region; a coupling capacitor connected to a row control line for controlling program and erase operations of a first one of a row of selected memory cells; and a floating gate of the transistor coupled to the tunneling region and the coupling capacitor at a common node therebetween, the floating gate used for storing a charge representing a data state of the memory cell; characterized in that one or more of the row and column driver circuits (520, 530) is isolated from the substrate to permit operation at a separate supply voltage. row and column driver circuits (520, 530) operable to select one or more rows and columns of memory cells, respectively, to apply a programming voltage comprising first and second half-write voltages (VPP1, VPP2) associated with the row and column driver circuits (520, 530), respectively, to the selected memory cells associated with the selected rows and columns, and to apply one of the first and second half-write voltages (VPP1, VPP2) or less to the remaining unselected memory cells of the array during a program or erase operation; the EEPROM memory cells comprising: a MOS floating-gate transistor having a drain region connected to a column-source select line, for selecting and programming or erasing a first one of a column of selected memory cells; a tunneling region; a coupling capacitor connected to a row control line for controlling program and erase operations of a first one of a row of selected memory cells; and a floating gate of the transistor coupled to the tunneling region and the coupling capacitor at a common node therebetween, the floating gate used for storing a charge representing a data state of the memory cell; characterized in that one or more of the row and column driver circuits (520, 530) is isolated from the substrate to permit operation at a separate supply voltage. a MOS floating-gate transistor having a drain region connected to a column-source select line, for selecting and programming or erasing a first one of a column of selected memory cells; a tunneling region; a coupling capacitor connected to a row control line for controlling program and erase operations of a first one of a row of selected memory cells; and a floating gate of the transistor coupled to the tunneling region and the coupling capacitor at a common node therebetween, the floating gate used for storing a charge representing a data state of the memory cell;