A semiconductor device comprising: a semiconductor body formed from a first semiconductor material; a first gate electrode disposed over an upper surface of the semiconductor body; a first sidewall spacer disposed along a sidewall of the first gate electrode; a second gate electrode disposed over an upper surface of the semiconductor body; a second sidewall spacer disposed along a sidewall of the second gate electrode; a first region embedded within the semiconductor body adjacent the first sidewall spacer; a second region embedded within the semiconductor body adjacent the second sidewall spacer; a third sidewall spacer disposed along a second sidewall of the first gate electrode, the second sidewall opposed from the first sidewall of said first gate electrode; a fourth sidewall spacer disposed along a second sidewall of the second gate electrode, the second sidewall opposed from the first sidewall of said second gate electrode; a third region (116a-r) embedded within the semiconductor body adjacent the third sidewall spacer; a fourth region (116b-l) embedded within the semiconductor body adjacent the fourth sidewall spacer; and a trench isolation structure surrounding the first and second gate electrodes (104a, 104b) and the first, second, third and fourth regions (116a-116b), characterized in that the first, second, third and fourth regions (116a-116b) are of a second semiconductor material; the trench isolation structure is laterally spaced from each of the first, second, third and fourth regions (116a-116b) of the second semiconductor material in the direction of a current path beneath the first and second gate electrodes (104a, 104b); and a length of the first, second, third and fourth regions (116a-116b) is constant in order to allow for a good stress optimization. a semiconductor body formed from a first semiconductor material; a first gate electrode disposed over an upper surface of the semiconductor body; a first sidewall spacer disposed along a sidewall of the first gate electrode; a second gate electrode disposed over an upper surface of the semiconductor body; a second sidewall spacer disposed along a sidewall of the second gate electrode; a first region embedded within the semiconductor body adjacent the first sidewall spacer; a second region embedded within the semiconductor body adjacent the second sidewall spacer; a third sidewall spacer disposed along a second sidewall of the first gate electrode, the second sidewall opposed from the first sidewall of said first gate electrode; a fourth sidewall spacer disposed along a second sidewall of the second gate electrode, the second sidewall opposed from the first sidewall of said second gate electrode; a third region (116a-r) embedded within the semiconductor body adjacent the third sidewall spacer; a fourth region (116b-l) embedded within the semiconductor body adjacent the fourth sidewall spacer; and a trench isolation structure surrounding the first and second gate electrodes (104a, 104b) and the first, second, third and fourth regions (116a-116b), characterized in that the first, second, third and fourth regions (116a-116b) are of a second semiconductor material; the trench isolation structure is laterally spaced from each of the first, second, third and fourth regions (116a-116b) of the second semiconductor material in the direction of a current path beneath the first and second gate electrodes (104a, 104b); and a length of the first, second, third and fourth regions (116a-116b) is constant in order to allow for a good stress optimization.