A complementary tunneling field effect transistor, comprising: a first drain region and a first source region that are disposed on a substrate, wherein the first drain region and the first source region comprise a first dopant; a first channel that is disposed on the first drain region and a second channel that is disposed on the first source region; a second source region that is disposed on the first channel and a second drain region that is disposed on the second channel, wherein the second source region and the second drain region comprise a second dopant; a first epitaxial layer that is disposed on and in direct contact with an upper surface of the first drain region and an upper surface of the second source region, and a second epitaxial layer that is disposed on and in direct contact with an upper surface of the second drain region and an upper surface of the first source region, wherein the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region; and a first gate stack layer that is disposed on and in direct contact with the first epitaxial layer, and a second gate stack layer that is disposed on and in direct contact with the second epitaxial layer, wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor. a first drain region and a first source region that are disposed on a substrate, wherein the first drain region and the first source region comprise a first dopant; a first channel that is disposed on the first drain region and a second channel that is disposed on the first source region; a second source region that is disposed on the first channel and a second drain region that is disposed on the second channel, wherein the second source region and the second drain region comprise a second dopant; a first epitaxial layer that is disposed on and in direct contact with an upper surface of the first drain region and an upper surface of the second source region, and a second epitaxial layer that is disposed on and in direct contact with an upper surface of the second drain region and an upper surface of the first source region, wherein the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region; and a first gate stack layer that is disposed on and in direct contact with the first epitaxial layer, and a second gate stack layer that is disposed on and in direct contact with the second epitaxial layer, wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor.