An imaging element comprising: a plurality of transfer paths configured to transfer, bit by bit, a time code of a predetermined number of bits for use in converting into a digital signal a pixel signal reflecting intensity of light received by a pixel, each of the plurality of transfer paths including a latch storage section configured to store the time code correspondingly bit by bit, wherein the pixel comprises an analog digital converter, ADC,; a relief transfer path configured the same as the transfer paths; a determination circuit configured to determine a presence or an absence of an error on a transfer path of the plurality of transfer paths; and a data line selection circuit (121, 122) including a plurality of switches, each transfer path of the plurality of transfer paths being connected to a corresponding switch of the plurality of switches, wherein the plurality of switches are configured to switch connection of the transfer path of the plurality of transfer paths with the relief transfer path based on the determination of the presence or the absence of an error on the transfer path, performed by the determination circuit, wherein the connection is switched to use the relief transfer path as the transfer path for transferring the time code of the predetermined number of bits, and wherein at the time of transfer via the transfer paths, time code of the predetermined number of bits is written to the latch storage sections corresponding to the transfer paths before being read out and transferred, the determination circuit is configured to determine the presence or the absence of an error on any of the latch storage sections corresponding to the plurality of the transfer paths by comparing a result of writing the time code of the predetermined number of bits to the latch storage sections individually with an expected value of a result of transferring the time code of the predetermined number of bits via the plurality of the transfer paths before having the time code read out and transferred, wherein, at a time of transfer via the transfer paths, predetermined data of the time code is written to the latch storage section corresponding to each of the transfer paths at the same time as being transferred, the determination circuit determining the presence or the absence of an error on any of the transfer paths by comparing the expected value with the result of transferring the predetermined data of the time code via the transfer paths, and wherein, on a basis of a result of the determination, the data line selection circuit (121, 122) is configured to switch the transfer paths excluding the transfer path determined to be erroneous and the relief transfer path, for use as the transfer paths for transferring the time code of the predetermined number of bits. a plurality of transfer paths configured to transfer, bit by bit, a time code of a predetermined number of bits for use in converting into a digital signal a pixel signal reflecting intensity of light received by a pixel, each of the plurality of transfer paths including a latch storage section configured to store the time code correspondingly bit by bit, wherein the pixel comprises an analog digital converter, ADC,; a relief transfer path configured the same as the transfer paths; a determination circuit configured to determine a presence or an absence of an error on a transfer path of the plurality of transfer paths; and a data line selection circuit (121, 122) including a plurality of switches, each transfer path of the plurality of transfer paths being connected to a corresponding switch of the plurality of switches, wherein the plurality of switches are configured to switch connection of the transfer path of the plurality of transfer paths with the relief transfer path based on the determination of the presence or the absence of an error on the transfer path, performed by the determination circuit, wherein the connection is switched to use the relief transfer path as the transfer path for transferring the time code of the predetermined number of bits, and wherein at the time of transfer via the transfer paths, time code of the predetermined number of bits is written to the latch storage sections corresponding to the transfer paths before being read out and transferred, the determination circuit is configured to determine the presence or the absence of an error on any of the latch storage sections corresponding to the plurality of the transfer paths by comparing a result of writing the time code of the predetermined number of bits to the latch storage sections individually with an expected value of a result of transferring the time code of the predetermined number of bits via the plurality of the transfer paths before having the time code read out and transferred, wherein, at a time of transfer via the transfer paths, predetermined data of the time code is written to the latch storage section corresponding to each of the transfer paths at the same time as being transferred, the determination circuit determining the presence or the absence of an error on any of the transfer paths by comparing the expected value with the result of transferring the predetermined data of the time code via the transfer paths, and wherein, on a basis of a result of the determination, the data line selection circuit (121, 122) is configured to switch the transfer paths excluding the transfer path determined to be erroneous and the relief transfer path, for use as the transfer paths for transferring the time code of the predetermined number of bits.