A semiconductor device comprising a bus (21R, 21W, 24R, 24W, 71R, 71W, 76R, 76W, 79W); a master configured to issue access requests including a read request and a write request to a memory; a memory controller which is coupled to the master through said bus, and which is configured to access the memory in accordance with the access requests; a cache which is arranged between the memory controller and the master, and configured to, when the access request is a write request, cache this write request; a first access control unit (50,22R,77) configured to perform first access control by controlling output of the read request issued by the master to the memory controller and output of the write request cached in the cache to the memory controller; and a second access control unit (60, 22W) configured to perform second access control by controlling output of the write request issued by the master to the memory controller, wherein the second access control unit is configured to perform the second access control in accordance with a free situation of the cache, characterized in that: the bus includes a read request bus (21R, 24R, 71R, 76R) configured to transmit the read request and a write request bus (21W, 24W, 71W, 76W, 79W) configured to transmit the write request, the first access control unit (50, 22R, 77) includes a read sub-bus controller including a read request issue control unit configured to receive the read request from the master through the read request bus, a first write sub-bus controller including a first write request issue control unit configured to receive the write request from the cache through the write request bus between the cache and the memory controller, and a first central bus control system configured to perform the first access control using the read sub-bus controller and the first write sub-bus controller, and wherein the second access control unit (60, 22W) includes a second write sub-bus controller including a second write request issue control unit configured to receive the write request from the master throuqh the write request bus, and a second central bus control system configured to perform the second access control using the second write sub-bus controller. the bus includes a read request bus (21R, 24R, 71R, 76R) configured to transmit the read request and a write request bus (21W, 24W, 71W, 76W, 79W) configured to transmit the write request, the first access control unit (50, 22R, 77) includes a read sub-bus controller including a read request issue control unit configured to receive the read request from the master through the read request bus, a first write sub-bus controller including a first write request issue control unit configured to receive the write request from the cache through the write request bus between the cache and the memory controller, and a first central bus control system configured to perform the first access control using the read sub-bus controller and the first write sub-bus controller, and wherein the second access control unit (60, 22W) includes a second write sub-bus controller including a second write request issue control unit configured to receive the write request from the master throuqh the write request bus, and a second central bus control system configured to perform the second access control using the second write sub-bus controller.