A field effect transistor, FET, cell formed on a first substrate, said field effect transistor cell comprising: a plurality of individual field effect transistors integrated in said first substrate; a plurality of interconnect bumps configured for flip-chip connection of the field effect transistor cell to a second substrate, the plurality of interconnect bumps comprising at least one signal input bump, gate interconnect bumps (211, 311), a source interconnect bump (212, 312) and a drain interconnect bump (213, 313), each of the individual field effect transistors comprising as terminals a gate terminal, a source terminal and a drain terminal, said gate terminal being interconnected and routed to first and second gate interconnect bumps of the plurality of interconnect bumps, said source terminal being connected and routed to a source interconnect bump of the plurality of interconnect bumps, and said drain terminal being connected and routed to a drain interconnect bump of the plurality of interconnect bumps; a stability circuit (220, 300) in communication with the terminals of the plurality of individual field effect transistors and further in communication with the plurality of interconnect bumps, said stability circuit comprising a first resistor connected between the gate terminal of an individual field effect transistor of the plurality of individual field effect transistors and the source interconnect bump connected to the source terminal of said individual field effect transistor, a second resistor and a first capacitor in parallel with each other connected between the gate terminal of said individual field effect transistor and a node, a third resistor connected between that node and the first gate interconnect bump interconnected to the gate terminal of said individual field effect transistor, a fourth resistor connected between that node and the second gate interconnect bump interconnected to the gate terminal of said individual field effect transistor, and a second capacitor connected between the signal input bump and said node. a plurality of individual field effect transistors integrated in said first substrate; a plurality of interconnect bumps configured for flip-chip connection of the field effect transistor cell to a second substrate, the plurality of interconnect bumps comprising at least one signal input bump, gate interconnect bumps (211, 311), a source interconnect bump (212, 312) and a drain interconnect bump (213, 313), each of the individual field effect transistors comprising as terminals a gate terminal, a source terminal and a drain terminal, said gate terminal being interconnected and routed to first and second gate interconnect bumps of the plurality of interconnect bumps, said source terminal being connected and routed to a source interconnect bump of the plurality of interconnect bumps, and said drain terminal being connected and routed to a drain interconnect bump of the plurality of interconnect bumps; a stability circuit (220, 300) in communication with the terminals of the plurality of individual field effect transistors and further in communication with the plurality of interconnect bumps, said stability circuit comprising a first resistor connected between the gate terminal of an individual field effect transistor of the plurality of individual field effect transistors and the source interconnect bump connected to the source terminal of said individual field effect transistor, a second resistor and a first capacitor in parallel with each other connected between the gate terminal of said individual field effect transistor and a node, a third resistor connected between that node and the first gate interconnect bump interconnected to the gate terminal of said individual field effect transistor, a fourth resistor connected between that node and the second gate interconnect bump interconnected to the gate terminal of said individual field effect transistor, and a second capacitor connected between the signal input bump and said node.