A method of driving a solid-state imaging device comprising: a photoelectric conversion layer that is formed over a semiconductor substrate; a MOS transistor circuit that reads out a signal corresponding to holes generated in the photoelectric conversion layer and then collected, and that is formed in the semiconductor substrate, wherein the MOS transistor circuit includes: a charge accumulation portion that is electrically connected with the photoelectric conversion layer; a reset transistor that comprises a drain connected to the charge accumulation portion, a source connected to a reset power source (Vs), and a gate, and that resets a potential of the charge accumulation portion to a reset potential (Vs); and an output transistor that outputs a signal corresponding to the potential of the charge accumulation portion, the output transistor has a gate terminal connected to the charge accumulation portion, the reset transistor and the output transistor are n-channel MOS transistors; characterized in that the driving is carried out according to the following formula: GND < Vs < GND + ΔV 2 + Vdd / 5 where GND denotes a reference potential of all potentials, Vs denotes the reset potential, ΔV2 denotes a difference between a first potential of the charge accumulation portion in a case where the reset transistor is in its ON state and a second potential (Vfd) of the charge accumulation portion immediately after the reset transistor has turned from its ON state into its OFF state, said difference ΔV2 being based on the capacitance between the charge accumulation portion and the gate of the reset transistor, and Vdd is the power source voltage connected to a drain terminal of the output transistor. a photoelectric conversion layer that is formed over a semiconductor substrate; a MOS transistor circuit that reads out a signal corresponding to holes generated in the photoelectric conversion layer and then collected, and that is formed in the semiconductor substrate, wherein the MOS transistor circuit includes: a charge accumulation portion that is electrically connected with the photoelectric conversion layer; a reset transistor that comprises a drain connected to the charge accumulation portion, a source connected to a reset power source (Vs), and a gate, and that resets a potential of the charge accumulation portion to a reset potential (Vs); and an output transistor that outputs a signal corresponding to the potential of the charge accumulation portion, the output transistor has a gate terminal connected to the charge accumulation portion, a charge accumulation portion that is electrically connected with the photoelectric conversion layer; a reset transistor that comprises a drain connected to the charge accumulation portion, a source connected to a reset power source (Vs), and a gate, and that resets a potential of the charge accumulation portion to a reset potential (Vs); and an output transistor that outputs a signal corresponding to the potential of the charge accumulation portion, the output transistor has a gate terminal connected to the charge accumulation portion, the reset transistor and the output transistor are n-channel MOS transistors; characterized in that the driving is carried out according to the following formula: GND < Vs < GND + ΔV 2 + Vdd / 5 where GND denotes a reference potential of all potentials, Vs denotes the reset potential, ΔV2 denotes a difference between a first potential of the charge accumulation portion in a case where the reset transistor is in its ON state and a second potential (Vfd) of the charge accumulation portion immediately after the reset transistor has turned from its ON state into its OFF state, said difference ΔV2 being based on the capacitance between the charge accumulation portion and the gate of the reset transistor, and Vdd is the power source voltage connected to a drain terminal of the output transistor.