A method of fabricating a fin field-effect transistor device comprising the steps of: patterning a base in a silicon-on-insulator layer having a first side, a second side opposite the first side, and a top; forming a gate dielectric layer over the base; forming a gate that surrounds at least a portion of the base and is separated from the base by the gate dielectric layer; and forming a source region and a drain region on opposite sides of the gate; the step of forming the gate further comprising the steps of: depositing a metal layer adjacent to the gate dielectric layer, wherein the metal layer is doped with at least one band edge metal; forming offset spacers (412, 414) on each of the sides of the base adjacent to the metal layer; forming a first metal layer and a second metal layer on the opposite sides of the base by selectively removing, from the top of the base, a portion of the metal layer exposed by the offset spacers (412, 414), the first and second metal layers (408a, 408b) both being separate portions of the metal layer; depositing a third metal layer over the offset spacers (412, 414) and adjacent to a portion of the gate dielectric layer on the top of the base, wherein the third metal layer is doped with at least one band edge metal different from the at least one band edge metal of the first and second metal layers (408a, 408b), the different band edge metals of the third metal layer and the first and second metal layers (408a, 408b) providing a first threshold voltage (V t1) at the sides of the gate different from a second threshold voltage (V t2) at the top of the gate; and depositing a top electrode layer over the third metal layer, wherein when the fin field-effect transistor is a n-channel field-effect transistor the band edge metal includes any one or more elements from the column of the group IIA and the group IIIB of the Periodic Table, and when the fin field-effect transistor is a p-channel field-effect transistor, the band edge metal includes one or more of aluminum, rhodium, rhenium, platinum, tungsten, nickel, cobalt. patterning a base in a silicon-on-insulator layer having a first side, a second side opposite the first side, and a top; forming a gate dielectric layer over the base; forming a gate that surrounds at least a portion of the base and is separated from the base by the gate dielectric layer; and forming a source region and a drain region on opposite sides of the gate; the step of forming the gate further comprising the steps of: depositing a metal layer adjacent to the gate dielectric layer, wherein the metal layer is doped with at least one band edge metal; forming offset spacers (412, 414) on each of the sides of the base adjacent to the metal layer; forming a first metal layer and a second metal layer on the opposite sides of the base by selectively removing, from the top of the base, a portion of the metal layer exposed by the offset spacers (412, 414), the first and second metal layers (408a, 408b) both being separate portions of the metal layer; depositing a third metal layer over the offset spacers (412, 414) and adjacent to a portion of the gate dielectric layer on the top of the base, wherein the third metal layer is doped with at least one band edge metal different from the at least one band edge metal of the first and second metal layers (408a, 408b), the different band edge metals of the third metal layer and the first and second metal layers (408a, 408b) providing a first threshold voltage (V t1) at the sides of the gate different from a second threshold voltage (V t2) at the top of the gate; and depositing a top electrode layer over the third metal layer, depositing a metal layer adjacent to the gate dielectric layer, wherein the metal layer is doped with at least one band edge metal; forming offset spacers (412, 414) on each of the sides of the base adjacent to the metal layer; forming a first metal layer and a second metal layer on the opposite sides of the base by selectively removing, from the top of the base, a portion of the metal layer exposed by the offset spacers (412, 414), the first and second metal layers (408a, 408b) both being separate portions of the metal layer; depositing a third metal layer over the offset spacers (412, 414) and adjacent to a portion of the gate dielectric layer on the top of the base, wherein the third metal layer is doped with at least one band edge metal different from the at least one band edge metal of the first and second metal layers (408a, 408b), the different band edge metals of the third metal layer and the first and second metal layers (408a, 408b) providing a first threshold voltage (V t1) at the sides of the gate different from a second threshold voltage (V t2) at the top of the gate; and depositing a top electrode layer over the third metal layer, wherein when the fin field-effect transistor is a n-channel field-effect transistor the band edge metal includes any one or more elements from the column of the group IIA and the group IIIB of the Periodic Table, and when the fin field-effect transistor is a p-channel field-effect transistor, the band edge metal includes one or more of aluminum, rhodium, rhenium, platinum, tungsten, nickel, cobalt.