A factory reset apparatus, comprising a reset switch, a first power supply module, a flip-flop, and a processor, wherein the flip-flop comprises a data input pin, a clock pin, and a true flip-flop output pin; the reset switch is connected to the data input pin; the first power supply module is connected to the clock pin; the true flip-flop output pin is connected to a first general purpose input/output pin of the processor; the reset switch is configured to generate a low-level reset signal when being pressed before the first power supply module is powered on and the first power supply module is configured to generate an original signal with a rising edge, when being powered on, wherein the first power supply module is further connected to a power input pin and a ground pin of the flip-flop; the first power supply module is configured to supply, after being powered on, working power to the flip-flop; and the apparatus further comprises a delay circuit, wherein the first power supply module is connected to the clock pin by using the delay circuit; and the original signal that is output by the first power supply module when being powered on passes through the delay circuit and is output as an electrical signal, wherein the reset signal is input into the flip-flop from the data input pin; the flip-flop is configured to receive the electrical signal from the clock pin, wherein the rising edge of the electrical signal is used to trigger the flip-flop to latch a low-level state of the reset signal; the flip-flop is configured to output a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal; and the processor is configured to start a factory reset operation according to the low-level reset request signal input from the first general purpose input/output pin. the reset switch is connected to the data input pin; the first power supply module is connected to the clock pin; the true flip-flop output pin is connected to a first general purpose input/output pin of the processor; the reset switch is configured to generate a low-level reset signal when being pressed before the first power supply module is powered on and the first power supply module is configured to generate an original signal with a rising edge, when being powered on, wherein the first power supply module is further connected to a power input pin and a ground pin of the flip-flop; the first power supply module is configured to supply, after being powered on, working power to the flip-flop; and the apparatus further comprises a delay circuit, wherein the first power supply module is connected to the clock pin by using the delay circuit; and the original signal that is output by the first power supply module when being powered on passes through the delay circuit and is output as an electrical signal, wherein the reset signal is input into the flip-flop from the data input pin; the flip-flop is configured to receive the electrical signal from the clock pin, wherein the rising edge of the electrical signal is used to trigger the flip-flop to latch a low-level state of the reset signal; the flip-flop is configured to output a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal; and the processor is configured to start a factory reset operation according to the low-level reset request signal input from the first general purpose input/output pin.