A gate drive circuit for generating asymmetric drive voltages, the gate drive circuit comprising: a gate drive transformer comprising: a primary winding responsive to a pulse width modulated, PWM, input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage, the positive bias voltage being asymmetric to the negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal; a first charge pump electrically connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal, the first charge pump comprising a first capacitor and a first diode connected in series, wherein a first terminal of the first capacitor is connected to a first terminal of the secondary winding of the gate drive transformer, a second terminal of the capacitor is connected to a cathode of the first diode, and an anode of the first diode is connected to a second terminal of the secondary winding of the gate drive transformer; a first transistor and a second transistor electrically connected to the first charge pump to drive the level shifted PWM output signal, wherein a collector of the first transistor is connected to a base of the first transistor using a first resistor, is connected to a base of the second transistor using a second resistor, and is connected to the cathode of the first diode and the second terminal of the first capacitor, and wherein a collector of the second transistor is connected to the anode of the first diode and to the second terminal of the secondary winding of the gate drive transformer; a second charge pump electrically connected to the first transistor and the second transistor to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal, the second charge pump comprising a second capacitor and a second diode connected in parallel, wherein a first terminal of the second capacitor is connected to a cathode of the second diode and a second terminal of the second capacitor is connected to an anode of the second diode; wherein an emitter of the first transistor and an emitter of the second transistor are connected to the first terminal of the second capacitor and the cathode of the second diode; and a gate switching device having a source, a drain, and a gate, wherein the gate of the gate switching device is electrically connected to the second charge pump, wherein the second terminal of the second capacitor and the anode of the second diode are connected to the gate of the gate switching device, wherein the readjusted PWM output signal establishes at least one of an ON condition and an OFF condition of the gate switching device. a primary winding responsive to a pulse width modulated, PWM, input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage, the positive bias voltage being asymmetric to the negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal; a first charge pump electrically connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal, the first charge pump comprising a first capacitor and a first diode connected in series, wherein a first terminal of the first capacitor is connected to a first terminal of the secondary winding of the gate drive transformer, a second terminal of the capacitor is connected to a cathode of the first diode, and an anode of the first diode is connected to a second terminal of the secondary winding of the gate drive transformer; a first transistor and a second transistor electrically connected to the first charge pump to drive the level shifted PWM output signal, wherein a collector of the first transistor is connected to a base of the first transistor using a first resistor, is connected to a base of the second transistor using a second resistor, and is connected to the cathode of the first diode and the second terminal of the first capacitor, and wherein a collector of the second transistor is connected to the anode of the first diode and to the second terminal of the secondary winding of the gate drive transformer; a second charge pump electrically connected to the first transistor and the second transistor to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal, the second charge pump comprising a second capacitor and a second diode connected in parallel, wherein a first terminal of the second capacitor is connected to a cathode of the second diode and a second terminal of the second capacitor is connected to an anode of the second diode; wherein an emitter of the first transistor and an emitter of the second transistor are connected to the first terminal of the second capacitor and the cathode of the second diode; and a gate switching device having a source, a drain, and a gate, wherein the gate of the gate switching device is electrically connected to the second charge pump, wherein the second terminal of the second capacitor and the anode of the second diode are connected to the gate of the gate switching device, wherein the readjusted PWM output signal establishes at least one of an ON condition and an OFF condition of the gate switching device.