Artificial neuron for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight, the artificial neuron including an integration circuit that comprises an accumulator of synaptic weights (C mem) at the terminals of which a membrane voltage (V mem) is established and a comparator (COMP) configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage, the artificial neuron being characterised in that it further includes: a read circuit which comprises a synaptic current accumulator (C load), the read circuit being configured to impose on the synapse a read voltage independent of the membrane voltage, to determine a piece of information on charging duration of the synaptic current accumulator (C load) and to provide an analogue value representative of the synaptic weight (PSa), said analogue value being said piece of information on charging duration; a logic circuit interposed between the read circuit and the integration circuit, the logic circuit being configured to generate from said analogue value a pulse (Cmd_exci, Cmd_inhi) having as duration the charging duration of the synaptic current accumulator (C load); and in that the integration circuit comprises a source of current (SI exc, SI inhi) controlled by said pulse to inject a current into the accumulator of synaptic weights during the duration of the pulse. the artificial neuron including an integration circuit that comprises an accumulator of synaptic weights (C mem) at the terminals of which a membrane voltage (V mem) is established and a comparator (COMP) configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage, the artificial neuron being characterised in that it further includes: a read circuit which comprises a synaptic current accumulator (C load), the read circuit being configured to impose on the synapse a read voltage independent of the membrane voltage, to determine a piece of information on charging duration of the synaptic current accumulator (C load) and to provide an analogue value representative of the synaptic weight (PSa), said analogue value being said piece of information on charging duration; a logic circuit interposed between the read circuit and the integration circuit, the logic circuit being configured to generate from said analogue value a pulse (Cmd_exci, Cmd_inhi) having as duration the charging duration of the synaptic current accumulator (C load); and a read circuit which comprises a synaptic current accumulator (C load), the read circuit being configured to impose on the synapse a read voltage independent of the membrane voltage, to determine a piece of information on charging duration of the synaptic current accumulator (C load) and to provide an analogue value representative of the synaptic weight (PSa), said analogue value being said piece of information on charging duration; a logic circuit interposed between the read circuit and the integration circuit, the logic circuit being configured to generate from said analogue value a pulse (Cmd_exci, Cmd_inhi) having as duration the charging duration of the synaptic current accumulator (C load); and in that the integration circuit comprises a source of current (SI exc, SI inhi) controlled by said pulse to inject a current into the accumulator of synaptic weights during the duration of the pulse.