An apparatus (100, 300) comprising: a cache including cache lines that are partitioned into a first subset of the cache lines and a second subset of the cache lines configured to operate according to two or more different cache replacement policies; at least one first counter associated with the first subset of cache lines; at least one second counter associated with the second subset of the cache lines; and a processor configured to: modify the at least one first or second counter in response to at least one of a cache hit or a cache miss associated with the first or second subsets characterised by: in response to a cache hit to the first or second subsets, incrementing the at least one first or second counter by an amount that is determined based on a degree of speculation of the memory access request that generated the cache hit to the first or second subsets, and in response to a cache miss to the first or second subsets, decrementing the at least one first or second counter by an amount that is determined based on a degree of speculation of the memory access request that generated the cache miss to the first or second subsets, and select a cache replacement policy from the two or more different cache replacement policies based on a comparison of the at least one first counter to the at least one second counter. a cache including cache lines that are partitioned into a first subset of the cache lines and a second subset of the cache lines configured to operate according to two or more different cache replacement policies; at least one first counter associated with the first subset of cache lines; at least one second counter associated with the second subset of the cache lines; and a processor configured to: modify the at least one first or second counter in response to at least one of a cache hit or a cache miss associated with the first or second subsets characterised by: in response to a cache hit to the first or second subsets, incrementing the at least one first or second counter by an amount that is determined based on a degree of speculation of the memory access request that generated the cache hit to the first or second subsets, and in response to a cache miss to the first or second subsets, decrementing the at least one first or second counter by an amount that is determined based on a degree of speculation of the memory access request that generated the cache miss to the first or second subsets, and select a cache replacement policy from the two or more different cache replacement policies based on a comparison of the at least one first counter to the at least one second counter. in response to a cache hit to the first or second subsets, incrementing the at least one first or second counter by an amount that is determined based on a degree of speculation of the memory access request that generated the cache hit to the first or second subsets, and in response to a cache miss to the first or second subsets, decrementing the at least one first or second counter by an amount that is determined based on a degree of speculation of the memory access request that generated the cache miss to the first or second subsets, and select a cache replacement policy from the two or more different cache replacement policies based on a comparison of the at least one first counter to the at least one second counter.