A polar transmitter, comprising: an amplitude path comprising an amplitude IQ-signal, which corresponds to the amplitude of a vector sum of an in-phase input signal (I, 102) and a quadrature-phase input signal (Q, 104); a phase path comprising a phase modulator configured to phase-modulate a phase IQ-signal, which corresponds to the phase of the vector sum of an in-phase input signal (I, 102) and a quadrature-phase input signal (Q, 104); a digital power amplifier, DPA, configured to amplify the phase-modulated, PM, IQ-signal based on the IQ-signal of the amplitude path; a tunable matching network coupled to an output of the DPA and configured to adjust a load impedance of the DPA; and a controller configured to adjust the matching network based on retrieving amplitude information and frequency information in a look-up table, the amplitude information being derived from the amplitude IQ-signal and the frequency information being derived from the PM IQ-signal, wherein the look-up table indicates a plurality of optimal operation modes of the matching network for specific combinations of amplitude and frequency information; wherein the controller is configured to update the lookup-table during a training operation, based on a relation of training signals applied to the DPA and an output signal at an output of the matching network; wherein the controller is configured to update the lookup-table based on an optimization criterion with respect to at least one of a saturated power efficiency and a back-off power efficiency of the polar transmitter depending on the training signals and the output signal; wherein the matching network comprises a plurality of switched capacitors which are switchable by the controller; wherein the matching network comprises a transformer, a first subset of the plurality of switched capacitors is tapped and embedded on a secondary winding of the transformer acting as a loading of the transformer: wherein a second subset of the plurality of switched capacitors is located at primary winding ports of the transformer; and wherein a third subset of the plurality of switched capacitors is located at secondary winding ports of the transformer. an amplitude path comprising an amplitude IQ-signal, which corresponds to the amplitude of a vector sum of an in-phase input signal (I, 102) and a quadrature-phase input signal (Q, 104); a phase path comprising a phase modulator configured to phase-modulate a phase IQ-signal, which corresponds to the phase of the vector sum of an in-phase input signal (I, 102) and a quadrature-phase input signal (Q, 104); a digital power amplifier, DPA, configured to amplify the phase-modulated, PM, IQ-signal based on the IQ-signal of the amplitude path; a tunable matching network coupled to an output of the DPA and configured to adjust a load impedance of the DPA; and a controller configured to adjust the matching network based on retrieving amplitude information and frequency information in a look-up table, the amplitude information being derived from the amplitude IQ-signal and the frequency information being derived from the PM IQ-signal, wherein the look-up table indicates a plurality of optimal operation modes of the matching network for specific combinations of amplitude and frequency information; wherein the controller is configured to update the lookup-table during a training operation, based on a relation of training signals applied to the DPA and an output signal at an output of the matching network; wherein the controller is configured to update the lookup-table based on an optimization criterion with respect to at least one of a saturated power efficiency and a back-off power efficiency of the polar transmitter depending on the training signals and the output signal; wherein the matching network comprises a plurality of switched capacitors which are switchable by the controller; wherein the matching network comprises a transformer, a first subset of the plurality of switched capacitors is tapped and embedded on a secondary winding of the transformer acting as a loading of the transformer: wherein a second subset of the plurality of switched capacitors is located at primary winding ports of the transformer; and wherein a third subset of the plurality of switched capacitors is located at secondary winding ports of the transformer.