A system with clock signal phase adjustment, the system comprising: a first data converter configured to receive a first clock signal and to provide a first feedback signal, wherein the first feedback signal comprises information indicative of a phase of a signal at a sampling node within the first data converter, and wherein the phase of the signal at the sampling node within the first data converter is based on the first clock signal; a second data converter configured to receive a second clock signal and to provide a second feedback signal, wherein the second feedback signal comprises information indicative of a phase of a signal at a sampling node within the second data converter, wherein the phase of the signal at the sampling node within the second data converter is based on the second clock signal; and a clock generator configured to provide the first clock signal and the second clock signal and receive the second feedback signal from the second data converter, the clock generator comprising: a feedback signal processor configured to receive the first feedback signal from the first data converter and to compute a phase control signal based on the first feedback signal and the information comprised in the second feedback signal, wherein the phase control signal is indicative of a phase adjustment of the first clock signal to synchronize the phase of the signal at the sampling node within the first data converter relative to the phase of the signal within the sampling node of the second data converter; and a clock generating circuit configured to adjust the phase of the first clock signal relative to the phase of the second clock signal based on the phase control signal. a first data converter configured to receive a first clock signal and to provide a first feedback signal, wherein the first feedback signal comprises information indicative of a phase of a signal at a sampling node within the first data converter, and wherein the phase of the signal at the sampling node within the first data converter is based on the first clock signal; a second data converter configured to receive a second clock signal and to provide a second feedback signal, wherein the second feedback signal comprises information indicative of a phase of a signal at a sampling node within the second data converter, wherein the phase of the signal at the sampling node within the second data converter is based on the second clock signal; and a clock generator configured to provide the first clock signal and the second clock signal and receive the second feedback signal from the second data converter, the clock generator comprising: a feedback signal processor configured to receive the first feedback signal from the first data converter and to compute a phase control signal based on the first feedback signal and the information comprised in the second feedback signal, wherein the phase control signal is indicative of a phase adjustment of the first clock signal to synchronize the phase of the signal at the sampling node within the first data converter relative to the phase of the signal within the sampling node of the second data converter; and a clock generating circuit configured to adjust the phase of the first clock signal relative to the phase of the second clock signal based on the phase control signal. a feedback signal processor configured to receive the first feedback signal from the first data converter and to compute a phase control signal based on the first feedback signal and the information comprised in the second feedback signal, wherein the phase control signal is indicative of a phase adjustment of the first clock signal to synchronize the phase of the signal at the sampling node within the first data converter relative to the phase of the signal within the sampling node of the second data converter; and a clock generating circuit configured to adjust the phase of the first clock signal relative to the phase of the second clock signal based on the phase control signal.