Electrical converter for converting a three-phase AC input into a DC output, comprising: three phase input terminals (a, b, c) and two output terminals (p, n), a three phase bridge rectifier having an input connected to the phase input terminals and an output connected to an upper intermediate node ( x) and a lower intermediate node ( y), the three phase rectifier comprising first semiconductor switches ( S xa, S xb, S xc, S ay, S by, S cy), a boost circuit comprising boost inductors ( L a, L b, L c), at least one second semiconductor switch ( S x m, S m y, S xy) that is actively switchable and at least one third semiconductor switch ( D x p, D n y, S p x, S y n), wherein the at least one second semiconductor switch and the at least one third semiconductor switch are connected in series across the output terminals (p, n), an output filter comprising a filter capacitor ( C pm, C mn, C pn) connected between the boost circuit and the output terminals, and a controller operably connected to the at least one second semiconductor switch, wherein the boost inductors ( L a, L b, L c) are connected between the phase terminals and the three phase bridge rectifier, wherein the at least one second semiconductor switch ( S x m, S m y, S xy) is connected across the upper intermediate node ( x) and the lower intermediate node ( y), and wherein the controller is configured to control the at least one second semiconductor switch via pulse width modulation allowing for obtaining a pulsed intermediate voltage between the upper intermediate node and the lower intermediate node having a modulated pulse width, characterised in that: the first semiconductor switches ( S xa, S xb, S xc, S ay, S by, S cy) are actively switchable, the controller is operably connected to the first semiconductor switches to control switching of the first semiconductor switches according to a switching pattern wherein the phase input terminal having an intermediate voltage between a highest voltage and a lowest voltage is alternatingly connected to the upper intermediate output node ( x) and the lower intermediate output node ( y). three phase input terminals (a, b, c) and two output terminals (p, n), a three phase bridge rectifier having an input connected to the phase input terminals and an output connected to an upper intermediate node ( x) and a lower intermediate node ( y), the three phase rectifier comprising first semiconductor switches ( S xa, S xb, S xc, S ay, S by, S cy), a boost circuit comprising boost inductors ( L a, L b, L c), at least one second semiconductor switch ( S x m, S m y, S xy) that is actively switchable and at least one third semiconductor switch ( D x p, D n y, S p x, S y n), wherein the at least one second semiconductor switch and the at least one third semiconductor switch are connected in series across the output terminals (p, n), an output filter comprising a filter capacitor ( C pm, C mn, C pn) connected between the boost circuit and the output terminals, and a controller operably connected to the at least one second semiconductor switch, wherein the boost inductors ( L a, L b, L c) are connected between the phase terminals and the three phase bridge rectifier, wherein the at least one second semiconductor switch ( S x m, S m y, S xy) is connected across the upper intermediate node ( x) and the lower intermediate node ( y), and wherein the controller is configured to control the at least one second semiconductor switch via pulse width modulation allowing for obtaining a pulsed intermediate voltage between the upper intermediate node and the lower intermediate node having a modulated pulse width, the first semiconductor switches ( S xa, S xb, S xc, S ay, S by, S cy) are actively switchable, the controller is operably connected to the first semiconductor switches to control switching of the first semiconductor switches according to a switching pattern wherein the phase input terminal having an intermediate voltage between a highest voltage and a lowest voltage is alternatingly connected to the upper intermediate output node ( x) and the lower intermediate output node ( y).