A ramp signal generating circuit comprising: a first shift register, a second shift register possessing a bidirectional scanning function, a voltage decreasing unit and a sampling unit; the voltage decreasing unit is connected to a power supply input terminal (Vref) and a ground terminal; the first shift register is connected to the voltage decreasing unit and is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage; the sampling unit has an output terminal (V O) and is connected to the voltage decreasing unit; the second shift register is connected to the sampling unit and is configured to control, through bidirectional scanning, the sampling unit to sample and output the voltages which are decreased continuously stage by stage by the voltage decreasing unit; characterized in that the voltage decreasing unit comprises a plurality of voltage decreasing resistors (R1, R2,..., Rn) connected in series to form a resistor string and is configured to continuously decrease a voltage inputted from the power supply input terminal (Vref) stage by stage along a flowing direction of current in the resistor string; wherein the voltage decreasing unit further comprises: a plurality of first transistors (M1, M2,..., Mn) arranged in a matrix; gates of the first transistors (M1, M2,..., Mn) located in a same row are connected to an output terminal of the first shift register; first electrodes of the first transistors (M1, M2,..., Mn) located in a same column are connected to an input terminal of the sampling unit; second electrodes of the first transistors (M1, M2,..., Mn) located in a same row are connected in series through voltage decreasing resistors (R1, R2,..., Rn), the second electrode of the first transistor (Mn) located at an i th row and a last column is connected to the second electrode of the first transistor (Mn) located at an (i+1) th row and the last column through a voltage decreasing resistor (Rn), the second electrode of the first transistor located at the (i+1) th row and a first column is connected to the second electrode of the first transistor located at an (i+2) th row and the first column through a voltage decreasing resistor, wherein i is an odd number or an even number. a first shift register, a second shift register possessing a bidirectional scanning function, a voltage decreasing unit and a sampling unit; the voltage decreasing unit is connected to a power supply input terminal (Vref) and a ground terminal; the first shift register is connected to the voltage decreasing unit and is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage; the sampling unit has an output terminal (V O) and is connected to the voltage decreasing unit; the second shift register is connected to the sampling unit and is configured to control, through bidirectional scanning, the sampling unit to sample and output the voltages which are decreased continuously stage by stage by the voltage decreasing unit; characterized in that the voltage decreasing unit comprises a plurality of voltage decreasing resistors (R1, R2,..., Rn) connected in series to form a resistor string and is configured to continuously decrease a voltage inputted from the power supply input terminal (Vref) stage by stage along a flowing direction of current in the resistor string; wherein the voltage decreasing unit further comprises: a plurality of first transistors (M1, M2,..., Mn) arranged in a matrix; gates of the first transistors (M1, M2,..., Mn) located in a same row are connected to an output terminal of the first shift register; first electrodes of the first transistors (M1, M2,..., Mn) located in a same column are connected to an input terminal of the sampling unit; second electrodes of the first transistors (M1, M2,..., Mn) located in a same row are connected in series through voltage decreasing resistors (R1, R2,..., Rn), the second electrode of the first transistor (Mn) located at an i th row and a last column is connected to the second electrode of the first transistor (Mn) located at an (i+1) th row and the last column through a voltage decreasing resistor (Rn), the second electrode of the first transistor located at the (i+1) th row and a first column is connected to the second electrode of the first transistor located at an (i+2) th row and the first column through a voltage decreasing resistor, wherein i is an odd number or an even number.