A three-dimensional memory device comprising: a lower-interconnect-level dielectric material layer located over a substrate and embedding lower-interconnect-level metal interconnect structures; a horizontal layer overlying the lower-interconnect-level dielectric material layer; an alternating stack of insulating layers (132, 232) and electrically conductive layers (146, 246) located over the horizontal layer; an array of memory stack structures (50, 60) extending through the alternating stack; laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer, wherein each of the laterally-insulated conductive via structures comprises a respective first conductive core that is electrically shorted to a respective one of the lower-interconnect-level metal interconnect structures, and a respective first cylindrical dielectric spacer that laterally surrounds the respective first conductive core; and laterally-insulated support structures that vertically extend through a subset of layers in the alternating stack, wherein each of the laterally-insulated support structures comprises a respective second conductive core having a same composition as the first conductive core, and a respective second cylindrical dielectric spacer that laterally surrounds the respective second conductive core, and wherein an entirety of a top planar surface of each second conductive core contacts a respective bottom surface of an overlying upper-interconnect-level dielectric material layer; wherein: the alternating stack includes a staircase region in which each electrically conductive layer (146, 246) except a topmost electrically conductive layer laterally extends farther than any overlying electrically conductive layer to provide multiple sets of stepped surfaces, wherein each set of stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack; a retro-stepped dielectric material portion overlies the multiple sets of stepped surfaces; and the laterally-insulated support structures vertically extend through a respective portion of the multiple sets of stepped surfaces and the retro-stepped dielectric material portion. a lower-interconnect-level dielectric material layer located over a substrate and embedding lower-interconnect-level metal interconnect structures; a horizontal layer overlying the lower-interconnect-level dielectric material layer; an alternating stack of insulating layers (132, 232) and electrically conductive layers (146, 246) located over the horizontal layer; an array of memory stack structures (50, 60) extending through the alternating stack; laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer, wherein each of the laterally-insulated conductive via structures comprises a respective first conductive core that is electrically shorted to a respective one of the lower-interconnect-level metal interconnect structures, and a respective first cylindrical dielectric spacer that laterally surrounds the respective first conductive core; and laterally-insulated support structures that vertically extend through a subset of layers in the alternating stack, wherein each of the laterally-insulated support structures comprises a respective second conductive core having a same composition as the first conductive core, and a respective second cylindrical dielectric spacer that laterally surrounds the respective second conductive core, and wherein an entirety of a top planar surface of each second conductive core contacts a respective bottom surface of an overlying upper-interconnect-level dielectric material layer; wherein: the alternating stack includes a staircase region in which each electrically conductive layer (146, 246) except a topmost electrically conductive layer laterally extends farther than any overlying electrically conductive layer to provide multiple sets of stepped surfaces, wherein each set of stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack; a retro-stepped dielectric material portion overlies the multiple sets of stepped surfaces; and the laterally-insulated support structures vertically extend through a respective portion of the multiple sets of stepped surfaces and the retro-stepped dielectric material portion. the alternating stack includes a staircase region in which each electrically conductive layer (146, 246) except a topmost electrically conductive layer laterally extends farther than any overlying electrically conductive layer to provide multiple sets of stepped surfaces, wherein each set of stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack; a retro-stepped dielectric material portion overlies the multiple sets of stepped surfaces; and the laterally-insulated support structures vertically extend through a respective portion of the multiple sets of stepped surfaces and the retro-stepped dielectric material portion.