Logic circuit for replacing a positively guided safety relay featuring a signal circuit contact, brake contact with an opening inlet (In-A) and opening outlet (Out_A) and a make contact with a closing inlet (In_B) and closing outlet (Out_B) with the logic circuit being equipped on two channels with a first logical channel and a second logical channel, comprises: a) for each logical canal (K1, K2) a first inlet (Set1, Set2) imitating a closing resp. opening of the signal circuit contact in response to a stress change and adapting accordingly a value from LOW to HIGH resp. HIGH to LOW; b) for each logical canal (K1, K2) a first outlet (Ou01, Ou02) being set to LOW in response to a stress change at the first inlet (Set1, Set2) and setting to LOW a second inlet (COu01, COu02) at the respectively other logical canal (K1, K2), whereat the setting to LOW of the second inlet (COu01, COu02) is tested in the particular logical canal before a first test signal (Test01, Test02) is applied to the opening inlet (In_A); c) for each logical canal (K1, K2) a third inlet (In_01, In_02) imitating an opening of the brake contact in response to a stress change triggered by the first test signal (Test01, Test02) and triggering a further testing whether the first outlet (Ou01, Ou02) has been set to LOW in the particular logical canal (K1, K2), before a predetermined delay time is running by means of a delay logic; d) for each logical canal (K1, K2) a fourth inlet (InC1, InC2), linked to the closing inlet (In_B), imitating a closing of the make contact in response to a stress change, thereby setting a second outlet (OuC1, OuC2) to HIGH; and whereat e) two series connected transistors (T1, T2) do not put through a signal voltage (V+) to the opening outlet (Out_A) if at least on of the first outlets (Ou01, Ou02) is set to LOW; and whereat f) two further series connected transistors (T3, T4) put through the signal voltage (V+) to the closing outlet (Out_B) if both second outlets (OuC1, OuC2) are set to HIGH. a) for each logical canal (K1, K2) a first inlet (Set1, Set2) imitating a closing resp. opening of the signal circuit contact in response to a stress change and adapting accordingly a value from LOW to HIGH resp. HIGH to LOW; b) for each logical canal (K1, K2) a first outlet (Ou01, Ou02) being set to LOW in response to a stress change at the first inlet (Set1, Set2) and setting to LOW a second inlet (COu01, COu02) at the respectively other logical canal (K1, K2), whereat the setting to LOW of the second inlet (COu01, COu02) is tested in the particular logical canal before a first test signal (Test01, Test02) is applied to the opening inlet (In_A); c) for each logical canal (K1, K2) a third inlet (In_01, In_02) imitating an opening of the brake contact in response to a stress change triggered by the first test signal (Test01, Test02) and triggering a further testing whether the first outlet (Ou01, Ou02) has been set to LOW in the particular logical canal (K1, K2), before a predetermined delay time is running by means of a delay logic; d) for each logical canal (K1, K2) a fourth inlet (InC1, InC2), linked to the closing inlet (In_B), imitating a closing of the make contact in response to a stress change, thereby setting a second outlet (OuC1, OuC2) to HIGH; and whereat e) two series connected transistors (T1, T2) do not put through a signal voltage (V+) to the opening outlet (Out_A) if at least on of the first outlets (Ou01, Ou02) is set to LOW; and whereat f) two further series connected transistors (T3, T4) put through the signal voltage (V+) to the closing outlet (Out_B) if both second outlets (OuC1, OuC2) are set to HIGH.