A dual gated integrated device, comprising: a first vertical junction field-effect transistor, VJFET, wherein the first VJFET comprises: a first VJFET source; a pair of first upper gates (820, 821) disposed on each side of the first VJFET source; a first upper N channel disposed between the pair of first upper gates; a first N - drift region disposed adjacent to the first upper N channel; and a first pair of lower gates (870, 875) of the first VJFET in a lower N channel; a second VJFET, wherein the second VJFET comprises: a second VJFET source; a pair of second upper gates (822, 823) disposed on each side of the second VJFET source, wherein a second upper N channel is disposed between the pair of second upper gates; and a second pair of lower gates (878, 879) of the second VJFET in the lower N channel; a Schottky contact (880, 876, 877), wherein the Schottky contact couples the first pair of lower gates of the first VJFET to the second pair of lower gates of the second VJFET wherein the lower N channel separates at least one gate of the first VJFET from at least one gate of the second VJFET, wherein the Schottky contact forms a rectifying contact to the lower N channel, and forms ohmic, non-rectifying contacts to the first pair of lower gates (870, 875) of the first VJFET and the second pair of lower gates (878, 879) of the second VJFET; and a common source connected to the first VJFET source and the second VJFET source, and wherein the common source is insulated from the first upper gates (820, 821) of the first VJFET and the second upper gates (822, 823) of the second VJFET by an insulator (891, 892, 893, 894), and the common source is connected to the first and second pairs of lower gates. a first vertical junction field-effect transistor, VJFET, wherein the first VJFET comprises: a first VJFET source; a pair of first upper gates (820, 821) disposed on each side of the first VJFET source; a first upper N channel disposed between the pair of first upper gates; a first N - drift region disposed adjacent to the first upper N channel; and a first pair of lower gates (870, 875) of the first VJFET in a lower N channel; a first VJFET source; a pair of first upper gates (820, 821) disposed on each side of the first VJFET source; a first upper N channel disposed between the pair of first upper gates; a first N - drift region disposed adjacent to the first upper N channel; and a first pair of lower gates (870, 875) of the first VJFET in a lower N channel; a second VJFET, wherein the second VJFET comprises: a second VJFET source; a pair of second upper gates (822, 823) disposed on each side of the second VJFET source, wherein a second upper N channel is disposed between the pair of second upper gates; and a second pair of lower gates (878, 879) of the second VJFET in the lower N channel; a second VJFET source; a pair of second upper gates (822, 823) disposed on each side of the second VJFET source, wherein a second upper N channel is disposed between the pair of second upper gates; and a second pair of lower gates (878, 879) of the second VJFET in the lower N channel; a Schottky contact (880, 876, 877), wherein the Schottky contact couples the first pair of lower gates of the first VJFET to the second pair of lower gates of the second VJFET wherein the lower N channel separates at least one gate of the first VJFET from at least one gate of the second VJFET, wherein the Schottky contact forms a rectifying contact to the lower N channel, and forms ohmic, non-rectifying contacts to the first pair of lower gates (870, 875) of the first VJFET and the second pair of lower gates (878, 879) of the second VJFET; and a common source connected to the first VJFET source and the second VJFET source, and wherein the common source is insulated from the first upper gates (820, 821) of the first VJFET and the second upper gates (822, 823) of the second VJFET by an insulator (891, 892, 893, 894), and the common source is connected to the first and second pairs of lower gates.