A method of manufacturing a semiconductor device, comprising: forming an interlayer insulating film over a semiconductor substrate having a first area and a second area; forming at least two holes in the interlayer insulating film, the holes including a first hole in the first area and a second hole in the second area; forming a first metal layer covering an internal surface of each of the holes; forming a second metal layer into each of the holes covered with the first metal layer and over the interlayer insulating film; removing the second metal layer over the interlayer insulating film, wherein the first metal layer and the second metal layer in the first area are a part of a lower electrode of a capacitor; forming a dielectric insulating film on the first metal layer and the second metal layer and over the interlayer insulating film; patterning the dielectric insulating film to leave the dielectric insulating film in the first area and to remove the dielectric insulating film in the second area; forming a third metal layer (114,115,116) on the dielectric insulating film in the first area, and on the first metal layer, the second metal layer and the interlayer insulating film in the second area; patterning the third metal layer covering the dielectric insulating film in the first area to form an upper electrode of the capacitor, and to form a interconnection (P2,P3) on the first metal layer and the second metal layer in the second area; wherein forming of the dielectric insulating film comprises; forming a first insulating layer and forming a second insulating layer on the first insulating layer, and wherein patterning of the dielectric insulating film comprises: forming a resist pattern on the second insulating layer, patterning the second insulating layer using the resist pattern as mask, peeling off the resist pattern, and forming a pattern on the first insulating layer using the second insulating layer as a mask, wherein the second insulating layer is removed during patterning of the first insulating layer and by a wet etching after the patterning of the first insulating layer, the wet etching being applied to a remaining part of the second insulating layer. forming an interlayer insulating film over a semiconductor substrate having a first area and a second area; forming at least two holes in the interlayer insulating film, the holes including a first hole in the first area and a second hole in the second area; forming a first metal layer covering an internal surface of each of the holes; forming a second metal layer into each of the holes covered with the first metal layer and over the interlayer insulating film; removing the second metal layer over the interlayer insulating film, wherein the first metal layer and the second metal layer in the first area are a part of a lower electrode of a capacitor; forming a dielectric insulating film on the first metal layer and the second metal layer and over the interlayer insulating film; patterning the dielectric insulating film to leave the dielectric insulating film in the first area and to remove the dielectric insulating film in the second area; forming a third metal layer (114,115,116) on the dielectric insulating film in the first area, and on the first metal layer, the second metal layer and the interlayer insulating film in the second area; patterning the third metal layer covering the dielectric insulating film in the first area to form an upper electrode of the capacitor, and to form a interconnection (P2,P3) on the first metal layer and the second metal layer in the second area; wherein forming of the dielectric insulating film comprises; forming a first insulating layer and forming a second insulating layer on the first insulating layer, and forming a first insulating layer and forming a second insulating layer on the first insulating layer, and wherein patterning of the dielectric insulating film comprises: forming a resist pattern on the second insulating layer, patterning the second insulating layer using the resist pattern as mask, peeling off the resist pattern, and forming a pattern on the first insulating layer using the second insulating layer as a mask, forming a resist pattern on the second insulating layer, patterning the second insulating layer using the resist pattern as mask, peeling off the resist pattern, and forming a pattern on the first insulating layer using the second insulating layer as a mask, wherein the second insulating layer is removed during patterning of the first insulating layer and by a wet etching after the patterning of the first insulating layer, the wet etching being applied to a remaining part of the second insulating layer.