An electrode-wiring substrate comprising: a plurality of gate electrode wires which are formed on an insulating substrate; a plurality of source electrode wires which intersect with the gate electrode wires, respectively; an insulating layer which electrically insulates the gate electrode wires from the source electrode wires; a plurality of switching elements which are formed near the intersections of the gate electrode wires and the source electrode wires, respectively; a display region which includes a plurality of pixel electrodes connected to the switching elements, respectively; a plurality of gate electrode terminals which are arranged at the periphery of the display region to input signals to the gate electrode wires, respectively; a plurality of source electrode terminals which are arranged at the periphery of the display region to input signals to the source electrode wires, respectively; a plurality of gate routing wires (108, 110) which are arranged at the periphery of the display region to connect the gate electrode wires to the gate electrode terminals, respectively; and a plurality of source routing wires which are arranged at the periphery of the display region to connect the source electrode wires to the source electrode terminals, respectively, wherein the gate routing wires (108, 110) and/or the source routing wires include first routing wires made of gate material for forming the gate electrode wires and second routing wires which are electrically insulated from the first routing wires by the insulating layer and made of source material for forming the source electrode wires, and the insulating layer includes at least a pair of a first connection hole (111, 122) and a second connection hole (113, 121) and the first connection hole (111, 122) electrically connects the first routing wire or the second routing wire to the gate electrode wire or the source electrode wire, while the second connection hole (113, 121) electrically connects the first routing wire or the second routing wire to the gate electrode terminal or the source electrode terminal, characterized in that the first routing wires and the second routing wires are alternately arranged so as not to coincide with each other when viewed in plan, and each of the plurality of gate electrode wires are connected to each of respective gate electrode terminals and/or each of the plurality of source electrode wires are connected to each of respective source electrode terminals, via the same number of multiple ones of the first connection hole (111, 122) and the second connection hole (113, 121). a plurality of gate electrode wires which are formed on an insulating substrate; a plurality of source electrode wires which intersect with the gate electrode wires, respectively; an insulating layer which electrically insulates the gate electrode wires from the source electrode wires; a plurality of switching elements which are formed near the intersections of the gate electrode wires and the source electrode wires, respectively; a display region which includes a plurality of pixel electrodes connected to the switching elements, respectively; a plurality of gate electrode terminals which are arranged at the periphery of the display region to input signals to the gate electrode wires, respectively; a plurality of source electrode terminals which are arranged at the periphery of the display region to input signals to the source electrode wires, respectively; a plurality of gate routing wires (108, 110) which are arranged at the periphery of the display region to connect the gate electrode wires to the gate electrode terminals, respectively; and a plurality of source routing wires which are arranged at the periphery of the display region to connect the source electrode wires to the source electrode terminals, respectively, wherein the gate routing wires (108, 110) and/or the source routing wires include first routing wires made of gate material for forming the gate electrode wires and second routing wires which are electrically insulated from the first routing wires by the insulating layer and made of source material for forming the source electrode wires, and the insulating layer includes at least a pair of a first connection hole (111, 122) and a second connection hole (113, 121) and the first connection hole (111, 122) electrically connects the first routing wire or the second routing wire to the gate electrode wire or the source electrode wire, while the second connection hole (113, 121) electrically connects the first routing wire or the second routing wire to the gate electrode terminal or the source electrode terminal, characterized in that the first routing wires and the second routing wires are alternately arranged so as not to coincide with each other when viewed in plan, and each of the plurality of gate electrode wires are connected to each of respective gate electrode terminals and/or each of the plurality of source electrode wires are connected to each of respective source electrode terminals, via the same number of multiple ones of the first connection hole (111, 122) and the second connection hole (113, 121).