A programmable integrated circuit device comprising: a plurality of specialized processing blocks, each of the plurality of specialized processing blocks comprising: a first floating-point arithmetic operator stage adapted to perform a floating-point multiplication; a second floating-point arithmetic operator stage adapted to perform a floating-point addition; at least three block inputs, wherein a first block input and a second block input of said block inputs are connected to said first floating-point arithmetic operator stage; a block output; a direct-connect input for receiving an input from an adjacent previous one of said plurality of specialized processing blocks; a direct-connect output for providing an output to an adjacent next one of said plurality of specialized processing blocks; and a configurable interconnect within the respective specialized processing block; characterized in that each of the plurality of specialized processing blocks is a specialized floating-point processing block, the configurable interconnect comprises: - a first multiplexer for selecting between a third block input of said block inputs and an output of said second floating-point arithmetic operator stage provided to the first multiplexer via a feedback path, as a first multiplexer output signal; - a second multiplexer for selecting, as a first input to said second floating-point arithmetic operator stage, between the first multiplexer output signal and said direct-connect input, - a third multiplexer for selecting, as a second input to said second floating-point arithmetic operator stage, between the first multiplexer output signal and the output of said first floating-point arithmetic operator stage and - a fourth multiplexer for selecting, as said direct-connect output, the other one of the first multiplexer output signal and said output of said first floating-point arithmetic operator stage, wherein said third multiplexer and said fourth multiplexer share opposite senses of a common control signal. a plurality of specialized processing blocks, each of the plurality of specialized processing blocks comprising: a first floating-point arithmetic operator stage adapted to perform a floating-point multiplication; a second floating-point arithmetic operator stage adapted to perform a floating-point addition; at least three block inputs, wherein a first block input and a second block input of said block inputs are connected to said first floating-point arithmetic operator stage; a block output; a direct-connect input for receiving an input from an adjacent previous one of said plurality of specialized processing blocks; a direct-connect output for providing an output to an adjacent next one of said plurality of specialized processing blocks; and a configurable interconnect within the respective specialized processing block; a first floating-point arithmetic operator stage adapted to perform a floating-point multiplication; a second floating-point arithmetic operator stage adapted to perform a floating-point addition; at least three block inputs, wherein a first block input and a second block input of said block inputs are connected to said first floating-point arithmetic operator stage; a block output; a direct-connect input for receiving an input from an adjacent previous one of said plurality of specialized processing blocks; a direct-connect output for providing an output to an adjacent next one of said plurality of specialized processing blocks; and a configurable interconnect within the respective specialized processing block; characterized in that each of the plurality of specialized processing blocks is a specialized floating-point processing block, the configurable interconnect comprises: - a first multiplexer for selecting between a third block input of said block inputs and an output of said second floating-point arithmetic operator stage provided to the first multiplexer via a feedback path, as a first multiplexer output signal; - a second multiplexer for selecting, as a first input to said second floating-point arithmetic operator stage, between the first multiplexer output signal and said direct-connect input, - a third multiplexer for selecting, as a second input to said second floating-point arithmetic operator stage, between the first multiplexer output signal and the output of said first floating-point arithmetic operator stage and - a fourth multiplexer for selecting, as said direct-connect output, the other one of the first multiplexer output signal and said output of said first floating-point arithmetic operator stage, wherein said third multiplexer and said fourth multiplexer share opposite senses of a common control signal. - a first multiplexer for selecting between a third block input of said block inputs and an output of said second floating-point arithmetic operator stage provided to the first multiplexer via a feedback path, as a first multiplexer output signal; - a second multiplexer for selecting, as a first input to said second floating-point arithmetic operator stage, between the first multiplexer output signal and said direct-connect input, - a third multiplexer for selecting, as a second input to said second floating-point arithmetic operator stage, between the first multiplexer output signal and the output of said first floating-point arithmetic operator stage and - a fourth multiplexer for selecting, as said direct-connect output, the other one of the first multiplexer output signal and said output of said first floating-point arithmetic operator stage,