A system, comprising: a processor core; a memory configured to store information for use by the processor core; a cache memory configured to fetch and store information from the memory; and a prefetch circuit configured to: issue a multi-group prefetch request to retrieve information from the memory to store in the cache memory using a predicted address, wherein the multi-group prefetch request includes a depth value indicative of a number of consecutively addressed fetch groups to retrieve and wherein the multi-group prefetch request is stored in a processing queue, wherein to issue the multi-group prefetch request, the prefetch circuit is further configured to issue a number of single-group prefetch requests, wherein the number of single-group prefetch requests corresponds to the depth value, wherein the depth value is an integer; generate an accuracy value based on a cache hit rate of prefetched information over a particular time interval; and modify the depth value based on the accuracy value, wherein to modify the depth value, the prefetch circuit is further configured to: increase the depth value in response to a determination that the accuracy value satisfies an upper threshold value, wherein to increase the depth value, the prefetch circuit is further configured to maintain a current depth value in response to a determination that the current depth value is equal to a maximum allowed depth value; and decrease the depth value in response to a determination that the accuracy value satisfies a lower threshold value. a processor core; a memory configured to store information for use by the processor core; a cache memory configured to fetch and store information from the memory; and a prefetch circuit configured to: issue a multi-group prefetch request to retrieve information from the memory to store in the cache memory using a predicted address, wherein the multi-group prefetch request includes a depth value indicative of a number of consecutively addressed fetch groups to retrieve and wherein the multi-group prefetch request is stored in a processing queue, wherein to issue the multi-group prefetch request, the prefetch circuit is further configured to issue a number of single-group prefetch requests, wherein the number of single-group prefetch requests corresponds to the depth value, wherein the depth value is an integer; generate an accuracy value based on a cache hit rate of prefetched information over a particular time interval; and modify the depth value based on the accuracy value, wherein to modify the depth value, the prefetch circuit is further configured to: increase the depth value in response to a determination that the accuracy value satisfies an upper threshold value, wherein to increase the depth value, the prefetch circuit is further configured to maintain a current depth value in response to a determination that the current depth value is equal to a maximum allowed depth value; and decrease the depth value in response to a determination that the accuracy value satisfies a lower threshold value. issue a multi-group prefetch request to retrieve information from the memory to store in the cache memory using a predicted address, wherein the multi-group prefetch request includes a depth value indicative of a number of consecutively addressed fetch groups to retrieve and wherein the multi-group prefetch request is stored in a processing queue, wherein to issue the multi-group prefetch request, the prefetch circuit is further configured to issue a number of single-group prefetch requests, wherein the number of single-group prefetch requests corresponds to the depth value, wherein the depth value is an integer; generate an accuracy value based on a cache hit rate of prefetched information over a particular time interval; and modify the depth value based on the accuracy value, wherein to modify the depth value, the prefetch circuit is further configured to: increase the depth value in response to a determination that the accuracy value satisfies an upper threshold value, wherein to increase the depth value, the prefetch circuit is further configured to maintain a current depth value in response to a determination that the current depth value is equal to a maximum allowed depth value; and decrease the depth value in response to a determination that the accuracy value satisfies a lower threshold value. increase the depth value in response to a determination that the accuracy value satisfies an upper threshold value, wherein to increase the depth value, the prefetch circuit is further configured to maintain a current depth value in response to a determination that the current depth value is equal to a maximum allowed depth value; and decrease the depth value in response to a determination that the accuracy value satisfies a lower threshold value.