An integrated circuit device comprising: control logic (141, 301) adapted to send a plurality of signals (211, 213, 215; 231, 233, 235; 303, 305) onto a signal tree having branches and leaves and being included on the integrated circuit device; user logic (101, 111) implementing a user design on the integrated circuit device; and fault detection circuitry (151, 201, 203, 205) on the integrated circuit device, wherein the fault detection circuitry (151, 201, 203, 205) comprises a plurality of logic gates (221, 223, 225; 261, 263, 265) adapted to monitor respective ones of a plurality of signal values at respective ones of a plurality of the leaves on the signal tree, and characterized in that wherein fault detection circuitry comprises a first daisy chain (221, 223, 225) of OR gates for outputting a first fault detect signal and a second daisy chain (261, 263, 265) of OR gates for outputting a second fault detect signal, wherein each branch of the signal tree comprises a first OR gate of the first daisy chain (221, 223, 225) and a second OR gate of the second first daisy chain (261, 263, 265), each of the two OR gates within each branch is for detecting a fault in a first signal value (211, 213, 215) and second signal value (231, 233, 235) of the plurality of signal values provided to the respective branch of the signal tree; the fault detection circuitry (151, 201, 203, 205) comprises masking subcircuitry (311, 313, 315), wherein the masking subcircuitry (311, 313, 315) is adapted to mask the first and/or second fault detect signal (207, 209) using respective AND gates (311, 313) of the masking subcircuitry (311, 313, 315), and to combine the outputs of AND gates (311, 313) using an OR gate of the masking subcircuitry (311, 313, 315) to output a device fault signal to the control logic (141, 301); and the control logic (141, 301) is adapted to implement a fault handling procedure upon receiving the device fault signal having a first value from the masking subcircuitry (311, 313, 315). control logic (141, 301) adapted to send a plurality of signals (211, 213, 215; 231, 233, 235; 303, 305) onto a signal tree having branches and leaves and being included on the integrated circuit device; user logic (101, 111) implementing a user design on the integrated circuit device; and fault detection circuitry (151, 201, 203, 205) on the integrated circuit device, wherein the fault detection circuitry (151, 201, 203, 205) comprises a plurality of logic gates (221, 223, 225; 261, 263, 265) adapted to monitor respective ones of a plurality of signal values at respective ones of a plurality of the leaves on the signal tree, and characterized in that wherein fault detection circuitry comprises a first daisy chain (221, 223, 225) of OR gates for outputting a first fault detect signal and a second daisy chain (261, 263, 265) of OR gates for outputting a second fault detect signal, wherein each branch of the signal tree comprises a first OR gate of the first daisy chain (221, 223, 225) and a second OR gate of the second first daisy chain (261, 263, 265), each of the two OR gates within each branch is for detecting a fault in a first signal value (211, 213, 215) and second signal value (231, 233, 235) of the plurality of signal values provided to the respective branch of the signal tree; the fault detection circuitry (151, 201, 203, 205) comprises masking subcircuitry (311, 313, 315), wherein the masking subcircuitry (311, 313, 315) is adapted to mask the first and/or second fault detect signal (207, 209) using respective AND gates (311, 313) of the masking subcircuitry (311, 313, 315), and to combine the outputs of AND gates (311, 313) using an OR gate of the masking subcircuitry (311, 313, 315) to output a device fault signal to the control logic (141, 301); and the control logic (141, 301) is adapted to implement a fault handling procedure upon receiving the device fault signal having a first value from the masking subcircuitry (311, 313, 315).