A receiver circuit supporting operation as an impulse radio ultra-wideband receiver having dynamic configuration comprising: a low noise amplifier, LNA, for amplifying received radio frequency signals from an antenna; a first amplifier for amplifying an output of the LNA; a squaring circuit electrically coupled to an output of the first amplifier for receiving amplified RF signals; a second amplifier electrically coupled to an output of the squaring circuit; an integration circuit electrically coupled to an output of the second amplifier; and characterised in that the receiver circuit further comprises: an N-bit flash analog-to-digital converter, ADC, electrically coupled to the integration circuit and generating N multiple output signals; wherein N is a positive integer and N≥2; and a power cycling controller for powering up and down the LNA, the first amplifier, the squaring circuit, the second amplifier, the integration circuit and the N-bit flash ADC within the receiver circuit in sequence to avoid voltage changes rippling through the receiver circuit and affecting the integration circuit; wherein a subset of components within the receiver circuit are decoupled by decoupling capacitors and biased independently through biasing resistors, each biasing resistor having a parallel transistor to accelerate recovery from power down by restoring the voltage differences at the decoupling capacitors; and the power cycling controller is configured to provide a control signal pulse to each parallel transistor to briefly open the parallel transistor in order to create a low impedance path to a voltage source for the biasing resistor associated with the parallel transistor in order to reduce settling time during powering up of a portion of the receiver circuit comprising a component of the subset of components associated with the biasing resistor and parallel transistor. a low noise amplifier, LNA, for amplifying received radio frequency signals from an antenna; a first amplifier for amplifying an output of the LNA; a squaring circuit electrically coupled to an output of the first amplifier for receiving amplified RF signals; a second amplifier electrically coupled to an output of the squaring circuit; an integration circuit electrically coupled to an output of the second amplifier; and characterised in that the receiver circuit further comprises: an N-bit flash analog-to-digital converter, ADC, electrically coupled to the integration circuit and generating N multiple output signals; wherein N is a positive integer and N≥2; and a power cycling controller for powering up and down the LNA, the first amplifier, the squaring circuit, the second amplifier, the integration circuit and the N-bit flash ADC within the receiver circuit in sequence to avoid voltage changes rippling through the receiver circuit and affecting the integration circuit; wherein a subset of components within the receiver circuit are decoupled by decoupling capacitors and biased independently through biasing resistors, each biasing resistor having a parallel transistor to accelerate recovery from power down by restoring the voltage differences at the decoupling capacitors; and the power cycling controller is configured to provide a control signal pulse to each parallel transistor to briefly open the parallel transistor in order to create a low impedance path to a voltage source for the biasing resistor associated with the parallel transistor in order to reduce settling time during powering up of a portion of the receiver circuit comprising a component of the subset of components associated with the biasing resistor and parallel transistor.