An operation method of a memory device, wherein the memory device includes a semiconductor substrate, a plurality of bit lines (B1, B2, B3) formed in the substrate, each bit line including a plurality of diffusion regions (204, 206) spaced apart from each other, and a plurality of word lines formed over the substrate, wherein the plurality of word lines and the plurality of bit lines (B1, B2, B3) define a plurality of memory cells, each memory cell having a trapping layer and corresponding to one word line and two consecutive ones of the plurality of diffusion regions (204, 206) of a bit line, wherein the memory cells are connected in series, and wherein each bit line has a first end and a second end, wherein the word line of each memory cell includes a control gate layer (218, 618), and each memory cell includes an n-type substrate, a channel region between the corresponding two consecutive diffusion regions (204, 206), the trapping layer (214, 614) above the channel region, a first insulating layer (212, 612) between the trapping layer (214, 614) and the channel region, and a second insulating layer (216, 616) between the trapping layer (214, 614) and the control gate (218, 618), the method comprising: selecting a memory cell, including applying a turn-on voltage to all of the plurality of word lines except the word line of the selected memory cell, and applying a ground bias to both the first end and the second end of all of the plurality of bit lines (B1, B2, B3) except the bit line of the selected memory cell; operating the selected memory cell; wherein the semiconductor substrate has an n-type conductivity, the plurality of diffusion regions (204, 206) has a p-type conductivity, and the turn-on voltage is a negative voltage, characterized in that operating the selected memory cell comprises resetting the selected memory cell, including applying a first negative bias to the word line of the selected memory cell, and applying the ground bias to both the first end and the second end of the bit line of the selected memory cell such that first and second electron tunneling processes are effected, wherein in the first tunneling process, electrons tunnel from the control gate (218, 618) of the selected memory cell, through the second insulating layer (216, 616) of the selected memory cell, into the trapping layer (214, 614) of the selected memory cell, and in the second tunneling process, electrons tunnel out of the trapping layer (214, 614) of the selected memory cell, through the first insulating layer (212, 612) of the selected memory cell, into the channel region of the selected memory cell, such that a threshold voltage of the selected memory cell is changed from a negative value to a positive value. selecting a memory cell, including applying a turn-on voltage to all of the plurality of word lines except the word line of the selected memory cell, and applying a ground bias to both the first end and the second end of all of the plurality of bit lines (B1, B2, B3) except the bit line of the selected memory cell; applying a turn-on voltage to all of the plurality of word lines except the word line of the selected memory cell, and applying a ground bias to both the first end and the second end of all of the plurality of bit lines (B1, B2, B3) except the bit line of the selected memory cell; operating the selected memory cell; wherein the semiconductor substrate has an n-type conductivity, the plurality of diffusion regions (204, 206) has a p-type conductivity, and the turn-on voltage is a negative voltage, characterized in that operating the selected memory cell comprises resetting the selected memory cell, including applying a first negative bias to the word line of the selected memory cell, and applying the ground bias to both the first end and the second end of the bit line of the selected memory cell such that first and second electron tunneling processes are effected, wherein in the first tunneling process, electrons tunnel from the control gate (218, 618) of the selected memory cell, through the second insulating layer (216, 616) of the selected memory cell, into the trapping layer (214, 614) of the selected memory cell, and in the second tunneling process, electrons tunnel out of the trapping layer (214, 614) of the selected memory cell, through the first insulating layer (212, 612) of the selected memory cell, into the channel region of the selected memory cell, such that a threshold voltage of the selected memory cell is changed from a negative value to a positive value.