A method of generating an output high frequency clock signal (770; 960) using a phase-locked loop, the method comprising: generating a reference clock signal (750; 920) in a first clock module; adjusting the reference clock signal (750; 920), in a first digital-to-time converter (780; 910), in accordance with a first control signal (820a; 930a) and generating a first input signal corresponding to the adjusted reference clock signal; receiving the first input signal at a first input of a time-to-digital converter (710; 940) and generating an output signal based on the first input signal and a second input signal received at a second input for the time-to-digital converter (710; 940); generating the output high frequency clock signal (770; 960) based on the first input signal; and generating a derived signal (760; 975) from the output high frequency clock signal (770; 960), in a feedback path of the phase-locked loop; characterised in that the method further comprises generating a second control signal (820b; 930b), each of the first and second control signals (820a, 820b; 930a, 930b) has a value being centred about a midpoint value M, and being adjusted by a fraction x, and, such that the value of one of the first and second control signals corresponds to M+x and the value of the other one of the first and second control signals corresponds to M-x; and the method further comprises receiving the second control signal by a second digital-to-time converter (830; 980) and using the second control signal (820b; 930b) to adjust the derived signal (760; 975) so that the adjusted reference clock signal and the adjusted derived signal are substantially aligned, and generate the second input signal for the time-to-digital converter (710; 940) corresponding to the adjusted derived signal (760, 975); wherein the derived signal comprises a phase selector output signal generated by a phase selector, wherein the phase selector is configured to receive a plurality of signals produced by a multi-phase divider dividing the high frequency clock signal and to provide the selector output signal as the derived signal. generating a reference clock signal (750; 920) in a first clock module; adjusting the reference clock signal (750; 920), in a first digital-to-time converter (780; 910), in accordance with a first control signal (820a; 930a) and generating a first input signal corresponding to the adjusted reference clock signal; receiving the first input signal at a first input of a time-to-digital converter (710; 940) and generating an output signal based on the first input signal and a second input signal received at a second input for the time-to-digital converter (710; 940); generating the output high frequency clock signal (770; 960) based on the first input signal; and generating a derived signal (760; 975) from the output high frequency clock signal (770; 960), in a feedback path of the phase-locked loop; characterised in that the method further comprises generating a second control signal (820b; 930b), each of the first and second control signals (820a, 820b; 930a, 930b) has a value being centred about a midpoint value M, and being adjusted by a fraction x, and, such that the value of one of the first and second control signals corresponds to M+x and the value of the other one of the first and second control signals corresponds to M-x; and the method further comprises receiving the second control signal by a second digital-to-time converter (830; 980) and using the second control signal (820b; 930b) to adjust the derived signal (760; 975) so that the adjusted reference clock signal and the adjusted derived signal are substantially aligned, and generate the second input signal for the time-to-digital converter (710; 940) corresponding to the adjusted derived signal (760, 975); wherein the derived signal comprises a phase selector output signal generated by a phase selector, wherein the phase selector is configured to receive a plurality of signals produced by a multi-phase divider dividing the high frequency clock signal and to provide the selector output signal as the derived signal.