A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate (9, 10), wherein the alternating stack is composed of, from bottom to top, a first contiguous subset of layers within the alternating stack and a second contiguous subset of layers within the alternating stack; a mesa structure located over the substrate; memory stack structures extending through the alternating stack in a memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; a first terrace region located above the mesa structure including first stepped surfaces of the first contiguous subset; a second terrace region including second stepped surfaces of the second contiguous subset; first contact via structures contacting respective electrically conductive layers within the first contiguous subset in the first terrace region; and second contact via structures contacting respective electrically conductive layers within the second contiguous subset in the second terrace region; wherein each electrically conductive layer except a topmost electrically conductive layer in the alternating stack includes a respective vertically extending portion within a combined region that includes a first contact region and a transition region located between the memory array region and the first contact region; each electrically conductive layer within the second contiguous subset includes a respective vertically extending portion having a planar topmost surface located within a same horizontal plane as a topmost surface of the alternating stack; an upper end of a vertically extending portion of each electrically conductive layer within the first contiguous subset is adjoined to an upper horizontal portion located above a horizontal plane including a top surface of the mesa structure; and a lower end of the vertically extending portion of each electrically conductive layer within the first contiguous subset is adjoined to a lower horizontal portion that continuously extends through the memory array region and into the second terrace region including the second stepped surfaces, characterised in that the first terrace region is located at a first side of the memory array region and the second terrace region is located at the second side of the memory array region. an alternating stack of insulating layers and electrically conductive layers located over a substrate (9, 10), wherein the alternating stack is composed of, from bottom to top, a first contiguous subset of layers within the alternating stack and a second contiguous subset of layers within the alternating stack; a mesa structure located over the substrate; memory stack structures extending through the alternating stack in a memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; a first terrace region located above the mesa structure including first stepped surfaces of the first contiguous subset; a second terrace region including second stepped surfaces of the second contiguous subset; first contact via structures contacting respective electrically conductive layers within the first contiguous subset in the first terrace region; and second contact via structures contacting respective electrically conductive layers within the second contiguous subset in the second terrace region; wherein each electrically conductive layer except a topmost electrically conductive layer in the alternating stack includes a respective vertically extending portion within a combined region that includes a first contact region and a transition region located between the memory array region and the first contact region; each electrically conductive layer within the second contiguous subset includes a respective vertically extending portion having a planar topmost surface located within a same horizontal plane as a topmost surface of the alternating stack; an upper end of a vertically extending portion of each electrically conductive layer within the first contiguous subset is adjoined to an upper horizontal portion located above a horizontal plane including a top surface of the mesa structure; and a lower end of the vertically extending portion of each electrically conductive layer within the first contiguous subset is adjoined to a lower horizontal portion that continuously extends through the memory array region and into the second terrace region including the second stepped surfaces, characterised in that the first terrace region is located at a first side of the memory array region and the second terrace region is located at the second side of the memory array region.