A memory cell disposed on a semiconductor substrate on which a peripheral circuit including a metal logic gate electrode containing a metallic material is provided, the memory cell comprising: a drain region disposed on a surface of the semiconductor substrate and connected with a bit line; a source region disposed on the surface of the semiconductor substrate and connected with a source line; a memory gate structure that is disposed between the drain region and the source region and in which a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode containing the metallic material are stacked in this order on the semiconductor substrate; a first select gate structure in which a metal first select gate electrode containing the metallic material is disposed on the semiconductor substrate between the drain region and the memory gate structure through a first select gate insulating film and that is disposed adjacent to a first sidewall of the memory gate structure through a first sidewall spacer; and a second select gate structure in which a metal second select gate electrode containing the metallic material is disposed on the semiconductor substrate between the source region and the memory gate structure through a second select gate insulating film and that is disposed adjacent to a second sidewall of the memory gate structure through a second sidewall spacer, wherein a first memory gate sidewall insulating film disposed along the first sidewall spacer and integrated with the upper memory gate insulating film is provided between the metal memory gate electrode and the first sidewall spacer, and a second memory gate sidewall insulating film disposed along the second sidewall spacer and integrated with the upper memory gate insulating film is provided between the metal memory gate electrode and the second sidewall spacer, and wherein the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode have planarized top surfaces, and a planarized top surface of the metal memory gate electrode, a planarized top surface of the metal first select gate electrode, and a planarized top surface of the metal second select gate electrode are flush with each other. a drain region disposed on a surface of the semiconductor substrate and connected with a bit line; a source region disposed on the surface of the semiconductor substrate and connected with a source line; a memory gate structure that is disposed between the drain region and the source region and in which a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode containing the metallic material are stacked in this order on the semiconductor substrate; a first select gate structure in which a metal first select gate electrode containing the metallic material is disposed on the semiconductor substrate between the drain region and the memory gate structure through a first select gate insulating film and that is disposed adjacent to a first sidewall of the memory gate structure through a first sidewall spacer; and a second select gate structure in which a metal second select gate electrode containing the metallic material is disposed on the semiconductor substrate between the source region and the memory gate structure through a second select gate insulating film and that is disposed adjacent to a second sidewall of the memory gate structure through a second sidewall spacer, wherein a first memory gate sidewall insulating film disposed along the first sidewall spacer and integrated with the upper memory gate insulating film is provided between the metal memory gate electrode and the first sidewall spacer, and a second memory gate sidewall insulating film disposed along the second sidewall spacer and integrated with the upper memory gate insulating film is provided between the metal memory gate electrode and the second sidewall spacer, and wherein the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode have planarized top surfaces, and a planarized top surface of the metal memory gate electrode, a planarized top surface of the metal first select gate electrode, and a planarized top surface of the metal second select gate electrode are flush with each other.