A method for fabricating an array substrate, comprising: providing a substrate; forming a first pattern on the substrate including a plurality of signal lines and a plurality of electrostatic discharge, ESD, lines so that each ESD line connects two signal lines; and removing a portion of each ESD line during a process of forming a second pattern over the first pattern to disconnect the two signal lines, wherein: each of the two signal lines is one of a gate line, a gate connection line, a common electrode line, a common electrode connection line, or each of the two signal lines is one of a data line, a data connection 2. line, a common electrode line, a common electrode connection line; and one end of each ESD line is connected to a first signal line of the two signal lines and the other end of each ESD line is connected to a second signal line of the two signal lines; characterized in that, two ESD lines connected to a same gate line are distributed at two ends of the gate line, one being connected to one end of the gate line, the other being connected to the other end of the gate line, and the two ESD lines are in a same layer as the gate line, or two ESD lines connected to a same data line are distributed at two ends of the data line, one being connected to one end of the data line, the other being connected to the other end of the data line, and the two ESD lines are in a same layer as the data line. providing a substrate; forming a first pattern on the substrate including a plurality of signal lines and a plurality of electrostatic discharge, ESD, lines so that each ESD line connects two signal lines; and removing a portion of each ESD line during a process of forming a second pattern over the first pattern to disconnect the two signal lines, wherein: each of the two signal lines is one of a gate line, a gate connection line, a common electrode line, a common electrode connection line, or each of the two signal lines is one of a data line, a data connection 2. line, a common electrode line, a common electrode connection line; and one end of each ESD line is connected to a first signal line of the two signal lines and the other end of each ESD line is connected to a second signal line of the two signal lines; characterized in that, two ESD lines connected to a same gate line are distributed at two ends of the gate line, one being connected to one end of the gate line, the other being connected to the other end of the gate line, and the two ESD lines are in a same layer as the gate line, or two ESD lines connected to a same data line are distributed at two ends of the data line, one being connected to one end of the data line, the other being connected to the other end of the data line, and the two ESD lines are in a same layer as the data line. each of the two signal lines is one of a gate line, a gate connection line, a common electrode line, a common electrode connection line, or each of the two signal lines is one of a data line, a data connection 2. line, a common electrode line, a common electrode connection line; and one end of each ESD line is connected to a first signal line of the two signal lines and the other end of each ESD line is connected to a second signal line of the two signal lines; characterized in that, two ESD lines connected to a same gate line are distributed at two ends of the gate line, one being connected to one end of the gate line, the other being connected to the other end of the gate line, and the two ESD lines are in a same layer as the gate line, or two ESD lines connected to a same data line are distributed at two ends of the data line, one being connected to one end of the data line, the other being connected to the other end of the data line, and the two ESD lines are in a same layer as the data line.