A microprocessor (102, 201a), comprising: a plurality of processing units (A1, A2, A3, A4); a plurality of caches arranged into a plurality of cache layers, the plurality of caches including a plurality of first caches (L1-A1, L1-A2, L1-A3, L1-A4) within a first cache layer and one or more second caches (L2-A1, L2-A2) within a second cache layer, a particular second cache in the second cache layer serving as a backing store for at least a particular first cache in the first cache layer; and control logic that configures at least the particular second cache to perform at least the following: receive, from the particular first cache, a logging request referencing a particular memory address; and based on the request, determine whether a cache line corresponding to the memory address is present in the particular second cache, and when the cache line is not present in the particular second cache, perform one of: cause the cache line to be logged when there does not exist a third cache that participates in logging and that serves as a backing store for at least the particular second cache, or forward the request to the third cache when the third cache does exist; or when the cache line is present in the particular second cache, perform at least one of: cause the cache line to be logged when the cache line is (i) not determined by the particular second cache to be logged, or (ii) determined by the particular second cache to be logged but the particular second cache has not determined that the first cache is aware of a current value stored in the cache line of the particular second cache; or determine that cache line need not be logged when (i) the cache line is determined by the particular second cache to be logged, and (ii) it is determined that the first cache is aware of the current value stored in the cache line of the particular second cache. a plurality of processing units (A1, A2, A3, A4); a plurality of caches arranged into a plurality of cache layers, the plurality of caches including a plurality of first caches (L1-A1, L1-A2, L1-A3, L1-A4) within a first cache layer and one or more second caches (L2-A1, L2-A2) within a second cache layer, a particular second cache in the second cache layer serving as a backing store for at least a particular first cache in the first cache layer; and control logic that configures at least the particular second cache to perform at least the following: receive, from the particular first cache, a logging request referencing a particular memory address; and based on the request, determine whether a cache line corresponding to the memory address is present in the particular second cache, and receive, from the particular first cache, a logging request referencing a particular memory address; and based on the request, determine whether a cache line corresponding to the memory address is present in the particular second cache, and when the cache line is not present in the particular second cache, perform one of: cause the cache line to be logged when there does not exist a third cache that participates in logging and that serves as a backing store for at least the particular second cache, or forward the request to the third cache when the third cache does exist; or cause the cache line to be logged when there does not exist a third cache that participates in logging and that serves as a backing store for at least the particular second cache, or forward the request to the third cache when the third cache does exist; or when the cache line is present in the particular second cache, perform at least one of: cause the cache line to be logged when the cache line is (i) not determined by the particular second cache to be logged, or (ii) determined by the particular second cache to be logged but the particular second cache has not determined that the first cache is aware of a current value stored in the cache line of the particular second cache; or determine that cache line need not be logged when (i) the cache line is determined by the particular second cache to be logged, and (ii) it is determined that the first cache is aware of the current value stored in the cache line of the particular second cache. cause the cache line to be logged when the cache line is (i) not determined by the particular second cache to be logged, or (ii) determined by the particular second cache to be logged but the particular second cache has not determined that the first cache is aware of a current value stored in the cache line of the particular second cache; or determine that cache line need not be logged when (i) the cache line is determined by the particular second cache to be logged, and (ii) it is determined that the first cache is aware of the current value stored in the cache line of the particular second cache.