A processor configured to perform operations comprising: determining that a control resource set, CORESET, is to be shared by at least a first transmission reception point, TRP, and a second TRP corresponding to a cell of a network; performing resource element group, REG, bundle to virtual REG bundle mapping on a per TRP basis, wherein multiple REG bundles are indexed on the per TRP basis; performing virtual REG bundle interleaving across the first TRP and the second TRP, wherein performing virtual REG bundle interleaving across the first TRP and the second TRP includes: determining a number of columns for a matrix based on, at least, a number of REG in the CORESET; determining a number of rows for the matrix based on, at least, a number of TRPs sharing the CORESET; determining whether an even CCE index or an odd CCE index is to be utilized; when the even CCE index is to be utilized, a first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the first TRP; when the odd CCE index is to be utilized, the first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the second TRP; and generating a second virtual REG bundle sequence based on, at least, the matrix, shifting REG bundles in different TRPs when constructing a CCE based on a shifting parameter, wherein the shifting parameter is a function of a TRP index; performing control channel element, CCE, to interleaved REG bundle mapping; and transmitting downlink control information, DCI, using the CORESET, wherein the CORESET is configured based on, at least, the CCE to interleaved REG bundle mapping. determining that a control resource set, CORESET, is to be shared by at least a first transmission reception point, TRP, and a second TRP corresponding to a cell of a network; performing resource element group, REG, bundle to virtual REG bundle mapping on a per TRP basis, wherein multiple REG bundles are indexed on the per TRP basis; performing virtual REG bundle interleaving across the first TRP and the second TRP, wherein performing virtual REG bundle interleaving across the first TRP and the second TRP includes: determining a number of columns for a matrix based on, at least, a number of REG in the CORESET; determining a number of rows for the matrix based on, at least, a number of TRPs sharing the CORESET; determining whether an even CCE index or an odd CCE index is to be utilized; when the even CCE index is to be utilized, a first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the first TRP; when the odd CCE index is to be utilized, the first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the second TRP; and generating a second virtual REG bundle sequence based on, at least, the matrix, shifting REG bundles in different TRPs when constructing a CCE based on a shifting parameter, wherein the shifting parameter is a function of a TRP index; performing control channel element, CCE, to interleaved REG bundle mapping; and transmitting downlink control information, DCI, using the CORESET, wherein the CORESET is configured based on, at least, the CCE to interleaved REG bundle mapping. determining a number of columns for a matrix based on, at least, a number of REG in the CORESET; determining a number of rows for the matrix based on, at least, a number of TRPs sharing the CORESET; determining whether an even CCE index or an odd CCE index is to be utilized; when the even CCE index is to be utilized, a first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the first TRP; when the odd CCE index is to be utilized, the first virtual REG bundle sequence is input into the matrix row by row in an increasing order of virtual REG bundle starting from the second TRP; and generating a second virtual REG bundle sequence based on, at least, the matrix, shifting REG bundles in different TRPs when constructing a CCE based on a shifting parameter, wherein the shifting parameter is a function of a TRP index; performing control channel element, CCE, to interleaved REG bundle mapping; and transmitting downlink control information, DCI, using the CORESET, wherein the CORESET is configured based on, at least, the CCE to interleaved REG bundle mapping.