A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process, comprising: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS / NMOS body control circuit; wherein, the PMOS / NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels, wherein the PMOS / NMOS body control circuit is configured to, through controlling voltages of body regions of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels, wherein the PMOS/NMOS body control circuit is configured as: when the input of the Schmitt trigger is low electrical level, se the voltage of the body region of the first NMOS transistor to 0, and set the voltage of the body region of the first PMOS transistor to V D 1; when the input of the Schmitt trigger is high electrical level, set the voltage of the body region of the first NMOS transistor to V D 2, and set the voltage of the body region of the first PMOS transistor to V DD; wherein, V DD represents the power supply voltage, V D 1 represents the low voltage outputted by the first output end of PMOS/NMOS body control circuit, said first output end is connected to the body region of the first PMOS transistor; V D 2 represents the high voltage outputted by the second output end of the PMOS/NMOS transistor body control circuit, said second output end is connected to the body region of the first NMOS transistor, characterized in that said PMOS/NMOS body control circuit comprises: a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first diode, a resistor and a second diode, wherein, the drain electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected to the body region of the first PMOS transistor; the drain electrode of the fourth NMOS and the source electrode of the third NMOS transistor are connected to the body region of the first NMOS transistor; the gate electrode of the third NMOS transistor is connected to the gate electrode and the gate electrode of the fourth PMOS transistor and the output end; the gate electrode of the fourth NMOS transistor is connected to the gate electrode of the third PMOS transistor; the source electrode of the fourth NMOS transistor is connected to the ground, the source electrode of the third PMOS transistor is connected to the power supply; the cathode of the first diode is connected to the power supply, the anode of the first diode is connected to one end of the resistor and the drain electrode of the fourth PMOS transistor; the anode of the second diode is connected to the ground, the cathode of the second diode is connected to the other end of the resistor and the drain electrode of the third NMOS transistor.