A manufacturing method for a trench field effect transistor structure, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate; forming a plurality of parallel first trenches arranged at intervals and a plurality of parallel second trenches arranged at intervals in the epitaxial layer, wherein the first trenches and the second trenches are arranged to intersect each other to define a plurality of implantation regions based on adjacent first trenches and second trenches; forming a first gate dielectric layer on an inner wall of the first trench, and forming a first gate structure on the first gate dielectric layer so that the first gate structure is filled in the first trench; and forming a second gate dielectric layer on an inner wall of the second trench, and forming a second gate structure on the second gate dielectric layer so that the second gate structure is filled in the second trench; performing ion implantation on the epitaxial layer to form a body region in each of the plurality of implantation regions, wherein the body region abuts both the first trenches and the second trenches defining the implantation region where the body region is formed; forming a source implantation mask on the epitaxial layer, wherein the source implantation mask comprises only a plurality of spaced implantation mask units, and each implantation mask unit covers a junction of the first trench and the second trench and extends to cover the implantation region around the junction, to form at least one shielded region on the body region; performing ion implantation on the epitaxial layer based on the source implantation mask to form a source in the body region, wherein the shielded region forms a body region lead-out region; and forming, on the epitaxial layer, a source electrode structure in contact with both an upper surface of the source and an upper surface of the body region lead-out region, to electrically lead out the source and the body region. providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate; forming a plurality of parallel first trenches arranged at intervals and a plurality of parallel second trenches arranged at intervals in the epitaxial layer, wherein the first trenches and the second trenches are arranged to intersect each other to define a plurality of implantation regions based on adjacent first trenches and second trenches; forming a first gate dielectric layer on an inner wall of the first trench, and forming a first gate structure on the first gate dielectric layer so that the first gate structure is filled in the first trench; and forming a second gate dielectric layer on an inner wall of the second trench, and forming a second gate structure on the second gate dielectric layer so that the second gate structure is filled in the second trench; performing ion implantation on the epitaxial layer to form a body region in each of the plurality of implantation regions, wherein the body region abuts both the first trenches and the second trenches defining the implantation region where the body region is formed; forming a source implantation mask on the epitaxial layer, wherein the source implantation mask comprises only a plurality of spaced implantation mask units, and each implantation mask unit covers a junction of the first trench and the second trench and extends to cover the implantation region around the junction, to form at least one shielded region on the body region; performing ion implantation on the epitaxial layer based on the source implantation mask to form a source in the body region, wherein the shielded region forms a body region lead-out region; and forming, on the epitaxial layer, a source electrode structure in contact with both an upper surface of the source and an upper surface of the body region lead-out region, to electrically lead out the source and the body region.