A computing device with a main board including a plurality of elements (211, 212, 213, 214), the computing device comprising: a clock generation unit including a plurality of clock generators configured to generate clocks of different frequencies to be used for control of operations of the plurality of elements (211, 212, 213, 214), wherein the plurality of clock generators are connected to a processor on the main board, and the processor controls the operations of the plurality of elements (211, 212, 213, 214) using the clocks generated by the plurality of clock generators, characterized in that: each of the clock generators is configured to generate clocks of various frequencies in a frequency range of 10 MHz to 500 MHz; the computing device further comprises a linear regulator unit including a plurality of linear regulators configured to convert a voltage from a power supply into different voltages required for the plurality of elements (211, 212, 213, 214) and apply the different voltages; and the plurality of linear regulators are connected in series to receive a voltage used in a preceding linear regulator and drop the received voltage, wherein a first linear regulator of the plurality of linear regulators receives a highest voltage from the power supply, stabilizes the highest voltage by removing noise from the highest voltage and supplies the stabilized voltage to an element CHIP N connected to the first linear regulator, and a second linear regulator connected to the first linear regulator drops an output voltage of the first linear regulator and supplies a stabilized voltage by removing noise from the dropped voltage to an element CHIP (N-1) connected to the second linear regulator. a clock generation unit including a plurality of clock generators configured to generate clocks of different frequencies to be used for control of operations of the plurality of elements (211, 212, 213, 214), wherein the plurality of clock generators are connected to a processor on the main board, and the processor controls the operations of the plurality of elements (211, 212, 213, 214) using the clocks generated by the plurality of clock generators, characterized in that: each of the clock generators is configured to generate clocks of various frequencies in a frequency range of 10 MHz to 500 MHz; the computing device further comprises a linear regulator unit including a plurality of linear regulators configured to convert a voltage from a power supply into different voltages required for the plurality of elements (211, 212, 213, 214) and apply the different voltages; and the plurality of linear regulators are connected in series to receive a voltage used in a preceding linear regulator and drop the received voltage, wherein a first linear regulator of the plurality of linear regulators receives a highest voltage from the power supply, stabilizes the highest voltage by removing noise from the highest voltage and supplies the stabilized voltage to an element CHIP N connected to the first linear regulator, and a second linear regulator connected to the first linear regulator drops an output voltage of the first linear regulator and supplies a stabilized voltage by removing noise from the dropped voltage to an element CHIP (N-1) connected to the second linear regulator. each of the clock generators is configured to generate clocks of various frequencies in a frequency range of 10 MHz to 500 MHz; the computing device further comprises a linear regulator unit including a plurality of linear regulators configured to convert a voltage from a power supply into different voltages required for the plurality of elements (211, 212, 213, 214) and apply the different voltages; and the plurality of linear regulators are connected in series to receive a voltage used in a preceding linear regulator and drop the received voltage, wherein a first linear regulator of the plurality of linear regulators receives a highest voltage from the power supply, stabilizes the highest voltage by removing noise from the highest voltage and supplies the stabilized voltage to an element CHIP N connected to the first linear regulator, and a second linear regulator connected to the first linear regulator drops an output voltage of the first linear regulator and supplies a stabilized voltage by removing noise from the dropped voltage to an element CHIP (N-1) connected to the second linear regulator.