A method of processing a convolution operation in a neural network in parallel by a processor, the processor comprising a convolution operator unit comprising a k-bit multiplier having full precision of k bits, wherein k is an even natural number greater or equal to 2, with decomposed sub-multipliers corresponding to k/2-bit multipliers in the convolution operator unit, the method comprising: determining, by the processor, m first-bit feature map operands and n second-bit weight operands based on pixel values (231, 232, 233) of input feature maps and weights of kernels, respectively, on which the convolution operation is to be performed in parallel and which are processable in parallel, wherein m and n are each an even natural number greater or equal to 2; dispatching, by the processor, m × n operand pairs of a feature map operand and a weight operand, in which the first-bit feature map operands and most significant bits of k/2 bits in the second-bit weight operands are mapped to each other, and operand pairs, in which the first-bit feature map operands and least significant bits of k/2 bits in the second-bit weight operands are mapped to each other respectively to the decomposed sub-multipliers corresponding to k/2-bit multipliers in the convolution operator unit, in response to the first-bit feature map operands being k/2-bit operands and the second-bit weight operands being k-bit operands and dispatching, by the processor, m × n operand pairs of the feature map operand and the weight operand, in which most significant bits of k/2 bits in the first-bit feature map operands and the second-bit weight operands are mapped to each other, and operand pairs, in which least significant bits of k/2 bits in the first-bit feature map operands and the second-bit weight operands are mapped to each other respectively to the decomposed sub-multipliers corresponding to k/2-bit multipliers in the convolution operator unit, in response to the first-bit feature map operands being k-bit operands and the second-bit weight operands being k/2-bit operands; performing the multiplication operations by the decomposed sub-multipliers of the convolution operator unit; generating, by the processor, m × n outputs by performing addition and accumulation operations on the results of multiplication operations performed by the decomposed sub-multipliers; and obtaining, by the processor, pixel values of output feature maps corresponding to results of the convolution operation based on the m × n outputs. determining, by the processor, m first-bit feature map operands and n second-bit weight operands based on pixel values (231, 232, 233) of input feature maps and weights of kernels, respectively, on which the convolution operation is to be performed in parallel and which are processable in parallel, wherein m and n are each an even natural number greater or equal to 2; dispatching, by the processor, m × n operand pairs of a feature map operand and a weight operand, in which the first-bit feature map operands and most significant bits of k/2 bits in the second-bit weight operands are mapped to each other, and operand pairs, in which the first-bit feature map operands and least significant bits of k/2 bits in the second-bit weight operands are mapped to each other respectively to the decomposed sub-multipliers corresponding to k/2-bit multipliers in the convolution operator unit, in response to the first-bit feature map operands being k/2-bit operands and the second-bit weight operands being k-bit operands and dispatching, by the processor, m × n operand pairs of the feature map operand and the weight operand, in which most significant bits of k/2 bits in the first-bit feature map operands and the second-bit weight operands are mapped to each other, and operand pairs, in which least significant bits of k/2 bits in the first-bit feature map operands and the second-bit weight operands are mapped to each other respectively to the decomposed sub-multipliers corresponding to k/2-bit multipliers in the convolution operator unit, in response to the first-bit feature map operands being k-bit operands and the second-bit weight operands being k/2-bit operands; performing the multiplication operations by the decomposed sub-multipliers of the convolution operator unit; generating, by the processor, m × n outputs by performing addition and accumulation operations on the results of multiplication operations performed by the decomposed sub-multipliers; and obtaining, by the processor, pixel values of output feature maps corresponding to results of the convolution operation based on the m × n outputs.