An electronic circuit (100,150,200), comprising: a circuit substrate; a differential amplifier disposed upon the circuit substrate, the differential amplifier comprising first and second transistors (106,108,124,126,156,158,178,180) coupled together in a differential arrangement, each transistor (106,108,124,126,156,158,178,180) having a respective control node comprising a base node or a gate node, and each transistor (106,108,124,126,156,158,178,180) having a respective current node comprising an emitter node or a source node through which a respective current flows; and an offset correction circuit disposed upon the circuit substrate, the offset correction circuit operable to adjust an offset voltage of the differential amplifier, the offset correction circuit comprising: a resistor network (102,104) having a plurality of resistors, the resistor network (102,104) coupled between the current nodes of the first and second transistors (106,108,124,126,156,158,178,180); a plurality of current generators (22,110,114,120,160,164,170) for simultaneously generating a respective plurality of currents, each current generator (22,110,114,120,160,164,170) having first and second respective nodes; a switching network having a plurality of switches (112,118,162,168), each switch (112,118,162,168) having a respective control node and respective first and second switched nodes, the first switched nodes coupled to the resistor network (102,104) and the second switched nodes coupled to the first nodes of the plurality of current generators (110,114,120,160,164,170); and a selection circuit (116,122,168,172) configured to generate a plurality of control signals, each control signal coupled to a respective control node of the switching network and operable to close one or more respective ones of the plurality of switches (112,118,162,168). a circuit substrate; a differential amplifier disposed upon the circuit substrate, the differential amplifier comprising first and second transistors (106,108,124,126,156,158,178,180) coupled together in a differential arrangement, each transistor (106,108,124,126,156,158,178,180) having a respective control node comprising a base node or a gate node, and each transistor (106,108,124,126,156,158,178,180) having a respective current node comprising an emitter node or a source node through which a respective current flows; and an offset correction circuit disposed upon the circuit substrate, the offset correction circuit operable to adjust an offset voltage of the differential amplifier, the offset correction circuit comprising: a resistor network (102,104) having a plurality of resistors, the resistor network (102,104) coupled between the current nodes of the first and second transistors (106,108,124,126,156,158,178,180); a plurality of current generators (22,110,114,120,160,164,170) for simultaneously generating a respective plurality of currents, each current generator (22,110,114,120,160,164,170) having first and second respective nodes; a switching network having a plurality of switches (112,118,162,168), each switch (112,118,162,168) having a respective control node and respective first and second switched nodes, the first switched nodes coupled to the resistor network (102,104) and the second switched nodes coupled to the first nodes of the plurality of current generators (110,114,120,160,164,170); and a selection circuit (116,122,168,172) configured to generate a plurality of control signals, each control signal coupled to a respective control node of the switching network and operable to close one or more respective ones of the plurality of switches (112,118,162,168). a resistor network (102,104) having a plurality of resistors, the resistor network (102,104) coupled between the current nodes of the first and second transistors (106,108,124,126,156,158,178,180); a plurality of current generators (22,110,114,120,160,164,170) for simultaneously generating a respective plurality of currents, each current generator (22,110,114,120,160,164,170) having first and second respective nodes; a switching network having a plurality of switches (112,118,162,168), each switch (112,118,162,168) having a respective control node and respective first and second switched nodes, the first switched nodes coupled to the resistor network (102,104) and the second switched nodes coupled to the first nodes of the plurality of current generators (110,114,120,160,164,170); and a selection circuit (116,122,168,172) configured to generate a plurality of control signals, each control signal coupled to a respective control node of the switching network and operable to close one or more respective ones of the plurality of switches (112,118,162,168).