A method of forming a memory device, comprising: providing a semiconductor substrate having a memory array area, a core device area and a high voltage, HV, device area; forming a first conductive layer over and insulated from the substrate in the memory array, core device, and HV device areas; forming a second conductive layer over and insulated from the first conductive layer in the memory array, core device, and HV device areas; forming a first insulation layer over the second conductive layer in the memory array, core device, and HV device areas; etching through portions of the first insulation layer and the first and second conductive layers in the memory array area to form pairs of stacks (S1, S2), wherein each of the stacks (S1, S2) includes a block of the second conductive layer over and insulated from a block of the first conductive layer; forming source regions in the substrate, wherein each of the source regions is disposed between the stacks (S1, S2) of one of the pairs of stacks; forming a third conductive layer over the first insulation layer in the memory array, core device and HV device areas; removing the third conductive layer from the core device and HV device areas, leaving the third conductive layer between and outside of the stacks (S1, S2) of the pairs of stacks in the memory array area; forming a second insulation layer over the third conductive layer and over the first insulation layer in the memory array area and over the first insulation layer in the core device and HV device areas; removing the first and second insulation layers, and the first and second conductive layers, from the core device and HV device areas; forming conductive gates disposed over and insulated from the substrate in the core device and HV device areas; removing the second insulation layer in the memory array area; removing portions of the third conductive layer to form blocks of the third conductive layer adjacent to and insulated from the pairs of stacks; forming drain regions in the substrate adjacent the blocks of the third conductive layer in the memory array area; and forming second source and second drain regions in the substrate adjacent the conductive gates in the core device and HV device areas. providing a semiconductor substrate having a memory array area, a core device area and a high voltage, HV, device area; forming a first conductive layer over and insulated from the substrate in the memory array, core device, and HV device areas; forming a second conductive layer over and insulated from the first conductive layer in the memory array, core device, and HV device areas; forming a first insulation layer over the second conductive layer in the memory array, core device, and HV device areas; etching through portions of the first insulation layer and the first and second conductive layers in the memory array area to form pairs of stacks (S1, S2), wherein each of the stacks (S1, S2) includes a block of the second conductive layer over and insulated from a block of the first conductive layer; forming source regions in the substrate, wherein each of the source regions is disposed between the stacks (S1, S2) of one of the pairs of stacks; forming a third conductive layer over the first insulation layer in the memory array, core device and HV device areas; removing the third conductive layer from the core device and HV device areas, leaving the third conductive layer between and outside of the stacks (S1, S2) of the pairs of stacks in the memory array area; forming a second insulation layer over the third conductive layer and over the first insulation layer in the memory array area and over the first insulation layer in the core device and HV device areas; removing the first and second insulation layers, and the first and second conductive layers, from the core device and HV device areas; forming conductive gates disposed over and insulated from the substrate in the core device and HV device areas; removing the second insulation layer in the memory array area; removing portions of the third conductive layer to form blocks of the third conductive layer adjacent to and insulated from the pairs of stacks; forming drain regions in the substrate adjacent the blocks of the third conductive layer in the memory array area; and forming second source and second drain regions in the substrate adjacent the conductive gates in the core device and HV device areas.