A method of forming a semiconductor structure, characterized by comprising: providing an initial substrate; forming, in the initial substrate, a substrate and a capacitive structure located on a top surface of the substrate, wherein the capacitive structure comprises a plurality of capacitors arranged in an array along a first direction and a second direction, the first direction and the second direction are each parallel to the top surface of the substrate, and the first direction intersects with the second direction; forming, in the initial substrate, a transistor structure located above the capacitive structure, wherein the transistor structure comprises a plurality of active pillars and a plurality of word lines, the active pillar is electrically connected to the capacitor, and the word line extends along the second direction and continuously cover the active pillars arranged at intervals along the second direction; and forming a bit line structure above the transistor structure, wherein the bit line structure comprises a plurality of bit lines, and the bit line extends along the first direction and are electrically connected to the active pillars arranged at intervals along the first direction; wherein the forming, in the initial substrate, a substrate and a capacitive structure located on a top surface of the substrate specifically comprises: etching the initial substrate, and forming a plurality of semiconductor pillars arranged in an array along the first direction and the second direction, etching holes each located between adjacent ones of the semiconductor pillars, and a plurality of recesses in communication with the plurality of etching holes in a one-to-one manner and located below the etching holes; forming a substrate isolation layer connecting adjacent ones of the recesses and filling up the recesses, and using the remaining initial substrate below the substrate isolation layer as the substrate; and forming a capacitor in the etching hole. providing an initial substrate; forming, in the initial substrate, a substrate and a capacitive structure located on a top surface of the substrate, wherein the capacitive structure comprises a plurality of capacitors arranged in an array along a first direction and a second direction, the first direction and the second direction are each parallel to the top surface of the substrate, and the first direction intersects with the second direction; forming, in the initial substrate, a transistor structure located above the capacitive structure, wherein the transistor structure comprises a plurality of active pillars and a plurality of word lines, the active pillar is electrically connected to the capacitor, and the word line extends along the second direction and continuously cover the active pillars arranged at intervals along the second direction; and forming a bit line structure above the transistor structure, wherein the bit line structure comprises a plurality of bit lines, and the bit line extends along the first direction and are electrically connected to the active pillars arranged at intervals along the first direction; wherein the forming, in the initial substrate, a substrate and a capacitive structure located on a top surface of the substrate specifically comprises: etching the initial substrate, and forming a plurality of semiconductor pillars arranged in an array along the first direction and the second direction, etching holes each located between adjacent ones of the semiconductor pillars, and a plurality of recesses in communication with the plurality of etching holes in a one-to-one manner and located below the etching holes; forming a substrate isolation layer connecting adjacent ones of the recesses and filling up the recesses, and using the remaining initial substrate below the substrate isolation layer as the substrate; and forming a capacitor in the etching hole. etching the initial substrate, and forming a plurality of semiconductor pillars arranged in an array along the first direction and the second direction, etching holes each located between adjacent ones of the semiconductor pillars, and a plurality of recesses in communication with the plurality of etching holes in a one-to-one manner and located below the etching holes; forming a substrate isolation layer connecting adjacent ones of the recesses and filling up the recesses, and using the remaining initial substrate below the substrate isolation layer as the substrate; and forming a capacitor in the etching hole.