A signal processing apparatus (200, 300), comprising: a signal input interface (210, 360), a signal output interface (220, 370), a reset signal generation unit (230, 310), a signal amplification and equalization unit (240, 320), an enable signal generation unit (250, 330), and N direct-current offset calibration loop units (260, 340, 350), wherein N is a positive integer; the signal input interface (210, 360) is connected to the signal amplification and equalization unit (240, 320), the signal amplification and equalization unit (240, 320) is connected to the signal output interface (220, 370) and the enable signal generation unit (250, 330), the enable signal generation unit (250, 330) is connected to the N direct-current offset calibration loop units (260, 340, 350), the N direct-current offset calibration loop units (260, 340, 350) are connected to the signal amplification and equalization unit (240, 320), and the reset signal generation unit (230, 310) is connected to the N direct-current offset calibration loop units (260, 340, 350); the signal input interface (210, 360) is configured to receive a first signal; the reset signal generation unit (230, 310) is configured to output a reset signal to the N direct-current offset calibration loop units (260, 340, 350) when an interval time occurs in the data burst block in the first signal; the signal amplification and equalization unit (240, 320) is configured to: adjust, based on a second signal output by the N direct-current offset calibration loop units (260, 340, 350), the first signal received from the signal input interface (210, 360), and amplify and equalize the first signal; the enable signal generation unit (250, 330) is configured to: detect a differential voltage corresponding to a signal output by the signal amplification and equalization unit (240, 320), and output an enable signal to the N direct-current offset calibration loop units (260, 340, 350) based on the differential voltage; the enable signal generation unit (250, 330) is further configured to output a clock signal to the N direct-current offset calibration loop units (260, 340, 350) based on the enable signal; the N direct-current offset calibration loop units (260, 340, 350) are configured to: perform resetting when receiving the reset signal output by the reset signal generation unit (230, 310), and when receiving the enable signal output by the enable signal generation unit (250, 330), start to output the second signal to the signal amplification and equalization unit (240, 320) based on the clock signal; and the signal output interface (220, 370) is configured to output the output signal adjusted, amplified, and equalized by the amplification and equalization unit (240, 320). the signal input interface (210, 360) is connected to the signal amplification and equalization unit (240, 320), the signal amplification and equalization unit (240, 320) is connected to the signal output interface (220, 370) and the enable signal generation unit (250, 330), the enable signal generation unit (250, 330) is connected to the N direct-current offset calibration loop units (260, 340, 350), the N direct-current offset calibration loop units (260, 340, 350) are connected to the signal amplification and equalization unit (240, 320), and the reset signal generation unit (230, 310) is connected to the N direct-current offset calibration loop units (260, 340, 350); the signal input interface (210, 360) is configured to receive a first signal; the reset signal generation unit (230, 310) is configured to output a reset signal to the N direct-current offset calibration loop units (260, 340, 350) when an interval time occurs in the data burst block in the first signal; the signal amplification and equalization unit (240, 320) is configured to: adjust, based on a second signal output by the N direct-current offset calibration loop units (260, 340, 350), the first signal received from the signal input interface (210, 360), and amplify and equalize the first signal; the enable signal generation unit (250, 330) is configured to: detect a differential voltage corresponding to a signal output by the signal amplification and equalization unit (240, 320), and output an enable signal to the N direct-current offset calibration loop units (260, 340, 350) based on the differential voltage; the enable signal generation unit (250, 330) is further configured to output a clock signal to the N direct-current offset calibration loop units (260, 340, 350) based on the enable signal; the N direct-current offset calibration loop units (260, 340, 350) are configured to: perform resetting when receiving the reset signal output by the reset signal generation unit (230, 310), and when receiving the enable signal output by the enable signal generation unit (250, 330), start to output the second signal to the signal amplification and equalization unit (240, 320) based on the clock signal; and the signal output interface (220, 370) is configured to output the output signal adjusted, amplified, and equalized by the amplification and equalization unit (240, 320).