A channel clock generator circuit to identify a channel for selection and insertion or extraction of digital data to or from a multiplexed serial data stream without the requirement of extra channel selection inputs, comprising: - a plurality of counters (515, 520) wherein each counter (515, 520) is designated to represent a channel of a multiplexed serialized data stream that is to be selected, wherein the input of each counter (515, 520) receives one of a multiple serial clock timing signals or word select signals (505, 510) for synchronizing the multiplexed serialized data stream such that the input of a designated counter (515, 520) receives one serial clock timing signal or one word select signal that has a greatest frequency indicative of the serial clock timing signal and the remaining counters (515, 520) receive the serial clock timing signal or word select signal indicative of the word select signals for identifying the channel being selected; - a valid signal generator circuit connected to the plurality of counters (515, 520) to receive a ready signal (525, 530) indicating that one of the counters (515, 520) has the one serial clock timing signal and is configured for generating a valid signal from one of the ready signals (525, 530) from one of the plurality of counters (515,520) receiving the one serial clock timing signal for indicating that the correct serial clock signal SCK and the correct word select signal WS are valid for gating to an external signal extraction or insertion circuit; and - a plurality of multiple signal selection circuits (540, 545) connected to receive each of the multiple serial clock timing signals or word select signals (505,510) and in communication with the counters (515, 520) to receive the ready signal (525, 530) from at least one of the counters (515, 520) to select a correct serial clock timing signal or word select signal (505, 510) from the multiple serial clock timing signals or word select signals (505,510) for providing a correct serial clock signal SCK and correct word select signal WS to an external signal extraction or insertion circuit for extracting or inserting serial data to the multiplexed serialized data stream. - a plurality of counters (515, 520) wherein each counter (515, 520) is designated to represent a channel of a multiplexed serialized data stream that is to be selected, wherein the input of each counter (515, 520) receives one of a multiple serial clock timing signals or word select signals (505, 510) for synchronizing the multiplexed serialized data stream such that the input of a designated counter (515, 520) receives one serial clock timing signal or one word select signal that has a greatest frequency indicative of the serial clock timing signal and the remaining counters (515, 520) receive the serial clock timing signal or word select signal indicative of the word select signals for identifying the channel being selected; - a valid signal generator circuit connected to the plurality of counters (515, 520) to receive a ready signal (525, 530) indicating that one of the counters (515, 520) has the one serial clock timing signal and is configured for generating a valid signal from one of the ready signals (525, 530) from one of the plurality of counters (515,520) receiving the one serial clock timing signal for indicating that the correct serial clock signal SCK and the correct word select signal WS are valid for gating to an external signal extraction or insertion circuit; and - a plurality of multiple signal selection circuits (540, 545) connected to receive each of the multiple serial clock timing signals or word select signals (505,510) and in communication with the counters (515, 520) to receive the ready signal (525, 530) from at least one of the counters (515, 520) to select a correct serial clock timing signal or word select signal (505, 510) from the multiple serial clock timing signals or word select signals (505,510) for providing a correct serial clock signal SCK and correct word select signal WS to an external signal extraction or insertion circuit for extracting or inserting serial data to the multiplexed serialized data stream.