A solid-state imaging device comprising: a photodetecting section having M×N (M is an integer not less than 2, N is an integer not less than 2) pixels each including a photodiode and a transistor connected at one end to the photodiode that are arrayed two-dimensionally in M rows and N columns; N readout wiring lines arranged for each column, and connected to the-other-side ends of the transistors included in the pixels of corresponding columns; a signal output section including N integration circuits for generating voltage values according to amounts of charges input through the respective N readout wiring lines, and for sequentially outputting voltage values output from the N integration circuits; potential changing means for switching potentials of K (K is an integer not less than 1 and not more than N) readout wiring lines included in the N readout wiring lines to a potential different from input potentials of corresponding K integration circuits; and a controlling section for controlling an output operation of voltage values in the signal output section and a switching operation of potentials in the potential changing means, wherein the controlling section is configured to reduce a difference between the electrode potential of the photodiode in each pixel and the potential of the corresponding readout wiring line by switching potentials of the K readout wiring lines to the different potential, the different potential being equivalent to the electrode potential of the photodiode of the corresponding pixel, for a predetermined period in which the transistor in each pixel is kept in a non-connected state and the charge is accumulated in the photodiode, the predetermined period being included in a period, starting, after an elapse of a readout period where voltage values corresponding to amounts of charges generated in the M×N pixels are sequentially output from the signal output section and, ending when a next readout period is started. a photodetecting section having M×N (M is an integer not less than 2, N is an integer not less than 2) pixels each including a photodiode and a transistor connected at one end to the photodiode that are arrayed two-dimensionally in M rows and N columns; N readout wiring lines arranged for each column, and connected to the-other-side ends of the transistors included in the pixels of corresponding columns; a signal output section including N integration circuits for generating voltage values according to amounts of charges input through the respective N readout wiring lines, and for sequentially outputting voltage values output from the N integration circuits; potential changing means for switching potentials of K (K is an integer not less than 1 and not more than N) readout wiring lines included in the N readout wiring lines to a potential different from input potentials of corresponding K integration circuits; and a controlling section for controlling an output operation of voltage values in the signal output section and a switching operation of potentials in the potential changing means, wherein the controlling section is configured to reduce a difference between the electrode potential of the photodiode in each pixel and the potential of the corresponding readout wiring line by switching potentials of the K readout wiring lines to the different potential, the different potential being equivalent to the electrode potential of the photodiode of the corresponding pixel, for a predetermined period in which the transistor in each pixel is kept in a non-connected state and the charge is accumulated in the photodiode, the predetermined period being included in a period, starting, after an elapse of a readout period where voltage values corresponding to amounts of charges generated in the M×N pixels are sequentially output from the signal output section and, ending when a next readout period is started.