A self-adjusting delay circuit adapted to delay a received clock signal provided for a received data signal (data), said self-adjusting delay circuit comprising: a clock edge counter adapted to count signal edges of the received clock signal providing an incremented n-bit counter value at output terminals (28-i) connected to corresponding inputs (29-i) of an adjustable delay line of said self-adjusting delay circuit via parallel signal lines (30-i), said adjustable delay line having a number (n) of inverters (50-i) being connected to each other in parallel, wherein each inverter (50-i) of said adjustable delay line is enabled by an associated bit of the n-bit counter value received from said clock edge counter via the parallel signal lines (30-i) to invert the received clock signal with a driving current strength of the inverter (50-i) corresponding to the significance of the respective bit of said n-bit counter value to load a capacitor of said adjustable delay line connected to the outputs of the inverters (50-i), wherein the driving current strength of the i-th inverter (50-i) of said adjustable delay line is 2 i-1 with 1≤i≤n, said self-adjusting delay circuit further comprising: - an edge comparator formed by a flip-flop having a clock input receiving the delayed clock signal (CLK') output by a clock output of said adjustable delay line and having a data input receiving the data signal (data) and - a phase margin security circuit for providing a phase margin security against clock jitter of the received clock signal, said phase margin security circuit comprising a predetermined number of flip-flops (13-i) connected in series to each other, wherein the first flip-flop of said phase margin security circuit is connected to an output of the flip-flop of said edge comparator, wherein the received clock signal is delayed by said adjustable delay line with an increasing time delay proportional to the incremented n-bit counter value output by said clock edge counter until said edge comparator detects that a rising signal edge of the received data signal (data) precedes a rising signal edge of the delayed clock signal (CLK') output by the clock output of said adjustable delay line including a time margin provided by said phase margin security circuit. a clock edge counter adapted to count signal edges of the received clock signal providing an incremented n-bit counter value at output terminals (28-i) connected to corresponding inputs (29-i) of an adjustable delay line of said self-adjusting delay circuit via parallel signal lines (30-i), said adjustable delay line having a number (n) of inverters (50-i) being connected to each other in parallel, wherein each inverter (50-i) of said adjustable delay line is enabled by an associated bit of the n-bit counter value received from said clock edge counter via the parallel signal lines (30-i) to invert the received clock signal with a driving current strength of the inverter (50-i) corresponding to the significance of the respective bit of said n-bit counter value to load a capacitor of said adjustable delay line connected to the outputs of the inverters (50-i), wherein the driving current strength of the i-th inverter (50-i) of said adjustable delay line is 2 i-1 with 1≤i≤n, said self-adjusting delay circuit further comprising: - an edge comparator formed by a flip-flop having a clock input receiving the delayed clock signal (CLK') output by a clock output of said adjustable delay line and having a data input receiving the data signal (data) and - a phase margin security circuit for providing a phase margin security against clock jitter of the received clock signal, said phase margin security circuit comprising a predetermined number of flip-flops (13-i) connected in series to each other, - an edge comparator formed by a flip-flop having a clock input receiving the delayed clock signal (CLK') output by a clock output of said adjustable delay line and having a data input receiving the data signal (data) and - a phase margin security circuit for providing a phase margin security against clock jitter of the received clock signal, said phase margin security circuit comprising a predetermined number of flip-flops (13-i) connected in series to each other, wherein the first flip-flop of said phase margin security circuit is connected to an output of the flip-flop of said edge comparator, wherein the received clock signal is delayed by said adjustable delay line with an increasing time delay proportional to the incremented n-bit counter value output by said clock edge counter until said edge comparator detects that a rising signal edge of the received data signal (data) precedes a rising signal edge of the delayed clock signal (CLK') output by the clock output of said adjustable delay line including a time margin provided by said phase margin security circuit.