A processing system comprising: a microcontroller device; an external memory device external to the microcontroller device, the external memory device coupled to the microcontroller device and storing one or more application codes, wherein each of the application codes comprises one or more load units, and the load units include executable instructions and/or data; the microcontroller device including: bus masters (202, 204, 206, 207) configured to execute the application codes; a random access memory, RAM, device internal to the microcontroller device and coupled to the bus masters via an interconnect, the RAM device configured to store copies of a subset of the load units; an address mapping device (270, 272, 274, 276) coupled to an access path from the bus masters to the RAM device, the address mapping device configured to modify a portion of an access request from a bus master that represents an address of the requested information; a cache controller device coupled to the RAM device and the external memory device, the cache controller device configured to: partition a copy of one of the load units into one or more segments, wherein the segments have a length up to a page size of the RAM device; load the segments into one or more of the pages with available space in the RAM device; maintain a record of the one or more pages into which the segments were loaded, wherein the cache controller device is further configured to perform each following operation independently of one another: allocate one segment associated with one of the load units to one of the pages, wherein the one segment occupies all of the one of the pages; allocate one segment associated with one of the load units to one of the pages, wherein the one segment occupies only a first or second portion of the one of the pages and a remaining portion of the one of the pages is available as free space; and allocate two segments associated with two different load units to one of the pages. a microcontroller device; an external memory device external to the microcontroller device, the external memory device coupled to the microcontroller device and storing one or more application codes, wherein each of the application codes comprises one or more load units, and the load units include executable instructions and/or data; the microcontroller device including: bus masters (202, 204, 206, 207) configured to execute the application codes; a random access memory, RAM, device internal to the microcontroller device and coupled to the bus masters via an interconnect, the RAM device configured to store copies of a subset of the load units; an address mapping device (270, 272, 274, 276) coupled to an access path from the bus masters to the RAM device, the address mapping device configured to modify a portion of an access request from a bus master that represents an address of the requested information; a cache controller device coupled to the RAM device and the external memory device, the cache controller device configured to: partition a copy of one of the load units into one or more segments, wherein the segments have a length up to a page size of the RAM device; load the segments into one or more of the pages with available space in the RAM device; maintain a record of the one or more pages into which the segments were loaded, bus masters (202, 204, 206, 207) configured to execute the application codes; a random access memory, RAM, device internal to the microcontroller device and coupled to the bus masters via an interconnect, the RAM device configured to store copies of a subset of the load units; an address mapping device (270, 272, 274, 276) coupled to an access path from the bus masters to the RAM device, the address mapping device configured to modify a portion of an access request from a bus master that represents an address of the requested information; a cache controller device coupled to the RAM device and the external memory device, the cache controller device configured to: partition a copy of one of the load units into one or more segments, wherein the segments have a length up to a page size of the RAM device; load the segments into one or more of the pages with available space in the RAM device; maintain a record of the one or more pages into which the segments were loaded, partition a copy of one of the load units into one or more segments, wherein the segments have a length up to a page size of the RAM device; load the segments into one or more of the pages with available space in the RAM device; maintain a record of the one or more pages into which the segments were loaded, wherein the cache controller device is further configured to perform each following operation independently of one another: allocate one segment associated with one of the load units to one of the pages, wherein the one segment occupies all of the one of the pages; allocate one segment associated with one of the load units to one of the pages, wherein the one segment occupies only a first or second portion of the one of the pages and a remaining portion of the one of the pages is available as free space; and allocate two segments associated with two different load units to one of the pages. allocate one segment associated with one of the load units to one of the pages, wherein the one segment occupies all of the one of the pages; allocate one segment associated with one of the load units to one of the pages, wherein the one segment occupies only a first or second portion of the one of the pages and a remaining portion of the one of the pages is available as free space; and allocate two segments associated with two different load units to one of the pages.