Light emitting diode chip comprising a semiconductor layer sequence situated on a carrier, and comprising an ESD protection device, which protects the light emitting diode chip against overvoltages, wherein the ESD protection device is produced by the doping of specific partial regions (21, 22) of the carrier and the ESD protection device has, in a direction parallel to a growth direction of the semiconductor layer sequence, exactly one n-doped partial region and exactly one p-doped partial region, characterized in that - the doped partial regions (21, 22) of the ESD protection device are completely separated by a barrier layer from a remaining partial region of the carrier and are not in direct electrical contact with the latter, - the ESD protection device is connected to the semiconductor layer sequence by means of an electrical conductor structure and the semiconductor layer sequence is covered at least partly by an insulation layer, on which the electrical conductor structure is situated, - the barrier layer is formed by a trench filled with silicon oxide or silicon nitride, - the barrier layer, in a direction parallel to the growth direction, penetrates through the carrier completely, - the carrier is not covered by the semiconductor layer sequence in a circumferential marginal region, - the semiconductor layer sequence, as seen in plan view, has a cutout in a corner region, the ESD protection device which is not covered by the semiconductor layer sequence being situated in said cutout, - the remaining partial region of the carrier which lies outside the ESD protection device is electrically conductive, and - the semiconductor layer sequence has a lower and an upper contact region for the purpose of electrical contacting, wherein the upper contact region faces away from the carrier and the lower contact region is fixed on the carrier by means of an electrically conductive material. - the doped partial regions (21, 22) of the ESD protection device are completely separated by a barrier layer from a remaining partial region of the carrier and are not in direct electrical contact with the latter, - the ESD protection device is connected to the semiconductor layer sequence by means of an electrical conductor structure and the semiconductor layer sequence is covered at least partly by an insulation layer, on which the electrical conductor structure is situated, - the barrier layer is formed by a trench filled with silicon oxide or silicon nitride, - the barrier layer, in a direction parallel to the growth direction, penetrates through the carrier completely, - the carrier is not covered by the semiconductor layer sequence in a circumferential marginal region, - the semiconductor layer sequence, as seen in plan view, has a cutout in a corner region, the ESD protection device which is not covered by the semiconductor layer sequence being situated in said cutout, - the remaining partial region of the carrier which lies outside the ESD protection device is electrically conductive, and - the semiconductor layer sequence has a lower and an upper contact region for the purpose of electrical contacting, wherein the upper contact region faces away from the carrier and the lower contact region is fixed on the carrier by means of an electrically conductive material.