A master controller configured to synchronize a plurality of timebase counters of a plurality of slave integrated circuits, wherein each of the plurality of timebase counters of the plurality of slave integrated circuits are configured to receive a clock signal oscillating at a predetermined common frequency, each timebase counter being configured to count from a first common value to a second common value then reset to the first common value, the master controller comprising: a master timebase counter; a register arranged to store a master timebase counter value; a data interface arranged to communicate with the plurality of slave integrated circuits; and a processor arranged to: cause the master controller to transmit a command to the slave integrated circuits; store the master timebase counter value in the register at the time of the command; receive a timebase counter value from each slave integrated circuit, each received timebase counter value being the timebase counter value recorded by the respective slave integrated circuit upon receipt of the command whilst each timebase counter performs a cyclic count from the first common value to the second common value; determine if each slave integrated circuit is in sync or out of sync by comparing each received timebase counter value to the master timebase counter value; and for each out of sync slave integrated circuit, calculate a correction offset value based on that slave integrated circuit's timebase counter value and transmit the correction offset value to that slave integrated circuit to cause the timebase counter of that out of sync slave integrated circuit to count between the correction offset value and the second common value before returning to counting between the first common value and the second common value in order to synchronise the time instant at which the timebase counters of the plurality of slave integrated circuits reset to the first common value whilst performing their counting. a master timebase counter; a register arranged to store a master timebase counter value; a data interface arranged to communicate with the plurality of slave integrated circuits; and a processor arranged to: cause the master controller to transmit a command to the slave integrated circuits; store the master timebase counter value in the register at the time of the command; receive a timebase counter value from each slave integrated circuit, each received timebase counter value being the timebase counter value recorded by the respective slave integrated circuit upon receipt of the command whilst each timebase counter performs a cyclic count from the first common value to the second common value; determine if each slave integrated circuit is in sync or out of sync by comparing each received timebase counter value to the master timebase counter value; and for each out of sync slave integrated circuit, calculate a correction offset value based on that slave integrated circuit's timebase counter value and transmit the correction offset value to that slave integrated circuit to cause the timebase counter of that out of sync slave integrated circuit to count between the correction offset value and the second common value before returning to counting between the first common value and the second common value in order to synchronise the time instant at which the timebase counters of the plurality of slave integrated circuits reset to the first common value whilst performing their counting. cause the master controller to transmit a command to the slave integrated circuits; store the master timebase counter value in the register at the time of the command; receive a timebase counter value from each slave integrated circuit, each received timebase counter value being the timebase counter value recorded by the respective slave integrated circuit upon receipt of the command whilst each timebase counter performs a cyclic count from the first common value to the second common value; determine if each slave integrated circuit is in sync or out of sync by comparing each received timebase counter value to the master timebase counter value; and for each out of sync slave integrated circuit, calculate a correction offset value based on that slave integrated circuit's timebase counter value and transmit the correction offset value to that slave integrated circuit to cause the timebase counter of that out of sync slave integrated circuit to count between the correction offset value and the second common value before returning to counting between the first common value and the second common value in order to synchronise the time instant at which the timebase counters of the plurality of slave integrated circuits reset to the first common value whilst performing their counting.