A memory array, comprising: a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, each memory cell further comprising: a storage device; and an access device formed in the substrate that is coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the memory array further comprising: a plurality of access structures including a plurality of first trenches, each first trench formed in the semiconductor substrate and each first trench including a pair of opposing side walls and a floor extending therebetween, the side walls including active regions of the access device; a plurality of second trenches, extending in a direction perpendicular to the first pairs of opposing side walls of the plurality of first trenches, each second trench formed between adjacent ones of the plurality of access structures, and each second trench including a dielectric layer formed on respective side walls of each second trench; and a plurality of third trenches formed between and parallel to adjacent ones of the first trenches and having a depth greater than the depth (d 3) of the first trenches characterized in that a conductive film structure is partially disposed on respective side walls of each second trench on the dielectric layer. a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, each memory cell further comprising: a storage device; and an access device formed in the substrate that is coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the memory array further comprising: a plurality of access structures including a plurality of first trenches, each first trench formed in the semiconductor substrate and each first trench including a pair of opposing side walls and a floor extending therebetween, the side walls including active regions of the access device; a plurality of second trenches, extending in a direction perpendicular to the first pairs of opposing side walls of the plurality of first trenches, each second trench formed between adjacent ones of the plurality of access structures, and each second trench including a dielectric layer formed on respective side walls of each second trench; and a plurality of third trenches formed between and parallel to adjacent ones of the first trenches and having a depth greater than the depth (d 3) of the first trenches characterized in that a conductive film structure is partially disposed on respective side walls of each second trench on the dielectric layer. a storage device; and an access device formed in the substrate that is coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the memory array further comprising: a plurality of access structures including a plurality of first trenches, each first trench formed in the semiconductor substrate and each first trench including a pair of opposing side walls and a floor extending therebetween, the side walls including active regions of the access device; a plurality of second trenches, extending in a direction perpendicular to the first pairs of opposing side walls of the plurality of first trenches, each second trench formed between adjacent ones of the plurality of access structures, and each second trench including a dielectric layer formed on respective side walls of each second trench; and a plurality of third trenches formed between and parallel to adjacent ones of the first trenches and having a depth greater than the depth (d 3) of the first trenches characterized in that a conductive film structure is partially disposed on respective side walls of each second trench on the dielectric layer. a plurality of access structures including a plurality of first trenches, each first trench formed in the semiconductor substrate and each first trench including a pair of opposing side walls and a floor extending therebetween, the side walls including active regions of the access device; a plurality of second trenches, extending in a direction perpendicular to the first pairs of opposing side walls of the plurality of first trenches, each second trench formed between adjacent ones of the plurality of access structures, and each second trench including a dielectric layer formed on respective side walls of each second trench; and a plurality of third trenches formed between and parallel to adjacent ones of the first trenches and having a depth greater than the depth (d 3) of the first trenches characterized in that a conductive film structure is partially disposed on respective side walls of each second trench on the dielectric layer.