A metal oxide semiconductor, MOS, integrated circuit, IC, (300, 400, 500) including a first standard cell (302a, 402a, 502a) and a second standard cell (302b, 402b, 502b) adjacent the first standard cell, the MOS IC comprising: a first MOS transistor (354a, 454a, 554a) in the first standard cell (302a, 402a, 502a), the first MOS transistor (354a, 454a, 554a) having a first MOS transistor source (352a, 452a, 552a); a first contact interconnect (330, 430, 530) extending in a first direction and contacting the first MOS transistor source (352a, 452a, 552a), the first contact interconnect (330, 430, 530) being within the first standard cell (302a, 402a, 502a), the first contact interconnect (330, 430, 530) being coupled to a voltage source (342, 442, 542); a first double diffusion break (356, 456, 556a) extending along a first boundary in the first direction of the first standard cell (302a, 402a, 502a) and the second standard cell (302b, 402b, 502b), the first double diffusion break (356, 456, 556a) being within both the first standard cell and the second standard cell; a second contact interconnect (360, 460, 560) extending in the first direction along the first boundary and over a portion of the first double diffusion break (356, 456, 556a), the second contact interconnect (360, 460, 560) being within both the first standard cell and the second standard cell, the second contact interconnect (360, 460, 560) being coupled to the voltage source (342, 442, 542); and a third contact interconnect (362, 462, 562) extending in a second direction orthogonal to the first direction and contacting the first contact interconnect (330, 430, 530) and the second contact interconnect (360, 460, 560) to couple the first contact interconnect (330, 430, 530) and the second contact interconnect (360, 460, 560) together. a first MOS transistor (354a, 454a, 554a) in the first standard cell (302a, 402a, 502a), the first MOS transistor (354a, 454a, 554a) having a first MOS transistor source (352a, 452a, 552a); a first contact interconnect (330, 430, 530) extending in a first direction and contacting the first MOS transistor source (352a, 452a, 552a), the first contact interconnect (330, 430, 530) being within the first standard cell (302a, 402a, 502a), the first contact interconnect (330, 430, 530) being coupled to a voltage source (342, 442, 542); a first double diffusion break (356, 456, 556a) extending along a first boundary in the first direction of the first standard cell (302a, 402a, 502a) and the second standard cell (302b, 402b, 502b), the first double diffusion break (356, 456, 556a) being within both the first standard cell and the second standard cell; a second contact interconnect (360, 460, 560) extending in the first direction along the first boundary and over a portion of the first double diffusion break (356, 456, 556a), the second contact interconnect (360, 460, 560) being within both the first standard cell and the second standard cell, the second contact interconnect (360, 460, 560) being coupled to the voltage source (342, 442, 542); and a third contact interconnect (362, 462, 562) extending in a second direction orthogonal to the first direction and contacting the first contact interconnect (330, 430, 530) and the second contact interconnect (360, 460, 560) to couple the first contact interconnect (330, 430, 530) and the second contact interconnect (360, 460, 560) together.