A method of manufacturing a substantially planar electronic device comprising a first terminal, a second terminal, and a semiconductor channel providing a current flow path via which current can flow from the first terminal to the second terminal, the method comprising the steps of: providing a substrate and a layer of semiconductor material supported by the substrate; forming a layer of resist material over the layer of semiconductor material, the layer of resist material comprising a plurality of first portions each having a first thickness, a second portion (R2a) having a second thickness, and a plurality of third portions each having a third thickness, wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness, said first portions defining positions of insulative features to be formed to interrupt the layer of semiconductor material and define at least a position of the semiconductor channel, the second portion (R2a) covering at least the semiconductor channel, and said third portions defining positions of the first and second terminals (22; 23); processing the layer of resist material to remove said first portions of the layer of resist material, without removing entirely the second (R2a) or third portions, to expose surfaces of corresponding underlying first portions of the semiconductor layer; removing said first portions of the semiconductor layer to expose surfaces of corresponding underlying first portions of the substrate and so form a plurality of insulative features interrupting the semiconductor layer, said plurality of insulative features defining the position of the semiconductor channel; further processing the layer of resist material to remove said second portion (R2a) of the layer of resist material, without removing entirely the third portions, to expose at least a surface of a second portion (R2a) of the semiconductor layer, said second portion (R2a) of the semiconductor layer providing said channel; depositing dielectric material on the resultant structure such that dielectric material fills the insulative features and forms a dielectric layer covering at least the semiconductor channel; and removing the remaining material of the third portions of the layer of resist material to expose surfaces of corresponding underlying third portions of the semiconductor layer. providing a substrate and a layer of semiconductor material supported by the substrate; forming a layer of resist material over the layer of semiconductor material, the layer of resist material comprising a plurality of first portions each having a first thickness, a second portion (R2a) having a second thickness, and a plurality of third portions each having a third thickness, wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness, said first portions defining positions of insulative features to be formed to interrupt the layer of semiconductor material and define at least a position of the semiconductor channel, the second portion (R2a) covering at least the semiconductor channel, and said third portions defining positions of the first and second terminals (22; 23); processing the layer of resist material to remove said first portions of the layer of resist material, without removing entirely the second (R2a) or third portions, to expose surfaces of corresponding underlying first portions of the semiconductor layer; removing said first portions of the semiconductor layer to expose surfaces of corresponding underlying first portions of the substrate and so form a plurality of insulative features interrupting the semiconductor layer, said plurality of insulative features defining the position of the semiconductor channel; further processing the layer of resist material to remove said second portion (R2a) of the layer of resist material, without removing entirely the third portions, to expose at least a surface of a second portion (R2a) of the semiconductor layer, said second portion (R2a) of the semiconductor layer providing said channel; depositing dielectric material on the resultant structure such that dielectric material fills the insulative features and forms a dielectric layer covering at least the semiconductor channel; and removing the remaining material of the third portions of the layer of resist material to expose surfaces of corresponding underlying third portions of the semiconductor layer.