A memory system, comprising: a controller device; a plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) arranged in a point-to-point ring topology with the controller device, each of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) comprising: an input for receiving a packet, a first portion of the packet comprising at least one command byte, and a second portion of the packet including parity bits to facilitate command error detection; a device error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte; circuitry configured to provide the packet to the device error manager; and an output for providing the packet to a subsequent semiconductor memory device or to the controller device; the controller device comprising: a command engine to generate the packet including the at least one command byte and the parity bits; an output to output the packet to a first device of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110); an input to receive the packet from a last device of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) after having been communicated through each of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) arranged in the point-to-point ring topology; and a controller error manager to determine, based on the received packet, whether an error occurred in transmission of the packet within the point to point ring topology, and the command engine being configured to selectively reissue the packet based on at which point the controller error manager determines that the error occurred in the point to point ring topology. a controller device; a plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) arranged in a point-to-point ring topology with the controller device, each of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) comprising: an input for receiving a packet, a first portion of the packet comprising at least one command byte, and a second portion of the packet including parity bits to facilitate command error detection; a device error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte; circuitry configured to provide the packet to the device error manager; and an output for providing the packet to a subsequent semiconductor memory device or to the controller device; an input for receiving a packet, a first portion of the packet comprising at least one command byte, and a second portion of the packet including parity bits to facilitate command error detection; a device error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte; circuitry configured to provide the packet to the device error manager; and an output for providing the packet to a subsequent semiconductor memory device or to the controller device; the controller device comprising: a command engine to generate the packet including the at least one command byte and the parity bits; an output to output the packet to a first device of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110); an input to receive the packet from a last device of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) after having been communicated through each of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) arranged in the point-to-point ring topology; and a controller error manager to determine, based on the received packet, whether an error occurred in transmission of the packet within the point to point ring topology, and the command engine being configured to selectively reissue the packet based on at which point the controller error manager determines that the error occurred in the point to point ring topology. a command engine to generate the packet including the at least one command byte and the parity bits; an output to output the packet to a first device of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110); an input to receive the packet from a last device of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) after having been communicated through each of the plurality of serially interconnected semiconductor memory devices (104, 106, 108, 110) arranged in the point-to-point ring topology; and a controller error manager to determine, based on the received packet, whether an error occurred in transmission of the packet within the point to point ring topology, and the command engine being configured to selectively reissue the packet based on at which point the controller error manager determines that the error occurred in the point to point ring topology.