An oscillator (100, 600, 900) for generating oscillation signals at two output terminals (N1, N2), comprising: an inductor (120, 620) coupled between the two output terminals (N1, N2); a capacitor (110, 610) coupled between the two output terminals (N1, N2); two P-type transistors (MP1, MP2), wherein source electrodes of the two P-type transistors (MP1, MP2) are coupled to a supply voltage, and gate electrodes of the two P-type transistors (MP1, MP2) are coupled to the two output terminals (N1, N2), respectively; and two N-type transistors (MN1, MN2), wherein gate electrodes of the two N-type transistors (MN1, MN2) are coupled to the two output terminals (N1, N2), respectively, and drain electrodes (ND1, ND2) of the two N-type transistors (MN1, MN2) are coupled to drain electrodes (ND1, ND2) of the two P-type transistors (MP1, MP2), respectively; wherein the drain electrodes (ND1, ND2) of the two N-type transistors (MN1, MN2) are coupled to two internal nodes of the inductor (120, 620); characterized in that each of the drain electrodes of the two N-type transistors is directly connected to a respective node of the internal nodes of the inductor, or is connected via a switch (SW1, SW3) of a switch module (SW1 - SW4) to a respective node of the internal nodes of the inductor, wherein the switch is directly connected to the drain electrode of the respective N-type transistor (MN1, MN2) and the respective internal node of the inductor, for selectively connecting the drain electrodes of two N-type transistors (MN1, MN2) to the two internal nodes of the inductor or not, wherein at least a segment of the inductor is in between the two internal nodes of the inductor (120, 620) and a further segment of the inductor (120, 620) is in between each of the internal nodes and a respective output terminal of the two output terminals (N1, N2). an inductor (120, 620) coupled between the two output terminals (N1, N2); a capacitor (110, 610) coupled between the two output terminals (N1, N2); two P-type transistors (MP1, MP2), wherein source electrodes of the two P-type transistors (MP1, MP2) are coupled to a supply voltage, and gate electrodes of the two P-type transistors (MP1, MP2) are coupled to the two output terminals (N1, N2), respectively; and two N-type transistors (MN1, MN2), wherein gate electrodes of the two N-type transistors (MN1, MN2) are coupled to the two output terminals (N1, N2), respectively, and drain electrodes (ND1, ND2) of the two N-type transistors (MN1, MN2) are coupled to drain electrodes (ND1, ND2) of the two P-type transistors (MP1, MP2), respectively; wherein the drain electrodes (ND1, ND2) of the two N-type transistors (MN1, MN2) are coupled to two internal nodes of the inductor (120, 620); characterized in that each of the drain electrodes of the two N-type transistors is directly connected to a respective node of the internal nodes of the inductor, or is connected via a switch (SW1, SW3) of a switch module (SW1 - SW4) to a respective node of the internal nodes of the inductor, wherein the switch is directly connected to the drain electrode of the respective N-type transistor (MN1, MN2) and the respective internal node of the inductor, for selectively connecting the drain electrodes of two N-type transistors (MN1, MN2) to the two internal nodes of the inductor or not, wherein at least a segment of the inductor is in between the two internal nodes of the inductor (120, 620) and a further segment of the inductor (120, 620) is in between each of the internal nodes and a respective output terminal of the two output terminals (N1, N2).