A programmable device comprising a Joint Test Action Group (JTAG) lockout assembly, the JTAG comprising: an embedded processor in the programmable device; a lockout processor operatively connected to the embedded processor, wherein the lockout processor comprises an unlock logic configured to allow or disallow JTAG communication with the embedded processor based on a multi-channel unlock sequence received via two or more unlock channels (122, 124); and a test interface operatively connected to the embedded processor and operatively connected to the lockout processor, the test interface including an unlock controller, the test interface being configured to: retrieve the multi-channel unlock sequence from one or more memory registers (126, 128, 130) via the unlock controller operating on the test interface; and execute the multi-channel unlock sequence across the two or more unlock channels (122, 124) via the unlock controller by providing, to the lockout processor, a series of pulses over at least one unlock channel from the two or more unlock channels based on the multi-channel unlock sequence; wherein the lockout processor is configured to allow access to the programmable device through the JTAG responsive to executing the multi-channel unlock sequence, if the execution of the unlock sequence, by the unlock controller is determined to be valid by the lockout processor, or disallow access to the programmable device through the JTAG responsive to executing the multi-channel unlock sequence, if the execution of the unlock sequence, by the unlock controller is determined to be invalid by the lockout processor; wherein the multi-channel unlock sequence comprises: a sequence portion indicative of one or more pulse sequences (208, 210) that are sequential with respect to a computer clock time; and a channel portion indicative of a channel (122, 124) respectively associated with each of the one or more pulse sequences (208, 210). an embedded processor in the programmable device; a lockout processor operatively connected to the embedded processor, wherein the lockout processor comprises an unlock logic configured to allow or disallow JTAG communication with the embedded processor based on a multi-channel unlock sequence received via two or more unlock channels (122, 124); and a test interface operatively connected to the embedded processor and operatively connected to the lockout processor, the test interface including an unlock controller, the test interface being configured to: retrieve the multi-channel unlock sequence from one or more memory registers (126, 128, 130) via the unlock controller operating on the test interface; and execute the multi-channel unlock sequence across the two or more unlock channels (122, 124) via the unlock controller by providing, to the lockout processor, a series of pulses over at least one unlock channel from the two or more unlock channels based on the multi-channel unlock sequence; retrieve the multi-channel unlock sequence from one or more memory registers (126, 128, 130) via the unlock controller operating on the test interface; and execute the multi-channel unlock sequence across the two or more unlock channels (122, 124) via the unlock controller by providing, to the lockout processor, a series of pulses over at least one unlock channel from the two or more unlock channels based on the multi-channel unlock sequence; wherein the lockout processor is configured to allow access to the programmable device through the JTAG responsive to executing the multi-channel unlock sequence, if the execution of the unlock sequence, by the unlock controller is determined to be valid by the lockout processor, or disallow access to the programmable device through the JTAG responsive to executing the multi-channel unlock sequence, if the execution of the unlock sequence, by the unlock controller is determined to be invalid by the lockout processor; wherein the multi-channel unlock sequence comprises: a sequence portion indicative of one or more pulse sequences (208, 210) that are sequential with respect to a computer clock time; and a channel portion indicative of a channel (122, 124) respectively associated with each of the one or more pulse sequences (208, 210). a sequence portion indicative of one or more pulse sequences (208, 210) that are sequential with respect to a computer clock time; and a channel portion indicative of a channel (122, 124) respectively associated with each of the one or more pulse sequences (208, 210).