A non-volatile semiconductor memory device comprising: a plurality of word lines formed in a matrix to which either one of a charge storage gate voltage and a charge storage inhibition gate voltage is applied; a plurality of memory cells connected to the respective word lines; and a bit line (L1,L2) that is configured to apply a selective voltage to the plurality of memory cells, a charge being stored in selected one of the plurality of memory cells due to a voltage difference between the charge storage gate voltage applied to the word line and the voltage applied to the bit line (L1,L2), characterized in that the non-volatile semiconductor memory device further comprises: power supply units respectively provided for word line columns; and common wirings (PGa,NGa) respectively provided for word line rows, each of the common wirings (PGa,NGa) configured to apply a predetermined common voltage to the power supply units on a word-line-row basis, wherein each of the power supply units includes: switching mechanisms (8a,9a) that are respectively provided for the word lines; and a unit wiring (5a,6a) that extends in the column direction, connects to the switching mechanisms (8a,9a) and uniformly applies unit voltages to the switching mechanisms (8a,9a), the unit voltage being different for each of the power supply units depending on whether or not the selected memory cell exists in the word line column, wherein the switching mechanisms (8a,9a) in each of the power supply units are configured to be turned on or off based on a voltage difference between the unit voltages applied to each of the power supply units and the common voltage, to individually apply the charge storage gate voltage or the charge storage inhibition gate voltage to each of the word lines via the power supply unit, wherein the switching mechanism (8a,9a) includes at least a PMOS switch and an NMOS switch, and the PMOS switch and the NMOS switch are configured to be individually turned on or off based on a voltage difference between the common voltage and the unit voltages occurring when the common voltage and the unit voltage are respectively applied thereto, each of the common wirings (PGa,NGa) includes a common PMOS control line (PGa) connected to a control gate of the PMOS switch and a common NMOS control line (NGa) connected to a control gate of the NMOS switch, the unit wiring (5a,6a) includes a first power supply line connected to a source of the PMOS switch and a second power supply line connected to a source of the NMOS switch, and the word line is connected to each of the drains of the PMOS switch and the NMOS switch. a plurality of word lines formed in a matrix to which either one of a charge storage gate voltage and a charge storage inhibition gate voltage is applied; a plurality of memory cells connected to the respective word lines; and a bit line (L1,L2) that is configured to apply a selective voltage to the plurality of memory cells, a charge being stored in selected one of the plurality of memory cells due to a voltage difference between the charge storage gate voltage applied to the word line and the voltage applied to the bit line (L1,L2), characterized in that the non-volatile semiconductor memory device further comprises: power supply units respectively provided for word line columns; and common wirings (PGa,NGa) respectively provided for word line rows, each of the common wirings (PGa,NGa) configured to apply a predetermined common voltage to the power supply units on a word-line-row basis, wherein each of the power supply units includes: switching mechanisms (8a,9a) that are respectively provided for the word lines; and a unit wiring (5a,6a) that extends in the column direction, connects to the switching mechanisms (8a,9a) and uniformly applies unit voltages to the switching mechanisms (8a,9a), the unit voltage being different for each of the power supply units depending on whether or not the selected memory cell exists in the word line column, wherein switching mechanisms (8a,9a) that are respectively provided for the word lines; and a unit wiring (5a,6a) that extends in the column direction, connects to the switching mechanisms (8a,9a) and uniformly applies unit voltages to the switching mechanisms (8a,9a), the unit voltage being different for each of the power supply units depending on whether or not the selected memory cell exists in the word line column, wherein the switching mechanisms (8a,9a) in each of the power supply units are configured to be turned on or off based on a voltage difference between the unit voltages applied to each of the power supply units and the common voltage, to individually apply the charge storage gate voltage or the charge storage inhibition gate voltage to each of the word lines via the power supply unit, wherein the switching mechanism (8a,9a) includes at least a PMOS switch and an NMOS switch, and the PMOS switch and the NMOS switch are configured to be individually turned on or off based on a voltage difference between the common voltage and the unit voltages occurring when the common voltage and the unit voltage are respectively applied thereto, each of the common wirings (PGa,NGa) includes a common PMOS control line (PGa) connected to a control gate of the PMOS switch and a common NMOS control line (NGa) connected to a control gate of the NMOS switch, the unit wiring (5a,6a) includes a first power supply line connected to a source of the PMOS switch and a second power supply line connected to a source of the NMOS switch, and the word line is connected to each of the drains of the PMOS switch and the NMOS switch.