A system for generating classification information for pixels, comprising: retrieval logic; a pixel storage allocation including a plurality of pixel slots (206a, 206b, 206c) each pixel slot (206a, 206b, 206c) being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots (206a, 206b, 206c) in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel, the pipelined processing logic includes a processing pipe; and scheduling logic configured to control dispatches from the pixel slots (206a, 206b, 206c) to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence, such that for a later pixel which is allocated into its pixel slot (206a, 206b, 206c) later than an earlier pixel is allocated into its pixel slot (206a, 206b, 206c), the pipelined processing logic generates the classification information for the later pixel sooner than for the earlier pixel, where the scheduling logic and processing pipe are configured such that, in the event that the earlier pixel stalls in the processing pipe, the stall is cleared, its pixel slot stores tracking information that is used to control subsequent processing of the earlier pixel in the processing pipe and where the tracking information tracks whether a storage request associated with processing the earlier pixel has been fulfilled, and where the scheduling logic is configured to dispatch the later pixel to the processing pipe prior to re-dispatching the earlier pixel to the processing pipe and re-dispatch the earlier pixel to the processing pipe upon such fulfillment of the storage request, and where the pipelined processing logic is configured to cause each pixel to be processed through a directed graph structure. retrieval logic; a pixel storage allocation including a plurality of pixel slots (206a, 206b, 206c) each pixel slot (206a, 206b, 206c) being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots (206a, 206b, 206c) in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel, the pipelined processing logic includes a processing pipe; and scheduling logic configured to control dispatches from the pixel slots (206a, 206b, 206c) to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence, such that for a later pixel which is allocated into its pixel slot (206a, 206b, 206c) later than an earlier pixel is allocated into its pixel slot (206a, 206b, 206c), the pipelined processing logic generates the classification information for the later pixel sooner than for the earlier pixel, where the scheduling logic and processing pipe are configured such that, in the event that the earlier pixel stalls in the processing pipe, the stall is cleared, its pixel slot stores tracking information that is used to control subsequent processing of the earlier pixel in the processing pipe and where the tracking information tracks whether a storage request associated with processing the earlier pixel has been fulfilled, and where the scheduling logic is configured to dispatch the later pixel to the processing pipe prior to re-dispatching the earlier pixel to the processing pipe and re-dispatch the earlier pixel to the processing pipe upon such fulfillment of the storage request, and where the pipelined processing logic is configured to cause each pixel to be processed through a directed graph structure.