A method for testing whether an interconnect in a semiconductor die suffers from manufacturing defects, the semiconductor die having at its surface a plurality of electrical contact elements (31, 31a, 31b, 31c, 31d; Pad A, Pad B, Pad X, Pad Y), and comprising a first interconnect-under-test (32;50) between a first electrical contact element (31a; Pad A) and a second electrical contact element (31b; Pad B), and furthermore comprising a second interconnect-under-test (40;51) between a third electrical contact element (31c; Pad X) and a fourth electrical contact element (31d; Pad Y); wherein the second interconnect-under-test (40;51) is connected to the first interconnect-under-test (32;50) via an electrical component (33; C), the method comprising testing a first signal path in the semiconductor die for manufacturing defects, the first signal path comprising a first part of the first interconnect-under-test (32;50) and a first deviation path from the first interconnect-under-test (32;50) over the electrical component (33; C) to the third electrical contact element (31c; Pad X), thus obtaining first test results, said testing the first signal path comprising probing on the first electrical contact element (31a; Pad A) and the third electrical contact element (31c; Pad X); and testing a second signal path in the semiconductor die for manufacturing defects, the second signal path comprising a second part of the first interconnect-under-test (32;50) and a second deviation path from the first interconnect-under-test (32;50) over the electrical component (33; C) to the fourth electrical contact element (31d; Pad Y), thus obtaining second test results, said testing the second signal path comprising probing on the second electrical contact element (31b; Pad B) and the fourth electrical contact element (31d; Pad Y), wherein the first and the second part of the first interconnect-under-test together form the first interconnect-under-test (32;50); the method further comprising: from the first and second test results deciding whether or not the first interconnect-under-test (32;50) suffers from manufacturing defects, from the first and second test results deciding whether or not the second interconnect-under-test (40; 51) suffers from manufacturing defects, wherein said electrical component (33; C) is a circuit having an electrical characteristic for being measured; wherein said first interconnect-under-test and said second interconnect-under-test are both vertical interconnects having the first and third electrical contact elements provided on the same side of the semiconductor die that is an opposite side of the side on which the second and fourth electrical contact elements are provided, or wherein said first interconnect-under-test and said second interconnect-under-test are both horizontal interconnects having the first, second, third and fourth electrical contact elements provided on the same side of the semiconductor die. from the first and second test results deciding whether or not the first interconnect-under-test (32;50) suffers from manufacturing defects, from the first and second test results deciding whether or not the second interconnect-under-test (40; 51) suffers from manufacturing defects, wherein said electrical component (33; C) is a circuit having an electrical characteristic for being measured; wherein said first interconnect-under-test and said second interconnect-under-test are both vertical interconnects having the first and third electrical contact elements provided on the same side of the semiconductor die that is an opposite side of the side on which the second and fourth electrical contact elements are provided, are both horizontal interconnects having the first, second, third and fourth electrical contact elements provided on the same side of the semiconductor die.