A power converter apparatus comprising: a substrate on which switching elements (Q, Q1 to Q6) are mounted; a positive terminal interconnection member and a negative terminal interconnection member placed on the substrate, wherein the interconnection members (27, 28) each have a plate-like main body (27a, 28a) that is located above and parallel to the substrate, and wherein the main bodies (27a, 28a) of the interconnection members are stacked to be close to each other while being electrically insulated from each other; and a capacitor having a positive terminal connected to the main body of the positive terminal interconnection member and a negative terminal connected to the main body of the negative terminal interconnection member, characterized in that each of the positive terminal interconnection member and the negative terminal interconnection member further includes a plate-like extension (27b, 28b) that extends from the corresponding main body (27a, 28a) toward the substrate while being parallel to and close to each other and being stacked on each other with an insulation member therebetween, and a terminal portion (27c, 28c) that is bent from the lower ends of the extension to extend parallel with the main bodies and is joined to the substrate; the substrate has a circuit pattern on which a plurality of semiconductor chips including the switching elements (Q, Q1 to Q6) are mounted, and wherein each terminal portion (27c, 28c) has at its distal end a joint portion (27c1, 28c1) that is joined to the circuit pattern; the joint portions (27c1, 28c1) on the same side of the interconnection members (27, 28) in the widthwise direction are located on a single line; the terminal portions (27c, 28c) are bent such that the cross-sectional shape of each interconnection member (27, 28) is cranked between the main body (27a, 28a) and the joint portion (27c1, 28c1); and wherein each joint portion (27c1, 28c1) is joined to the circuit pattern, so as to be spaced from the semiconductor chips by equal distances on the single line. a substrate on which switching elements (Q, Q1 to Q6) are mounted; a positive terminal interconnection member and a negative terminal interconnection member placed on the substrate, wherein the interconnection members (27, 28) each have a plate-like main body (27a, 28a) that is located above and parallel to the substrate, and wherein the main bodies (27a, 28a) of the interconnection members are stacked to be close to each other while being electrically insulated from each other; and a capacitor having a positive terminal connected to the main body of the positive terminal interconnection member and a negative terminal connected to the main body of the negative terminal interconnection member, characterized in that each of the positive terminal interconnection member and the negative terminal interconnection member further includes a plate-like extension (27b, 28b) that extends from the corresponding main body (27a, 28a) toward the substrate while being parallel to and close to each other and being stacked on each other with an insulation member therebetween, and a terminal portion (27c, 28c) that is bent from the lower ends of the extension to extend parallel with the main bodies and is joined to the substrate; a plate-like extension (27b, 28b) that extends from the corresponding main body (27a, 28a) toward the substrate while being parallel to and close to each other and being stacked on each other with an insulation member therebetween, and a terminal portion (27c, 28c) that is bent from the lower ends of the extension to extend parallel with the main bodies and is joined to the substrate; the substrate has a circuit pattern on which a plurality of semiconductor chips including the switching elements (Q, Q1 to Q6) are mounted, and wherein each terminal portion (27c, 28c) has at its distal end a joint portion (27c1, 28c1) that is joined to the circuit pattern; the joint portions (27c1, 28c1) on the same side of the interconnection members (27, 28) in the widthwise direction are located on a single line; the terminal portions (27c, 28c) are bent such that the cross-sectional shape of each interconnection member (27, 28) is cranked between the main body (27a, 28a) and the joint portion (27c1, 28c1); and wherein each joint portion (27c1, 28c1) is joined to the circuit pattern, so as to be spaced from the semiconductor chips by equal distances on the single line.