A self-locking detection circuit, characterized in that the self-locking detection circuit comprises a self-locking circuit, a detection circuit, a power-on delay circuit, and an anti-reverse diode, wherein the self-locking circuit comprises a three-terminal transistor group, a first input end, a second input end, a first current-limiting resistor, and a second current-limiting resistor, the three-terminal transistor group comprising a first transistor and a second transistor, the detection circuit comprises a pull-up resistor, a bleeder resistor, and a third transistor, the power-on delay circuit comprises a first resistor and a capacitor, and a gate of the first transistor is electrically connected with a drain of the second transistor via the first current-limiting resistor, a drain of the first transistor is electrically connected with a gate of the second transistor via the second current-limiting resistor, a source of the first transistor is electrically connected with a power terminal via the first resistor, and a source of the second transistor is grounded; a first end of the pull-up resistor is electrically connected with the gate of the first transistor via the first current-limiting resistor, and a second end of the pull-up resistor is configured to be electrically connected with the power terminal; a gate of the third transistor is electrically connected with the drain of the second transistor, a drain of the third transistor is configured to be electrically connected with the power terminal, and a source of the third transistor is grounded via the bleeder resistor; the first end of the pull-up resistor is provided with a first terminal for signal output, and the source of the third transistor is provided with a second terminal for signal output; the first input end is provided between the gate of the third transistor and the first terminal, the first input end is electrically connected with a cathode of the anti-reverse diode, and the first input end is configured to receive a level signal output from a controller; the second input end is electrically connected with the drain of the first transistor, and the second input end is electrically connected with the gate of the second transistor via the second current-limiting resistor; an anode of the anti-reverse diode is electrically connected with the gate of the third transistor, and the anode of the anti-reverse diode is electrically connected with the gate of the first transistor via the first current-limiting resistor; and one end of the capacitor is electrically connected with the source of the first transistor, and the other end of the capacitor is grounded. the self-locking circuit comprises a three-terminal transistor group, a first input end, a second input end, a first current-limiting resistor, and a second current-limiting resistor, the three-terminal transistor group comprising a first transistor and a second transistor, the detection circuit comprises a pull-up resistor, a bleeder resistor, and a third transistor, the power-on delay circuit comprises a first resistor and a capacitor, and a gate of the first transistor is electrically connected with a drain of the second transistor via the first current-limiting resistor, a drain of the first transistor is electrically connected with a gate of the second transistor via the second current-limiting resistor, a source of the first transistor is electrically connected with a power terminal via the first resistor, and a source of the second transistor is grounded; a first end of the pull-up resistor is electrically connected with the gate of the first transistor via the first current-limiting resistor, and a second end of the pull-up resistor is configured to be electrically connected with the power terminal; a gate of the third transistor is electrically connected with the drain of the second transistor, a drain of the third transistor is configured to be electrically connected with the power terminal, and a source of the third transistor is grounded via the bleeder resistor; the first end of the pull-up resistor is provided with a first terminal for signal output, and the source of the third transistor is provided with a second terminal for signal output; the first input end is provided between the gate of the third transistor and the first terminal, the first input end is electrically connected with a cathode of the anti-reverse diode, and the first input end is configured to receive a level signal output from a controller; the second input end is electrically connected with the drain of the first transistor, and the second input end is electrically connected with the gate of the second transistor via the second current-limiting resistor; an anode of the anti-reverse diode is electrically connected with the gate of the third transistor, and the anode of the anti-reverse diode is electrically connected with the gate of the first transistor via the first current-limiting resistor; and one end of the capacitor is electrically connected with the source of the first transistor, and the other end of the capacitor is grounded.