A gain amplifier comprising: a differential amplifier (140; 320) comprising feedback capacitors (130; 330); a switched input stage having a first and second output coupled with the differential amplifier, comprising: first and second capacitors (110; 310, 312), a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches (102, 104; 302, 304) controlled by a first clock signal (Φ) to connect the first terminals of the first capacitor (110a; 310a) with said first or second input, respectively and to connect the first terminals of the second capacitors (110b; 310b) with said second and first input, respectively; and a second plurality of switches (120, 122; 320, 322) controlled by a phase shifted clock signal to connect the second terminal of the first capacitor (110a, 310a) with a first or second input of the differential amplifier (140; 320) and connecting the second terminal of the second capacitor (110b, 310b) with the second or first input of the differential amplifier (140; 320), wherein the phase shifted signal is the clock signal (Φ) shifted by 1⁄4 period, first and second reset switches (150; 350) coupled in parallel to a first and second feedback capacitor (130; 330); characterized in that the first and second reset switches (150; 350) are controlled by a control signal having twice the frequency of the clock signal (Φ). a differential amplifier (140; 320) comprising feedback capacitors (130; 330); a switched input stage having a first and second output coupled with the differential amplifier, comprising: first and second capacitors (110; 310, 312), a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches (102, 104; 302, 304) controlled by a first clock signal (Φ) to connect the first terminals of the first capacitor (110a; 310a) with said first or second input, respectively and to connect the first terminals of the second capacitors (110b; 310b) with said second and first input, respectively; and a second plurality of switches (120, 122; 320, 322) controlled by a phase shifted clock signal to connect the second terminal of the first capacitor (110a, 310a) with a first or second input of the differential amplifier (140; 320) and connecting the second terminal of the second capacitor (110b, 310b) with the second or first input of the differential amplifier (140; 320), wherein the phase shifted signal is the clock signal (Φ) shifted by 1⁄4 period, first and second capacitors (110; 310, 312), a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches (102, 104; 302, 304) controlled by a first clock signal (Φ) to connect the first terminals of the first capacitor (110a; 310a) with said first or second input, respectively and to connect the first terminals of the second capacitors (110b; 310b) with said second and first input, respectively; and a second plurality of switches (120, 122; 320, 322) controlled by a phase shifted clock signal to connect the second terminal of the first capacitor (110a, 310a) with a first or second input of the differential amplifier (140; 320) and connecting the second terminal of the second capacitor (110b, 310b) with the second or first input of the differential amplifier (140; 320), wherein the phase shifted signal is the clock signal (Φ) shifted by 1⁄4 period, first and second reset switches (150; 350) coupled in parallel to a first and second feedback capacitor (130; 330); characterized in that the first and second reset switches (150; 350) are controlled by a control signal having twice the frequency of the clock signal (Φ).