A low leakage switch comprising: a first transistor being a sampling transistor; a second transistor having one end of its channel connected to an input node and the other end of its channel connected to a backgate of the first transistor; and a third transistor one end of its channel connected to said input node and the other end of its channel connected to a backgate of the second transistor; means for activating the first, second and third transistors; and a pre-sampling capacitor, characterized in that the low leakage switch further comprises: a pre-sampling transistor (P0, P1CASC), wherein the pre-sampling transistor has one end of its channel connected to said input node and the other end of its channel connected to the pre-sampling capacitor, and wherein said one end of the channel of the first transistor is connected to said other end of the channel of the pre-sampling transistor (P0, P1CASC) and to the pre-sampling capacitor, wherein said means for activating are also configured to activate said pre-sampling transistor, said means being able to activate the first transistor after activating the pre-sampling (P0, P1CASC), second and third transistors such that the voltage level of the backgate of the first transistor is adjusted before the first transistor is activated. a first transistor being a sampling transistor; a second transistor having one end of its channel connected to an input node and the other end of its channel connected to a backgate of the first transistor; and a third transistor one end of its channel connected to said input node and the other end of its channel connected to a backgate of the second transistor; means for activating the first, second and third transistors; and a pre-sampling capacitor, characterized in that the low leakage switch further comprises: a pre-sampling transistor (P0, P1CASC), wherein the pre-sampling transistor has one end of its channel connected to said input node and the other end of its channel connected to the pre-sampling capacitor, and wherein said one end of the channel of the first transistor is connected to said other end of the channel of the pre-sampling transistor (P0, P1CASC) and to the pre-sampling capacitor, wherein said means for activating are also configured to activate said pre-sampling transistor, said means being able to activate the first transistor after activating the pre-sampling (P0, P1CASC), second and third transistors such that the voltage level of the backgate of the first transistor is adjusted before the first transistor is activated. a pre-sampling transistor (P0, P1CASC), wherein the pre-sampling transistor has one end of its channel connected to said input node and the other end of its channel connected to the pre-sampling capacitor, and wherein said one end of the channel of the first transistor is connected to said other end of the channel of the pre-sampling transistor (P0, P1CASC) and to the pre-sampling capacitor, wherein said means for activating are also configured to activate said pre-sampling transistor, said means being able to activate the first transistor after activating the pre-sampling (P0, P1CASC), second and third transistors such that the voltage level of the backgate of the first transistor is adjusted before the first transistor is activated.