A display substrate, comprising: a base substrate comprising a display area and a peripheral area located on at least a first side of the display area; a plurality of pixel units arranged in an array in a first direction and a second direction in the display area of the base substrate, wherein each of the pixel units comprises a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit, and the light-emitting device comprises a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode; a first power trace located in the peripheral area and electrically connected to the first electrode; a second power trace located in the peripheral area and electrically connected to the second electrode; a planarization layer, wherein at least a portion of planarization layer is located in the peripheral area; and a frame sealant arranged on the base substrate, wherein the peripheral area comprises a first peripheral area on a side of the frame sealant close to the display area and a second peripheral area on a side of the frame sealant away from the display area, the first side of the display area is a signal input side, and the first power trace and the second power trace are both located in the first peripheral area and on the signal input side, and wherein an orthographic projection of the planarization layer on the base substrate at least partially overlaps an orthographic projection of each of the first power trace and the second power trace on the base substrate, the first power trace and the second power trace are located in different layers, and a portion of the planarization layer is located between the first power trace and the second power trace; wherein the planarization layer comprises a first portion in the first peripheral area and a second portion in the second peripheral area, an orthographic projection of the first portion of the planarization layer on the base substrate at least partially overlaps the orthographic projection of each of the first power trace and the second power trace on the base substrate, and the first portion of the planarization layer is located between the first power trace and the second power trace; and wherein the display substrate further comprises a plurality of pads on the signal input side and in the peripheral area, characterized in that the second portion of the planarization layer is adjacent to the plurality of pads, and is located on a side of the plurality of pads close to the frame sealant. a base substrate comprising a display area and a peripheral area located on at least a first side of the display area; a plurality of pixel units arranged in an array in a first direction and a second direction in the display area of the base substrate, wherein each of the pixel units comprises a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit, and the light-emitting device comprises a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode; a first power trace located in the peripheral area and electrically connected to the first electrode; a second power trace located in the peripheral area and electrically connected to the second electrode; a planarization layer, wherein at least a portion of planarization layer is located in the peripheral area; and a frame sealant arranged on the base substrate, wherein the peripheral area comprises a first peripheral area on a side of the frame sealant close to the display area and a second peripheral area on a side of the frame sealant away from the display area, the first side of the display area is a signal input side, and the first power trace and the second power trace are both located in the first peripheral area and on the signal input side, and wherein an orthographic projection of the planarization layer on the base substrate at least partially overlaps an orthographic projection of each of the first power trace and the second power trace on the base substrate, the first power trace and the second power trace are located in different layers, and a portion of the planarization layer is located between the first power trace and the second power trace; wherein the planarization layer comprises a first portion in the first peripheral area and a second portion in the second peripheral area, an orthographic projection of the first portion of the planarization layer on the base substrate at least partially overlaps the orthographic projection of each of the first power trace and the second power trace on the base substrate, and the first portion of the planarization layer is located between the first power trace and the second power trace; and wherein the display substrate further comprises a plurality of pads on the signal input side and in the peripheral area, characterized in that the second portion of the planarization layer is adjacent to the plurality of pads, and is located on a side of the plurality of pads close to the frame sealant.