A method for manufacturing a Fin-shaped Field Effect Transistor, comprising the steps of: • Providing a structure having: i. A semiconductor substrate, ii. A layer of dielectric material overlaying said substrate and comprising at least one trench of depth h extending down to said substrate, and iii. A filling comprising one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, filling in said at least one trench and forming a fin of height h within each of said at least one trench, thereby providing at least one fin, said at least one fin having side walls, a top surface, a drain region and a source region, • Removing said layer of dielectric material in order to provide: i. at least one fin core structure having free side walls and a free top surface, and ii. a recess exposing a substrate surface area around said at least one fin core structure, • Overlaying a coating onto said at least one fin core structure, thereby providing at least one coated fin having said top surface, and all side walls on the total height h, coated with said coating, wherein said coating comprises one or more metal oxide layers, at least one of which comprising aluminium, wherein said coating has a thickness of from 1 to 10 nm, • Filling in said recess so as to cover the exposed substrate surface area and the side walls of the at least one coated fin up to a certain height h' lower than h with a dielectric material, • Covering the top surface and the exposed sidewalls of the at least one coated fin with a gate electrode. • Providing a structure having: i. A semiconductor substrate, ii. A layer of dielectric material overlaying said substrate and comprising at least one trench of depth h extending down to said substrate, and iii. A filling comprising one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, filling in said at least one trench and forming a fin of height h within each of said at least one trench, thereby providing at least one fin, said at least one fin having side walls, a top surface, a drain region and a source region, i. A semiconductor substrate, ii. A layer of dielectric material overlaying said substrate and comprising at least one trench of depth h extending down to said substrate, and iii. A filling comprising one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, filling in said at least one trench and forming a fin of height h within each of said at least one trench, thereby providing at least one fin, said at least one fin having side walls, a top surface, a drain region and a source region, • Removing said layer of dielectric material in order to provide: i. at least one fin core structure having free side walls and a free top surface, and ii. a recess exposing a substrate surface area around said at least one fin core structure, i. at least one fin core structure having free side walls and a free top surface, and ii. a recess exposing a substrate surface area around said at least one fin core structure, • Overlaying a coating onto said at least one fin core structure, thereby providing at least one coated fin having said top surface, and all side walls on the total height h, coated with said coating, wherein said coating comprises one or more metal oxide layers, at least one of which comprising aluminium, wherein said coating has a thickness of from 1 to 10 nm, • Filling in said recess so as to cover the exposed substrate surface area and the side walls of the at least one coated fin up to a certain height h' lower than h with a dielectric material, • Covering the top surface and the exposed sidewalls of the at least one coated fin with a gate electrode.