An apparatus having a plurality of serially connected devices including at least first and second devices, the first device having a memory (950, 1050), an input for receiving an input signal (SI, SIP) and an output for outputting a device output signal, the second device having an input responsive to the device output signal from the first device, the input of the first device being configured to commonly receive access command information and memory location information at different times as the input signal, the first device further having: a first control input configured to receive a first input enable signal; characterized by: a second control input configured to receive a first output enable signal; and control circuitry (900, 1000, 1100) configured to: receive the input signal in response to the input enable signal, produce an output control signal in response to either one of the first input enable signal and the first output enable signal, enable an output buffer in response to said output control signal, and provide an output signal via said output buffer to the output in response to the received input signal and the output control signal being at a first logic level, the output signal including, in response to a selection signal (ID_MATCH): the received input signal, or data read from the memory in accordance with the memory location information by the control circuitry (900, 1000, 1100) in a case of the access command being for data reading. a first control input configured to receive a first input enable signal; a second control input configured to receive a first output enable signal; and control circuitry (900, 1000, 1100) configured to: receive the input signal in response to the input enable signal, produce an output control signal in response to either one of the first input enable signal and the first output enable signal, enable an output buffer in response to said output control signal, and provide an output signal via said output buffer to the output in response to the received input signal and the output control signal being at a first logic level, the output signal including, in response to a selection signal (ID_MATCH): the received input signal, or data read from the memory in accordance with the memory location information by the control circuitry (900, 1000, 1100) in a case of the access command being for data reading. receive the input signal in response to the input enable signal, produce an output control signal in response to either one of the first input enable signal and the first output enable signal, enable an output buffer in response to said output control signal, and provide an output signal via said output buffer to the output in response to the received input signal and the output control signal being at a first logic level, the output signal including, in response to a selection signal (ID_MATCH): the received input signal, or data read from the memory in accordance with the memory location information by the control circuitry (900, 1000, 1100) in a case of the access command being for data reading. the received input signal, or data read from the memory in accordance with the memory location information by the control circuitry (900, 1000, 1100) in a case of the access command being for data reading.