A semiconductor device comprising: a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type neighbouring to said first semiconductor layer, a third semiconductor layer of said first conductive type neighbouring to said second semiconductor layer, a plurality of insulated gates passing through said third semiconductor layer and reaching said second semiconductor layer, a first area and a second area which are areas between said neighbouring insulated gates and neighbouring to each other, a fourth semiconductor layer of said second conductive type in contact with said insulated gates in said third semiconductor layer in said first area, a first main electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer in said first area, and a second main electrode electrically connected to said first semiconductor layer, wherein: an interval between said neighbouring insulated gate in said second area is formed to be larger than an interval between said neighbouring insulated gates in said first area, said third semiconductor layer is formed continuously in said second area and a groove which is a contact hole is formed, at the bottom of said contact hole, a p+ layer whose impurity density is higher than that of said third semiconductor layer is formed, characterized in that said third semiconductor layer is electrically connected to said first main electrode via said p+ layer; said p+ layer is disposed between the third semiconductor layer and the contact hole said interval between said neighbouring insulated gates in said first area is La, said interval between said neighbouring insulated gates in said second area is Lb, and La ≤ 5 μm and Lb/La > 1. a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type neighbouring to said first semiconductor layer, a third semiconductor layer of said first conductive type neighbouring to said second semiconductor layer, a plurality of insulated gates passing through said third semiconductor layer and reaching said second semiconductor layer, a first area and a second area which are areas between said neighbouring insulated gates and neighbouring to each other, a fourth semiconductor layer of said second conductive type in contact with said insulated gates in said third semiconductor layer in said first area, a first main electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer in said first area, and a second main electrode electrically connected to said first semiconductor layer, wherein: an interval between said neighbouring insulated gate in said second area is formed to be larger than an interval between said neighbouring insulated gates in said first area, said third semiconductor layer is formed continuously in said second area and a groove which is a contact hole is formed, at the bottom of said contact hole, a p+ layer whose impurity density is higher than that of said third semiconductor layer is formed, characterized in that said third semiconductor layer is electrically connected to said first main electrode via said p+ layer; said p+ layer is disposed between the third semiconductor layer and the contact hole said interval between said neighbouring insulated gates in said first area is La, said interval between said neighbouring insulated gates in said second area is Lb, and La ≤ 5 μm and Lb/La > 1. an interval between said neighbouring insulated gate in said second area is formed to be larger than an interval between said neighbouring insulated gates in said first area, said third semiconductor layer is formed continuously in said second area and a groove which is a contact hole is formed, at the bottom of said contact hole, a p+ layer whose impurity density is higher than that of said third semiconductor layer is formed, characterized in that said third semiconductor layer is electrically connected to said first main electrode via said p+ layer; said p+ layer is disposed between the third semiconductor layer and the contact hole said interval between said neighbouring insulated gates in said first area is La, said interval between said neighbouring insulated gates in said second area is Lb, and La ≤ 5 μm and Lb/La > 1.