An electronic device for data processing comprising: a Central Processing Unit for data processing, a Closely Coupled Memory for storing a first set of data and instructions, an external memory system for storing a second set of data and instructions, and a first clock unit for receiving a main clock signal having a main clock frequency and converting said main clock signal into a first clock signal for at least the Central Processing Unit and Closely Coupled Memory, the Central Processing Unit, Closely Coupled Memory and the first clock unit being integrated in a single chip, the Central Processing Unit being connected to the Closely Coupled Memory via an internal memory bus, the external memory system being external to the single chip and connected to an external memory bus for at least transmitting data to said Closely Coupled Memory, the electronic device further comprising a second clock unit arranged for receiving said main clock signal and converting said main clock signal into a second clock signal for the external memory system, characterized in that the first clock signal has a first clock frequency and the second clock signal has a second clock frequency, the second clock frequency being higher than said first clock frequency, and wherein the device is configured to switch per time unit the external memory system for an active period T active in an active state to retrieve from the external memory system a predetermined amount of data in a burst and for a standby period T standby in a standby state between two subsequent bursts, to retrieve the predetermined amount of data per time unit from the external memory system in bursts. a Central Processing Unit for data processing, a Closely Coupled Memory for storing a first set of data and instructions, an external memory system for storing a second set of data and instructions, and a first clock unit for receiving a main clock signal having a main clock frequency and converting said main clock signal into a first clock signal for at least the Central Processing Unit and Closely Coupled Memory, the Central Processing Unit, Closely Coupled Memory and the first clock unit being integrated in a single chip, the Central Processing Unit being connected to the Closely Coupled Memory via an internal memory bus, the external memory system being external to the single chip and connected to an external memory bus for at least transmitting data to said Closely Coupled Memory, the electronic device further comprising a second clock unit arranged for receiving said main clock signal and converting said main clock signal into a second clock signal for the external memory system, characterized in that the first clock signal has a first clock frequency and the second clock signal has a second clock frequency, the second clock frequency being higher than said first clock frequency, and wherein the device is configured to switch per time unit the external memory system for an active period T active in an active state to retrieve from the external memory system a predetermined amount of data in a burst and for a standby period T standby in a standby state between two subsequent bursts, to retrieve the predetermined amount of data per time unit from the external memory system in bursts.