Decoder circuitry for an input channel having a first data rate, a codeword on said input channel including a plurality of symbols, wherein: said circuitry includes both an option to provide a first output channel having said first data rate and an option to provide a plurality of second output channels having data rates less than said first data rate; said decoder circuitry comprises syndrome calculation circuitry (310, 400), polynomial calculation circuitry, and search-and-correct circuitry; and said syndrome calculation circuitry comprises: a plurality of finite-field multipliers corresponding in number to said plurality of symbols for multiplying said symbols by a power of a root of said finite field, each respective multiplier in said plurality of multipliers, other than a first multiplier, multiplying a respective symbol in said plurality of symbols by a higher power of said root than an adjacent multiplier in said plurality of multipliers, first-level adder circuitry for adding outputs of a number of groups of multipliers in said plurality of multipliers, a second-level adder for adding outputs of said first-level adder circuitry, a first accumulator for accumulating outputs of said second-level adder as syndromes of said first output channel, a plurality of second accumulators equal in number to said groups of multipliers for accumulating outputs of said first-level adder circuitry, and a respective scaling multiplier for all but one of said second accumulators, whereby an output of each of said second accumulators is a syndrome of one of said second output channels. said circuitry includes both an option to provide a first output channel having said first data rate and an option to provide a plurality of second output channels having data rates less than said first data rate; said decoder circuitry comprises syndrome calculation circuitry (310, 400), polynomial calculation circuitry, and search-and-correct circuitry; and said syndrome calculation circuitry comprises: a plurality of finite-field multipliers corresponding in number to said plurality of symbols for multiplying said symbols by a power of a root of said finite field, each respective multiplier in said plurality of multipliers, other than a first multiplier, multiplying a respective symbol in said plurality of symbols by a higher power of said root than an adjacent multiplier in said plurality of multipliers, first-level adder circuitry for adding outputs of a number of groups of multipliers in said plurality of multipliers, a second-level adder for adding outputs of said first-level adder circuitry, a first accumulator for accumulating outputs of said second-level adder as syndromes of said first output channel, a plurality of second accumulators equal in number to said groups of multipliers for accumulating outputs of said first-level adder circuitry, and a respective scaling multiplier for all but one of said second accumulators, whereby an output of each of said second accumulators is a syndrome of one of said second output channels. a plurality of finite-field multipliers corresponding in number to said plurality of symbols for multiplying said symbols by a power of a root of said finite field, each respective multiplier in said plurality of multipliers, other than a first multiplier, multiplying a respective symbol in said plurality of symbols by a higher power of said root than an adjacent multiplier in said plurality of multipliers, first-level adder circuitry for adding outputs of a number of groups of multipliers in said plurality of multipliers, a second-level adder for adding outputs of said first-level adder circuitry, a first accumulator for accumulating outputs of said second-level adder as syndromes of said first output channel, a plurality of second accumulators equal in number to said groups of multipliers for accumulating outputs of said first-level adder circuitry, and a respective scaling multiplier for all but one of said second accumulators, whereby an output of each of said second accumulators is a syndrome of one of said second output channels.