An image processing system comprising: a processor unit; a hardware accelerator component; and a non-transitory computer-readable medium or media comprising one or more sequences of instructions which, when executed by the processor unit, causes steps to be performed comprising: receiving a pair of images of a scene, in which the pair of images comprises a first image and a second image; performing depth map inference using the pair of images and a trained neural network model that comprises a plurality of operations, in which at least some of the operations of the plurality of operations of the trained neural network model are performed by the hardware accelerator component that is communicatively coupled to the processor unit, wherein the pair of images are used as an input of the trained neural network model; and outputting, by the trained neural network model, a depth map comprising distance information to surfaces in the scene; and the hardware accelerator component being configured to perform at least some of the operations of the trained neural network model using a different bit representation than that used by the processor unit; wherein the processor unit and the hardware accelerator component cooperate, for the pair of images, to run the trained neural network model, including the following: the processor unit controls a workflow of the trained neural network and sequentially assigns one or more layers' computation task to the hardware accelerator component, wherein the hardware accelerator component fetches data and layer parameters from the processor unit, performs the layer's computation task and returns processed data to the processor unit; wherein the neural network is trained using one or more training workstations, wherein the one or more training workstations use a different bit representation than the hardware accelerator component; and wherein the trained model is fine-tuned for deployment under use of the hardware accelerator component, the fine-tuning using a bit representation conversion to simulate an operation that will be performed by the hardware accelerator component when the trained neural network is deployed. a processor unit; a hardware accelerator component; and a non-transitory computer-readable medium or media comprising one or more sequences of instructions which, when executed by the processor unit, causes steps to be performed comprising: receiving a pair of images of a scene, in which the pair of images comprises a first image and a second image; performing depth map inference using the pair of images and a trained neural network model that comprises a plurality of operations, in which at least some of the operations of the plurality of operations of the trained neural network model are performed by the hardware accelerator component that is communicatively coupled to the processor unit, wherein the pair of images are used as an input of the trained neural network model; and outputting, by the trained neural network model, a depth map comprising distance information to surfaces in the scene; and receiving a pair of images of a scene, in which the pair of images comprises a first image and a second image; performing depth map inference using the pair of images and a trained neural network model that comprises a plurality of operations, in which at least some of the operations of the plurality of operations of the trained neural network model are performed by the hardware accelerator component that is communicatively coupled to the processor unit, wherein the pair of images are used as an input of the trained neural network model; and outputting, by the trained neural network model, a depth map comprising distance information to surfaces in the scene; and the hardware accelerator component being configured to perform at least some of the operations of the trained neural network model using a different bit representation than that used by the processor unit; wherein the processor unit and the hardware accelerator component cooperate, for the pair of images, to run the trained neural network model, including the following: the processor unit controls a workflow of the trained neural network and sequentially assigns one or more layers' computation task to the hardware accelerator component, wherein the hardware accelerator component fetches data and layer parameters from the processor unit, performs the layer's computation task and returns processed data to the processor unit; wherein the neural network is trained using one or more training workstations, wherein the one or more training workstations use a different bit representation than the hardware accelerator component; and wherein the trained model is fine-tuned for deployment under use of the hardware accelerator component, the fine-tuning using a bit representation conversion to simulate an operation that will be performed by the hardware accelerator component when the trained neural network is deployed.