Apparatus for performing a computer-implemented method for building a circuit layout from a MOS transistor circuit schematic, the apparatus comprising: a serial MOS element provider configured for providing a set of serial MOS elements (4, 4a, 4b), comprising: a transistor functional unit provider configured for providing a set of transistor functional units (10, 10a, 10b), wherein each transistor functional unit (10a, 10b) of the set of transistor functional units comprises a representation of one transistor finger having a gate area or of a plurality of serially connected transistor fingers having connected gate areas, wherein each transistor finger comprises a gate channel area with at least a drain area, a source area and the gate area; and a serial MOS element generator configured for generating at least one serial MOS element having at least two serially connected transistor functional units, wherein the transistor functional units of the serial MOS element comprise the same gate width; a circuit builder configured for receiving the at least one serial MOS element and for building the MOS transistor circuit schematic using one or multiple instances of the at least one serial MOS element, wherein the circuit builder is further configured for building the MOS transistor circuit schematic based on the layout parameters of each instance of the multiple instances of the at least one serial MOS element; and a translator for translating the MOS transistor circuit schematic into the circuit layout using the serial MOS element's layouts; wherein the serial MOS element generator is configured to generate the at least one serial MOS element such that an instance of the at least one serial MOS element is directly abuttable to a further instance of each of the at least one serial MOS elements wherein directly abutted instances of serial MOS elements are electrically connected by forming joint diffusion areas by forming a joint doping area representing a drain or a source connection of the MOS transistor. a serial MOS element provider configured for providing a set of serial MOS elements (4, 4a, 4b), comprising: a transistor functional unit provider configured for providing a set of transistor functional units (10, 10a, 10b), wherein each transistor functional unit (10a, 10b) of the set of transistor functional units comprises a representation of one transistor finger having a gate area or of a plurality of serially connected transistor fingers having connected gate areas, wherein each transistor finger comprises a gate channel area with at least a drain area, a source area and the gate area; and a serial MOS element generator configured for generating at least one serial MOS element having at least two serially connected transistor functional units, wherein the transistor functional units of the serial MOS element comprise the same gate width; a transistor functional unit provider configured for providing a set of transistor functional units (10, 10a, 10b), wherein each transistor functional unit (10a, 10b) of the set of transistor functional units comprises a representation of one transistor finger having a gate area or of a plurality of serially connected transistor fingers having connected gate areas, wherein each transistor finger comprises a gate channel area with at least a drain area, a source area and the gate area; and a serial MOS element generator configured for generating at least one serial MOS element having at least two serially connected transistor functional units, wherein the transistor functional units of the serial MOS element comprise the same gate width; a circuit builder configured for receiving the at least one serial MOS element and for building the MOS transistor circuit schematic using one or multiple instances of the at least one serial MOS element, wherein the circuit builder is further configured for building the MOS transistor circuit schematic based on the layout parameters of each instance of the multiple instances of the at least one serial MOS element; and a translator for translating the MOS transistor circuit schematic into the circuit layout using the serial MOS element's layouts; wherein the serial MOS element generator is configured to generate the at least one serial MOS element such that an instance of the at least one serial MOS element is directly abuttable to a further instance of each of the at least one serial MOS elements wherein directly abutted instances of serial MOS elements are electrically connected by forming joint diffusion areas by forming a joint doping area representing a drain or a source connection of the MOS transistor.