A tunable CMOS circuit comprising a CMOS element configured to receive an analogue input signal (V IN), and a tunable load (R1, R2) connected to the CMOS element and configured to set a switch point of the CMOS element, wherein the CMOS element is configured to output an output current (I 3), the output current (I 3) being largest when the analogue input signal (V IN) is equal to the switch point, wherein: the CMOS element comprises a first CMOS stage (M1, M2) and a second CMOS stage (M3, M4), the first CMOS stage (M1, M2) is configured to receive the analogue input signal (V IN) and to output a midpoint signal (V MID), and constitutes a CMOS inverter; the output of the first CMOS stage (M1, M2) is connected to an input of the second CMOS stage (M3, M4), characterized in that the second CMOS stage includes a CMOS inverter constituted by an NMOS transistor and a PMOS transistor serially connected and having their control gates both receiving the midpoint signal (Vmid), the CMOS inverter configured to draw a current (I 2) at a source of the PMOS transistor which is equal or proportional to the output current (I out) and is largest when both PMOS and NMOS transistors are simultaneously maximally open due to the analogue input signal (Vin) being equal to the switch point. a CMOS element configured to receive an analogue input signal (V IN), and a tunable load (R1, R2) connected to the CMOS element and configured to set a switch point of the CMOS element, wherein the CMOS element is configured to output an output current (I 3), the output current (I 3) being largest when the analogue input signal (V IN) is equal to the switch point, wherein: the CMOS element comprises a first CMOS stage (M1, M2) and a second CMOS stage (M3, M4), the first CMOS stage (M1, M2) is configured to receive the analogue input signal (V IN) and to output a midpoint signal (V MID), and constitutes a CMOS inverter; the output of the first CMOS stage (M1, M2) is connected to an input of the second CMOS stage (M3, M4), characterized in that the second CMOS stage includes a CMOS inverter constituted by an NMOS transistor and a PMOS transistor serially connected and having their control gates both receiving the midpoint signal (Vmid), the CMOS inverter configured to draw a current (I 2) at a source of the PMOS transistor which is equal or proportional to the output current (I out) and is largest when both PMOS and NMOS transistors are simultaneously maximally open due to the analogue input signal (Vin) being equal to the switch point. the CMOS element comprises a first CMOS stage (M1, M2) and a second CMOS stage (M3, M4), the first CMOS stage (M1, M2) is configured to receive the analogue input signal (V IN) and to output a midpoint signal (V MID), and constitutes a CMOS inverter; the output of the first CMOS stage (M1, M2) is connected to an input of the second CMOS stage (M3, M4), characterized in that the second CMOS stage includes a CMOS inverter constituted by an NMOS transistor and a PMOS transistor serially connected and having their control gates both receiving the midpoint signal (Vmid), the CMOS inverter configured to draw a current (I 2) at a source of the PMOS transistor which is equal or proportional to the output current (I out) and is largest when both PMOS and NMOS transistors are simultaneously maximally open due to the analogue input signal (Vin) being equal to the switch point.