An uninterruptible power supply, comprising: an input configured to receive input power; an output; a power conversion circuit coupled with the input and the output and comprising an inverter; a bypass switch configured to couple the input to the output in a bypass mode of operation; said bypass switch including semiconductor controlled rectifiers (SCR 305A, 305B) arranged in an anti-parallel configuration; a controller coupled with the power conversion circuit, and the bypass switch; the controller being configured to control the two SCR's in alternate states throughout the input voltage waveform cycle to eliminate or substantially reduce backfeed from the inverter, by activating the bypass switch in a first configuration to provide the input power at the output during a first half of a cycle of an input voltage waveform; and by activating the bypass switch in a second configuration different from the first configuration to provide the input power at the output during a second half of the cycle of the input voltage waveform, characterized in that the controller comprises a phase lock loop circuit and a gate control circuit, the locked loop receiving as input a sensed input bypass voltage, and the phase lock loop circuit being configured to provide the input voltage waveform to the gate control circuit, and the gate control circuit being configured to activate the bypass switch in one of the first configuration and the second configuration based at least in part on the input voltage waveform, and in that the controller operates the inverter in parallel with the input power main lines during bypass operation, and controls the inverter to provide in a bypass mode of operation, at the input, a power factor correction approaching unity. an input configured to receive input power; an output; a power conversion circuit coupled with the input and the output and comprising an inverter; a bypass switch configured to couple the input to the output in a bypass mode of operation; said bypass switch including semiconductor controlled rectifiers (SCR 305A, 305B) arranged in an anti-parallel configuration; a controller coupled with the power conversion circuit, and the bypass switch; the controller being configured to control the two SCR's in alternate states throughout the input voltage waveform cycle to eliminate or substantially reduce backfeed from the inverter, by activating the bypass switch in a first configuration to provide the input power at the output during a first half of a cycle of an input voltage waveform; and by activating the bypass switch in a second configuration different from the first configuration to provide the input power at the output during a second half of the cycle of the input voltage waveform, characterized in that the controller comprises a phase lock loop circuit and a gate control circuit, the locked loop receiving as input a sensed input bypass voltage, and the phase lock loop circuit being configured to provide the input voltage waveform to the gate control circuit, and the gate control circuit being configured to activate the bypass switch in one of the first configuration and the second configuration based at least in part on the input voltage waveform, and in that the controller operates the inverter in parallel with the input power main lines during bypass operation, and controls the inverter to provide in a bypass mode of operation, at the input, a power factor correction approaching unity.