A test structure (100, 200, 400, 500, 600, 700, 800, 900) for directly measuring a stability of one or more static random access memory, SRAM, cells in an Integrated Circuit, IC, device, wherein the SRAM cell comprises a first inverter (136, 436, 536, 636, 736, 836), a second inverter (130, 430, 530, 630, 730, 830), a first access transistor and a second access transistor, the test structure (100, 200, 400, 500, 600, 700, 800, 900) comprising, for each SRAM cell (406, 506) of the one or more SRAM cells (106, 206, 206', 206", 300, 350, 406, 506, 606, 706, 806, 906): a first transmission gate, TG, (102, 104, 232,302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') for measuring a static noise margin, SNM, and electrically coupled to a first side of a cut off in the SRAM cell (406, 506); a second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') for measuring a static noise margin, SNM, and electrically coupled to a second side of the cut off; a first external pin electrically coupled to the first TG (102, 104, 232, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and a second external pin electrically coupled to the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'); a first internal node electrically coupled to the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and coupled to one side of one of the inverters, and a second internal node electrically coupled to the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and coupled to the other side of the one of the inverters, wherein the cut off is located between the inverters, wherein: the cut off provides an electrical open between the first side of the cut off and the second side of the cut off; and the first internal node is electrically coupled to the first external pin through the first TG and the second internal node is electrically coupled to the second external pin through the second TG. a first transmission gate, TG, (102, 104, 232,302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') for measuring a static noise margin, SNM, and electrically coupled to a first side of a cut off in the SRAM cell (406, 506); a second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') for measuring a static noise margin, SNM, and electrically coupled to a second side of the cut off; a first external pin electrically coupled to the first TG (102, 104, 232, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and a second external pin electrically coupled to the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904'); a first internal node electrically coupled to the first TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and coupled to one side of one of the inverters, and a second internal node electrically coupled to the second TG (102, 104, 302, 302', 304, 304', 402, 404, 502, 504, 602, 604, 702, 704, 802, 804, 902, 902', 904, 904') and coupled to the other side of the one of the inverters, wherein the cut off is located between the inverters, wherein: the cut off provides an electrical open between the first side of the cut off and the second side of the cut off; and the first internal node is electrically coupled to the first external pin through the first TG and the second internal node is electrically coupled to the second external pin through the second TG. the cut off provides an electrical open between the first side of the cut off and the second side of the cut off; and the first internal node is electrically coupled to the first external pin through the first TG and the second internal node is electrically coupled to the second external pin through the second TG.