An integrated circuit comprising: • a switch comprising: ∘ a gate; ∘ a first source/drain region (210") at a top surface of a semiconductor substrate of the switch; and ∘ a second source/drain region at the top surface of the semiconductor substrate, wherein the first source/drain region (210") and the second source/drain region are disposed on opposing sides of the gate; and • a first conductive line provided in a first direction over the switch, wherein at least a portion of the first conductive line is aligned with the gate, and wherein the first conductive line is electrically coupled to ground, wherein the first direction is a direction perpendicular to the top surface of the semiconductor substrate and extending away from the semiconductor substrate; • a second conductive line in a same layer as the first conductive line, wherein the second conductive line is electrically connected to the first source/drain region (210"); • a third conductive line in the same layer as the first conductive line, wherein the third conductive line is electrically connected to the second source/drain region, and wherein the first conductive line is disposed between the second conductive line and the third conductive line; • first interconnect features electrically connecting the second conductive line to an input line of the integrated circuit, wherein the input line is disposed in a first conductive line layer of the integrated circuit and the input line is arranged in the first direction higher than the second conductive line; and • second interconnect features electrically connecting the third conductive line to an output line of the integrated circuit, wherein the output line is disposed in a second conductive line layer of the integrated circuit and the output line is arranged in the first direction higher than the third conductive line. • a switch comprising: ∘ a gate; ∘ a first source/drain region (210") at a top surface of a semiconductor substrate of the switch; and ∘ a second source/drain region at the top surface of the semiconductor substrate, wherein the first source/drain region (210") and the second source/drain region are disposed on opposing sides of the gate; and ∘ a gate; ∘ a first source/drain region (210") at a top surface of a semiconductor substrate of the switch; and ∘ a second source/drain region at the top surface of the semiconductor substrate, wherein the first source/drain region (210") and the second source/drain region are disposed on opposing sides of the gate; and • a first conductive line provided in a first direction over the switch, wherein at least a portion of the first conductive line is aligned with the gate, and wherein the first conductive line is electrically coupled to ground, wherein the first direction is a direction perpendicular to the top surface of the semiconductor substrate and extending away from the semiconductor substrate; • a second conductive line in a same layer as the first conductive line, wherein the second conductive line is electrically connected to the first source/drain region (210"); • a third conductive line in the same layer as the first conductive line, wherein the third conductive line is electrically connected to the second source/drain region, and wherein the first conductive line is disposed between the second conductive line and the third conductive line; • first interconnect features electrically connecting the second conductive line to an input line of the integrated circuit, wherein the input line is disposed in a first conductive line layer of the integrated circuit and the input line is arranged in the first direction higher than the second conductive line; and • second interconnect features electrically connecting the third conductive line to an output line of the integrated circuit, wherein the output line is disposed in a second conductive line layer of the integrated circuit and the output line is arranged in the first direction higher than the third conductive line.