A compute device for caching data in a two-level memory, 2LM, comprising: a memory including: a volatile memory comprising one or more volatile memory devices; and a non-volatile memory comprising one or more non-volatile memory devices; and a processor configured to: determine a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices that the persistent memory address space is mapped to, wherein each non-volatile memory device contains the persistent 2LM data; configure the persistent memory address space to operate in a first mode of operation, wherein the first mode of operation is a persistent two-level memory, 2LM, mode for storing the persistent 2LM data in the non-volatile memory, in which application data written to the persistent memory address space is reusable across power cycles; and configure an operating system to cache accesses to the persistent memory address space in the volatile memory, characterised in that to configure the operating system comprises: allowing the operating system to use the persistent memory address space as a cached volatile memory operable in a second mode of operation, wherein the second mode of operation is a caching mode for caching the persistent 2LM data in the volatile memory, and converting from the first mode of operation for the persistent memory address space to the second mode of operation for the persistent memory address space. a memory including: a volatile memory comprising one or more volatile memory devices; and a non-volatile memory comprising one or more non-volatile memory devices; and a processor configured to: determine a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices that the persistent memory address space is mapped to, wherein each non-volatile memory device contains the persistent 2LM data; configure the persistent memory address space to operate in a first mode of operation, wherein the first mode of operation is a persistent two-level memory, 2LM, mode for storing the persistent 2LM data in the non-volatile memory, in which application data written to the persistent memory address space is reusable across power cycles; and configure an operating system to cache accesses to the persistent memory address space in the volatile memory, characterised in that to configure the operating system comprises: allowing the operating system to use the persistent memory address space as a cached volatile memory operable in a second mode of operation, wherein the second mode of operation is a caching mode for caching the persistent 2LM data in the volatile memory, and converting from the first mode of operation for the persistent memory address space to the second mode of operation for the persistent memory address space. determine a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices that the persistent memory address space is mapped to, wherein each non-volatile memory device contains the persistent 2LM data; configure the persistent memory address space to operate in a first mode of operation, wherein the first mode of operation is a persistent two-level memory, 2LM, mode for storing the persistent 2LM data in the non-volatile memory, in which application data written to the persistent memory address space is reusable across power cycles; and configure an operating system to cache accesses to the persistent memory address space in the volatile memory, characterised in that to configure the operating system comprises: allowing the operating system to use the persistent memory address space as a cached volatile memory operable in a second mode of operation, wherein the second mode of operation is a caching mode for caching the persistent 2LM data in the volatile memory, and converting from the first mode of operation for the persistent memory address space to the second mode of operation for the persistent memory address space. allowing the operating system to use the persistent memory address space as a cached volatile memory operable in a second mode of operation, wherein the second mode of operation is a caching mode for caching the persistent 2LM data in the volatile memory, and converting from the first mode of operation for the persistent memory address space to the second mode of operation for the persistent memory address space.