A sampling switch circuit, comprising: an input node (V IN), connected to receive an input voltage signal to be sampled; a sampling transistor (M S) comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node (V IN); a capacitor (C 1); a current source configured to cause a defined current (I D) to flow therethrough; and switching circuitry configured to alternate between a precharge configuration and an output configuration in dependence upon a clock signal, wherein: in the precharge configuration, the switching circuitry connects the capacitor (C 1) into a current path between said current source and a first voltage reference node (V DD1) to form a potential difference across the capacitor (C 1) which is dependent on the defined current (I D); in the output configuration, the switching circuitry connects the capacitor (C 1) between a second voltage reference node (V DD2) configured to provide a DC voltage signal and the gate terminal of the sampling transistor (M S) so that a voltage level applied at the gate terminal of the sampling transistor (M S) is dependent on the defined current (I D); the current source is a controllable current source and configured such that the defined current (I D) is a current dependent on a control signal; and the switching circuitry is configured, in the precharge configuration, to connect the gate terminal of the sampling transistor (M S) to a third voltage reference node so that a voltage level applied at the gate terminal of the sampling transistor (M S) in the precharge configuration is dependent on a voltage level provided at the third voltage reference node, the third reference voltage signal having a voltage level configured to cause the difference between voltage levels provided at the gate and source terminals of the sampling transistor (M S) to be less than the threshold voltage of the sampling transistor (M S). an input node (V IN), connected to receive an input voltage signal to be sampled; a sampling transistor (M S) comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node (V IN); a capacitor (C 1); a current source configured to cause a defined current (I D) to flow therethrough; and switching circuitry configured to alternate between a precharge configuration and an output configuration in dependence upon a clock signal, wherein: in the precharge configuration, the switching circuitry connects the capacitor (C 1) into a current path between said current source and a first voltage reference node (V DD1) to form a potential difference across the capacitor (C 1) which is dependent on the defined current (I D); in the output configuration, the switching circuitry connects the capacitor (C 1) between a second voltage reference node (V DD2) configured to provide a DC voltage signal and the gate terminal of the sampling transistor (M S) so that a voltage level applied at the gate terminal of the sampling transistor (M S) is dependent on the defined current (I D); the current source is a controllable current source and configured such that the defined current (I D) is a current dependent on a control signal; and the switching circuitry is configured, in the precharge configuration, to connect the gate terminal of the sampling transistor (M S) to a third voltage reference node so that a voltage level applied at the gate terminal of the sampling transistor (M S) in the precharge configuration is dependent on a voltage level provided at the third voltage reference node, the third reference voltage signal having a voltage level configured to cause the difference between voltage levels provided at the gate and source terminals of the sampling transistor (M S) to be less than the threshold voltage of the sampling transistor (M S). in the precharge configuration, the switching circuitry connects the capacitor (C 1) into a current path between said current source and a first voltage reference node (V DD1) to form a potential difference across the capacitor (C 1) which is dependent on the defined current (I D); in the output configuration, the switching circuitry connects the capacitor (C 1) between a second voltage reference node (V DD2) configured to provide a DC voltage signal and the gate terminal of the sampling transistor (M S) so that a voltage level applied at the gate terminal of the sampling transistor (M S) is dependent on the defined current (I D); the current source is a controllable current source and configured such that the defined current (I D) is a current dependent on a control signal; and the switching circuitry is configured, in the precharge configuration, to connect the gate terminal of the sampling transistor (M S) to a third voltage reference node so that a voltage level applied at the gate terminal of the sampling transistor (M S) in the precharge configuration is dependent on a voltage level provided at the third voltage reference node, the third reference voltage signal having a voltage level configured to cause the difference between voltage levels provided at the gate and source terminals of the sampling transistor (M S) to be less than the threshold voltage of the sampling transistor (M S).