Non-volatile resistive memory device comprising a plurality of memory cells and bit lines, word lines, source lines and form lines for addressing and biasing the memory cells, and a memory controller for applying voltages to said bit lines, word lines, source lines and form lines, each of said plurality of memory cells comprising: a cell selecting transistor; a resistive memory structure serially connected to a drain-source path of the cell selecting transistor, the resistive memory structure and the cell selecting transistor together forming a conductive path between one of said bit lines and one of said source lines and the gate of the cell selecting transistor being connected to one of said word lines; and a boosting capacitor connected between one of said form lines and an internal node of the memory cell at a connection between the resistive memory structure and the cell selecting transistor, said boosting capacitor being configured for boosting a voltage on said internal node; characterised in that the memory device is an oxide-type resistive RAM and in that said memory controller is arranged for performing an electroforming procedure in which in a first phase a supply voltage is applied to said bit and word lines and a ground voltage is applied to said form and source lines for a predetermined period, such that said boosting capacitors are charged by sub-threshold leakage current through said cell selecting transistors, and in a second phase the voltage on said form lines is driven to said supply voltage while maintaining the bit and word lines at the supply voltage and the source lines at the ground voltage, such that charge on said boosting capacitors boosts the voltage on said internal nodes to a forming voltage suitable for electroforming said resistive memory structure. a cell selecting transistor; a resistive memory structure serially connected to a drain-source path of the cell selecting transistor, the resistive memory structure and the cell selecting transistor together forming a conductive path between one of said bit lines and one of said source lines and the gate of the cell selecting transistor being connected to one of said word lines; and a boosting capacitor connected between one of said form lines and an internal node of the memory cell at a connection between the resistive memory structure and the cell selecting transistor, said boosting capacitor being configured for boosting a voltage on said internal node; characterised in that the memory device is an oxide-type resistive RAM and in that said memory controller is arranged for performing an electroforming procedure in which in a first phase a supply voltage is applied to said bit and word lines and a ground voltage is applied to said form and source lines for a predetermined period, such that said boosting capacitors are charged by sub-threshold leakage current through said cell selecting transistors, and in a second phase the voltage on said form lines is driven to said supply voltage while maintaining the bit and word lines at the supply voltage and the source lines at the ground voltage, such that charge on said boosting capacitors boosts the voltage on said internal nodes to a forming voltage suitable for electroforming said resistive memory structure.