A digital output sensor comprising: a sensor module configured to provide digital data representative of a sensed parameter; an output port configured to transmit the digital data; a First-In-First-Out (FIFO) memory buffer, characterized in that the FIFO memory buffer has a single port memory, wherein the digital data from the sensor module is pushed into the FIFO memory buffer via a single memory port, and wherein the digital data is popped out of the FIFO memory buffer via the single memory port for receipt by the output port; an output holding register operatively coupled between the sensor module and the single port memory, the output holding register for temporarily storing the digital data prior to being pushed into the FIFO memory buffer via the single memory port; an output staging register operatively coupled between the single port memory and the output port, the output staging register for temporarily storing popped digital data from the FIFO memory buffer via the single memory port prior to receipt by the output port; a controller which controls the FIFO memory buffer, the controller configured to: determine when new digital data is ready at the output holding register; when new digital data is ready at the output holding register, push new digital data from the output holding register into the FIFO memory buffer via the single memory port; when there is no new digital data ready at the output holding register, determine whether to pop the digital data from the FIFO memory buffer to the output staging register via the single memory port, and if so, pop the digital data from the FIFO memory buffer to the output staging register via the single memory port; and when the output staging register is empty and the FIFO memory is empty, determine whether to bypass the FIFO memory buffer and transfer new digital data directly from the output holding register to the output staging register. a sensor module configured to provide digital data representative of a sensed parameter; an output port configured to transmit the digital data; a First-In-First-Out (FIFO) memory buffer, characterized in that the FIFO memory buffer has a single port memory, wherein the digital data from the sensor module is pushed into the FIFO memory buffer via a single memory port, and wherein the digital data is popped out of the FIFO memory buffer via the single memory port for receipt by the output port; an output holding register operatively coupled between the sensor module and the single port memory, the output holding register for temporarily storing the digital data prior to being pushed into the FIFO memory buffer via the single memory port; an output staging register operatively coupled between the single port memory and the output port, the output staging register for temporarily storing popped digital data from the FIFO memory buffer via the single memory port prior to receipt by the output port; a controller which controls the FIFO memory buffer, the controller configured to: determine when new digital data is ready at the output holding register; when new digital data is ready at the output holding register, push new digital data from the output holding register into the FIFO memory buffer via the single memory port; when there is no new digital data ready at the output holding register, determine whether to pop the digital data from the FIFO memory buffer to the output staging register via the single memory port, and if so, pop the digital data from the FIFO memory buffer to the output staging register via the single memory port; and when the output staging register is empty and the FIFO memory is empty, determine whether to bypass the FIFO memory buffer and transfer new digital data directly from the output holding register to the output staging register. determine when new digital data is ready at the output holding register; when new digital data is ready at the output holding register, push new digital data from the output holding register into the FIFO memory buffer via the single memory port; when there is no new digital data ready at the output holding register, determine whether to pop the digital data from the FIFO memory buffer to the output staging register via the single memory port, and if so, pop the digital data from the FIFO memory buffer to the output staging register via the single memory port; and when the output staging register is empty and the FIFO memory is empty, determine whether to bypass the FIFO memory buffer and transfer new digital data directly from the output holding register to the output staging register.