An erasable programmable single-poly nonvolatile memory, comprising: a substrate structure (P-substrate); a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage (V SG), and the first source/drain region is connected to a source line voltage (V SL); a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage (V BL), and the first source/drain region, the second source/drain region, and the third source/drain region are constructed in a N-well region; and an erase gate region, wherein said floating gate extends over said erase gate region and wherein the erase gate region comprises an n-type source/drain region connected to an erase line voltage (V EL) and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure; characterized in that the erase gate region further comprises a first n-type double diffused drain region formed between the n-type source/drain region and the P-well region, wherein the P-well region comprises: a first p-type region formed under a surface of the substrate structure and contacted to the first n-type double diffused drain region; a plurality of second p-type regions; and a third p-type region formed under the first p-type region; wherein the first p-type region and the third p-type region are located between the second p-type regions; and wherein a dosage in the second p-type regions is higher than a dosage in the first p-type region, and a dosage in the third p-type region is higher than the dosage in the first p-type region. a substrate structure (P-substrate); a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage (V SG), and the first source/drain region is connected to a source line voltage (V SL); a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage (V BL), and the first source/drain region, the second source/drain region, and the third source/drain region are constructed in a N-well region; and an erase gate region, wherein said floating gate extends over said erase gate region and wherein the erase gate region comprises an n-type source/drain region connected to an erase line voltage (V EL) and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure; characterized in that the erase gate region further comprises a first n-type double diffused drain region formed between the n-type source/drain region and the P-well region, wherein the P-well region comprises: a first p-type region formed under a surface of the substrate structure and contacted to the first n-type double diffused drain region; a plurality of second p-type regions; and a third p-type region formed under the first p-type region; wherein the first p-type region and the third p-type region are located between the second p-type regions; and wherein a dosage in the second p-type regions is higher than a dosage in the first p-type region, and a dosage in the third p-type region is higher than the dosage in the first p-type region.