A system comprising a high-frequency switch and a first, a second and a third control voltage source (415a, 415b, 415c), wherein the high-frequency switch comprises: a transistor including a drain, a source, a gate, and a back gate, the transistor performing electrical conduction or cut-off between the drain and the source by controlling a voltage at the gate; a resistive element disposed between the back gate and the second control voltage source; and a first switching circuit for causing a short circuit between the back gate and the first control voltage source upon the cut-off, wherein the anode side of a parasitic diode included in the first switching circuit is connected to the back gate, and the cathode side of the parasitic diode is connected to the first control voltage source;; wherein the transistor is an NMOS transistor, and the first switching circuit is formed with the parasitic diode (411, 507), which is formed at a junction surface between an N-well and the back gate, the N-well being configured to perform electrical cut-off between a semiconductor substrate and the back gate of the NMOS transistor; and the first, second and third control voltage sources (415a, 415b, 415c) are configured for controlling a bias potential of the parasitic diode (411, 507); wherein the third control voltage source is a source-drain bias control voltage source; wherein the system is configured such that when the parasitic diode (411, 507) is reverse-biased, the second control voltage source and the third control voltage source are biased to ground, and the first control voltage source is biased at a withstand voltage of the NMOS transistor, and the system is further configured such that when the parasitic diode (411, 507) is forward-biased, the second control voltage source is biased at a voltage greater than or equal to a threshold voltage of the diode, and the third control voltage source is biased at the withstand voltage of the NMOS transistor and the first control voltage source is biased to ground. a transistor including a drain, a source, a gate, and a back gate, the transistor performing electrical conduction or cut-off between the drain and the source by controlling a voltage at the gate; a resistive element disposed between the back gate and the second control voltage source; and a first switching circuit for causing a short circuit between the back gate and the first control voltage source upon the cut-off, wherein the anode side of a parasitic diode included in the first switching circuit is connected to the back gate, and the cathode side of the parasitic diode is connected to the first control voltage source;; wherein the transistor is an NMOS transistor, and the first switching circuit is formed with the parasitic diode (411, 507), which is formed at a junction surface between an N-well and the back gate, the N-well being configured to perform electrical cut-off between a semiconductor substrate and the back gate of the NMOS transistor; and the first, second and third control voltage sources (415a, 415b, 415c) are configured for controlling a bias potential of the parasitic diode (411, 507); wherein the third control voltage source is a source-drain bias control voltage source; wherein the system is configured such that when the parasitic diode (411, 507) is reverse-biased, the second control voltage source and the third control voltage source are biased to ground, and the first control voltage source is biased at a withstand voltage of the NMOS transistor, and the system is further configured such that when the parasitic diode (411, 507) is forward-biased, the second control voltage source is biased at a voltage greater than or equal to a threshold voltage of the diode, and the third control voltage source is biased at the withstand voltage of the NMOS transistor and the first control voltage source is biased to ground.