A cache management circuit for predictive adjustment of a cache control policy based on persistent cache control information, the cache management circuit configured to: receive a memory request comprising a memory address to access data at the memory address; receive a hit-miss indicator from a cache memory, the hit-miss indicator indicating a cache hit in response to the data at the memory address being stored in the cache memory and indicating a cache miss in response to the data at the memory address not being stored in the cache memory; generate cache control information corresponding to the memory address based on the hit-miss indicator and the cache control policy; store the cache control information corresponding to the memory address persistently, independent of the data being evicted from the cache memory; and control generation of a retention rank of a cache line based on the stored cache control information, wherein the cache management circuit comprises a predictor table comprising a plurality of entries for storing the cache control information, each entry corresponding to a memory address, the cache management circuit further configured to store the cache control information in an entry in the predictor table corresponding to the memory address in the memory request; and wherein the cache management circuit comprises a replacement likelihood history circuit configured to store an RHL pattern comprising retention ranks of cache lines in the cache memory accessed in consecutive memory requests, the cache management circuit configured to: record an RLH pattern corresponding to the received memory request; generate a hash of the RLH pattern and the memory address of the memory request; and store the cache control information in the entry of the predictor table corresponding to the memory address of the memory request, the entry comprising an index matching the hash. receive a memory request comprising a memory address to access data at the memory address; receive a hit-miss indicator from a cache memory, the hit-miss indicator indicating a cache hit in response to the data at the memory address being stored in the cache memory and indicating a cache miss in response to the data at the memory address not being stored in the cache memory; generate cache control information corresponding to the memory address based on the hit-miss indicator and the cache control policy; store the cache control information corresponding to the memory address persistently, independent of the data being evicted from the cache memory; and control generation of a retention rank of a cache line based on the stored cache control information, wherein the cache management circuit comprises a predictor table comprising a plurality of entries for storing the cache control information, each entry corresponding to a memory address, the cache management circuit further configured to store the cache control information in an entry in the predictor table corresponding to the memory address in the memory request; and wherein the cache management circuit comprises a replacement likelihood history circuit configured to store an RHL pattern comprising retention ranks of cache lines in the cache memory accessed in consecutive memory requests, the cache management circuit configured to: record an RLH pattern corresponding to the received memory request; generate a hash of the RLH pattern and the memory address of the memory request; and store the cache control information in the entry of the predictor table corresponding to the memory address of the memory request, the entry comprising an index matching the hash. record an RLH pattern corresponding to the received memory request; generate a hash of the RLH pattern and the memory address of the memory request; and store the cache control information in the entry of the predictor table corresponding to the memory address of the memory request, the entry comprising an index matching the hash.