A memory circuit, comprising: first and second flip-flop circuits (219, 220) which are arranged in a bit line direction; a first write control circuit (206, 208) which is connected to said first flip-flop circuit; a second write control circuit (215, 217) which is connected to said second flip-flop circuit; a first read control circuit (205, 207) which is connected to said first flip-flop circuit, is controlled by a first read control signal supplied to the first read word line (+RWL1), to perform read control of a read signal from said first flip-flop circuit; and a second read control circuit (216, 218) which is connected to said second flip-flop circuit, is controlled by a second read control signal supplied to the second read word line (+RWL0), to perform read control of a read signal from said second flip-flop circuit, characterised in that first and second flip-flop circuits (219, 220) are connected in parallel to a common write word line (+WWL), the common write word line (+WWL) being parallel to first and second read word lines (+RWL, -RWL) the first write control circuit (206, 208) is controlled by a write control signal supplied to said common write word line (+WWL), to supply a first write signal (+WBL1) to said first flip-flop circuit the second write control circuit (215, 217) is controlled by a write control signal supplied to said common write word line (+WWL), to supply a second write signal (+WBL0) to said second flip-flop circuit, the first and second write signals (+WBL1, +WBL0) are configured to be set respectively in the first and second flip-circuits (219, 220) at the same time by using the common write word line (+WWL); and said first read control circuit (205, 207) and said second read control circuit (216, 218), are configured in response to said first and second read control signals supplied to said first and second read word lines (+RWL1, +RWL0) respectively, to read out data from said first and second flip-flop circuits (219, 220) onto first and second read bit lines (+RBL, -RBL). first and second flip-flop circuits (219, 220) which are arranged in a bit line direction; a first write control circuit (206, 208) which is connected to said first flip-flop circuit; a second write control circuit (215, 217) which is connected to said second flip-flop circuit; a first read control circuit (205, 207) which is connected to said first flip-flop circuit, is controlled by a first read control signal supplied to the first read word line (+RWL1), to perform read control of a read signal from said first flip-flop circuit; and a second read control circuit (216, 218) which is connected to said second flip-flop circuit, is controlled by a second read control signal supplied to the second read word line (+RWL0), to perform read control of a read signal from said second flip-flop circuit, characterised in that first and second flip-flop circuits (219, 220) are connected in parallel to a common write word line (+WWL), the common write word line (+WWL) being parallel to first and second read word lines (+RWL, -RWL) the first write control circuit (206, 208) is controlled by a write control signal supplied to said common write word line (+WWL), to supply a first write signal (+WBL1) to said first flip-flop circuit the second write control circuit (215, 217) is controlled by a write control signal supplied to said common write word line (+WWL), to supply a second write signal (+WBL0) to said second flip-flop circuit, the first and second write signals (+WBL1, +WBL0) are configured to be set respectively in the first and second flip-circuits (219, 220) at the same time by using the common write word line (+WWL); and said first read control circuit (205, 207) and said second read control circuit (216, 218), are configured in response to said first and second read control signals supplied to said first and second read word lines (+RWL1, +RWL0) respectively, to read out data from said first and second flip-flop circuits (219, 220) onto first and second read bit lines (+RBL, -RBL).