A digital-to analog-converter, DAC, comprising: - a MSB resistor ladder comprising a plurality of series connected resistors 660), wherein the MSB resistor ladder is coupled between a first and second reference potential, wherein a supply voltage is greater than the first reference potential + 1V and the first reference potential is preferably one half of the supply voltage and the second reference potential is preferably ground; - a LSB resistor ladder comprising a plurality of series connected resistors, wherein each LSB resistor is formed by p-channel depletion transistors (330 1..330 m-1; 910; 930) connected as diodes; - a plurality of switching units for connecting one of said series connected resistors 660) of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit 630) comprises a first p-channel depletion field effect transistor (330 m) for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second p-channel depletion field effect transistor (330 0) for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein gates and wells of each first and second p-channel depletion field effect transistors (330m, 330 0) are controlled such that each source drain path of the first and second p-channel depletion field effect transistors (330 m, 330 0) forms a resistor having approximately the same value as a resistor of the LSB resistor ladder when switched on, and a decoder for controlling one of the switching units to connect an associated resistor of the MSB resistor ladder with the LSB resistor ladder and for selecting one of a plurality of tapping nodes of the LSB resistor ladder for providing an output voltage of the DAC; wherein a gate of the first p-channel depletion field effect transistors (330 m) is switched between the first terminal of the LSB resistor ladder and the supply voltage and a well of the first p-channel depletion field effect transistors (330 m) is switched between the first reference potential and the supply voltage, respectively, and a gate of the second p-channel depletion field effect transistors (330 0) is switched between the second reference potential and the supply voltage and a well of the second p-channel depletion field effect transistors (330 0) is switched between the second terminal of the LSB resistor ladder and the supply voltage, respectively. - a MSB resistor ladder comprising a plurality of series connected resistors 660), wherein the MSB resistor ladder is coupled between a first and second reference potential, wherein a supply voltage is greater than the first reference potential + 1V and the first reference potential is preferably one half of the supply voltage and the second reference potential is preferably ground; - a LSB resistor ladder comprising a plurality of series connected resistors, wherein each LSB resistor is formed by p-channel depletion transistors (330 1..330 m-1; 910; 930) connected as diodes; - a plurality of switching units for connecting one of said series connected resistors 660) of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit 630) comprises a first p-channel depletion field effect transistor (330 m) for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second p-channel depletion field effect transistor (330 0) for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein gates and wells of each first and second p-channel depletion field effect transistors (330m, 330 0) are controlled such that each source drain path of the first and second p-channel depletion field effect transistors (330 m, 330 0) forms a resistor having approximately the same value as a resistor of the LSB resistor ladder when switched on, and a decoder for controlling one of the switching units to connect an associated resistor of the MSB resistor ladder with the LSB resistor ladder and for selecting one of a plurality of tapping nodes of the LSB resistor ladder for providing an output voltage of the DAC;