An integrated circuit constructed on a semiconductor substrate comprising: at least one magnetic random access memory (MRAM) array configured for having performance and density criteria that match MOS transistor based memory wherein MOS transistor based memory is a static random access memory (SRAM), a dynamic random access memory (DRAM), or a flash memory, comprising: a plurality of MRAM cells (215, 220) arranged in rows and columns, wherein each MRAM cell comprising: a magnetic tunnel junction device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer; and a gating metal oxide semiconductor transistor serially connected to the MTJ device; and at least one magnetic one-time-programmable memory array, comprising: a plurality of magnetic one-time programmable memory cells (255, 260) arranged in rows and columns, wherein each magnetic one-time-programmable memory cell comprising: a magnetic tunnel junction device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, and a gating metal oxide semiconductor transistor serially connected to the MTJ device, characterized in that a diameter of the MTJ device is chosen such that a resistance of the tunnel barrier insulating layer is increased to a level that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is a write voltage for the MRAM cell, wherein the diameter of the MTJ device of the magnetic one-time-programmable memory cell is chosen to be approximately 20% smaller than a diameter of the MTJ device of the MRAM cell. at least one magnetic random access memory (MRAM) array configured for having performance and density criteria that match MOS transistor based memory wherein MOS transistor based memory is a static random access memory (SRAM), a dynamic random access memory (DRAM), or a flash memory, comprising: a plurality of MRAM cells (215, 220) arranged in rows and columns, wherein each MRAM cell comprising: a magnetic tunnel junction device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer; and a gating metal oxide semiconductor transistor serially connected to the MTJ device; and a magnetic tunnel junction device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer; and a gating metal oxide semiconductor transistor serially connected to the MTJ device; and at least one magnetic one-time-programmable memory array, comprising: a plurality of magnetic one-time programmable memory cells (255, 260) arranged in rows and columns, wherein each magnetic one-time-programmable memory cell comprising: a magnetic tunnel junction device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, and a gating metal oxide semiconductor transistor serially connected to the MTJ device, characterized in that a diameter of the MTJ device is chosen such that a resistance of the tunnel barrier insulating layer is increased to a level that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is a write voltage for the MRAM cell, wherein the diameter of the MTJ device of the magnetic one-time-programmable memory cell is chosen to be approximately 20% smaller than a diameter of the MTJ device of the MRAM cell. a magnetic tunnel junction device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, and a gating metal oxide semiconductor transistor serially connected to the MTJ device, characterized in that a diameter of the MTJ device is chosen such that a resistance of the tunnel barrier insulating layer is increased to a level that the tunnel barrier insulating layer is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is a write voltage for the MRAM cell, wherein the diameter of the MTJ device of the magnetic one-time-programmable memory cell is chosen to be approximately 20% smaller than a diameter of the MTJ device of the MRAM cell.