A circuit, comprising: - a differential circuit stage having a first input, a second input and an output, - a negative feedback path from the output to the second input of the differential circuit stage (10, 100), wherein: - the negative feedback path comprises a unitary gain path from the output to the second input of the differential circuit stage (10, 100), the unitary gain path coupled, at the output, to ground via a reference impedance (Z REF; C REF), wherein a negative impedance (Z NEG; C IN) is available at the first input of the differential circuit stage (10, 100), characterized in that: - the differential circuit stage comprises a differential input stage having a first input node coupled to the first input of the differential circuit stage, a second input node coupled to the second input of the differential circuit stage, and in phase dual outputs provided at respectively first output node and a second output node, - a first positive feedback path is provided from the first output node to the first input node of the differential input stage, - a second positive feedback path is provided from the second output node to the first input node of the differential input stage, - the negative feedback path is coupled to both the first output node and the second output node of the differential input stage via respective first transistors in a pair of first transistors (10A, 10B), - the first positive feedback path and the second positive feedback path comprise respective second transistors in a pair of second transistors (10C, 10D), - each of the first transistors in the pair of first transistors (10A, 10B) is coupled in a current mirror arrangement to a respective one of the second transistors in the pair of second transistors (10C, 10D) such that a control electrode of said each of the first transistors in the pair of first transistors and a control electrode of said respective one of the second transistors in the pair of second transistors are connected to each other and driven by a respective one of the dual outputs of the differential input stage. - a differential circuit stage having a first input, a second input and an output, - a negative feedback path from the output to the second input of the differential circuit stage (10, 100), - the negative feedback path comprises a unitary gain path from the output to the second input of the differential circuit stage (10, 100), the unitary gain path coupled, at the output, to ground via a reference impedance (Z REF; C REF), wherein a negative impedance (Z NEG; C IN) is available at the first input of the differential circuit stage (10, 100), - the differential circuit stage comprises a differential input stage having a first input node coupled to the first input of the differential circuit stage, a second input node coupled to the second input of the differential circuit stage, and in phase dual outputs provided at respectively first output node and a second output node, - a first positive feedback path is provided from the first output node to the first input node of the differential input stage, - a second positive feedback path is provided from the second output node to the first input node of the differential input stage, - the negative feedback path is coupled to both the first output node and the second output node of the differential input stage via respective first transistors in a pair of first transistors (10A, 10B), - the first positive feedback path and the second positive feedback path comprise respective second transistors in a pair of second transistors (10C, 10D), - each of the first transistors in the pair of first transistors (10A, 10B) is coupled in a current mirror arrangement to a respective one of the second transistors in the pair of second transistors (10C, 10D) such that a control electrode of said each of the first transistors in the pair of first transistors and a control electrode of said respective one of the second transistors in the pair of second transistors are connected to each other and driven by a respective one of the dual outputs of the differential input stage.