Apparatus for processing data comprising: a processor core capable of performing data processing operations in response to a sequence of instructions, wherein the data processing operations comprise read operations which retrieve data items from a memory and write operations which write data items to the memory, wherein the memory is a non-volatile memory; a write-back cache capable of storing local copies of the data items retrieved from the memory and written to the memory by the processor core when executing the sequence of instructions; and a storage unit capable of storing indications of the write operations initiated by the processor core, and the processor core is capable of responding to an end instruction in the sequence of instructions by: causing the local copies of data items which are the subject of the write operations by the processor core and for which an indication is stored in the storage unit to be cleaned from the write-back cache to the memory; and clearing the indications of the write operations stored in the storage unit, wherein the processor core is further capable of causing the indications of the write operations initiated by the processor core to be stored in the storage unit after a begin instruction in the sequence of instructions, characterized in that: the processor core is capable of only performing a write operation to a predetermined portion of the memory when a pending write instruction specifying the predetermined portion of the memory is preceded by the begin instruction and followed by the end instruction, and the processor core is capable of preventing a write operation to the predetermined portion of the memory from being performed when a pending write instruction specifying the predetermined portion of the memory is not preceded by the begin instruction and followed by the end instruction. a processor core capable of performing data processing operations in response to a sequence of instructions, wherein the data processing operations comprise read operations which retrieve data items from a memory and write operations which write data items to the memory, wherein the memory is a non-volatile memory; a write-back cache capable of storing local copies of the data items retrieved from the memory and written to the memory by the processor core when executing the sequence of instructions; and a storage unit capable of storing indications of the write operations initiated by the processor core, and the processor core is capable of responding to an end instruction in the sequence of instructions by: causing the local copies of data items which are the subject of the write operations by the processor core and for which an indication is stored in the storage unit to be cleaned from the write-back cache to the memory; and clearing the indications of the write operations stored in the storage unit, causing the local copies of data items which are the subject of the write operations by the processor core and for which an indication is stored in the storage unit to be cleaned from the write-back cache to the memory; and clearing the indications of the write operations stored in the storage unit, wherein the processor core is further capable of causing the indications of the write operations initiated by the processor core to be stored in the storage unit after a begin instruction in the sequence of instructions, characterized in that: the processor core is capable of only performing a write operation to a predetermined portion of the memory when a pending write instruction specifying the predetermined portion of the memory is preceded by the begin instruction and followed by the end instruction, and the processor core is capable of preventing a write operation to the predetermined portion of the memory from being performed when a pending write instruction specifying the predetermined portion of the memory is not preceded by the begin instruction and followed by the end instruction. the processor core is capable of only performing a write operation to a predetermined portion of the memory when a pending write instruction specifying the predetermined portion of the memory is preceded by the begin instruction and followed by the end instruction, and the processor core is capable of preventing a write operation to the predetermined portion of the memory from being performed when a pending write instruction specifying the predetermined portion of the memory is not preceded by the begin instruction and followed by the end instruction.