Tristate output buffer, comprising: a first branch with a first buffer; a second branch with a second buffer; wherein the first buffer comprises: a supply port (Vdd), a ground port (Vss), an output port (Outa), two switchable semiconductor elements (Q1, Q1e) of a first type and two switchable semiconductor elements (Q2, Q2e) of a second type; wherein a switching behavior of the switchable semiconductor elements (Q1, Q1e) of the first type differs from a switching behavior of the switchable semiconductor elements (Q2, Q2e) of the second type; wherein the two switchable semiconductor elements (Q1, Q1e) of the first type are connected in series and are arranged between the supply port (Vdd) and the output port (Outa) such that they can be put in a conductive state independently of each other; wherein the two switchable semiconductor elements (Q2, Q2e) of the second type are connected in series and are arranged between the ground port (Vss) and the output port (Outa) such that they can be put in a conductive state independently of each other; wherein the tristate output buffer furthermore comprises a third branch with a third buffer; wherein the third buffer comprises the same elements as the first buffer and the elements of the third buffer are also interconnected with each other in a manner as the elements of the first buffer; wherein the output port (Outa) of the first buffer, an output port (Outb) of the second buffer, and an output port (Outc) of the third buffer are connected together and form an output port (Out) of the tristate output buffer; wherein each branch of the group consisting of the first branch, the second branch, and the third branch comprises a first signal interface (upa, upb, upc), wherein in the first branch, the second branch, and the third branch the respective first signal interface (upa, upb, upc) is fed directly to a control port of a first semiconductor element of the first type; is wherein each branch of the group consisting of the first branch, the second branch, and the third branch comprises a majority decision unit (115, 125, 135); wherein each majority decision unit comprises a first majority voter with an input interface (A, B, C) that is coupled with all of the first signal interfaces (upa, upb, upc) of the first branch, the second branch, and the third branch, and which first majority voter is configured to determine a first majority value based on values of the connected first signal interfaces and to output the first majority value at an outbound interface; wherein the outbound interface of the first majority voter is fed directly to a control port of a second semiconductor element (Q1e) of the first type. a first branch with a first buffer; a second branch with a second buffer; wherein the first buffer comprises: a supply port (Vdd), a ground port (Vss), an output port (Outa), two switchable semiconductor elements (Q1, Q1e) of a first type and two switchable semiconductor elements (Q2, Q2e) of a second type; wherein a switching behavior of the switchable semiconductor elements (Q1, Q1e) of the first type differs from a switching behavior of the switchable semiconductor elements (Q2, Q2e) of the second type; wherein the two switchable semiconductor elements (Q1, Q1e) of the first type are connected in series and are arranged between the supply port (Vdd) and the output port (Outa) such that they can be put in a conductive state independently of each other; wherein the two switchable semiconductor elements (Q2, Q2e) of the second type are connected in series and are arranged between the ground port (Vss) and the output port (Outa) such that they can be put in a conductive state independently of each other; wherein the tristate output buffer furthermore comprises a third branch with a third buffer; wherein the third buffer comprises the same elements as the first buffer and the elements of the third buffer are also interconnected with each other in a manner as the elements of the first buffer; wherein the output port (Outa) of the first buffer, an output port (Outb) of the second buffer, and an output port (Outc) of the third buffer are connected together and form an output port (Out) of the tristate output buffer; wherein each branch of the group consisting of the first branch, the second branch, and the third branch comprises a first signal interface (upa, upb, upc), wherein in the first branch, the second branch, and the third branch the respective first signal interface (upa, upb, upc) is fed directly to a control port of a first semiconductor element of the first type; is wherein each branch of the group consisting of the first branch, the second branch, and the third branch comprises a majority decision unit (115, 125, 135); wherein each majority decision unit comprises a first majority voter with an input interface (A, B, C) that is coupled with all of the first signal interfaces (upa, upb, upc) of the first branch, the second branch, and the third branch, and which first majority voter is configured to determine a first majority value based on values of the connected first signal interfaces and to output the first majority value at an outbound interface; wherein the outbound interface of the first majority voter is fed directly to a control port of a second semiconductor element (Q1e) of the first type.