A liquid crystal display device comprising: a driver circuit configured to receive at least a first input signal, a second input signal, a third input signal, and a fourth input signal, and to output an output signal, the output signal potential being set according to the first to fourth input signals; and a pixel comprising a liquid crystal element, wherein the liquid crystal element is controlled by the output signal; wherein the driver circuit comprises a first switch (201_1), a second switch (201_2), a third switch (101_1), and a fourth switch (101_2), and a first wiring (115_1) to which the first input signal is input, a second wiring (115_2) to which the second input signal is input, a third wiring to which the third input signal is input, a fourth wiring to which the fourth input signal is input, and a fifth wiring, wherein a potential applied to the fifth wiring is equal to the potential of the output signals; the first switch (201_1) is connected to the first wiring (115_1) and to the third switch (101_1) and configured to control the third switch (101_1); the second switch (201_2) is connected to the second wiring (115_2) and to the fourth switch (101_2) and configured to control the fourth switch (101_2); the first switch (201_1) and the second switch (201_2) are configured to be turned on and off according to the third input signal; the third switch (101_1) and the fourth switch (101_2) are connected in parallel and each of the third switch (101_1) and the fourth switch (101_2) has a first terminal connected to the fourth wiring and a second terminal connected to the fifth wiring; the third switch (101_1) is configured to set an electrical potential state of the output signal according to the fourth input signal when turned on in accordance with the first input signal; and the fourth switch (101_2) is configured to set an electrical potential state of the output signal according to the fourth input signal when turned on in accordance with the second input signal; characterized in that the driver circuit is adapted to output the fourth input signal by repeatedly switching the fourth input signal between a first potential state and a second potential state as a clock signal and further adapted to control the first to fourth input signals such that: the first input signal is at a high level in a first frame period and at a low level in a second frame period, the first and second frame periods forming a periodic frame sequence and each comprising a plurality of sub-periods; the second input signal is at a low level in the first frame period and at a high level in the second frame period; the third input signal is at a high level and the fourth input signal is at a low level in a first sub-period (A1, A2) of the first and second frame periods; and the third input signal is at a low level and the fourth input signal is at a high level in a second sub-period (B1, B2) of the first and second frame periods. a driver circuit configured to receive at least a first input signal, a second input signal, a third input signal, and a fourth input signal, and to output an output signal, the output signal potential being set according to the first to fourth input signals; and a pixel comprising a liquid crystal element, wherein the liquid crystal element is controlled by the output signal; wherein the driver circuit comprises a first switch (201_1), a second switch (201_2), a third switch (101_1), and a fourth switch (101_2), and a first wiring (115_1) to which the first input signal is input, a second wiring (115_2) to which the second input signal is input, a third wiring to which the third input signal is input, a fourth wiring to which the fourth input signal is input, and a fifth wiring, wherein a potential applied to the fifth wiring is equal to the potential of the output signals; the first switch (201_1) is connected to the first wiring (115_1) and to the third switch (101_1) and configured to control the third switch (101_1); the second switch (201_2) is connected to the second wiring (115_2) and to the fourth switch (101_2) and configured to control the fourth switch (101_2); the first switch (201_1) and the second switch (201_2) are configured to be turned on and off according to the third input signal; the third switch (101_1) and the fourth switch (101_2) are connected in parallel and each of the third switch (101_1) and the fourth switch (101_2) has a first terminal connected to the fourth wiring and a second terminal connected to the fifth wiring; the third switch (101_1) is configured to set an electrical potential state of the output signal according to the fourth input signal when turned on in accordance with the first input signal; and the fourth switch (101_2) is configured to set an electrical potential state of the output signal according to the fourth input signal when turned on in accordance with the second input signal; the first input signal is at a high level in a first frame period and at a low level in a second frame period, the first and second frame periods forming a periodic frame sequence and each comprising a plurality of sub-periods; the second input signal is at a low level in the first frame period and at a high level in the second frame period; the third input signal is at a high level and the fourth input signal is at a low level in a first sub-period (A1, A2) of the first and second frame periods; and the third input signal is at a low level and the fourth input signal is at a high level in a second sub-period (B1, B2) of the first and second frame periods.