Apparatus for processing data, comprising: processing circuitry to execute a hypervisor program to provide a virtual machine execution environment and to execute a virtual machine program using said virtual machine execution environment; and memory management circuitry to manage a translation of a virtual address generated by said virtual machine program to a physical address of a memory using first stage translation data specifying a translation from said virtual address to an intermediate physical address and second stage translation data specifying a translation from said intermediate physical address to said physical address; characterised in that said memory management circuitry controls access to said memory to provide one or more virtual-machine private regions within said memory, that are accessible to said virtual machine program and are at least marked as inaccessible to said hypervisor program; said first stage translation data includes attribute data to mark respective regions of said memory as one of one or more device memory regions or as one of one or more non-device memory regions, the one or more device memory regions including memory addresses dedicated to memory-mapped hardware devices; and when a memory access request by said virtual machine program is to a target region of said memory that is both a virtual machine private region and a device memory region, said memory management circuitry is adapted to manage said translation in dependence upon said second stage translation data to provide private-device region management, wherein said first stage translation data and said second stage translation data are accessible to said virtual machine program, but inaccessible to said hypervisor program. processing circuitry to execute a hypervisor program to provide a virtual machine execution environment and to execute a virtual machine program using said virtual machine execution environment; and memory management circuitry to manage a translation of a virtual address generated by said virtual machine program to a physical address of a memory using first stage translation data specifying a translation from said virtual address to an intermediate physical address and second stage translation data specifying a translation from said intermediate physical address to said physical address; characterised in that said memory management circuitry controls access to said memory to provide one or more virtual-machine private regions within said memory, that are accessible to said virtual machine program and are at least marked as inaccessible to said hypervisor program; said first stage translation data includes attribute data to mark respective regions of said memory as one of one or more device memory regions or as one of one or more non-device memory regions, the one or more device memory regions including memory addresses dedicated to memory-mapped hardware devices; and when a memory access request by said virtual machine program is to a target region of said memory that is both a virtual machine private region and a device memory region, said memory management circuitry is adapted to manage said translation in dependence upon said second stage translation data to provide private-device region management, wherein said first stage translation data and said second stage translation data are accessible to said virtual machine program, but inaccessible to said hypervisor program. said memory management circuitry controls access to said memory to provide one or more virtual-machine private regions within said memory, that are accessible to said virtual machine program and are at least marked as inaccessible to said hypervisor program; said first stage translation data includes attribute data to mark respective regions of said memory as one of one or more device memory regions or as one of one or more non-device memory regions, the one or more device memory regions including memory addresses dedicated to memory-mapped hardware devices; and when a memory access request by said virtual machine program is to a target region of said memory that is both a virtual machine private region and a device memory region, said memory management circuitry is adapted to manage said translation in dependence upon said second stage translation data to provide private-device region management, wherein said first stage translation data and said second stage translation data are accessible to said virtual machine program, but inaccessible to said hypervisor program.