A double data rate circuit comprising: a clock generator, configured to receive a source clock signal (CKs) to generate a pair of complementary clock signals (CK, CKc); a clock divider, coupled to the clock generator, and configured to generate four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1) using only single-edge transitions of the pair of complementary clock signals (CK, CKc), the four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1) being successively out-of-phase by 90°; and a multiplexer, coupled to the clock divider, and configured to multiplex multiple data bits (DrO, Df0, Dr1, Df1) into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits (DrO, Df0, Dr1, Df1) upon a first edge transition of and a second edge transition of two of the four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel U1), respectively, and outputting each selected data bit (DrO, Df0, Dr1, Df1) as the output data stream, wherein the multiplexer comprises four 3-input NAND gates (50a-50d) and one 4-input NAND gate coupled thereto; each of the four 3-input NAND gates (50a-50d) is configured to receive one of four multiple data bits (DrO, Df0, Dr1, Df1) and two of the four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1), start outputting the received data bit (DrO, Df0, Dr1, Df1) upon the first edge transition of one of the two received multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel U1), and stop outputting the received data bit (DrO, Df0, Dr1, Df1) upon the second edge transition of another one of the two received multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel U1), the two received multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1) being out-of-phase by 90°; and the 4-input NAND gate is configured to receive respective output signals from the four 3-input NAND gates (50a-50d) to generate the output data stream, wherein in particular inputs of the 3-input NAND gates (50a-50d) are matched in pull-up paths and pull-down paths, and inputs of the 4-input NAND gate are matched in pull-up paths and pull-down paths, wherein the 3-input NAND gates (50a-50d) and the 4-input NAND gate are implemented in a matched structure. a clock generator, configured to receive a source clock signal (CKs) to generate a pair of complementary clock signals (CK, CKc); a clock divider, coupled to the clock generator, and configured to generate four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1) using only single-edge transitions of the pair of complementary clock signals (CK, CKc), the four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1) being successively out-of-phase by 90°; and a multiplexer, coupled to the clock divider, and configured to multiplex multiple data bits (DrO, Df0, Dr1, Df1) into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits (DrO, Df0, Dr1, Df1) upon a first edge transition of and a second edge transition of two of the four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel U1), respectively, and outputting each selected data bit (DrO, Df0, Dr1, Df1) as the output data stream, wherein the multiplexer comprises four 3-input NAND gates (50a-50d) and one 4-input NAND gate coupled thereto; each of the four 3-input NAND gates (50a-50d) is configured to receive one of four multiple data bits (DrO, Df0, Dr1, Df1) and two of the four multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1), start outputting the received data bit (DrO, Df0, Dr1, Df1) upon the first edge transition of one of the two received multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel U1), and stop outputting the received data bit (DrO, Df0, Dr1, Df1) upon the second edge transition of another one of the two received multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel U1), the two received multiphase clock signals (CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1) being out-of-phase by 90°; and the 4-input NAND gate is configured to receive respective output signals from the four 3-input NAND gates (50a-50d) to generate the output data stream, wherein in particular inputs of the 3-input NAND gates (50a-50d) are matched in pull-up paths and pull-down paths, and inputs of the 4-input NAND gate are matched in pull-up paths and pull-down paths, wherein the 3-input NAND gates (50a-50d) and the 4-input NAND gate are implemented in a matched structure.