A digital fractional frequency-division phase-locked loop, comprising a control apparatus, a time-to-digital converter TDC, a digital loop filter DLF, a digital controlled oscillator DCO, a feedback frequency divider DIV, and a Sigma-Delta modulator SDM, wherein an output end of the control apparatus is connected to a first input end of the TDC; an output end of the TDC is connected to an input end of the DLF; an output end of the DLF is connected to an input end of the DCO; an output end of the DCO is connected to a first input end of the DIV; an output end of the DIV is connected to a second input end of the TDC, a second input end of the DIV is connected to an output end of the SDM; a first input end of the control apparatus is connected to the output end of the SDM; a second input end of the control apparatus is connected to an input end of the SDM; and a third input end of the control apparatus receives a reference clock of the phase-locked loop; the SDM is configured to obtain a frequency division control word according to a frequency control word input to the SDM; the DIV is configured to perform frequency division processing on an output signal of the DCO according to the frequency division control word to obtain a feedback clock; the control apparatus is configured to perform delay processing on an active edge of the reference clock according to the frequency control word and the frequency division control word to obtain a delayed reference clock; the TDC is configured to perform phase discrimination processing on the feedback clock and the delayed reference clock to obtain a time difference between the delayed reference clock and the feedback clock; the DLF is configured to perform filtering processing on the time difference that is output after the TDC performs the phase discrimination processing to obtain a processing result; and the DCO is configured to obtain the output signal according to the processing result; wherein the control apparatus comprises: a controller and a digital-to-time converter DTC; a first input end of the controller is connected to the first input end of the control apparatus, and a second input end of the controller is connected to the second input end of the control apparatus; a first output end of the controller is connected to a first input end of the DTC; a second input end of the DTC is connected to a third input end of the control apparatus; an output end of the DTC is connected to the output end of the control apparatus; the controller is configured to receive the frequency control word and the frequency division control word, and determine a value of a delay control signal according to the frequency control word and the frequency division control word; and the DTC is configured to perform the delay processing on the active edge of the reference clock according to the value of the delay control signal to obtain the delayed reference clock; wherein the controller is specifically configured to determine a value D DTC [ k] of the delay control signal, according to the following formula: D DTC k = ∑ i = 1 k N DIV i − N. F wherein D DTC [ k] is a value of the delay control signal at the k th sampling point, N DIV [ i] is an instantaneous value of the frequency division control word output by the SDM at the i th sampling point, and N.F is a value of the frequency control word, wherein N is an integer part of the frequency control word, and. F denotes a fractional part of the frequency control word; wherein a third input end of the controller is connected to the output end of the TDC and the second input end of the controller is connected to the second input end of the DTC; and the controller is further configured to determine a value of a gain control signal according to the frequency control word, the frequency division control word, and the time difference that is output by the TDC, wherein the gain control signal is used to control an adjustment gain of the delay control signal; wherein the controller is specifically configured to, by using a preset adaptive correction algorithm, determine a value G DTC [ k] of the gain control signal, according to the following formula: G DTC k = K LMS × ∑ i = 1 k D DTC i × sgn D TDC i wherein G DTC [ k] is a value of the gain control signal at the k th sampling point, K LMS is a gain of the adaptive correction algorithm, D TDC [ i] is a time difference that is output by the TDC at the i th sampling point, and sgn() is a sign function.