A microelectronic device of flash memory comprising: - a substrate (100, 200), - a plurality of memory cells comprising transistors made in an etched stack (202, 302, 402) of layers based on said substrate whereof a plurality of semi-conductor layers, the etched stack comprising at least one first block (110, 310, 410) of common source of said transistors, and at least one second block (215, 315, 415) in which drain regions and contact zones are formed, - a plurality of other blocks (120, 220, 220a, 220b, 220c, 220d, 220e, 220f) distinct and juxtaposed, connecting the first block (110, 310, 410) and the second block (215, 315, 415), said other distinct blocks comprising, in a direction orthogonal to the principal plane of the substrate (100, 200), several transistor channels, distinct and parallel to each other and to the principal plane of the substrate (100, 200), being distributed according to a matricial arrangement of horizontal rows and vertical rows of channels, - a plurality of gates formed by at least one gate material, including: - a first selection gate (140, 240) coating said channels, - a plurality of control gates (150 1,..., 150 n, 250 1,..., 250 n) coating said channels, - a plurality of second selection gates (160 1,..., 160 m, 260 1,..., 260 m) each coating the channels of the same row of the matricial arrangement, at least one or more of said gates based on a superposition of layers comprising at least one first layer of dielectrical material (252, 352) at least one charge storage zone (354, 354), and at least one second layer of dielectrical material (256, 356), the second block having at least one stepped profile, said stepped profile comprising a plurality of steps (E1, E2, E3, E4, E5), at least one or more of said steps being provided to form bit lines contacting zones, - a plurality of bit lines (130 1,..., 130n, 230) parallel to the principal plane of the substrate is arranged on the second block, each bit line (130 1,..., 130n, 230) being connected to the drains of a same horizontal row of the matricial arrangement. - a substrate (100, 200), - a plurality of memory cells comprising transistors made in an etched stack (202, 302, 402) of layers based on said substrate whereof a plurality of semi-conductor layers, the etched stack comprising at least one first block (110, 310, 410) of common source of said transistors, and at least one second block (215, 315, 415) in which drain regions and contact zones are formed, - a plurality of other blocks (120, 220, 220a, 220b, 220c, 220d, 220e, 220f) distinct and juxtaposed, connecting the first block (110, 310, 410) and the second block (215, 315, 415), said other distinct blocks comprising, in a direction orthogonal to the principal plane of the substrate (100, 200), several transistor channels, distinct and parallel to each other and to the principal plane of the substrate (100, 200), being distributed according to a matricial arrangement of horizontal rows and vertical rows of channels, - a plurality of gates formed by at least one gate material, including: - a first selection gate (140, 240) coating said channels, - a plurality of control gates (150 1,..., 150 n, 250 1,..., 250 n) coating said channels, - a plurality of second selection gates (160 1,..., 160 m, 260 1,..., 260 m) each coating the channels of the same row of the matricial arrangement, at least one or more of said gates based on a superposition of layers comprising at least one first layer of dielectrical material (252, 352) at least one charge storage zone (354, 354), and at least one second layer of dielectrical material (256, 356), the second block having at least one stepped profile, said stepped profile comprising a plurality of steps (E1, E2, E3, E4, E5), at least one or more of said steps being provided to form bit lines contacting zones, - a plurality of bit lines (130 1,..., 130n, 230) parallel to the principal plane of the substrate is arranged on the second block, each bit line (130 1,..., 130n, 230) being connected to the drains of a same horizontal row of the matricial arrangement.