A method of producing a pixellated display device including: a display medium, an array of transistors including: source and drain electrodes at a first level, and gate electrodes and gate addressing lines at a second level for controlling the transistors, and an array of pixel electrodes at a third level, which pixel electrodes are located at least partly between the array of transistors and the display medium, and via which respective portions of the display medium are controllable by the transistors, wherein each pixel electrode is controllable through a respective transistor via one of said gate addressing lines and also overlaps with another of said gate addressing lines and/or the source electrode connected to said another of said gate addressing lines; wherein a patterned lower dielectric layer is configured to provide electrical insulation between the source/drain electrodes at the first level and gate electrodes/gate addressing lines at the second level, and wherein a patterned upper dielectric layer is configured to provide electrical insulation between the gate electrodes/gate addressing lines at the second level and the pixel electrodes at the third level; and characterised in that forming the array of pixel electrodes comprises printing a patterned layer of pixel electrode material over the patterned lower and upper dielectric layers (5, 11); wherein: the lower dielectric layer and the pixel electrode material are chosen such that the lower dielectric layer repels the pixel electrode material as it is being printed; and the material of the upper dielectric layer is chosen such that it covers the lower dielectric layer in areas where the pixel electrodes are to contact the drain electrodes; whereby in areas of the pixel where the upper dielectric layer does not overlap the lower dielectric layer, the lower dielectric layer provides a channel that is repulsive to the pixel electrode material as it is being printed. a display medium, an array of transistors including: source and drain electrodes at a first level, and gate electrodes and gate addressing lines at a second level for controlling the transistors, and source and drain electrodes at a first level, and gate electrodes and gate addressing lines at a second level for controlling the transistors, and an array of pixel electrodes at a third level, which pixel electrodes are located at least partly between the array of transistors and the display medium, and via which respective portions of the display medium are controllable by the transistors, wherein each pixel electrode is controllable through a respective transistor via one of said gate addressing lines and also overlaps with another of said gate addressing lines and/or the source electrode connected to said another of said gate addressing lines; wherein a patterned lower dielectric layer is configured to provide electrical insulation between the source/drain electrodes at the first level and gate electrodes/gate addressing lines at the second level, and wherein a patterned upper dielectric layer is configured to provide electrical insulation between the gate electrodes/gate addressing lines at the second level and the pixel electrodes at the third level; and characterised in that forming the array of pixel electrodes comprises printing a patterned layer of pixel electrode material over the patterned lower and upper dielectric layers (5, 11); wherein: the lower dielectric layer and the pixel electrode material are chosen such that the lower dielectric layer repels the pixel electrode material as it is being printed; and the material of the upper dielectric layer is chosen such that it covers the lower dielectric layer in areas where the pixel electrodes are to contact the drain electrodes; the lower dielectric layer and the pixel electrode material are chosen such that the lower dielectric layer repels the pixel electrode material as it is being printed; and the material of the upper dielectric layer is chosen such that it covers the lower dielectric layer in areas where the pixel electrodes are to contact the drain electrodes; whereby in areas of the pixel where the upper dielectric layer does not overlap the lower dielectric layer, the lower dielectric layer provides a channel that is repulsive to the pixel electrode material as it is being printed.