A clock circuit, comprising a buffer module, N first multiplexers (120-1 - 120-N), and N clock gating cells (130-1 - 130-N), wherein N is a positive integer, • wherein the buffer module comprises an input end and N output ends (112-1 - 112-N), the buffer module is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal whose driving capability is enhanced from the N output ends, and the N output ends (112-1 - 112-N) of the buffer module are connected to data ends (132-1 - 132-N) of the N clock gating cells (130-1 - 130-N) one to one, • wherein output ends (124-1 - 124-N) of the N first multiplexers (123-1 - 123-N) are connected to enabling ends (131-1 - 131-N) of the N clock gating cells (130-1 - 130-N) one to one, and each first multiplexer (120-1 - 120-N) is configured to choose, according to a logic selection signal received by an address input end (123-1 - 123-N), whether to output, from an output end (124-1 - 124-N), a gating logic signal received by a first data input end (121-1 - 121-N) or a frequency division logic signal received by a second data input end (122-1 - 122-N), • wherein each clock gating cell (130-1 - 130-N) is configured to output a clock signal from an output end (133-1 - 133-N) according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end (124-1 - 124-N) of a corresponding first multiplexer (120-1 - 120-N) and the clock signal received by a data end (132-1 - 132-N) from an output end (112-1 - 112-N) of the buffer module, • wherein the buffer module comprises M buffers, wherein M is a positive integer, and M≥N, the M buffers form a tree-shaped clock structure having a root node and N leaf nodes, and paths between the root node and all the leaf nodes have an equal length; and an input end of a buffer at a position of the root node is the input end of the buffer module, and output ends of N buffers at positions of the N leaf nodes are the N output ends of the buffer module, characterized in that the tree-shaped clock structure is an H-shaped clock network structure. • wherein the buffer module comprises an input end and N output ends (112-1 - 112-N), the buffer module is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal whose driving capability is enhanced from the N output ends, and the N output ends (112-1 - 112-N) of the buffer module are connected to data ends (132-1 - 132-N) of the N clock gating cells (130-1 - 130-N) one to one, • wherein output ends (124-1 - 124-N) of the N first multiplexers (123-1 - 123-N) are connected to enabling ends (131-1 - 131-N) of the N clock gating cells (130-1 - 130-N) one to one, and each first multiplexer (120-1 - 120-N) is configured to choose, according to a logic selection signal received by an address input end (123-1 - 123-N), whether to output, from an output end (124-1 - 124-N), a gating logic signal received by a first data input end (121-1 - 121-N) or a frequency division logic signal received by a second data input end (122-1 - 122-N), • wherein each clock gating cell (130-1 - 130-N) is configured to output a clock signal from an output end (133-1 - 133-N) according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end (124-1 - 124-N) of a corresponding first multiplexer (120-1 - 120-N) and the clock signal received by a data end (132-1 - 132-N) from an output end (112-1 - 112-N) of the buffer module, • wherein the buffer module comprises M buffers, wherein M is a positive integer, and M≥N, the M buffers form a tree-shaped clock structure having a root node and N leaf nodes, and paths between the root node and all the leaf nodes have an equal length; and an input end of a buffer at a position of the root node is the input end of the buffer module, and output ends of N buffers at positions of the N leaf nodes are the N output ends of the buffer module,