A power supply circuit for a wireless mobile device having a plurality of power amplification components (160_1-160_N, 170_1-170_M), wherein each power amplification component of a first subset (160_1-160_N) of the power amplification components is configured to operate according to an APT (average power tracking) mode and each power amplification component of a second subset (170_1-170_M) of the power amplification components is configured to operate according to either an ET (envelop tracking) mode or the APT mode, the power supply circuit includes: a first DC(direct current)-DC converter, coupled to each of the power amplification components of the first subset of the power amplification components, the first DC-DC converter being configured to provide a plurality of first output voltages (VAPT1-VATPN) and/or a plurality of DC intermediate voltages (VHF1-VHFM), the plurality of first output voltages being provided to the first subset of the power amplification components, respectively; a second DC-DC converter, coupled to the first DC-DC converter and each of the power amplification components of the second subset of the power amplification components, the second DC-DC converter being configured to provide a plurality of DC components (ET_DC1-ET_DCM) of a plurality of second output voltages (VET1-VETM); a plurality of linear amplifiers (130_1-130_M), each of the plurality of linear amplifiers coupled between the first DC-DC converter and a respective one of the second subset of the power amplification components; and a plurality of bypass switches (140_1-140_M), each of the bypass switches of the plurality of bypass switches coupled to the first DC-DC converter and a respective one of the second subset of the power amplification components, for conducting the plurality of DC intermediate voltages directly to the second subset of the power amplification components, respectively, when the second subset of the power amplification components are to be operated under the APT mode, wherein the bypass switches are used to bypass the respective linear amplifiers when the second subset of the power amplification components are to be operated under the APT mode; wherein when the plurality of linear amplifiers receive the plurality of DC intermediate voltages from the first DC-DC converter, respectively, the plurality of linear amplifiers provide a plurality of AC components (ET_AC1-ET_ACM) of the plurality of second output voltages, respectively; wherein the plurality of DC components of the plurality of second output voltages and the plurality of AC components of the plurality of second output voltages are combined into the plurality of second output voltages, respectively and the plurality of second output voltages are provided to the second subset of the power amplification components, respectively. a first DC(direct current)-DC converter, coupled to each of the power amplification components of the first subset of the power amplification components, the first DC-DC converter being configured to provide a plurality of first output voltages (VAPT1-VATPN) and/or a plurality of DC intermediate voltages (VHF1-VHFM), the plurality of first output voltages being provided to the first subset of the power amplification components, respectively; a second DC-DC converter, coupled to the first DC-DC converter and each of the power amplification components of the second subset of the power amplification components, the second DC-DC converter being configured to provide a plurality of DC components (ET_DC1-ET_DCM) of a plurality of second output voltages (VET1-VETM); a plurality of linear amplifiers (130_1-130_M), each of the plurality of linear amplifiers coupled between the first DC-DC converter and a respective one of the second subset of the power amplification components; and a plurality of bypass switches (140_1-140_M), each of the bypass switches of the plurality of bypass switches coupled to the first DC-DC converter and a respective one of the second subset of the power amplification components, for conducting the plurality of DC intermediate voltages directly to the second subset of the power amplification components, respectively, when the second subset of the power amplification components are to be operated under the APT mode, wherein the bypass switches are used to bypass the respective linear amplifiers when the second subset of the power amplification components are to be operated under the APT mode; wherein when the plurality of linear amplifiers receive the plurality of DC intermediate voltages from the first DC-DC converter, respectively, the plurality of linear amplifiers provide a plurality of AC components (ET_AC1-ET_ACM) of the plurality of second output voltages, respectively; wherein the plurality of DC components of the plurality of second output voltages and the plurality of AC components of the plurality of second output voltages are combined into the plurality of second output voltages, respectively and the plurality of second output voltages are provided to the second subset of the power amplification components, respectively.