A method for the manufacture of a semiconductor device comprising: forming a first element forming layer (501a, 301b) over a first substrate; forming a second element forming layer (502a, 302b) over a second substrate (500, 300b) and attaching the first element forming layer (501a, 301b) and the second element forming layer (502a, 302b) by an adhesive layer; wherein the first element forming layer (501a, 301b) includes a first transistor provided over an insulating layer, a second transistor provided over the insulating layer, a first conductive layer which functions as a source wiring or a drain wiring of the first transistor, and a second conductive layer which functions as a source wiring or a drain wiring of the second transistor; wherein the second element forming layer (502a, 302b) includes a memory element (454, 354) comprising a third conductive layer (453, 353) an organic compound layer (452, 352) or a phase change layer (452, 352), and a fourth conductive layer (451, 351) laminated in this order and a conductive layer which functions as an antenna; wherein the adhesive layer contains conductive particles; wherein the first conductive layer which functions as the source wiring or the drain wiring of the first transistor is electrically connected to the fourth conductive layer (451, 351) through at least a first conductive particle of the conductive particles; wherein the second conductive layer which functions as the source wiring or the drain wiring of the second transistor is electrically connected to the conductive layer which functions as the antenna through at least a second conductive particle of the conductive particles; and wherein the conductive layer which functions as the antenna is formed at the same time as the fourth conductive layer (451, 351). forming a first element forming layer (501a, 301b) over a first substrate; forming a second element forming layer (502a, 302b) over a second substrate (500, 300b) and attaching the first element forming layer (501a, 301b) and the second element forming layer (502a, 302b) by an adhesive layer; wherein the first element forming layer (501a, 301b) includes a first transistor provided over an insulating layer, a second transistor provided over the insulating layer, a first conductive layer which functions as a source wiring or a drain wiring of the first transistor, and a second conductive layer which functions as a source wiring or a drain wiring of the second transistor; wherein the second element forming layer (502a, 302b) includes a memory element (454, 354) comprising a third conductive layer (453, 353) an organic compound layer (452, 352) or a phase change layer (452, 352), and a fourth conductive layer (451, 351) laminated in this order and a conductive layer which functions as an antenna; wherein the adhesive layer contains conductive particles; wherein the first conductive layer which functions as the source wiring or the drain wiring of the first transistor is electrically connected to the fourth conductive layer (451, 351) through at least a first conductive particle of the conductive particles; wherein the second conductive layer which functions as the source wiring or the drain wiring of the second transistor is electrically connected to the conductive layer which functions as the antenna through at least a second conductive particle of the conductive particles; and wherein the conductive layer which functions as the antenna is formed at the same time as the fourth conductive layer (451, 351).