A method for forming a memory, comprising: providing a semiconductor structure; and forming a memory cell on the semiconductor structure, the memory cell being electrically coupled to a second doped region, wherein providing the semiconductor structure comprising: providing a substrate, wherein a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate,; etching the active layer and the sacrificial layer to form active lines along a first direction; forming first isolation layers that fill spacing between the active lines; etching end portions of the active lines to form openings exposing the sacrificial layer; removing the sacrificial layer along the openings, and forming gaps between a bottom of the active lines and the substrate; filling the gaps with a conductive material to form bit lines extending along the first direction; filling the openings with the conductive material to form bit line connecting lines located in the openings, wherein a bottom of the bit line connecting lines is connected to the bit lines; patterning the active lines to form a plurality of active columns that are discrete, the plurality of active columns being arranged in an array along the first direction and a second direction; and forming a first doped region, a channel region, and a second doped region that are located on a bottom of an active column and sequentially arranged upwards, and forming a gate structure surrounding the channel region. providing a semiconductor structure; and forming a memory cell on the semiconductor structure, the memory cell being electrically coupled to a second doped region, wherein providing the semiconductor structure comprising: providing a substrate, wherein a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate,; etching the active layer and the sacrificial layer to form active lines along a first direction; forming first isolation layers that fill spacing between the active lines; etching end portions of the active lines to form openings exposing the sacrificial layer; removing the sacrificial layer along the openings, and forming gaps between a bottom of the active lines and the substrate; filling the gaps with a conductive material to form bit lines extending along the first direction; filling the openings with the conductive material to form bit line connecting lines located in the openings, wherein a bottom of the bit line connecting lines is connected to the bit lines; patterning the active lines to form a plurality of active columns that are discrete, the plurality of active columns being arranged in an array along the first direction and a second direction; and forming a first doped region, a channel region, and a second doped region that are located on a bottom of an active column and sequentially arranged upwards, and forming a gate structure surrounding the channel region. providing a substrate, wherein a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate,; etching the active layer and the sacrificial layer to form active lines along a first direction; forming first isolation layers that fill spacing between the active lines; etching end portions of the active lines to form openings exposing the sacrificial layer; removing the sacrificial layer along the openings, and forming gaps between a bottom of the active lines and the substrate; filling the gaps with a conductive material to form bit lines extending along the first direction; filling the openings with the conductive material to form bit line connecting lines located in the openings, wherein a bottom of the bit line connecting lines is connected to the bit lines; patterning the active lines to form a plurality of active columns that are discrete, the plurality of active columns being arranged in an array along the first direction and a second direction; and forming a first doped region, a channel region, and a second doped region that are located on a bottom of an active column and sequentially arranged upwards, and forming a gate structure surrounding the channel region.