A system for therapeutic treatments with electromagnetic waves, comprising an antenna and an apparatus configured to generate a supply current (i out) for said antenna in order to generate said electromagnetic wave, wherein said apparatus comprises: - a digital processing circuit configured to generate a first PWM signal having a given duty cycle, wherein said first PWM signal is set, for each switching cycle (Tsw), to high for a switch-on period (Torr) and to low for a switch-off period (T OFF); - a switching stage configured to generate an amplified PWM signal (V 240) by amplifying said first PWM signal; - an analog low-pass or band-pass filter configured to generate said supply current (i out) by filtering said amplified PWM signal (V 240); - a current sensor configured to provide a digital sample (CS D) indicative of the amplitude of said supply current (i out); wherein said digital processing circuit is configured to: - generate a sequence of first digital values (S imp) of a periodic base pulse having a given frequency (f imp); - generate a second PWM signal (PWM P), wherein said second PWM signal (PWM P) is set, for each switching cycle (T pac), to a respective first logic level for a packet switch-on period (T pac_on) and to a respective second logic level for a packet switch-off period (T pac_off); - generate a third PWM signal (PWM Tr), wherein said third PWM signal (PWM Tr) is set, for each switching cycle (T tr), to a respective first logic level for a train switch-on period (T tr_on) and to a respective second logic level for a train switch-off period (T tr_off); - generate an enable signal, wherein said enable signal is set to a respective first logic level when said second PWM signal (PWM P) has the respective first logic level and said third PWM signal (PWM Tr) has the respective first logic level, and to a respective second logic level when said second PWM signal (PWM P) has the respective second logic level or said third PWM signal (PWM Tr) has the respective second logic level; - generate a second digital value (S D), wherein the second digital value (S D) is set to the first digital value (S imp) when said enable signal has the respective first logic level and to zero when said enable signal has the respective second logic level; - generate said first PWM signal as a function of a third digital value indicative of said given duty cycle; - vary said third digital value via a discrete proportional-integral regulation configured to regulate the difference between said second digital value (S D) and said digital sample (CS D) to zero. - a digital processing circuit configured to generate a first PWM signal having a given duty cycle, wherein said first PWM signal is set, for each switching cycle (Tsw), to high for a switch-on period (Torr) and to low for a switch-off period (T OFF); - a switching stage configured to generate an amplified PWM signal (V 240) by amplifying said first PWM signal; - an analog low-pass or band-pass filter configured to generate said supply current (i out) by filtering said amplified PWM signal (V 240); - a current sensor configured to provide a digital sample (CS D) indicative of the amplitude of said supply current (i out); - generate a sequence of first digital values (S imp) of a periodic base pulse having a given frequency (f imp); - generate a second PWM signal (PWM P), wherein said second PWM signal (PWM P) is set, for each switching cycle (T pac), to a respective first logic level for a packet switch-on period (T pac_on) and to a respective second logic level for a packet switch-off period (T pac_off); - generate a third PWM signal (PWM Tr), wherein said third PWM signal (PWM Tr) is set, for each switching cycle (T tr), to a respective first logic level for a train switch-on period (T tr_on) and to a respective second logic level for a train switch-off period (T tr_off); - generate an enable signal, wherein said enable signal is set to a respective first logic level when said second PWM signal (PWM P) has the respective first logic level and said third PWM signal (PWM Tr) has the respective first logic level, and to a respective second logic level when said second PWM signal (PWM P) has the respective second logic level or said third PWM signal (PWM Tr) has the respective second logic level; - generate a second digital value (S D), wherein the second digital value (S D) is set to the first digital value (S imp) when said enable signal has the respective first logic level and to zero when said enable signal has the respective second logic level; - generate said first PWM signal as a function of a third digital value indicative of said given duty cycle; - vary said third digital value via a discrete proportional-integral regulation configured to regulate the difference between said second digital value (S D) and said digital sample (CS D) to zero.