A power quad flat no-lead (PQFN) semiconductor package comprising: a leadframe comprising a plurality of die pads; a driver integrated circuit coupled to a first die pad of the leadframe; a plurality of vertical conduction power devices (140a-140f) including a first group of vertical conduction power devices (140a-140c) coupled to a second die pad of the leadframe and a second group of vertical conduction power devices (140d-140f) individually coupled to corresponding die pads (150d-150f) of the leadframe; a plurality of wirebonds (170a, 170b) providing electrical interconnects between the driver IC, the plurality of vertical conduction power devices (140a-140f), and a plurality of external leads of the leadframe, wherein a top surface electrode of one of the first group of vertical conduction power devices is electrically connected to a portion of the leadframe by a wirebond, wherein the driver IC is electrically connected to the portion of the leadframe by a wirebond, and wherein the portion of the leadframe is electrically connected to a bottom surface electrode of one of the second group of vertical conduction power devices, wherein the package is configured as a full bridge power device, wherein the first group of vertical power devices (140a-140c) comprises high side field-effect transistors (FETs) of the full bridge power device and the second group of vertical power devices (140d-140f) comprises low side field-effect transistors (FETs) of the full bridge power device, wherein drain electrodes of the first group of vertical power devices (140a-140c) are coupled to the second die pad of the leadframe, wherein drain electrodes of the second group of vertical power devices (140d-140f) are individually coupled to the corresponding die pads (150d-150f) of the leadframe, wherein the first die pad, the second die pad and the corresponding die pads (150d-150f) are exposed at a bottom surface of the leadframe, and wherein the PQFN package is encapsulated by a mold compound. a leadframe comprising a plurality of die pads; a driver integrated circuit coupled to a first die pad of the leadframe; a plurality of vertical conduction power devices (140a-140f) including a first group of vertical conduction power devices (140a-140c) coupled to a second die pad of the leadframe and a second group of vertical conduction power devices (140d-140f) individually coupled to corresponding die pads (150d-150f) of the leadframe; a plurality of wirebonds (170a, 170b) providing electrical interconnects between the driver IC, the plurality of vertical conduction power devices (140a-140f), and a plurality of external leads of the leadframe, wherein a top surface electrode of one of the first group of vertical conduction power devices is electrically connected to a portion of the leadframe by a wirebond, wherein the driver IC is electrically connected to the portion of the leadframe by a wirebond, and wherein the portion of the leadframe is electrically connected to a bottom surface electrode of one of the second group of vertical conduction power devices, wherein the first group of vertical power devices (140a-140c) comprises high side field-effect transistors (FETs) of the full bridge power device and the second group of vertical power devices (140d-140f) comprises low side field-effect transistors (FETs) of the full bridge power device, wherein drain electrodes of the first group of vertical power devices (140a-140c) are coupled to the second die pad of the leadframe, wherein drain electrodes of the second group of vertical power devices (140d-140f) are individually coupled to the corresponding die pads (150d-150f) of the leadframe, wherein the first die pad, the second die pad and the corresponding die pads (150d-150f) are exposed at a bottom surface of the leadframe, and wherein the PQFN package is encapsulated by a mold compound.