A clock data recovery circuit comprising: a first phase detection circuit adapted to compare a phase of a first periodic signal (RCKD) to a phase of a second periodic signal (FBCLK) to generate a first control signal (UPPF, DNPF) indicative of a difference between the phases of the first periodic signal (RCKD) and the second periodic signal (FBCLK); a phase adjustment circuit adapted to cause the phase of the second periodic signal (FBCLK) and a phase of a third periodic signal (CLKL1) to vary based on a variation in the first control signal (UPPF, DNPF); a sampler circuit (210, 222) adapted to sample a data signal (DXP, DXN) to generate a sampled data signal (DE, DEB, DO, DOB) in response to the third periodic signal (CLKL1); a first frequency divider circuit adapted to generate the third periodic signal (CLKL1) based on a fourth periodic signal; a second frequency divider circuit adapted to generate the second periodic signal (FBCLK) based on a fifth periodic signal (CLKL2); and wherein the phase adjustment circuit is adapted to cause phases of the fourth periodic signal and the fifth periodic signal (CLKL2) to vary based on a change in the first control signal (UPPF, DNPF); characterized by a control circuit adapted to adjust a frequency of the third periodic signal (CLKL1) by varying a frequency division value of the first frequency divider circuit in response to the data signal (DE, DEB, DO, DOB) changing from a first data rate to a second data rate, while maintaining a frequency of the second periodic signal (FBCLK) constant, wherein the control circuit is adapted to adjust the frequency of the second periodic signal (FBCLK) by varying frequency division value of the second frequency divider circuit and to adjust the frequency of the third periodic signal (CLKL1) by varying a frequency division value of the first frequency divider circuit in response to the data signal (DE, DEB, DO, DOB) changing from the second data rate to a third data rate, wherein the first, second, and third data rates that are based on at least three data transmission protocols. a first phase detection circuit adapted to compare a phase of a first periodic signal (RCKD) to a phase of a second periodic signal (FBCLK) to generate a first control signal (UPPF, DNPF) indicative of a difference between the phases of the first periodic signal (RCKD) and the second periodic signal (FBCLK); a phase adjustment circuit adapted to cause the phase of the second periodic signal (FBCLK) and a phase of a third periodic signal (CLKL1) to vary based on a variation in the first control signal (UPPF, DNPF); a sampler circuit (210, 222) adapted to sample a data signal (DXP, DXN) to generate a sampled data signal (DE, DEB, DO, DOB) in response to the third periodic signal (CLKL1); a first frequency divider circuit adapted to generate the third periodic signal (CLKL1) based on a fourth periodic signal; a second frequency divider circuit adapted to generate the second periodic signal (FBCLK) based on a fifth periodic signal (CLKL2); and wherein the phase adjustment circuit is adapted to cause phases of the fourth periodic signal and the fifth periodic signal (CLKL2) to vary based on a change in the first control signal (UPPF, DNPF); characterized by a control circuit adapted to adjust a frequency of the third periodic signal (CLKL1) by varying a frequency division value of the first frequency divider circuit in response to the data signal (DE, DEB, DO, DOB) changing from a first data rate to a second data rate, while maintaining a frequency of the second periodic signal (FBCLK) constant, wherein the control circuit is adapted to adjust the frequency of the second periodic signal (FBCLK) by varying frequency division value of the second frequency divider circuit and to adjust the frequency of the third periodic signal (CLKL1) by varying a frequency division value of the first frequency divider circuit in response to the data signal (DE, DEB, DO, DOB) changing from the second data rate to a third data rate, wherein the first, second, and third data rates that are based on at least three data transmission protocols.