A driver circuit comprising: a first transistor connected between a line of a first voltage and an output terminal; a second transistor connected between said output terminal and a line of a second voltage lower than said first voltage; a first control circuit including first and second power supply nodes (1c,1d), for supplying a voltage of said first power supply node to a control electrode of said first transistor to turn said first transistor on in response to setting of an input signal to a first logic level, and for supplying a voltage of said second power supply node to the control electrode of said first transistor to turn said first transistor off in response to setting of said input signal to a second logic level; and a second control circuit including third and fourth power supply nodes (2c, 2d), for supplying a voltage of said fourth power supply node to a control electrode of said second transistor to turn said second transistor off in response to setting of said input signal to said first logic level, and for supplying a voltage of said third power supply node to the control electrode of said second transistor to turn said second transistor on in response to setting of said input signal to said second logic level; said first power supply node being connected to said output terminal, said third power supply node receiving said second voltage, said fourth power supply node receiving a third voltage lower than said second voltage, each of said first and second transistors being a normally-on type n-channel FET made of a wide band gap semiconductor, said driver circuit further comprising: a capacitor connected between said first and second power supply nodes; a switch element connected between said second and fourth power supply nodes; and a third control circuit for turning said switch element on to charge said capacitor in response to a decrease in a voltage corresponding to a difference between a voltage of said output terminal and said second voltage to a level lower than a predetermined voltage. a first transistor connected between a line of a first voltage and an output terminal; a second transistor connected between said output terminal and a line of a second voltage lower than said first voltage; a first control circuit including first and second power supply nodes (1c,1d), for supplying a voltage of said first power supply node to a control electrode of said first transistor to turn said first transistor on in response to setting of an input signal to a first logic level, and for supplying a voltage of said second power supply node to the control electrode of said first transistor to turn said first transistor off in response to setting of said input signal to a second logic level; and a second control circuit including third and fourth power supply nodes (2c, 2d), for supplying a voltage of said fourth power supply node to a control electrode of said second transistor to turn said second transistor off in response to setting of said input signal to said first logic level, and for supplying a voltage of said third power supply node to the control electrode of said second transistor to turn said second transistor on in response to setting of said input signal to said second logic level; said first power supply node being connected to said output terminal, said third power supply node receiving said second voltage, said fourth power supply node receiving a third voltage lower than said second voltage, each of said first and second transistors being a normally-on type n-channel FET made of a wide band gap semiconductor, said driver circuit further comprising: a capacitor connected between said first and second power supply nodes; a switch element connected between said second and fourth power supply nodes; and a third control circuit for turning said switch element on to charge said capacitor in response to a decrease in a voltage corresponding to a difference between a voltage of said output terminal and said second voltage to a level lower than a predetermined voltage. a capacitor connected between said first and second power supply nodes; a switch element connected between said second and fourth power supply nodes; and a third control circuit for turning said switch element on to charge said capacitor in response to a decrease in a voltage corresponding to a difference between a voltage of said output terminal and said second voltage to a level lower than a predetermined voltage.