A transmitter, comprising: a clock generator that generates an in-phase differential clock signal and a quadrature-phase differential clock signal, a multiplexer circuit configured to serialize an input signal to generate an output signal based on a four-phase clock signal including an in-phase clock signal (cki), an anti-in-phase clock signal (cki_b), a quadrature-phase clock signal (ckq) and an anti-quadrature-phase clock signal (ckq_b) obtained from the in-phase differential clock signal and the quadrature-phase differential clock signal; a first pair of clock correction circuits (304 1, 304 2) that output the in-phase (cki) and the anti-in-phase clock signals (cki_b), respectively, of the four-phase clock signal; a second pair of clock correction circuits (304 3, 304 4) that output the quadrature-phase (ckq) and the anti-quadrature-phase clock signals (ckq_b), respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase phase mismatch in the four-phase clock signal; a calibration circuit configured to supply a first pair of control signals (312I 1, 312I 2) to each of the first pair of clock correction circuits (304 1, 304 2), and a second pair of control signals (312Q 1, 312Q 2) to each of the second pair of clock correction circuits (304 3, 304 4), to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit; and wherein each clock correction circuit of the first pair of clock correction circuits (304 1, 304 2) comprises a first inverter, at least one second inverter coupled to the input of the first inverter, at least one third inverter coupled to the output of the first inverter, and a control circuit coupled in parallel with the first inverter, the control circuit of the first pair of clock correction circuits (304 1, 304 2) each receiving the first pair of control signals (312I 1, 312I 2), and wherein each clock correction circuit of the second pair of clock correction circuits (304 3, 304 4) comprises a first inverter, at least one second inverter coupled to the input of the first inverter, at least one third inverter coupled to the output of the first inverter, and a control circuit coupled in parallel with the first inverter, thecontrol circuit of the second pair of control circuits (304 1, 304 2) each receiving the second pair of control signals (312Q 1, 312Q 2), wherein the third inverters of the first pair of clock correction circuits (304 1, 304 2) provide the in-phase and anti-in-phase clock signals (cki, cki_b), respectively, to the detector circuit, and wherein the third inverters of the second pair of clock correction circuits (304 3, 304 4) provide the quadrature-phase and the anti-quadrature phase clock signals (ckq, ckq_b), respectively, to the detector circuit. a clock generator that generates an in-phase differential clock signal and a quadrature-phase differential clock signal, a multiplexer circuit configured to serialize an input signal to generate an output signal based on a four-phase clock signal including an in-phase clock signal (cki), an anti-in-phase clock signal (cki_b), a quadrature-phase clock signal (ckq) and an anti-quadrature-phase clock signal (ckq_b) obtained from the in-phase differential clock signal and the quadrature-phase differential clock signal; a first pair of clock correction circuits (304 1, 304 2) that output the in-phase (cki) and the anti-in-phase clock signals (cki_b), respectively, of the four-phase clock signal; a second pair of clock correction circuits (304 3, 304 4) that output the quadrature-phase (ckq) and the anti-quadrature-phase clock signals (ckq_b), respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase phase mismatch in the four-phase clock signal; a calibration circuit configured to supply a first pair of control signals (312I 1, 312I 2) to each of the first pair of clock correction circuits (304 1, 304 2), and a second pair of control signals (312Q 1, 312Q 2) to each of the second pair of clock correction circuits (304 3, 304 4), to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit; and wherein each clock correction circuit of the first pair of clock correction circuits (304 1, 304 2) comprises a first inverter, at least one second inverter coupled to the input of the first inverter, at least one third inverter coupled to the output of the first inverter, and a control circuit coupled in parallel with the first inverter, the control circuit of the first pair of clock correction circuits (304 1, 304 2) each receiving the first pair of control signals (312I 1, 312I 2), and wherein each clock correction circuit of the second pair of clock correction circuits (304 3, 304 4) comprises a first inverter, at least one second inverter coupled to the input of the first inverter, at least one third inverter coupled to the output of the first inverter, and a control circuit coupled in parallel with the first inverter, thecontrol circuit of the second pair of control circuits (304 1, 304 2) each receiving the second pair of control signals (312Q 1, 312Q 2), wherein the third inverters of the first pair of clock correction circuits (304 1, 304 2) provide the in-phase and anti-in-phase clock signals (cki, cki_b), respectively, to the detector circuit, and wherein the third inverters of the second pair of clock correction circuits (304 3, 304 4) provide the quadrature-phase and the anti-quadrature phase clock signals (ckq, ckq_b), respectively, to the detector circuit.