A thin film transistor array substrate comprising: a substrate; a gate line formed on the substrate; a first gate electrode formed on the substrate and branched from the gate line; a gate insulating film formed over the substrate so as to cover the gate line and the first gate electrode; an active layer formed on the gate insulating film so as to overlap with at least a portion of the first gate electrode; a data line formed on the gate insulating film to cross the gate line, wherein the data line includes a plurality of metal layers (111, 112) comprising a first metal layer and a second metal layer formed of copper (Cu); a source electrode formed on the gate insulating film and branched from the data line so as to overlap with a first side of the active layer; a drain electrode formed on the gate insulating film and spaced apart from the source electrode so as to overlap with a second side of the active layer; an interlayer insulating film formed over the gate insulating film so as to cover the data line, the source electrode, and the drain electrode; and a pixel electrode formed on the interlayer insulating film and connected to the drain electrode via a first contact hole penetrating the interlayer insulating film to expose at least a portion of the drain electrode; and a second gate electrode formed on the interlayer insulating film so as to overlap with at least a portion of the active layer and connected to the first gate electrode via a second contact hole penetrating the interlayer insulating film and the gate insulating film to expose at least a portion of any one of the first gate electrode and the gate line, characterized in that the source electrode and the drain electrode include the remaining metal layer excluding the second metal layer among the plurality of the metal layers (111, 112) for preventing a short circuit between any one of the source electrode and the drain electrode and the second gate electrode formed thereabove due to through-migration of copper. a substrate; a gate line formed on the substrate; a first gate electrode formed on the substrate and branched from the gate line; a gate insulating film formed over the substrate so as to cover the gate line and the first gate electrode; an active layer formed on the gate insulating film so as to overlap with at least a portion of the first gate electrode; a data line formed on the gate insulating film to cross the gate line, wherein the data line includes a plurality of metal layers (111, 112) comprising a first metal layer and a second metal layer formed of copper (Cu); a source electrode formed on the gate insulating film and branched from the data line so as to overlap with a first side of the active layer; a drain electrode formed on the gate insulating film and spaced apart from the source electrode so as to overlap with a second side of the active layer; an interlayer insulating film formed over the gate insulating film so as to cover the data line, the source electrode, and the drain electrode; and a pixel electrode formed on the interlayer insulating film and connected to the drain electrode via a first contact hole penetrating the interlayer insulating film to expose at least a portion of the drain electrode; and a second gate electrode formed on the interlayer insulating film so as to overlap with at least a portion of the active layer and connected to the first gate electrode via a second contact hole penetrating the interlayer insulating film and the gate insulating film to expose at least a portion of any one of the first gate electrode and the gate line, characterized in that the source electrode and the drain electrode include the remaining metal layer excluding the second metal layer among the plurality of the metal layers (111, 112) for preventing a short circuit between any one of the source electrode and the drain electrode and the second gate electrode formed thereabove due to through-migration of copper.