A device, comprising: a pair of serializer/deserializers (32, 34; 50, 52; 12, 14) implemented in semiconductor circuitry, each serializer/deserializer having a parallel in serial out, PISO, and a serial in parallel out, SIPO, device with a serial communication line (18; 20) provided therebetween, that together constitutes a SerDes lane (36, 38, 40, 42); and an error detection system associated with the SerDes lane, the error detection system being adapted to detect when the SerDes lane is invalid, wherein the error detection system includes at a transmit side (32; 50; 12) of the SerDes lane means for determining a hash code of a packet of data in the SerDes lane and for sending the determined hash code along with the associated packet of data to a receive side (34, 52; 14) of the SerDes lane, and at a receive side of the SerDes lane means for calculating a hash code of the received packet of data in the SerDes lane and for comparing the calculated hash code to the received hash code, and for determining that the SerDes lane is invalid when the hash code calculated by the receive side of the SerDes lane is different than the hash code received from the transmit side of the SerDes lane; a communication link to provide information about an invalid SerDes lane (36, 38, 40, 42), from the receive side (34; 52; 14) to the transmit side (32; 50; 12); an error correction system associated with one or more SerDes lanes to reconstruct data in the SerDes lane when it is determined that the SerDes lane is invalid, the error correction system including a parity lane associated with one or more SerDes lanes (36, 38, 40, 42), the error correction system is configured to include parity information into the parity lane based on an Exclusive OR product of the bit value on each of the associated one or more SerDes lanes; and wherein the receive side is adapted to communicate an invalid indicator to the transmit side over the communication link; wherein the transmit side of the SerDes lane is configured to perform an operation to reset the SerDes lane when the transmit side of the SerDes lane receives the invalid indicator from the receive side of the SerDes lane via the communication link, indicating that the SerDes lane is invalid, and wherein the error correction system is configured to use the received parity information to reconstruct bits in a SerDes lane that has been determined to be invalid. a pair of serializer/deserializers (32, 34; 50, 52; 12, 14) implemented in semiconductor circuitry, each serializer/deserializer having a parallel in serial out, PISO, and a serial in parallel out, SIPO, device with a serial communication line (18; 20) provided therebetween, that together constitutes a SerDes lane (36, 38, 40, 42); and an error detection system associated with the SerDes lane, the error detection system being adapted to detect when the SerDes lane is invalid, wherein the error detection system includes at a transmit side (32; 50; 12) of the SerDes lane means for determining a hash code of a packet of data in the SerDes lane and for sending the determined hash code along with the associated packet of data to a receive side (34, 52; 14) of the SerDes lane, and at a receive side of the SerDes lane means for calculating a hash code of the received packet of data in the SerDes lane and for comparing the calculated hash code to the received hash code, and for determining that the SerDes lane is invalid when the hash code calculated by the receive side of the SerDes lane is different than the hash code received from the transmit side of the SerDes lane; a communication link to provide information about an invalid SerDes lane (36, 38, 40, 42), from the receive side (34; 52; 14) to the transmit side (32; 50; 12); an error correction system associated with one or more SerDes lanes to reconstruct data in the SerDes lane when it is determined that the SerDes lane is invalid, the error correction system including a parity lane associated with one or more SerDes lanes (36, 38, 40, 42), the error correction system is configured to include parity information into the parity lane based on an Exclusive OR product of the bit value on each of the associated one or more SerDes lanes; and wherein the receive side is adapted to communicate an invalid indicator to the transmit side over the communication link; wherein the transmit side of the SerDes lane is configured to perform an operation to reset the SerDes lane when the transmit side of the SerDes lane receives the invalid indicator from the receive side of the SerDes lane via the communication link, indicating that the SerDes lane is invalid, and wherein the error correction system is configured to use the received parity information to reconstruct bits in a SerDes lane that has been determined to be invalid.