A packaged semiconductor device (100, 220), comprising: an interface die (101, 125, 227), a storage die (103, 229), a substrate, wherein the interface die (101, 125, 227) and the storage die (103, 229) are disposed on the substrate, the storage die (103, 229) comprises independently accessible storage arrays (104 1, 104 2, 104 3, 104 4), the interface die (101, 125, 227) comprising: a core logic block comprising a command decode circuitry, a timing circuitry and a data serializing and deserializing circuitry, a first memory array interface (105 1 - 105 4, 137 1 - 137 4) coupled to a first set of signaling paths for communicating a first set of row control signals and column control signals from the interface die (101, 125, 227) to the storage die (103, 229) and a second memory array interface (105 1 - 105 4, 137 1 - 137 4) coupled to a second set of signaling paths for communicating a second set of row control signals and column control signals from the interface die (101, 125, 227) to the storage die (103, 229), wherein the first set of signaling paths and the second set of signaling paths each route command, address and data signals; and wherein the core logic block is adapted to use the first memory array interface (105 1 - 105 4, 137 1 - 137 4) to facilitate a first memory transaction with the independently accessible storage arrays (104 1, 104 2, 104 3, 104 4) of the storage die (103, 229), and the second memory array interface (105 1 - 105 4, 137 1 - 137 4) to facilitate a second memory transaction with the independently accessible storage arrays (104 1, 104 2, 104 3, 104 4) of the storage die (103, 229). an interface die (101, 125, 227), a storage die (103, 229), a substrate, wherein the interface die (101, 125, 227) and the storage die (103, 229) are disposed on the substrate, the storage die (103, 229) comprises independently accessible storage arrays (104 1, 104 2, 104 3, 104 4), the interface die (101, 125, 227) comprising: a core logic block comprising a command decode circuitry, a timing circuitry and a data serializing and deserializing circuitry, a first memory array interface (105 1 - 105 4, 137 1 - 137 4) coupled to a first set of signaling paths for communicating a first set of row control signals and column control signals from the interface die (101, 125, 227) to the storage die (103, 229) and a second memory array interface (105 1 - 105 4, 137 1 - 137 4) coupled to a second set of signaling paths for communicating a second set of row control signals and column control signals from the interface die (101, 125, 227) to the storage die (103, 229), wherein the first set of signaling paths and the second set of signaling paths each route command, address and data signals; and a core logic block comprising a command decode circuitry, a timing circuitry and a data serializing and deserializing circuitry, a first memory array interface (105 1 - 105 4, 137 1 - 137 4) coupled to a first set of signaling paths for communicating a first set of row control signals and column control signals from the interface die (101, 125, 227) to the storage die (103, 229) and a second memory array interface (105 1 - 105 4, 137 1 - 137 4) coupled to a second set of signaling paths for communicating a second set of row control signals and column control signals from the interface die (101, 125, 227) to the storage die (103, 229), wherein the first set of signaling paths and the second set of signaling paths each route command, address and data signals; and wherein the core logic block is adapted to use the first memory array interface (105 1 - 105 4, 137 1 - 137 4) to facilitate a first memory transaction with the independently accessible storage arrays (104 1, 104 2, 104 3, 104 4) of the storage die (103, 229), and the second memory array interface (105 1 - 105 4, 137 1 - 137 4) to facilitate a second memory transaction with the independently accessible storage arrays (104 1, 104 2, 104 3, 104 4) of the storage die (103, 229). the first memory array interface (105 1 - 105 4, 137 1 - 137 4) to facilitate a first memory transaction with the independently accessible storage arrays (104 1, 104 2, 104 3, 104 4) of the storage die (103, 229), and the second memory array interface (105 1 - 105 4, 137 1 - 137 4) to facilitate a second memory transaction with the independently accessible storage arrays (104 1, 104 2, 104 3, 104 4) of the storage die (103, 229).