A system, comprising: a first phase-locked loop configured to: receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal, the system characterized by: a frequency change limiter coupled to the first PLL and configured to: receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate; and a second PLL configured to: receive the first signal from the frequency change limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output. a first phase-locked loop configured to: receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal, the system characterized by: a frequency change limiter coupled to the first PLL and configured to: receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate; and a second PLL configured to: receive the first signal from the frequency change limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output. receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal, the system characterized by: a frequency change limiter coupled to the first PLL and configured to: receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate; and a second PLL configured to: receive the first signal from the frequency change limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output. a frequency change limiter coupled to the first PLL and configured to: receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate; and receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate; and a second PLL configured to: receive the first signal from the frequency change limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output. receive the first signal from the frequency change limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output.