CDR circuitry for receiving and processing a CDR data signal, the CDR circuitry comprising: reference clock dividing means for dividing a reference clock signal by a first user-programmable value and for providing the divided reference clock signal to a phase frequency detector circuitry; the phase frequency detector circuitry for receiving the divided reference clock signal from the reference clock dividing means and a divided first feedback clock signal from a first feedback clock dividing means, and for determining a phase and frequency error between the divided reference clock signal and the divided first feedback clock signal; a voltage controlled oscillator for outputting a clock signal recovered from the CDR data signal as a second feedback clock signal; second feedback clock dividing means for dividing the second feedback clock signal by a second user-programmable value; phase detector means for receiving the CDR data signal, for receiving a divided second feedback clock signal from the second feedback clock dividing means, and for determining a phase error between the divided second feedback clock signal and the CDR data signal; wherein the voltage controlled oscillator is adapted to speed up or slow down the recovered clock signal in response to either one of the phase and frequency error determined by the phase frequency detector circuitry or the phase error determined by the phase detector means; said first feedback clock dividing means for receiving the divided second feedback clock signal from the second feedback clock dividing means; for generating the divided first feedback clock signal by dividing the divided second feedback clock signal by a third user-programmable value and for providing the divided first feedback clock signal to the phase frequency detector circuitry; means for resetting the phase detector means and the phase frequency detector circuitry; and means for dynamically reprogramming the first user-programmable value, the second user-programmable value, and the third user-programmable value subsequent to resetting the phase detector means and the phase frequency detector circuitry. reference clock dividing means for dividing a reference clock signal by a first user-programmable value and for providing the divided reference clock signal to a phase frequency detector circuitry; the phase frequency detector circuitry for receiving the divided reference clock signal from the reference clock dividing means and a divided first feedback clock signal from a first feedback clock dividing means, and for determining a phase and frequency error between the divided reference clock signal and the divided first feedback clock signal; a voltage controlled oscillator for outputting a clock signal recovered from the CDR data signal as a second feedback clock signal; second feedback clock dividing means for dividing the second feedback clock signal by a second user-programmable value; phase detector means for receiving the CDR data signal, for receiving a divided second feedback clock signal from the second feedback clock dividing means, and for determining a phase error between the divided second feedback clock signal and the CDR data signal; wherein the voltage controlled oscillator is adapted to speed up or slow down the recovered clock signal in response to either one of the phase and frequency error determined by the phase frequency detector circuitry or the phase error determined by the phase detector means; said first feedback clock dividing means for receiving the divided second feedback clock signal from the second feedback clock dividing means; for generating the divided first feedback clock signal by dividing the divided second feedback clock signal by a third user-programmable value and for providing the divided first feedback clock signal to the phase frequency detector circuitry; means for resetting the phase detector means and the phase frequency detector circuitry; and means for dynamically reprogramming the first user-programmable value, the second user-programmable value, and the third user-programmable value subsequent to resetting the phase detector means and the phase frequency detector circuitry.