A flash memory system, comprising: a sector comprising a first row of flash memory cells and a second row of flash memory cells directly adjacent to the first row, each of the flash memory cells comprising a floating gate (29 or 30), a control gate terminal (27 or 28) located above the floating gate, a word line terminal (25 or 26) located adjacent to a first side of the floating gate, and a common erase gate terminal located adjacent to a second side of the floating gate, a common source line terminal, a bit line terminal (23 or 24), wherein the word line terminal of each flash memory cell in the first row is connected to a first word line and the word line terminal of each flash memory cell in the second row is connected to a second word line, the control gate terminal of each flash memory cell in the first row is connected to a first control gate line and the control gate terminal of each flash memory cell in the second row is connected to a second control gate line, the common erase gate terminal of each flash memory cell in the first row and the second row is connected to a common erase gate line; the common source line terminal of each flash memory cell in the first row and the second row is connected to a common source line; the bit line terminal of each flash memory cell in the first row is connected to a first bit line and the bit line terminal of each flash memory cell in the second row is connected to a second bit line; and wherein the system further comprises: control logic for inhibiting the erasing of the second row while erasing the first row by applying: a voltage between 3 and 20 volts to the common erase gate line, a bias voltage of -9 volts to the first control gate line, a bias voltage of 9 volts to the second control gate line, a negative bias voltage up to -5 volts to the first word line, a bias voltage between 0.8 and 5 volts to the second word line, and a bias voltage of 0 volt to the common source line, a bias voltage of 0 volt to both the first and second bit line. a sector comprising a first row of flash memory cells and a second row of flash memory cells directly adjacent to the first row, each of the flash memory cells comprising a floating gate (29 or 30), a control gate terminal (27 or 28) located above the floating gate, a word line terminal (25 or 26) located adjacent to a first side of the floating gate, and a common erase gate terminal located adjacent to a second side of the floating gate, a common source line terminal, a bit line terminal (23 or 24), wherein the word line terminal of each flash memory cell in the first row is connected to a first word line and the word line terminal of each flash memory cell in the second row is connected to a second word line, the control gate terminal of each flash memory cell in the first row is connected to a first control gate line and the control gate terminal of each flash memory cell in the second row is connected to a second control gate line, the common erase gate terminal of each flash memory cell in the first row and the second row is connected to a common erase gate line; the common source line terminal of each flash memory cell in the first row and the second row is connected to a common source line; the bit line terminal of each flash memory cell in the first row is connected to a first bit line and the bit line terminal of each flash memory cell in the second row is connected to a second bit line; and wherein the system further comprises: control logic for inhibiting the erasing of the second row while erasing the first row by applying: a voltage between 3 and 20 volts to the common erase gate line, a bias voltage of -9 volts to the first control gate line, a bias voltage of 9 volts to the second control gate line, a negative bias voltage up to -5 volts to the first word line, a bias voltage between 0.8 and 5 volts to the second word line, and a bias voltage of 0 volt to the common source line, a bias voltage of 0 volt to both the first and second bit line. a voltage between 3 and 20 volts to the common erase gate line, a bias voltage of -9 volts to the first control gate line, a bias voltage of 9 volts to the second control gate line, a negative bias voltage up to -5 volts to the first word line, a bias voltage between 0.8 and 5 volts to the second word line, and a bias voltage of 0 volt to the common source line, a bias voltage of 0 volt to both the first and second bit line.