A semiconductor package (312, 412) comprising: a composite field effect Transistor comprising a group IV FET (340, 440) cascoded with a high-voltage III-V transistor (330, 430), characterized in that said high-voltage III-V transistor (330, 430) includes a first drain (332, 432) and a first gate (336, 436) on a top side of said high-voltage III-V transistor (330, 430) and a first source (334, 434) on a bottom side of said high-voltage III-V transistor (330, 430) that is opposite to said top side of said high-voltage III-V transistor (330, 430), wherein said group IV FET (340, 440) includes a second drain (342, 442) on a top side of said group IV FET (340, 440) and a second source (344, 444) on a bottom side of said group IV FET (340, 440) that is opposite to said top side of said group IV FET (340, 440), wherein said high-voltage III-V transistor (330, 340) is situated so as to be die stacked on said group IV transitor (340, 440) and said first source (334, 434) of said high-voltage III-V transistor (330, 340) is coupled to said second drain (342, 442) of said group IV transistor (340, 440), and in that it comprises a drain contact (322, 422), a source contact (324, 424), and a gate contact (326, 426) on a top surface to provide external connections to said composite FET, a bottom surface including a gate conductive carrier segment (376, 476) and a source conductive carrier segment (374, 474), a packaging dielectric (350, 450) surrounding said drain contact (322, 422), said source contact (324, 424) and said gate contact (326, 426), wherein said drain contact (322, 422), said source contact (324, 424), and said gate contact (326, 426) are substantially coplanar with said packaging dielectric (350, 450) at a top surface of said packaging dielectric (350, 450), a contour element (358, 458, 558a) in the form of a groove or a ridge formed between said drain contact (322, 422) and said source contact (324, 424) in said packaging dielectric (350, 450), said contour element (358, 458) increasing a creepage distance between said drain contact (322, 422) and said source contact (324, 424) in said semiconductor package (312, 412) so as to increase a breakdown voltage of said semiconductor package (312, 412), wherein said first drain (332, 432) of said high-voltage III-V transistor (330, 430) is coupled to said drain contact (322, 422), said second source (344, 444) of said group IV FET (340, 440) is coupled to said source contact (324, 424) though said source conductive carrier segment and said first gate of said high-voltage III-V transistor (330, 430) is coupled to said source contact (324, 424) through said source conductive carrier (374, 474); and wherein a second gate (346, 436) of said group IV FET (340, 440) is coupled to said gate contact (326, 426). a composite field effect Transistor comprising a group IV FET (340, 440) cascoded with a high-voltage III-V transistor (330, 430), characterized in that said high-voltage III-V transistor (330, 430) includes a first drain (332, 432) and a first gate (336, 436) on a top side of said high-voltage III-V transistor (330, 430) and a first source (334, 434) on a bottom side of said high-voltage III-V transistor (330, 430) that is opposite to said top side of said high-voltage III-V transistor (330, 430), wherein said group IV FET (340, 440) includes a second drain (342, 442) on a top side of said group IV FET (340, 440) and a second source (344, 444) on a bottom side of said group IV FET (340, 440) that is opposite to said top side of said group IV FET (340, 440), wherein said high-voltage III-V transistor (330, 340) is situated so as to be die stacked on said group IV transitor (340, 440) and said first source (334, 434) of said high-voltage III-V transistor (330, 340) is coupled to said second drain (342, 442) of said group IV transistor (340, 440), and in that it comprises a drain contact (322, 422), a source contact (324, 424), and a gate contact (326, 426) on a top surface to provide external connections to said composite FET, a bottom surface including a gate conductive carrier segment (376, 476) and a source conductive carrier segment (374, 474), a packaging dielectric (350, 450) surrounding said drain contact (322, 422), said source contact (324, 424) and said gate contact (326, 426), wherein said drain contact (322, 422), said source contact (324, 424), and said gate contact (326, 426) are substantially coplanar with said packaging dielectric (350, 450) at a top surface of said packaging dielectric (350, 450), a contour element (358, 458, 558a) in the form of a groove or a ridge formed between said drain contact (322, 422) and said source contact (324, 424) in said packaging dielectric (350, 450), said contour element (358, 458) increasing a creepage distance between said drain contact (322, 422) and said source contact (324, 424) in said semiconductor package (312, 412) so as to increase a breakdown voltage of said semiconductor package (312, 412), wherein said first drain (332, 432) of said high-voltage III-V transistor (330, 430) is coupled to said drain contact (322, 422), said second source (344, 444) of said group IV FET (340, 440) is coupled to said source contact (324, 424) though said source conductive carrier segment and said first gate of said high-voltage III-V transistor (330, 430) is coupled to said source contact (324, 424) through said source conductive carrier (374, 474); and wherein a second gate (346, 436) of said group IV FET (340, 440) is coupled to said gate contact (326, 426).