A circuit arrangement, comprising: a logic circuit; a plurality of input register logic circuits (104-1... 104-P) each coupled to the logic circuit and each including a bi-stable circuit, wherein each of the bi-stable circuits is configured to receive an input data signal, wherein each of the input register logic circuits (104-1... 104P) includes a bypass path and a multiplexer circuit, wherein each multiplexer circuit is configured to select between the input data signal on the bypass path and an output signal from the bi-stable circuit to provide as an output data signal (144-1... 144-P) from the input register logic circuit (104-1... 104-P), and the logic circuit is configured to receive the plurality of output data signals (144-1...144P) from the plurality of input register logic circuits (104-1... 104-P); and a control circuit coupled to the input register logic circuits (104-1...104-P) and comprising clock modulation logic configured to: generate a plurality of delayed clock signals from an input clock signal, the plurality of delayed clock signals including a first delayed clock signal and a second delayed clock signal; selectively provide one or more of the delayed clock signals (306, 308) or the input clock signal to clock inputs of the bi-stable circuit; and selectively provide one or more of the delayed clock signals (306, 308) or the input clock signal to the logic circuit, wherein the clock modulation logic includes a variable clock delay logic circuit including a first delay circuit and a second delay circuit, wherein the first delay circuit is configured to generate the first delayed clock signal from the input clock signal, wherein the second delay circuit is configured to generate the second delayed clock signal from the output of the first delay circuit to make equal a clock delay to the plurality of input register logic circuits (104-1... 104-P) and a clock delay to the logic circuit. a logic circuit; a plurality of input register logic circuits (104-1... 104-P) each coupled to the logic circuit and each including a bi-stable circuit, wherein each of the bi-stable circuits is configured to receive an input data signal, wherein each of the input register logic circuits (104-1... 104P) includes a bypass path and a multiplexer circuit, wherein each multiplexer circuit is configured to select between the input data signal on the bypass path and an output signal from the bi-stable circuit to provide as an output data signal (144-1... 144-P) from the input register logic circuit (104-1... 104-P), and the logic circuit is configured to receive the plurality of output data signals (144-1...144P) from the plurality of input register logic circuits (104-1... 104-P); and a control circuit coupled to the input register logic circuits (104-1...104-P) and comprising clock modulation logic configured to: generate a plurality of delayed clock signals from an input clock signal, the plurality of delayed clock signals including a first delayed clock signal and a second delayed clock signal; selectively provide one or more of the delayed clock signals (306, 308) or the input clock signal to clock inputs of the bi-stable circuit; and selectively provide one or more of the delayed clock signals (306, 308) or the input clock signal to the logic circuit, generate a plurality of delayed clock signals from an input clock signal, the plurality of delayed clock signals including a first delayed clock signal and a second delayed clock signal; selectively provide one or more of the delayed clock signals (306, 308) or the input clock signal to clock inputs of the bi-stable circuit; and selectively provide one or more of the delayed clock signals (306, 308) or the input clock signal to the logic circuit, wherein the clock modulation logic includes a variable clock delay logic circuit including a first delay circuit and a second delay circuit, wherein the first delay circuit is configured to generate the first delayed clock signal from the input clock signal, wherein the second delay circuit is configured to generate the second delayed clock signal from the output of the first delay circuit to make equal a clock delay to the plurality of input register logic circuits (104-1... 104-P) and a clock delay to the logic circuit.