A control plane for controlling transfer of data to a data plane, the control plane comprising: a number n of at least two memory cells (D j) for each storing a digitally coded parameter value, wherein each memory cell (D j) has a data input electrode, a data output electrode and a control electrode; n data input terminals, wherein each data input terminal is configured to receive a data input value (α j) and to apply the received data input value (αj) to the data input electrode of an associated memory cell (D j) to which the data input terminal is coupled, and n data output terminals, wherein each data output terminal is coupled to a data output electrode of an associated memory cell (D j), wherein the control plane further comprises a first delay line comprising n or n-1 first delay elements (106 j-1, 106 j, 106 j+1), wherein each of the first delay elements (106 j-1, 106 j, 106 j+1) is associated with a corresponding memory cell (D j), the first delay line being arranged for receiving a stream of parameter control bits which are sequentially injected, the parameter control bits indicating whether the corresponding parameter value is used or not, and wherein each first delay element (106 j-1, 106 j, 106 j+1) controls, based on its current parameter control bit, by means of an associated access control device (108 j-1, 108 j, 108 j+1), the transfer of data received by each corresponding memory cell (Dj) via its associated data input terminal to its associated data output terminal, thereby combining the received data input value (αj) with the digitally coded parameter value stored in the corresponding memory cell (D j), and a second delay line comprising n or n-1 second delay elements (107 j-1, 107 j, 107 j+1), wherein each of the second delay elements (107 j-1, 107 j, 107 j+1) is associated with a corresponding memory cell (D j), the second delay line being arranged for receiving an enabling signal for enabling the parameter control bits of the stream of parameter control bits in the first delay line, by means of each associated access control device (108 j-1, 108 j, 108 j+1), to be passed to the control electrode of each associated memory cell (D j) such that, when data is input to the data input terminal associated with each memory cell (Dj), said data is combined with the digitally coded parameter value stored in the corresponding memory cell (D j) and a result is transferred in a controlled and synchronised fashion to the associated data output terminal, depending on the stream of parameter control bits and the enabling signal, each delay element of the first delay line and the second delay line which are associated with the same memory cell (D j) have a pairwise matched delay, the first delay line having a first delay and the second delay line having a second delay, wherein the second delay is substantially twice the value of the first delay. a number n of at least two memory cells (D j) for each storing a digitally coded parameter value, wherein each memory cell (D j) has a data input electrode, a data output electrode and a control electrode; n data input terminals, wherein each data input terminal is configured to receive a data input value (α j) and to apply the received data input value (αj) to the data input electrode of an associated memory cell (D j) to which the data input terminal is coupled, and n data output terminals, wherein each data output terminal is coupled to a data output electrode of an associated memory cell (D j), wherein the control plane further comprises a first delay line comprising n or n-1 first delay elements (106 j-1, 106 j, 106 j+1), wherein each of the first delay elements (106 j-1, 106 j, 106 j+1) is associated with a corresponding memory cell (D j), the first delay line being arranged for receiving a stream of parameter control bits which are sequentially injected, the parameter control bits indicating whether the corresponding parameter value is used or not, and wherein each first delay element (106 j-1, 106 j, 106 j+1) controls, based on its current parameter control bit, by means of an associated access control device (108 j-1, 108 j, 108 j+1), the transfer of data received by each corresponding memory cell (Dj) via its associated data input terminal to its associated data output terminal, thereby combining the received data input value (αj) with the digitally coded parameter value stored in the corresponding memory cell (D j), and a second delay line comprising n or n-1 second delay elements (107 j-1, 107 j, 107 j+1), wherein each of the second delay elements (107 j-1, 107 j, 107 j+1) is associated with a corresponding memory cell (D j), the second delay line being arranged for receiving an enabling signal for enabling the parameter control bits of the stream of parameter control bits in the first delay line, by means of each associated access control device (108 j-1, 108 j, 108 j+1), to be passed to the control electrode of each associated memory cell (D j) such that, when data is input to the data input terminal associated with each memory cell (Dj), said data is combined with the digitally coded parameter value stored in the corresponding memory cell (D j) and a result is transferred in a controlled and synchronised fashion to the associated data output terminal, depending on the stream of parameter control bits and the enabling signal, each delay element of the first delay line and the second delay line which are associated with the same memory cell (D j) have a pairwise matched delay, the first delay line having a first delay and the second delay line having a second delay, wherein the second delay is substantially twice the value of the first delay.