An analog-to-digital conversion, ADC, circuit to convert an analog input signal to a digital output signal, comprising: a sample-and-hold circuit configured to generate a sampled input signal from the analog input signal; a plurality of conversion stages coupled in series, each of the plurality of conversion stages configured to generate a bit for the digital output signal; and a data latch configured to receive bits for the digital output signal from the plurality of conversion stages and to provide the digital output signal based on the bits; wherein the ADC circuit is configured to be an asynchronous serial-ripple ADC configured to receive an external clock signal to trigger a comparator of a first conversion stage of the plurality of conversion stages, and wherein a conversion stage of the plurality of conversion stages includes: a comparator circuit (C1, C2, C3, CN) configured to compare the sampled input signal with a reference signal and to generate an associated bit for the digital output signal based on a result of the comparison; a multiplexer circuit (520, 522) configured to provide an associated reference signal to a comparator circuit (C1, C2, C3, CN) of a next conversion stage, the next conversion stage being subsequent to the conversion stage; and a decision detect circuit (530, 530A, 530B, 530C) configured to generate a clock pulse to trigger the comparator circuit (C1, C2, C3, CN) of the conversion stage in response to detecting an associated bit generated by a comparator circuit (C1, C2, C3, CN) of a prior conversion stage, the prior conversion stage preceding the conversion stage. a sample-and-hold circuit configured to generate a sampled input signal from the analog input signal; a plurality of conversion stages coupled in series, each of the plurality of conversion stages configured to generate a bit for the digital output signal; and a data latch configured to receive bits for the digital output signal from the plurality of conversion stages and to provide the digital output signal based on the bits; wherein the ADC circuit is configured to be an asynchronous serial-ripple ADC configured to receive an external clock signal to trigger a comparator of a first conversion stage of the plurality of conversion stages, and wherein a conversion stage of the plurality of conversion stages includes: a comparator circuit (C1, C2, C3, CN) configured to compare the sampled input signal with a reference signal and to generate an associated bit for the digital output signal based on a result of the comparison; a multiplexer circuit (520, 522) configured to provide an associated reference signal to a comparator circuit (C1, C2, C3, CN) of a next conversion stage, the next conversion stage being subsequent to the conversion stage; and a decision detect circuit (530, 530A, 530B, 530C) configured to generate a clock pulse to trigger the comparator circuit (C1, C2, C3, CN) of the conversion stage in response to detecting an associated bit generated by a comparator circuit (C1, C2, C3, CN) of a prior conversion stage, the prior conversion stage preceding the conversion stage. a comparator circuit (C1, C2, C3, CN) configured to compare the sampled input signal with a reference signal and to generate an associated bit for the digital output signal based on a result of the comparison; a multiplexer circuit (520, 522) configured to provide an associated reference signal to a comparator circuit (C1, C2, C3, CN) of a next conversion stage, the next conversion stage being subsequent to the conversion stage; and a decision detect circuit (530, 530A, 530B, 530C) configured to generate a clock pulse to trigger the comparator circuit (C1, C2, C3, CN) of the conversion stage in response to detecting an associated bit generated by a comparator circuit (C1, C2, C3, CN) of a prior conversion stage, the prior conversion stage preceding the conversion stage.