A method of making a monolithic three dimensional NAND string, comprising the following sequence of steps: forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, wherein the first material layers are silicon oxide layers and the second material layers are silicon nitride layers; etching the stack to form at least one front side opening in the stack; forming at least one blocking dielectric in the front side opening over a sidewall of the at least one front side opening; forming at least one charge storage region over the at least one blocking dielectric in the at least one front side opening; forming a tunnel dielectric layer over the at least one charge storage region in the at least one front side opening; forming a semiconductor channel material over the tunnel dielectric layer in the at least one front side opening; etching the stack to form at least one back side opening in the stack; selectively removing portions of the silicon nitride layers to form recesses between adjacent silicon oxide layers by selectively partially etching the silicon nitride layers through the back side opening to form the recesses containing remaining portions of the silicon nitride layers adjacent to the at least one blocking dielectric; and forming ruthenium control gate electrodes in the recesses by forming a ruthenium layer in the recesses by atomic layer deposition without forming a conductive barrier or nucleation layer in the recesses, wherein the step of forming the ruthenium layer comprises selectively forming thicker portions of the ruthenium layer in the recesses on the remaining portions of the silicon nitride layers than in the back side opening on edge portions of the silicon oxide layers, and removing the ruthenium layer from the back side opening to leave the ruthenium control gate electrodes in the recesses. forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, wherein the first material layers are silicon oxide layers and the second material layers are silicon nitride layers; etching the stack to form at least one front side opening in the stack; forming at least one blocking dielectric in the front side opening over a sidewall of the at least one front side opening; forming at least one charge storage region over the at least one blocking dielectric in the at least one front side opening; forming a tunnel dielectric layer over the at least one charge storage region in the at least one front side opening; forming a semiconductor channel material over the tunnel dielectric layer in the at least one front side opening; etching the stack to form at least one back side opening in the stack; selectively removing portions of the silicon nitride layers to form recesses between adjacent silicon oxide layers by selectively partially etching the silicon nitride layers through the back side opening to form the recesses containing remaining portions of the silicon nitride layers adjacent to the at least one blocking dielectric; and forming ruthenium control gate electrodes in the recesses by forming a ruthenium layer in the recesses by atomic layer deposition without forming a conductive barrier or nucleation layer in the recesses, wherein the step of forming the ruthenium layer comprises selectively forming thicker portions of the ruthenium layer in the recesses on the remaining portions of the silicon nitride layers than in the back side opening on edge portions of the silicon oxide layers, and removing the ruthenium layer from the back side opening to leave the ruthenium control gate electrodes in the recesses.