Amplifier circuit with a differential input (inn, inp) and a differential output (outn, outp) arranged in a differential current path of an output stage, the amplifier circuit comprising - a first pair of matched transistors (M1, M2) having a first threshold voltage and comprising control terminals connected to the differential input (inn, inp); - a second pair of matched transistors (M3, M4) having the first threshold voltage and comprising control terminals connected to the differential input (inn, inp), said second pair being part of voltage sources cross-coupling said first pair of matched transistors (M1, M2); - a first pair of triplets (LG1, LG2) of transistors having a second threshold voltage being different from the first threshold voltage, the transistors of each triplet (LG1, LG2) being commonly connected to a respective dedicated transistor of the first pair of matched transistors (M1, M2) such that a respective current path is formed with the dedicated transistor; - a second pair of triplets (LG3, LG4) of transistors having the second threshold voltage, the transistors of each triplet (LG3, LG4) being commonly connected to a respective dedicated transistor of the second pair of matched transistors (M3, M4) such that a respective current path is formed with the dedicated transistor; wherein - a first transistor (M1_1, M2_1, M3_1, M4_1) of each of the triplets has its control terminal connected to the control terminal of the respective dedicated transistor (M1, M2, M3, M4) connected in the current path and is matched to a second and a third transistor of the same triplet by a common matching ratio; - control terminals of the second and third transistors of each triplet are commonly connected to control terminals of the first transistors of the respective other triplet of the pair; - the first transistors (M1_1, M2_1) of the first pair of triplets (LG1, LG2) are connected to the differential current path of the output stage, to the second transistors (M3_2, M4_2) of the second pair of triplets (LG3, LG4), and to the respective second transistor (M2_2, M1_2) of the respective other triplet of the first pair of triplets (LG1, LG2); - the first transistors (M3_1, M4_1) of the second pair of triplets (LG3, LG4) are connected to a first pair of bias transistors (MBP1, MBP2) being part of the voltage sources, to the third transistors (M1_3, M2_3) of the first pair of triplets (LG1, LG2), to the third transistor of the respective other triplet of the second pair of triplets (LG3, LG4) and to control terminals of a second pair of bias transistors (MBN1, MBN2) being part of the voltage sources; and - a current through the second pair of bias transistors (MBN1, MBN2) is mirrored to a pair of matched output transistors (MBN3, MBN4) being arranged in the differential current path of the output stage. - a first pair of matched transistors (M1, M2) having a first threshold voltage and comprising control terminals connected to the differential input (inn, inp); - a second pair of matched transistors (M3, M4) having the first threshold voltage and comprising control terminals connected to the differential input (inn, inp), said second pair being part of voltage sources cross-coupling said first pair of matched transistors (M1, M2); - a first pair of triplets (LG1, LG2) of transistors having a second threshold voltage being different from the first threshold voltage, the transistors of each triplet (LG1, LG2) being commonly connected to a respective dedicated transistor of the first pair of matched transistors (M1, M2) such that a respective current path is formed with the dedicated transistor; - a second pair of triplets (LG3, LG4) of transistors having the second threshold voltage, the transistors of each triplet (LG3, LG4) being commonly connected to a respective dedicated transistor of the second pair of matched transistors (M3, M4) such that a respective current path is formed with the dedicated transistor; - a first transistor (M1_1, M2_1, M3_1, M4_1) of each of the triplets has its control terminal connected to the control terminal of the respective dedicated transistor (M1, M2, M3, M4) connected in the current path and is matched to a second and a third transistor of the same triplet by a common matching ratio; - control terminals of the second and third transistors of each triplet are commonly connected to control terminals of the first transistors of the respective other triplet of the pair; - the first transistors (M1_1, M2_1) of the first pair of triplets (LG1, LG2) are connected to the differential current path of the output stage, to the second transistors (M3_2, M4_2) of the second pair of triplets (LG3, LG4), and to the respective second transistor (M2_2, M1_2) of the respective other triplet of the first pair of triplets (LG1, LG2); - the first transistors (M3_1, M4_1) of the second pair of triplets (LG3, LG4) are connected to a first pair of bias transistors (MBP1, MBP2) being part of the voltage sources, to the third transistors (M1_3, M2_3) of the first pair of triplets (LG1, LG2), to the third transistor of the respective other triplet of the second pair of triplets (LG3, LG4) and to control terminals of a second pair of bias transistors (MBN1, MBN2) being part of the voltage sources; and - a current through the second pair of bias transistors (MBN1, MBN2) is mirrored to a pair of matched output transistors (MBN3, MBN4) being arranged in the differential current path of the output stage.