A computing system comprising: a plurality of host processors; a plurality of hybrid memory cube devices configured as a distributed shared memory for the host processors, wherein an hybrid memory cube device includes: a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die mapped to include at least a portion of a memory coherence directory; and a logic base die packaged with at least the first memory die and the second memory die of the hybrid memory cube device of the distributed shared memory, the logic base die including at least one memory controller configured to manage three-dimensional access to memory of the plurality of memory dies by at least one second device, and logic circuitry configured to determine memory coherence state information for a word of memory of the memory die of the plurality of memory dies, to store the memory coherence state information in association with the word of memory of the memory die, to communicate information regarding the access to memory, to communicate packetized information using an input/output, I/O, protocol used to access the memory die, to implement a memory coherence protocol as part of the packetized I/O protocol, and to include the memory coherence state information in a packetized message of the packetized input/output, I/O, protocol. a plurality of host processors; a plurality of hybrid memory cube devices configured as a distributed shared memory for the host processors, wherein an hybrid memory cube device includes: a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die mapped to include at least a portion of a memory coherence directory; and a logic base die packaged with at least the first memory die and the second memory die of the hybrid memory cube device of the distributed shared memory, the logic base die including at least one memory controller configured to manage three-dimensional access to memory of the plurality of memory dies by at least one second device, and logic circuitry configured to determine memory coherence state information for a word of memory of the memory die of the plurality of memory dies, to store the memory coherence state information in association with the word of memory of the memory die, to communicate information regarding the access to memory, to communicate packetized information using an input/output, I/O, protocol used to access the memory die, to implement a memory coherence protocol as part of the packetized I/O protocol, and to include the memory coherence state information in a packetized message of the packetized input/output, I/O, protocol. a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die mapped to include at least a portion of a memory coherence directory; and a logic base die packaged with at least the first memory die and the second memory die of the hybrid memory cube device of the distributed shared memory, the logic base die including at least one memory controller configured to manage three-dimensional access to memory of the plurality of memory dies by at least one second device, and logic circuitry configured to determine memory coherence state information for a word of memory of the memory die of the plurality of memory dies, to store the memory coherence state information in association with the word of memory of the memory die, to communicate information regarding the access to memory, to communicate packetized information using an input/output, I/O, protocol used to access the memory die, to implement a memory coherence protocol as part of the packetized I/O protocol, and to include the memory coherence state information in a packetized message of the packetized input/output, I/O, protocol.