An apparatus for sampling data, the apparatus comprising: a master latch comprising a first data path and a second data path, wherein the first data path comprises a scan path which is input into a memory circuitry of the master latch, and wherein the second data path is a non-scan path which is input via a transmission gate coupled to the memory circuitry; and a slave latch coupled to the master latch; wherein the memory circuitry comprises: a first tristate inverter (M5s) having an input coupled to the transmission gate; and a second tristate inverter having an input coupled to an output of the first tristate inverter (M5s) and the scan path, wherein an output of the second tristate inverter is coupled to the transmission gate; wherein the scan path comprises a tristate inverter (M2s) with an input coupled to a scan input and an output coupled to the input of the second tristate inverter; wherein the apparatus further comprises circuitry to generate scan select based gated clocks derived from an input clock, the scan select based gated clocks comprising a first clock, a second clock, a third clock (nc2s), and a fourth clock (nc3s); wherein the first and second clocks are to control the transmission gate and the second tristate inverter; and wherein the third (nc2s) and fourth (nc3s) clocks are to control the first tri-state inverter (M5s)and the tristate inverter (M2s) of the scan path; wherein the circuitry comprises: an first inverter having an input coupled to the input clock, and an output; an AND logic coupled to the output of the first inverter, wherein the AND logic comprises a NAND gate coupled in series with a second inverter by way of a first node, and wherein the AND logic is to receive a scan select signal and the output of the first inverter as inputs; and an OR logic comprising a NOR gate coupled in series with a third inverter coupled by way of a second node, wherein the OR logic is coupled to the input of the first inverter, and wherein the OR logic is to receive the scan select signal and the input of the first inverter as inputs; wherein the first node provides the first clock; wherein an output of the AND logic provides the second clock; wherein the second node provides the third clock (nc2s); and wherein an output of the OR logic provides the fourth clock (nc3s). a master latch comprising a first data path and a second data path, wherein the first data path comprises a scan path which is input into a memory circuitry of the master latch, and wherein the second data path is a non-scan path which is input via a transmission gate coupled to the memory circuitry; and a slave latch coupled to the master latch; wherein the memory circuitry comprises: a first tristate inverter (M5s) having an input coupled to the transmission gate; and a second tristate inverter having an input coupled to an output of the first tristate inverter (M5s) and the scan path, wherein an output of the second tristate inverter is coupled to the transmission gate; a first tristate inverter (M5s) having an input coupled to the transmission gate; and a second tristate inverter having an input coupled to an output of the first tristate inverter (M5s) and the scan path, wherein an output of the second tristate inverter is coupled to the transmission gate; wherein the scan path comprises a tristate inverter (M2s) with an input coupled to a scan input and an output coupled to the input of the second tristate inverter; wherein the apparatus further comprises circuitry to generate scan select based gated clocks derived from an input clock, the scan select based gated clocks comprising a first clock, a second clock, a third clock (nc2s), and a fourth clock (nc3s); wherein the first and second clocks are to control the transmission gate and the second tristate inverter; and wherein the third (nc2s) and fourth (nc3s) clocks are to control the first tri-state inverter (M5s)and the tristate inverter (M2s) of the scan path; an first inverter having an input coupled to the input clock, and an output; an AND logic coupled to the output of the first inverter, wherein the AND logic comprises a NAND gate coupled in series with a second inverter by way of a first node, and wherein the AND logic is to receive a scan select signal and the output of the first inverter as inputs; and an OR logic comprising a NOR gate coupled in series with a third inverter coupled by way of a second node, wherein the OR logic is coupled to the input of the first inverter, and wherein the OR logic is to receive the scan select signal and the input of the first inverter as inputs; wherein the first node provides the first clock; wherein an output of the AND logic provides the second clock; wherein the second node provides the third clock (nc2s); and wherein an output of the OR logic provides the fourth clock (nc3s).