A processor comprising: a microarchitectural feature being a configurable feature of the processor; dynamic tuning unit, DTU, circuitry; a disabled-cycles counter in the DTU circuitry, the disabled-cycles counter to indicate how many cycles were consumed while the processor was executing a program for a first execution window with the microarchitectural feature disabled; an enabled-cycles counter in the DTU circuitry, the enabled-cycles counter to indicate how many cycles were consumed while the processor was executing a program for a second execution window with the microarchitectural feature enabled, wherein each execution window comprises a predetermined number of retired instructions from an application; and performance evaluation unit, PEU, circuitry in the DTU circuitry, the PEU circuitry to automatically determine whether the processor achieved worse performance in the second execution window, relative to the first execution window, based on the disabled-cycles counter and the enabled-cycles counter; and an evaluation table in the processor, wherein the evaluation table comprises a usefulness state for a selected address, wherein the selected address identifies an instruction within the application, the instruction to be evaluated for performance with different settings of the microarchitectural feature, (a) the usefulness state to be updated by the PEU circuitry to denote worse performance, in response to a determination that the processor achieved worse performance in the second execution window with the microarchitectural feature enabled, relative to the first execution window with the microarchitectural feature disabled, and (b) the usefulness state to be updated by the PEU circuitry to denote a confirmed bad state, in response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, after iteration of at least two execution windows with the microarchitectural feature enabled; and tuning implementation unit, TIU, circuitry in the DTU circuitry to automatically disable the microarchitectural feature for the selected address for subsequent execution windows, in response to the usefulness state for the selected address in the evaluation table denoting the confirmed bad state. a microarchitectural feature being a configurable feature of the processor; dynamic tuning unit, DTU, circuitry; a disabled-cycles counter in the DTU circuitry, the disabled-cycles counter to indicate how many cycles were consumed while the processor was executing a program for a first execution window with the microarchitectural feature disabled; an enabled-cycles counter in the DTU circuitry, the enabled-cycles counter to indicate how many cycles were consumed while the processor was executing a program for a second execution window with the microarchitectural feature enabled, wherein each execution window comprises a predetermined number of retired instructions from an application; and performance evaluation unit, PEU, circuitry in the DTU circuitry, the PEU circuitry to automatically determine whether the processor achieved worse performance in the second execution window, relative to the first execution window, based on the disabled-cycles counter and the enabled-cycles counter; and an evaluation table in the processor, wherein the evaluation table comprises a usefulness state for a selected address, wherein the selected address identifies an instruction within the application, the instruction to be evaluated for performance with different settings of the microarchitectural feature, (a) the usefulness state to be updated by the PEU circuitry to denote worse performance, in response to a determination that the processor achieved worse performance in the second execution window with the microarchitectural feature enabled, relative to the first execution window with the microarchitectural feature disabled, and (b) the usefulness state to be updated by the PEU circuitry to denote a confirmed bad state, in response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, after iteration of at least two execution windows with the microarchitectural feature enabled; and tuning implementation unit, TIU, circuitry in the DTU circuitry to automatically disable the microarchitectural feature for the selected address for subsequent execution windows, in response to the usefulness state for the selected address in the evaluation table denoting the confirmed bad state.