A display panel (100; 500; 600; 700; 800) comprising: a display area; a peripheral area which surrounds the display area and includes a first peripheral area (PA 1), and a second peripheral area opposite to the first peripheral area (PA 1); a plurality of pixels (P; P1, P2,..., P12) in the display area, and including a plurality of pixel rows (PL1, PL2, PL3) and a plurality of pixel columns (PC1, PC2); a plurality of data lines (DLm-1, DLm, DLm+1, DLM+2) which extends in a column direction, wherein between two adjacent data lines (DLm-1, DLm, DLm+1, DLM+2) two adjacent pixel columns (PC1, PC2) are positioned; a plurality of first gate lines (GLi-1, GLi) which extends in a row direction, and is at a first side of each of the pixel rows (PL1, PL2, PL3); a plurality of second gate lines (GLj-1, GLj) which extends in the row direction, and is at a second side of the each of the pixel rows (PL1, PL2, PL3) opposite to the first side; a first gate driving circuit in the first peripheral area (PA 1), and including a first stage (SCi-1, SCi) which provides a gate signal (G1, G3,..,Gi-1, Gi,.., Gk-1) to the first gate line (GLi-1, GLi); and a second gate driving circuit in the second peripheral area, and including a second stage (SCj-1, SCj) which provides the gate signal (G1, G3,..,Gi-1, Gi,.., Gk-1) to the second gate line (GLj-1, GLj), wherein the plurality of pixels (P; P1, P2,..., P12) includes a plurality of monochrome pixels (R; G; B) consisting of a plurality of red pixels positioned in a first pixel column, a plurality of green pixels positioned in a second pixel column adjacent to the first pixel column, and a plurality of blue pixels positioned in a third pixel column adjacent to the second pixel column, characterized in that a gate line of one of the first and second plurality of gate lines (GLi-1, GLi; GLj-1, GLj) is electrically connected to each of the red pixels in a pixel row and a gate line of the other of the first and second plurality of gate lines (GLi-1, GLi; GLj-1, GLj) is electrically connected to each of the green pixels in the same pixel row, and the blue pixels in the same pixel row are alternately connected to the gate line of the first plurality of gate lines and to the gate line of the second plurality of gate lines (GLi-1, GLi; GLj-1, GLj), and in that a first discharging circuit is positioned adjacent to the second stage (SCj-1, SCj), and includes a first discharging transistor arranged to discharge a high voltage applied to the first gate line (GLi-1, GLi) to a low voltage (VOFF); and a second discharging circuit is positioned adjacent to the first stage (SCi-1, SCi), and includes a second discharging transistor arranged to discharge a high voltage applied to the second gate line (GLj-1, GLj) to a low voltage (VOFF). a display area; a peripheral area which surrounds the display area and includes a first peripheral area (PA 1), and a second peripheral area opposite to the first peripheral area (PA 1); a plurality of pixels (P; P1, P2,..., P12) in the display area, and including a plurality of pixel rows (PL1, PL2, PL3) and a plurality of pixel columns (PC1, PC2); a plurality of data lines (DLm-1, DLm, DLm+1, DLM+2) which extends in a column direction, wherein between two adjacent data lines (DLm-1, DLm, DLm+1, DLM+2) two adjacent pixel columns (PC1, PC2) are positioned; a plurality of first gate lines (GLi-1, GLi) which extends in a row direction, and is at a first side of each of the pixel rows (PL1, PL2, PL3); a plurality of second gate lines (GLj-1, GLj) which extends in the row direction, and is at a second side of the each of the pixel rows (PL1, PL2, PL3) opposite to the first side; a first gate driving circuit in the first peripheral area (PA 1), and including a first stage (SCi-1, SCi) which provides a gate signal (G1, G3,..,Gi-1, Gi,.., Gk-1) to the first gate line (GLi-1, GLi); and a second gate driving circuit in the second peripheral area, and including a second stage (SCj-1, SCj) which provides the gate signal (G1, G3,..,Gi-1, Gi,.., Gk-1) to the second gate line (GLj-1, GLj), wherein the plurality of pixels (P; P1, P2,..., P12) includes a plurality of monochrome pixels (R; G; B) consisting of a plurality of red pixels positioned in a first pixel column, a plurality of green pixels positioned in a second pixel column adjacent to the first pixel column, and a plurality of blue pixels positioned in a third pixel column adjacent to the second pixel column, characterized in that a gate line of one of the first and second plurality of gate lines (GLi-1, GLi; GLj-1, GLj) is electrically connected to each of the red pixels in a pixel row and a gate line of the other of the first and second plurality of gate lines (GLi-1, GLi; GLj-1, GLj) is electrically connected to each of the green pixels in the same pixel row, and the blue pixels in the same pixel row are alternately connected to the gate line of the first plurality of gate lines and to the gate line of the second plurality of gate lines (GLi-1, GLi; GLj-1, GLj), and in that a first discharging circuit is positioned adjacent to the second stage (SCj-1, SCj), and includes a first discharging transistor arranged to discharge a high voltage applied to the first gate line (GLi-1, GLi) to a low voltage (VOFF); and a second discharging circuit is positioned adjacent to the first stage (SCi-1, SCi), and includes a second discharging transistor arranged to discharge a high voltage applied to the second gate line (GLj-1, GLj) to a low voltage (VOFF).