A charge pump circuit for supplying power to a class-G amplifier, wherein the class-G amplifier comprises an input configured to receive a time-varying input signal (Input Signal), the charge pump comprising: a switch module configured to generate a first output voltage (HPVDD) at a first output terminal of the charge pump circuit and a second output voltage (HPVSS) at a second output terminal of the charge pump circuit according to an input voltage, wherein said first and second output terminals are connectable to the class-G amplifier for supplying power; a digital control circuit, coupled to the first output terminal of the charge pump circuit and the second output terminal of the charge pump circuit, configured to receive an up digital signal (D UP) and a down digital signal (D DN), which are based on the input signal (Input Signal), and configured to adjust the first output voltage (HPVDD) to a voltage level of the input voltage and adjust the second output voltage (HPVSS) to a ground voltage level according to the up digital signal (D UP) and the down digital signal (D DN) during a ramp-up mode in which the switch module stopped switching, comprising: a digital-to-analog converter, configured to generate a corresponding up reference voltage (VR UP) and a corresponding down reference voltage (VR DN) according to the up digital signal (D UP) and the down digital signal (D DN); and a voltage follower (Vf), comprising a plurality of operational amplifiers and a plurality of transistor switches (M UP, M DN), configured to lock the first output voltage (HPVDD) and the second output voltage (HPVSS) according to the up reference voltage (VR UP) and the down reference voltage (VR DN); wherein the plurality of transistor switches (M UP, M DN) are configured to directly receive the first output voltage (HPVDD) and the second output voltage (HPVSS). a switch module configured to generate a first output voltage (HPVDD) at a first output terminal of the charge pump circuit and a second output voltage (HPVSS) at a second output terminal of the charge pump circuit according to an input voltage, wherein said first and second output terminals are connectable to the class-G amplifier for supplying power; a digital control circuit, coupled to the first output terminal of the charge pump circuit and the second output terminal of the charge pump circuit, configured to receive an up digital signal (D UP) and a down digital signal (D DN), which are based on the input signal (Input Signal), and configured to adjust the first output voltage (HPVDD) to a voltage level of the input voltage and adjust the second output voltage (HPVSS) to a ground voltage level according to the up digital signal (D UP) and the down digital signal (D DN) during a ramp-up mode in which the switch module stopped switching, comprising: a digital-to-analog converter, configured to generate a corresponding up reference voltage (VR UP) and a corresponding down reference voltage (VR DN) according to the up digital signal (D UP) and the down digital signal (D DN); and a voltage follower (Vf), comprising a plurality of operational amplifiers and a plurality of transistor switches (M UP, M DN), configured to lock the first output voltage (HPVDD) and the second output voltage (HPVSS) according to the up reference voltage (VR UP) and the down reference voltage (VR DN); wherein the plurality of transistor switches (M UP, M DN) are configured to directly receive the first output voltage (HPVDD) and the second output voltage (HPVSS). a digital-to-analog converter, configured to generate a corresponding up reference voltage (VR UP) and a corresponding down reference voltage (VR DN) according to the up digital signal (D UP) and the down digital signal (D DN); and a voltage follower (Vf), comprising a plurality of operational amplifiers and a plurality of transistor switches (M UP, M DN), configured to lock the first output voltage (HPVDD) and the second output voltage (HPVSS) according to the up reference voltage (VR UP) and the down reference voltage (VR DN); wherein the plurality of transistor switches (M UP, M DN) are configured to directly receive the first output voltage (HPVDD) and the second output voltage (HPVSS).