An apparatus comprising a first processor and a second processor, each having a first logic output pin (11, 21), a second logic output pin (12, 22), a first logic input pin (13, 23) and a second logic input pin (14, 24), wherein: for each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102); for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102); each of the first and the second processor (101, 102) is operable in a transmit mode to transmit data to the respective other processor (101, 102) by controlling the second logic output pin (12, 22) to provide a logic data signal indicating a sequence of data bits (D7-D0) and controlling the first logic output pin (11, 21) to provide a logic clock signal with state transitions indicating when the logic data signal indicates the values of the individual data bits (D7-D0) in the sequence; and each of the first and the second processor (101, 102) is operable in a receive mode to receive data from the respective other processor (101, 102) by determining a sequence of data bits (D7-D0) from the logic data signal received on the first logic input pin (13, 23) in response to state transitions of the logic clock signal received on the second logic input pin (14, 24); characterized in that each of the first and the second processor (101, 102) further is configured to: in dependence on being in the receive mode and able to receive data, control the second logic output pin (12, 22) to provide a logic clear-to-send signal indicating the ability to receive data and control the first logic output pin (11, 21) to provide a logic data-acknowledge signal with state transitions indicating successful reception of individual data bits (D7-D0); and in dependence on being in the transmit mode, delay transmission of the first data bit in the sequence (D7-D0) until determining that the logic clear-to-send signal indicates the ability to receive data by the respective other processor (101, 102) and delay transmission of each subsequent data bit in the sequence (D7-D0) until determining a state transition of the logic data-acknowledge signal that indicates successful reception of the respective previous data bit by the respective other processor (101, 102). for each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102); for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102); each of the first and the second processor (101, 102) is operable in a transmit mode to transmit data to the respective other processor (101, 102) by controlling the second logic output pin (12, 22) to provide a logic data signal indicating a sequence of data bits (D7-D0) and controlling the first logic output pin (11, 21) to provide a logic clock signal with state transitions indicating when the logic data signal indicates the values of the individual data bits (D7-D0) in the sequence; and each of the first and the second processor (101, 102) is operable in a receive mode to receive data from the respective other processor (101, 102) by determining a sequence of data bits (D7-D0) from the logic data signal received on the first logic input pin (13, 23) in response to state transitions of the logic clock signal received on the second logic input pin (14, 24); characterized in that each of the first and the second processor (101, 102) further is configured to: in dependence on being in the receive mode and able to receive data, control the second logic output pin (12, 22) to provide a logic clear-to-send signal indicating the ability to receive data and control the first logic output pin (11, 21) to provide a logic data-acknowledge signal with state transitions indicating successful reception of individual data bits (D7-D0); and in dependence on being in the transmit mode, delay transmission of the first data bit in the sequence (D7-D0) until determining that the logic clear-to-send signal indicates the ability to receive data by the respective other processor (101, 102) and delay transmission of each subsequent data bit in the sequence (D7-D0) until determining a state transition of the logic data-acknowledge signal that indicates successful reception of the respective previous data bit by the respective other processor (101, 102). in dependence on being in the receive mode and able to receive data, control the second logic output pin (12, 22) to provide a logic clear-to-send signal indicating the ability to receive data and control the first logic output pin (11, 21) to provide a logic data-acknowledge signal with state transitions indicating successful reception of individual data bits (D7-D0); and in dependence on being in the transmit mode, delay transmission of the first data bit in the sequence (D7-D0) until determining that the logic clear-to-send signal indicates the ability to receive data by the respective other processor (101, 102) and delay transmission of each subsequent data bit in the sequence (D7-D0) until determining a state transition of the logic data-acknowledge signal that indicates successful reception of the respective previous data bit by the respective other processor (101, 102).