A broadband amplifier comprising: a first transistor; a second transistor; and an impedance matching circuit, wherein the impedance matching circuit comprises: a first branch including: first parallel capacitors (9d, 9c); and a transmission line connected to an input terminal of the first transistor; a second branch including: second parallel capacitors (9d, 9c); and a transmission line connected to an input terminal of the second transistor; and a plurality of via holes (9f, 9e), wherein one of the plurality of via holes (9f, 9e) is configured to connect an end of one of the first parallel capacitors (9d, 9c) and an end of one of the second parallel capacitors (9f, 9e) to a lower potential electrode in common, and another one of the plurality of via holes (9f, 9e) is configured to connect an end of another one of the first parallel capacitors (9d, 9c) and a source terminal or emitter of the first transistor to a lower potential electrode in common and a further one of the plurality of via holes (9f, 9e) is configured to connect another one of the second parallel capacitors (9d, 9c) and a source terminal or emitter of the second transistor to a lower potential electrode in common. a first transistor; a second transistor; and an impedance matching circuit, wherein the impedance matching circuit comprises: a first branch including: first parallel capacitors (9d, 9c); and a transmission line connected to an input terminal of the first transistor; a second branch including: second parallel capacitors (9d, 9c); and a transmission line connected to an input terminal of the second transistor; and a plurality of via holes (9f, 9e), wherein one of the plurality of via holes (9f, 9e) is configured to connect an end of one of the first parallel capacitors (9d, 9c) and an end of one of the second parallel capacitors (9f, 9e) to a lower potential electrode in common, and another one of the plurality of via holes (9f, 9e) is configured to connect an end of another one of the first parallel capacitors (9d, 9c) and a source terminal or emitter of the first transistor to a lower potential electrode in common and a further one of the plurality of via holes (9f, 9e) is configured to connect another one of the second parallel capacitors (9d, 9c) and a source terminal or emitter of the second transistor to a lower potential electrode in common. a first branch including: first parallel capacitors (9d, 9c); and a transmission line connected to an input terminal of the first transistor; a second branch including: second parallel capacitors (9d, 9c); and a transmission line connected to an input terminal of the second transistor; and a plurality of via holes (9f, 9e), wherein one of the plurality of via holes (9f, 9e) is configured to connect an end of one of the first parallel capacitors (9d, 9c) and an end of one of the second parallel capacitors (9f, 9e) to a lower potential electrode in common, and another one of the plurality of via holes (9f, 9e) is configured to connect an end of another one of the first parallel capacitors (9d, 9c) and a source terminal or emitter of the first transistor to a lower potential electrode in common and a further one of the plurality of via holes (9f, 9e) is configured to connect another one of the second parallel capacitors (9d, 9c) and a source terminal or emitter of the second transistor to a lower potential electrode in common.