A cache memory, segmented into M ways, wherein M is an integer; where each way comprising: an instruction memory portion, comprising a plurality of instruction memory locations configured to store instruction data encoding a plurality of central processing unit CPU instructions; a tag memory portion, comprising a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in; wherein the tag memory portion comprises a plurality of tag memory circuits, wherein each of the tag memory circuits of the tag memory portion is configured to store tag data of a separate one of the M ways; wherein tag memory locations of each of the tag memory circuits of the tag memory portion are configured to be read during a first time period, and wherein the read tag memory locations are each identified with an index portion of a CPU address; and a comparison circuit configured to compare the tag data of each of the read tag memory locations with a tag portion of the CPU address; wherein the instruction memory portion comprises a single memory circuit comprising an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array, wherein each of the tag memory circuits comprises: a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array; and wherein the comparison circuit comprises M tag comparators and M tri-state driver arrays which are respectively connected to a tag comparator; wherein a tag comparator is respectively associated with one of the M ways and each of tag comparators is configured to compare one of the M tags with the tag portion of the CPU address at bus CPUTAG and at most one of the M tags matches the tag portion of the CPU address; wherein data inputs of each of tri-state driver arrays are connected to one of the way identification busses, each of tri-state driver arrays receives an indication of whether a particular one of the M tags at tag busses matches the tag portion of the CPU address at bus CPUTAG, and outputs data at a way bus (WAY) indicating the particular way identified at its data input. an instruction memory portion, comprising a plurality of instruction memory locations configured to store instruction data encoding a plurality of central processing unit CPU instructions; a tag memory portion, comprising a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in; wherein the tag memory portion comprises a plurality of tag memory circuits, wherein each of the tag memory circuits of the tag memory portion is configured to store tag data of a separate one of the M ways; wherein tag memory locations of each of the tag memory circuits of the tag memory portion are configured to be read during a first time period, and wherein the read tag memory locations are each identified with an index portion of a CPU address; and a comparison circuit configured to compare the tag data of each of the read tag memory locations with a tag portion of the CPU address; wherein the instruction memory portion comprises a single memory circuit comprising an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array, wherein each of the tag memory circuits comprises: a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array; and wherein the comparison circuit comprises M tag comparators and M tri-state driver arrays which are respectively connected to a tag comparator; wherein a tag comparator is respectively associated with one of the M ways and each of tag comparators is configured to compare one of the M tags with the tag portion of the CPU address at bus CPUTAG and at most one of the M tags matches the tag portion of the CPU address; wherein data inputs of each of tri-state driver arrays are connected to one of the way identification busses, each of tri-state driver arrays receives an indication of whether a particular one of the M tags at tag busses matches the tag portion of the CPU address at bus CPUTAG, and outputs data at a way bus (WAY) indicating the particular way identified at its data input. a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array; and wherein the comparison circuit comprises M tag comparators and M tri-state driver arrays which are respectively connected to a tag comparator; wherein a tag comparator is respectively associated with one of the M ways and each of tag comparators is configured to compare one of the M tags with the tag portion of the CPU address at bus CPUTAG and at most one of the M tags matches the tag portion of the CPU address; wherein data inputs of each of tri-state driver arrays are connected to one of the way identification busses, each of tri-state driver arrays receives an indication of whether a particular one of the M tags at tag busses matches the tag portion of the CPU address at bus CPUTAG, and outputs data at a way bus (WAY) indicating the particular way identified at its data input.