A display panel comprising a plurality of pixels arranged in rows, each row of pixels having a corresponding scan line, each pixel comprising: an organic light emitting diode (OLED); a driving transistor (Md) comprising a drain electrode directly coupled to the OLED; a first transistor comprising a gate electrode directly coupled to a first scan line (Sn), a source electrode for receiving a data signal, and a drain electrode directly coupled to the source electrode of the driving transistor; a second transistor comprising a gate electrode directly coupled to a second scan line (Sn-1) corresponding to the scan line preceding the first scan line, a source electrode directly coupled to a first power source supply (ELVDD), and a drain electrode directly coupled to the source electrode of the driving transistor; a capacitor comprising a first electrode directly coupled to a gate electrode of the driving transistor and a second electrode directly coupled to the first power source supply (ELVDD); an initialization transistor comprising a gate electrode directly coupled to the second scan line (Sn-1), a source electrode for receiving an initialization voltage (VINT), and a drain electrode directly coupled to the gate electrode of the driving transistor, and a threshold voltage compensation transistor comprising a gate electrode directly coupled to the first scan line (Sn), a source electrode directly coupled to the drain electrode of the driving transistor (Md), and a drain electrode directly coupled to the gate electrode of the driving transistor (Md); wherein rows of pixels sequentially receive scan signals in each frame, and wherein within each frame a second scan signal is transmitted to the second scan line preceding a first scan signal being transmitted to the first scan line. an organic light emitting diode (OLED); a driving transistor (Md) comprising a drain electrode directly coupled to the OLED; a first transistor comprising a gate electrode directly coupled to a first scan line (Sn), a source electrode for receiving a data signal, and a drain electrode directly coupled to the source electrode of the driving transistor; a second transistor comprising a gate electrode directly coupled to a second scan line (Sn-1) corresponding to the scan line preceding the first scan line, a source electrode directly coupled to a first power source supply (ELVDD), and a drain electrode directly coupled to the source electrode of the driving transistor; a capacitor comprising a first electrode directly coupled to a gate electrode of the driving transistor and a second electrode directly coupled to the first power source supply (ELVDD); an initialization transistor comprising a gate electrode directly coupled to the second scan line (Sn-1), a source electrode for receiving an initialization voltage (VINT), and a drain electrode directly coupled to the gate electrode of the driving transistor, and a threshold voltage compensation transistor comprising a gate electrode directly coupled to the first scan line (Sn), a source electrode directly coupled to the drain electrode of the driving transistor (Md), and a drain electrode directly coupled to the gate electrode of the driving transistor (Md);