A differential low-noise amplifier circuit comprising: - a first transistor NMOS (M 1) and a second transistor NMOS (M 2), each transistor (M 1, M 2) having a source terminal, a gate terminal and a drain terminal; and - a third transistor NMOS (M 3) and a fourth transistor NMOS (M 4), each transistor (M 3, M 4) having a source terminal, a gate terminal and a drain terminal; wherein: - the source of the second transistor (M 2) is coupled to the drain terminal of the first transistor (M 1), and the source of the third transistor (M 3) is coupled to the drain terminal of the fourth transistor (M 4); and - the gate terminal of the first transistor (M 1) has a first capacitive coupling (C 1) to the source terminal of the fourth transistor (M 4) and the gate terminal of the fourth transistor (M 4) has a second capacitive coupling (C 2) to the source terminal of the first transistor (M 1); the low-noise amplifier circuit further comprises a fifth transistor PMOS (M 5) and a sixth transistor PMOS (M 6), each transistor (M 5, M 6) having a source terminal, a gate terminal and a drain terminal wherein: - the drain of the fifth transistor (M 5) is coupled to the drain terminal of the second transistor (M 2), and the drain of the sixth transistor (M 6) is coupled to the drain terminal of the third transistor (M 3); - the source terminal of the fifth transistor (M 5) has a third capacitive coupling (C 3) to the source terminal of the first transistor (M 1); - the gate terminal of the fifth transistor (M 5) has a fourth capacitive coupling (C 4) to at least the source terminal of the sixth transistor (M 6) or the source terminal of the fourth transistor (M 4); - the gate terminal of the sixth transistor (M 6) has a fifth capacitive coupling (C 5) to at least the source terminal of the fifth transistor (M 5) or the source terminal of the first transistor (M 1); and - the source terminal of the sixth transistor (M 6) has a sixth capacitive coupling (C 6) to the source terminal of the fourth transistor (M 4); - and the third (C 3) and sixth (C 6) capacitive couplings, each comprising at least one wired capacitor, provide an equivalent input resistance for each side circuit (10, 54) of the differential low noise amplifier circuit. - a first transistor NMOS (M 1) and a second transistor NMOS (M 2), each transistor (M 1, M 2) having a source terminal, a gate terminal and a drain terminal; and - a third transistor NMOS (M 3) and a fourth transistor NMOS (M 4), each transistor (M 3, M 4) having a source terminal, a gate terminal and a drain terminal; - the source of the second transistor (M 2) is coupled to the drain terminal of the first transistor (M 1), and the source of the third transistor (M 3) is coupled to the drain terminal of the fourth transistor (M 4); and - the gate terminal of the first transistor (M 1) has a first capacitive coupling (C 1) to the source terminal of the fourth transistor (M 4) and the gate terminal of the fourth transistor (M 4) has a second capacitive coupling (C 2) to the source terminal of the first transistor (M 1); - the drain of the fifth transistor (M 5) is coupled to the drain terminal of the second transistor (M 2), and the drain of the sixth transistor (M 6) is coupled to the drain terminal of the third transistor (M 3); - the source terminal of the fifth transistor (M 5) has a third capacitive coupling (C 3) to the source terminal of the first transistor (M 1); - the gate terminal of the fifth transistor (M 5) has a fourth capacitive coupling (C 4) to at least the source terminal of the sixth transistor (M 6) or the source terminal of the fourth transistor (M 4); - the gate terminal of the sixth transistor (M 6) has a fifth capacitive coupling (C 5) to at least the source terminal of the fifth transistor (M 5) or the source terminal of the first transistor (M 1); and - the source terminal of the sixth transistor (M 6) has a sixth capacitive coupling (C 6) to the source terminal of the fourth transistor (M 4); - and the third (C 3) and sixth (C 6) capacitive couplings, each comprising at least one wired capacitor, provide an equivalent input resistance for each side circuit (10, 54) of the differential low noise amplifier circuit.