A memory module comprising: a plurality of memory integrated circuit packages to store data; and a command buffer IC to buffer a plurality of memory commands destined for the memory IC packages, the command buffer IC comprising: a first interface circuit and/or a second interface circuit, each to receive the plurality of memory commands; at least one programmable memory (354, 356) to store a plurality of pre-programmed reference command patterns, each including a plurality of commands, and to store a plurality of pre-programmed command sequences, each including one or more commands and each associated with one of the plurality of pre-programmed reference command patterns; a pattern matching circuit to compare the plurality of memory commands to each of the pre-programmed reference command patterns so as to determine whether the plurality of memory commands match a pre-programmed reference command pattern from the plurality of pre-programmed reference command patterns, and a sequence selector circuit to, responsive to the plurality of memory commands matching the pre-programmed reference command pattern, select a pre-programmed command sequence from the plurality of pre-programmed command sequences, the selected pre-programmed command sequence associated with the matching pre-programmed reference command pattern; and one or more third interface circuits (310, 380, 390) to output the selected pre-programmed command sequence to one or more devices (10, 202, 250) separate from the command buffer IC, wherein the command buffer IC is configured to, responsive to the plurality of memory commands not matching a pre-programmed reference command pattern, provide the plurality of memory commands to the memory IC packages. a plurality of memory integrated circuit packages to store data; and a command buffer IC to buffer a plurality of memory commands destined for the memory IC packages, the command buffer IC comprising: a first interface circuit and/or a second interface circuit, each to receive the plurality of memory commands; at least one programmable memory (354, 356) to store a plurality of pre-programmed reference command patterns, each including a plurality of commands, and to store a plurality of pre-programmed command sequences, each including one or more commands and each associated with one of the plurality of pre-programmed reference command patterns; a pattern matching circuit to compare the plurality of memory commands to each of the pre-programmed reference command patterns so as to determine whether the plurality of memory commands match a pre-programmed reference command pattern from the plurality of pre-programmed reference command patterns, and a sequence selector circuit to, responsive to the plurality of memory commands matching the pre-programmed reference command pattern, select a pre-programmed command sequence from the plurality of pre-programmed command sequences, the selected pre-programmed command sequence associated with the matching pre-programmed reference command pattern; and one or more third interface circuits (310, 380, 390) to output the selected pre-programmed command sequence to one or more devices (10, 202, 250) separate from the command buffer IC, wherein the command buffer IC is configured to, responsive to the plurality of memory commands not matching a pre-programmed reference command pattern, provide the plurality of memory commands to the memory IC packages. a first interface circuit and/or a second interface circuit, each to receive the plurality of memory commands; at least one programmable memory (354, 356) to store a plurality of pre-programmed reference command patterns, each including a plurality of commands, and to store a plurality of pre-programmed command sequences, each including one or more commands and each associated with one of the plurality of pre-programmed reference command patterns; a pattern matching circuit to compare the plurality of memory commands to each of the pre-programmed reference command patterns so as to determine whether the plurality of memory commands match a pre-programmed reference command pattern from the plurality of pre-programmed reference command patterns, and a sequence selector circuit to, responsive to the plurality of memory commands matching the pre-programmed reference command pattern, select a pre-programmed command sequence from the plurality of pre-programmed command sequences, the selected pre-programmed command sequence associated with the matching pre-programmed reference command pattern; and one or more third interface circuits (310, 380, 390) to output the selected pre-programmed command sequence to one or more devices (10, 202, 250) separate from the command buffer IC, wherein the command buffer IC is configured to, responsive to the plurality of memory commands not matching a pre-programmed reference command pattern, provide the plurality of memory commands to the memory IC packages.