A method of forming a capacitor, comprising: forming a first section of the capacitor over a memory array region of a semiconductor substrate; the first section comprising a first capacitor storage node (78, 80), a first dielectric material over the first capacitor storage node (78, 80), and a first capacitor outer electrode material over the first dielectric material; electrically connecting the first capacitor outer electrode material to a first conductive interconnect that is over a region of the semiconductor substrate peripheral to the memory array region; forming a second section of the capacitor over the first section of the capacitor; the second section comprising a second capacitor storage node (128, 130), a second dielectric material over the second capacitor storage node (128, 130), and a second capacitor outer electrode material over the second dielectric material; the second capacitor storage node (128, 130) being in electrical contact with the first capacitor storage node (78, 80); electrically connecting the second capacitor outer electrode material to a second conductive interconnect that is over the region of the semiconductor substrate peripheral to the memory array region; electrically connecting the first and second conductive interconnects (68; 118) to one another to electrically couple the first and second capacitor outer electrode materials (84, 134) to one another; and wherein the first and second capacitor storage nodes (78, 80; 128, 130) comprise pillars having an equivalent first lateral width, characterized in that the second capacitor storage node (128, 130) is formed to be in electrical contact with the first capacitor storage node (78, 80) by forming an electrically conductive neck between the pillars of the first and second capacitor storage nodes (78, 80; 128, 130), and wherein the electrically conductive neck has a second lateral width which is less than the first lateral width. forming a first section of the capacitor over a memory array region of a semiconductor substrate; the first section comprising a first capacitor storage node (78, 80), a first dielectric material over the first capacitor storage node (78, 80), and a first capacitor outer electrode material over the first dielectric material; electrically connecting the first capacitor outer electrode material to a first conductive interconnect that is over a region of the semiconductor substrate peripheral to the memory array region; forming a second section of the capacitor over the first section of the capacitor; the second section comprising a second capacitor storage node (128, 130), a second dielectric material over the second capacitor storage node (128, 130), and a second capacitor outer electrode material over the second dielectric material; the second capacitor storage node (128, 130) being in electrical contact with the first capacitor storage node (78, 80); electrically connecting the second capacitor outer electrode material to a second conductive interconnect that is over the region of the semiconductor substrate peripheral to the memory array region; electrically connecting the first and second conductive interconnects (68; 118) to one another to electrically couple the first and second capacitor outer electrode materials (84, 134) to one another; and wherein the first and second capacitor storage nodes (78, 80; 128, 130) comprise pillars having an equivalent first lateral width, characterized in that the second capacitor storage node (128, 130) is formed to be in electrical contact with the first capacitor storage node (78, 80) by forming an electrically conductive neck between the pillars of the first and second capacitor storage nodes (78, 80; 128, 130), and wherein the electrically conductive neck has a second lateral width which is less than the first lateral width.