A chip for determining oversampled data to be included in unit intervals for use in determining bit values of a received signal comprising: sampling circuitry to produce oversampled data from a received signal; and logic to determine unit intervals from the oversampled data and to determine bit values of the received signal from the unit intervals of oversampled data, wherein each unit interval includes a group of the oversampled data and the logic determines at least a first unit interval having a first number of oversampled data and a second unit interval having a second number of oversampled data that is different than the first number of oversampled data, the logic including: a pipeline of a plurality of pipeline stages, each of the plurality of pipeline stages processing a portion of a line of oversampled data during a clock cycle, a line of data including a certain number of oversampled data values, each pipeline stage determining whether or not to generate a single output bit or no output bit during each clock cycle based on a respective unit interval in a respective portion of a respective line evaluated during the clock cycle, wherein the pipeline advances a line of data being processed by a first stage of the plurality of pipeline stages in a first clock cycle to a succeeding second stage of the plurality of pipeline stages for processing in a second clock cycle. sampling circuitry to produce oversampled data from a received signal; and logic to determine unit intervals from the oversampled data and to determine bit values of the received signal from the unit intervals of oversampled data, wherein each unit interval includes a group of the oversampled data and the logic determines at least a first unit interval having a first number of oversampled data and a second unit interval having a second number of oversampled data that is different than the first number of oversampled data, the logic including: a pipeline of a plurality of pipeline stages, each of the plurality of pipeline stages processing a portion of a line of oversampled data during a clock cycle, a line of data including a certain number of oversampled data values, each pipeline stage determining whether or not to generate a single output bit or no output bit during each clock cycle based on a respective unit interval in a respective portion of a respective line evaluated during the clock cycle, wherein the pipeline advances a line of data being processed by a first stage of the plurality of pipeline stages in a first clock cycle to a succeeding second stage of the plurality of pipeline stages for processing in a second clock cycle. a pipeline of a plurality of pipeline stages, each of the plurality of pipeline stages processing a portion of a line of oversampled data during a clock cycle, a line of data including a certain number of oversampled data values, each pipeline stage determining whether or not to generate a single output bit or no output bit during each clock cycle based on a respective unit interval in a respective portion of a respective line evaluated during the clock cycle, wherein the pipeline advances a line of data being processed by a first stage of the plurality of pipeline stages in a first clock cycle to a succeeding second stage of the plurality of pipeline stages for processing in a second clock cycle.