A device comprising a preamplifier circuit that receives a differential input voltage V1, V2 and generates a differential output voltage Vo-, Vo+, wherein the preamplifier circuit comprises: an input stage including a first transconductor and a load, wherein the first transconductor receives the differential input voltage V1, V2 and, and the load is connected to the outputs of the first transconductor at first and second nodes N1 and N2 such that there is a first amplified differential voltage V1amp-, Vlamp+ at the outputs of the first transconductor; a second transconductor that is connected to the load by way of the first and second nodes N1, N2 and wherein the output of the second transconductor is connected in parallel with the output of the first transconductor; a first feedback capacitor that has a first terminal connected to an inverting output terminal of the second transconductor and a second terminal connected to an inverting input terminal of the second transconductor; a second feedback capacitor that has a first terminal connected to a non-inverting output terminal of the second transconductor and a second terminal connected to a non- inverting input terminal of the second transconductor; a third switch connected between the non-inverting output terminal and the inverting input terminal of the second transconductor; and a fourth switch connected between the inverting output terminal and the non-inverting input terminal of the second transconductor, a first switch connected between an inverting output terminal and a non-inverting input terminal of the first transconductor; and a second switch connected between a non-inverting output terminal and an inverting input terminal of the first transconductor, and wherein the device further comprises a sample-and-hold circuit connected to the preamplifier circuit, wherein the input stage of the preamplifier circuit receives the differential input voltage V1, V2 from the sample-and-hold circuit, wherein the sample-and-hold circuit is configured to operate in a sampling phase and an amplification phase wherein, during the amplification phase the voltage V1 output by the sample-and-hold circuit is based on the sum of a first component V+ of a differential input voltage and a common-mode voltage Vcm and the voltage V2 is based on the sum of a second component V- of the differential input voltage and a common-mode voltage Vcm; wherein the first and second switches (214a, 214b) are turned on during a sampling phase of the preamplifier circuit; wherein the third and fourth switches (218a, 218b) are turned on during the sampling phase of the preamplifier circuit, wherein the sample-and-hold circuit and the first and second feedback capacitors (220a, 220b) together store combined offset voltages of the first and second transconductors (210, 216) during the sampling phase of the preamplifier circuit. an input stage including a first transconductor and a load, wherein the first transconductor receives the differential input voltage V1, V2 and, and the load is connected to the outputs of the first transconductor at first and second nodes N1 and N2 such that there is a first amplified differential voltage V1amp-, Vlamp+ at the outputs of the first transconductor; a second transconductor that is connected to the load by way of the first and second nodes N1, N2 and wherein the output of the second transconductor is connected in parallel with the output of the first transconductor; a first feedback capacitor that has a first terminal connected to an inverting output terminal of the second transconductor and a second terminal connected to an inverting input terminal of the second transconductor; a second feedback capacitor that has a first terminal connected to a non-inverting output terminal of the second transconductor and a second terminal connected to a non- inverting input terminal of the second transconductor; a third switch connected between the non-inverting output terminal and the inverting input terminal of the second transconductor; and a fourth switch connected between the inverting output terminal and the non-inverting input terminal of the second transconductor, a first switch connected between an inverting output terminal and a non-inverting input terminal of the first transconductor; and a second switch connected between a non-inverting output terminal and an inverting input terminal of the first transconductor, and wherein the device further comprises a sample-and-hold circuit connected to the preamplifier circuit, wherein the input stage of the preamplifier circuit receives the differential input voltage V1, V2 from the sample-and-hold circuit, wherein the sample-and-hold circuit is configured to operate in a sampling phase and an amplification phase wherein, during the amplification phase the voltage V1 output by the sample-and-hold circuit is based on the sum of a first component V+ of a differential input voltage and a common-mode voltage Vcm and the voltage V2 is based on the sum of a second component V- of the differential input voltage and a common-mode voltage Vcm; wherein the first and second switches (214a, 214b) are turned on during a sampling phase of the preamplifier circuit; wherein the third and fourth switches (218a, 218b) are turned on during the sampling phase of the preamplifier circuit, wherein the sample-and-hold circuit and the first and second feedback capacitors (220a, 220b) together store combined offset voltages of the first and second transconductors (210, 216) during the sampling phase of the preamplifier circuit.