A method of producing a semiconductor device, comprising: - forming an integrated circuit component at or near a main surface of a semiconductor substrate, - forming an insulating region at the main surface in an area that is provided for an interconnection via, - applying a stop layer on the insulating region, - applying a dielectric layer on the main surface, - forming an electrical interconnect traversing the dielectric layer and a further electrical interconnect traversing the dielectric layer in the area that is provided for the interconnection via, the further electrical interconnect being arranged on the stop layer at a distance from the semiconductor material of the substrate before the interconnection via is etched, - arranging a structured metal plane on the dielectric layer, the interconnect and the further electrical interconnect contacting the metal plane, the interconnect traversing the dielectric layer between the metal plane and the integrated circuit component, - etching the substrate from an opposite surface to open the interconnection via and at least partially removing the insulating region, and - providing the interconnection via with a metallization leading through the substrate between the main surface and the opposite surface, the metallization being connected to the further electrical interconnect, characterized in that - the further electrical interconnect traversing the dielectric layer is arranged at a distance of less than 0.1 μm from the semiconductor material of the substrate before the interconnection via is etched, and - the stop layer is removed to uncover a contact area of the further electrical interconnect before the metallization is connected to the further electrical interconnect. - forming an integrated circuit component at or near a main surface of a semiconductor substrate, - forming an insulating region at the main surface in an area that is provided for an interconnection via, - applying a stop layer on the insulating region, - applying a dielectric layer on the main surface, - forming an electrical interconnect traversing the dielectric layer and a further electrical interconnect traversing the dielectric layer in the area that is provided for the interconnection via, the further electrical interconnect being arranged on the stop layer at a distance from the semiconductor material of the substrate before the interconnection via is etched, - arranging a structured metal plane on the dielectric layer, the interconnect and the further electrical interconnect contacting the metal plane, the interconnect traversing the dielectric layer between the metal plane and the integrated circuit component, - etching the substrate from an opposite surface to open the interconnection via and at least partially removing the insulating region, and - providing the interconnection via with a metallization leading through the substrate between the main surface and the opposite surface, the metallization being connected to the further electrical interconnect, - the further electrical interconnect traversing the dielectric layer is arranged at a distance of less than 0.1 μm from the semiconductor material of the substrate before the interconnection via is etched, and - the stop layer is removed to uncover a contact area of the further electrical interconnect before the metallization is connected to the further electrical interconnect.