A clock data recovery device comprising: a phase change determination circuit configured to: detect a phase difference between a data signal and a capture clock signal; and generate, based upon the detected phase difference, a delta signal and a delta selection signal, the delta signal representing an incremental change to a phase accumulator of the capture clock signal, the delta selection signal representing the actual delta value for a current iteration; and a speculative calculation circuit that includes: a first calculation circuit configured to generate a first set of phase interpolation codes from a first prior value of the delta signal; a second calculation circuit configured to generate a second set of PI codes from a second prior value of the delta signal; a third calculation circuit configured to generate a third set of PI codes from a speculative value of the delta signal that is based upon the first prior value and the second prior value of the delta signal using an algorithm that takes into account the direction and quantity of change between prior delta values; and a selection circuit configured to select, in response to the delta selection signal, between the first, second, and third sets of PI codes to provide the selection as an output of the clock data recovery device. a phase change determination circuit configured to: detect a phase difference between a data signal and a capture clock signal; and generate, based upon the detected phase difference, a delta signal and a delta selection signal, the delta signal representing an incremental change to a phase accumulator of the capture clock signal, the delta selection signal representing the actual delta value for a current iteration; and detect a phase difference between a data signal and a capture clock signal; and generate, based upon the detected phase difference, a delta signal and a delta selection signal, the delta signal representing an incremental change to a phase accumulator of the capture clock signal, the delta selection signal representing the actual delta value for a current iteration; and a speculative calculation circuit that includes: a first calculation circuit configured to generate a first set of phase interpolation codes from a first prior value of the delta signal; a second calculation circuit configured to generate a second set of PI codes from a second prior value of the delta signal; a third calculation circuit configured to generate a third set of PI codes from a speculative value of the delta signal that is based upon the first prior value and the second prior value of the delta signal using an algorithm that takes into account the direction and quantity of change between prior delta values; and a selection circuit configured to select, in response to the delta selection signal, between the first, second, and third sets of PI codes to provide the selection as an output of the clock data recovery device. a first calculation circuit configured to generate a first set of phase interpolation codes from a first prior value of the delta signal; a second calculation circuit configured to generate a second set of PI codes from a second prior value of the delta signal; a third calculation circuit configured to generate a third set of PI codes from a speculative value of the delta signal that is based upon the first prior value and the second prior value of the delta signal using an algorithm that takes into account the direction and quantity of change between prior delta values; and a selection circuit configured to select, in response to the delta selection signal, between the first, second, and third sets of PI codes to provide the selection as an output of the clock data recovery device.