A pixel circuit of a photo detector panel for generating a pixel image in a display cycle, comprising: a reset sub-circuit respectively coupled to a first node and a second node and controlled by a first control signal to provide an initialization voltage (V INI) to the first node and the second node in a reset period of the display cycle; a photoelectric-conversion sub-circuit coupled to the first node and configured to convert an optical signal to a first voltage at the first node; (V DATA) a driving sub-circuit comprising a bias input port configured to be provided with a bias voltage (V Bias), an output port configured to output a current signal, and being controlled by a second voltage at the second node (V B1, V B2); a compensation sub-circuit coupled between the first node and the second node and configured to be controlled by a second control signal to store the first voltage at the first node and connect the second node to a second terminal of a driving transistor (DTFT) in a compensation period of the display cycle to determine the second voltage at the second node (V B1), the second voltage being dependent on the bias voltage provided to the first terminal of the driving transistor and a threshold voltage of the driving transistor; and an integration sub-circuit coupled to the first node and controlled by a third control signal to provide a reference voltage to the first node in an integration period of the display cycle to determine a third voltage at the second node (V B2) to generate a current signal to the output port in an output period of the display cycle, wherein the current signal is substantially independent from the threshold voltage of the driving transistor and the bias voltage; the driving sub-circuit comprises the driving transistor (DTFT) having a first terminal coupled to the bias input port (V Bias), the second terminal coupled to the output port, and a gate terminal configured to receive the second voltage; wherein the photoelectric-conversion sub-circuit comprises a photodiode coupled between a first common voltage port and the first node and a pixel capacitor (C_P) coupled between a second common voltage port and the first node; wherein the first common voltage port is configured to be provided with a first common voltage (V Com1) set to be larger than the bias voltage (V Bias), the second common voltage port is configured to be provided with a second common voltage (V Com2) set to be smaller than the bias voltage; wherein the compensation sub-circuit comprises a fourth transistor having a first terminal coupled to the second node, a second terminal coupled to the second terminal of the driving transistor (DTFT), and a gate terminal configured to be controlled by the second control signal; and a storage capacitor: (Cst) having a first terminal coupled to the first node and a second terminal coupled to the second node. a reset sub-circuit respectively coupled to a first node and a second node and controlled by a first control signal to provide an initialization voltage (V INI) to the first node and the second node in a reset period of the display cycle; a photoelectric-conversion sub-circuit coupled to the first node and configured to convert an optical signal to a first voltage at the first node; (V DATA) a driving sub-circuit comprising a bias input port configured to be provided with a bias voltage (V Bias), an output port configured to output a current signal, and being controlled by a second voltage at the second node (V B1, V B2); a compensation sub-circuit coupled between the first node and the second node and configured to be controlled by a second control signal to store the first voltage at the first node and connect the second node to a second terminal of a driving transistor (DTFT) in a compensation period of the display cycle to determine the second voltage at the second node (V B1), the second voltage being dependent on the bias voltage provided to the first terminal of the driving transistor and a threshold voltage of the driving transistor; and an integration sub-circuit coupled to the first node and controlled by a third control signal to provide a reference voltage to the first node in an integration period of the display cycle to determine a third voltage at the second node (V B2) to generate a current signal to the output port in an output period of the display cycle, wherein the current signal is substantially independent from the threshold voltage of the driving transistor and the bias voltage; the driving sub-circuit comprises the driving transistor (DTFT) having a first terminal coupled to the bias input port (V Bias), the second terminal coupled to the output port, and a gate terminal configured to receive the second voltage; wherein the photoelectric-conversion sub-circuit comprises a photodiode coupled between a first common voltage port and the first node and a pixel capacitor (C_P) coupled between a second common voltage port and the first node; wherein the first common voltage port is configured to be provided with a first common voltage (V Com1) set to be larger than the bias voltage (V Bias), the second common voltage port is configured to be provided with a second common voltage (V Com2) set to be smaller than the bias voltage; wherein the compensation sub-circuit comprises a fourth transistor having a first terminal coupled to the second node, a second terminal coupled to the second terminal of the driving transistor (DTFT), and a gate terminal configured to be controlled by the second control signal; and a storage capacitor: (Cst) having a first terminal coupled to the first node and a second terminal coupled to the second node.