An apparatus, comprising: an image processing unit, comprising: a network (104, 1004, 1104); a plurality of stencil processor circuits each comprising an array of execution lanes including vertically and horizontally adjacent execution lanes (510, 601) and being coupled to a two-dimensional shift register array structure (306, 406) so that the execution lane array and shift register array structure are fixed in position relative to one another to simultaneously process multiple overlapping stencils, which are arranged vertically and horizontally, through execution of program code, wherein each execution lane operates on image data within a corresponding stencil, wherein image data within the two-dimensional shift register array structure (306, 406) may be, caused by the program code, shifted down, up, left and right; a plurality of sheet generators (103_1,..., 103_N, 803, 1003_1,..., 1003_5, 1103_1,..., 1103 N) respectively coupled between the plurality of stencil processors (102, 102_1,..., 102_N, 802, 1002_1,..., 1002_5, 1102_1,..., 1102_N) and the network (104, 1004, 1104), the sheet generators (103_1,..., 103_N, 803, 1003_1,..., 1003_5, 1103_1,..., 1103_N) to parse input line groups of image data into input sheets (204, 205) of image data and each sheet generator providing said input sheets of image data to a corresponding stencil processor for processing by the stencil processors (102, 102_1,..., 102_N, 802, 1002_1,..., 1002_5, 1102_1,..., 1102_N), and, to form output line groups of image data from output sheets of image data received from the stencil processors (102, 102_1,..., 102_N, 802, 1002_1,..., 1002_5, 1102_1,..., 1102_N); a plurality of line buffer units (101, 101_1,..., 101_M, 1001_1,..., 1001_6, 1101_1,..., 1101_5) coupled to the network (104, 1004, 1104) to pass line groups (901_1,..., 901_N) in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow. a network (104, 1004, 1104); a plurality of stencil processor circuits each comprising an array of execution lanes including vertically and horizontally adjacent execution lanes (510, 601) and being coupled to a two-dimensional shift register array structure (306, 406) so that the execution lane array and shift register array structure are fixed in position relative to one another to simultaneously process multiple overlapping stencils, which are arranged vertically and horizontally, through execution of program code, wherein each execution lane operates on image data within a corresponding stencil, wherein image data within the two-dimensional shift register array structure (306, 406) may be, caused by the program code, shifted down, up, left and right; a plurality of sheet generators (103_1,..., 103_N, 803, 1003_1,..., 1003_5, 1103_1,..., 1103 N) respectively coupled between the plurality of stencil processors (102, 102_1,..., 102_N, 802, 1002_1,..., 1002_5, 1102_1,..., 1102_N) and the network (104, 1004, 1104), the sheet generators (103_1,..., 103_N, 803, 1003_1,..., 1003_5, 1103_1,..., 1103_N) to parse input line groups of image data into input sheets (204, 205) of image data and each sheet generator providing said input sheets of image data to a corresponding stencil processor for processing by the stencil processors (102, 102_1,..., 102_N, 802, 1002_1,..., 1002_5, 1102_1,..., 1102_N), and, to form output line groups of image data from output sheets of image data received from the stencil processors (102, 102_1,..., 102_N, 802, 1002_1,..., 1002_5, 1102_1,..., 1102_N); a plurality of line buffer units (101, 101_1,..., 101_M, 1001_1,..., 1001_6, 1101_1,..., 1101_5) coupled to the network (104, 1004, 1104) to pass line groups (901_1,..., 901_N) in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.