A charge pump circuit arrangement, comprising: - a multitude of capacitors (110, 111, 112, 113) comprising a first group of capacitors (110, 112) and a second group of capacitors (111, 113); - the first group of capacitors coupled to a terminal for a first clock signal and the second group of capacitors coupled to a terminal for a second clock signal, the first and second clock signals having non-overlapping clock pulses; - switches (115, 116) configured to connect one of the capacitors to another one of the capacitors; - each one of the capacitors comprising a semiconductor substrate including a deep well doping region of a first conductivity type and a well doping region of a second conductivity type disposed above the deep well doping region of the first conductivity type, a portion of the capacitors disposed in the semiconductor substrate; - the deep well doping regions of the first group of capacitors (110, 112) controlled by a first control signal (CTRL1) that is in phase with the first clock signal and the deep well doping regions of the second group of capacitors (111, 113) controlled by a second control signal (CTRL2) that is in phase with the second clock signal, wherein the deep well doping regions of the capacitors of the first group are coupled to a switch circuit that is controlled by the first clock signal and that is connected to one of the capacitors of the first group and one of the capacitors of the second group and the deep well doping regions of the second group of capacitors are coupled to another switch circuit that is controlled by the second clock signal and that is connected to the one of the capacitors of the first group and the one of the capacitors of the second group and wherein the switch circuit and the other switch circuit each comprise a terminal for one of the first and second clock signals (CLK1, CLK2) and a series connection of complementary MOS transistors (410, 411) connected to the one of the capacitors of the first group and the one of the capacitors of the second group. - a multitude of capacitors (110, 111, 112, 113) comprising a first group of capacitors (110, 112) and a second group of capacitors (111, 113); - the first group of capacitors coupled to a terminal for a first clock signal and the second group of capacitors coupled to a terminal for a second clock signal, the first and second clock signals having non-overlapping clock pulses; - switches (115, 116) configured to connect one of the capacitors to another one of the capacitors; - each one of the capacitors comprising a semiconductor substrate including a deep well doping region of a first conductivity type and a well doping region of a second conductivity type disposed above the deep well doping region of the first conductivity type, a portion of the capacitors disposed in the semiconductor substrate; - the deep well doping regions of the first group of capacitors (110, 112) controlled by a first control signal (CTRL1) that is in phase with the first clock signal and the deep well doping regions of the second group of capacitors (111, 113) controlled by a second control signal (CTRL2) that is in phase with the second clock signal, wherein the deep well doping regions of the capacitors of the first group are coupled to a switch circuit that is controlled by the first clock signal and that is connected to one of the capacitors of the first group and one of the capacitors of the second group and the deep well doping regions of the second group of capacitors are coupled to another switch circuit that is controlled by the second clock signal and that is connected to the one of the capacitors of the first group and the one of the capacitors of the second group and wherein the switch circuit and the other switch circuit each comprise a terminal for one of the first and second clock signals (CLK1, CLK2) and a series connection of complementary MOS transistors (410, 411) connected to the one of the capacitors of the first group and the one of the capacitors of the second group.