A computer-implemented method (300, 400, 500) of generating a hardware design to calculate a modulo value for any integer input value in a target input range with respect to a constant divisor d, the hardware design comprising one or more range reduction stages and wherein the hardware design comprises computer readable instructions that, when processed at an integrated circuit manufacturing system, cause the integrated circuit manufacturing system to generate a manifestation of an integrated circuit to calculate the modulo value, the method comprising in a processing module: (a) generating at least one hardware design component to map a desired input range to a target output range using each of a plurality of modulo preserving range reduction methods (406, 504, 506), wherein the target output range is [0, d-1]; (b) synthesizing each of the hardware design components (408, 508); (c) analyzing the synthesized hardware design components and generating one or more synthesis metrics for each synthesized hardware design component based on the analysis, wherein the one or more synthesis metrics comprise one or more of delay, area, and power usage to produce a modulo value; (d) selecting one of the hardware design components as an optimum hardware design component for the desired input range based on the one or more synthesis metrics (408, 508); (e) determining whether a maximum input range of the optimum hardware design component comprises the target input range; (f) in response to determining that the maximum input range of the optimum hardware design component does not comprise the target input range, expanding the desired input range and repeating steps (a) to (d) for the expanded desired input range; and (g) in response to determining that the maximum input range of the optimum hardware design component comprises the target input range, outputting the optimum hardware design component (h) wherein each hardware design component is associated with one of the plurality of modulo preserving range reduction methods and generating a particular hardware design component comprises generating a primary hardware design component that uses the associated modulo preserving range reduction method to map the desired input range; (i) wherein generating the particular hardware design component further comprises: a. identifying an output range of the primary hardware design component; b. determining whether the identified output range of the primary hardware design component is greater than the target output range; and c. in response to determining that the identified output range of the primary hardware design component is greater than the target output range, combining the primary hardware design component with a previously identified optimum hardware design component to generate the particular hardware design component. (a) generating at least one hardware design component to map a desired input range to a target output range using each of a plurality of modulo preserving range reduction methods (406, 504, 506), wherein the target output range is [0, d-1]; (b) synthesizing each of the hardware design components (408, 508); (c) analyzing the synthesized hardware design components and generating one or more synthesis metrics for each synthesized hardware design component based on the analysis, wherein the one or more synthesis metrics comprise one or more of delay, area, and power usage to produce a modulo value; (d) selecting one of the hardware design components as an optimum hardware design component for the desired input range based on the one or more synthesis metrics (408, 508); (e) determining whether a maximum input range of the optimum hardware design component comprises the target input range; (f) in response to determining that the maximum input range of the optimum hardware design component does not comprise the target input range, expanding the desired input range and repeating steps (a) to (d) for the expanded desired input range; and (g) in response to determining that the maximum input range of the optimum hardware design component comprises the target input range, outputting the optimum hardware design component (h) wherein each hardware design component is associated with one of the plurality of modulo preserving range reduction methods and generating a particular hardware design component comprises generating a primary hardware design component that uses the associated modulo preserving range reduction method to map the desired input range; (i) wherein generating the particular hardware design component further comprises: a. identifying an output range of the primary hardware design component; b. determining whether the identified output range of the primary hardware design component is greater than the target output range; and c. in response to determining that the identified output range of the primary hardware design component is greater than the target output range, combining the primary hardware design component with a previously identified optimum hardware design component to generate the particular hardware design component. a. identifying an output range of the primary hardware design component; b. determining whether the identified output range of the primary hardware design component is greater than the target output range; and c. in response to determining that the identified output range of the primary hardware design component is greater than the target output range, combining the primary hardware design component with a previously identified optimum hardware design component to generate the particular hardware design component.