A processing device comprising: an executing unit configured to execute instructions included in a plurality of threads each having a plurality of instructions; an instruction supply control unit configured to supply the instructions to the executing unit; a plurality of instruction buffers configured to store, as an instruction stream, instructions to be supplied to the executing unit from a thread among the plurality of threads, each of the plurality of instruction buffers including a data unit configured to store the instruction stream in a plurality of entries, a thread id unit configured to store a thread id of the thread to which the stored instruction stream belongs, and a pointer unit defining a linking relationship between two instruction buffers by pointing to an instruction buffer storing an instruction to be executed next within the same thread; a cache memory unit stored with the instruction stream from a storage unit; an instruction fetch unit configured to control read of the subsequent instruction via the cache memory unit from a readout address of the storage unit and storage of the readout instruction into the instruction buffer; a plurality of instruction fetch address retaining units (11-1, 11-2) each provided individually on a per-thread basis each instruction fetch address retaining unit configured to retain the readout address of the instruction to be read next; a fetch sequence management unit configured to manage a sequence among a plurality of threads in the order of elapse time after the instruction fetch unit has requested an instruction fetch of instructions belonging to each of the plurality of threads; a fetch thread determining unit configured to determine a thread to be selected for the instruction fetch as the thread having a longer period of elapse time among the plurality of threads; and a control unit configured to control each of the plurality of instruction buffers by use of a thread allocating unit allocating the selected thread among the plurality of threads to which the instruction to be stored next belongs, to a next instruction buffer among instruction buffers established as invalid to store the subsequent instruction read by the instruction fetch unit. an executing unit configured to execute instructions included in a plurality of threads each having a plurality of instructions; an instruction supply control unit configured to supply the instructions to the executing unit; a plurality of instruction buffers configured to store, as an instruction stream, instructions to be supplied to the executing unit from a thread among the plurality of threads, each of the plurality of instruction buffers including a data unit configured to store the instruction stream in a plurality of entries, a thread id unit configured to store a thread id of the thread to which the stored instruction stream belongs, and a pointer unit defining a linking relationship between two instruction buffers by pointing to an instruction buffer storing an instruction to be executed next within the same thread; a cache memory unit stored with the instruction stream from a storage unit; an instruction fetch unit configured to control read of the subsequent instruction via the cache memory unit from a readout address of the storage unit and storage of the readout instruction into the instruction buffer; a plurality of instruction fetch address retaining units (11-1, 11-2) each provided individually on a per-thread basis each instruction fetch address retaining unit configured to retain the readout address of the instruction to be read next; a fetch sequence management unit configured to manage a sequence among a plurality of threads in the order of elapse time after the instruction fetch unit has requested an instruction fetch of instructions belonging to each of the plurality of threads; a fetch thread determining unit configured to determine a thread to be selected for the instruction fetch as the thread having a longer period of elapse time among the plurality of threads; and a control unit configured to control each of the plurality of instruction buffers by use of a thread allocating unit allocating the selected thread among the plurality of threads to which the instruction to be stored next belongs, to a next instruction buffer among instruction buffers established as invalid to store the subsequent instruction read by the instruction fetch unit.