A metal oxide semiconductor, MOS, device, comprising: a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate, a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate, the second MOS transistor source and the first MOS transistor source being coupled to a first voltage source, and a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the second MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source formed by the source of the first MOS transistor, the third MOS transistor drain formed by the source of the second MOS transistor, the third MOS transistor gate floating; a fourth MOS transistor having a fourth MOS transistor source, a fourth MOS transistor drain, and a fourth MOS transistor gate, a fifth MOS transistor having a fifth MOS transistor source, a fifth MOS transistor drain, and a fifth MOS transistor gate, the fifth MOS transistor source and the fourth MOS transistor source being coupled to a second voltage source; and wherein the first MOS transistor gate, the second MOS transistor gate, the fourth MOS transistor gate, and the fifth MOS transistor gate are connected together; and wherein the first MOS transistor drain, the second MOS transistor drain, the fourth MOS transistor drain, and the fifth MOS transistor drain are connected together; a sixth MOS transistor having a sixth MOS transistor source, a sixth MOS transistor drain, and a sixth MOS transistor gate the sixth MOS transistor source being formed by the source of the fourth MOS transistor, the sixth MOS transistor drain formed by the source of the fifth MOS transistor, the sixth MOS transistor gate floating, the sixth MOS transistor gate located between the fourth MOS transistor source and the fifth MOS transistor source; and wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor are p-type MOS, pMOS, transistors, and the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are n-type MOS, nMOS, transistors, and wherein the potential of the first voltage source is configured to be greater than the potential of the second voltage source. a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate, a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate, the second MOS transistor source and the first MOS transistor source being coupled to a first voltage source, and a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the second MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source formed by the source of the first MOS transistor, the third MOS transistor drain formed by the source of the second MOS transistor, the third MOS transistor gate floating; a fourth MOS transistor having a fourth MOS transistor source, a fourth MOS transistor drain, and a fourth MOS transistor gate, a fifth MOS transistor having a fifth MOS transistor source, a fifth MOS transistor drain, and a fifth MOS transistor gate, the fifth MOS transistor source and the fourth MOS transistor source being coupled to a second voltage source; and wherein the first MOS transistor gate, the second MOS transistor gate, the fourth MOS transistor gate, and the fifth MOS transistor gate are connected together; and wherein the first MOS transistor drain, the second MOS transistor drain, the fourth MOS transistor drain, and the fifth MOS transistor drain are connected together; a sixth MOS transistor having a sixth MOS transistor source, a sixth MOS transistor drain, and a sixth MOS transistor gate the sixth MOS transistor source being formed by the source of the fourth MOS transistor, the sixth MOS transistor drain formed by the source of the fifth MOS transistor, the sixth MOS transistor gate floating, the sixth MOS transistor gate located between the fourth MOS transistor source and the fifth MOS transistor source; and wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor are p-type MOS, pMOS, transistors, and the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are n-type MOS, nMOS, transistors, and wherein the potential of the first voltage source is configured to be greater than the potential of the second voltage source.