A short range radio communication device comprising: a transceiver; a clock circuit; a controller configured to operate the transceiver in a frequency range in accordance with a first frequency hopping sequence consisting of frequencies in a first segment of the frequency range and a second frequency hopping sequence consisting of frequencies in a second segment of the frequency range, wherein the first frequency hopping sequence and the second frequency hopping sequence are synchronized with the clock circuit, each segment having a phase across the frequencies of the frequency range, wherein said phase is based on the clock circuit; and a processing circuit configured to: determine a time offset between an initial starting point of operation of the transceiver in accordance with the first frequency hopping sequence in the first segment and a shifted starting point of the operation of the transceiver in accordance with the first frequency hopping sequence in a shifted first segment to determine a phase offset of the first frequency hopping sequence in the shifted first segment to the second frequency hopping sequence in the second segment so that the shifted first segment does not overlap the second segment; and control at least one of the controller and the clock circuit to operate the transceiver in accordance with the first frequency hopping sequence in the shifted first segment at the shifted starting point; wherein the shifted starting point is different from the initial starting point. a transceiver; a clock circuit; a controller configured to operate the transceiver in a frequency range in accordance with a first frequency hopping sequence consisting of frequencies in a first segment of the frequency range and a second frequency hopping sequence consisting of frequencies in a second segment of the frequency range, wherein the first frequency hopping sequence and the second frequency hopping sequence are synchronized with the clock circuit, each segment having a phase across the frequencies of the frequency range, wherein said phase is based on the clock circuit; and a processing circuit configured to: determine a time offset between an initial starting point of operation of the transceiver in accordance with the first frequency hopping sequence in the first segment and a shifted starting point of the operation of the transceiver in accordance with the first frequency hopping sequence in a shifted first segment to determine a phase offset of the first frequency hopping sequence in the shifted first segment to the second frequency hopping sequence in the second segment so that the shifted first segment does not overlap the second segment; and control at least one of the controller and the clock circuit to operate the transceiver in accordance with the first frequency hopping sequence in the shifted first segment at the shifted starting point; wherein the shifted starting point is different from the initial starting point. determine a time offset between an initial starting point of operation of the transceiver in accordance with the first frequency hopping sequence in the first segment and a shifted starting point of the operation of the transceiver in accordance with the first frequency hopping sequence in a shifted first segment to determine a phase offset of the first frequency hopping sequence in the shifted first segment to the second frequency hopping sequence in the second segment so that the shifted first segment does not overlap the second segment; and control at least one of the controller and the clock circuit to operate the transceiver in accordance with the first frequency hopping sequence in the shifted first segment at the shifted starting point;