Method for saturation detection of a transformer's iron core, in particular for a resistance spot welding transformer, by means of a binary logic, comprising the following steps: - determining a value of a first input into a first comparing means, said first input value representing a signal based on measuring the primary current of said transformer using a suitable measuring device configured to measure the instantaneous value of said primary current, or the slope of the primary current in the form of a corresponding time derivative of the primary current represented by an output voltage of a Rogowski coil; - determining a value of a second input into said first comparing means, said second input value representing a reference value of an amplitude or a slope of the current; - determining a binary output value b 1 of said first comparing means on the basis of comparing of said values of said first and said second inputs into said comparing means, wherein b 1 = 1 if the value of said first input in said first comparing means is greater or equal to the value of said second input in said first comparing means, this representing a first condition for saturation detection, and b 1 = 0, if the value of said first input is smaller than the value of said second input; - a first delaying step of delaying the output from said first comparing means with value b 1 for one sampling interval in order to obtain a value b 2 by using a first delaying means; - a second delaying step of delaying the output from said first delaying means with value b 2 for one sampling interval in order to obtain a value b 3 by using a second delaying means; - summing output values b 1, b 2, b 3, said sum equal to a value b 5, said summing performed by using an adding means, to obtain said value b 5; - determining whether b 5 is greater than a predetermined value, which is preferably 3, this representing a second condition for saturation detection, by using a second comparing means and setting an output value of said second comparing means to b 6 = 1 if this condition is met; - providing said output value b 6 of said second comparing means as an input to a timer configured for holding input b 6 for time T d, wherein T d = mT s, wherein value m and sampling time T s depend on a modulation frequency of the primary current, to obtain an output of said timer as a value b 7; - negating said value b 7 by providing it as input value b 7 into a negating means to obtain at the output of said negating means a value b 8; - setting an output from said binary logic to value 1, if at the same time b 6 = 1 and b 8 = 1, otherwise setting said output from binary logic to value 0 to obtain output value b 9; said output value of said binary logic being b 9 = 1 meaning confirmed saturation detection. - determining a value of a first input into a first comparing means, said first input value representing a signal based on measuring the primary current of said transformer using a suitable measuring device configured to measure the instantaneous value of said primary current, or the slope of the primary current in the form of a corresponding time derivative of the primary current represented by an output voltage of a Rogowski coil; - determining a value of a second input into said first comparing means, said second input value representing a reference value of an amplitude or a slope of the current; - determining a binary output value b 1 of said first comparing means on the basis of comparing of said values of said first and said second inputs into said comparing means, wherein b 1 = 1 if the value of said first input in said first comparing means is greater or equal to the value of said second input in said first comparing means, this representing a first condition for saturation detection, and b 1 = 0, if the value of said first input is smaller than the value of said second input; - a first delaying step of delaying the output from said first comparing means with value b 1 for one sampling interval in order to obtain a value b 2 by using a first delaying means; - a second delaying step of delaying the output from said first delaying means with value b 2 for one sampling interval in order to obtain a value b 3 by using a second delaying means; - summing output values b 1, b 2, b 3, said sum equal to a value b 5, said summing performed by using an adding means, to obtain said value b 5; - determining whether b 5 is greater than a predetermined value, which is preferably 3, this representing a second condition for saturation detection, by using a second comparing means and setting an output value of said second comparing means to b 6 = 1 if this condition is met; - providing said output value b 6 of said second comparing means as an input to a timer configured for holding input b 6 for time T d, wherein T d = mT s, wherein value m and sampling time T s depend on a modulation frequency of the primary current, to obtain an output of said timer as a value b 7; - negating said value b 7 by providing it as input value b 7 into a negating means to obtain at the output of said negating means a value b 8; - setting an output from said binary logic to value 1, if at the same time b 6 = 1 and b 8 = 1, otherwise setting said output from binary logic to value 0 to obtain output value b 9; said output value of said binary logic being b 9 = 1 meaning confirmed saturation detection.