A method for managing electrical power usage, comprising the steps of: providing an allocated amount of power during a first predetermined time period through a hot output line of an IGBT/FET based device having a digital signal processor; and monitoring the power consumed through said hot output line during said first predetermined time period with said digital signal processor; wherein said IGBT/FET based device comprises: at least one phase input connection configured for inputting a predetermined amount of incoming energy having at least one analog signal into said IGBT/FET based device; at least one sensor connected to said at least one phase input connection and configured for sensing said predetermined amount of incoming energy into said IGBT/FET based device; at least one volts zero crossing point detector in electrical connection with said at least one phase input connection and configured for determining at least one zero volts crossing point of said at least one analog signal; at least one half cycle identifier in electrical connection with said at least one phase input connection and configured for identifying at least one positive half cycle of said at least one analog signal and at least one negative half cycle of said at least one analog signal; at least one logic device in electrical connection with said at least one volts zero crossing point detector and said at least one half cycle identifier and configured for routing said at least one positive half cycle of said at least one analog signal and said at least one negative half cycle of said at least one analog signal to said digital signal processor; said digital signal processor in electrical connection with said at least one logic device and configured for processing said at least one analog signal; at least one voltage reducing means having at least one drive control wherein said at least one voltage reducing means is in electrical connection with said at least one digital signal processor and is configured for reducing said predetermined amount of incoming energy by providing pulse width modulation to the at least one analog signal to yield a reduced amount of energy; and at least one phase output connection in electrical connection with said at least one voltage reducing means and configured for outputting said reduced amount of energy out of said IGBT/FET based device; wherein the method further comprises sending a first signal with said digital signal processor when the monitored consumed power exceeds said allocated amount of power during said first predetermined time period, the first signal alerting the need to reduce power usage. providing an allocated amount of power during a first predetermined time period through a hot output line of an IGBT/FET based device having a digital signal processor; and monitoring the power consumed through said hot output line during said first predetermined time period with said digital signal processor; at least one phase input connection configured for inputting a predetermined amount of incoming energy having at least one analog signal into said IGBT/FET based device; at least one sensor connected to said at least one phase input connection and configured for sensing said predetermined amount of incoming energy into said IGBT/FET based device; at least one volts zero crossing point detector in electrical connection with said at least one phase input connection and configured for determining at least one zero volts crossing point of said at least one analog signal; at least one half cycle identifier in electrical connection with said at least one phase input connection and configured for identifying at least one positive half cycle of said at least one analog signal and at least one negative half cycle of said at least one analog signal; at least one logic device in electrical connection with said at least one volts zero crossing point detector and said at least one half cycle identifier and configured for routing said at least one positive half cycle of said at least one analog signal and said at least one negative half cycle of said at least one analog signal to said digital signal processor; said digital signal processor in electrical connection with said at least one logic device and configured for processing said at least one analog signal; at least one voltage reducing means having at least one drive control wherein said at least one voltage reducing means is in electrical connection with said at least one digital signal processor and is configured for reducing said predetermined amount of incoming energy by providing pulse width modulation to the at least one analog signal to yield a reduced amount of energy; and at least one phase output connection in electrical connection with said at least one voltage reducing means and configured for outputting said reduced amount of energy out of said IGBT/FET based device; wherein