A FET MMIC chip power amplifier, comprising: a plurality of field effect transistor, FET, cells configured to receive and amplify an RF input signal, each FET cell of the plurality of FET cells comprising: a source region, a drain region, and a gate electrode configured to receive said RF input signal and to control carriers through a channel region of a semiconductor region of the FET MMIC chip power amplifier between the source region and the drain region; wherein the gate electrodes of the plurality of FET cells are parallel one to another; and wherein the gate electrode of each FET cell has one end connected to a common gate manifold contact pad; drain electrodes in ohmic contact with the drain regions of the plurality of FET cells, wherein the drain electrodes have ends thereof connected to a drain manifold contact pad; the plurality of FET cells further comprising a linearizing diode having: a cathode electrode consisting of a first drain electrode of the drain electrodes in ohmic contact with a first drain region of one FET cell of the plurality of FET cells and a second drain electrode of the drain electrodes in ohmic contact with a second drain region of an adjacent FET cell of the plurality of FET cells to provide a cathode for the linearizing diode, the linearizing diode being disposed between said first and second drain region, said cathode electrode being connected to the drain manifold contact pad; an anode electrode in Schottky contact with a diode region of the semiconductor region between said first and second drain region and disposed along a line parallel to the gate electrodes to provide an anode for the linearizing diode, said anode electrode being connected to the common gate manifold contact pad; the linearizing diode being configured to compensate a non-linear gate to source capacitance, Cgs, versus gate to source voltage, Vgs, variation of the plurality of FET cells. a plurality of field effect transistor, FET, cells configured to receive and amplify an RF input signal, each FET cell of the plurality of FET cells comprising: a source region, a drain region, and a gate electrode configured to receive said RF input signal and to control carriers through a channel region of a semiconductor region of the FET MMIC chip power amplifier between the source region and the drain region; wherein the gate electrodes of the plurality of FET cells are parallel one to another; and wherein the gate electrode of each FET cell has one end connected to a common gate manifold contact pad; a source region, a drain region, and a gate electrode configured to receive said RF input signal and to control carriers through a channel region of a semiconductor region of the FET MMIC chip power amplifier between the source region and the drain region; wherein the gate electrodes of the plurality of FET cells are parallel one to another; and wherein the gate electrode of each FET cell has one end connected to a common gate manifold contact pad; drain electrodes in ohmic contact with the drain regions of the plurality of FET cells, wherein the drain electrodes have ends thereof connected to a drain manifold contact pad; the plurality of FET cells further comprising a linearizing diode having: a cathode electrode consisting of a first drain electrode of the drain electrodes in ohmic contact with a first drain region of one FET cell of the plurality of FET cells and a second drain electrode of the drain electrodes in ohmic contact with a second drain region of an adjacent FET cell of the plurality of FET cells to provide a cathode for the linearizing diode, the linearizing diode being disposed between said first and second drain region, said cathode electrode being connected to the drain manifold contact pad; an anode electrode in Schottky contact with a diode region of the semiconductor region between said first and second drain region and disposed along a line parallel to the gate electrodes to provide an anode for the linearizing diode, said anode electrode being connected to the common gate manifold contact pad; the linearizing diode being configured to compensate a non-linear gate to source capacitance, Cgs, versus gate to source voltage, Vgs, variation of the plurality of FET cells. a cathode electrode consisting of a first drain electrode of the drain electrodes in ohmic contact with a first drain region of one FET cell of the plurality of FET cells and a second drain electrode of the drain electrodes in ohmic contact with a second drain region of an adjacent FET cell of the plurality of FET cells to provide a cathode for the linearizing diode, the linearizing diode being disposed between said first and second drain region, said cathode electrode being connected to the drain manifold contact pad; an anode electrode in Schottky contact with a diode region of the semiconductor region between said first and second drain region and disposed along a line parallel to the gate electrodes to provide an anode for the linearizing diode, said anode electrode being connected to the common gate manifold contact pad; the linearizing diode being configured to compensate a non-linear gate to source capacitance, Cgs, versus gate to source voltage, Vgs, variation of the plurality of FET cells.