An integrated circuit comprising: a power switch coupled between a first voltage supply node and an internal voltage supply node (VDD_INT), wherein the power switch is a p-type power switch; and a switch control circuit coupled to a control electrode of the power switch, wherein the switch control circuit includes: a driver circuit coupled between a second voltage supply node (VDD_CTL) and a third voltage supply node; a pass-gate having a first node coupled to an output of the driver circuit, a second node coupled to the control electrode of the power switch, and a control input; a pull-up transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the control electrode of the power switch, and a control electrode, wherein the pull-up transistor is a p-type transistor; a bias circuit coupled to each of the first and second voltage supply nodes and having a bias output configured to provide a higher voltage between the first and the second voltage supply nodes as a bias voltage to a body electrode of the pull-up transistor; and a resistor-capacitor circuit coupled between the bias output and the third voltage supply node, and having an output coupled to the control electrode of the pull-up transistor, wherein the RC circuit comprises: a first RC circuit PMOS transistor having a first current electrode and a body electrode coupled to the bias output, a second current electrode coupled to the control electrode of the pull-up transistor, and a control electrode coupled to the third voltage supply node; and a capacitive element coupled between the control electrode of the pull-up transistor and the third voltage supply node. a power switch coupled between a first voltage supply node and an internal voltage supply node (VDD_INT), wherein the power switch is a p-type power switch; and a switch control circuit coupled to a control electrode of the power switch, wherein the switch control circuit includes: a driver circuit coupled between a second voltage supply node (VDD_CTL) and a third voltage supply node; a pass-gate having a first node coupled to an output of the driver circuit, a second node coupled to the control electrode of the power switch, and a control input; a pull-up transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the control electrode of the power switch, and a control electrode, wherein the pull-up transistor is a p-type transistor; a bias circuit coupled to each of the first and second voltage supply nodes and having a bias output configured to provide a higher voltage between the first and the second voltage supply nodes as a bias voltage to a body electrode of the pull-up transistor; and a resistor-capacitor circuit coupled between the bias output and the third voltage supply node, and having an output coupled to the control electrode of the pull-up transistor, wherein the RC circuit comprises: a first RC circuit PMOS transistor having a first current electrode and a body electrode coupled to the bias output, a second current electrode coupled to the control electrode of the pull-up transistor, and a control electrode coupled to the third voltage supply node; and a capacitive element coupled between the control electrode of the pull-up transistor and the third voltage supply node. a driver circuit coupled between a second voltage supply node (VDD_CTL) and a third voltage supply node; a pass-gate having a first node coupled to an output of the driver circuit, a second node coupled to the control electrode of the power switch, and a control input; a pull-up transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the control electrode of the power switch, and a control electrode, wherein the pull-up transistor is a p-type transistor; a bias circuit coupled to each of the first and second voltage supply nodes and having a bias output configured to provide a higher voltage between the first and the second voltage supply nodes as a bias voltage to a body electrode of the pull-up transistor; and a resistor-capacitor circuit coupled between the bias output and the third voltage supply node, and having an output coupled to the control electrode of the pull-up transistor, wherein the RC circuit comprises: a first RC circuit PMOS transistor having a first current electrode and a body electrode coupled to the bias output, a second current electrode coupled to the control electrode of the pull-up transistor, and a control electrode coupled to the third voltage supply node; and a capacitive element coupled between the control electrode of the pull-up transistor and the third voltage supply node. a first RC circuit PMOS transistor having a first current electrode and a body electrode coupled to the bias output, a second current electrode coupled to the control electrode of the pull-up transistor, and a control electrode coupled to the third voltage supply node; and a capacitive element coupled between the control electrode of the pull-up transistor and the third voltage supply node.