A microcontroller comprising: a first central processing unit, CPU,; a first memory coupled with said CPU through a first data bus; a programmable cycle state machine coupled with the first memory and said CPU through said first data bus and comprising a second memory coupled with said first data bus and comprising a second data bus, wherein the programmable cycle state machine is configured to transfer data from said second memory through said second data bus to a display device to drive said display device and comprising a connection to the display device; a register unit programmable by said CPU and configured for storing a program for the programmable cycle state machine and being coupled with the programmable cycle state machine; a special instruction processing unit, SIPU, (1401; 1603) comprising an opcode interface, wherein the SIPU is operable to read and write data to said first memory and to receive instructions directly from the CPU through said opcode interface and comprising an arithmetic logic unit, ALU, and a register bank coupled with the ALU; a plurality of configuration registers programmable by said CPU; wherein in response to a command from the CPU the SIPU by means of said ALU and associated register bank is operable to manipulate multiple values in the first memory which are to be transferred to said display device, wherein said command is stored in one of said configuration registers; wherein the programmable cycle state machine is configured by said CPU through said register unit to continuously transfer data from the first memory to the display device; and wherein the programmable cycle state machine is operable to periodically transmit a control signal to the display device to coordinate the data transfers with the input timing requirements of the display device. a first central processing unit, CPU,; a first memory coupled with said CPU through a first data bus; a programmable cycle state machine coupled with the first memory and said CPU through said first data bus and comprising a second memory coupled with said first data bus and comprising a second data bus, wherein the programmable cycle state machine is configured to transfer data from said second memory through said second data bus to a display device to drive said display device and comprising a connection to the display device; a register unit programmable by said CPU and configured for storing a program for the programmable cycle state machine and being coupled with the programmable cycle state machine; a special instruction processing unit, SIPU, (1401; 1603) comprising an opcode interface, wherein the SIPU is operable to read and write data to said first memory and to receive instructions directly from the CPU through said opcode interface and comprising an arithmetic logic unit, ALU, and a register bank coupled with the ALU; a plurality of configuration registers programmable by said CPU; wherein in response to a command from the CPU the SIPU by means of said ALU and associated register bank is operable to manipulate multiple values in the first memory which are to be transferred to said display device, wherein said command is stored in one of said configuration registers; wherein the programmable cycle state machine is configured by said CPU through said register unit to continuously transfer data from the first memory to the display device; and wherein the programmable cycle state machine is operable to periodically transmit a control signal to the display device to coordinate the data transfers with the input timing requirements of the display device.