A radio transmitter, comprising: a digital domain signal processing module and a balanced Doherty power amplifier circuit, wherein the balanced Doherty power amplifier circuit comprises: a first peak amplifier, wherein an input end of the first peak amplifier is connected to a first input end of the balanced Doherty power amplifier circuit; a first matching unit, wherein an input end of the first matching unit is directly connected to an output end of the first peak amplifier, and an output end of the first matching unit is connected to an output end (Vout) of the balanced Doherty power amplifier circuit; a first main amplifier, wherein an input end of the first main amplifier is directly connected to a second input end of the balanced Doherty power amplifier circuit, and an output end of the first main amplifier is directly connected to the input end of the first matching unit via a respective one-fourth wavelength line; a second peak amplifier, wherein an input end of the second peak amplifier is connected to the first input end of the balanced Doherty power amplifier circuit; a second matching unit, wherein an input end of the second matching unit is directly connected to an output end of the second peak amplifier, and an output end of the second matching unit is connected to the output end (Vout) of the balanced Doherty power amplifier circuit; and a second main amplifier, wherein an input end of the second main amplifier is directly connected to the second input end of the balanced Doherty power amplifier circuit, and an output end of the second main amplifier is directly connected to the input end of the second matching unit via a respective one-fourth wavelength line; the input end of the first peak amplifier is directly connected to the first input end (Vim) of the balanced Doherty power amplifier circuit via a respective one-fourth wavelength line; and the input end of the second peak amplifier is directly connected to the first input end (Vim) of the balanced Doherty power amplifier circuit via a respective one-fourth wavelength line; the digital domain signal processing module is connected to the first input end (Vim) and the second input end of the balanced Doherty power amplifier circuit, and is configured to provide an input signal that matches the balanced Doherty power amplifier circuit. a first peak amplifier, wherein an input end of the first peak amplifier is connected to a first input end of the balanced Doherty power amplifier circuit; a first matching unit, wherein an input end of the first matching unit is directly connected to an output end of the first peak amplifier, and an output end of the first matching unit is connected to an output end (Vout) of the balanced Doherty power amplifier circuit; a first main amplifier, wherein an input end of the first main amplifier is directly connected to a second input end of the balanced Doherty power amplifier circuit, and an output end of the first main amplifier is directly connected to the input end of the first matching unit via a respective one-fourth wavelength line; a second peak amplifier, wherein an input end of the second peak amplifier is connected to the first input end of the balanced Doherty power amplifier circuit; a second matching unit, wherein an input end of the second matching unit is directly connected to an output end of the second peak amplifier, and an output end of the second matching unit is connected to the output end (Vout) of the balanced Doherty power amplifier circuit; and a second main amplifier, wherein an input end of the second main amplifier is directly connected to the second input end of the balanced Doherty power amplifier circuit, and an output end of the second main amplifier is directly connected to the input end of the second matching unit via a respective one-fourth wavelength line; the input end of the first peak amplifier is directly connected to the first input end (Vim) of the balanced Doherty power amplifier circuit via a respective one-fourth wavelength line; and the input end of the second peak amplifier is directly connected to the first input end (Vim) of the balanced Doherty power amplifier circuit via a respective one-fourth wavelength line; the digital domain signal processing module is connected to the first input end (Vim) and the second input end of the balanced Doherty power amplifier circuit, and is configured to provide an input signal that matches the balanced Doherty power amplifier circuit.