A current output circuit, comprising - an output terminal, - a first current mirror, - a first pass transistor fabricated as n-channel field-effect transistor, - a first delivering terminal at which a first voltage is tapped, - a second current mirror, - a second pass transistor fabricated as p-channel field-effect transistor, and - a second delivering terminal at which a second voltage is tapped with V1 ≥ V2, wherein the first current mirror and the first pass transistor form a current source and the second current mirror and the second pass transistor form a current sink, wherein the first current mirror comprises a first mirror transistor and a further mirror transistor which are both fabricated as p-channel field-effect transistors, wherein a first terminal of the first mirror transistor and a first terminal of the further mirror transistor of the first current mirror are connected to the first delivering terminal, wherein a control terminal of the first mirror transistor is connected to a control terminal of the further mirror transistor of the first current mirror and to a second terminal of the further mirror transistor of the first current mirror, wherein a series circuit consisting of the first mirror transistor and of the first pass transistor is adapted to couple the first delivering terminal to the output terminal, wherein the second current mirror comprises a second mirror transistor and an additional mirror transistor which are both fabricated as n-channel field-effect transistors, wherein a first terminal of the second mirror transistor and a first terminal of the additional mirror transistor of the second current mirror are connected to the second delivering terminal, wherein control terminals of the second mirror transistor and of the additional mirror transistor of the second current mirror are connected to each other and to a second terminal of the additional mirror transistor of the second current mirror, and wherein a series circuit consisting of the second mirror transistor and the second pass transistor is adapted to connect the second delivering terminal to the output terminal, characterized in that: the first pass transistor has a bulk terminal that is connected to a first node between the first pass transistor and the first mirror transistor, wherein the second pass transistor has a bulk terminal that is connected to a second node between the second pass transistor and the second mirror transistor, wherein the output circuit comprises a first node switch that is adapted to couple a first common terminal to the first node and a second node switch that is adapted to couple the second node to a second common terminal, wherein a first common voltage is tapped at the first common terminal and a second common voltage is tapped at the second common terminal, wherein the output circuit comprises a first control switch that is adapted to couple the first common terminal to a control terminal of the first pass transistor and a second control switch that is adapted to couple the second common terminal to a control terminal of the second pass transistor, and wherein the output circuit comprises a control circuit which is adapted to provide a digital signal to the control terminal of the first node switch and of the first control switch and an additional digital signal to the control terminal of the second node switch and of the second control switch. - an output terminal, - a first current mirror, - a first pass transistor fabricated as n-channel field-effect transistor, - a first delivering terminal at which a first voltage is tapped, - a second current mirror, - a second pass transistor fabricated as p-channel field-effect transistor, and - a second delivering terminal at which a second voltage is tapped with V1 ≥ V2, the first pass transistor has a bulk terminal that is connected to a first node between the first pass transistor and the first mirror transistor, wherein the second pass transistor has a bulk terminal that is connected to a second node between the second pass transistor and the second mirror transistor, wherein the output circuit comprises a first node switch that is adapted to couple a first common terminal to the first node and a second node switch that is adapted to couple the second node to a second common terminal, wherein a first common voltage is tapped at the first common terminal and a second common voltage is tapped at the second common terminal, wherein the output circuit comprises a first control switch that is adapted to couple the first common terminal to a control terminal of the first pass transistor and a second control switch that is adapted to couple the second common terminal to a control terminal of the second pass transistor, and wherein the output circuit comprises a control circuit which is adapted to provide a digital signal to the control terminal of the first node switch and of the first control switch and an additional digital signal to the control terminal of the second node switch and of the second control switch.