A very-small-aperture terminal, VSAT, (14a-14f, 200) comprising: an application-specific integrated circuit, ASIC, (510, 770), said ASIC comprising: a first transmit modulator configured to modulate an input information signal, the first transmit modulator comprising a burst formatter configured to burst format the input information signal, wherein said ASIC is configured to operate in a regular mode or bypass mode, wherein during the regular mode of operation, a remainder of the first transmit modulator is configured to modulate the burst-formatted input information signal, and wherein during the bypass mode of operation, the burst-formatted input information signal comprises fewer burst segments than in the regular mode of operation and bypasses the remainder of the first transmit modulator; and an output configured to receive the burst formatted input information signal bypassing the remainder of the first transmit modulator during the bypass mode of operation; and wherein said VSAT further comprising: a field programmable gate array, FPGA, (520, 780), said FPGA comprising: an input coupled to the output and configured to receive the burst-formatted input information signal bypassing the remainder of the first transmit modulator; and a second transmit modulator (522, 600) configured to modulate the burst-formatted input information signal bypassing the remainder of the first transmit modulator, wherein said FPGA is configured to insert additional burst segments into the burst-formatted input information signal prior to the second transmit modulator modulating the burst-formatted input information signal. an application-specific integrated circuit, ASIC, (510, 770), said ASIC comprising: a first transmit modulator configured to modulate an input information signal, the first transmit modulator comprising a burst formatter configured to burst format the input information signal, wherein said ASIC is configured to operate in a regular mode or bypass mode, wherein during the regular mode of operation, a remainder of the first transmit modulator is configured to modulate the burst-formatted input information signal, and wherein during the bypass mode of operation, the burst-formatted input information signal comprises fewer burst segments than in the regular mode of operation and bypasses the remainder of the first transmit modulator; and an output configured to receive the burst formatted input information signal bypassing the remainder of the first transmit modulator during the bypass mode of operation; and wherein said VSAT further comprising: a first transmit modulator configured to modulate an input information signal, the first transmit modulator comprising a burst formatter configured to burst format the input information signal, wherein said ASIC is configured to operate in a regular mode or bypass mode, wherein during the regular mode of operation, a remainder of the first transmit modulator is configured to modulate the burst-formatted input information signal, and wherein during the bypass mode of operation, the burst-formatted input information signal comprises fewer burst segments than in the regular mode of operation and bypasses the remainder of the first transmit modulator; and an output configured to receive the burst formatted input information signal bypassing the remainder of the first transmit modulator during the bypass mode of operation; and wherein said VSAT further comprising: a field programmable gate array, FPGA, (520, 780), said FPGA comprising: an input coupled to the output and configured to receive the burst-formatted input information signal bypassing the remainder of the first transmit modulator; and a second transmit modulator (522, 600) configured to modulate the burst-formatted input information signal bypassing the remainder of the first transmit modulator, wherein said FPGA is configured to insert additional burst segments into the burst-formatted input information signal prior to the second transmit modulator modulating the burst-formatted input information signal. an input coupled to the output and configured to receive the burst-formatted input information signal bypassing the remainder of the first transmit modulator; and a second transmit modulator (522, 600) configured to modulate the burst-formatted input information signal bypassing the remainder of the first transmit modulator, wherein said FPGA is configured to insert additional burst segments into the burst-formatted input information signal prior to the second transmit modulator modulating the burst-formatted input information signal.