A data storage circuit comprising an array of memory cells (BC ij), of N rows (L i) and M columns (C j), produced on a semiconductor substrate, comprising: - for each row (L i), a first input node (WL<i>) configured to receive a selection signal (VWL<i>); - at least one second input node (SL<j>) configured to receive a first write voltage (VSL<j>); - for each column (C j), an input/output node (BL<j>) configured to receive a second write voltage (VBL<j>) and supply a read voltage (VBL<j>); - the memory cells (BC ij) being configurable and non-volatile; each one being intended to operate in either one of two operating configurations (CONF 1, CONF2); the first operating configuration (CONF1) corresponding to a ferroelectric memory with varying electrical bias; and the second operating configuration (CONF2) corresponding to a resistive memory with varying conductive filament; each memory cell (BC ij) comprising: • a stack of thin layers in the following order: a first layer made of an electrically conductive material forming a lower electrode, a second layer made of a dielectric and ferroelectric material, a third layer made of electrically conductive material forming an upper electrode connected to the second input node (SL<j>) associated with the column of said memory cell (BC ij); • a selection transistor having a gate connected to the first input node (WL<i>) associated with the row of said memory cell (BC ij) and connecting the lower electrode to the input/output node (BL<j>) associated with the column of said memory cell (BC ij); the data storage circuit being configured, upon each transition from one operating configuration, called starting configuration, to the other operating configuration (CONF1, CONF2), called finishing configuration, to perform the following: - reading each memory cell (BC ij) in the starting configuration and temporarily storing a resulting read signal; - applying a transformation voltage to each memory cell (BC ij); - converting each read signal in the starting configuration into a write signal compatible with the finishing configuration; - rewriting each memory cell (BC ij) based on the write signals compatible with the starting configuration. - for each row (L i), a first input node (WL<i>) configured to receive a selection signal (VWL<i>); - at least one second input node (SL<j>) configured to receive a first write voltage (VSL<j>); - for each column (C j), an input/output node (BL<j>) configured to receive a second write voltage (VBL<j>) and supply a read voltage (VBL<j>); - the memory cells (BC ij) being configurable and non-volatile; each one being intended to operate in either one of two operating configurations (CONF 1, CONF2); the first operating configuration (CONF1) corresponding to a ferroelectric memory with varying electrical bias; and the second operating configuration (CONF2) corresponding to a resistive memory with varying conductive filament; each memory cell (BC ij) comprising: • a stack of thin layers in the following order: a first layer made of an electrically conductive material forming a lower electrode, a second layer made of a dielectric and ferroelectric material, a third layer made of electrically conductive material forming an upper electrode connected to the second input node (SL<j>) associated with the column of said memory cell (BC ij); • a selection transistor having a gate connected to the first input node (WL<i>) associated with the row of said memory cell (BC ij) and connecting the lower electrode to the input/output node (BL<j>) associated with the column of said memory cell (BC ij); • a stack of thin layers in the following order: a first layer made of an electrically conductive material forming a lower electrode, a second layer made of a dielectric and ferroelectric material, a third layer made of electrically conductive material forming an upper electrode connected to the second input node (SL<j>) associated with the column of said memory cell (BC ij); • a selection transistor having a gate connected to the first input node (WL<i>) associated with the row of said memory cell (BC ij) and connecting the lower electrode to the input/output node (BL<j>) associated with the column of said memory cell (BC ij); the data storage circuit being configured, upon each transition from one operating configuration, called starting configuration, to the other operating configuration (CONF1, CONF2), called finishing configuration, to perform the following: - reading each memory cell (BC ij) in the starting configuration and temporarily storing a resulting read signal; - applying a transformation voltage to each memory cell (BC ij); - converting each read signal in the starting configuration into a write signal compatible with the finishing configuration; - rewriting each memory cell (BC ij) based on the write signals compatible with the starting configuration. - reading each memory cell (BC ij) in the starting configuration and temporarily storing a resulting read signal; - applying a transformation voltage to each memory cell (BC ij); - converting each read signal in the starting configuration into a write signal compatible with the finishing configuration; - rewriting each memory cell (BC ij) based on the write signals compatible with the starting configuration.