A method, comprising: receiving an instruction (202; 302; 404) comprising a first operand and a second operand, the first operand specifying a data value to be translated to a first physical address when a processor processes the instruction in non-privileged mode, the second operand specifying a virtual address associated with a location of a first register in a surrogate memory accessing agent when the processor processes the instruction in non-privileged mode, the first operand specifying the first physical address when the processor processes the instruction in privileged mode, and the second operand specifying a second physical address associated with the location of the first register in the surrogate memory accessing agent when the processor processes the instruction in privileged mode; translating by a memory management unit the data value to the first physical address when the processor processes the instruction in non-privileged mode; translating the virtual address by the memory management unit to the second physical address associated with the location of the first register in the surrogate memory accessing agent when the processor processes the instruction in non-privileged mode; providing, when the processor processes the instruction in privileged mode, the first physical address as input from the processor to a multiplexer, where the multiplexer provides the input received from the processor to the surrogate memory accessing agent; and storing the first physical address in the first register in the surrogate memory accessing agent associated with the second physical address. receiving an instruction (202; 302; 404) comprising a first operand and a second operand, the first operand specifying a data value to be translated to a first physical address when a processor processes the instruction in non-privileged mode, the second operand specifying a virtual address associated with a location of a first register in a surrogate memory accessing agent when the processor processes the instruction in non-privileged mode, the first operand specifying the first physical address when the processor processes the instruction in privileged mode, and the second operand specifying a second physical address associated with the location of the first register in the surrogate memory accessing agent when the processor processes the instruction in privileged mode; translating by a memory management unit the data value to the first physical address when the processor processes the instruction in non-privileged mode; translating the virtual address by the memory management unit to the second physical address associated with the location of the first register in the surrogate memory accessing agent when the processor processes the instruction in non-privileged mode; providing, when the processor processes the instruction in privileged mode, the first physical address as input from the processor to a multiplexer, where the multiplexer provides the input received from the processor to the surrogate memory accessing agent; and storing the first physical address in the first register in the surrogate memory accessing agent associated with the second physical address.