A system for suppressing power supply noise, comprising: a first p-channel field effect transistor, PFET,, wherein a first PFET source and a first PFET body of the first PFET are connected to a voltage supply; a first n-channel field effect transistor, NFET,, wherein a first NFET source and a first NFET body of the first NFET are connected to ground; and at least one capacitive device comprising a single one of a second NFET and a second PFET, wherein the first PFET and the first NFET are connected in a half-cross-coupled configuration so that: a first PFET drain of the first PFET is connected to a first NFET gate of the first NFET without connection of the first PFET drain of the first PFET or the first NFET gate of the first NFET to the voltage supply, a first NFET drain of the first NFET is connected to a first PFET gate of the first PFET without connection of the first NFET drain of the first NFET or the first PFET gate of the first PFET to ground, in an instance when the at least one capacitive device comprises a single second NFET without the second PFET, a second NFET drain, a second NFET source, and a second NFET body of the second NFET are connected to ground, and a second NFET gate of the second NFET is connected to the first NFET gate of the first NFET without connection of the second NFET gate of the second NFET to ground or to the voltage supply, and in an instance when the at least one capacitive device comprises a single second PFET without the second NFET, a second PFET drain, a second PFET source, and a second PFET body of the second PFET are connected to the voltage supply, and a second PFET gate of the second PFET is connected to the first PFET gate of the first PFET without connection of the second PFET gate of the second PFET to the voltage supply or to ground. a first p-channel field effect transistor, PFET,, wherein a first PFET source and a first PFET body of the first PFET are connected to a voltage supply; a first n-channel field effect transistor, NFET,, wherein a first NFET source and a first NFET body of the first NFET are connected to ground; and at least one capacitive device comprising a single one of a second NFET and a second PFET, wherein the first PFET and the first NFET are connected in a half-cross-coupled configuration so that: a first PFET drain of the first PFET is connected to a first NFET gate of the first NFET without connection of the first PFET drain of the first PFET or the first NFET gate of the first NFET to the voltage supply, a first NFET drain of the first NFET is connected to a first PFET gate of the first PFET without connection of the first NFET drain of the first NFET or the first PFET gate of the first PFET to ground, in an instance when the at least one capacitive device comprises a single second NFET without the second PFET, a second NFET drain, a second NFET source, and a second NFET body of the second NFET are connected to ground, and a second NFET gate of the second NFET is connected to the first NFET gate of the first NFET without connection of the second NFET gate of the second NFET to ground or to the voltage supply, and in an instance when the at least one capacitive device comprises a single second PFET without the second NFET, a second PFET drain, a second PFET source, and a second PFET body of the second PFET are connected to the voltage supply, and a second PFET gate of the second PFET is connected to the first PFET gate of the first PFET without connection of the second PFET gate of the second PFET to the voltage supply or to ground. a first PFET drain of the first PFET is connected to a first NFET gate of the first NFET without connection of the first PFET drain of the first PFET or the first NFET gate of the first NFET to the voltage supply, a first NFET drain of the first NFET is connected to a first PFET gate of the first PFET without connection of the first NFET drain of the first NFET or the first PFET gate of the first PFET to ground, in an instance when the at least one capacitive device comprises a single second NFET without the second PFET, a second NFET drain, a second NFET source, and a second NFET body of the second NFET are connected to ground, and a second NFET gate of the second NFET is connected to the first NFET gate of the first NFET without connection of the second NFET gate of the second NFET to ground or to the voltage supply, and in an instance when the at least one capacitive device comprises a single second PFET without the second NFET, a second PFET drain, a second PFET source, and a second PFET body of the second PFET are connected to the voltage supply, and a second PFET gate of the second PFET is connected to the first PFET gate of the first PFET without connection of the second PFET gate of the second PFET to the voltage supply or to ground.