An apparatus, comprising: a plurality of NAND strings (NS1, NS2, 700n, 710n, 720n and 730n) extending vertically in a stack, each NAND string comprising a source end, a source side select gate transistor (701, 721, 741, 761) at the source end, a drain end, a dummy memory cell (703, 723, 743, 763) adjacent to a source side data memory cell (704, 724, 744, 764), and a plurality of non-source side data memory cells (705-714, 725-734, 745-754, 765-774) between the source side data memory cell and the drain end; a dummy word line (WLDS1) connected to the dummy memory cells; a plurality of data word lines (WLL0-WLL10) comprising a source side data word line connected to the source side data memory cell and non-source side data word lines (WLL1-WLL10) connected to the non-source side data memory cells; and a control circuit (110, 122), the control circuit configured to apply a voltage at a control gate read level (VvA, VvB, VcC, VrA, VrB, VrC) to a selected data word line among the plurality of data word lines while sensing memory cells connected to the selected data word line and while applying a voltage at a read pass level (Vread pass) to unselected data word lines among the plurality of data word lines; characterised in that the control circuit is further configured to: subsequently ramp down a voltage of the non-source side data word lines to a steady state voltage, followed by, after the ramping down the voltage of the non-source side data word lines to the steady state voltage, ramping down a voltage of the source side data word line and the voltage of the dummy word line to the steady state voltage. a plurality of NAND strings (NS1, NS2, 700n, 710n, 720n and 730n) extending vertically in a stack, each NAND string comprising a source end, a source side select gate transistor (701, 721, 741, 761) at the source end, a drain end, a dummy memory cell (703, 723, 743, 763) adjacent to a source side data memory cell (704, 724, 744, 764), and a plurality of non-source side data memory cells (705-714, 725-734, 745-754, 765-774) between the source side data memory cell and the drain end; a dummy word line (WLDS1) connected to the dummy memory cells; a plurality of data word lines (WLL0-WLL10) comprising a source side data word line connected to the source side data memory cell and non-source side data word lines (WLL1-WLL10) connected to the non-source side data memory cells; and a control circuit (110, 122), the control circuit configured to apply a voltage at a control gate read level (VvA, VvB, VcC, VrA, VrB, VrC) to a selected data word line among the plurality of data word lines while sensing memory cells connected to the selected data word line and while applying a voltage at a read pass level (Vread pass) to unselected data word lines among the plurality of data word lines; characterised in that the control circuit is further configured to: subsequently ramp down a voltage of the non-source side data word lines to a steady state voltage, followed by, after the ramping down the voltage of the non-source side data word lines to the steady state voltage, ramping down a voltage of the source side data word line and the voltage of the dummy word line to the steady state voltage.