A physically unclonable function circuit comprising: a bit node and a bit bar node; a first inverter and a second inverter that are cross-coupled between the bit node and the bit bar node; a first pre-charge transistor coupled between the bit node and a power supply rail; a second pre-charge transistor coupled between the bit bar node and the power supply rail, the first and second pre-charge transistors to receive a clock signal via respective first and second clock paths characterised by: a first delay chain disposed on the first clock path; a second delay chain disposed on the second clock path; and control circuitry to: pass the clock signal to the first and second pre-charge transistors during a bit generation mode to generate a PUF bit at the bit node with a first value; and write a second value to the bit node during a delay hardening mode, the second value being a logical inverse of the first value to provide a differential delay in the first and second clock paths: wherein, during a bit generation process of the PUF circuit, the first and second pre-charge transistors are turned on and then off, responsive to the clock signal, to generate an output bit, and wherein the PUF circuit is to perform multiple instances of the bit generation process to generate respective output bits, and wherein the PUF circuit further comprises: a counter coupled to the bit node to count a number of times that the PUF circuit generates an output bit of a first logic value over the number of iterations of the bit generation process for which the PUF circuit generates an output bit, wherein a value of the PUF bit associated with the PUF circuit is set to the first logic value if the counted number is above a threshold, and is set to a second logic value if the counted value is below the threshold. a bit node and a bit bar node; a first inverter and a second inverter that are cross-coupled between the bit node and the bit bar node; a first pre-charge transistor coupled between the bit node and a power supply rail; a second pre-charge transistor coupled between the bit bar node and the power supply rail, the first and second pre-charge transistors to receive a clock signal via respective first and second clock paths a first delay chain disposed on the first clock path; a second delay chain disposed on the second clock path; and control circuitry to: pass the clock signal to the first and second pre-charge transistors during a bit generation mode to generate a PUF bit at the bit node with a first value; and write a second value to the bit node during a delay hardening mode, the second value being a logical inverse of the first value to provide a differential delay in the first and second clock paths: wherein, during a bit generation process of the PUF circuit, the first and second pre-charge transistors are turned on and then off, responsive to the clock signal, to generate an output bit, and wherein the PUF circuit is to perform multiple instances of the bit generation process to generate respective output bits, and wherein the PUF circuit further comprises: a counter coupled to the bit node to count a number of times that the PUF circuit generates an output bit of a first logic value over the number of iterations of the bit generation process for which the PUF circuit generates an output bit, wherein a value of the PUF bit associated with the PUF circuit is set to the first logic value if the counted number is above a threshold, and is set to a second logic value if the counted value is below the threshold. pass the clock signal to the first and second pre-charge transistors during a bit generation mode to generate a PUF bit at the bit node with a first value; and write a second value to the bit node during a delay hardening mode, the second value being a logical inverse of the first value to provide a differential delay in the first and second clock paths: wherein, during a bit generation process of the PUF circuit, the first and second pre-charge transistors are turned on and then off, responsive to the clock signal, to generate an output bit, and wherein the PUF circuit is to perform multiple instances of the bit generation process to generate respective output bits, and wherein the PUF circuit further comprises: a counter coupled to the bit node to count a number of times that the PUF circuit generates an output bit of a first logic value over the number of iterations of the bit generation process for which the PUF circuit generates an output bit, wherein a value of the PUF bit associated with the PUF circuit is set to the first logic value if the counted number is above a threshold, and is set to a second logic value if the counted value is below the threshold.