A decoder for receiving a bit line in a flash memory device, comprising: a plurality of receiving blocks, each receiving block (700, 701,..., 707) configured to receive a different bit of data from the bit line, wherein each receiving block comprises an N-LDE1 transistor (601, 611,..., 671) comprising a first terminal and a second terminal, each first terminal of the N-LDE1 transistor in each of the plurality of receiving blocks coupled to the bit line and an N-LDE2 transistor (602, 612,..., 672) comprising a first terminal and a second terminal, each first terminal of the N-LDE2 transistor coupled to the bit line and each second terminal of the N-LDE2 transistor coupled to ground; and an output block coupled to the second terminal of the N-LDE1 transistor in each of the plurality of receiving blocks for generating an output; wherein each N-LDE1 transistor is an NMOS transistor comprising a source with a first shallow trench isolation area width of 0.2-0.3 μm, a drain with a second shallow trench isolation area width of 0.2-0.3 μm, a first gate, a distance between a first edge of the first gate and the closest edge of the first shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the first gate and the closest edge of the second shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE1 transistor was manufactured with a well spacing of 1.0-2.0 μm to its drain and a well spacing of 1.0-2.0 μm to its source; and wherein each N-LDE2 transistor is an NMOS transistor comprising a source with a third shallow trench isolation area width of 0.2-0.3 μm, a drain with a fourth shallow trench isolation area width of 0.2-0.3 μm, a second gate, a distance between a first edge of the second gate and the closest edge of the third shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the second gate and the closest edge of the fourth shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source. a plurality of receiving blocks, each receiving block (700, 701,..., 707) configured to receive a different bit of data from the bit line, wherein each receiving block comprises an N-LDE1 transistor (601, 611,..., 671) comprising a first terminal and a second terminal, each first terminal of the N-LDE1 transistor in each of the plurality of receiving blocks coupled to the bit line and an N-LDE2 transistor (602, 612,..., 672) comprising a first terminal and a second terminal, each first terminal of the N-LDE2 transistor coupled to the bit line and each second terminal of the N-LDE2 transistor coupled to ground; and an output block coupled to the second terminal of the N-LDE1 transistor in each of the plurality of receiving blocks for generating an output; wherein each N-LDE1 transistor is an NMOS transistor comprising a source with a first shallow trench isolation area width of 0.2-0.3 μm, a drain with a second shallow trench isolation area width of 0.2-0.3 μm, a first gate, a distance between a first edge of the first gate and the closest edge of the first shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the first gate and the closest edge of the second shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE1 transistor was manufactured with a well spacing of 1.0-2.0 μm to its drain and a well spacing of 1.0-2.0 μm to its source; and wherein each N-LDE2 transistor is an NMOS transistor comprising a source with a third shallow trench isolation area width of 0.2-0.3 μm, a drain with a fourth shallow trench isolation area width of 0.2-0.3 μm, a second gate, a distance between a first edge of the second gate and the closest edge of the third shallow trench isolation area of 2.0-4.0 μm, and a distance between a second edge of the second gate and the closest edge of the fourth shallow trench isolation area of 2.0-4.0 μm, and wherein each N-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source.