A package structure comprising a semiconductor functional structure (200, 600), wherein the semiconductor functional structure (200, 600) comprises a semiconductor functional layer (201, 601) and an interconnect layer (202, 602), and the top surface of the interconnect layer (202, 602) serves as the top surface of the semiconductor functional structure (200, 600), the package structure further comprising: an isolation layer (203, 603) having N via holes (204, 604), wherein the isolation layer (203, 603) covers a surface of the interconnect layer (202, 602), and the via holes (204, 604) expose parts of the interconnect layer (202, 602); N first pads (205, 605), wherein each of the first pads (205, 605) is formed by the interconnect layer (202, 602) exposed by one of the via holes (204, 604), and N is a positive integer greater than 1; N redistribution layers (206, 606) on the N first pads (205, 605), wherein each of the redistribution layers (206, 606) of the N redistribution layers (206, 606) covers the isolation layer (203, 603) and is electrically connected with a corresponding one of the N first pads (205, 605), some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure (200, 600), other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure (200, 600), the first edge and the second edge are two opposite edges of the semiconductor functional structure (200, 600); a first insulating layer (208, 608) covering the redistribution layers (206, 606) and exposing parts of each of the redistribution layers (206, 606); and second pads (211, 611) and third pads (212, 612), wherein the exposed parts of each of the redistribution layers (206, 606) form a second pad (211, 611) and a third pad (212, 612), both an offset direction and an offset distance between a center point of the second pad (211, 611) and a center point of a corresponding first pad (205, 605) are the same for all the second pads (211, 611), a relative position between the second pad (211, 611) and the third pad (212, 612) for some of the redistribution layers is different from a relative position between the second pad (211, 611) and the third pad (212, 612) for other redistribution layers; the first pads (205, 605) and the second pads (211, 611) are used for testing the semiconductor functional structure (200, 600) at different operating speeds, and the third pads (212, 612) are used for achieving functional interaction corresponding to contents tested by the second pads (211, 611). an isolation layer (203, 603) having N via holes (204, 604), wherein the isolation layer (203, 603) covers a surface of the interconnect layer (202, 602), and the via holes (204, 604) expose parts of the interconnect layer (202, 602); N first pads (205, 605), wherein each of the first pads (205, 605) is formed by the interconnect layer (202, 602) exposed by one of the via holes (204, 604), and N is a positive integer greater than 1; N redistribution layers (206, 606) on the N first pads (205, 605), wherein each of the redistribution layers (206, 606) of the N redistribution layers (206, 606) covers the isolation layer (203, 603) and is electrically connected with a corresponding one of the N first pads (205, 605), some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure (200, 600), other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure (200, 600), the first edge and the second edge are two opposite edges of the semiconductor functional structure (200, 600); a first insulating layer (208, 608) covering the redistribution layers (206, 606) and exposing parts of each of the redistribution layers (206, 606); and second pads (211, 611) and third pads (212, 612), wherein the exposed parts of each of the redistribution layers (206, 606) form a second pad (211, 611) and a third pad (212, 612), both an offset direction and an offset distance between a center point of the second pad (211, 611) and a center point of a corresponding first pad (205, 605) are the same for all the second pads (211, 611), a relative position between the second pad (211, 611) and the third pad (212, 612) for some of the redistribution layers is different from a relative position between the second pad (211, 611) and the third pad (212, 612) for other redistribution layers; the first pads (205, 605) and the second pads (211, 611) are used for testing the semiconductor functional structure (200, 600) at different operating speeds, and the third pads (212, 612) are used for achieving functional interaction corresponding to contents tested by the second pads (211, 611).