A computer-implemented method of performing a lossy synthesis of a fixed-point polynomial with rational coefficients and fabricating an implementation of the fixed-point polynomial with rational coefficients in hardware logic that satisfies a defined error bound, the method comprising: receiving, in a synthesizer module, the polynomial as a data-flow graph comprising one or more nodes, wherein a node is either a sum-of-products operator or a constant division operator; computing, in the synthesizer module, a precision parameter which relates to the precision of the result as represented by the number of bits provided and an accuracy parameter that relates to how close the result is to the correct result for each node in the data-flow graph based on the defined error bound for the polynomial by solving an optimization problem over all nodes; optimizing, in the synthesizer module, a single summation array for each node using a truncation scheme and an error bound for the node, wherein the error bound for the node is calculated using the precision parameter and the accuracy parameter for the node; and outputting, from the synthesizer module, a hardware representation of a binary logic circuit which implements the fixed-point polynomial, wherein the hardware representation is based on an optimized single summation array for each node; wherein the optimization problem is: min ∑ i P i k i subject to: Δ i k i ≤ 2 u i − 1 2 n i for all i e i = u i 2 n i for all i ∑ α λ α e α ≤ η where: P i ( k i) is a function of a number of partial products that remain in a summation array for a node i after truncation, Δ i ( k i) is a maximal value of a truncated section in the summation array for the node i, e i is the error bound for the node, u i is the accuracy parameter for the node i and n i is the precision parameter for the node i, η is the defined error bound for the polynomial, λ α = max x c α x, c α ( x) is a polynomial in x, e α is an error bound associated with a term in the polynomial c α ( x) and α is a vector of integers. receiving, in a synthesizer module, the polynomial as a data-flow graph comprising one or more nodes, wherein a node is either a sum-of-products operator or a constant division operator; computing, in the synthesizer module, a precision parameter which relates to the precision of the result as represented by the number of bits provided and an accuracy parameter that relates to how close the result is to the correct result for each node in the data-flow graph based on the defined error bound for the polynomial by solving an optimization problem over all nodes; optimizing, in the synthesizer module, a single summation array for each node using a truncation scheme and an error bound for the node, wherein the error bound for the node is calculated using the precision parameter and the accuracy parameter for the node; and outputting, from the synthesizer module, a hardware representation of a binary logic circuit which implements the fixed-point polynomial, wherein the hardware representation is based on an optimized single summation array for each node; wherein the optimization problem is: min ∑ i P i k i subject to: Δ i k i ≤ 2 u i − 1 2 n i for all i e i = u i 2 n i for all i ∑ α λ α e α ≤ η where: P i ( k i) is a function of a number of partial products that remain in a summation array for a node i after truncation, Δ i ( k i) is a maximal value of a truncated section in the summation array for the node i, e i is the error bound for the node, u i is the accuracy parameter for the node i and n i is the precision parameter for the node i, η is the defined error bound for the polynomial, λ α = max x c α x, c α ( x) is a polynomial in x, e α is an error bound associated with a term in the polynomial c α ( x) and α is a vector of integers.