A method of controlling a settling time of a switched capacitor circuit, the method is characterized by: configuring a reference capacitance to be proportional to an effective capacitance seen by an amplifier output current of the switched capacitor circuit; adjusting a reference current under closed-loop control to charge the reference capacitance to a defined reference voltage in one cycle time corresponding to an input clock frequency of an input clock signal intended for the switched capacitor circuit by, applying the input clock signal or a conditioned clock signal derived from the input clock signal to a first input of a phase detector and to a first one of one or more variable delay cells, each having a variable delay time defined by the time needed for the reference current to charge the reference capacitance to the reference voltage, applying a delayed clock signal output from a last one of the one or more variable delay cells to a second input of the phase detector, such that an error signal output by the phase detector reflects a cycle time difference between the delayed clock signal and the input clock signal, and adjusting the reference current to minimize the cycle time difference; and configuring the amplifier output current to be generated in proportion to the reference current. configuring a reference capacitance to be proportional to an effective capacitance seen by an amplifier output current of the switched capacitor circuit; adjusting a reference current under closed-loop control to charge the reference capacitance to a defined reference voltage in one cycle time corresponding to an input clock frequency of an input clock signal intended for the switched capacitor circuit by, applying the input clock signal or a conditioned clock signal derived from the input clock signal to a first input of a phase detector and to a first one of one or more variable delay cells, each having a variable delay time defined by the time needed for the reference current to charge the reference capacitance to the reference voltage, applying a delayed clock signal output from a last one of the one or more variable delay cells to a second input of the phase detector, such that an error signal output by the phase detector reflects a cycle time difference between the delayed clock signal and the input clock signal, and adjusting the reference current to minimize the cycle time difference; and applying the input clock signal or a conditioned clock signal derived from the input clock signal to a first input of a phase detector and to a first one of one or more variable delay cells, each having a variable delay time defined by the time needed for the reference current to charge the reference capacitance to the reference voltage, applying a delayed clock signal output from a last one of the one or more variable delay cells to a second input of the phase detector, such that an error signal output by the phase detector reflects a cycle time difference between the delayed clock signal and the input clock signal, and adjusting the reference current to minimize the cycle time difference; and configuring the amplifier output current to be generated in proportion to the reference current.