A system for transmitting data, the system comprising: a transmitter comprising: a plurality of data output circuits, each of the plurality of data output circuits comprising a delay adjust circuit, the plurality of data output circuits being configured to operate at a data rate; and a sampling clock output circuit configured to output a sampling clock signal with a total sampling clock edge rate equal to the data rate, and a plurality of receivers, each of the plurality of receivers connected to a corresponding one of the plurality of data output circuits, each of the plurality of receivers comprising: a sampling clock input connected to the sampling clock output circuit; a data input circuit; and a receiver output, a back channel connected to a receiver of the plurality of receivers, and to the delay adjust circuit of the corresponding data output circuit, the back channel configured to: measure a delay error in the receiver; and adjust a delay in the delay adjust circuit of the corresponding data output circuit, to reduce the delay error, wherein the system is configured to perform a sweep calibration to set the delay in the delay adjust circuit, characterized in that the sweep calibration comprises: sending, by the plurality of data output circuits, a sequence of alternating ones and zeros; operating the receiver in a mode in which every other sampling clock edge is disregarded; changing the delay in the delay adjust circuit in increments in a first direction until both, at a first threshold delay, a first pass-fail or fail-pass boundary is reached, and, at a second threshold delay, a second pass-fail or fail-pass boundary is reached; determining, from the first threshold delay and from the second threshold delay, a range of delays corresponding to a pass region; and setting the delay of the delay adjust circuit to a value that is substantially centered in the pass region. a transmitter comprising: a plurality of data output circuits, each of the plurality of data output circuits comprising a delay adjust circuit, the plurality of data output circuits being configured to operate at a data rate; and a sampling clock output circuit configured to output a sampling clock signal with a total sampling clock edge rate equal to the data rate, and a plurality of data output circuits, each of the plurality of data output circuits comprising a delay adjust circuit, the plurality of data output circuits being configured to operate at a data rate; and a sampling clock output circuit configured to output a sampling clock signal with a total sampling clock edge rate equal to the data rate, and a plurality of receivers, each of the plurality of receivers connected to a corresponding one of the plurality of data output circuits, each of the plurality of receivers comprising: a sampling clock input connected to the sampling clock output circuit; a data input circuit; and a receiver output, a sampling clock input connected to the sampling clock output circuit; a data input circuit; and a receiver output, a back channel connected to a receiver of the plurality of receivers, and to the delay adjust circuit of the corresponding data output circuit, the back channel configured to: measure a delay error in the receiver; and adjust a delay in the delay adjust circuit of the corresponding data output circuit, to reduce the delay error, measure a delay error in the receiver; and adjust a delay in the delay adjust circuit of the corresponding data output circuit, to reduce the delay error, wherein the system is configured to perform a sweep calibration to set the delay in the delay adjust circuit, characterized in that the sweep calibration comprises: sending, by the plurality of data output circuits, a sequence of alternating ones and zeros; operating the receiver in a mode in which every other sampling clock edge is disregarded; changing the delay in the delay adjust circuit in increments in a first direction until both, at a first threshold delay, a first pass-fail or fail-pass boundary is reached, and, at a second threshold delay, a second pass-fail or fail-pass boundary is reached; determining, from the first threshold delay and from the second threshold delay, a range of delays corresponding to a pass region; and setting the delay of the delay adjust circuit to a value that is substantially centered in the pass region. sending, by the plurality of data output circuits, a sequence of alternating ones and zeros; operating the receiver in a mode in which every other sampling clock edge is disregarded; changing the delay in the delay adjust circuit in increments in a first direction until both, at a first threshold delay, a first pass-fail or fail-pass boundary is reached, and, at a second threshold delay, a second pass-fail or fail-pass boundary is reached; determining, from the first threshold delay and from the second threshold delay, a range of delays corresponding to a pass region; and setting the delay of the delay adjust circuit to a value that is substantially centered in the pass region.