A method of a frequency power manager for controlling a power mode of a plurality of modules (130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150) of a physical, PHY, interface of a random access memory, RAM, comprising: receiving an indication of a desired operational frequency; determining to switch from a first power mode of the PHY interface to a second power mode of the PHY interface based on the received indication of the desired operational frequency, the first power mode being associated with a first set of modules of the plurality of modules of the PHY interface, the second power mode being associated with a second set of modules of the plurality of modules of the PHY interface, the second power mode corresponding to the desired operational frequency; enabling modules in the second set of modules that are unassociated with the first power mode; stopping traffic through the plurality of modules (130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150) upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode; routing traffic through the second set of modules; and disabling modules (130, 132, 140) in the first set of modules that are unassociated with the second power mode, wherein the plurality of modules (130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150) includes at least one of a calibrated delay circuit, CDC, an input receiver, a low-dropout, LDO, regulator, a current-to-voltage converter, a phase lock loop, PLL, a bias current generator, or a reference voltage generator, wherein the second power mode associated with said second set of modules is a higher power mode or a lower power mode than the first power mode associated with said first set of modules. receiving an indication of a desired operational frequency; determining to switch from a first power mode of the PHY interface to a second power mode of the PHY interface based on the received indication of the desired operational frequency, the first power mode being associated with a first set of modules of the plurality of modules of the PHY interface, the second power mode being associated with a second set of modules of the plurality of modules of the PHY interface, the second power mode corresponding to the desired operational frequency; enabling modules in the second set of modules that are unassociated with the first power mode; stopping traffic through the plurality of modules (130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150) upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode; routing traffic through the second set of modules; and disabling modules (130, 132, 140) in the first set of modules that are unassociated with the second power mode, wherein the plurality of modules (130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150) includes at least one of a calibrated delay circuit, CDC, an input receiver, a low-dropout, LDO, regulator, a current-to-voltage converter, a phase lock loop, PLL, a bias current generator, or a reference voltage generator, wherein the second power mode associated with said second set of modules is a higher power mode or a lower power mode than the first power mode associated with said first set of modules.