A symmetric LDMOS transistor, comprising: - a semiconductor substrate, - a well of a first type of conductivity in the substrate, - wells of an opposite second type of conductivity in the well of the first type of conductivity, the wells of the second type of conductivity being arranged at a distance from one another, - source/drain regions in the wells of the second type of conductivity, - source/drain contacts are applied to the source/drain regions, - a gate dielectric on the substrate, - a gate electrode on the gate dielectric, - a doped region of the second type of conductivity in the well of the first type of conductivity, the doped region of the second type of conductivity being arranged between the wells of the second type of conductivity at a distance (21, 22) from the wells of the second type of conductivity, and - a gap of the gate electrode above the doped region of the second type of conductivity, the gate electrode overlapping regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity, characterized in that - the gap is the position of a plane of symmetry, - the doped region of the second type of conductivity comprises areas arranged about the plane of symmetry, - a body contact region (14, 14') is connected with the well of the first type of conductivity and arranged at the centre between the areas of the doped region of the second type of conductivity, - a connection between the areas of the doped region is provided by an external connection via a metallization belonging to a wiring or by an interconnecting doped region of the second type of conductivity within the well of the first type of conductivity, and - a body contact is applied to the body contact region (14, 14'). - a semiconductor substrate, - a well of a first type of conductivity in the substrate, - wells of an opposite second type of conductivity in the well of the first type of conductivity, the wells of the second type of conductivity being arranged at a distance from one another, - source/drain regions in the wells of the second type of conductivity, - source/drain contacts are applied to the source/drain regions, - a gate dielectric on the substrate, - a gate electrode on the gate dielectric, - a doped region of the second type of conductivity in the well of the first type of conductivity, the doped region of the second type of conductivity being arranged between the wells of the second type of conductivity at a distance (21, 22) from the wells of the second type of conductivity, and - a gap of the gate electrode above the doped region of the second type of conductivity, the gate electrode overlapping regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity, - the gap is the position of a plane of symmetry, - the doped region of the second type of conductivity comprises areas arranged about the plane of symmetry, - a body contact region (14, 14') is connected with the well of the first type of conductivity and arranged at the centre between the areas of the doped region of the second type of conductivity, - a connection between the areas of the doped region is provided by an external connection via a metallization belonging to a wiring or by an interconnecting doped region of the second type of conductivity within the well of the first type of conductivity, and - a body contact is applied to the body contact region (14, 14').