An apparatus, comprising: an output buffer that holds N words arranged as N/J mutually exclusive output buffer word groups of J words each of the N words, J is greater than 2 and N is at least twice J; an array of N processing units arranged as N/J mutually exclusive PU groups of J PUs each of the N PUs, each PU group of the N/J PU groups has an associated output buffer word group of the N/J output buffer word groups, each PU having: first and second multiplexed registers (208, 705; 3006, 3032) each having: at least J+1 inputs, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input (213; 713; 803) that controls selection of the J+1 inputs for provision on the output; an accumulator having an output for provision to a respective one of the N output buffer words; and an arithmetic unit having first and second inputs to receive the output of the first and second multiplexed registers (208, 705; 3006, 3032), respectively, and a third input that receives the accumulator output, the arithmetic unit performs an operation on the first, second and third inputs to generate a result for accumulation into the accumulator; wherein the output buffer includes a mask input that controls which words, if any, of the N words retain their current value or are updated with their respective accumulator output; and the first multiplexed register (208; 3006) also includes a shifted input that receives the output of the first multiplexed register (208; 3006) of an adjacent PU, the first multiplexed registers (208; 3006) of the N PUs collectively operate as an N-word rotater when the first multiplexed register (208; 3006) control input (213; 713; 803) specifies the shifted input. an output buffer that holds N words arranged as N/J mutually exclusive output buffer word groups of J words each of the N words, J is greater than 2 and N is at least twice J; an array of N processing units arranged as N/J mutually exclusive PU groups of J PUs each of the N PUs, each PU group of the N/J PU groups has an associated output buffer word group of the N/J output buffer word groups, each PU having: first and second multiplexed registers (208, 705; 3006, 3032) each having: at least J+1 inputs, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input (213; 713; 803) that controls selection of the J+1 inputs for provision on the output; an accumulator having an output for provision to a respective one of the N output buffer words; and an arithmetic unit having first and second inputs to receive the output of the first and second multiplexed registers (208, 705; 3006, 3032), respectively, and a third input that receives the accumulator output, the arithmetic unit performs an operation on the first, second and third inputs to generate a result for accumulation into the accumulator; wherein first and second multiplexed registers (208, 705; 3006, 3032) each having: at least J+1 inputs, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input (213; 713; 803) that controls selection of the J+1 inputs for provision on the output; at least J+1 inputs, a first input of the J+1 inputs receives an operand from a memory and the other J inputs receive the J words of the associated output buffer word group; an output; and a control input (213; 713; 803) that controls selection of the J+1 inputs for provision on the output; an accumulator having an output for provision to a respective one of the N output buffer words; and an arithmetic unit having first and second inputs to receive the output of the first and second multiplexed registers (208, 705; 3006, 3032), respectively, and a third input that receives the accumulator output, the arithmetic unit performs an operation on the first, second and third inputs to generate a result for accumulation into the accumulator; wherein the output buffer includes a mask input that controls which words, if any, of the N words retain their current value or are updated with their respective accumulator output; and the first multiplexed register (208; 3006) also includes a shifted input that receives the output of the first multiplexed register (208; 3006) of an adjacent PU, the first multiplexed registers (208; 3006) of the N PUs collectively operate as an N-word rotater when the first multiplexed register (208; 3006) control input (213; 713; 803) specifies the shifted input.