An in-memory mixed-signal computing cell, comprising: a plurality of computing sub-cells, each configured to perform 1-bit multiplication and comprising a corresponding memory element; a computing capacitor; and a control element, wherein the control element and the computing capacitor are shared among the plurality of computing sub-cells; wherein each memory element comprises corresponding two cross-coupled CMOS inverters and a corresponding complementary transmission gate; the corresponding two cross-coupled CMOS inverters storing a corresponding 1-bit filter parameter; the corresponding complementary transmission gate comprising a corresponding NMOS transistor having a gate connected to a corresponding input signal; the corresponding complementary transmission gate further comprising a corresponding PMOS transistor having a gate connected to a corresponding complementary input signal; one of the corresponding CMOS inverters comprising an output connected to an input of the corresponding complementary transmission gate; the corresponding complementary transmission gate comprising an output connected to both a bottom plate of the computing capacitor and the control element wherein the computing cell is such that, for each computing sub-cell when activated, a multiplication result of the corresponding input signal and the corresponding filter parameter is stored as a voltage on the bottom plate of the computing capacitor; and wherein the control element comprises a first NMOS transistor, a second NMOS transistor and a PMOS transistor; the first NMOS transistor having a source that is grounded, and a drain connected together with a drain of the second NMOS transistor and a drain of the PMOS transistor to the bottom plate of the shared computing capacitor; the first NMOS transistor having a gate, the computing cell being such that, the gate of the first NMOS transistor is at a same voltage level during computation of an activated computing sub-cell as a signal to which the gate of the PMOS transistor in the complementary transmission gate of the activated computing sub-cell is connected; the second NMOS transistor having a source that is grounded, and a gate connectable to a bit line; the PMOS transistor having a source connected to Vdd, and a gate connectable to a further complementary bit line. a plurality of computing sub-cells, each configured to perform 1-bit multiplication and comprising a corresponding memory element; a computing capacitor; and a control element, wherein the control element and the computing capacitor are shared among the plurality of computing sub-cells; wherein each memory element comprises corresponding two cross-coupled CMOS inverters and a corresponding complementary transmission gate; the corresponding two cross-coupled CMOS inverters storing a corresponding 1-bit filter parameter; the corresponding complementary transmission gate comprising a corresponding NMOS transistor having a gate connected to a corresponding input signal; the corresponding complementary transmission gate further comprising a corresponding PMOS transistor having a gate connected to a corresponding complementary input signal; one of the corresponding CMOS inverters comprising an output connected to an input of the corresponding complementary transmission gate; the corresponding complementary transmission gate comprising an output connected to both a bottom plate of the computing capacitor and the control element wherein the computing cell is such that, for each computing sub-cell when activated, a multiplication result of the corresponding input signal and the corresponding filter parameter is stored as a voltage on the bottom plate of the computing capacitor; and wherein the control element comprises a first NMOS transistor, a second NMOS transistor and a PMOS transistor; the first NMOS transistor having a source that is grounded, and a drain connected together with a drain of the second NMOS transistor and a drain of the PMOS transistor to the bottom plate of the shared computing capacitor; the first NMOS transistor having a gate, the computing cell being such that, the gate of the first NMOS transistor is at a same voltage level during computation of an activated computing sub-cell as a signal to which the gate of the PMOS transistor in the complementary transmission gate of the activated computing sub-cell is connected; the second NMOS transistor having a source that is grounded, and a gate connectable to a bit line; the PMOS transistor having a source connected to Vdd, and a gate connectable to a further complementary bit line.