A system of reducing power consumption in a portable electronic device, the system comprising: a memory; a processor coupled to the memory; a kernel stored in the memory and configured to execute on the processor, the kernel being configured to maintain a switching regulator of a power management integrated circuit, PMIC, in a low power state and a linear regulator of the PMIC in an off state while the system is in a low power mode, wherein the switching regulator is configured to provide power to the processor and wherein the kernel is configured to enter the low power mode by performing the following acts: freeze a running user-space process and kernel thread executing on the processor; configure a wakeup source to generate a wakeup interrupt; gate a clock which is defined in a clock gating register coupled to the processor; place into the off state the linear regulator; place into the low power state the switching regulator; gate a serial peripheral interface clock or a universal serial bus clock or both which are coupled to the processor; set a state retention mode for the processor in a clock control module which is coupled to the processor; disable interrupt generation from a non-wakeup source; disable processor scaling on the processor; and gate a main clock of the processor. a memory; a processor coupled to the memory; a kernel stored in the memory and configured to execute on the processor, the kernel being configured to maintain a switching regulator of a power management integrated circuit, PMIC, in a low power state and a linear regulator of the PMIC in an off state while the system is in a low power mode, wherein the switching regulator is configured to provide power to the processor and wherein the kernel is configured to enter the low power mode by performing the following acts: freeze a running user-space process and kernel thread executing on the processor; configure a wakeup source to generate a wakeup interrupt; gate a clock which is defined in a clock gating register coupled to the processor; place into the off state the linear regulator; place into the low power state the switching regulator; gate a serial peripheral interface clock or a universal serial bus clock or both which are coupled to the processor; set a state retention mode for the processor in a clock control module which is coupled to the processor; disable interrupt generation from a non-wakeup source; disable processor scaling on the processor; and gate a main clock of the processor. freeze a running user-space process and kernel thread executing on the processor; configure a wakeup source to generate a wakeup interrupt; gate a clock which is defined in a clock gating register coupled to the processor; place into the off state the linear regulator; place into the low power state the switching regulator; gate a serial peripheral interface clock or a universal serial bus clock or both which are coupled to the processor; set a state retention mode for the processor in a clock control module which is coupled to the processor; disable interrupt generation from a non-wakeup source; disable processor scaling on the processor; and gate a main clock of the processor.