A method of operating a time-interleaved analog-to-digital converter (221,222,223,321,322,323) for conversion of an analog input signal to a digital output signal having a variable sample rate R, wherein the time-interleaved analog-to-digital converter comprises: an array of an integer number N of constituent analog-to-digital converters each having an analog input and a digital output, wherein each constituent analog-to-digital converter is adapted to operate based on an analog-to-digital converter operational clock with fixed clock frequency which is not constrained by the variable sampling rate R, and to digitize an analog signal sample during a constituent analog-to-digital converter latency T; an integer number N of sample-and-hold units, (211,212,213,311,312,313) each sample-and-hold unit connected to the analog input of a respective one of the N of constituent analog-to-digital converters; and a timing circuit for generating: the analog-to-digital converter operation clock signal; and an integer number M of timing signals (265,365) each timing signal having a period of M/R, wherein M is less or equal to N, and wherein M/R is larger than or equal to T; the method comprising, for each of a number M of the N constituent analog-to-digital converters, wherein each of the M constituent analog-to-digital converters is associated with a corresponding sample-and-hold unit: clocking the corresponding sample-and-hold unit with a respective one of the M timing signals to provide a sample of the analog input signal at the analog input of the constituent analog-to-digital converter, wherein no timing signal is used to clock two or more of the sample-and-hold units; operating the constituent analog-to-digital converter based on the analog-to-digital converter operation clock to provide a digital signal at the digital output of the constituent analog-to-digital converter; and providing (180, 190) a sample of the digital signal of the digital output of the constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals by aligning the sample with the respective one of the M timing signals. an array of an integer number N of constituent analog-to-digital converters each having an analog input and a digital output, wherein each constituent analog-to-digital converter is adapted to operate based on an analog-to-digital converter operational clock with fixed clock frequency which is not constrained by the variable sampling rate R, and to digitize an analog signal sample during a constituent analog-to-digital converter latency T; an integer number N of sample-and-hold units, (211,212,213,311,312,313) each sample-and-hold unit connected to the analog input of a respective one of the N of constituent analog-to-digital converters; and a timing circuit for generating: the analog-to-digital converter operation clock signal; and an integer number M of timing signals (265,365) each timing signal having a period of M/R, wherein M is less or equal to N, and wherein M/R is larger than or equal to T; the analog-to-digital converter operation clock signal; and an integer number M of timing signals (265,365) each timing signal having a period of M/R, wherein M is less or equal to N, and wherein M/R is larger than or equal to T; the method comprising, for each of a number M of the N constituent analog-to-digital converters, wherein each of the M constituent analog-to-digital converters is associated with a corresponding sample-and-hold unit: clocking the corresponding sample-and-hold unit with a respective one of the M timing signals to provide a sample of the analog input signal at the analog input of the constituent analog-to-digital converter, wherein no timing signal is used to clock two or more of the sample-and-hold units; operating the constituent analog-to-digital converter based on the analog-to-digital converter operation clock to provide a digital signal at the digital output of the constituent analog-to-digital converter; and providing (180, 190) a sample of the digital signal of the digital output of the constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals by aligning the sample with the respective one of the M timing signals. clocking the corresponding sample-and-hold unit with a respective one of the M timing signals to provide a sample of the analog input signal at the analog input of the constituent analog-to-digital converter, wherein no timing signal is used to clock two or more of the sample-and-hold units; operating the constituent analog-to-digital converter based on the analog-to-digital converter operation clock to provide a digital signal at the digital output of the constituent analog-to-digital converter; and providing (180, 190) a sample of the digital signal of the digital output of the constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals by aligning the sample with the respective one of the M timing signals.