A method for forming a gate stack of a non-volatile memory, NVM, over a semiconductor substrate having an NVM region and a non-NVM region which does not overlap the NVM region, the method comprising: forming a select gate layer over the substrate in the NVM region and the non-NVM region; simultaneously etching the select gate layer in the NVM region and the select gate layer in the non-NVM region, wherein the etching the select gate layer in the NVM region results in a first portion of the select gate layer remaining in the NVM region; forming a charge storage layer over the substrate in the NVM region and the non-NVM region, wherein the charge storage layer is formed over the first portion of the select gate layer; forming a control gate layer over the charge storage layer in the NVM region and the non-NVM region; simultaneously etching the control gate layer in the NVM region and the non-NVM region; simultaneously etching the charge storage layer in the NVM region and the non-NVM region, wherein the etching the control gate layer and the charge storage layer in the NVM region results in: only a portion of the charge storage layer remaining over the first portion of the select gate layer; the charge storage layer overlapping a sidewall of the first portion of the select gate layer; and only a portion of the control gate layer remaining over the portion of the charge storage layer; and forming a split gate device using the first portion of the select gate layer, the portion of the charge storage layer, and the portion of the control gate layer. forming a select gate layer over the substrate in the NVM region and the non-NVM region; simultaneously etching the select gate layer in the NVM region and the select gate layer in the non-NVM region, wherein the etching the select gate layer in the NVM region results in a first portion of the select gate layer remaining in the NVM region; forming a charge storage layer over the substrate in the NVM region and the non-NVM region, wherein the charge storage layer is formed over the first portion of the select gate layer; forming a control gate layer over the charge storage layer in the NVM region and the non-NVM region; simultaneously etching the control gate layer in the NVM region and the non-NVM region; simultaneously etching the charge storage layer in the NVM region and the non-NVM region, wherein the etching the control gate layer and the charge storage layer in the NVM region results in: only a portion of the charge storage layer remaining over the first portion of the select gate layer; the charge storage layer overlapping a sidewall of the first portion of the select gate layer; and only a portion of the control gate layer remaining over the portion of the charge storage layer; and only a portion of the charge storage layer remaining over the first portion of the select gate layer; the charge storage layer overlapping a sidewall of the first portion of the select gate layer; and only a portion of the control gate layer remaining over the portion of the charge storage layer; and forming a split gate device using the first portion of the select gate layer, the portion of the charge storage layer, and the portion of the control gate layer.