A phase adjusting circuit, comprising a detection module, a comparison module, a counting module, and an adjustment module that are connected in sequence; wherein, the detection module is configured to detect a phase difference between a rising edge of a first clock signal (CLKOI) and a rising edge of a second clock signal (CLKOQ) to obtain a first detection signal (Detection_clkoi_q) and a phase difference between a rising edge of the second clock signal (CLKOQ) and a falling edge of the first clock signal (CLKOI) to obtain a second detection signal (Detection_clkoi_ib); the comparison module is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal; the counting module is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value; and the adjustment module is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference between the first clock signal and the second clock signal is a preset value; wherein the phase adjusting circuit is configured to be applied to a memory, and the comparison module comprises a duty cycle unit, a preprocessing unit, and a sampling unit; wherein, the duty cycle unit is configured to receive the first detection signal and the second detection signal, and perform duty cycle comparison of the first detection signal and the second detection signal to obtain a comparison result signal; wherein the comparison result signal is in a first level state in response to a duty cycle of the first detection signal being higher than a duty cycle of the second detection signal, or the comparison result signal is in a second level state in response to a duty cycle of the first detection signal being lower than a duty cycle of the second detection signal; the preprocessing unit is configured to receive a main clock signal of the memory, and perform frequency division of the main clock signal to obtain a sampling clock signal; and the sampling unit is configured to receive the sampling clock signal and the comparison result signal, and perform sampling of the comparison result signal based on the sampling clock signal to obtain the counting indication signal. the detection module is configured to detect a phase difference between a rising edge of a first clock signal (CLKOI) and a rising edge of a second clock signal (CLKOQ) to obtain a first detection signal (Detection_clkoi_q) and a phase difference between a rising edge of the second clock signal (CLKOQ) and a falling edge of the first clock signal (CLKOI) to obtain a second detection signal (Detection_clkoi_ib); the comparison module is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal; the counting module is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value; and the adjustment module is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference between the first clock signal and the second clock signal is a preset value; wherein the phase adjusting circuit is configured to be applied to a memory, and the comparison module comprises a duty cycle unit, a preprocessing unit, and a sampling unit; wherein, the duty cycle unit is configured to receive the first detection signal and the second detection signal, and perform duty cycle comparison of the first detection signal and the second detection signal to obtain a comparison result signal; wherein the comparison result signal is in a first level state in response to a duty cycle of the first detection signal being higher than a duty cycle of the second detection signal, or the comparison result signal is in a second level state in response to a duty cycle of the first detection signal being lower than a duty cycle of the second detection signal; the preprocessing unit is configured to receive a main clock signal of the memory, and perform frequency division of the main clock signal to obtain a sampling clock signal; and the sampling unit is configured to receive the sampling clock signal and the comparison result signal, and perform sampling of the comparison result signal based on the sampling clock signal to obtain the counting indication signal.