A scan driving circuit comprising a multi-stage shift register unit configured to output scan signals by its stages under control of a clock signal comprising a first clock signal supplied via a first clock signal line and a second clock signal (CKBR) supplied via a second clock signal line, wherein the first clock signal and the second clock signal have opposite phases, wherein the shift register unit includes output terminals for outputting the scan signals, wherein the scan driving circuit further comprises a multi-stage signal generating unit, wherein an n-th stage signal generating unit of the multi-stage signal generating unit has first and second input terminals connected respectively to an output terminal of an n-th stage shift register unit of the multi-stage shift register unit and an output terminal of an (n+j)-th stage shift register unit of the multi-stage shift register unit, wherein the n-th stage signal generating unit has an output terminal configured to output a first voltage level or a second voltage level, and is configured to convert a voltage level outputted by its output terminal from the first voltage level into the second voltage level under triggering of a scan signal outputted by the n-th stage shift register unit, and to convert the voltage level outputted by its output terminal from the second voltage level into the first voltage level under triggering of a scan signal outputted by the (n+j)-th stage shift register unit; wherein the n and j both are positive integers, wherein: the n-th stage signal generating unit comprises: a first switching element (Ta) with a control terminal thereof being connected to the second clock signal line, and a first terminal thereof being connected to the output terminal of the n-th stage shift register unit, a second switching element (Tb) with a control terminal thereof being connected to a second terminal of the first switching element, and a first terminal thereof being connected to a high level voltage line for supplying the first voltage level; a third switching element (Tc) with a control terminal thereof being connected to the output terminal of the (n+j)-th stage shift register unit, a first terminal thereof being connected to a second terminal of the second switching element, and a second terminal thereof being connected to a low level voltage line for supplying the second voltage level; a fourth switching element (Td) with a control terminal thereof being connected to the second terminal of the second switching element, and a second terminal thereof being connected to the low level voltage line; a fifth switching element (Te) with a control terminal thereof being connected to the second terminal of the first switching element, a first terminal thereof being connected to the high level voltage line, and a second terminal thereof being connected to a first terminal of the fourth switching element; a first capacitor (Ca) with a first terminal thereof being connected to the high level voltage line, and a second terminal thereof being connected to the second terminal of the first switching element; a second capacitor (Cb) with a first terminal thereof being connected to the second terminal of the fifth switching element, and a second terminal thereof being connected to the second terminal of the second switching element; the output terminal being connected to the second terminal of the fifth switching element. a first switching element (Ta) with a control terminal thereof being connected to the second clock signal line, and a first terminal thereof being connected to the output terminal of the n-th stage shift register unit, a second switching element (Tb) with a control terminal thereof being connected to a second terminal of the first switching element, and a first terminal thereof being connected to a high level voltage line for supplying the first voltage level; a third switching element (Tc) with a control terminal thereof being connected to the output terminal of the (n+j)-th stage shift register unit, a first terminal thereof being connected to a second terminal of the second switching element, and a second terminal thereof being connected to a low level voltage line for supplying the second voltage level; a fourth switching element (Td) with a control terminal thereof being connected to the second terminal of the second switching element, and a second terminal thereof being connected to the low level voltage line; a fifth switching element (Te) with a control terminal thereof being connected to the second terminal of the first switching element, a first terminal thereof being connected to the high level voltage line, and a second terminal thereof being connected to a first terminal of the fourth switching element; a first capacitor (Ca) with a first terminal thereof being connected to the high level voltage line, and a second terminal thereof being connected to the second terminal of the first switching element; a second capacitor (Cb) with a first terminal thereof being connected to the second terminal of the fifth switching element, and a second terminal thereof being connected to the second terminal of the second switching element; the output terminal being connected to the second terminal of the fifth switching element.