A gate driving circuit (130; 140) comprising: a plurality of stages (STG1,..., STG(n+1)) each stage comprising: a gate line; a pull-up transistor outputting a gate driving signal for driving the gate line; a capacitor (210, C1) formed with a dielectric substance disposed between a first electrode connected to a gate electrode of the pull-up transistor and a second electrode connected to a drain electrode of the pull-up transistor; a holding transistor connected to the pull-up transistor to maintain a voltage level of the gate driving signal; a switching transistor connected to the pull-up transistor and the capacitor (210, C1) to control the holding transistor through the gate driving signal; and a second connecting electrode connecting the second electrode to a contact portion, the contact portion connected to a gate electrode of the switching transistor; characterized in that each stage comprises a gate pad formed at one end of the gate line and a first connecting electrode connecting the gate pad to the second electrode, wherein the second electrode is larger than the first electrode for forming a contact region for the first connecting electrode and for the second connecting electrode; the first electrode of the capacitor (210, C1), the gate pad and the contact portion are disposed on an insulating substrate layer; an insulating layer is disposed on the substrate covering the first electrode, the gate pad and the contact portion, wherein the insulating layer comprises contact holes (242; 243; 244; 245; 246) for contacting at least the first electrode, the gate pad and the contact portion; and the second electrode is disposed on the insulating layer; wherein the gate driving circuit (130; 140) further comprises a signal supply line that connects the contact portion to the gate electrode of the switching transistor, wherein the contact portion is spaced apart from the gate pad by a predetermined distance; wherein the dielectric substance is formed by the insulating layer insulating the gate line, and by an amorphous silicon layer. a plurality of stages (STG1,..., STG(n+1)) each stage comprising: a gate line; a pull-up transistor outputting a gate driving signal for driving the gate line; a capacitor (210, C1) formed with a dielectric substance disposed between a first electrode connected to a gate electrode of the pull-up transistor and a second electrode connected to a drain electrode of the pull-up transistor; a holding transistor connected to the pull-up transistor to maintain a voltage level of the gate driving signal; a switching transistor connected to the pull-up transistor and the capacitor (210, C1) to control the holding transistor through the gate driving signal; and a gate line; a pull-up transistor outputting a gate driving signal for driving the gate line; a capacitor (210, C1) formed with a dielectric substance disposed between a first electrode connected to a gate electrode of the pull-up transistor and a second electrode connected to a drain electrode of the pull-up transistor; a holding transistor connected to the pull-up transistor to maintain a voltage level of the gate driving signal; a switching transistor connected to the pull-up transistor and the capacitor (210, C1) to control the holding transistor through the gate driving signal; and a second connecting electrode connecting the second electrode to a contact portion, the contact portion connected to a gate electrode of the switching transistor; characterized in that each stage comprises a gate pad formed at one end of the gate line and a first connecting electrode connecting the gate pad to the second electrode, wherein the second electrode is larger than the first electrode for forming a contact region for the first connecting electrode and for the second connecting electrode; the first electrode of the capacitor (210, C1), the gate pad and the contact portion are disposed on an insulating substrate layer; an insulating layer is disposed on the substrate covering the first electrode, the gate pad and the contact portion, wherein the insulating layer comprises contact holes (242; 243; 244; 245; 246) for contacting at least the first electrode, the gate pad and the contact portion; and the second electrode is disposed on the insulating layer;