A memory module comprising: a substrate having signal traces thereon; and a plurality of multi-die memory devices disposed on the substrate and coupled to the signal traces, each of the multi-die memory devices including: a first integrated circuit die having a synchronous interface to receive memory access commands synchronously with respect to a clock signal via the signal traces on the substrate, the memory module characterized by for each of the multi-die memory devices, the first integrated circuit die has a plurality of clockless memory control interfaces to output row and column control signals unaccompanied by a synchronizing timing reference signal; and each of the multi-die memory devices includes further a second integrated circuit die having a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including a data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission effected by a sequence of demand signals received by the first integrated circuit die, a sampling signal able to trigger sampling operations within a data receiver within the first integrated circuit die to sample the read data. a substrate having signal traces thereon; and a plurality of multi-die memory devices disposed on the substrate and coupled to the signal traces, each of the multi-die memory devices including: a first integrated circuit die having a synchronous interface to receive memory access commands synchronously with respect to a clock signal via the signal traces on the substrate, the memory module characterized by for each of the multi-die memory devices, the first integrated circuit die has a plurality of clockless memory control interfaces to output row and column control signals unaccompanied by a synchronizing timing reference signal; and each of the multi-die memory devices includes further a second integrated circuit die having a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including a data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission effected by a sequence of demand signals received by the first integrated circuit die, a sampling signal able to trigger sampling operations within a data receiver within the first integrated circuit die to sample the read data. a first integrated circuit die having a synchronous interface to receive memory access commands synchronously with respect to a clock signal via the signal traces on the substrate, the memory module characterized by for each of the multi-die memory devices, the first integrated circuit die has a plurality of clockless memory control interfaces to output row and column control signals unaccompanied by a synchronizing timing reference signal; and each of the multi-die memory devices includes further a second integrated circuit die having a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including a data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission effected by a sequence of demand signals received by the first integrated circuit die, a sampling signal able to trigger sampling operations within a data receiver within the first integrated circuit die to sample the read data.