A power switch controller (204, 304, 404, 504) for driving a back-to-back power switch that has a gate terminal, a source terminal, a first terminal, and a second terminal, the power switch controller (204, 304, 404, 504) comprising: an amplifier having a supply terminal configured to receive a supply voltage (Vcc), an output configured to be coupled to the gate terminal of the back-to-back power switch, a first input configured to be coupled the source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier, wherein the amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier, characterized in that the amplifier comprises: a second supply terminal configured to receive a second supply voltage (V DD, GND) lower than the supply voltage (Vcc); a first transistor having a current path coupled to the second supply terminal; a current mirror coupled to the supply terminal; a second transistor having a gate coupled to the first input of the amplifier, and a current path coupled between the current path of the first transistor and the current mirror; and a third transistor having a gate coupled to the second input of the amplifier, and a current path coupled between the current path of the first transistor and the current mirror,the power switch controller (304, 404, 504) further comprising a fourth transistor having a current path coupled to the supply terminal, the current path of the fourth transistor configured to be coupled to the gate terminal of the back-to-back power switch,the power switch controller (304, 404, 504) further comprising: a current generator (307, 507) configured to generate a reference current (I REF1, I REF4); and an offset generator (315, 515) configured to generate the offset voltage (V REF) based on the reference current (I REF1, I REF4). an amplifier having a supply terminal configured to receive a supply voltage (Vcc), an output configured to be coupled to the gate terminal of the back-to-back power switch, a first input configured to be coupled the source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier, wherein the amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier, characterized in that the amplifier comprises: a second supply terminal configured to receive a second supply voltage (V DD, GND) lower than the supply voltage (Vcc); a first transistor having a current path coupled to the second supply terminal; a current mirror coupled to the supply terminal; a second transistor having a gate coupled to the first input of the amplifier, and a current path coupled between the current path of the first transistor and the current mirror; and a third transistor having a gate coupled to the second input of the amplifier, and a current path coupled between the current path of the first transistor and the current mirror,the power switch controller (304, 404, 504) further comprising a fourth transistor having a current path coupled to the supply terminal, the current path of the fourth transistor configured to be coupled to the gate terminal of the back-to-back power switch,the power switch controller (304, 404, 504) further comprising: a current generator (307, 507) configured to generate a reference current (I REF1, I REF4); and an offset generator (315, 515) configured to generate the offset voltage (V REF) based on the reference current (I REF1, I REF4). a second supply terminal configured to receive a second supply voltage (V DD, GND) lower than the supply voltage (Vcc); a first transistor having a current path coupled to the second supply terminal; a current mirror coupled to the supply terminal; a second transistor having a gate coupled to the first input of the amplifier, and a current path coupled between the current path of the first transistor and the current mirror; and a third transistor having a gate coupled to the second input of the amplifier, and a current path coupled between the current path of the first transistor and the current mirror,the power switch controller (304, 404, 504) further comprising a fourth transistor having a current path coupled to the supply terminal, the current path of the fourth transistor configured to be coupled to the gate terminal of the back-to-back power switch,the power switch controller (304, 404, 504) further comprising: a current generator (307, 507) configured to generate a reference current (I REF1, I REF4); and an offset generator (315, 515) configured to generate the offset voltage (V REF) based on the reference current (I REF1, I REF4). a current generator (307, 507) configured to generate a reference current (I REF1, I REF4); and an offset generator (315, 515) configured to generate the offset voltage (V REF) based on the reference current (I REF1, I REF4).