A digital class D amplifier comprising a pulse width modulator (PW_Mod) comprising: - a digital loop filter (Loop_F) having a first input adapted to receive an input signal (x[n]) and a second input adapted to receive a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process, at a clock frequency (f_s), the input and feedback signals for providing as output a filtered digital signal (w[n]); - a PWM conversion module (PW_CM) having an input for receiving the filtered digital signal (w[n]) and having a first output connected to the second input of the digital loop filter (Loop_F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output the feedback signal (fb[n]), said PWM conversion module (PW_CM) comprising a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), said first reference triangular waveform (VTn[n]) having a frequency (f_osc) lower than said clock frequency (f_s); characterized in that the PWM conversion module (PW_CM) comprises: - a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing in their combination a differential output pulse width modulated signal (yn[n],yp[n]); and - an algebraic adder having a first input coupled to an output of the first comparator (CMP_N) and a second input coupled to an output of the second comparator (CMP_P), the algebraic adder adapted to combine said first and said second PWM signals for providing as output said feedback signal (fb[n]). - a digital loop filter (Loop_F) having a first input adapted to receive an input signal (x[n]) and a second input adapted to receive a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process, at a clock frequency (f_s), the input and feedback signals for providing as output a filtered digital signal (w[n]); - a PWM conversion module (PW_CM) having an input for receiving the filtered digital signal (w[n]) and having a first output connected to the second input of the digital loop filter (Loop_F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output the feedback signal (fb[n]), said PWM conversion module (PW_CM) comprising a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), said first reference triangular waveform (VTn[n]) having a frequency (f_osc) lower than said clock frequency (f_s); - a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing in their combination a differential output pulse width modulated signal (yn[n],yp[n]); and - an algebraic adder having a first input coupled to an output of the first comparator (CMP_N) and a second input coupled to an output of the second comparator (CMP_P), the algebraic adder adapted to combine said first and said second PWM signals for providing as output said feedback signal (fb[n]).