A reduced switch-on slew low dropout, LDO, regulator comprising: a pass gate controllably coupling, in response to a pass gate control signal, Vhg, a voltage rail, Vdd, to a regulator output, Vout; a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage, Vref, and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state; a pass gate disabling circuit configured to selectively over-ride the pass gate control signal and switch the pass gate OFF, wherein the controllable slew differential amplifier includes a switchable tail current source that is switchable between sourcing a slew-limiting bias current, I_SB, and sourcing a full-slew bias current, I_ON, and is configured to generate the pass gate control signal at the full-slew rate with the full-slew bias current, and at the reduced slew rate with the slew-limiting bias current; and characterized by: a tail current control circuit (256, 260, M20, C2) configured to switch (M20, 256) the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal, ST_ON/OFF and, at a delay DLY after an OFF-to-ON transition of the ST_ON/OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current, wherein the tail current control circuit includes a delay capacitor, and a charging circuit configured to charge the delay capacitor, in response to the OFF-to-ON transition of the ST_ON/OFF, from a zero voltage to a tail current source mode switch threshold, in a charging time having a duration approximately equal to the DLY. a pass gate controllably coupling, in response to a pass gate control signal, Vhg, a voltage rail, Vdd, to a regulator output, Vout; a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage, Vref, and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state; a pass gate disabling circuit configured to selectively over-ride the pass gate control signal and switch the pass gate OFF, wherein the controllable slew differential amplifier includes a switchable tail current source that is switchable between sourcing a slew-limiting bias current, I_SB, and sourcing a full-slew bias current, I_ON, and is configured to generate the pass gate control signal at the full-slew rate with the full-slew bias current, and at the reduced slew rate with the slew-limiting bias current; and characterized by: a tail current control circuit (256, 260, M20, C2) configured to switch (M20, 256) the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal, ST_ON/OFF and, at a delay DLY after an OFF-to-ON transition of the ST_ON/OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current, wherein the tail current control circuit includes a delay capacitor, and a charging circuit configured to charge the delay capacitor, in response to the OFF-to-ON transition of the ST_ON/OFF, from a zero voltage to a tail current source mode switch threshold, in a charging time having a duration approximately equal to the DLY. a tail current control circuit (256, 260, M20, C2) configured to switch (M20, 256) the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal, ST_ON/OFF and, at a delay DLY after an OFF-to-ON transition of the ST_ON/OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current, wherein the tail current control circuit includes a delay capacitor, and a charging circuit configured to charge the delay capacitor, in response to the OFF-to-ON transition of the ST_ON/OFF, from a zero voltage to a tail current source mode switch threshold, in a charging time having a duration approximately equal to the DLY.