A semiconductor device including a single-ended type analog to digital conversion circuit, comprising: a comparator which switches a logic level of an output signal based on a relative size relationship between voltage levels to be inputted to two input terminals; a first comparison wiring (Wp) coupled with one terminal of the comparator; a second comparison wiring (Wn) coupled with the other terminal of the comparator; an input wiring (Win)to which an input signal is transmitted; a plurality of first capacitors (30;....;36) each one end of which is coupled with the first comparison wiring (Wp), which sample input signals when starting conversion processing, and each of which has a capacitance value corresponding to a weight of a bit to be converted; and a plurality of second capacitors (37;...;39) each one end of which is coupled with the second comparison wiring (Wn) and the sum of whose capacitance values is equivalent to the sum of the capacitance values of the first capacitors, characterized in that the second capacitors include: a redundant bit capacitor having one end coupled with the second comparison wiring and having a capacitance value corresponding to a weight of a redundant bit, and an adjustment capacitor (37;38) having a capacitance value obtained by subtracting capacitance value of the redundant bit capacitor from the sum of the capacitance values of the first capacitors, and a switch for applying a high-potential side reference voltage (VREFP) or a low-potential side reference voltage (VREFN) to the other end of the redundant bit capacitor based on a preceding comparison operation result. a comparator which switches a logic level of an output signal based on a relative size relationship between voltage levels to be inputted to two input terminals; a first comparison wiring (Wp) coupled with one terminal of the comparator; a second comparison wiring (Wn) coupled with the other terminal of the comparator; an input wiring (Win)to which an input signal is transmitted; a plurality of first capacitors (30;....;36) each one end of which is coupled with the first comparison wiring (Wp), which sample input signals when starting conversion processing, and each of which has a capacitance value corresponding to a weight of a bit to be converted; and a plurality of second capacitors (37;...;39) each one end of which is coupled with the second comparison wiring (Wn) and the sum of whose capacitance values is equivalent to the sum of the capacitance values of the first capacitors, characterized in that the second capacitors include: a redundant bit capacitor having one end coupled with the second comparison wiring and having a capacitance value corresponding to a weight of a redundant bit, and an adjustment capacitor (37;38) having a capacitance value obtained by subtracting capacitance value of the redundant bit capacitor from the sum of the capacitance values of the first capacitors, and a switch for applying a high-potential side reference voltage (VREFP) or a low-potential side reference voltage (VREFN) to the other end of the redundant bit capacitor based on a preceding comparison operation result. a redundant bit capacitor having one end coupled with the second comparison wiring and having a capacitance value corresponding to a weight of a redundant bit, and an adjustment capacitor (37;38) having a capacitance value obtained by subtracting capacitance value of the redundant bit capacitor from the sum of the capacitance values of the first capacitors, and a switch for applying a high-potential side reference voltage (VREFP) or a low-potential side reference voltage (VREFN) to the other end of the redundant bit capacitor based on a preceding comparison operation result.