A high frequency semiconductor amplifier comprising: a Si substrate having a first region and a second region, the first region and the second region being provided on a continuous Si plate, or separate Si plates, an input circuit provided on the first region of the Si substrate and including a first DC blocking capacitor, an input transmission line, a first input pad part and a first bias circuit, the input transmission line having a first region and a second region spaced from each other, the first DC blocking capacitor being connected between the first region and the second region of the input transmission line, the first input pad part, being connected to the second region of the input transmission line, the first bias circuit including a first grounded capacitor and a first transmission line, the first transmission line having one end portion connected to the first grounded capacitor and another end portion connected to the second region of the input transmission line; an output circuit (30,70) provided on the second region of the Si substrate and including a first output pad part, a second DC blocking capacitor (37,78), an output transmission line (32,72) and a second bias circuit (36,76), the output transmission line (32, 72) having a first region (32a, 72a) and a second region (32b, 72b) spaced from each other, the second DC blocking capacitor (37, 78) being connected between the first region (32a, 72a) and the second region (32b, 72b) of the output transmission line (32, 72), the first output pad part being connected to the first region (32a, 72a) of the output transmission line (32, 72), the second bias circuit (36, 76) including a second grounded capacitor (34, 74) and a second transmission line (35, 75), the second transmission line (35, 75) having one end portion connected to the second grounded capacitor (34, 74) and another end portion connected to the first region (32a, 72a) of the output transmission line (32, 72); a first semiconductor element including a nitride-based semiconductor layer and arranged between the input circuit and the output circuit (30, 70); and a metal plate to which the first semiconductor element and the Si substrate are bonded, the first grounded capacitors, the second grounded capacitor (34,74), the first DC blocking capacitor and the second DC blocking capacitor (37,78) having a first dielectric layer (94a, 94b) including Si oxide film or Si nitride film and sandwiched between upper and lower metal films, and being provided on a surface of the Si substrate. a Si substrate having a first region and a second region, the first region and the second region being provided on a continuous Si plate, or separate Si plates, an input circuit provided on the first region of the Si substrate and including a first DC blocking capacitor, an input transmission line, a first input pad part and a first bias circuit, the input transmission line having a first region and a second region spaced from each other, the first DC blocking capacitor being connected between the first region and the second region of the input transmission line, the first input pad part, being connected to the second region of the input transmission line, the first bias circuit including a first grounded capacitor and a first transmission line, the first transmission line having one end portion connected to the first grounded capacitor and another end portion connected to the second region of the input transmission line; an output circuit (30,70) provided on the second region of the Si substrate and including a first output pad part, a second DC blocking capacitor (37,78), an output transmission line (32,72) and a second bias circuit (36,76), the output transmission line (32, 72) having a first region (32a, 72a) and a second region (32b, 72b) spaced from each other, the second DC blocking capacitor (37, 78) being connected between the first region (32a, 72a) and the second region (32b, 72b) of the output transmission line (32, 72), the first output pad part being connected to the first region (32a, 72a) of the output transmission line (32, 72), the second bias circuit (36, 76) including a second grounded capacitor (34, 74) and a second transmission line (35, 75), the second transmission line (35, 75) having one end portion connected to the second grounded capacitor (34, 74) and another end portion connected to the first region (32a, 72a) of the output transmission line (32, 72); a first semiconductor element including a nitride-based semiconductor layer and arranged between the input circuit and the output circuit (30, 70); and a metal plate to which the first semiconductor element and the Si substrate are bonded, the first grounded capacitors, the second grounded capacitor (34,74), the first DC blocking capacitor and the second DC blocking capacitor (37,78) having a first dielectric layer (94a, 94b) including Si oxide film or Si nitride film and sandwiched between upper and lower metal films, and being provided on a surface of the Si substrate.