A computing method executed by a computing apparatus, comprising: obtaining, based on a plurality of first floating point numbers of a first vector and a plurality of second floating point numbers of a second vector that are input to the computing apparatus, a plurality of first fixed point numbers in binary representation and a plurality of first exponents in binary representation that correspond to the plurality of first floating point numbers respectively, and a plurality of second fixed point numbers in binary representation and a plurality of second exponents in binary representation that correspond to the plurality of second floating point numbers respectively, wherein the plurality of first floating point numbers correspond to the plurality of second floating point numbers, and each of the plurality of first fixed point number and the plurality of second fixed point numbers comprises a sign bit and a first preset number of fixed point mantissa bits; obtaining a fixed point product and a fixed point product exponent corresponding to the fixed point product of each first fixed point number of the plurality of first fixed point numbers and a second fixed point number corresponding to the first fixed point number; obtaining a fixed point inner product calculation result of the first vector and the second vector based on the fixed point product exponent corresponding to each of a plurality of fixed point products corresponding to the plurality of first fixed point numbers; and obtaining, based on the fixed point inner product calculation result, a floating point inner product calculation result in a floating point data format corresponding to the fixed point inner product calculation result. obtaining, based on a plurality of first floating point numbers of a first vector and a plurality of second floating point numbers of a second vector that are input to the computing apparatus, a plurality of first fixed point numbers in binary representation and a plurality of first exponents in binary representation that correspond to the plurality of first floating point numbers respectively, and a plurality of second fixed point numbers in binary representation and a plurality of second exponents in binary representation that correspond to the plurality of second floating point numbers respectively, wherein the plurality of first floating point numbers correspond to the plurality of second floating point numbers, and each of the plurality of first fixed point number and the plurality of second fixed point numbers comprises a sign bit and a first preset number of fixed point mantissa bits; obtaining a fixed point product and a fixed point product exponent corresponding to the fixed point product of each first fixed point number of the plurality of first fixed point numbers and a second fixed point number corresponding to the first fixed point number; obtaining a fixed point inner product calculation result of the first vector and the second vector based on the fixed point product exponent corresponding to each of a plurality of fixed point products corresponding to the plurality of first fixed point numbers; and obtaining, based on the fixed point inner product calculation result, a floating point inner product calculation result in a floating point data format corresponding to the fixed point inner product calculation result.