A semiconductor device stack, comprising: a semiconductor device; and a further semiconductor device, wherein the semiconductor device comprises: a semiconductor base comprising a first base region having a first conductivity type, a plurality of second base regions having a second conductivity type and formed in a surface region of one surface of said first base region, a plurality of emitter regions having the first conductivity type and formed in a surface region of said second base regions, and a collector region having the second conductive type and formed on an another surface of said first base region; a front surface electrode (31, 51) formed on an upper surface of the plurality of emitter regions; and a gate electrode formed, via a gate insulating film, on said second base regions sandwiched between said first base region and said emitter regions, wherein a first region, in which said emitter regions occupy said second base regions at a first rate, is formed at a center of said semiconductor device, wherein a second region, in which said emitter regions occupy said second base regions at a second rate larger than said first rate, is formed at a circumference of said semiconductor device so as to enclose said first region, and wherein said further semiconductor device is arranged only on the center of the semiconductor device with the front surface electrode (31, 51) and a soldered electrode in between. a semiconductor device; and a further semiconductor device, wherein the semiconductor device comprises: a semiconductor base comprising a first base region having a first conductivity type, a plurality of second base regions having a second conductivity type and formed in a surface region of one surface of said first base region, a plurality of emitter regions having the first conductivity type and formed in a surface region of said second base regions, and a collector region having the second conductive type and formed on an another surface of said first base region; a front surface electrode (31, 51) formed on an upper surface of the plurality of emitter regions; and a gate electrode formed, via a gate insulating film, on said second base regions sandwiched between said first base region and said emitter regions, a semiconductor base comprising a first base region having a first conductivity type, a plurality of second base regions having a second conductivity type and formed in a surface region of one surface of said first base region, a plurality of emitter regions having the first conductivity type and formed in a surface region of said second base regions, and a collector region having the second conductive type and formed on an another surface of said first base region; a front surface electrode (31, 51) formed on an upper surface of the plurality of emitter regions; and a gate electrode formed, via a gate insulating film, on said second base regions sandwiched between said first base region and said emitter regions, wherein a first region, in which said emitter regions occupy said second base regions at a first rate, is formed at a center of said semiconductor device, wherein a second region, in which said emitter regions occupy said second base regions at a second rate larger than said first rate, is formed at a circumference of said semiconductor device so as to enclose said first region, and wherein said further semiconductor device is arranged only on the center of the semiconductor device with the front surface electrode (31, 51) and a soldered electrode in between.