A chip package structure, wherein the chip package structure comprises: a substrate having a first board surface and a second board surface that is opposite to the first board surface, wherein the substrate has a plurality of conductive portions arranged on the second board surface; a chip module mounted on the first board surface and electrically coupled to the conductive portions; an encapsulant formed on the first board surface, wherein the chip module is embedded in the encapsulant, and wherein the encapsulant has a patterned trench that is recessed in a top surface thereof and that corresponds in shape to a predetermined two-dimensional code pattern; an electromagnetic interference shielding layer covering the encapsulant, wherein the EMI shielding layer includes a recognition region formed on the top surface and an embedded region that is formed in the patterned trench; and a recognition contrast layer filled in the patterned trench and connected to the embedded region, wherein the recognition contrast layer and the recognition region of the EMI shielding layer respectively have different colors that conform to grade A or grade B in ISO/IEC 15415 standard; wherein an end portion of the recognition contrast layer protrudes from the top surface of the encapsulant and is coplanar with the recognition region of the EMI shielding layer, so that the recognition contrast layer and the recognition region of the EMI shielding layer jointly form the predetermined 2D code pattern having a planar shape; wherein the EMI shielding layer is a nano-metallic layer and is of a single color, and the recognition contrast layer is a toner layer and has a plurality of regions (33a, 33b, 33c, 33d) respectively having different colors. a substrate having a first board surface and a second board surface that is opposite to the first board surface, wherein the substrate has a plurality of conductive portions arranged on the second board surface; a chip module mounted on the first board surface and electrically coupled to the conductive portions; an encapsulant formed on the first board surface, wherein the chip module is embedded in the encapsulant, and wherein the encapsulant has a patterned trench that is recessed in a top surface thereof and that corresponds in shape to a predetermined two-dimensional code pattern; an electromagnetic interference shielding layer covering the encapsulant, wherein the EMI shielding layer includes a recognition region formed on the top surface and an embedded region that is formed in the patterned trench; and a recognition contrast layer filled in the patterned trench and connected to the embedded region, wherein the recognition contrast layer and the recognition region of the EMI shielding layer respectively have different colors that conform to grade A or grade B in ISO/IEC 15415 standard; wherein an end portion of the recognition contrast layer protrudes from the top surface of the encapsulant and is coplanar with the recognition region of the EMI shielding layer, so that the recognition contrast layer and the recognition region of the EMI shielding layer jointly form the predetermined 2D code pattern having a planar shape; wherein the EMI shielding layer is a nano-metallic layer and is of a single color, and the recognition contrast layer is a toner layer and has a plurality of regions (33a, 33b, 33c, 33d) respectively having different colors.