A signal processing circuit comprising: an arithmetic circuit including a logic circuit which carries out arithmetic processing and a switching element which controls the supply of power supply voltage to the logic circuit; and a memory device configured to store data from the arithmetic circuit, wherein the memory device comprises a plurality of memory elements, wherein each of the plurality of memory elements comprises a pair of logic elements (101, 102) configured to hold the data by connection of an output terminal of one of the pair of logic elements (101, 102) to an input terminal of the other of the pair of logic elements (101, 102) and an output terminal of the other of the pair of logic elements (101, 102) to an input terminal of the one of the pair of logic elements (101, 102), a capacitor, a first transistor which includes an oxide semiconductor in a channel formation region and is configured to control writing of the data to the capacitor, and a second transistor, wherein the pair of logic elements (101, 102) comprise at least one of an inverter and a clocked inverter, wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to the input terminal of the one of the pair of logic elements (101, 102), wherein one of a source and a drain of the second transistor is electrically connected to the input terminal of the one of the pair of logic elements (101, 102), and wherein the other of the source and the drain of the second transistor is electrically connected to the output terminal of the other of the pair of logic elements (101, 102). an arithmetic circuit including a logic circuit which carries out arithmetic processing and a switching element which controls the supply of power supply voltage to the logic circuit; and a memory device configured to store data from the arithmetic circuit, wherein the memory device comprises a plurality of memory elements, wherein each of the plurality of memory elements comprises a pair of logic elements (101, 102) configured to hold the data by connection of an output terminal of one of the pair of logic elements (101, 102) to an input terminal of the other of the pair of logic elements (101, 102) and an output terminal of the other of the pair of logic elements (101, 102) to an input terminal of the one of the pair of logic elements (101, 102), a capacitor, a first transistor which includes an oxide semiconductor in a channel formation region and is configured to control writing of the data to the capacitor, and a second transistor, wherein the pair of logic elements (101, 102) comprise at least one of an inverter and a clocked inverter, wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to the input terminal of the one of the pair of logic elements (101, 102), wherein one of a source and a drain of the second transistor is electrically connected to the input terminal of the one of the pair of logic elements (101, 102), and wherein the other of the source and the drain of the second transistor is electrically connected to the output terminal of the other of the pair of logic elements (101, 102).