A data processing apparatus comprising: register storage circuitry having a plurality of registers to store data elements; decoder circuitry responsive to a data processing instruction to generate control signals, the data processing instruction specifying in the plurality of registers: a first source register sub-divided into a plurality of first data elements grouped into a first plurality of independent intra-register lanes of the first source register and a second source register sub-divided into a plurality of second data elements grouped into a second plurality of independent intra-register lanes of the second source register; and processing circuitry responsive to the control signals to perform, for each intra-register lane of the first plurality of independent intra-register lanes, a dot product operation comprising: extracting a first set of two or more first data elements from the intra-register lane of the first plurality of independent intra-register lanes; extracting a second set of two or more second data elements from an intra-register lane of the second plurality of independent intra-register lanes; performing pair-wise multiply operations of multiplying together the first set of two or more first data elements and the second set of two or more second data elements; and summing results of the pair-wise multiply operations, wherein: the data processing instruction specifies a repeated intra-register lane among the second plurality of independent intra-register lanes of the second source register; and the processing circuitry is responsive to the control signals to perform the dot product operation independently in each of the first plurality of intra-register lanes of the first source register and to reuse content of the repeated intra-register lane for the intra-register lane of the second plurality of independent intra-register lanes for each intra-register lane of the first plurality of independent intra-register lanes. register storage circuitry having a plurality of registers to store data elements; decoder circuitry responsive to a data processing instruction to generate control signals, the data processing instruction specifying in the plurality of registers: a first source register sub-divided into a plurality of first data elements grouped into a first plurality of independent intra-register lanes of the first source register and a second source register sub-divided into a plurality of second data elements grouped into a second plurality of independent intra-register lanes of the second source register; and processing circuitry responsive to the control signals to perform, for each intra-register lane of the first plurality of independent intra-register lanes, a dot product operation comprising: extracting a first set of two or more first data elements from the intra-register lane of the first plurality of independent intra-register lanes; extracting a second set of two or more second data elements from an intra-register lane of the second plurality of independent intra-register lanes; performing pair-wise multiply operations of multiplying together the first set of two or more first data elements and the second set of two or more second data elements; and summing results of the pair-wise multiply operations, extracting a first set of two or more first data elements from the intra-register lane of the first plurality of independent intra-register lanes; extracting a second set of two or more second data elements from an intra-register lane of the second plurality of independent intra-register lanes; performing pair-wise multiply operations of multiplying together the first set of two or more first data elements and the second set of two or more second data elements; and summing results of the pair-wise multiply operations, wherein: the data processing instruction specifies a repeated intra-register lane among the second plurality of independent intra-register lanes of the second source register; and the processing circuitry is responsive to the control signals to perform the dot product operation independently in each of the first plurality of intra-register lanes of the first source register and to reuse content of the repeated intra-register lane for the intra-register lane of the second plurality of independent intra-register lanes for each intra-register lane of the first plurality of independent intra-register lanes. the data processing instruction specifies a repeated intra-register lane among the second plurality of independent intra-register lanes of the second source register; and the processing circuitry is responsive to the control signals to perform the dot product operation independently in each of the first plurality of intra-register lanes of the first source register and to reuse content of the repeated intra-register lane for the intra-register lane of the second plurality of independent intra-register lanes for each intra-register lane of the first plurality of independent intra-register lanes.