A pixel driving circuit, comprising: a control unit (214, 314) being coupled with a data line (204, 304), a common power line (202, 302), a first scan line (206, 306) and a first node (220, 320), and controlling a voltage of the first node (220, 320) to be a voltage on the data line (204, 304) or a voltage on the common power line (202, 302) by an input signal from the first scan line (206, 306), wherein the control unit (214, 314) comprises one transistor having a PMOS structure and one transistor having a NMOS structure; a capacitor (234, 334) having a first sustaining electrode coupled with the first node (220, 320) and a second sustaining electrode coupled with a second node (222, 322); a third transistor (224, 324) having a source coupled with a third node, a gate coupled with a first input terminal (210, 310), and a drain coupled with the second node (222, 322); and a fourth transistor (230, 330) having a source coupled with the third node, a gate coupled with a second input terminal (212, 312), and a drain coupled with an anode of a light emitting diode (232, 332), characterized in that the pixel driving circuit further comprises: a first transistor (228, 328) having a source coupled with the common power line (202, 302), a gate coupled with a second scan line (208, 308), and a drain; and a second transistor (226, 326) having a source coupled with the third node, a gate coupled with the second node (222, 322), and a drain coupled with the drain of the first transistor (228, 328), wherein the second scan line (208, 308) is the first scan line of a pixel driving circuit adjacent to the pixel driving circuit. a control unit (214, 314) being coupled with a data line (204, 304), a common power line (202, 302), a first scan line (206, 306) and a first node (220, 320), and controlling a voltage of the first node (220, 320) to be a voltage on the data line (204, 304) or a voltage on the common power line (202, 302) by an input signal from the first scan line (206, 306), wherein the control unit (214, 314) comprises one transistor having a PMOS structure and one transistor having a NMOS structure; a capacitor (234, 334) having a first sustaining electrode coupled with the first node (220, 320) and a second sustaining electrode coupled with a second node (222, 322); a third transistor (224, 324) having a source coupled with a third node, a gate coupled with a first input terminal (210, 310), and a drain coupled with the second node (222, 322); and a fourth transistor (230, 330) having a source coupled with the third node, a gate coupled with a second input terminal (212, 312), and a drain coupled with an anode of a light emitting diode (232, 332), characterized in that the pixel driving circuit further comprises: a first transistor (228, 328) having a source coupled with the common power line (202, 302), a gate coupled with a second scan line (208, 308), and a drain; and a second transistor (226, 326) having a source coupled with the third node, a gate coupled with the second node (222, 322), and a drain coupled with the drain of the first transistor (228, 328), a first transistor (228, 328) having a source coupled with the common power line (202, 302), a gate coupled with a second scan line (208, 308), and a drain; and a second transistor (226, 326) having a source coupled with the third node, a gate coupled with the second node (222, 322), and a drain coupled with the drain of the first transistor (228, 328), wherein the second scan line (208, 308) is the first scan line of a pixel driving circuit adjacent to the pixel driving circuit.