A system for synchronizing the states of several sequential processing units (405, 409) comprising: an input for receiving a common clock signal (clk); a first clock signal path for providing a first output clock signal derived from the common clock signal (clk) to a first processing unit; and a second clock signal path for providing a second output clock signal to a second processing unit, the second clock signal path comprising a clock processing means for changing a phase of the common clock signal (clk) to provide the second output clock signal, and means for determining a synchronization error between the states of the processing units (405, 409), which receives an output signal of the first processing unit via a first input and an output signal of the second processing unit via a second input, wherein an output of the means for determining the synchronisation error is fed back to a control input of the clock processing means, wherein in applications where the distribution of a common reset signal to all processing units (405, 409) is not practical, the processing units (405, 409) are allowed to start in random initial states, the offset between the states are measured and the state offset is corrected, wherein the processing units (405, 409) consist of a counter having at least on state variable and the clock processing means is able to shift the phase of the common clock signal (clk) over an angle of more than 360° without discontinuity or in such small discrete increments that the second sequential processing unit keeps operating while the phase is rotated in order to generate the second output clock signal, and wherein after N cycles of the common clock signal (clk) the clock processing means rotates the phase of the common clock signal (clk) by 360°, and over this time frame the first processing unit experiences N clock cycles, whereas the second processing unit experiences N+1 clock cycles or N-1 clock cycles depending in which direction the clock processing means rotates the phase. an input for receiving a common clock signal (clk); a first clock signal path for providing a first output clock signal derived from the common clock signal (clk) to a first processing unit; and a second clock signal path for providing a second output clock signal to a second processing unit, the second clock signal path comprising a clock processing means for changing a phase of the common clock signal (clk) to provide the second output clock signal, and means for determining a synchronization error between the states of the processing units (405, 409), which receives an output signal of the first processing unit via a first input and an output signal of the second processing unit via a second input, wherein an output of the means for determining the synchronisation error is fed back to a control input of the clock processing means, wherein in applications where the distribution of a common reset signal to all processing units (405, 409) is not practical, the processing units (405, 409) are allowed to start in random initial states, the offset between the states are measured and the state offset is corrected, wherein the processing units (405, 409) consist of a counter having at least on state variable and the clock processing means is able to shift the phase of the common clock signal (clk) over an angle of more than 360° without discontinuity or in such small discrete increments that the second sequential processing unit keeps operating while the phase is rotated in order to generate the second output clock signal, and wherein after N cycles of the common clock signal (clk) the clock processing means rotates the phase of the common clock signal (clk) by 360°, and over this time frame the first processing unit experiences N clock cycles, whereas the second processing unit experiences N+1 clock cycles or N-1 clock cycles depending in which direction the clock processing means rotates the phase.