A dynamic current sink suitable for stabilizing an output voltage at an output node (NOUT) of an LDO (Low Dropout Linear Regulator), when the dynamic current sink is coupled to said LDO, the dynamic current sink comprising: a first voltage comparator, suitable for comparing a first reference voltage (VREF1) with a second control signal from the LDO when the dynamic current sink is coupled to said LDO, so as to generate a first control signal; a first transistor, wherein the first transistor has a control terminal for receiving the first control signal, a first terminal coupled to a ground voltage, and a second terminal coupled to a first node; a first current source, supplying a first current to the first node; a first inverter, wherein the first inverter has an input terminal coupled to the first node, and an output terminal coupled to a second node; a second current source, supplying a second current to a third node; an NAND gate, wherein the NAND gate has a first input terminal coupled to the third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node; a first capacitor, coupled between the fourth node and a fifth node; a first resistor, coupled between the fifth node and the ground voltage; a second transistor, wherein the second transistor has a control terminal coupled to the fifth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the third node; and a third transistor, wherein the third transistor has a control terminal coupled to the fifth node, a first terminal coupled to the ground voltage, and a second terminal suitable for being coupled to the output node (NOUT) when the dynamic current sink is coupled to said LDO; wherein the third transistor is configured to selectively draw a first discharge current from the output node (NOUT). a first voltage comparator, suitable for comparing a first reference voltage (VREF1) with a second control signal from the LDO when the dynamic current sink is coupled to said LDO, so as to generate a first control signal; a first transistor, wherein the first transistor has a control terminal for receiving the first control signal, a first terminal coupled to a ground voltage, and a second terminal coupled to a first node; a first current source, supplying a first current to the first node; a first inverter, wherein the first inverter has an input terminal coupled to the first node, and an output terminal coupled to a second node; a second current source, supplying a second current to a third node; an NAND gate, wherein the NAND gate has a first input terminal coupled to the third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node; a first capacitor, coupled between the fourth node and a fifth node; a first resistor, coupled between the fifth node and the ground voltage; a second transistor, wherein the second transistor has a control terminal coupled to the fifth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the third node; and a third transistor, wherein the third transistor has a control terminal coupled to the fifth node, a first terminal coupled to the ground voltage, and a second terminal suitable for being coupled to the output node (NOUT) when the dynamic current sink is coupled to said LDO; wherein the third transistor is configured to selectively draw a first discharge current from the output node (NOUT).