A memory device comprising: a sense amplifier; a first memory cell including: a first transistor having a control gate; a second transistor having a control gate, and a first current electrode coupled to an input of the sense amplifier; and a resistive storage element having a first terminal and a second terminal; a second memory cell including: a first transistor having a control gate, and a first current electrode coupled to another input of the sense amplifier; a second transistor having a control gate; and a resistive storage element having a first terminal and a second terminal; a word line coupled to the control gates of the first and second transistors of the first and second memory cells; and a source line coupled to a second terminal of the resistive storage elements in the first and second memory cells, wherein the memory device is operable to: provide a sense current through the first transistor of the first memory cell; sense a first feedback voltage at the first current electrode of the second transistor in the first memory cell, wherein the first feedback voltage is at the first terminal of the resistive storage element; sense a second feedback voltage at the first current electrode of the first transistor of the second memory cell, wherein the second feedback voltage is at a second terminal of the resistive storage element; and adjust the sense current through the first memory cell based on the first and second feedback voltages. a sense amplifier; a first memory cell including: a first transistor having a control gate; a second transistor having a control gate, and a first current electrode coupled to an input of the sense amplifier; and a resistive storage element having a first terminal and a second terminal; a first transistor having a control gate; a second transistor having a control gate, and a first current electrode coupled to an input of the sense amplifier; and a resistive storage element having a first terminal and a second terminal; a second memory cell including: a first transistor having a control gate, and a first current electrode coupled to another input of the sense amplifier; a second transistor having a control gate; and a resistive storage element having a first terminal and a second terminal; a first transistor having a control gate, and a first current electrode coupled to another input of the sense amplifier; a second transistor having a control gate; and a resistive storage element having a first terminal and a second terminal; a word line coupled to the control gates of the first and second transistors of the first and second memory cells; and a source line coupled to a second terminal of the resistive storage elements in the first and second memory cells, provide a sense current through the first transistor of the first memory cell; sense a first feedback voltage at the first current electrode of the second transistor in the first memory cell, wherein the first feedback voltage is at the first terminal of the resistive storage element; sense a second feedback voltage at the first current electrode of the first transistor of the second memory cell, wherein the second feedback voltage is at a second terminal of the resistive storage element; and adjust the sense current through the first memory cell based on the first and second feedback voltages.