A storage device (100; 1150_1 to 1150_n; 1250_1 to 1250_m) comprising: a nonvolatile memory device; and a storage controller, wherein the storage controller includes: a multi-protocol host interface circuit configured to: receive a first-type request, T1RQ, including a first logical address from an external host, transmit/receive data corresponding to the first-type request, T1RQ, to/from the external host by a block unit, receive S110; S207) a second-type request, T2RQ, including a first physical address from the external host, and transmit/receive data corresponding to the second-type request, T2RQ, to/from the external host by a unit smaller than the block unit; and a mapping cache manager configured to manage an address translation table cache, ATTC, and characterized in that the mapping cache manager is further configured to: send an address translation request including the first physical address to the external host in response to determining that the mapping information corresponding to the first physical address, PA, is absent in the address translation table cache, ATTC, receive a response including a second logical address corresponding to the first physical address from the external host, and store the corresponding second logical address in the address translation table cache, ATTC, so as to be correlated with the first physical address, PA. a nonvolatile memory device; and a storage controller, wherein the storage controller includes: a multi-protocol host interface circuit configured to: receive a first-type request, T1RQ, including a first logical address from an external host, transmit/receive data corresponding to the first-type request, T1RQ, to/from the external host by a block unit, receive S110; S207) a second-type request, T2RQ, including a first physical address from the external host, and transmit/receive data corresponding to the second-type request, T2RQ, to/from the external host by a unit smaller than the block unit; and a mapping cache manager configured to manage an address translation table cache, ATTC, and a multi-protocol host interface circuit configured to: receive a first-type request, T1RQ, including a first logical address from an external host, transmit/receive data corresponding to the first-type request, T1RQ, to/from the external host by a block unit, receive S110; S207) a second-type request, T2RQ, including a first physical address from the external host, and transmit/receive data corresponding to the second-type request, T2RQ, to/from the external host by a unit smaller than the block unit; and receive a first-type request, T1RQ, including a first logical address from an external host, transmit/receive data corresponding to the first-type request, T1RQ, to/from the external host by a block unit, receive S110; S207) a second-type request, T2RQ, including a first physical address from the external host, and transmit/receive data corresponding to the second-type request, T2RQ, to/from the external host by a unit smaller than the block unit; and a mapping cache manager configured to manage an address translation table cache, ATTC, and characterized in that the mapping cache manager is further configured to: send an address translation request including the first physical address to the external host in response to determining that the mapping information corresponding to the first physical address, PA, is absent in the address translation table cache, ATTC, receive a response including a second logical address corresponding to the first physical address from the external host, and store the corresponding second logical address in the address translation table cache, ATTC, so as to be correlated with the first physical address, PA. send an address translation request including the first physical address to the external host in response to determining that the mapping information corresponding to the first physical address, PA, is absent in the address translation table cache, ATTC, receive a response including a second logical address corresponding to the first physical address from the external host, and store the corresponding second logical address in the address translation table cache, ATTC, so as to be correlated with the first physical address, PA.