A RISC processor supporting an X86 virtual machine, characterized in comprising: an instruction module for storing a virtual machine instruction set that supports the X86 virtual machine; a decoder for, during the decoding of an instruction of the virtual machine instruction set, distinguishing the virtual machine instruction set mode of the instruction, decoding the instruction according to the distinguished virtual machine instruction set mode, and outputting the decoded instruction to the fixed-point operation component or the floating-point operation component; a look-up table for storing the jump addresses in an X86 program and the MIPS jump addresses, and quickly looking up the translations from the jump addresses in the X86 program to the MIPS jump addresses according to the output of the decoder; a fixed-point operation component for making a processing on the fixed-point instruction of the virtual machine instruction set according to the output of the decoder and outputting the execution result; a floating-point operation component for making a processing on the floating-point instruction of the virtual machine instruction set according to the output of the decoder and outputting the execution result; a floating-point register pile, including a floating-point control register, floating-point register stacks, and Nos. 1-3 floating-point registers; wherein, the decoder further comprises a TOP pointer register for maintaining a floating-point stack operation pointer and storing the value of the floating-point stack operation pointer, wherein the decoder further comprises a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table according to an instruction related to the look-up table, wherein the floating-point control register maintains a stack enable bit, the enable bit set to 1 denoting that the processor will emulate a floating-point register stack operation of the X86 processor, and wherein, if the stack enable bit is set, the source of or the number of the destination logic register for any register with a register number smaller than 8 involved in the corresponding floating-point operation instruction will be modified according to the TOP value and the TOP value will be modified according to the content of the instruction during decoding. an instruction module for storing a virtual machine instruction set that supports the X86 virtual machine; a decoder for, during the decoding of an instruction of the virtual machine instruction set, distinguishing the virtual machine instruction set mode of the instruction, decoding the instruction according to the distinguished virtual machine instruction set mode, and outputting the decoded instruction to the fixed-point operation component or the floating-point operation component; a look-up table for storing the jump addresses in an X86 program and the MIPS jump addresses, and quickly looking up the translations from the jump addresses in the X86 program to the MIPS jump addresses according to the output of the decoder; a fixed-point operation component for making a processing on the fixed-point instruction of the virtual machine instruction set according to the output of the decoder and outputting the execution result; a floating-point operation component for making a processing on the floating-point instruction of the virtual machine instruction set according to the output of the decoder and outputting the execution result; a floating-point register pile, including a floating-point control register, floating-point register stacks, and Nos. 1-3 floating-point registers; wherein, the decoder further comprises a TOP pointer register for maintaining a floating-point stack operation pointer and storing the value of the floating-point stack operation pointer, wherein the decoder further comprises a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table according to an instruction related to the look-up table, wherein the floating-point control register maintains a stack enable bit, the enable bit set to 1 denoting that the processor will emulate a floating-point register stack operation of the X86 processor, and wherein, if the stack enable bit is set, the source of or the number of the destination logic register for any register with a register number smaller than 8 involved in the corresponding floating-point operation instruction will be modified according to the TOP value and the TOP value will be modified according to the content of the instruction during decoding.