A DRAM structure, comprising: a substrate and a conductive structure located above the substrate, wherein the substrate comprises a device area, and a first connection and a second connection area that are respectively arranged on two sides of the device area; the conductive structure comprises a plurality of first conductive structures and second conductive structures that are spaced apart from each other in a second direction and extend in a first direction; and lengths of the first conductive structures vary in steps and lengths of the second conductive structures vary in steps; the first conductive structures are located above the device area and extend to the first connection area, and the second conductive structures are located above the device area and extend to the second connection area; and the lengths of the first conductive structures located above the first connection area vary in steps, and the lengths of the second conductive structures located above the second connection area vary in steps; the first conductive structures and the second conductive structures correspond to a wordline structure, which extend along the first direction; the wordline structure penetrates the device area and surrounds a plurality of channel structures; a bitline structure, comprising a plurality of bitlines, penetrates the device area and extending in the second direction; each of the bitlines is connected to first ends of the plurality of channel structures and a second ends of the plurality of channel structures are connected to a storage node; characterized in that each first conductive structure and each second conductive structure above the device area surround the plurality of channel structures spaced apart from each other; and dielectric layers are arranged between the first conductive structure and the channel structures, and between the second conductive structure and the channel structures, the channel structures are arranged in an array, extend in a third direction and are spaced from each other in the first direction and the second direction; and each first conductive structure above the first connection area surrounds a first active layer, and a first insulation layer is arranged between the first conductive structure and the first active layer; each second conductive structure above the second connection area surrounds a second active layer, and a second insulation layer is arranged between the second conductive structure and the second active layer, and wherein the first active layer and the plurality of channel structures corresponding to a same first conductive structure are arranged at a same layer; and the second active layer and the plurality of channel structures corresponding to a same second conductive structure are arranged at a same layer. a substrate and a conductive structure located above the substrate, wherein the substrate comprises a device area, and a first connection and a second connection area that are respectively arranged on two sides of the device area; the conductive structure comprises a plurality of first conductive structures and second conductive structures that are spaced apart from each other in a second direction and extend in a first direction; and lengths of the first conductive structures vary in steps and lengths of the second conductive structures vary in steps; the first conductive structures are located above the device area and extend to the first connection area, and the second conductive structures are located above the device area and extend to the second connection area; and the lengths of the first conductive structures located above the first connection area vary in steps, and the lengths of the second conductive structures located above the second connection area vary in steps; the first conductive structures and the second conductive structures correspond to a wordline structure, which extend along the first direction; the wordline structure penetrates the device area and surrounds a plurality of channel structures; a bitline structure, comprising a plurality of bitlines, penetrates the device area and extending in the second direction; each of the bitlines is connected to first ends of the plurality of channel structures and a second ends of the plurality of channel structures are connected to a storage node; characterized in that each first conductive structure and each second conductive structure above the device area surround the plurality of channel structures spaced apart from each other; and dielectric layers are arranged between the first conductive structure and the channel structures, and between the second conductive structure and the channel structures, the channel structures are arranged in an array, extend in a third direction and are spaced from each other in the first direction and the second direction; and each first conductive structure above the first connection area surrounds a first active layer, and a first insulation layer is arranged between the first conductive structure and the first active layer; each second conductive structure above the second connection area surrounds a second active layer, and a second insulation layer is arranged between the second conductive structure and the second active layer, and wherein the first active layer and the plurality of channel structures corresponding to a same first conductive structure are arranged at a same layer; and the second active layer and the plurality of channel structures corresponding to a same second conductive structure are arranged at a same layer.