A shift register (410, 411,... 414) comprising: a plurality of bistable circuits (SR,... SR(n)) each having a first state and a second state and being connected in series with each other, wherein the plurality of bistable circuits (SR,... SR(n)) are configured to sequentially become in the first state based on at least four phase-shifted clock signals (GCK1, GCK2, GCK3, GCK4) including two phase-shifted clock signals (GCK1, GCK3) which are provided as a first clock signal and a second clock signal to odd-order stage bistable circuits out of the plurality of bistable circuits (SR,... SR(n)), and two phase-shifted clock signals (GCK2, GCK4) which are provided as the first clock signal and the second clock signal to even-order stage bistable circuits out of the plurality of bistable circuits (SR,... SR(n)), wherein each bistable circuit (SR(k)) includes: an output node (GOUT, 51) configured to output a state signal indicating either one of the first state and the second state; an output-control switching element in which the first clock signal is provided to a second electrode, and a third electrode is connected to the output node (GOUT, 51); a first first-node charge unit (T1 configured to charge a first node (netA) connected to a first electrode of the output-control switching element based on a state signal output from a pre-stage bistable circuit (SR(k-1)) of each bistable circuit (SR(k)) concerned; a second first-node charge unit: configured to charge the first node (netA) based on a state signal output from a next-stage bistable circuit (SR(k+1)) of each bistable circuit (SR(k)) concerned; a first first-node discharge unit: configured to discharge the first node (netA) based on a state signal output from a bistable circuit (SR(k)) of a third stage after each bistable circuit (SR(k+3)) concerned, and a second first-node discharge unit configured to discharge the first node (netA) based on a state signal output from a bistable circuit (SR(k)) of a third stage before each bistable circuit (SR(k-3)) concerned. a plurality of bistable circuits (SR,... SR(n)) each having a first state and a second state and being connected in series with each other, wherein the plurality of bistable circuits (SR,... SR(n)) are configured to sequentially become in the first state based on at least four phase-shifted clock signals (GCK1, GCK2, GCK3, GCK4) including two phase-shifted clock signals (GCK1, GCK3) which are provided as a first clock signal and a second clock signal to odd-order stage bistable circuits out of the plurality of bistable circuits (SR,... SR(n)), and two phase-shifted clock signals (GCK2, GCK4) which are provided as the first clock signal and the second clock signal to even-order stage bistable circuits out of the plurality of bistable circuits (SR,... SR(n)), wherein each bistable circuit (SR(k)) includes: an output node (GOUT, 51) configured to output a state signal indicating either one of the first state and the second state; an output-control switching element in which the first clock signal is provided to a second electrode, and a third electrode is connected to the output node (GOUT, 51); a first first-node charge unit (T1 configured to charge a first node (netA) connected to a first electrode of the output-control switching element based on a state signal output from a pre-stage bistable circuit (SR(k-1)) of each bistable circuit (SR(k)) concerned; a second first-node charge unit: configured to charge the first node (netA) based on a state signal output from a next-stage bistable circuit (SR(k+1)) of each bistable circuit (SR(k)) concerned; a first first-node discharge unit: configured to discharge the first node (netA) based on a state signal output from a bistable circuit (SR(k)) of a third stage after each bistable circuit (SR(k+3)) concerned, and a second first-node discharge unit configured to discharge the first node (netA) based on a state signal output from a bistable circuit (SR(k)) of a third stage before each bistable circuit (SR(k-3)) concerned. an output node (GOUT, 51) configured to output a state signal indicating either one of the first state and the second state; an output-control switching element in which the first clock signal is provided to a second electrode, and a third electrode is connected to the output node (GOUT, 51); a first first-node charge unit (T1 configured to charge a first node (netA) connected to a first electrode of the output-control switching element based on a state signal output from a pre-stage bistable circuit (SR(k-1)) of each bistable circuit (SR(k)) concerned; a second first-node charge unit: configured to charge the first node (netA) based on a state signal output from a next-stage bistable circuit (SR(k+1)) of each bistable circuit (SR(k)) concerned; a first first-node discharge unit: configured to discharge the first node (netA) based on a state signal output from a bistable circuit (SR(k)) of a third stage after each bistable circuit (SR(k+3)) concerned, and a second first-node discharge unit configured to discharge the first node (netA) based on a state signal output from a bistable circuit (SR(k)) of a third stage before each bistable circuit (SR(k-3)) concerned.