An apparatus, comprising: a power gating field effect transistor, FET, comprising a gate, a source, and a drain, wherein the source is coupled to a voltage rail (Vdd), wherein the drain is coupled to a load, and wherein the gate is configured to receive a gating voltage (V G) to selectively turn on the power gating FET to allow a load current to flow between the voltage rail and the load by way of the power gating FET; and a differential amplifier configured to generate a current-related voltage (Vs) related to the load current by applying a gain to an input voltage, wherein the input voltage is based on a drain-to-source voltage (V DS) of the power gating FET, and wherein the gain varies inversely with the input voltage in response to variation in temperature or gate-to-source voltage of the power gating FET, wherein the differential amplifier comprises: an operational amplifier; a first compensating PMOS device (P2B) including a first gate, a first source, and a first drain, wherein the first compensating PMOS device (P2B) is coupled between the source of the power gating FET and a first input of the operational amplifier, wherein the first gate is configured to receive a first gate voltage substantially the same as the gating voltage that turns on the power gating FET; a second compensating PMOS device (P2A) including a second gate, a second source, and a second drain, wherein the second compensating PMOS device (P2A) is coupled between the drain of the power gating FET and a second input of the operational amplifier, wherein the second gate is configured to receive a second gate voltage substantially the same as the gating voltage that turns on the power gating FET; and at least one feedback resistor (R2A, R2B) coupled across an output of the operational amplifier and one of the first or second inputs of the operational amplifier, wherein the current-related voltage is generated at the output of the operational amplifier. a power gating field effect transistor, FET, comprising a gate, a source, and a drain, wherein the source is coupled to a voltage rail (Vdd), wherein the drain is coupled to a load, and wherein the gate is configured to receive a gating voltage (V G) to selectively turn on the power gating FET to allow a load current to flow between the voltage rail and the load by way of the power gating FET; and a differential amplifier configured to generate a current-related voltage (Vs) related to the load current by applying a gain to an input voltage, wherein the input voltage is based on a drain-to-source voltage (V DS) of the power gating FET, and wherein the gain varies inversely with the input voltage in response to variation in temperature or gate-to-source voltage of the power gating FET, wherein the differential amplifier comprises: an operational amplifier; a first compensating PMOS device (P2B) including a first gate, a first source, and a first drain, wherein the first compensating PMOS device (P2B) is coupled between the source of the power gating FET and a first input of the operational amplifier, wherein the first gate is configured to receive a first gate voltage substantially the same as the gating voltage that turns on the power gating FET; a second compensating PMOS device (P2A) including a second gate, a second source, and a second drain, wherein the second compensating PMOS device (P2A) is coupled between the drain of the power gating FET and a second input of the operational amplifier, wherein the second gate is configured to receive a second gate voltage substantially the same as the gating voltage that turns on the power gating FET; and at least one feedback resistor (R2A, R2B) coupled across an output of the operational amplifier and one of the first or second inputs of the operational amplifier, wherein the current-related voltage is generated at the output of the operational amplifier. an operational amplifier; a first compensating PMOS device (P2B) including a first gate, a first source, and a first drain, wherein the first compensating PMOS device (P2B) is coupled between the source of the power gating FET and a first input of the operational amplifier, wherein the first gate is configured to receive a first gate voltage substantially the same as the gating voltage that turns on the power gating FET; a second compensating PMOS device (P2A) including a second gate, a second source, and a second drain, wherein the second compensating PMOS device (P2A) is coupled between the drain of the power gating FET and a second input of the operational amplifier, wherein the second gate is configured to receive a second gate voltage substantially the same as the gating voltage that turns on the power gating FET; and at least one feedback resistor (R2A, R2B) coupled across an output of the operational amplifier and one of the first or second inputs of the operational amplifier, wherein the current-related voltage is generated at the output of the operational amplifier.