Method for reducing the non-linearity effect of a digital-analogue converter on an electronic interface circuit of a capacitive sensor for measuring a physical parameter, said capacitive sensor including at least two differential connected capacitors (C1X, C2X) whose common electrode is capable of moving relative to each fixed electrode of the two capacitors to alter the capacitive value of each capacitor when the physical parameter is being measured, said electronic circuit including a charge transfer amplifier connected to the common electrode via a switching unit, a logic unit connected to the amplifier output for digital processing of the data supplied by the amplifier and for supplying digital measuring signals, and a digital-analogue converter capable of supplying a measuring voltage (V DAC) to the electrodes via the switching unit, the measuring voltage being defined on the basis of a binary word (DACbus) conversion defining at least one of the digital measuring signals, the method including, in each successive measuring cycle, steps consisting in: a) biasing the electrodes of the capacitors (C1X, C2X, CM) via the switching unit with a measuring voltage (V DAC) supplied by the digital-analogue converter on the basis of a first digital measuring signal stored in at least a first register of the logic unit, from a preceding cycle or a first initial binary word supplied by the logic unit, the first digital signal depending on a first biasing of the fixed electrodes of the capacitors, b) biasing the fixed electrode of the first capacitor (C1X) at a regulated high voltage (V REG) from a voltage source of the electronic circuit, and biasing the fixed electrode of the second capacitor (C2X) at a low voltage (Vss) from the voltage source, in order to adapt the first digital measuring signal in the logic unit, c) biasing the electrodes of the capacitors (C1X, C2X, CM) via the switching unit with a measuring voltage (V DAC) supplied by the digital-analogue converter on the basis of a second digital measuring signal stored in at least a second register of the logic unit, from a preceding cycle or a second initial binary word supplied by the logic unit, the second digital signal depending on a second biasing which is the reverse of the first biasing of the fixed electrodes of the capacitors, and d) biasing the fixed electrode of the first capacitor (C1X) at a low voltage (Vss) from the electronic circuit voltage source, and biasing the fixed electrode of the second capacitor (C2X) at a regulated high voltage (V REG) from the voltage source, in order to adapt the second digital measuring signal in the logic unit, characterized in that initially, or during the physical parameter measuring cycles, a defined offset voltage (Vref) of an electronic assembly (15, 16) of the digital-analogue converter is introduced into the digital-analogue converter to modify or modulate the first and second digital signals, in that a mean of a positive integration curve and of a negative integration curve is performed with digital values stored in the first and second registers of the logic unit, and in that a mean of the first and second digital signals is taken so as to supply a digital output signal (OUT DX) relating to the physical parameter measurement with a reduction in the non-linearity effect of the digital-analogue converter, which includes a capacitor array controlled in succession by the binary word (DACbus) of the first register and by the binary word (DACbus) of the second register. a) biasing the electrodes of the capacitors (C1X, C2X, CM) via the switching unit with a measuring voltage (V DAC) supplied by the digital-analogue converter on the basis of a first digital measuring signal stored in at least a first register of the logic unit, from a preceding cycle or a first initial binary word supplied by the logic unit, the first digital signal depending on a first biasing of the fixed electrodes of the capacitors, b) biasing the fixed electrode of the first capacitor (C1X) at a regulated high voltage (V REG) from a voltage source of the electronic circuit, and biasing the fixed electrode of the second capacitor (C2X) at a low voltage (Vss) from the voltage source, in order to adapt the first digital measuring signal in the logic unit, c) biasing the electrodes of the capacitors (C1X, C2X, CM) via the switching unit with a measuring voltage (V DAC) supplied by the digital-analogue converter on the basis of a second digital measuring signal stored in at least a second register of the logic unit, from a preceding cycle or a second initial binary word supplied by the logic unit, the second digital signal depending on a second biasing which is the reverse of the first biasing of the fixed electrodes of the capacitors, and d) biasing the fixed electrode of the first capacitor (C1X) at a low voltage (Vss) from the electronic circuit voltage source, and biasing the fixed electrode of the second capacitor (C2X) at a regulated high voltage (V REG) from the voltage source, in order to adapt the second digital measuring signal in the logic unit,