Method of input data compression performed by a plurality of cores (14A,..., 14N) communicating with a central memory, each core (14A,..., 14N) being associated to an operating cache memory able to store data items, and comprising a plurality of vector registers able to store data items to be processed, each vector register presenting a predetermined register length, for each core, the operating cache memory comprising a plurality of cache lines, each cache line presenting a predetermined cache line length which is a multiple of the register length; the input data presents a two-dimensional input array formed by a plurality data items stored contiguously in the central memory according to a contiguous direction; the method comprising a step (110; 110') of two-dimensional wavelet transform implemented using a low band-pass filter vector of dimension N and a high band-pass filter vector of dimension N, said step comprising the following sub-steps: A) forming from the input array at least one tile (B 1,..., B 4) comprising a plurality of consecutive data block columns (C 11,..., C 13), each data block column (C 11,..., C 13) being formed by a plurality of lines of consecutive data items according to the contiguous direction, the length of each line being a multiple of the cache line length; C) for the or each tile (B 1,..., B 4), processing each data block column (C 11,..., C 13) and for each data block column (C 11,..., C 13), computing dot products between the low band-pass or high band-pass filter vector and each group of N lines using fused multiply-add instructions for the core (14A,..., 14N), computing of step C) being performed on several cores (14A,..., 14N), the tile(s) being stored in the operating cache memory which is shared between at two cores or the tile being stored in a central memory of a computer system comprising said cores (14A, 14N). for each core, the operating cache memory comprising a plurality of cache lines, each cache line presenting a predetermined cache line length which is a multiple of the register length; the input data presents a two-dimensional input array formed by a plurality data items stored contiguously in the central memory according to a contiguous direction; the method comprising a step (110; 110') of two-dimensional wavelet transform implemented using a low band-pass filter vector of dimension N and a high band-pass filter vector of dimension N, said step comprising the following sub-steps: A) forming from the input array at least one tile (B 1,..., B 4) comprising a plurality of consecutive data block columns (C 11,..., C 13), each data block column (C 11,..., C 13) being formed by a plurality of lines of consecutive data items according to the contiguous direction, the length of each line being a multiple of the cache line length; C) for the or each tile (B 1,..., B 4), processing each data block column (C 11,..., C 13) and for each data block column (C 11,..., C 13), computing dot products between the low band-pass or high band-pass filter vector and each group of N lines using fused multiply-add instructions for the core (14A,..., 14N), computing of step C) being performed on several cores (14A,..., 14N), the tile(s) being stored in the operating cache memory which is shared between at two cores or the tile being stored in a central memory of a computer system comprising said cores (14A, 14N). A) forming from the input array at least one tile (B 1,..., B 4) comprising a plurality of consecutive data block columns (C 11,..., C 13), each data block column (C 11,..., C 13) being formed by a plurality of lines of consecutive data items according to the contiguous direction, the length of each line being a multiple of the cache line length; C) for the or each tile (B 1,..., B 4), processing each data block column (C 11,..., C 13) and for each data block column (C 11,..., C 13), computing dot products between the low band-pass or high band-pass filter vector and each group of N lines using fused multiply-add instructions for the core (14A,..., 14N), computing of step C) being performed on several cores (14A,..., 14N), the tile(s) being stored in the operating cache memory which is shared between at two cores or the tile being stored in a central memory of a computer system comprising said cores (14A, 14N).