A printed circuit board comprising: a first insulating layer (220, 420, 620); a second insulating layer (225, 425, 625) below the first insulating layer ( 220,420,620); an outer circuit layer (231, 235, 245, 431, 435, 445, 631, 635, 645) on a top surface of the first insulating layer (220,420,620) or a bottom surface of the second insulating layer (225, 425, 625); at least one via (215, 415, 615) formed through the first (220, 420, 620) and second insulating layers (225, 425, 625); and an inner circuit layer (212, 411, 612) buried in the first (220, 420,620) and second insulating layers (225,425,625); wherein the via (215, 415, 615) and the inner circuit layer (212, 411, 612) are made from an etched metal substrate (110, 510); wherein the via (215, 415, 615) includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the first (220, 420, 620) and second insulating layer (225, 425, 625), and the first width is larger than the second width, wherein an upper portion of the inner circuit layer (212, 411, 612) is buried in the first insulating layer ( 220, 420, 620), and an lower portion of the inner circuit layer (212, 411, 612) is buried in the second insulating layer ( 225, 425, 625); wherein a top surface of the via ( 215, 415, 615) is exposed through the top surface of the first insulating layer ( 220, 420, 620), and a bottom surface of the via ( 215, 415, 615) is exposed through the bottom surface of the second insulating layer ( 225, 425, 625); wherein the via ( 215, 415, 615) has a hexagonal sectional shape, and wherein each of the upper and lower portions of the inner circuit layer (212, 411, 612) has a triangular sectional shape. a first insulating layer (220, 420, 620); a second insulating layer (225, 425, 625) below the first insulating layer ( 220,420,620); an outer circuit layer (231, 235, 245, 431, 435, 445, 631, 635, 645) on a top surface of the first insulating layer (220,420,620) or a bottom surface of the second insulating layer (225, 425, 625); at least one via (215, 415, 615) formed through the first (220, 420, 620) and second insulating layers (225, 425, 625); and an inner circuit layer (212, 411, 612) buried in the first (220, 420,620) and second insulating layers (225,425,625); wherein the via (215, 415, 615) includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the first (220, 420, 620) and second insulating layer (225, 425, 625), and the first width is larger than the second width, wherein an upper portion of the inner circuit layer (212, 411, 612) is buried in the first insulating layer ( 220, 420, 620), and an lower portion of the inner circuit layer (212, 411, 612) is buried in the second insulating layer ( 225, 425, 625); wherein a top surface of the via ( 215, 415, 615) is exposed through the top surface of the first insulating layer ( 220, 420, 620), and a bottom surface of the via ( 215, 415, 615) is exposed through the bottom surface of the second insulating layer ( 225, 425, 625); wherein the via ( 215, 415, 615) has a hexagonal sectional shape, and wherein each of the upper and lower portions of the inner circuit layer (212, 411, 612) has a triangular sectional shape.