A data processor, comprising: a plurality of bus masters; a plurality of slaves to which the bus masters can make access; a plurality of relay circuits each of which is coupled to a corresponding one of the bus masters and a corresponding one of the slaves; a ring bus through which the relay circuits are coupled in the shape of a ring; and a monitor circuit which monitors the amount of request packets in the ring bus, wherein the monitor circuit limits request packets to be sent to the relay circuit from the bus master according to the amount of request packets in the ring bus, characterized in that: each relay circuit includes: an arbitration circuit which arbitrates an adjacent request packet being a request packet of an adjacent relay circuit and a bus request packet being a request packet of a nearest bus master with use of priority of the adjacent request packet and priority of the bus request packet, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts the priority of the bus request packet according to the number of the relay circuits through which the bus request packet passes before reaching its destination, and wherein the priority adjustment circuit is so configured as to adjust such that the priority of the bus request packet becomes higher when the number of times the bus request packet is rejected in the arbitration circuit exceeds a predetermine d threshold value, and wherein the predetermined threshold value is set such that the greater the number of the relay circuits through which the bus request packet passes before reaching its destination is, the smaller the predetermined threshold value is. a plurality of bus masters; a plurality of slaves to which the bus masters can make access; a plurality of relay circuits each of which is coupled to a corresponding one of the bus masters and a corresponding one of the slaves; a ring bus through which the relay circuits are coupled in the shape of a ring; and a monitor circuit which monitors the amount of request packets in the ring bus, wherein the monitor circuit limits request packets to be sent to the relay circuit from the bus master according to the amount of request packets in the ring bus, characterized in that: each relay circuit includes: an arbitration circuit which arbitrates an adjacent request packet being a request packet of an adjacent relay circuit and a bus request packet being a request packet of a nearest bus master with use of priority of the adjacent request packet and priority of the bus request packet, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts the priority of the bus request packet according to the number of the relay circuits through which the bus request packet passes before reaching its destination, and wherein the priority adjustment circuit is so configured as to adjust such that the priority of the bus request packet becomes higher when the number of times the bus request packet is rejected in the arbitration circuit exceeds a predetermine d threshold value, and wherein the predetermined threshold value is set such that the greater the number of the relay circuits through which the bus request packet passes before reaching its destination is, the smaller the predetermined threshold value is. each relay circuit includes: an arbitration circuit which arbitrates an adjacent request packet being a request packet of an adjacent relay circuit and a bus request packet being a request packet of a nearest bus master with use of priority of the adjacent request packet and priority of the bus request packet, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts the priority of the bus request packet according to the number of the relay circuits through which the bus request packet passes before reaching its destination, and an arbitration circuit which arbitrates an adjacent request packet being a request packet of an adjacent relay circuit and a bus request packet being a request packet of a nearest bus master with use of priority of the adjacent request packet and priority of the bus request packet, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts the priority of the bus request packet according to the number of the relay circuits through which the bus request packet passes before reaching its destination, and wherein the priority adjustment circuit is so configured as to adjust such that the priority of the bus request packet becomes higher when the number of times the bus request packet is rejected in the arbitration circuit exceeds a predetermine d threshold value, and wherein the predetermined threshold value is set such that the greater the number of the relay circuits through which the bus request packet passes before reaching its destination is, the smaller the predetermined threshold value is.