An array substrate (400, 500) comprising: a first pixel PX(n.n) and a second pixel PX(n, n+1) of a same pixel row and directly neighboring the first pixel PX(n.n) in a gate line direction; the first pixel PX(n,n) comprising a first pixel electrode (491a, 591a) and a first common electrode (491c, 591c) and the second pixel PX(n,n+1) comprising a second pixel electrode (491b, 591b) and a second common electrode (491d, 591d) the first pixel electrode (491a, 591a) forming a first capacitor with a first power line and a second capacitor with a second power line, the first and second power lines (431, 435) being adapted to receive voltages having different polarities, respectively, the first pixel electrode (491a, 591a) being electrically connected to a first data line (471a, Dj); the second pixel electrode (491b, 591b) forming a fourth capacitor with the first power line and a fifth capacitor with the second power line, the second pixel electrode (491b, 591b) being electrically connected to a second data line (471b, Dj+1) being adapted to receive a voltage having an opposite polarity to a voltage applied to the first data line (471a, Dj); the first common electrode (491c, 591c) forming a third capacitor with the second power line, the first common electrode (491c, 591c) being electrically connected to the first power line; and the second common electrode (491d, 591d) forming a sixth capacitor with the first power line, the second common electrode (491d, 591d) being electrically connected to the second power line characterized in that a capacitance of the third capacitor is substantially the same as a sum of capacitances of the first capacitor and the second capacitor, and a capacitance of the sixth capacitor is substantially the same as a sum of capacitances of the fourth capacitor and the fifth capacitor. a first pixel PX(n.n) and a second pixel PX(n, n+1) of a same pixel row and directly neighboring the first pixel PX(n.n) in a gate line direction; the first pixel PX(n,n) comprising a first pixel electrode (491a, 591a) and a first common electrode (491c, 591c) and the second pixel PX(n,n+1) comprising a second pixel electrode (491b, 591b) and a second common electrode (491d, 591d) the first pixel electrode (491a, 591a) forming a first capacitor with a first power line and a second capacitor with a second power line, the first and second power lines (431, 435) being adapted to receive voltages having different polarities, respectively, the first pixel electrode (491a, 591a) being electrically connected to a first data line (471a, Dj); the second pixel electrode (491b, 591b) forming a fourth capacitor with the first power line and a fifth capacitor with the second power line, the second pixel electrode (491b, 591b) being electrically connected to a second data line (471b, Dj+1) being adapted to receive a voltage having an opposite polarity to a voltage applied to the first data line (471a, Dj); the first common electrode (491c, 591c) forming a third capacitor with the second power line, the first common electrode (491c, 591c) being electrically connected to the first power line; and the second common electrode (491d, 591d) forming a sixth capacitor with the first power line, the second common electrode (491d, 591d) being electrically connected to the second power line a capacitance of the third capacitor is substantially the same as a sum of capacitances of the first capacitor and the second capacitor, and a capacitance of the sixth capacitor is substantially the same as a sum of capacitances of the fourth capacitor and the fifth capacitor.