A charge pump for converting a phase and/or frequency difference into a control voltage for a delay locked-loop, DLL, comprising: a first current source component (70.1, 75.1) coupled between a voltage supply and a first output node (80.1); a second current source component (70.2, 75.2) coupled between the voltage supply and a second output node (80.2), a control node of the first current source component being coupled to a control node of the second current source component; and a common mode feedback circuit including a first input coupled to the first output node, a second input coupled to the second output node, and an output coupled to the control nodes of the first and second current source components wherein a first bias current source (78.1) supplies a first adjustable bias current to the first and second output nodes, and a second bias current source (78.2) supplies a second adjustable bias current to the first and second output nodes; wherein the charge pump further comprises: a first switch (74.1, 84.1) coupled between the first bias current source and the first output node; a second switch (74.2, 84.2) coupled between the first bias current source and the second output node; a third switch (76.1, 86.1) coupled between the second bias current source and the first output node; and a fourth switch (76.2, 86.2) coupled between the second bias current source and the second output node; wherein the first bias current includes a fixed current plus a first offset current, and the second bias current includes the fixed current minus a second offset current, wherein the first and second offset currents are tunable; and wherein the first and second switches are controlled by a first pulse received from the first output of a phase frequency detector of a delay locked loop, and the third and fourth switches are controlled by a second pulse received from the second output of the phase frequency detector. a first current source component (70.1, 75.1) coupled between a voltage supply and a first output node (80.1); a second current source component (70.2, 75.2) coupled between the voltage supply and a second output node (80.2), a control node of the first current source component being coupled to a control node of the second current source component; and a common mode feedback circuit including a first input coupled to the first output node, a second input coupled to the second output node, and an output coupled to the control nodes of the first and second current source components wherein a first bias current source (78.1) supplies a first adjustable bias current to the first and second output nodes, and a second bias current source (78.2) supplies a second adjustable bias current to the first and second output nodes; wherein the charge pump further comprises: a first switch (74.1, 84.1) coupled between the first bias current source and the first output node; a second switch (74.2, 84.2) coupled between the first bias current source and the second output node; a third switch (76.1, 86.1) coupled between the second bias current source and the first output node; and a fourth switch (76.2, 86.2) coupled between the second bias current source and the second output node; a first switch (74.1, 84.1) coupled between the first bias current source and the first output node; a second switch (74.2, 84.2) coupled between the first bias current source and the second output node; a third switch (76.1, 86.1) coupled between the second bias current source and the first output node; and a fourth switch (76.2, 86.2) coupled between the second bias current source and the second output node; wherein the first bias current includes a fixed current plus a first offset current, and the second bias current includes the fixed current minus a second offset current, wherein the first and second offset currents are tunable; and wherein the first and second switches are controlled by a first pulse received from the first output of a phase frequency detector of a delay locked loop, and the third and fourth switches are controlled by a second pulse received from the second output of the phase frequency detector.