A coplanar capacitor, comprising: a substrate (103, 303, 903); a voltage-tunable dielectric layer (107, 307, 907, 1207, 1307) over the substrate (103, 303, 903); a plurality of bias lines (109A, 109B, 1209, 1309) over the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307), wherein each of the plurality of bias lines (109A, 109B, 1209, 1309) has vertical sides, and wherein the plurality of bias lines (109A, 109B, 1209, 1309) are covered by an inter-level dielectric (111A, 111B; 311); a plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D), wherein each of the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) is located adjacent a respective vertical side of one of the plurality of bias lines (109A, 109B, 1209, 1309), wherein each of the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) covers a respective portion of the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307), wherein each of the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) spans a respective distance between a top of the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307) and a top of the inter-level dielectric (111A, 111B; 311), and wherein each respective distance includes a full height of the respective vertical side; and metallization over the inter-level dielectric (111A, 111B; 311), the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) and exposed portions of the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307), wherein the metallization (112, 312) forms RF electrodes, and wherein the sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) provide for isolation of the RF electrodes from the bias lines (109A, 109B, 1209, 1309). a substrate (103, 303, 903); a voltage-tunable dielectric layer (107, 307, 907, 1207, 1307) over the substrate (103, 303, 903); a plurality of bias lines (109A, 109B, 1209, 1309) over the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307), wherein each of the plurality of bias lines (109A, 109B, 1209, 1309) has vertical sides, and wherein the plurality of bias lines (109A, 109B, 1209, 1309) are covered by an inter-level dielectric (111A, 111B; 311); a plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D), wherein each of the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) is located adjacent a respective vertical side of one of the plurality of bias lines (109A, 109B, 1209, 1309), wherein each of the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) covers a respective portion of the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307), wherein each of the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) spans a respective distance between a top of the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307) and a top of the inter-level dielectric (111A, 111B; 311), and wherein each respective distance includes a full height of the respective vertical side; and metallization over the inter-level dielectric (111A, 111B; 311), the plurality of sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) and exposed portions of the voltage-tunable dielectric layer (107, 307, 907, 1207, 1307), wherein the metallization (112, 312) forms RF electrodes, and wherein the sidewall spacers (113A, 113B, 113C, 113D; 314A, 314B, 314C, 314D) provide for isolation of the RF electrodes from the bias lines (109A, 109B, 1209, 1309).