A read operation circuit used in a semiconductor memory, wherein the semiconductor memory comprises a Data Queque, DQ, port, a data bus inversion, DBI, port, and a memory bank, the read operation circuit comprising: a DBI encoder connected to the memory bank, wherein the DBI encoder is configured to read data from the memory bank, and determine whether to invert the read data according to a number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, wherein the DBI port is configured to receive the DBI data; a parallel-to-serial conversion circuit connected between the DQ port and the DBI encoder through the global bus and configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer connected to the memory bank through the global bus; and characterized by a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low; the data buffer comprises a plurality of Positive Metal Oxide Semiconductor, PMOS, transistors, a gate of each PMOS transistor being connected to the memory bank, a drain of each PMOS transistor being connected to the global bus; and wherein the precharge module comprises a plurality of Negative Metal Oxide Semiconductor, NMOS, transistors and a plurality of hold circuits, a gate of each NMOS transistor being connected to the precharge signal line, a drain of each of the plurality of NMOS transistors being connected to the global bus, and an input terminal and an output terminal of each hold circuit being connected to the global bus, the hold circuit forming a positive feedback and latching the global bus at a low level. a DBI encoder connected to the memory bank, wherein the DBI encoder is configured to read data from the memory bank, and determine whether to invert the read data according to a number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, wherein the DBI port is configured to receive the DBI data; a parallel-to-serial conversion circuit connected between the DQ port and the DBI encoder through the global bus and configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer connected to the memory bank through the global bus; and characterized by a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low; the data buffer comprises a plurality of Positive Metal Oxide Semiconductor, PMOS, transistors, a gate of each PMOS transistor being connected to the memory bank, a drain of each PMOS transistor being connected to the global bus; and wherein the precharge module comprises a plurality of Negative Metal Oxide Semiconductor, NMOS, transistors and a plurality of hold circuits, a gate of each NMOS transistor being connected to the precharge signal line, a drain of each of the plurality of NMOS transistors being connected to the global bus, and an input terminal and an output terminal of each hold circuit being connected to the global bus, the hold circuit forming a positive feedback and latching the global bus at a low level.