A computer device comprising: a first processor; a plurality of memory circuits: a data bus (DATA), coupling the first processor to each of the memory circuits, wherein each of the memory circuits has a data port with a width of m bits and the data bus has a length of n bits, n being greater than m, the data port of each memory circuit being coupled to a corresponding set of m bits of the data bus, the first processor being adapted to provide one or several addresses for a data value of n bits to be read or written via the data bus into the plurality of memory circuits, the computer device being characterised in that at least a first of the memory circuits comprises at least one other processor capable of: - accessing data words of the first memory circuit, the width m of the data port of the first memory circuit being less than the data word, - and performing operations on the data words; the computer device also being characterised in that the first processor and/or another circuit is configured to read or write the n-bit data value in the first memory circuit; - by converting the first address into a plurality of second addresses corresponding to m-bit memory locations in the first memory circuit, at least two of the second addresses of the plurality of second addresses being contiguous addresses; and - by performing the reading or writing operation of the n-bit data value in the first memory circuit over a plurality of memory access operations. a first processor; a plurality of memory circuits: a data bus (DATA), coupling the first processor to each of the memory circuits, wherein each of the memory circuits has a data port with a width of m bits and the data bus has a length of n bits, n being greater than m, the data port of each memory circuit being coupled to a corresponding set of m bits of the data bus, the first processor being adapted to provide one or several addresses for a data value of n bits to be read or written via the data bus into the plurality of memory circuits, the computer device being characterised in that at least a first of the memory circuits comprises at least one other processor capable of: - accessing data words of the first memory circuit, the width m of the data port of the first memory circuit being less than the data word, - and performing operations on the data words; the computer device also being characterised in that the first processor and/or another circuit is configured to read or write the n-bit data value in the first memory circuit; - by converting the first address into a plurality of second addresses corresponding to m-bit memory locations in the first memory circuit, at least two of the second addresses of the plurality of second addresses being contiguous addresses; and - by performing the reading or writing operation of the n-bit data value in the first memory circuit over a plurality of memory access operations. a data bus (DATA), coupling the first processor to each of the memory circuits, wherein each of the memory circuits has a data port with a width of m bits and the data bus has a length of n bits, n being greater than m, the data port of each memory circuit being coupled to a corresponding set of m bits of the data bus, the first processor being adapted to provide one or several addresses for a data value of n bits to be read or written via the data bus into the plurality of memory circuits, the computer device being characterised in that at least a first of the memory circuits comprises at least one other processor capable of: - accessing data words of the first memory circuit, the width m of the data port of the first memory circuit being less than the data word, - and performing operations on the data words; - accessing data words of the first memory circuit, the width m of the data port of the first memory circuit being less than the data word, - and performing operations on the data words; the computer device also being characterised in that the first processor and/or another circuit is configured to read or write the n-bit data value in the first memory circuit; - by converting the first address into a plurality of second addresses corresponding to m-bit memory locations in the first memory circuit, at least two of the second addresses of the plurality of second addresses being contiguous addresses; and - by performing the reading or writing operation of the n-bit data value in the first memory circuit over a plurality of memory access operations. - by converting the first address into a plurality of second addresses corresponding to m-bit memory locations in the first memory circuit, at least two of the second addresses of the plurality of second addresses being contiguous addresses; and - by performing the reading or writing operation of the n-bit data value in the first memory circuit over a plurality of memory access operations.