A display device, comprising: a display area including pixels coupled to data lines (D1-Dm) and scan lines (S1-Sn); a plurality of test pads (TVP1, TVP2), each test pad (TVP1, TVP2) being configured to receive a test signal; a plurality of first test transistors (TT1, TT2) coupled between the data lines (D1-Dm) of the display area and the plurality of test pads (TVP1, TVP2); at least one test control pad (TP1, TP1-1, TP1-2, TP2-1, TP2-2) coupled to control electrodes of the first test transistors (TT1, TT2); a plurality of initialization transistors (IT1-IT3) coupled between the data lines (D1-Dm) of the display area and pads (IVP1, IVP2, IPV3) to receive initialization signals; a plurality of initialization control pads (IP1-IP3) coupled to control electrodes of the initialization transistors (IT1-IT3); at least one outline (OL1, OL2) coupled between one of the first test transistors (TT1, TT2) and one of the plurality of test pads (TVP1, TVP2), the at least one outline (OL1, OL2) being located in a non-display area outside the display area; wherein the at least one outline (OL1, OL2) traverses a path that is adjacent to the display area, before returning on a substantially parallel path; and characterised in that the display device further comprises: a resistor between at least one of the first test transistors (TT1, TT2) that is not directly coupled to the at least one outline (OL1, OL2) and the one of the plurality of test pads (TVP1, TVP2), wherein the resistance of the resistor is chosen such that a voltage difference between the test signal supplied to one of the first test transistors (TT1, TT2) directly coupled to the at least one outline (OL1, OL2) and the test signal supplied to the one of the first test transistors (TT1, TT2) that is not directly coupled to the at least one outline (OL1, OL2) is minimized. a display area including pixels coupled to data lines (D1-Dm) and scan lines (S1-Sn); a plurality of test pads (TVP1, TVP2), each test pad (TVP1, TVP2) being configured to receive a test signal; a plurality of first test transistors (TT1, TT2) coupled between the data lines (D1-Dm) of the display area and the plurality of test pads (TVP1, TVP2); at least one test control pad (TP1, TP1-1, TP1-2, TP2-1, TP2-2) coupled to control electrodes of the first test transistors (TT1, TT2); a plurality of initialization transistors (IT1-IT3) coupled between the data lines (D1-Dm) of the display area and pads (IVP1, IVP2, IPV3) to receive initialization signals; a plurality of initialization control pads (IP1-IP3) coupled to control electrodes of the initialization transistors (IT1-IT3); at least one outline (OL1, OL2) coupled between one of the first test transistors (TT1, TT2) and one of the plurality of test pads (TVP1, TVP2), the at least one outline (OL1, OL2) being located in a non-display area outside the display area; wherein the at least one outline (OL1, OL2) traverses a path that is adjacent to the display area, before returning on a substantially parallel path; and characterised in that the display device further comprises: a resistor between at least one of the first test transistors (TT1, TT2) that is not directly coupled to the at least one outline (OL1, OL2) and the one of the plurality of test pads (TVP1, TVP2), wherein the resistance of the resistor is chosen such that a voltage difference between the test signal supplied to one of the first test transistors (TT1, TT2) directly coupled to the at least one outline (OL1, OL2) and the test signal supplied to the one of the first test transistors (TT1, TT2) that is not directly coupled to the at least one outline (OL1, OL2) is minimized. a resistor between at least one of the first test transistors (TT1, TT2) that is not directly coupled to the at least one outline (OL1, OL2) and the one of the plurality of test pads (TVP1, TVP2), wherein the resistance of the resistor is chosen such that a voltage difference between the test signal supplied to one of the first test transistors (TT1, TT2) directly coupled to the at least one outline (OL1, OL2) and the test signal supplied to the one of the first test transistors (TT1, TT2) that is not directly coupled to the at least one outline (OL1, OL2) is minimized.