An apparatus comprising: a first voltage domain circuit including a first circuit component configured to provide a first digital output signal, wherein the first voltage domain circuit is configured to receive a first supply voltage and wherein the first digital output signal has high and low states and the voltage of the high state is based on the first supply voltage; a second voltage domain circuit comprising a second circuit component, wherein the second voltage domain circuit is configured to receive a second supply voltage that is greater than the first supply voltage; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based on the first digital output signal with an increased voltage level of the high state, wherein the level shifter arrangement is configured to provide said second digital output signal for input to the second circuit component; wherein the level shifter arrangement comprises a first stage and a second stage; wherein the first stage comprises a first arrangement of one or more diode-connected PMOS transistors (220,222,224), a source terminal of at least one of said one transistors or more diode-connected PMOS transistors configured to couple to the second supply voltage and a drain terminal of at least one of said one or more diode-connected PMOS transistors (220,222,224) coupled to a first CMOS inverter arrangement, the first CMOS inverter arrangement having a first terminal coupled to said drain terminal and a voltage reference terminal for coupling to a voltage reference; and wherein the second stage comprises a second arrangement of one or more diode-connected PMOS transistors (240, 242), a source terminal of at least one of said one or more diode-connected PMOS transistors (240, 242) configured for coupling to the second supply voltage and a drain terminal of at least one of said one or more diode-connected PMOS transistors coupled to a second CMOS inverter arrangement, the second CMOS inverter arrangement having a first terminal coupled to said drain terminal and a voltage reference terminal for coupling to a voltage reference; wherein the first CMOS inverter arrangement is configured to receive the first digital output signal and provide a first intermediate digital output signal to the second CMOS inverter arrangement of the second stage, wherein the second CMOS inverter arrangement is configured to receive the intermediate digital output signal and provide the second digital output signal for the second circuit component; and wherein the first and second arrangements of diode-connected PMOS transistors are configured such that that a voltage drop provided by the first arrangement is greater than the voltage drop provided by the second arrangement. a first voltage domain circuit including a first circuit component configured to provide a first digital output signal, wherein the first voltage domain circuit is configured to receive a first supply voltage and wherein the first digital output signal has high and low states and the voltage of the high state is based on the first supply voltage; a second voltage domain circuit comprising a second circuit component, wherein the second voltage domain circuit is configured to receive a second supply voltage that is greater than the first supply voltage; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based on the first digital output signal with an increased voltage level of the high state, wherein the level shifter arrangement is configured to provide said second digital output signal for input to the second circuit component; wherein the level shifter arrangement comprises a first stage and a second stage; wherein the first stage comprises a first arrangement of one or more diode-connected PMOS transistors (220,222,224), a source terminal of at least one of said one transistors or more diode-connected PMOS transistors configured to couple to the second supply voltage and a drain terminal of at least one of said one or more diode-connected PMOS transistors (220,222,224) coupled to a first CMOS inverter arrangement, the first CMOS inverter arrangement having a first terminal coupled to said drain terminal and a voltage reference terminal for coupling to a voltage reference; and wherein the second stage comprises a second arrangement of one or more diode-connected PMOS transistors (240, 242), a source terminal of at least one of said one or more diode-connected PMOS transistors (240, 242) configured for coupling to the second supply voltage and a drain terminal of at least one of said one or more diode-connected PMOS transistors coupled to a second CMOS inverter arrangement, the second CMOS inverter arrangement having a first terminal coupled to said drain terminal and a voltage reference terminal for coupling to a voltage reference; wherein the first CMOS inverter arrangement is configured to receive the first digital output signal and provide a first intermediate digital output signal to the second CMOS inverter arrangement of the second stage, wherein the second CMOS inverter arrangement is configured to receive the intermediate digital output signal and provide the second digital output signal for the second circuit component; and wherein the first and second arrangements of diode-connected PMOS transistors are configured such that that a voltage drop provided by the first arrangement is greater than the voltage drop provided by the second arrangement.