An apparatus comprising: a memory device comprising an array of memory cells, and configured to operate from a clock signal; erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array; and erase signal generation circuitry configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses; the erase signal generation circuitry being configured to issue said erase signal in said asserted state if the control signal is removed or if the control signal does not take the form of said pulse signal; wherein: said erase signal generation circuitry comprises capacitor circuitry, and output circuitry configured to generate the erase signal in dependence on an output from the capacitor circuitry; the capacitor circuitry being configured to switch between a charging operation and a discharging operation dependent on the control signal; if the control signal is removed or if the control signal does not take the form of said pulse signal, the output from the capacitor circuitry being configured to reach a predetermined activation voltage level, thereby causing the output circuitry to generate said erase signal in said asserted state; and if the control signal takes the form of said pulse signal the output from the capacitor circuitry being configured not to reach said predetermined activation voltage level, thereby causing the erase signal to be maintained in said deasserted state. a memory device comprising an array of memory cells, and configured to operate from a clock signal; erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array; and erase signal generation circuitry configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses; the erase signal generation circuitry being configured to issue said erase signal in said asserted state if the control signal is removed or if the control signal does not take the form of said pulse signal; wherein: said erase signal generation circuitry comprises capacitor circuitry, and output circuitry configured to generate the erase signal in dependence on an output from the capacitor circuitry; the capacitor circuitry being configured to switch between a charging operation and a discharging operation dependent on the control signal; if the control signal is removed or if the control signal does not take the form of said pulse signal, the output from the capacitor circuitry being configured to reach a predetermined activation voltage level, thereby causing the output circuitry to generate said erase signal in said asserted state; and if the control signal takes the form of said pulse signal the output from the capacitor circuitry being configured not to reach said predetermined activation voltage level, thereby causing the erase signal to be maintained in said deasserted state. said erase signal generation circuitry comprises capacitor circuitry, and output circuitry configured to generate the erase signal in dependence on an output from the capacitor circuitry; the capacitor circuitry being configured to switch between a charging operation and a discharging operation dependent on the control signal; if the control signal is removed or if the control signal does not take the form of said pulse signal, the output from the capacitor circuitry being configured to reach a predetermined activation voltage level, thereby causing the output circuitry to generate said erase signal in said asserted state; and if the control signal takes the form of said pulse signal the output from the capacitor circuitry being configured not to reach said predetermined activation voltage level, thereby causing the erase signal to be maintained in said deasserted state.