A semiconductor device (2, 3, 4) having outside electrode terminals on its lower surface, wherein said semiconductor device (2, 3, 4) has: a semiconductor substrate (6a, 6b, 6c); circuit elements formed at a first main surface side of said semiconductor substrate (6a, 6b, 6c); a multilayer wiring part (7a, 7b, 7c) formed on said circuit elements configured by wiring electrically connected with said circuit elements and an insulating layer being alternately stacked; a first insulating layer (8a, 8b, 8c) for covering said insulating layer of the uppermost layer configuring said multilayer wiring part (7a, 7b, 7c), said first insulating layer being provided all over said multilayer wiring part and serving as a supporting member of said semiconductor substrate (6a, 6b, 6c); a second insulating layer (11a, 11b, 11c) for covering a second main surface to become an opposite face against the first main surface of said semiconductor substrate (6a, 6b, 6c); a plurality of post electrodes (9a, 9b, 9c) formed on respective specified wiring of said multilayer wiring part (7a, 7b, 7c) to be exposed in a surface of said first insulating layer (8a, 8b, 8c); a plurality of through-type electrodes (12a, 12b, 12c) provided to pierce through said semiconductor substrate (6a, 6b, 6c) and said second insulating layer (11a, 11b, 11c) from specified depth of said multilayer wiring part (7a, 7b, 7c), brought into contact to said semiconductor substrate (6a, 6b, 6c) through an insulating film and connected with specified wiring of said multilayer wiring part (7a, 7b, 7c) respectively; and said outside electrode terminals connected to said through-type electrodes (12a, 12b, 12c). a semiconductor substrate (6a, 6b, 6c); circuit elements formed at a first main surface side of said semiconductor substrate (6a, 6b, 6c); a multilayer wiring part (7a, 7b, 7c) formed on said circuit elements configured by wiring electrically connected with said circuit elements and an insulating layer being alternately stacked; a first insulating layer (8a, 8b, 8c) for covering said insulating layer of the uppermost layer configuring said multilayer wiring part (7a, 7b, 7c), said first insulating layer being provided all over said multilayer wiring part and serving as a supporting member of said semiconductor substrate (6a, 6b, 6c); a second insulating layer (11a, 11b, 11c) for covering a second main surface to become an opposite face against the first main surface of said semiconductor substrate (6a, 6b, 6c); a plurality of post electrodes (9a, 9b, 9c) formed on respective specified wiring of said multilayer wiring part (7a, 7b, 7c) to be exposed in a surface of said first insulating layer (8a, 8b, 8c); a plurality of through-type electrodes (12a, 12b, 12c) provided to pierce through said semiconductor substrate (6a, 6b, 6c) and said second insulating layer (11a, 11b, 11c) from specified depth of said multilayer wiring part (7a, 7b, 7c), brought into contact to said semiconductor substrate (6a, 6b, 6c) through an insulating film and connected with specified wiring of said multilayer wiring part (7a, 7b, 7c) respectively; and said outside electrode terminals connected to said through-type electrodes (12a, 12b, 12c).