An integrated circuit comprising: a memory array including a first plurality of linearly arranged array blocks (332, 334, 374, 375; 406; 426; 446, 447; 462, 464), each array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) comprising a plurality of word lines (102, 104; 336-338, 342; 360-363) and bit lines (106, 108; 322, 324; 333, 335); a first data bus (373; 402; 412; 442; 466) generally spanning the first plurality of linearly arranged array blocks, each of a first group of the first plurality of array blocks associated with the first data bus (373; 402; 422; 442; 466); a second data bus (378; 404; 424; 444; 468) generally spanning the first plurality of linearly arranged array blocks; CHARACTERISED IN THAT: each of a second group of the first plurality of linearly arranged array blocks associated with the second data bus (378; 404; 424; 444; 468); a row selection circuit (152, 302. 304) configured, in a first mode of operation, to simultaneously select a word line (102, 104; 336-338, 342; 360-363) in a first array block (332, 334, 374, 375; 406, 426; 446, 447; 462, 464) within the first group and a word line (102, 104; 336-338, 342; 360-363) in a second array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) within the second group; and a column selection circuit (202; 312-316; 379, 380) configured, in the first mode of operation, to simultaneously couple one or more selected bit lines (106, 108; 322, 324; 333, 335) in the first array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) to corresponding lines of the first data bus (373; 402; 422; 442; 466) and one or more selected bit lines (106, 108; 322, 324; 333, 335) in the second array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) to corresponding lines of the second data bus (378; 404; 424; 444; 468). a memory array including a first plurality of linearly arranged array blocks (332, 334, 374, 375; 406; 426; 446, 447; 462, 464), each array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) comprising a plurality of word lines (102, 104; 336-338, 342; 360-363) and bit lines (106, 108; 322, 324; 333, 335); a first data bus (373; 402; 412; 442; 466) generally spanning the first plurality of linearly arranged array blocks, each of a first group of the first plurality of array blocks associated with the first data bus (373; 402; 422; 442; 466); a second data bus (378; 404; 424; 444; 468) generally spanning the first plurality of linearly arranged array blocks; CHARACTERISED IN THAT: each of a second group of the first plurality of linearly arranged array blocks associated with the second data bus (378; 404; 424; 444; 468); a row selection circuit (152, 302. 304) configured, in a first mode of operation, to simultaneously select a word line (102, 104; 336-338, 342; 360-363) in a first array block (332, 334, 374, 375; 406, 426; 446, 447; 462, 464) within the first group and a word line (102, 104; 336-338, 342; 360-363) in a second array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) within the second group; and a column selection circuit (202; 312-316; 379, 380) configured, in the first mode of operation, to simultaneously couple one or more selected bit lines (106, 108; 322, 324; 333, 335) in the first array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) to corresponding lines of the first data bus (373; 402; 422; 442; 466) and one or more selected bit lines (106, 108; 322, 324; 333, 335) in the second array block (332, 334, 374, 375; 406; 426; 446, 447; 462, 464) to corresponding lines of the second data bus (378; 404; 424; 444; 468).