A semiconductor device (100, 200, 300), comprising: a first electrode; a second electrode; a silicon carbide layer provided between the first electrode and the second electrode and including a first silicon carbide region of a first conductive type, a second silicon carbide region of a second conductive type provided between the first electrode and the first silicon carbide region, and a third silicon carbide region of the first conductive type provided between the first electrode and the second silicon carbide region; a first gate electrode provided between the first electrode and the silicon carbide layer and extending in a first direction parallel to a surface of the silicon carbide layer; a second gate electrode provided between the first electrode and the silicon carbide layer and extending in the first direction; a third gate electrode provided between the first electrode and the silicon carbide layer and extending in the first direction; a gate wiring line provided between the first electrode and the silicon carbide layer and extending in a second direction crossing the first direction, the second direction being parallel to the surface, the first gate electrode, the second gate electrode, and the third gate electrode being connected to the gate wiring line; and a gate insulating layer provided between the first gate electrode and the silicon carbide layer, between the second gate electrode and the silicon carbide layer, and between the third gate electrode and the silicon carbide layer, wherein, assuming that a distance between the first gate electrode and the second gate electrode in the second direction in a first region is S1, a distance between the first gate electrode and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, a distance between the second gate electrode and the third gate electrode in the second direction in the first region is S3, and a distance between the second gate electrode and the third gate electrode in the second direction in the second region is S4, following Expression 1, Expression 2, Expression 3, and Expression 4 are satisfied, and the first gate electrode, the second gate electrode, and the third gate electrode are connected to the gate wiring line in the second region, S 1 < S 3, which corresponds to Expression 1 S 1 < S 2, which corresponds to Expression 2 S 3 > S 4, which corresponds to Expression 3 S 1 < S 4, which corresponds to Expression 4. a first electrode; a second electrode; a silicon carbide layer provided between the first electrode and the second electrode and including a first silicon carbide region of a first conductive type, a second silicon carbide region of a second conductive type provided between the first electrode and the first silicon carbide region, and a third silicon carbide region of the first conductive type provided between the first electrode and the second silicon carbide region; a first gate electrode provided between the first electrode and the silicon carbide layer and extending in a first direction parallel to a surface of the silicon carbide layer; a second gate electrode provided between the first electrode and the silicon carbide layer and extending in the first direction; a third gate electrode provided between the first electrode and the silicon carbide layer and extending in the first direction; a gate wiring line provided between the first electrode and the silicon carbide layer and extending in a second direction crossing the first direction, the second direction being parallel to the surface, the first gate electrode, the second gate electrode, and the third gate electrode being connected to the gate wiring line; and a gate insulating layer provided between the first gate electrode and the silicon carbide layer, between the second gate electrode and the silicon carbide layer, and between the third gate electrode and the silicon carbide layer, wherein, assuming that a distance between the first gate electrode and the second gate electrode in the second direction in a first region is S1, a distance between the first gate electrode and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, a distance between the second gate electrode and the third gate electrode in the second direction in the first region is S3, and a distance between the second gate electrode and the third gate electrode in the second direction in the second region is S4, following Expression 1, Expression 2, Expression 3, and Expression 4 are satisfied, and the first gate electrode, the second gate electrode, and the third gate electrode are connected to the gate wiring line in the second region, S 1 < S 3, which corresponds to Expression 1 S 1 < S 2, which corresponds to Expression 2 S 3 > S 4, which corresponds to Expression 3 S 1 < S 4, which corresponds to Expression 4.