A three-dimensional memory device (100, 300), comprising: a first semiconductor structure (102, 302) comprising a peripheral circuit, an array of embedded dynamic random-access memory (DRAM) cells, and a first bonding layer comprising a plurality of first bonding contacts; a second semiconductor structure (104, 304) comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts; and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface, wherein the first semiconductor structure (102, 302) comprises: a substrate; the peripheral circuit directly on the substrate; the array of embedded DRAM cells directly on the substrate and outside of the peripheral circuit; and the first bonding layer above the peripheral circuit and the array of embedded DRAM cells, wherein the second semiconductor structure (104, 304) comprises: the second bonding layer above the first bonding layer; a memory stack above the second bonding layer; the array of 3D NAND memory strings extending vertically through the memory stack; characterized by a semiconductor layer above and in contact with the array of 3D NAND memory strings, wherein the semiconductor layer includes isolation regions and doped regions. a first semiconductor structure (102, 302) comprising a peripheral circuit, an array of embedded dynamic random-access memory (DRAM) cells, and a first bonding layer comprising a plurality of first bonding contacts; a second semiconductor structure (104, 304) comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts; and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface, wherein the first semiconductor structure (102, 302) comprises: a substrate; the peripheral circuit directly on the substrate; the array of embedded DRAM cells directly on the substrate and outside of the peripheral circuit; and the first bonding layer above the peripheral circuit and the array of embedded DRAM cells, wherein the second semiconductor structure (104, 304) comprises: the second bonding layer above the first bonding layer; a memory stack above the second bonding layer; the array of 3D NAND memory strings extending vertically through the memory stack; characterized by a semiconductor layer above and in contact with the array of 3D NAND memory strings, wherein the semiconductor layer includes isolation regions and doped regions. a substrate; the peripheral circuit directly on the substrate; the array of embedded DRAM cells directly on the substrate and outside of the peripheral circuit; and the first bonding layer above the peripheral circuit and the array of embedded DRAM cells, wherein the second semiconductor structure (104, 304) comprises: the second bonding layer above the first bonding layer; a memory stack above the second bonding layer; the array of 3D NAND memory strings extending vertically through the memory stack; characterized by a semiconductor layer above and in contact with the array of 3D NAND memory strings, wherein the semiconductor layer includes isolation regions and doped regions. the second bonding layer above the first bonding layer; a memory stack above the second bonding layer; the array of 3D NAND memory strings extending vertically through the memory stack; characterized by a semiconductor layer above and in contact with the array of 3D NAND memory strings, wherein the semiconductor layer includes isolation regions and doped regions.