A display device comprising: a timing controller adapted to receive a reset signal and a first logic voltage, and adapted to be turned on to a floating state by the first logic voltage during which the timing controller outputs unstable timing control signals and, after a switching period (Tc), to be switched from the floating state to a normal operating state by the reset signal to generate timing control signals (Tsig); a level shifter adapted to receive the first logic voltage and a second logic voltage and adapted to level-shift the timing control signals (Tsig) to the second logic voltage and to output the same, wherein the display device is adapted to apply the first logic voltage and the second logic voltage such that the timing of application of the second logic voltage at a second ON level corresponding to a start of the switching period (Tc) is a certain amount of time (Tx) preceding the timing of application of the first logic voltage at a first ON level and, after the switching period (Tc), apply the reset signal at a third ON level such that the switching period lasts from the applying the second logic voltage at the second ON level until applying the reset signal at the third ON level, wherein the level shifter is adapted to receive an output enable signal and stop the level shifting and outputting of the timing control signals (Tsig) in response to the output enable signal of disable level HIGH, and start the level shifting and outputting of the timing control signals (Tsig) in response to the output enable signal of enable level LOW; and an output enable signal control part adapted to output the output enable signal at enable level LOW or disable level HIGH, depending on the reset signal, such that during the switching period (Tc), the output enable signal is at disable level HIGH, and after completion of the switching period (Tc), the output enable signal is at enable level LOW. a timing controller adapted to receive a reset signal and a first logic voltage, and adapted to be turned on to a floating state by the first logic voltage during which the timing controller outputs unstable timing control signals and, after a switching period (Tc), to be switched from the floating state to a normal operating state by the reset signal to generate timing control signals (Tsig); a level shifter adapted to receive the first logic voltage and a second logic voltage and adapted to level-shift the timing control signals (Tsig) to the second logic voltage and to output the same, wherein the display device is adapted to apply the first logic voltage and the second logic voltage such that the timing of application of the second logic voltage at a second ON level corresponding to a start of the switching period (Tc) is a certain amount of time (Tx) preceding the timing of application of the first logic voltage at a first ON level and, after the switching period (Tc), apply the reset signal at a third ON level such that the switching period lasts from the applying the second logic voltage at the second ON level until applying the reset signal at the third ON level, wherein the level shifter is adapted to receive an output enable signal and stop the level shifting and outputting of the timing control signals (Tsig) in response to the output enable signal of disable level HIGH, and start the level shifting and outputting of the timing control signals (Tsig) in response to the output enable signal of enable level LOW; and an output enable signal control part adapted to output the output enable signal at enable level LOW or disable level HIGH, depending on the reset signal, such that during the switching period (Tc), the output enable signal is at disable level HIGH, and after completion of the switching period (Tc), the output enable signal is at enable level LOW.