A stacked die assembly for integrated circuit dies of an integrated circuit device, comprising: a first interposer formed on a wafer, the first interposer having a first offset region which is a part of an interconnect restricted area, the first offset region having a first boundary that is coterminous with a first edge of the first interposer; a second interposer formed on the wafer and severed from the first interposer, the second interposer having a second offset region which is a part of the interconnect restricted area, the second offset region having a second boundary that is coterminous with a second edge of the second interposer, wherein the first edge of the first interposer and the second edge of the second interposer are positioned substantially side by side for abutting one another and the interconnect restricted area has interconnects but does not have fine pitch interconnects; a first integrated circuit die mounted on and interconnected to the first interposer and the second interposer via fine pitch interconnects (715, 1315); a second integrated circuit die mounted on and interconnected to the second interposer via fine pitch interconnects (715, 1315); and the fine pitch interconnects being located outside the interconnect restricted area of the first interposer and the second interposer; wherein signals are routed between the first interposer and the second interposer via the first integrated circuit die and the fine pitch interconnects, and signals are routed between the first integrated circuit die and the second integrated circuit die via a plurality of conductive lines of the second interposer which are outside of the second offset region; and some of fine pitch interconnects (715, 1315) are coupled to connectors (711, 1330) on an opposite side of the first and second interposers (500A, 500B) via through-substrate vias (712, 1335), some of the through substrate vias (712, 1335) extending through the first interposer and some of the through substrate vias (712, 1335) extending through the second interposer, wherein the connectors (711, 1330) are larger than the fine pitch interconnects (715, 1315) and the interconnect density of the fine pitch interconnects (715, 1315) is greater that that of the connectors (711, 1330). a first interposer formed on a wafer, the first interposer having a first offset region which is a part of an interconnect restricted area, the first offset region having a first boundary that is coterminous with a first edge of the first interposer; a second interposer formed on the wafer and severed from the first interposer, the second interposer having a second offset region which is a part of the interconnect restricted area, the second offset region having a second boundary that is coterminous with a second edge of the second interposer, wherein the first edge of the first interposer and the second edge of the second interposer are positioned substantially side by side for abutting one another and the interconnect restricted area has interconnects but does not have fine pitch interconnects; a first integrated circuit die mounted on and interconnected to the first interposer and the second interposer via fine pitch interconnects (715, 1315); a second integrated circuit die mounted on and interconnected to the second interposer via fine pitch interconnects (715, 1315); and the fine pitch interconnects being located outside the interconnect restricted area of the first interposer and the second interposer; wherein signals are routed between the first interposer and the second interposer via the first integrated circuit die and the fine pitch interconnects, and signals are routed between the first integrated circuit die and the second integrated circuit die via a plurality of conductive lines of the second interposer which are outside of the second offset region; and some of fine pitch interconnects (715, 1315) are coupled to connectors (711, 1330) on an opposite side of the first and second interposers (500A, 500B) via through-substrate vias (712, 1335), some of the through substrate vias (712, 1335) extending through the first interposer and some of the through substrate vias (712, 1335) extending through the second interposer, wherein the connectors (711, 1330) are larger than the fine pitch interconnects (715, 1315) and the interconnect density of the fine pitch interconnects (715, 1315) is greater that that of the connectors (711, 1330).