An electronic device, comprising: a housing; a display; a communication circuit including a plurality of circuit lines; an antenna assistant device connected to the communication circuit; a printed circuit board, PCB, arranged between a lower portion of the display and a bottom of the housing; wherein the PCB includes: multiple layers; a wiring area, in which the communication circuit including the plurality of circuit lines is arranged, a fill cut area, in which no circuit line is formed and the antenna assistant device connected to the communication circuit is arranged; wherein the wiring area and the fill cut area are coplanar and extend each through the multiple layers of the PCB; and wherein the antenna assistant device comprises: a first conductive pattern comprising stacked capacitor substrates, wherein at least first sides of the stacked capacitor substrates are configured to be connected to an antenna (172, 174), and at least second sides opposite the first sides of the stacked capacitor substrates are configured to be connected to a feeder; a second conductive pattern disposed at a lower or upper portion of the first conductive pattern, wherein one side of the second conductive pattern is configured to be connected to the feeder and another side of the second conductive pattern opposite the one side is configured to be connected to a ground; and a conductive plate disposed between the first conductive pattern and the second conductive pattern, wherein each of the first conductive pattern, the second conductive pattern, and the conductive plate is defined by a metal layer of the PCB. a housing; a display; a communication circuit including a plurality of circuit lines; an antenna assistant device connected to the communication circuit; a printed circuit board, PCB, arranged between a lower portion of the display and a bottom of the housing; wherein the PCB includes: multiple layers; a wiring area, in which the communication circuit including the plurality of circuit lines is arranged, a fill cut area, in which no circuit line is formed and the antenna assistant device connected to the communication circuit is arranged; multiple layers; a wiring area, in which the communication circuit including the plurality of circuit lines is arranged, a fill cut area, in which no circuit line is formed and the antenna assistant device connected to the communication circuit is arranged; wherein the wiring area and the fill cut area are coplanar and extend each through the multiple layers of the PCB; and wherein the antenna assistant device comprises: a first conductive pattern comprising stacked capacitor substrates, wherein at least first sides of the stacked capacitor substrates are configured to be connected to an antenna (172, 174), and at least second sides opposite the first sides of the stacked capacitor substrates are configured to be connected to a feeder; a second conductive pattern disposed at a lower or upper portion of the first conductive pattern, wherein one side of the second conductive pattern is configured to be connected to the feeder and another side of the second conductive pattern opposite the one side is configured to be connected to a ground; and a conductive plate disposed between the first conductive pattern and the second conductive pattern, wherein each of the first conductive pattern, the second conductive pattern, and the conductive plate is defined by a metal layer of the PCB. a first conductive pattern comprising stacked capacitor substrates, wherein at least first sides of the stacked capacitor substrates are configured to be connected to an antenna (172, 174), and at least second sides opposite the first sides of the stacked capacitor substrates are configured to be connected to a feeder; a second conductive pattern disposed at a lower or upper portion of the first conductive pattern, wherein one side of the second conductive pattern is configured to be connected to the feeder and another side of the second conductive pattern opposite the one side is configured to be connected to a ground; and a conductive plate disposed between the first conductive pattern and the second conductive pattern, wherein each of the first conductive pattern, the second conductive pattern, and the conductive plate is defined by a metal layer of the PCB.