Testing device for testing at least one first control device, wherein the testing device comprises at least: a first computing unit for executing a model code, wherein by means of the model code a simulated controlled system signal for stimulating the control device can be provided and an actuator signal of the control device can be processed, and a first time signal converter unit having at least (i) a first time signal interface for receiving a first time signal from a global time signal source, and (ii) a changeover signal transmission unit arranged to transmit a first changeover signal to a first multiplexers, the first multiplexer is enclosed by the testing device, and (iii) a first clock transmission unit arranged to generate a first periodic clock signal from the first time signal and to output the first periodic clock signal to a first PLL comprised by the testing device, and wherein the testing device further comprises: (a) a first oscillator arranged to generate a second periodic clock signal and to output the second periodic clock signal to a second PLL, the second PLL is included in the testing device; and (b) a first watch which, on the one hand, is connected to the first multiplexer by means of a clock signal line and, on the other hand, is arranged to forward a first clock signal to a first input/output unit and/or to the first computing unit, wherein a first multiplexer input of the first multiplexer is connected to a first PLL output of the first PLL for transmitting a first frequency stabilized clock signal in the direction of the first multiplexer, and wherein a second multiplexer input of the first multiplexer is connected to a second PLL output of the second PLL for transmitting a second frequency stabilized clock signal in the direction of the first multiplexer, and wherein the first switch-over signal is provided in order to thereby control the first multiplexer in such a way that, depending on a state of the switch-over signal, either the first frequency-stabilized clock signal or the second frequency-stabilized clock signal can be forwarded to the first watch by means of the first multiplexer, and wherein the first watch is set up, in order to process either the first frequency-stabilized clock signal or the second frequency-stabilized clock signal to generate the first clock signal, depending on the state of the changeover signal, the first computing unit and/or the first input/output unit being set up to combine the first clock signal with calculated data of the first computing unit and/or with data received via the input/output interfaces of the first input/output unit. (a) a first oscillator arranged to generate a second periodic clock signal and to output the second periodic clock signal to a second PLL, the second PLL is included in the testing device; and (b) a first watch which, on the one hand, is connected to the first multiplexer by means of a clock signal line and, on the other hand, is arranged to forward a first clock signal to a first input/output unit and/or to the first computing unit, wherein a first multiplexer input of the first multiplexer is connected to a first PLL output of the first PLL for transmitting a first frequency stabilized clock signal in the direction of the first multiplexer, and wherein a second multiplexer input of the first multiplexer is connected to a second PLL output of the second PLL for transmitting a second frequency stabilized clock signal in the direction of the first multiplexer, and wherein the first switch-over signal is provided in order to thereby control the first multiplexer in such a way that, depending on a state of the switch-over signal, either the first frequency-stabilized clock signal or the second frequency-stabilized clock signal can be forwarded to the first watch by means of the first multiplexer, and wherein the first watch is set up, in order to process either the first frequency-stabilized clock signal or the second frequency-stabilized clock signal to generate the first clock signal, depending on the state of the changeover signal, the first computing unit and/or the first input/output unit being set up to combine the first clock signal with calculated data of the first computing unit and/or with data received via the input/output interfaces of the first input/output unit.