A memory system (400, 500), comprising: an array of memory cells arranged in rows and columns; a row decoder for receiving a row address component and asserting one of a plurality of word lines comprising 32 or more word lines, each word line coupled to a row in the array; and a hierarchical ROM encoder system (411, 511), comprising: a first ROM encoder (401, 501) for receiving the plurality of word lines and generating a first output; a first logic block (403, 502) for receiving the plurality of word lines and generating a plurality of first logic block outputs, the first logic block comprising a plurality of logic gates, each logic gate being connected to a plurality of word lines and generating a corresponding first logic block output; a second ROM encoder (402, 503) for receiving the plurality of first logic block outputs and generating a second output, the second ROM encoder comprising a plurality of rows, each row associated with one of the plurality of first logic block outputs; a first comparator (404, 506) for comparing the first output and a first part of the row address component; a second comparator (405, 507) for comparing the second output and a second part of the row address component; and a gate (406, 509) for generating a row address fault detection signal based on an output from the first comparator and an output from the second comparator. an array of memory cells arranged in rows and columns; a row decoder for receiving a row address component and asserting one of a plurality of word lines comprising 32 or more word lines, each word line coupled to a row in the array; and a hierarchical ROM encoder system (411, 511), comprising: a first ROM encoder (401, 501) for receiving the plurality of word lines and generating a first output; a first logic block (403, 502) for receiving the plurality of word lines and generating a plurality of first logic block outputs, the first logic block comprising a plurality of logic gates, each logic gate being connected to a plurality of word lines and generating a corresponding first logic block output; a second ROM encoder (402, 503) for receiving the plurality of first logic block outputs and generating a second output, the second ROM encoder comprising a plurality of rows, each row associated with one of the plurality of first logic block outputs; a first comparator (404, 506) for comparing the first output and a first part of the row address component; a second comparator (405, 507) for comparing the second output and a second part of the row address component; and a gate (406, 509) for generating a row address fault detection signal based on an output from the first comparator and an output from the second comparator. a first ROM encoder (401, 501) for receiving the plurality of word lines and generating a first output; a first logic block (403, 502) for receiving the plurality of word lines and generating a plurality of first logic block outputs, the first logic block comprising a plurality of logic gates, each logic gate being connected to a plurality of word lines and generating a corresponding first logic block output; a second ROM encoder (402, 503) for receiving the plurality of first logic block outputs and generating a second output, the second ROM encoder comprising a plurality of rows, each row associated with one of the plurality of first logic block outputs; a first comparator (404, 506) for comparing the first output and a first part of the row address component; a second comparator (405, 507) for comparing the second output and a second part of the row address component; and a gate (406, 509) for generating a row address fault detection signal based on an output from the first comparator and an output from the second comparator.