A spike timing dependent plasticity, STDP, function cell having an STDP function for a neuromorphic circuit, the STDP function cell comprising: a synapse comprising: a memory device having a variable resistance; a transistor connected to the memory device; a first synapse terminal; and a second synapse terminal; a pre-synaptic neuron connected to the memory device through the first synapse terminal of the synapse; and a post-synaptic neuron connected to a source terminal of the transistor through the second synapse terminal of the synapse, wherein a channel of the memory device is connected in series with a channel of the transistor, characterized in that the pre-synaptic neuron and the post-synaptic neuron each comprise: an electronic neuron circuit configured to fire a spike; a spike time recorder configured to record a point of time when the electronic neuron circuit fires the spike as a digital code; and a pulse shaper configured to restore a pulse shape of the spike based on the digital code; wherein the spike time recorder and the pulse shaper are configured to operate in synchronization with a clock; and in that the STDP function cell is configured to selectively operate in a communication mode in which the synapse transmits information from the pre-synaptic neuron to the post-synaptic neuron, and a learning mode in which a synaptic weight of the synapse changes in response to a voltage difference of the pulse shapers, whereby said voltage difference is applied to both a first terminal and a second terminal of the memory device, wherein the STDP function cell is configured to switch between the communication mode and the learning mode according to a time division multiplexing scheme. a synapse comprising: a memory device having a variable resistance; a transistor connected to the memory device; a first synapse terminal; and a second synapse terminal; a memory device having a variable resistance; a transistor connected to the memory device; a first synapse terminal; and a second synapse terminal; a pre-synaptic neuron connected to the memory device through the first synapse terminal of the synapse; and a post-synaptic neuron connected to a source terminal of the transistor through the second synapse terminal of the synapse, wherein a channel of the memory device is connected in series with a channel of the transistor, the pre-synaptic neuron and the post-synaptic neuron each comprise: an electronic neuron circuit configured to fire a spike; a spike time recorder configured to record a point of time when the electronic neuron circuit fires the spike as a digital code; and a pulse shaper configured to restore a pulse shape of the spike based on the digital code; an electronic neuron circuit configured to fire a spike; a spike time recorder configured to record a point of time when the electronic neuron circuit fires the spike as a digital code; and a pulse shaper configured to restore a pulse shape of the spike based on the digital code; wherein the spike time recorder and the pulse shaper are configured to operate in synchronization with a clock; and in that the STDP function cell is configured to selectively operate in a communication mode in which the synapse transmits information from the pre-synaptic neuron to the post-synaptic neuron, and a learning mode in which a synaptic weight of the synapse changes in response to a voltage difference of the pulse shapers, whereby said voltage difference is applied to both a first terminal and a second terminal of the memory device, wherein the STDP function cell is configured to switch between the communication mode and the learning mode according to a time division multiplexing scheme.