A semiconductor product, comprising: a semiconductor wafer having a semiconductive substrate and a first surface and a second surface, the first and second surfaces disposed on opposite sides of the substrate, the semiconductor wafer having a thickness between the first surface and the second surface of between 2 to 50 micrometer; a carrier wafer attached to the semiconductor wafer, the first surface of the semiconductor wafer facing the carrier wafer; at least one dielectric layer disposed on the first surface; at least one wiring embedded in the dielectric layer; at least one via hole formed in the substrate extending from the second surface to the at least one wiring; an electrically conductive path coupled to the wiring and extending through the via hole to the second surface of the semiconductor wafer; at least one deep trench (146a, 146b) filled with dielectric that extends from the second surface of the semiconductor wafer to the bottom of at least one shallow trench formed in the substrate extending from the first surface filled with an insulating material (101a, 101b); a super junction laterally diffused MOS transistor having a gate electrode disposed at the first surface of the semiconductor wafer, a source doping region and a drain doping region disposed in the substrate adjacent to the first surface and a plurality of n-doped regions and p-doped regions establishing a drift region disposed in alternating sequence adjacent to one another between the source doping region and the drain doping region, wherein the plurality of n-doped and p-doped regions is disposed at the first surface of the semiconductor wafer and reaches the second surface of the semiconductor wafer; a CMOS circuit including a doping region other than the at least one doping region (602, 603, 605); at least one deep trench (146a, 146b) filled with dielectric formed in the substrate extending from the second surface to the insulating material (101a, 101b) filled in the at least one shallow trench; wherein the at least one deep trench (146a, 146b) is filled with an insulating material to form a barrier between the at least one doping region (602, 603, 605) and the CMOS circuit; and a silicon dioxide disposed on the second surface of the semiconductor wafer. a semiconductor wafer having a semiconductive substrate and a first surface and a second surface, the first and second surfaces disposed on opposite sides of the substrate, the semiconductor wafer having a thickness between the first surface and the second surface of between 2 to 50 micrometer; a carrier wafer attached to the semiconductor wafer, the first surface of the semiconductor wafer facing the carrier wafer; at least one dielectric layer disposed on the first surface; at least one wiring embedded in the dielectric layer; at least one via hole formed in the substrate extending from the second surface to the at least one wiring; an electrically conductive path coupled to the wiring and extending through the via hole to the second surface of the semiconductor wafer; at least one deep trench (146a, 146b) filled with dielectric that extends from the second surface of the semiconductor wafer to the bottom of at least one shallow trench formed in the substrate extending from the first surface filled with an insulating material (101a, 101b); a super junction laterally diffused MOS transistor having a gate electrode disposed at the first surface of the semiconductor wafer, a source doping region and a drain doping region disposed in the substrate adjacent to the first surface and a plurality of n-doped regions and p-doped regions establishing a drift region disposed in alternating sequence adjacent to one another between the source doping region and the drain doping region, wherein the plurality of n-doped and p-doped regions is disposed at the first surface of the semiconductor wafer and reaches the second surface of the semiconductor wafer; a CMOS circuit including a doping region other than the at least one doping region (602, 603, 605); at least one deep trench (146a, 146b) filled with dielectric formed in the substrate extending from the second surface to the insulating material (101a, 101b) filled in the at least one shallow trench; wherein the at least one deep trench (146a, 146b) is filled with an insulating material to form a barrier between the at least one doping region (602, 603, 605) and the CMOS circuit; and a silicon dioxide disposed on the second surface of the semiconductor wafer.