A method for routing victim traffic in a cache coherent distributed shared memory multi-processor comprising: a first processor node connected to a second processor node by a low bandwidth coherent link; a third processor node (12 0) connected to the first processor node by a first high bandwidth coherent link and connected to the second processor node by a second high bandwidth coherent link; a plurality of memory caches, including at least a first memory cache coupled to the first processor node, a second memory cache coupled to the second processor node and a third memory cache coupled to the third processor node, wherein victim traffic is data evicted from at least one of the plurality of memory caches; monitoring victim traffic and non-victim traffic between nodes of a processor; wherein each of the processor nodes comprise: a plurality of compute units (105, 106, 107) connected to a cross bar switch, the cross bar switch configured to control traffic sent from the compute units to a designated link; characterized by the method comprising: selecting, by a compute unit of the first processor node by setting a control register having a defined routing scheme that determines the designated link, a routing scheme for the victim traffic that utilizes the high bandwidth coherent links between the nodes and a routing scheme for the non-victim traffic that utilizes the low bandwidth coherent link between the nodes. a first processor node connected to a second processor node by a low bandwidth coherent link; a third processor node (12 0) connected to the first processor node by a first high bandwidth coherent link and connected to the second processor node by a second high bandwidth coherent link; a plurality of memory caches, including at least a first memory cache coupled to the first processor node, a second memory cache coupled to the second processor node and a third memory cache coupled to the third processor node, wherein victim traffic is data evicted from at least one of the plurality of memory caches; monitoring victim traffic and non-victim traffic between nodes of a processor; wherein each of the processor nodes comprise: a plurality of compute units (105, 106, 107) connected to a cross bar switch, the cross bar switch configured to control traffic sent from the compute units to a designated link; characterized by the method comprising: selecting, by a compute unit of the first processor node by setting a control register having a defined routing scheme that determines the designated link, a routing scheme for the victim traffic that utilizes the high bandwidth coherent links between the nodes and a routing scheme for the non-victim traffic that utilizes the low bandwidth coherent link between the nodes. a plurality of compute units (105, 106, 107) connected to a cross bar switch, the cross bar switch configured to control traffic sent from the compute units to a designated link; characterized by the method comprising: selecting, by a compute unit of the first processor node by setting a control register having a defined routing scheme that determines the designated link, a routing scheme for the victim traffic that utilizes the high bandwidth coherent links between the nodes and a routing scheme for the non-victim traffic that utilizes the low bandwidth coherent link between the nodes.