An oscillator circuit comprising: a tank circuit comprising an inductor (420, 421); comprising a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit, the discretely switchable capacitance module having a first capacitor serially coupled between a first node and a second node; a serial coupling of an PMOS FET between the second node and a third node, the PMOS FET having a gate configured to receive a constant bias voltage; a first DC-feed circuit having a first end coupled to the second node and a second end configured to receive a HI voltage or a LO voltage; and a second DC-feed circuit, having a first end coupled to a fourth node and a second end configured to receive the HI voltage or the LO voltage; and wherein the serial coupling of the PMOS FET between the second node and the third node further comprises the fourth node serially coupled between the PMOS FET and the third node and a second capacitor serially coupled between the third node and the fourth node such that when the HI voltage is applied to the second end of the first DC feed circuit and the second end of the second DC feed circuit, the first capacitor is coupled between the first node and the third node via the PMOS FET and the second capacitor is coupled between the second node and the third node via the PMOS FET such that the serial combination of the first and the second capacitor is coupled in parallel with the inductor of the tank circuit, and when the LO voltage is applied to the second end of the first DC feed circuit and the second end of the second DC feed circuit the serial combination of the first and the second capacitor is not coupled in parallel with the inductor; wherein output signals of the oscillator circuit are prevented to pass from the first node or the second node to the HI or LO voltages through the first or the second capacitor respectively; characterised in that the bias voltage is half of the HI voltage. a tank circuit comprising an inductor (420, 421); comprising a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit, the discretely switchable capacitance module having a first capacitor serially coupled between a first node and a second node; a serial coupling of an PMOS FET between the second node and a third node, the PMOS FET having a gate configured to receive a constant bias voltage; a first DC-feed circuit having a first end coupled to the second node and a second end configured to receive a HI voltage or a LO voltage; and a second DC-feed circuit, having a first end coupled to a fourth node and a second end configured to receive the HI voltage or the LO voltage; and a first capacitor serially coupled between a first node and a second node; a serial coupling of an PMOS FET between the second node and a third node, the PMOS FET having a gate configured to receive a constant bias voltage; a first DC-feed circuit having a first end coupled to the second node and a second end configured to receive a HI voltage or a LO voltage; and a second DC-feed circuit, having a first end coupled to a fourth node and a second end configured to receive the HI voltage or the LO voltage; wherein the serial coupling of the PMOS FET between the second node and the third node further comprises the fourth node serially coupled between the PMOS FET and the third node and a second capacitor serially coupled between the third node and the fourth node such that when the HI voltage is applied to the second end of the first DC feed circuit and the second end of the second DC feed circuit, the first capacitor is coupled between the first node and the third node via the PMOS FET and the second capacitor is coupled between the second node and the third node via the PMOS FET such that the serial combination of the first and the second capacitor is coupled in parallel with the inductor of the tank circuit, and when the LO voltage is applied to the second end of the first DC feed circuit and the second end of the second DC feed circuit the serial combination of the first and the second capacitor is not coupled in parallel with the inductor; wherein output signals of the oscillator circuit are prevented to pass from the first node or the second node to the HI or LO voltages through the first or the second capacitor respectively; characterised in that the bias voltage is half of the HI voltage.