A method for forming a semiconductor device comprising a first field-effect transistor, FET, device and a second FET device, the method comprising: forming, on a semiconductor substrate, a first transistor structure and a second transistor structure separated by a first trench, the first trench comprising a first dielectric wall protruding above a top surface of the transistor structures, wherein each of the first and the second transistor structures comprises a plurality of stacked nanosheets (102a-b) forming a channel structure, and a source portion and a drain portion horizontally separated by said channel structure, and wherein forming said first dielectric wall comprises: forming spacers in the first trench at sidewalls of the first source/drain portion of the first transistor structure and of the first source/drain portion of the second transistor structure, said spacers protruding above a top surface of the transistor structures; forming the first dielectric wall in the first trench between said spacers; and removing said spacers; and the method further comprising: depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure; and etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure. forming, on a semiconductor substrate, a first transistor structure and a second transistor structure separated by a first trench, the first trench comprising a first dielectric wall protruding above a top surface of the transistor structures, wherein each of the first and the second transistor structures comprises a plurality of stacked nanosheets (102a-b) forming a channel structure, and a source portion and a drain portion horizontally separated by said channel structure, and wherein forming said first dielectric wall comprises: forming spacers in the first trench at sidewalls of the first source/drain portion of the first transistor structure and of the first source/drain portion of the second transistor structure, said spacers protruding above a top surface of the transistor structures; forming the first dielectric wall in the first trench between said spacers; and removing said spacers; forming spacers in the first trench at sidewalls of the first source/drain portion of the first transistor structure and of the first source/drain portion of the second transistor structure, said spacers protruding above a top surface of the transistor structures; forming the first dielectric wall in the first trench between said spacers; and removing said spacers; and the method further comprising: depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure; and etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure. depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure; and etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.