A sense amplifier, comprising: a first power input terminal, a second power input terminal, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor, wherein a source of the first PMOS transistor and a source of the second PMOS transistor are connected to the first power input terminal of the sense amplifier; a drain of the first PMOS transistor and a gate of the second PMOS transistor are connected to a sensing bitline (SABL); a gate of the first PMOS transistor and a drain of the second PMOS transistor are connected to a complementary sensing bitline (SABLB); a first terminal of the first switch transistor is connected to the sensing bitline (SABL), a second terminal of the first switch transistor is connected to the complementary sensing bitline (SABLB), and a control terminal of the first switch transistor is connected to an equalization control signal; a first terminal of the second switch transistor is connected to a complementary bitline, a second terminal of the second switch transistor is connected to the sensing bitline (SABL), and a control terminal of the second switch transistor is connected to a first control signal; a first terminal of the third switch transistor is connected to a bitline, a second terminal of the third switch transistor is connected to the complementary sensing bitline (SABLB), and a control terminal of the third switch transistor is connected to a second control signal; a first terminal of the fourth switch transistor is connected to the sensing bitline (SABL), a second terminal of the fourth switch transistor is connected to a drain of the first NMOS transistor, and a control terminal of the fourth switch transistor is connected to a third control signal; a first terminal of the fifth switch transistor is connected to the complementary sensing bitline (SABLB), a second terminal of the fifth switch transistor is connected to a drain of the second NMOS transistor, and a control terminal of the fifth switch transistor is connected to a fourth control signal; and a source of the first NMOS transistor and a source of the second NMOS transistor are connected to the second power input terminal of the sense amplifier; a gate of the first NMOS transistor is connected to the bitline, and a gate of the second NMOS transistor is connected to the complementary bitline. a source of the first PMOS transistor and a source of the second PMOS transistor are connected to the first power input terminal of the sense amplifier; a drain of the first PMOS transistor and a gate of the second PMOS transistor are connected to a sensing bitline (SABL); a gate of the first PMOS transistor and a drain of the second PMOS transistor are connected to a complementary sensing bitline (SABLB); a first terminal of the first switch transistor is connected to the sensing bitline (SABL), a second terminal of the first switch transistor is connected to the complementary sensing bitline (SABLB), and a control terminal of the first switch transistor is connected to an equalization control signal; a first terminal of the second switch transistor is connected to a complementary bitline, a second terminal of the second switch transistor is connected to the sensing bitline (SABL), and a control terminal of the second switch transistor is connected to a first control signal; a first terminal of the third switch transistor is connected to a bitline, a second terminal of the third switch transistor is connected to the complementary sensing bitline (SABLB), and a control terminal of the third switch transistor is connected to a second control signal; a first terminal of the fourth switch transistor is connected to the sensing bitline (SABL), a second terminal of the fourth switch transistor is connected to a drain of the first NMOS transistor, and a control terminal of the fourth switch transistor is connected to a third control signal; a first terminal of the fifth switch transistor is connected to the complementary sensing bitline (SABLB), a second terminal of the fifth switch transistor is connected to a drain of the second NMOS transistor, and a control terminal of the fifth switch transistor is connected to a fourth control signal; and a source of the first NMOS transistor and a source of the second NMOS transistor are connected to the second power input terminal of the sense amplifier; a gate of the first NMOS transistor is connected to the bitline, and a gate of the second NMOS transistor is connected to the complementary bitline.