An apparatus comprising: one or more processor cores, wherein at least one of the one or more processor cores is configured to implement, with hardware support for memory management, a virtual machine environment for executing guest software; a first translation table base register to store a first base address, the first base address to reference a first table of a first multilevel memory address translation stage, the first multilevel memory address translation stage to provide a mapping of a virtual address to a guest physical address, wherein the first table of the first multilevel memory address translation stage is stored in physical memory; and a second translation table base register to store a second base address, the second base address to reference a first table of a second multilevel memory address translation stage (555, 565, 575), the second multilevel memory address translation stage to provide a mapping of the guest physical address to a physical address; wherein the first table of the second multilevel memory address translation stage (555, 565, 575) is stored in physical memory and is to store access information for content stored at the physical address, the access information including at least one: read access control information, write access control information, and execute access control information; wherein the at least one of the one or more processor cores is configured to validate that memory access is permitted to the physical address based on the access information stored in the first table of the second multilevel memory address translation stage (555, 565, 575). one or more processor cores, wherein at least one of the one or more processor cores is configured to implement, with hardware support for memory management, a virtual machine environment for executing guest software; a first translation table base register to store a first base address, the first base address to reference a first table of a first multilevel memory address translation stage, the first multilevel memory address translation stage to provide a mapping of a virtual address to a guest physical address, wherein the first table of the first multilevel memory address translation stage is stored in physical memory; and a second translation table base register to store a second base address, the second base address to reference a first table of a second multilevel memory address translation stage (555, 565, 575), the second multilevel memory address translation stage to provide a mapping of the guest physical address to a physical address; wherein the first table of the second multilevel memory address translation stage (555, 565, 575) is stored in physical memory and is to store access information for content stored at the physical address, the access information including at least one: read access control information, write access control information, and execute access control information; wherein the at least one of the one or more processor cores is configured to validate that memory access is permitted to the physical address based on the access information stored in the first table of the second multilevel memory address translation stage (555, 565, 575). read access control information, write access control information, and execute access control information; wherein the at least one of the one or more processor cores is configured to validate that memory access is permitted to the physical address based on the access information stored in the first table of the second multilevel memory address translation stage (555, 565, 575).