A general purpose graphics processing unit, GPGPU, comprising: two or more parallel processing units (42A-42D) configured to operate selectively as stages of a processing pipeline; one or more local memory buffers (44A-44C), each of the buffers connected between at least two of the parallel processing units, configured to hold data for transfer between the parallel processing units, wherein each the one or more local memory buffers is directly connected between the at least two of the parallel processing units in the processing pipeline; and, a control unit configured to configure the two or more parallel processing units to operate selectively as stages of the processing pipeline, configure one or more of the parallel processing units to send data to the one or more local memory buffers, and configure one or more of the parallel processing units to receive data from the one or more local memory buffers, wherein the control unit preserves data sequence within the processing pipeline, and wherein the control unit is configured to: execute a sequence-determining counter upon entry of a data set to at least one of the parallel processing units to record a sequence of data threads of the data set; and execute a sequence-enforcing barrier upon exit of the data set from the at least one of the parallel processing units to release the data threads of the data set from the parallel processing unit in the same sequence as recorded by the sequence-determining counter. two or more parallel processing units (42A-42D) configured to operate selectively as stages of a processing pipeline; one or more local memory buffers (44A-44C), each of the buffers connected between at least two of the parallel processing units, configured to hold data for transfer between the parallel processing units, wherein each the one or more local memory buffers is directly connected between the at least two of the parallel processing units in the processing pipeline; and, a control unit configured to configure the two or more parallel processing units to operate selectively as stages of the processing pipeline, configure one or more of the parallel processing units to send data to the one or more local memory buffers, and configure one or more of the parallel processing units to receive data from the one or more local memory buffers, wherein the control unit preserves data sequence within the processing pipeline, and wherein the control unit is configured to: execute a sequence-determining counter upon entry of a data set to at least one of the parallel processing units to record a sequence of data threads of the data set; and execute a sequence-enforcing barrier upon exit of the data set from the at least one of the parallel processing units to release the data threads of the data set from the parallel processing unit in the same sequence as recorded by the sequence-determining counter. execute a sequence-determining counter upon entry of a data set to at least one of the parallel processing units to record a sequence of data threads of the data set; and execute a sequence-enforcing barrier upon exit of the data set from the at least one of the parallel processing units to release the data threads of the data set from the parallel processing unit in the same sequence as recorded by the sequence-determining counter.