A driving device (10A; 10) driving a solid-state image pickup device, comprising at least one driving circuit (20A-1, 20A-1,..., 20A-8) and a control circuit producing a control signal to control said driving circuit, characterized in that said driving circuit (20A-i) comprises: first through N-th selective operation driving portions selectively producing first through N-th selective operation driving signals, where N represents an integer which is not less than two, an n-th selective operation driving portion including M x 2 (n-1) P-channel FETs connected in parallel with each other and M x 2 (n-1) N-channel FETs connected in parallel with each other, where M represents an integer which is not less than one and n represents each of 1 through N, said M x 2 (n-1) P-channel FETs having drains connected to drains of said M x 2 (n-1) N-channel FETs; a selection circuit (251 P-258P, 251 N-258N) selectively driving said first through N-th selective operation driving portions in response to the control signal; and a supplying arrangement combining the first through the N-th selective operation driving signals by connecting outputs of the first through the N-th selective operation driving portions to supply a combined driving signal (DOUTi) to said solid-state image pickup device, wherein said control circuit comprises a command decoder producing, in response to an external command (CMD DATA), as the control signal, first through N-th selection signals (CHiD0-CHiD7, CHiD0L-CHiD7L), wherein said selection circuit comprises first through N-th selection circuit portions (251P-258P, 251N-258N) selectively driving said first through said N-th selective operation driving portions in response to the first through the N-th selection signals (CHiD0-CHiD7, CHiD0L-CHiD7L), respectively, wherein said driving device (10A; 10) receives, as an input signal, a pair of opposite phase input signals (DINPi, DINNi) having opposite phases with each other, wherein respective P-channel FETs (221 P-228P) constituting said first through said N-th selective operation driving portions have sources which are supplied with a first power supply voltage (VHHi), wherein respective N-channel FETs (221 N-228N) constituting said first through said N-th selective operation driving portions have sources which are supplied with a second power supply voltage (VLLi) lower than the first power supply voltage, wherein said driving circuit (20A-i; 20-i) comprises a logic level generation circuit generating first and second logic input signals having inverse logic levels each other on the basis of the pair of opposite phase signals (DINPi, DINNi), wherein said command decoder produces, as the first through the N-th selection signals, first through N-th positive selection signals (CHiD0-CHiD7) and first through N-th negative selection signals (CHiD0L-CHiD7L) having reverse polarity with each other in order to select said first through said N-th selective operation driving portions, respectively, wherein an n-th selection circuit portion comprises: an n-th selection operation NAND gate NANDing the first logic input signal and an n-th positive selection signal (CHiD(n-1)) to supply an n-th selection operation NANDed result to gates of said M x 2 (n-1) P-channel FETs; and an n-th selection operation AND gate ANDing the second logic input signal and an n-th negative selection signal (CHiD(n-1)L) to supply an n-th selection operation ANDed result to gates of said M x 2 (n-1) N-channel FETs. first through N-th selective operation driving portions selectively producing first through N-th selective operation driving signals, where N represents an integer which is not less than two, an n-th selective operation driving portion including M x 2 (n-1) P-channel FETs connected in parallel with each other and M x 2 (n-1) N-channel FETs connected in parallel with each other, where M represents an integer which is not less than one and n represents each of 1 through N, said M x 2 (n-1) P-channel FETs having drains connected to drains of said M x 2 (n-1) N-channel FETs; a selection circuit (251 P-258P, 251 N-258N) selectively driving said first through N-th selective operation driving portions in response to the control signal; and a supplying arrangement combining the first through the N-th selective operation driving signals by connecting outputs of the first through the N-th selective operation driving portions to supply a combined driving signal (DOUTi) to said solid-state image pickup device, an n-th selection operation NAND gate NANDing the first logic input signal and an n-th positive selection signal (CHiD(n-1)) to supply an n-th selection operation NANDed result to gates of said M x 2 (n-1) P-channel FETs; and an n-th selection operation AND gate ANDing the second logic input signal and an n-th negative selection signal (CHiD(n-1)L) to supply an n-th selection operation ANDed result to gates of said M x 2 (n-1) N-channel FETs.