A cyclic redundancy check, CRC, circuit comprising: a first shift register to a p-th (p is a natural number greater than 1) shift register (SRp) which each have one stage or a plurality of stages connected in cascade, and in which an inputted signal is delayed and then outputted from the one stage or the plurality of stages, and in which the output of a signal from the one stage or the plurality of stages is performed in synchronization with a clock signal; a first exclusive OR circuit (EXOR1) to a (p-1)th exclusive OR circuit (EXOR(p-1)) each calculating an exclusive OR of two inputted signals; and a switching circuit to which a data signal, a select signal, and an output of a last stage of the p-th shift register (SRp) are inputted, and which switches one of a first signal or a second signal to be outputted in response to the select signal, whereiri an output of the switching circuit is inputted to a first stage of the first shift register, wherein an output of a last stage of an r-th (r is a natural number smaller than p) shift register (SRr), and the output of the switching circuit are inputted to an r-th exclusive OR circuit (EXORr), and an output of the r-th exclusive OR circuit (EXORr) is inputted to a first stage of a (r+1)th shift register (SR(r+1)), wherein the switching circuit comprises: an exclusive OR circuit to which the data signal and the output of the last stage of the p-th shift register (SRp) are inputted; and a selector which is configured to output an output of the exclusive OR circuit as the first signal or to output the data signal as the second signal in response to the select signal, wherein the second signal is a logical value of "0"; and wherein the CRC circuit is configured to switch between a first case wherein the data signal is a received data signal and wherein a CRC code is calculated and output in parallel by the CRC circuit; and a second case wherein by the CRC circuit a) the CRC code is calculated when the data signal is a transmitted data signal and b) the CRC code that has been calculated when the data signal was the transmitted data signal is output serially when the selector outputs the data signal as the second signal. a first shift register to a p-th (p is a natural number greater than 1) shift register (SRp) which each have one stage or a plurality of stages connected in cascade, and in which an inputted signal is delayed and then outputted from the one stage or the plurality of stages, and in which the output of a signal from the one stage or the plurality of stages is performed in synchronization with a clock signal; a first exclusive OR circuit (EXOR1) to a (p-1)th exclusive OR circuit (EXOR(p-1)) each calculating an exclusive OR of two inputted signals; and a switching circuit to which a data signal, a select signal, and an output of a last stage of the p-th shift register (SRp) are inputted, and which switches one of a first signal or a second signal to be outputted in response to the select signal, whereiri an output of the switching circuit is inputted to a first stage of the first shift register, wherein an output of a last stage of an r-th (r is a natural number smaller than p) shift register (SRr), and the output of the switching circuit are inputted to an r-th exclusive OR circuit (EXORr), and an output of the r-th exclusive OR circuit (EXORr) is inputted to a first stage of a (r+1)th shift register (SR(r+1)), wherein the switching circuit comprises: an exclusive OR circuit to which the data signal and the output of the last stage of the p-th shift register (SRp) are inputted; and a selector which is configured to output an output of the exclusive OR circuit as the first signal or to output the data signal as the second signal in response to the select signal, an exclusive OR circuit to which the data signal and the output of the last stage of the p-th shift register (SRp) are inputted; and a selector which is configured to output an output of the exclusive OR circuit as the first signal or to output the data signal as the second signal in response to the select signal, wherein the second signal is a logical value of "0"; and wherein the CRC circuit is configured to switch between a first case wherein the data signal is a received data signal and wherein a CRC code is calculated and output in parallel by the CRC circuit; and a second case wherein by the CRC circuit a) the CRC code is calculated when the data signal is a transmitted data signal and b) the CRC code that has been calculated when the data signal was the transmitted data signal is output serially when the selector outputs the data signal as the second signal.