A memory system comprising: an array of memory cells arranged in rows and columns; a first set of word-lines, wherein each of the first set of the word-lines is coupled to a first plurality of memory cells in at least one row; a first set of bit-lines, wherein each of the first set of the bit-lines is coupled to a second plurality of memory cells in at least one column; wherein each of the first plurality of the memory cells and each of the second plurality of the memory cells comprises: at least one memory storage element comprising at least one magnetic Josephson junction comprising itself at least one magnetic barrier layer configured to be in either a first state or a second state in response to an application of a word-line current, via the at least one of the first set of the word-lines, to the at least one magnetic Josephson junction, the at least one memory storage element further comprising at least two Josephson junctions (212, 214) and an inductor coupled to the at least one magnetic Josephson junction to form a latching superconducting quantum interference device, SQUID; and at least one inductive-shunt (360, 370, 380, 390, 685, 695) coupled in parallel to the at least one memory cell, wherein the memory system is further configured to perform a read operation on the at least one memory storage element in response to an application of a bit-line current to the at least one of the first set of the bit-lines, the at least one inductive-shunt being configured to, after the read operation, remove at least a portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the at least one of the first set of the bit-lines during the read operation, such that the portion of the bit-line current removed by the at least one inductive-shunt is sufficient to turn-off the latching SQUID within the at least one memory cell. an array of memory cells arranged in rows and columns; a first set of word-lines, wherein each of the first set of the word-lines is coupled to a first plurality of memory cells in at least one row; a first set of bit-lines, wherein each of the first set of the bit-lines is coupled to a second plurality of memory cells in at least one column; wherein each of the first plurality of the memory cells and each of the second plurality of the memory cells comprises: at least one memory storage element comprising at least one magnetic Josephson junction comprising itself at least one magnetic barrier layer configured to be in either a first state or a second state in response to an application of a word-line current, via the at least one of the first set of the word-lines, to the at least one magnetic Josephson junction, the at least one memory storage element further comprising at least two Josephson junctions (212, 214) and an inductor coupled to the at least one magnetic Josephson junction to form a latching superconducting quantum interference device, SQUID; and at least one inductive-shunt (360, 370, 380, 390, 685, 695) coupled in parallel to the at least one memory cell, wherein the memory system is further configured to perform a read operation on the at least one memory storage element in response to an application of a bit-line current to the at least one of the first set of the bit-lines, the at least one inductive-shunt being configured to, after the read operation, remove at least a portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the at least one of the first set of the bit-lines during the read operation, such that the portion of the bit-line current removed by the at least one inductive-shunt is sufficient to turn-off the latching SQUID within the at least one memory cell. at least one memory storage element comprising at least one magnetic Josephson junction comprising itself at least one magnetic barrier layer configured to be in either a first state or a second state in response to an application of a word-line current, via the at least one of the first set of the word-lines, to the at least one magnetic Josephson junction, the at least one memory storage element further comprising at least two Josephson junctions (212, 214) and an inductor coupled to the at least one magnetic Josephson junction to form a latching superconducting quantum interference device, SQUID; and at least one inductive-shunt (360, 370, 380, 390, 685, 695) coupled in parallel to the at least one memory cell, wherein the memory system is further configured to perform a read operation on the at least one memory storage element in response to an application of a bit-line current to the at least one of the first set of the bit-lines, the at least one inductive-shunt being configured to, after the read operation, remove at least a portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the at least one of the first set of the bit-lines during the read operation, such that the portion of the bit-line current removed by the at least one inductive-shunt is sufficient to turn-off the latching SQUID within the at least one memory cell.