A peak detector circuit comprising: - a first switching device having a collector terminal, an emitter terminal, and a control terminal; - a second switching device having a collector terminal, an emitter terminal, and a control terminal; - a third switching device having a collector terminal, an emitter terminal, and a control terminal; - a fourth switching device having a collector terminal, an emitter terminal and a control terminal; - a first load having a first terminal and a second terminal, said first terminal of said first load being connected to ground; - a second load having a first terminal and a second terminal, said first terminal of said second load being connected to ground; - a third load having a first terminal and a second terminal, said first terminal of said third load being connected to a supply voltage node; - a fourth load having a first terminal and a second terminal, said first terminal of said fourth load being connected to said supply voltage node; - a first output (vsigB) coupled to said second terminal of said first load and coupled to both the emitter terminals of said first and second switching devices (51,52); - a second output (vrefB) coupled to said second terminal of said second load and coupled to both emitter terminals of said third and fourth switching devices (53,54); - a third output (vsigT) coupled to said second terminal of said third load and coupled to both collector terminals of said first and second switching devices (51,52); - a fourth output (vrefT) coupled to said second terminal of said fourth load, and coupled to both collector terminals of said third and fourth switching devices (53,54), where said control terminals of said first and second switching devices (51,52) are arranged to receive a differential input voltage (vin,vinp), whereby said control terminals of said first, second, third, and fourth switching devices (51, 52, 53 and 54) are arranged to be biased with a common DC bias voltage (vb), so that the DC biasing term from the output can be fully compensated, and whereby said first, second, third and fourth load are selected so that: R 1 = R 2 = α ⁢ f * R 3 = α ⁢ f * R 4, with R1, R2, R3, R4 a resistance of said first, second, third and fourth load, respectively, and αf a common-base current gain of said switching devices (51,52,53,54). - a first switching device having a collector terminal, an emitter terminal, and a control terminal; - a second switching device having a collector terminal, an emitter terminal, and a control terminal; - a third switching device having a collector terminal, an emitter terminal, and a control terminal; - a fourth switching device having a collector terminal, an emitter terminal and a control terminal; - a first load having a first terminal and a second terminal, said first terminal of said first load being connected to ground; - a second load having a first terminal and a second terminal, said first terminal of said second load being connected to ground; - a third load having a first terminal and a second terminal, said first terminal of said third load being connected to a supply voltage node; - a fourth load having a first terminal and a second terminal, said first terminal of said fourth load being connected to said supply voltage node; - a first output (vsigB) coupled to said second terminal of said first load and coupled to both the emitter terminals of said first and second switching devices (51,52); - a second output (vrefB) coupled to said second terminal of said second load and coupled to both emitter terminals of said third and fourth switching devices (53,54); - a third output (vsigT) coupled to said second terminal of said third load and coupled to both collector terminals of said first and second switching devices (51,52); - a fourth output (vrefT) coupled to said second terminal of said fourth load, and coupled to both collector terminals of said third and fourth switching devices (53,54),