A method for programming in a memory device, comprising: programming selected memory cells (MCO, MCI, 500, 510, 520, 532, 533, 534, 705-709) connected to a selected word line (WLn) of a set of word lines (524, WLL0-WLL22), wherein memory cells connected to the set of word lines are arranged in NAND strings (NSO to NS0-14; NS0A to NS0A-14; NS0 to NS5; NS1A to NS5A; NS0 to NS3), and each NAND string comprises a charge-trapping layer (403, 504, 514, 521) which extends continuously in the NAND string; the selected memory cells are programmed to a plurality of target data states, and memory cells which are to remain in an erased state are also connected to the selected word line, the programming is performed by performing a plurality of program-verify iterations for the selected word line, each program-verify iteration of the plurality of program-verify iterations is performed by applying a program voltage (PP1-PP10) followed by performing a verify test for one or more target data states of the plurality of target data states, and the program voltage is stepped up in each of the plurality of program-verify iterations; and during each program voltage application, applying a first pass voltage (Vpass1, 1040-1042, 1050-1054, 1060-1066) to a word line (WLn+1) in the set of word lines which is adjacent to the selected word line and after the selected word line in a word line programming order, while applying a second pass voltage (Vpass2, 1043, 1055, 1073-1076) to a word line (WLn-1) in the set of word lines which is adjacent to the selected word line and before the selected word line in a word line programming order, wherein during one or more initial program-verify iterations of the plurality of program-verify iterations, the first pass voltage exceeds the second pass voltage (1043, 1055, 1067, 1073, 1075) by a difference, the first pass voltage becomes progressively smaller during subsequent program-verify iterations of the plurality of program-verify iterations, and the difference becomes progressively smaller during the subsequent program-verify iterations, characterised in that: the difference by which the first pass voltage exceeds the second pass voltage is at least as high as a difference between a verify voltage (VvC) of a highest target data state of the plurality of target data states and a verify voltage (VvA) of a lowest target data state of the plurality of target data states, and; the second pass voltage becomes progressively smaller during the subsequent program-verify iterations of the plurality of program-verify iterations. programming selected memory cells (MCO, MCI, 500, 510, 520, 532, 533, 534, 705-709) connected to a selected word line (WLn) of a set of word lines (524, WLL0-WLL22), wherein memory cells connected to the set of word lines are arranged in NAND strings (NSO to NS0-14; NS0A to NS0A-14; NS0 to NS5; NS1A to NS5A; NS0 to NS3), and each NAND string comprises a charge-trapping layer (403, 504, 514, 521) which extends continuously in the NAND string; the selected memory cells are programmed to a plurality of target data states, and memory cells which are to remain in an erased state are also connected to the selected word line, the programming is performed by performing a plurality of program-verify iterations for the selected word line, each program-verify iteration of the plurality of program-verify iterations is performed by applying a program voltage (PP1-PP10) followed by performing a verify test for one or more target data states of the plurality of target data states, and the program voltage is stepped up in each of the plurality of program-verify iterations; and during each program voltage application, applying a first pass voltage (Vpass1, 1040-1042, 1050-1054, 1060-1066) to a word line (WLn+1) in the set of word lines which is adjacent to the selected word line and after the selected word line in a word line programming order, while applying a second pass voltage (Vpass2, 1043, 1055, 1073-1076) to a word line (WLn-1) in the set of word lines which is adjacent to the selected word line and before the selected word line in a word line programming order, wherein during one or more initial program-verify iterations of the plurality of program-verify iterations, the first pass voltage exceeds the second pass voltage (1043, 1055, 1067, 1073, 1075) by a difference, the first pass voltage becomes progressively smaller during subsequent program-verify iterations of the plurality of program-verify iterations, and the difference becomes progressively smaller during the subsequent program-verify iterations, characterised in that: the difference by which the first pass voltage exceeds the second pass voltage is at least as high as a difference between a verify voltage (VvC) of a highest target data state of the plurality of target data states and a verify voltage (VvA) of a lowest target data state of the plurality of target data states, and; the second pass voltage becomes progressively smaller during the subsequent program-verify iterations of the plurality of program-verify iterations. the difference by which the first pass voltage exceeds the second pass voltage is at least as high as a difference between a verify voltage (VvC) of a highest target data state of the plurality of target data states and a verify voltage (VvA) of a lowest target data state of the plurality of target data states, and; the second pass voltage becomes progressively smaller during the subsequent program-verify iterations of the plurality of program-verify iterations.