A display apparatus comprising a pixel array and a driver (103, 104, 105) configured to drive the pixel array, said pixel array having scanning lines (WSL101... WSL10m) as rows, signal lines (DTL101... DTL10n) as columns, a matrix of pixels disposed at respective intersections of said scanning lines and said signal lines, and power supply lines (DSL101... DSL10m) disposed along respective rows of said pixels, said driver having a main scanner configured to supply control signals to said scanning lines, a power supply scanner configured to supply a first potential (Vcc_H) and a second potential (Vcc_L) to said power supply lines, and a signal selector configured to supply a signal potential (Vin), which serves as a video signal, and a reference potential (Vo) to said signal lines, each of said pixels including a light-emitting device, a sampling transistor, a drive transistor, and a retention capacitor, said sampling transistor having a gate, a source, and a drain, said gate being connected to one of said scanning lines, either one of said source and said drain being connected to one of said signal lines, and the other of said source and said drain being connected to the gate of said drive transistor, said drive transistor having a source and a drain, either one of which is connected to said light-emitting device and the other connected to one of said power supply lines, said retention capacitor having one end connected to the gate of said drive transistor and having its other end connected to the one of said source and said drain of the drive transistor connected to said light-emitting device, wherein the main scanner is arranged to render said sampling transistor conductive by supplying a control signal to the associated one of said scanning lines, said power supply scanner is arranged, after the sampling transistor has been rendered conductive by supplying the control signal to the associated one of said scanning lines and following an initialization period in which the signal selector is controlled to supply the reference potential (Vo) to the associated one of said signal lines so that the gate potential of the drive transistor is reset to the reference potential (Vo), to perform a first switch to switch the power supply line from said first potential to said second potential and subsequently to perform a second switch to switch the power supply line from said second potential back to said first potential; said signal selector is arranged to supply the reference potential to said signal line throughout the period between said first switch and said second switch, the second potential being lower than the reference potential by at least the threshold voltage of the drive transistor; after the second switch, during a threshold correcting period the power supply line is maintained at said first potential, and the signal line is maintained at said reference potential to enable the one of the source and the drain of the drive transistor connected to said light-emitting device to reach a potential such that a voltage which essentially corresponds to the threshold voltage of said drive transistor is retained in said retention capacitor; and said signal selector being controlled, after the threshold correcting period, to switch said signal line from the reference potential to the signal potential; wherein the signal selector is configured to switch the signal line from the reference potential to the signal potential at a first timing after the sampling transistor is rendered conductive, the main scanner is configured to stop applying the control signal to the scanning line at a second timing after the first timing, thereby rendering the sampling transistor nonconductive, and the period between the first timing and the second timing is appropriately set to correct the signal potential as it is retained in the retention capacitor with respect to the mobility of the drive transistor; and wherein the signal selector is configured to apply a gradient to a positive-going edge of the video signal which switches from the reference potential to the signal potential for thereby allowing the period between the first timing and the second timing to be shorter when the signal potential is higher and the period between the first timing and the second timing to be longer when the signal potential is lower.