A SRAM memory unit comprising: a plurality of memory cells, each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b); a pre-charge circuit configured to provide a voltage for charging the bit lines (130a, 130b); and a multiplexer circuit comprising: for each bit line (130a, 130b), an associated switch that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit when activated by a corresponding bit line selection signal, the switch consisting of an NMOS device (142a, 142b) and characterised in that a multiplexer controller that is configured to be able to separately select each pair of bit lines (130a, 130b) by activating the associated switch NMOS devices (142a, 142b) using the corresponding bit line selection signals, and that is configured to select all of the pairs of bit lines connected to the data input and output circuitry simultaneously when pre-charging the bit lines (130a, 130b) such that all of the bit lines (130a, 130b) connected to the data input and output circuitry are pre-charged concurrently via the NMOS devices (142a, 142b). a plurality of memory cells, each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b); a pre-charge circuit configured to provide a voltage for charging the bit lines (130a, 130b); and a multiplexer circuit comprising: for each bit line (130a, 130b), an associated switch that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit when activated by a corresponding bit line selection signal, the switch consisting of an NMOS device (142a, 142b) and characterised in that a multiplexer controller that is configured to be able to separately select each pair of bit lines (130a, 130b) by activating the associated switch NMOS devices (142a, 142b) using the corresponding bit line selection signals, and that is configured to select all of the pairs of bit lines connected to the data input and output circuitry simultaneously when pre-charging the bit lines (130a, 130b) such that all of the bit lines (130a, 130b) connected to the data input and output circuitry are pre-charged concurrently via the NMOS devices (142a, 142b). for each bit line (130a, 130b), an associated switch that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit when activated by a corresponding bit line selection signal, the switch consisting of an NMOS device (142a, 142b) and characterised in that a multiplexer controller that is configured to be able to separately select each pair of bit lines (130a, 130b) by activating the associated switch NMOS devices (142a, 142b) using the corresponding bit line selection signals, and that is configured to select all of the pairs of bit lines connected to the data input and output circuitry simultaneously when pre-charging the bit lines (130a, 130b) such that all of the bit lines (130a, 130b) connected to the data input and output circuitry are pre-charged concurrently via the NMOS devices (142a, 142b).