A register renaming recover circuit in a processor (104, 802) configured to: receive a flush indicator indicating a flush of one or more instructions in the processor (104, 802) based on an interrupting instruction that caused the flush of the one or more instructions in the processor (104, 802); receive an interrupting instruction indicator indicating a position of an interrupting instruction entry allocated to the interrupting instruction in a reorder buffer in the processor (104, 802); determine a position of an oldest flushed instruction entry (OF_PTR, 138) allocated for an oldest instruction of the one or more instructions indicated to flush based on the interrupting instruction indicator; and traverse the reorder buffer in the processor (104, 802) in a first direction wherein the first direction is either from the position of the oldest flushed instruction entry (OF_PTR, 138) to an oldest instruction entry in the reorder buffer or from the position of the oldest flushed instruction entry (OF_PRT, 138) to a youngest instruction entry in the reorder buffer by being configured to: determine if a first instruction allocated to a first instruction entry in the reorder buffer in the first direction resulted in a logical register-to-physical register mapping in a map entry of a register mapping table in the processor (104, 802); and in response to determining the first instruction allocated to the first instruction entry in the reorder buffer in the first direction resulted in a logical register-to-physical register mapping in a map entry of the register mapping table in the processor (104, 802) recover the logical register-to-physical register mapping of the map entry in the register mapping table to a previous logical register-to-physical register mapping prior to the oldest instruction of the one or more instructions indicated to flush. receive a flush indicator indicating a flush of one or more instructions in the processor (104, 802) based on an interrupting instruction that caused the flush of the one or more instructions in the processor (104, 802); receive an interrupting instruction indicator indicating a position of an interrupting instruction entry allocated to the interrupting instruction in a reorder buffer in the processor (104, 802); determine a position of an oldest flushed instruction entry (OF_PTR, 138) allocated for an oldest instruction of the one or more instructions indicated to flush based on the interrupting instruction indicator; and traverse the reorder buffer in the processor (104, 802) in a first direction wherein the first direction is either from the position of the oldest flushed instruction entry (OF_PTR, 138) to an oldest instruction entry in the reorder buffer or from the position of the oldest flushed instruction entry (OF_PRT, 138) to a youngest instruction entry in the reorder buffer by being configured to: determine if a first instruction allocated to a first instruction entry in the reorder buffer in the first direction resulted in a logical register-to-physical register mapping in a map entry of a register mapping table in the processor (104, 802); and in response to determining the first instruction allocated to the first instruction entry in the reorder buffer in the first direction resulted in a logical register-to-physical register mapping in a map entry of the register mapping table in the processor (104, 802) recover the logical register-to-physical register mapping of the map entry in the register mapping table to a previous logical register-to-physical register mapping prior to the oldest instruction of the one or more instructions indicated to flush. determine if a first instruction allocated to a first instruction entry in the reorder buffer in the first direction resulted in a logical register-to-physical register mapping in a map entry of a register mapping table in the processor (104, 802); and in response to determining the first instruction allocated to the first instruction entry in the reorder buffer in the first direction resulted in a logical register-to-physical register mapping in a map entry of the register mapping table in the processor (104, 802) recover the logical register-to-physical register mapping of the map entry in the register mapping table to a previous logical register-to-physical register mapping prior to the oldest instruction of the one or more instructions indicated to flush.