A computer readable memory comprising: a complementary metal oxide semiconductor, CMOS, layer comprising: eight multiplexer units (305,310) connected to k input lines and n output lines; and four CMOS transistor crossbar arrays, each of the CMOS transistor crossbar arrays being connected to two of the multiplexer units (305,310) by 2 n output lines, each of the CMOS transistor crossbar arrays connected to n 2 vias; two access arrays formed above the CMOS transistor crossbar arrays, each of the access arrays connected to two of the CMOS transistor crossbar arrays by 2 n 2 vias; and a multilayer resistive crossbar memory stacked over the CMOS layer to form a memory box and connected to the CMOS layer via the multiplexer units (305,310), CMOS transistor crossbar arrays and access arrays, the multilayer resistive crossbar memory comprising stacked crossbar memory arrays, the stacked crossbar memory arrays including crossbars, wherein each of the two access arrays is connected to n 4 crossbars of the stacked crossbar memory arrays, each crossbar of the stacked crossbar memory arrays in the multilayer resistive crossbar memory is connected and selected by one of the access arrays such that each memory element in the multilayer resistive crossbar memory is uniquely addressed, the two access arrays are a first switching crossbar array and a second switching crossbar array, the first switching crossbar array disposed on a first side of the memory box, and the second switching crossbar array disposed on a second side of the memory box, in which the first and second switching crossbar arrays are perpendicular to the CMOS layer and the switches in the first and second crossbar arrays directly connect to crossbars of the stacked crossbar memory arrays in the multilayer resistive crossbar memory, and the first switching crossbar array is arranged to select a column crossbar in a layer of the multilayer resistive crossbar memory and the second switching crossbar array is arranged to select a row crossbar in the layer of the multilayer resistive crossbar memory, in which the column crossbar and the row crossbar intersect to address a memory element disposed between the column crossbar and the row crossbar. a complementary metal oxide semiconductor, CMOS, layer comprising: eight multiplexer units (305,310) connected to k input lines and n output lines; and four CMOS transistor crossbar arrays, each of the CMOS transistor crossbar arrays being connected to two of the multiplexer units (305,310) by 2 n output lines, each of the CMOS transistor crossbar arrays connected to n 2 vias; eight multiplexer units (305,310) connected to k input lines and n output lines; and four CMOS transistor crossbar arrays, each of the CMOS transistor crossbar arrays being connected to two of the multiplexer units (305,310) by 2 n output lines, each of the CMOS transistor crossbar arrays connected to n 2 vias; two access arrays formed above the CMOS transistor crossbar arrays, each of the access arrays connected to two of the CMOS transistor crossbar arrays by 2 n 2 vias; and a multilayer resistive crossbar memory stacked over the CMOS layer to form a memory box and connected to the CMOS layer via the multiplexer units (305,310), CMOS transistor crossbar arrays and access arrays, the multilayer resistive crossbar memory comprising stacked crossbar memory arrays, the stacked crossbar memory arrays including crossbars, wherein each of the two access arrays is connected to n 4 crossbars of the stacked crossbar memory arrays, each crossbar of the stacked crossbar memory arrays in the multilayer resistive crossbar memory is connected and selected by one of the access arrays such that each memory element in the multilayer resistive crossbar memory is uniquely addressed, the two access arrays are a first switching crossbar array and a second switching crossbar array, the first switching crossbar array disposed on a first side of the memory box, and the second switching crossbar array disposed on a second side of the memory box, in which the first and second switching crossbar arrays are perpendicular to the CMOS layer and the switches in the first and second crossbar arrays directly connect to crossbars of the stacked crossbar memory arrays in the multilayer resistive crossbar memory, and the first switching crossbar array is arranged to select a column crossbar in a layer of the multilayer resistive crossbar memory and the second switching crossbar array is arranged to select a row crossbar in the layer of the multilayer resistive crossbar memory, in which the column crossbar and the row crossbar intersect to address a memory element disposed between the column crossbar and the row crossbar.