An apparatus comprising: a phase-locked loop, PLL, configured to generate a local oscillator, LO, signal, for a transceiver; a jitter generator configured to: receive a reference clock; add jitter to the reference clock; and output the reference clock with the added jitter to the phase lock loop; and a jitter controller configured to output a signal to the jitter generator to control a characteristic of the jitter added to the reference clock, wherein: the reference clock with the added jitter reduces a fractional spur caused by a radio frequency, RF, attacker coupling into the PLL, the jitter generator comprises a delay-locked loop, DLL, incorporating first delay line, wherein the first delay line includes a plurality of delay elements, wherein each delay element delays the reference clock by a delay amount, the jitter generator further comprises a second delay line, the first delay line is configured to receive the input clock signal related to a period of the RF attacker, the delay locked loop is configured to output a delay control signal based on the input clock related to the period of the RF attacker, the delay control signal is used to tune the delay amount of each delay element in the second delay line, and the jitter controller comprises an edge selector configured to select, according to a value of an edge selection code received from a digital sequence generator, a delayed reference signal output by one of a plurality of delay elements of the second delay line to output the reference clock with the jitter. a phase-locked loop, PLL, configured to generate a local oscillator, LO, signal, for a transceiver; a jitter generator configured to: receive a reference clock; add jitter to the reference clock; and output the reference clock with the added jitter to the phase lock loop; and receive a reference clock; add jitter to the reference clock; and output the reference clock with the added jitter to the phase lock loop; and a jitter controller configured to output a signal to the jitter generator to control a characteristic of the jitter added to the reference clock, wherein: the reference clock with the added jitter reduces a fractional spur caused by a radio frequency, RF, attacker coupling into the PLL, the jitter generator comprises a delay-locked loop, DLL, incorporating first delay line, wherein the first delay line includes a plurality of delay elements, wherein each delay element delays the reference clock by a delay amount, the jitter generator further comprises a second delay line, the first delay line is configured to receive the input clock signal related to a period of the RF attacker, the delay locked loop is configured to output a delay control signal based on the input clock related to the period of the RF attacker, the delay control signal is used to tune the delay amount of each delay element in the second delay line, and the jitter controller comprises an edge selector configured to select, according to a value of an edge selection code received from a digital sequence generator, a delayed reference signal output by one of a plurality of delay elements of the second delay line to output the reference clock with the jitter. the reference clock with the added jitter reduces a fractional spur caused by a radio frequency, RF, attacker coupling into the PLL, the jitter generator comprises a delay-locked loop, DLL, incorporating first delay line, wherein the first delay line includes a plurality of delay elements, wherein each delay element delays the reference clock by a delay amount, the jitter generator further comprises a second delay line, the first delay line is configured to receive the input clock signal related to a period of the RF attacker, the delay locked loop is configured to output a delay control signal based on the input clock related to the period of the RF attacker, the delay control signal is used to tune the delay amount of each delay element in the second delay line, and the jitter controller comprises an edge selector configured to select, according to a value of an edge selection code received from a digital sequence generator, a delayed reference signal output by one of a plurality of delay elements of the second delay line to output the reference clock with the jitter.