An electrode arrangement (100; 200), comprising: a semiconductor carrier substrate (102; 202) having a first side surface (104; 204) and a second side surface (106; 206) opposite to the first side surface (104; 204); a first array of electrodes (110; 210) arranged above the first side surface (104; 204); a second array of electrodes (120; 220) arranged below the second side surface (106; 206); an electronic circuitry (130; 230) for processing electrical signals recorded by the first array of the electrodes (110; 210) and the second array of electrodes (120; 220), said electronic circuitry (130; 230) comprising at least one layer arranged above the first side surface (104; 204) and below the first array of electrodes (110; 210); a connecting layer (140 240) arranged above the at least one layer of the electronic circuitry (130; 230), said connecting layer (140; 240) being configured to connect the electrodes (110; 210) of the first array and the electrodes (120; 220) of the second array to the electronic circuitry (130; 230), wherein the connecting layer (140; 240) is configured to provide a first connection (142a; 242a) in a plane of the connecting layer (140; 240) between a first point (144a; 244a) and a second point (144b; 244b) for connecting an electrode (120; 220) in the second array to the electronic circuitry (130; 230); a first interconnect (146; 246) for electrically connecting the first point (144a; 244a) to the electronic circuitry (130; 230); a plurality of through-substrate vias, TSVs, (150; 250) extending through the semiconductor carrier substrate (102; 202) between the first side surface (104; 204) and the second side surface (106; 206) for forming an electrical connection through the semiconductor carrier substrate (102; 202); a second interconnect (148; 248) extending through a plane defined by the at least one layer of the electronic circuitry (130; 230), wherein the second interconnect (148; 248) and a first TSV (150; 250) of the plurality of TSVs electrically connect the second point (144b; 244b) to the electrode (120; 220) in the second array. a semiconductor carrier substrate (102; 202) having a first side surface (104; 204) and a second side surface (106; 206) opposite to the first side surface (104; 204); a first array of electrodes (110; 210) arranged above the first side surface (104; 204); a second array of electrodes (120; 220) arranged below the second side surface (106; 206); an electronic circuitry (130; 230) for processing electrical signals recorded by the first array of the electrodes (110; 210) and the second array of electrodes (120; 220), said electronic circuitry (130; 230) comprising at least one layer arranged above the first side surface (104; 204) and below the first array of electrodes (110; 210); a connecting layer (140 240) arranged above the at least one layer of the electronic circuitry (130; 230), said connecting layer (140; 240) being configured to connect the electrodes (110; 210) of the first array and the electrodes (120; 220) of the second array to the electronic circuitry (130; 230), wherein the connecting layer (140; 240) is configured to provide a first connection (142a; 242a) in a plane of the connecting layer (140; 240) between a first point (144a; 244a) and a second point (144b; 244b) for connecting an electrode (120; 220) in the second array to the electronic circuitry (130; 230); a first interconnect (146; 246) for electrically connecting the first point (144a; 244a) to the electronic circuitry (130; 230); a plurality of through-substrate vias, TSVs, (150; 250) extending through the semiconductor carrier substrate (102; 202) between the first side surface (104; 204) and the second side surface (106; 206) for forming an electrical connection through the semiconductor carrier substrate (102; 202); a second interconnect (148; 248) extending through a plane defined by the at least one layer of the electronic circuitry (130; 230), wherein the second interconnect (148; 248) and a first TSV (150; 250) of the plurality of TSVs electrically connect the second point (144b; 244b) to the electrode (120; 220) in the second array.