A capacitive sensing circuit configured to sense a contact capacitor (Cf) with one end being grounded, wherein the capacitive sensing circuit comprises: a sample-and-hold circuit connected to the other end of the contact capacitor (Cf), wherein the sample-and-hold circuit comprises: a first switch having one end for receiving a positive voltage and the other end connected to the contact capacitor; and a second switch having one end connected to the contact capacitor and the other end connected to the integrating input terminal, wherein the first switch is turned on and the second switch is turned off at a first time, and the first switch is turned off and the second switch is turned on at a second time; an integrating circuit comprising: an integrating input terminal connected to the sample-and-hold circuit; and an integrating output terminal for outputting an integrating output voltage (V OUT); a comparator (comp) comprising: a first input terminal connected to the integrating output terminal for receiving the integrating output voltage (V OUT); a second input terminal for receiving a reference voltage (V REF); and a comparison output terminal; a counter (cntr) connected to the comparison output terminal and configured to accumulate a cumulative number of transitions of the comparator (comp); a voltage boost circuit connected to the integrating input terminal and configured to add a specific value (V K) to the integrating output voltage (V OUT) when the comparator (comp) performs a transition, wherein the voltage boost circuit comprises: a boost capacitor connected to the integrating input terminal; a fifth switch having one end for receiving a positive voltage and the other end connected to the boost capacitor; and a sixth switch having one end for receiving a ground voltage and the other end connected to the boost capacitor; a logic circuit connected to the counter (cntr), wherein the logic circuit outputs an integration time (T OUT) of the integrating circuit when the cumulative number is equal to a predetermined number, wherein the integration time correlates with a capacitance value of the contact capacitor (Cf). a sample-and-hold circuit connected to the other end of the contact capacitor (Cf), wherein the sample-and-hold circuit comprises: a first switch having one end for receiving a positive voltage and the other end connected to the contact capacitor; and a second switch having one end connected to the contact capacitor and the other end connected to the integrating input terminal, wherein the first switch is turned on and the second switch is turned off at a first time, and the first switch is turned off and the second switch is turned on at a second time; a first switch having one end for receiving a positive voltage and the other end connected to the contact capacitor; and a second switch having one end connected to the contact capacitor and the other end connected to the integrating input terminal, wherein the first switch is turned on and the second switch is turned off at a first time, and the first switch is turned off and the second switch is turned on at a second time; an integrating circuit comprising: an integrating input terminal connected to the sample-and-hold circuit; and an integrating output terminal for outputting an integrating output voltage (V OUT); an integrating input terminal connected to the sample-and-hold circuit; and an integrating output terminal for outputting an integrating output voltage (V OUT); a comparator (comp) comprising: a first input terminal connected to the integrating output terminal for receiving the integrating output voltage (V OUT); a second input terminal for receiving a reference voltage (V REF); and a comparison output terminal; a first input terminal connected to the integrating output terminal for receiving the integrating output voltage (V OUT); a second input terminal for receiving a reference voltage (V REF); and a comparison output terminal; a counter (cntr) connected to the comparison output terminal and configured to accumulate a cumulative number of transitions of the comparator (comp); a voltage boost circuit connected to the integrating input terminal and configured to add a specific value (V K) to the integrating output voltage (V OUT) when the comparator (comp) performs a transition, wherein the voltage boost circuit comprises: a boost capacitor connected to the integrating input terminal; a fifth switch having one end for receiving a positive voltage and the other end connected to the boost capacitor; and a sixth switch having one end for receiving a ground voltage and the other end connected to the boost capacitor; a boost capacitor connected to the integrating input terminal; a fifth switch having one end for receiving a positive voltage and the other end connected to the boost capacitor; and a sixth switch having one end for receiving a ground voltage and the other end connected to the boost capacitor; a logic circuit connected to the counter (cntr), wherein the logic circuit outputs an integration time (T OUT) of the integrating circuit when the cumulative number is equal to a predetermined number, wherein the integration time correlates with a capacitance value of the contact capacitor (Cf).