A frequency multiplying device for determination of a fundamental frequency f of an analogue target signal, the device comprising • a generating device for generating a reference signal having a frequency f osc, wherein f osc is greater than f, • a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal and outputs a first counter signal • a frequency divider being coupled between the generating device and the first counter and • a second counter being coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and • a comparator with a first input coupled to the first counter to receive the first counter signal and with a second input coupled to the second counter to receive the second counter signal, wherein the comparator is configured to generate a signal to an output of the comparator in the event the first counter signal is equal to the second counter signal, and with an output of the comparator being coupled to reset the second counter, wherein the frequency multiplying device has a latch register with an input and an output, the input coupled to the output of the first counter and the output coupled to the first input of the comparator,, characterized in that the first counter is adapted to count the number of signal edges generated from the reference signal in a time interval equal to 1/f, wherein the output from the first binary counter is divided by a factor of D1, that is an integer power of 2, in the latch register that is configured to shift the bits by log2 places. • a generating device for generating a reference signal having a frequency f osc, wherein f osc is greater than f, • a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal and outputs a first counter signal • a frequency divider being coupled between the generating device and the first counter and • a second counter being coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and • a comparator with a first input coupled to the first counter to receive the first counter signal and with a second input coupled to the second counter to receive the second counter signal, wherein the comparator is configured to generate a signal to an output of the comparator in the event the first counter signal is equal to the second counter signal, and with an output of the comparator being coupled to reset the second counter, wherein the frequency multiplying device has a latch register with an input and an output, the input coupled to the output of the first counter and the output coupled to the first input of the comparator,, characterized in that the first counter is adapted to count the number of signal edges generated from the reference signal in a time interval equal to 1/f, wherein the output from the first binary counter is divided by a factor of D1, that is an integer power of 2, in the latch register that is configured to shift the bits by log2 places.