A display device comprising a shift register comprising a shift register unit, said shift register unit comprising: an input module of which a first end is connected with an input end (INPUT) of the shift register unit to receive an input signal from the input end (INPUT), and a second end is connected with a pull-up node, and which is configured to transmit a received input signal to the pull-up node; an output module of which a first end is connected with the pull-up node, a second end is connected with a first control signal end, and a third end is connected with an output end of the shift register unit, and which is configured to output a first control signal of the first control signal end to the output end when a pull-up signal at the pull-up node is in effective pull-up level; a coupling module of which a first end is connected with a second control signal end, a second end is connected with the pull-up node, and a third end is connected with a third control signal end, and which is configured to control the pull-up signal at the pull-up node according to a second control signal of the second control signal end and a third control signal of the third control signal end by way of voltage coupling, wherein the coupling module comprises a coupling transistor (Tc), whose gate is connected with the second control signal end, and first electrode is connected with the third control signal end; and a first capacitor, whose first end is connected with a second electrode of the coupling transistor (Tc), and second end is connected with the pull-up node, and wherein the coupling module is configured to make the pull-up signal at the pull-up node jump from the first coupling voltage to the second coupling voltage by way of voltage-coupling when the second control signal of the second control signal end is in effective control level and the third control signal of the third control signal end jumps from the first level to the second level, characterized in that the display device is adapted to control the first control signal, the second control signa and the third control signal such that the first control signal is a first clock signal provided by a first clock signal end and a period of the first control signal is the first period, a period of the third control signal is a second period, the second period is 1/2 of the first period, a duty ratio of the third control signal is smaller than or equal to 1/2, and the third control signal is in effective control level at both a jump-up edge and a jump-down edge of the first control signal so as to obtain a gate pulse at the output end, said gate pulse having a pulse period which is 1/2 of the first period, the second control signal having a waveform corresponding to the gate pulse at the output end but delayed by 1/4 of the first period compared to the output signal at the output end of the shift register unit. an input module of which a first end is connected with an input end (INPUT) of the shift register unit to receive an input signal from the input end (INPUT), and a second end is connected with a pull-up node, and which is configured to transmit a received input signal to the pull-up node; an output module of which a first end is connected with the pull-up node, a second end is connected with a first control signal end, and a third end is connected with an output end of the shift register unit, and which is configured to output a first control signal of the first control signal end to the output end when a pull-up signal at the pull-up node is in effective pull-up level; a coupling module of which a first end is connected with a second control signal end, a second end is connected with the pull-up node, and a third end is connected with a third control signal end, and which is configured to control the pull-up signal at the pull-up node according to a second control signal of the second control signal end and a third control signal of the third control signal end by way of voltage coupling, wherein the coupling module comprises a coupling transistor (Tc), whose gate is connected with the second control signal end, and first electrode is connected with the third control signal end; and a first capacitor, whose first end is connected with a second electrode of the coupling transistor (Tc), and second end is connected with the pull-up node, and wherein the coupling module is configured to make the pull-up signal at the pull-up node jump from the first coupling voltage to the second coupling voltage by way of voltage-coupling when the second control signal of the second control signal end is in effective control level and the third control signal of the third control signal end jumps from the first level to the second level, characterized in that the display device is adapted to control the first control signal, the second control signa and the third control signal such that the first control signal is a first clock signal provided by a first clock signal end and a period of the first control signal is the first period, a period of the third control signal is a second period, the second period is 1/2 of the first period, a duty ratio of the third control signal is smaller than or equal to 1/2, and the third control signal is in effective control level at both a jump-up edge and a jump-down edge of the first control signal so as to obtain a gate pulse at the output end, said gate pulse having a pulse period which is 1/2 of the first period, the second control signal having a waveform corresponding to the gate pulse at the output end but delayed by 1/4 of the first period compared to the output signal at the output end of the shift register unit.