A type-I phase-locked loop, PLL, (200, 600, 900, 1400) comprising: a phase detector (201, 601, 901) operable to receive: a reference signal; and a feedback signal; a controlled oscillator (203, 603, 903) having an input coupled to an output of the phase detector; and a feedback divider (204, 604, 904) coupled to an output of the controlled oscillator, wherein the feedback divider has a reset input configured to receive a reset input signal, wherein the reset input signal is synchronized with the reference signal and the feedback divider operable to: divide the output of the controlled oscillator by a division value to generate the feedback signal which is provided to the phase detector; and in response to the reset input signal being disabled, perform a first division cycle of the feedback divider, wherein the division value of the feedback divider is set to a nominal value after the first division cycle, wherein the division value during the first division cycle is different from the nominal value, wherein during the first division cycle the division value of the feedback divider is set to the nominal value multiplied by a ratio of a phase difference of the phase detector under a locked state and 360° such that a locking relationship is achieved between the reference signal and the feedback signal during the first division cycle. a phase detector (201, 601, 901) operable to receive: a reference signal; and a feedback signal; a reference signal; and a feedback signal; a controlled oscillator (203, 603, 903) having an input coupled to an output of the phase detector; and a feedback divider (204, 604, 904) coupled to an output of the controlled oscillator, wherein the feedback divider has a reset input configured to receive a reset input signal, wherein the reset input signal is synchronized with the reference signal and the feedback divider operable to: divide the output of the controlled oscillator by a division value to generate the feedback signal which is provided to the phase detector; and in response to the reset input signal being disabled, perform a first division cycle of the feedback divider, wherein the division value of the feedback divider is set to a nominal value after the first division cycle, wherein the division value during the first division cycle is different from the nominal value, wherein during the first division cycle the division value of the feedback divider is set to the nominal value multiplied by a ratio of a phase difference of the phase detector under a locked state and 360° such that a locking relationship is achieved between the reference signal and the feedback signal during the first division cycle. divide the output of the controlled oscillator by a division value to generate the feedback signal which is provided to the phase detector; and in response to the reset input signal being disabled, perform a first division cycle of the feedback divider, wherein the division value of the feedback divider is set to a nominal value after the first division cycle, wherein the division value during the first division cycle is different from the nominal value, wherein during the first division cycle the division value of the feedback divider is set to the nominal value multiplied by a ratio of a phase difference of the phase detector under a locked state and 360° such that a locking relationship is achieved between the reference signal and the feedback signal during the first division cycle.