A system comprising at least two assemblies (16A, 16B, 16C) of transistors and a control circuit of the assemblies (16A, 16B, 16C), each assembly (16A, 16B, 16C) of transistors comprising a first transistor (1A, 1B, 1C) and a second transistor (2A, 2B, 2C) coupled in series between first (15, 56) and second (17, 57) supply nodes, characterized in that the control circuit is configured to provide a control signal respective of each assembly (16A, 16B, 16C) of transistors, the control circuit being configured to regulate middle point currents (IoutA, IoutB, IoutC) respective of all the assemblies (16A, 16B, 16C) of transistors according to a difference between the sum of values representative of middle point currents (IoutA, IoutB, IoutC) of all the assemblies (16A, 16B, 16C) of transistors and a sum of set values (IinA, IinB, IinC) assigned to the assemblies (16A, 16B, 16C) of transistors so that the respective middle point currents (IoutA, IoutB, IoutC) are substantially identical, the middle point (IoutA, IoutB, IoutC) respective of each assembly (16A, 16B, 16C) of transistors corresponding to the connecting point of the first transistor (1A, 1B, 1C) with the second transistor (2A, 2B, 2C) of said assembly, the control circuit comprises, for each assembly (16A, 16B, 16C) of transistors, a stage comprising an adder (23A, 23B, 23C) and a device (21A, 21B, 21C) for measuring the representative value of the middle point current (IoutA, IoutB, IoutC) respective of the assembly (16A, 16B, 16C) of transistors, the adder (23A, 23B, 23C) of each stage being configured to substract the representative value of the middle point current (IoutA, IoutB, IoutC) of said assembly (16A, 16B, 16C) of transistors from the set value (IinA, IinB, IinC) assigned to said assembly (16A, 16B, 16C) of transistors, the adder (23A, 23B, 23C) of each stage being configured to provide an error (eA, eB, eC), the gates of each assembly (16A, 16B, 16C) of transistors being coupled to the corresponding stage, the control circuit further comprises an adding circuit configured to add the errors (eA, eB, eC) respective of the adders (23A, 23B, 23C) of each stage, in order to obtain the difference, one of the stages comprises a corrector configured to receive as an input said difference and to provide as an output the respective control signals of the assemblies (16A, 16B, 16C) of the transistors. the control circuit is configured to provide a control signal respective of each assembly (16A, 16B, 16C) of transistors, the control circuit being configured to regulate middle point currents (IoutA, IoutB, IoutC) respective of all the assemblies (16A, 16B, 16C) of transistors according to a difference between the sum of values representative of middle point currents (IoutA, IoutB, IoutC) of all the assemblies (16A, 16B, 16C) of transistors and a sum of set values (IinA, IinB, IinC) assigned to the assemblies (16A, 16B, 16C) of transistors so that the respective middle point currents (IoutA, IoutB, IoutC) are substantially identical, the middle point (IoutA, IoutB, IoutC) respective of each assembly (16A, 16B, 16C) of transistors corresponding to the connecting point of the first transistor (1A, 1B, 1C) with the second transistor (2A, 2B, 2C) of said assembly, the control circuit comprises, for each assembly (16A, 16B, 16C) of transistors, a stage comprising an adder (23A, 23B, 23C) and a device (21A, 21B, 21C) for measuring the representative value of the middle point current (IoutA, IoutB, IoutC) respective of the assembly (16A, 16B, 16C) of transistors, the adder (23A, 23B, 23C) of each stage being configured to substract the representative value of the middle point current (IoutA, IoutB, IoutC) of said assembly (16A, 16B, 16C) of transistors from the set value (IinA, IinB, IinC) assigned to said assembly (16A, 16B, 16C) of transistors, the adder (23A, 23B, 23C) of each stage being configured to provide an error (eA, eB, eC), the gates of each assembly (16A, 16B, 16C) of transistors being coupled to the corresponding stage, the control circuit further comprises an adding circuit configured to add the errors (eA, eB, eC) respective of the adders (23A, 23B, 23C) of each stage, in order to obtain the difference, one of the stages comprises a corrector configured to receive as an input said difference and to provide as an output the respective control signals of the assemblies (16A, 16B, 16C) of the transistors.