A circuit comprising: a first voltage supply node; a first N-channel field effect transistor, NFET, having a drain, a gate, a source, and a body, wherein the body is coupled to the source, wherein the drain of the first NFET is coupled to the first supply node, wherein said first NFET is configured to have a drain-to-gate overlap capacitance, through which a first current flows in a first current path during an ESD event; a first resistor having a first lead and a second lead, wherein the first lead of the first resistor is coupled to the gate of the first NFET, and wherein the second lead of the first resistor is coupled to the source of the first NFET, the first resistor configured such that during said ESD event said first current flows across the first resistor reducing the trigger voltage of the first NFET during said ESD event; a second NFET having a drain, a gate, a source, and a body, wherein the body is coupled to the source; a second resistor having a first lead and a second lead, wherein the first lead of the second resistor is coupled to the gate of the second NFET, and wherein the second lead of the second resistor is coupled to the source of the second NFET; and a first capacitance structure having a first lead and a second lead, wherein the first capacitance structure is taken from the group consisting of: a diode, a metal-insulator-metal capacitor (MIMCAP), a field insulator capacitor, a gate-insulator-semiconductor capacitor, wherein the first lead of the first capacitance structure is coupled to the first voltage supply node, wherein the first capacitance structure is coupled to the second resistor, and wherein the first capacitance structure is configured to supply a second current that flows through the second resistor during said ESD event, which reduces the trigger voltage of the second NFET during said ESD event, wherein the first and second NFETs are configured to operate under said ESD event in a snap-back mode, said reduced trigger voltages being equal and corresponding to drain-to-source voltages of the NFETs configured to initiate bipolar transistor conduction in said snap-back mode. a first voltage supply node; a first N-channel field effect transistor, NFET, having a drain, a gate, a source, and a body, wherein the body is coupled to the source, wherein the drain of the first NFET is coupled to the first supply node, wherein said first NFET is configured to have a drain-to-gate overlap capacitance, through which a first current flows in a first current path during an ESD event; a first resistor having a first lead and a second lead, wherein the first lead of the first resistor is coupled to the gate of the first NFET, and wherein the second lead of the first resistor is coupled to the source of the first NFET, the first resistor configured such that during said ESD event said first current flows across the first resistor reducing the trigger voltage of the first NFET during said ESD event; a second NFET having a drain, a gate, a source, and a body, wherein the body is coupled to the source; a second resistor having a first lead and a second lead, wherein the first lead of the second resistor is coupled to the gate of the second NFET, and wherein the second lead of the second resistor is coupled to the source of the second NFET; and a first capacitance structure having a first lead and a second lead, wherein the first capacitance structure is taken from the group consisting of: a diode, a metal-insulator-metal capacitor (MIMCAP), a field insulator capacitor, a gate-insulator-semiconductor capacitor, wherein the first lead of the first capacitance structure is coupled to the first voltage supply node, wherein the first capacitance structure is coupled to the second resistor, and wherein the first capacitance structure is configured to supply a second current that flows through the second resistor during said ESD event, which reduces the trigger voltage of the second NFET during said ESD event,