A semiconductor device comprising: a first memory module; a second memory module; a third memory module; a first control signal line (EXR_0) coupled in parallel with the first memory module and the second memory module to transmit a control signal to the first and second memory modules; a second control signal line (EXR_1) coupled with the third memory module and the first memory module to transmit the control signal to the third memory module; a first wiring (INRij) disposed in the first memory module and coupled with the first control signal line and the second control signal line to transmit the control signal from the first control signal line to the second control signal line; a second wiring (INRij) disposed in the second memory module and coupled with the first control signal line to receive the control signal from the first control signal line; and a third wiring (INRij) disposed in the third memory module and coupled with the second control signal line to receive the control signal from the second control signal, wherein each of the memory modules includes a memory cell array including memory cells; and a peripheral circuit (30, 40, or 50) for reading data from the memory cells or writing data to the memory cells, wherein the first memory module includes a first transistor (304, 307, 420, or 421) having a gate electrode coupled to the first wiring and having a source-drain path coupled between the peripheral circuit of the first memory module and a first node supplied with a first voltage, wherein the second memory module includes a second transistor (304, 307, 420, or 421) having a gate electrode coupled to the second wiring and having a source-drain path coupled between the peripheral circuit of the second memory module and a second node supplied with a second voltage, wherein the third memory module includes a third transistor (304, 307, 420, or 421) having a gate electrode coupled to the third wiring and having a source-drain path coupled between the peripheral circuit of the third memory module and a third node supplied with a third voltage, and wherein the first memory module has a greater storage capacity than the second memory module, wherein each of the first, second, and third voltages is a power supply voltage or a ground voltage. a first memory module; a second memory module; a third memory module; a first control signal line (EXR_0) coupled in parallel with the first memory module and the second memory module to transmit a control signal to the first and second memory modules; a second control signal line (EXR_1) coupled with the third memory module and the first memory module to transmit the control signal to the third memory module; a first wiring (INRij) disposed in the first memory module and coupled with the first control signal line and the second control signal line to transmit the control signal from the first control signal line to the second control signal line; a second wiring (INRij) disposed in the second memory module and coupled with the first control signal line to receive the control signal from the first control signal line; and a third wiring (INRij) disposed in the third memory module and coupled with the second control signal line to receive the control signal from the second control signal, wherein each of the memory modules includes a memory cell array including memory cells; and a peripheral circuit (30, 40, or 50) for reading data from the memory cells or writing data to the memory cells, wherein the first memory module includes a first transistor (304, 307, 420, or 421) having a gate electrode coupled to the first wiring and having a source-drain path coupled between the peripheral circuit of the first memory module and a first node supplied with a first voltage, wherein the second memory module includes a second transistor (304, 307, 420, or 421) having a gate electrode coupled to the second wiring and having a source-drain path coupled between the peripheral circuit of the second memory module and a second node supplied with a second voltage, wherein the third memory module includes a third transistor (304, 307, 420, or 421) having a gate electrode coupled to the third wiring and having a source-drain path coupled between the peripheral circuit of the third memory module and a third node supplied with a third voltage, and wherein the first memory module has a greater storage capacity than the second memory module, wherein each of the first, second, and third voltages is a power supply voltage or a ground voltage.