A liquid crystal display comprising a control circuit; and a plurality of pixel circuits arranged to form a matrix on a substrate, wherein each of the plurality of pixel circuits comprises: a liquid crystal cell unit comprising a liquid crystal cell and a hold capacitor with first ends thereof commonly connected; a pixel-select switch having a first end connected to a signal line (16-i) and a second end connected to the first ends of the liquid crystal cell and the hold capacitor; a memory circuit for holding a digital image signal, the memory circuit of a cross-coupled inverter type being connected to a negative power-supply line (33-i) for feeding a negative power-supply voltage VSS to the memory circuit and further being connected to a positive power-supply line (30-i) for feeding a positive power-supply voltage (VCCMEM) to the memory circuit; a data-write switch having a first end connected to the signal line and a second end connected to an input terminal of the memory circuit; and a read buffer for reading the digital image signal held in the memory circuit and writing the digital image signal to the liquid crystal cell unit, characterized in that the control circuit is adapted to control digital image data to be written to the memory circuit by (a) lowering once the positive power-supply voltage (VCCMEM) supplied to the positive power-supply line (30-i) forcibly from a VDD level to a VSS level and then setting it to a VCC level, to reduce the time it takes for the positive power-supply voltage (VCCMEM) to shift from VDD level to VCC level, the VSS level being lower than the VCC level, the VCC level being lower than the VDD level; (b) controlling the data write switch to write the image data to the memory circuit at VCC level; and (c) restoring the positive power-supply voltage (VCCMEM) to VDD level. a liquid crystal cell unit comprising a liquid crystal cell and a hold capacitor with first ends thereof commonly connected; a pixel-select switch having a first end connected to a signal line (16-i) and a second end connected to the first ends of the liquid crystal cell and the hold capacitor; a memory circuit for holding a digital image signal, the memory circuit of a cross-coupled inverter type being connected to a negative power-supply line (33-i) for feeding a negative power-supply voltage VSS to the memory circuit and further being connected to a positive power-supply line (30-i) for feeding a positive power-supply voltage (VCCMEM) to the memory circuit; a data-write switch having a first end connected to the signal line and a second end connected to an input terminal of the memory circuit; and a read buffer for reading the digital image signal held in the memory circuit and writing the digital image signal to the liquid crystal cell unit, (a) lowering once the positive power-supply voltage (VCCMEM) supplied to the positive power-supply line (30-i) forcibly from a VDD level to a VSS level and then setting it to a VCC level, to reduce the time it takes for the positive power-supply voltage (VCCMEM) to shift from VDD level to VCC level, the VSS level being lower than the VCC level, the VCC level being lower than the VDD level; (b) controlling the data write switch to write the image data to the memory circuit at VCC level; and (c) restoring the positive power-supply voltage (VCCMEM) to VDD level.