A memory device, comprising: a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface, and wherein the top surface of the first fin is recessed relative to the top surface of the second fin; a memory cell formed on a first fin of the plurality of fins, comprising: spaced apart first source and first drain regions in the first fin, with a first channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source and first drain regions, a floating gate of polysilicon material that extends along a first portion of the first channel region, wherein the floating gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a select gate of metal material that extends along a second portion of the first channel region, wherein the select gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a control gate of polysilicon material that extends along and is insulated from the floating gate, and an erase gate of polysilicon material that extends along and is insulated from the first source region; a logic device formed on a second fin of the plurality of fins, comprising: spaced apart second source and second drain regions in the second fin, with a second channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source and second drain regions, and a first logic gate of metal material that extends along the second channel region, wherein the first logic gate wraps around the second fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the second fin. a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface, and wherein the top surface of the first fin is recessed relative to the top surface of the second fin; a memory cell formed on a first fin of the plurality of fins, comprising: spaced apart first source and first drain regions in the first fin, with a first channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source and first drain regions, a floating gate of polysilicon material that extends along a first portion of the first channel region, wherein the floating gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a select gate of metal material that extends along a second portion of the first channel region, wherein the select gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a control gate of polysilicon material that extends along and is insulated from the floating gate, and an erase gate of polysilicon material that extends along and is insulated from the first source region; spaced apart first source and first drain regions in the first fin, with a first channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source and first drain regions, a floating gate of polysilicon material that extends along a first portion of the first channel region, wherein the floating gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a select gate of metal material that extends along a second portion of the first channel region, wherein the select gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a control gate of polysilicon material that extends along and is insulated from the floating gate, and an erase gate of polysilicon material that extends along and is insulated from the first source region; a logic device formed on a second fin of the plurality of fins, comprising: spaced apart second source and second drain regions in the second fin, with a second channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source and second drain regions, and a first logic gate of metal material that extends along the second channel region, wherein the first logic gate wraps around the second fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the second fin. spaced apart second source and second drain regions in the second fin, with a second channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source and second drain regions, and a first logic gate of metal material that extends along the second channel region, wherein the first logic gate wraps around the second fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the second fin.