A memory controller for communicating with a memory device including one or more memory chips, the memory controller comprising: a fault determination circuit configured to receive a first parity, a second parity, and data read out from a first row of one memory chip of the memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit configured to store a repair parity for repairing a fault of a row of a plurality of rows of the one memory chip of the memory device, wherein the plurality of rows of the one memory chip constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; a recovery circuit configured to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row; and a parity managing circuit configured to generate the repair parity and manage an update operation with respect to the repair parity stored in the parity storage circuit when a memory operation with respect to the one memory chip of the memory device is performed, wherein the repair parity is read from the parity storage circuit within the memory controller and provided to the recovery circuit, wherein in a data read process with respect to the one memory chip of the memory device, read data is temporarily stored in a cache memory, and wherein, when the data read out from the first row is loaded into the cache memory in the data read process, the parity managing circuit configured to generate a new repair parity using the data read out from the first row and a repair parity corresponding to an old parity, and to update the parity storage circuit with the new repair parity, characterized in that, as the data read out from the first row is loaded into the cache memory, the first row is removed from the repair unit and the new repair parity has information used to repair faults of the remaining rows of the repair unit. a fault determination circuit configured to receive a first parity, a second parity, and data read out from a first row of one memory chip of the memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit configured to store a repair parity for repairing a fault of a row of a plurality of rows of the one memory chip of the memory device, wherein the plurality of rows of the one memory chip constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; a recovery circuit configured to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row; and a parity managing circuit configured to generate the repair parity and manage an update operation with respect to the repair parity stored in the parity storage circuit when a memory operation with respect to the one memory chip of the memory device is performed, wherein the repair parity is read from the parity storage circuit within the memory controller and provided to the recovery circuit, wherein in a data read process with respect to the one memory chip of the memory device, read data is temporarily stored in a cache memory, and wherein, when the data read out from the first row is loaded into the cache memory in the data read process, the parity managing circuit configured to generate a new repair parity using the data read out from the first row and a repair parity corresponding to an old parity, and to update the parity storage circuit with the new repair parity, characterized in that, as the data read out from the first row is loaded into the cache memory, the first row is removed from the repair unit and the new repair parity has information used to repair faults of the remaining rows of the repair unit.