A circuit comprising: a first bit line; a second bit line; a sensing circuit (SENPAIR) coupled to the first bit line and the second bit line; a node configured to be selectively coupled to at least three voltage sources including a first voltage source, a second voltage source and a third voltage source; the first voltage source configured to supply a retention voltage (VREST) to the node; the second voltage source configured to supply a ground reference voltage to the node; and the third voltage source configured to supply a reference voltage (VREF) to the node; and a first switch and a second switch configured to receive respective first control signal and second control signal (ZRWL) and to pass a voltage at the node to the respective bit line (BL;BLB), when the respective control signal is activated; wherein when a memory cell coupled to the first bit line is in a retention mode, the first voltage source is configured to supply a retention voltage value (VREST) to the node, such that a current leak from the memory cell to the first bit line and/or the second bit line is reduced compared to the node receiving a voltage VSS value, wherein the circuit is configured for: - when the memory cell is in the retention mode (T1, T7), passing the retention voltage value (VREST) from the node through the first switch to the first bit line and through the second switch to the second bit line; - when the memory cell is in an access preparation mode, transferring the ground reference voltage to the node and from the node through the first switch to the first bit line and through the second switch to the second bit line, and subsequently disconnecting the first bit line from the node by turning off the first switch; and - when the memory cell is in an access mode (T3-T6): connecting the first bit line to the memory cell; applying the reference voltage value (VREF) to the second bit line through the second switch, thereby causing a voltage split between the first bit line and the second bit line to develop; subsequently disconnecting the second bit line from the node by turning off the second switch, and turning on a sensing pair (SENPAIR) of the sensing circuit, thereby causing the voltage split to further develop by the sensing pair. a first bit line; a second bit line; a sensing circuit (SENPAIR) coupled to the first bit line and the second bit line; a node configured to be selectively coupled to at least three voltage sources including a first voltage source, a second voltage source and a third voltage source; the first voltage source configured to supply a retention voltage (VREST) to the node; the second voltage source configured to supply a ground reference voltage to the node; and the third voltage source configured to supply a reference voltage (VREF) to the node; and a first switch and a second switch configured to receive respective first control signal and second control signal (ZRWL) and to pass a voltage at the node to the respective bit line (BL;BLB), when the respective control signal is activated; wherein when a memory cell coupled to the first bit line is in a retention mode, the first voltage source is configured to supply a retention voltage value (VREST) to the node, such that a current leak from the memory cell to the first bit line and/or the second bit line is reduced compared to the node receiving a voltage VSS value, wherein the circuit is configured for: - when the memory cell is in the retention mode (T1, T7), passing the retention voltage value (VREST) from the node through the first switch to the first bit line and through the second switch to the second bit line; - when the memory cell is in an access preparation mode, transferring the ground reference voltage to the node and from the node through the first switch to the first bit line and through the second switch to the second bit line, and subsequently disconnecting the first bit line from the node by turning off the first switch; and - when the memory cell is in an access mode (T3-T6): connecting the first bit line to the memory cell; applying the reference voltage value (VREF) to the second bit line through the second switch, thereby causing a voltage split between the first bit line and the second bit line to develop; subsequently disconnecting the second bit line from the node by turning off the second switch, and turning on a sensing pair (SENPAIR) of the sensing circuit, thereby causing the voltage split to further develop by the sensing pair. - when the memory cell is in the retention mode (T1, T7), passing the retention voltage value (VREST) from the node through the first switch to the first bit line and through the second switch to the second bit line; - when the memory cell is in an access preparation mode, transferring the ground reference voltage to the node and from the node through the first switch to the first bit line and through the second switch to the second bit line, and subsequently disconnecting the first bit line from the node by turning off the first switch; and - when the memory cell is in an access mode (T3-T6): connecting the first bit line to the memory cell; applying the reference voltage value (VREF) to the second bit line through the second switch, thereby causing a voltage split between the first bit line and the second bit line to develop; subsequently disconnecting the second bit line from the node by turning off the second switch, and turning on a sensing pair (SENPAIR) of the sensing circuit, thereby causing the voltage split to further develop by the sensing pair.