A gate driving circuit, comprising N stages of cascaded shift registers, N being an integer greater than or equal to 4, characterized in that, in the N stages of shift registers, an output signal terminal of an n th stage of shift register is connected to an input signal terminal of an (n+I/2) th stage of shift register, and a reset signal terminal of the n th stage of shift register is connected to an output signal terminal of an (n+K) th stage of shift register, wherein n is an integer greater than or equal to 1 and less than (N-I/2), K is an integer greater than I/2 and less than I, and I is a number of clock signal lines connected to the gate driving circuit, which is equal to 6 or 8; wherein each stage of shift register among the N stages of shift registers comprises: an output sub-circuit (711, 811) connected to an output signal terminal (OUTPUT), a clock signal input terminal for receiving a clock signal of the stage of shift register and a pull-up control node of the stage of shift register, and configured to turn on a connection between the clock signal input terminal and the output signal terminal (OUTPUT) when the pull-up control node is at an active operating level; and a reset sub-circuit (712', 812) connected to the reset signal terminal (RESET) for receiving a reset signal (Reset(n)), the pull-up control node and a first level terminal for providing a first level respectively, and configured to reset the pull-up control node to the first level under control of the reset signal (Reset(n)), wherein the reset sub-circuit (712', 812) is further connected to a total reset signal terminal (TRST) for receiving a total reset signal (Trst), the output signal terminal (OUTPUT) and a first fixed level terminal for receiving a first fixed level, and configured to reset the pull-up control node and a potential at the output signal terminal (OUTPUT) to the first fixed level under control of the total reset signal (Trst) when scanning of each frame of display image ends. in the N stages of shift registers, an output signal terminal of an n th stage of shift register is connected to an input signal terminal of an (n+I/2) th stage of shift register, and a reset signal terminal of the n th stage of shift register is connected to an output signal terminal of an (n+K) th stage of shift register, wherein n is an integer greater than or equal to 1 and less than (N-I/2), K is an integer greater than I/2 and less than I, and I is a number of clock signal lines connected to the gate driving circuit, which is equal to 6 or 8; wherein each stage of shift register among the N stages of shift registers comprises: an output sub-circuit (711, 811) connected to an output signal terminal (OUTPUT), a clock signal input terminal for receiving a clock signal of the stage of shift register and a pull-up control node of the stage of shift register, and configured to turn on a connection between the clock signal input terminal and the output signal terminal (OUTPUT) when the pull-up control node is at an active operating level; and a reset sub-circuit (712', 812) connected to the reset signal terminal (RESET) for receiving a reset signal (Reset(n)), the pull-up control node and a first level terminal for providing a first level respectively, and configured to reset the pull-up control node to the first level under control of the reset signal (Reset(n)), wherein the reset sub-circuit (712', 812) is further connected to a total reset signal terminal (TRST) for receiving a total reset signal (Trst), the output signal terminal (OUTPUT) and a first fixed level terminal for receiving a first fixed level, and configured to reset the pull-up control node and a potential at the output signal terminal (OUTPUT) to the first fixed level under control of the total reset signal (Trst) when scanning of each frame of display image ends. an output sub-circuit (711, 811) connected to an output signal terminal (OUTPUT), a clock signal input terminal for receiving a clock signal of the stage of shift register and a pull-up control node of the stage of shift register, and configured to turn on a connection between the clock signal input terminal and the output signal terminal (OUTPUT) when the pull-up control node is at an active operating level; and a reset sub-circuit (712', 812) connected to the reset signal terminal (RESET) for receiving a reset signal (Reset(n)), the pull-up control node and a first level terminal for providing a first level respectively, and configured to reset the pull-up control node to the first level under control of the reset signal (Reset(n)), wherein the reset sub-circuit (712', 812) is further connected to a total reset signal terminal (TRST) for receiving a total reset signal (Trst), the output signal terminal (OUTPUT) and a first fixed level terminal for receiving a first fixed level, and configured to reset the pull-up control node and a potential at the output signal terminal (OUTPUT) to the first fixed level under control of the total reset signal (Trst) when scanning of each frame of display image ends.