An apparatus, comprising: a power line communication PLC device that is configured to communicate on alternating current AC power wiring in a frequency range of 9 kilohertz to 500 kilohertz, characterized in that the PLC device does not use automatic gain control AGC functionality prior to analog to digital conversion given that the PLC device includes: an over-sampled analog-to-digital converter ADC with a sample clock of at least 10 megahertz, characterized in that the over-sampled ADC includes: a loop filter that is configured to maintain a noise power spectral density that does not exceed 3 decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above characterized in that the loop filter is configured to compare an input signal with a quantized output signal that is produced by a quantizer and fed back into the loop filter, frequency weigh differences between the input and quantized output signals based on the comparison, and provide a result of the frequency weighing to the quantizer which generates the quantized output signal that is fed back into the loop filter, and a digital filter and decimator configured to remove quantization noise characterized in that the digital filter and decimator are configured to receive the quantized output signal and remove quantization noise using at least one of a bit shifter, a cascaded integrator-comb CIC filter, an infinite impulse response IIR filter, or a digital multiplier, wherein a decimation factor of the decimator is such that the decimation factor provides an output decimation rate between 350 kilohertz and 1.6 megahertz. a power line communication PLC device that is configured to communicate on alternating current AC power wiring in a frequency range of 9 kilohertz to 500 kilohertz, characterized in that the PLC device does not use automatic gain control AGC functionality prior to analog to digital conversion given that the PLC device includes: an over-sampled analog-to-digital converter ADC with a sample clock of at least 10 megahertz, characterized in that the over-sampled ADC includes: a loop filter that is configured to maintain a noise power spectral density that does not exceed 3 decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above characterized in that the loop filter is configured to compare an input signal with a quantized output signal that is produced by a quantizer and fed back into the loop filter, frequency weigh differences between the input and quantized output signals based on the comparison, and provide a result of the frequency weighing to the quantizer which generates the quantized output signal that is fed back into the loop filter, and a digital filter and decimator configured to remove quantization noise characterized in that the digital filter and decimator are configured to receive the quantized output signal and remove quantization noise using at least one of a bit shifter, a cascaded integrator-comb CIC filter, an infinite impulse response IIR filter, or a digital multiplier, wherein a decimation factor of the decimator is such that the decimation factor provides an output decimation rate between 350 kilohertz and 1.6 megahertz. an over-sampled analog-to-digital converter ADC with a sample clock of at least 10 megahertz, characterized in that the over-sampled ADC includes: a loop filter that is configured to maintain a noise power spectral density that does not exceed 3 decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above characterized in that the loop filter is configured to compare an input signal with a quantized output signal that is produced by a quantizer and fed back into the loop filter, frequency weigh differences between the input and quantized output signals based on the comparison, and provide a result of the frequency weighing to the quantizer which generates the quantized output signal that is fed back into the loop filter, and a digital filter and decimator configured to remove quantization noise characterized in that the digital filter and decimator are configured to receive the quantized output signal and remove quantization noise using at least one of a bit shifter, a cascaded integrator-comb CIC filter, an infinite impulse response IIR filter, or a digital multiplier, wherein a decimation factor of the decimator is such that the decimation factor provides an output decimation rate between 350 kilohertz and 1.6 megahertz. a loop filter that is configured to maintain a noise power spectral density that does not exceed 3 decibels above a minimum noise floor, of the noise power spectral density, at 80 kilohertz or above characterized in that the loop filter is configured to compare an input signal with a quantized output signal that is produced by a quantizer and fed back into the loop filter, frequency weigh differences between the input and quantized output signals based on the comparison, and provide a result of the frequency weighing to the quantizer which generates the quantized output signal that is fed back into the loop filter, and a digital filter and decimator configured to remove quantization noise characterized in that the digital filter and decimator are configured to receive the quantized output signal and remove quantization noise using at least one of a bit shifter, a cascaded integrator-comb CIC filter, an infinite impulse response IIR filter, or a digital multiplier, wherein a decimation factor of the decimator is such that the decimation factor provides an output decimation rate between 350 kilohertz and 1.6 megahertz.