A capacitance detecting circuit for fingerprint detection, comprising: a pixel sensing circuit that includes a sensing conducting layer that interfaces with an object to form a capacitance with the object; a first capacitor (C1, Ccs) coupled to the pixel sensing circuit and coupled to a ground via a first switch; an integrator electrically coupled to the first capacitor (C1, Ccs) and configured to generate an integrating output voltage (Vpo), the integrator including: a first single-ended amplifier, including: an integrating output terminal configured to output the integrating output voltage (Vpo), and a first input terminal coupled to the first capacitor (C1, Ccs), and at least one integration capacitor (Cint_1, Cint_2, Cint_3, Cint_4, Cint) coupled to the first input terminal; a second capacitor; a second switch between the second capacitor and the first input terminal of the integrator; a third switch to couple the second capacitor to a voltage generator; a fourth switch to couple the second capacitor to a ground; and a comparator coupled to the integrating output terminal of the first single-ended amplifier and configured to generate a comparing output(Vo_cmp) indicative of the capacitance between the sensing conducting layer and the object by comparing the integrating output voltage (Vpo) and a reference voltage (Vr); wherein the second switch is configured to turn on and off based on the comparing output (Vo_cmp) to provide an electrical connection between the second capacitor and the integrator; wherein the second switch and the fourth switch are controlled to be ON when the comparing output (Vo_cmp) indicates that the integrating output voltage (Vpo) is smaller than the reference voltage (Vr). a pixel sensing circuit that includes a sensing conducting layer that interfaces with an object to form a capacitance with the object; a first capacitor (C1, Ccs) coupled to the pixel sensing circuit and coupled to a ground via a first switch; an integrator electrically coupled to the first capacitor (C1, Ccs) and configured to generate an integrating output voltage (Vpo), the integrator including: a first single-ended amplifier, including: an integrating output terminal configured to output the integrating output voltage (Vpo), and a first input terminal coupled to the first capacitor (C1, Ccs), and at least one integration capacitor (Cint_1, Cint_2, Cint_3, Cint_4, Cint) coupled to the first input terminal; a first single-ended amplifier, including: an integrating output terminal configured to output the integrating output voltage (Vpo), and a first input terminal coupled to the first capacitor (C1, Ccs), and an integrating output terminal configured to output the integrating output voltage (Vpo), and a first input terminal coupled to the first capacitor (C1, Ccs), and at least one integration capacitor (Cint_1, Cint_2, Cint_3, Cint_4, Cint) coupled to the first input terminal; a second capacitor; a second switch between the second capacitor and the first input terminal of the integrator; a third switch to couple the second capacitor to a voltage generator; a fourth switch to couple the second capacitor to a ground; and a comparator coupled to the integrating output terminal of the first single-ended amplifier and configured to generate a comparing output(Vo_cmp) indicative of the capacitance between the sensing conducting layer and the object by comparing the integrating output voltage (Vpo) and a reference voltage (Vr); wherein the second switch is configured to turn on and off based on the comparing output (Vo_cmp) to provide an electrical connection between the second capacitor and the integrator; wherein the second switch and the fourth switch are controlled to be ON when the comparing output (Vo_cmp) indicates that the integrating output voltage (Vpo) is smaller than the reference voltage (Vr).