A method of forming an nMOS or a pMOS nanowire field-effect transistor, the method comprising: receiving a substrate with a semiconductor seeding surface; forming a hardmask fin over the seeding surface; forming an isolation region adjacent opposing sides of the hardmask fin; forming a stack of semiconductor layers in a trench with the seeding surface at the bottom of the trench by: removing the hardmask fin, epitaxially growing said stack of semiconductor layers comprising an intervening semiconductor device layer on the seeding surface within the trench, the intervening device layer having at least one of a lattice constant mismatch, or coefficient of thermal expansion, CTE, mismatch, with the semiconductor seeding surface, and alternatingly growing at least two pMOS nanowire layers (280A, 280B) and at least two nMOS nanowire layers (290A, 290B), recessing the isolation region from a top surface to expose sidewalls of the at least two pMOS nanowire layers (280A, 280B) and the at least two nMOS nanowire layers; etching either the at least two nMOS nanowire layers or the at least two pMOS nanowire layers of the exposed semiconductor layers; depositing a first gate dielectric layer and a first gate electrode material surrounding the remaining of said nMOS and pMOS nanowire channel layers; wherein the nanowire FET comprises: a first source region and a first drain region with a vertical stack of said remaining semiconductor pMOS or nMOS nanowire channel layers (280A, 280B, 290A, 290B) disposed there between and disposed over a first planar semiconductor seeding surface, said remaining pMOS or nMOS nanowire channels being made of Germanium or of a III-V semiconductor, respectively, and having a composition other than that of the said first planar semiconductor seeding surface the first planar semiconductor seeding surface being a top surface of a semiconductor mesa surrounded by said isolation region. receiving a substrate with a semiconductor seeding surface; forming a hardmask fin over the seeding surface; forming an isolation region adjacent opposing sides of the hardmask fin; forming a stack of semiconductor layers in a trench with the seeding surface at the bottom of the trench by: removing the hardmask fin, epitaxially growing said stack of semiconductor layers comprising an intervening semiconductor device layer on the seeding surface within the trench, the intervening device layer having at least one of a lattice constant mismatch, or coefficient of thermal expansion, CTE, mismatch, with the semiconductor seeding surface, and alternatingly growing at least two pMOS nanowire layers (280A, 280B) and at least two nMOS nanowire layers (290A, 290B), recessing the isolation region from a top surface to expose sidewalls of the at least two pMOS nanowire layers (280A, 280B) and the at least two nMOS nanowire layers; etching either the at least two nMOS nanowire layers or the at least two pMOS nanowire layers of the exposed semiconductor layers; depositing a first gate dielectric layer and a first gate electrode material surrounding the remaining of said nMOS and pMOS nanowire channel layers; wherein the nanowire FET comprises: a first source region and a first drain region with a vertical stack of said remaining semiconductor pMOS or nMOS nanowire channel layers (280A, 280B, 290A, 290B) disposed there between and disposed over a first planar semiconductor seeding surface, said remaining pMOS or nMOS nanowire channels being made of Germanium or of a III-V semiconductor, respectively, and having a composition other than that of the said first planar semiconductor seeding surface the first planar semiconductor seeding surface being a top surface of a semiconductor mesa surrounded by said isolation region. removing the hardmask fin, epitaxially growing said stack of semiconductor layers comprising an intervening semiconductor device layer on the seeding surface within the trench, the intervening device layer having at least one of a lattice constant mismatch, or coefficient of thermal expansion, CTE, mismatch, with the semiconductor seeding surface, and alternatingly growing at least two pMOS nanowire layers (280A, 280B) and at least two nMOS nanowire layers (290A, 290B), recessing the isolation region from a top surface to expose sidewalls of the at least two pMOS nanowire layers (280A, 280B) and the at least two nMOS nanowire layers; etching either the at least two nMOS nanowire layers or the at least two pMOS nanowire layers of the exposed semiconductor layers; depositing a first gate dielectric layer and a first gate electrode material surrounding the remaining of said nMOS and pMOS nanowire channel layers; wherein the nanowire FET comprises: a first source region and a first drain region with a vertical stack of said remaining semiconductor pMOS or nMOS nanowire channel layers (280A, 280B, 290A, 290B) disposed there between and disposed over a first planar semiconductor seeding surface, said remaining pMOS or nMOS nanowire channels being made of Germanium or of a III-V semiconductor, respectively, and having a composition other than that of the said first planar semiconductor seeding surface the first planar semiconductor seeding surface being a top surface of a semiconductor mesa surrounded by said isolation region.