A semiconductor device, comprising: first and second central processing units (CPU 0, CPU 3); and a set of monitoring registers provided inside or outside the second central processing unit, for receiving information representing an internal state of the first central processing unit, whereby the semiconductor device is configured to transfer said information from the first central processing unit (CPU 0) during execution of a program, and whereby said set of monitoring registers is configured to hold the transferred information, the set of monitoring registers being mapped in a memory space of the second central processing unit (CPU 3); wherein: the first central processing unit (CPU 0) includes a first core circuit (10_0) for executing the program; the second central processing unit (CPU 3) includes a second core circuit (10_3) for executing the program; and the second central processing unit (CPU 3) is capable of reading the information held in the set of monitoring registers by executing a command; characterized in that: the set of monitoring registers includes a first monitoring register; and in that the semiconductor device is further configured to update a value of the first monitoring register, only when a value transferred from the first central processing unit (CPU 0) has changed, with information before said change. first and second central processing units (CPU 0, CPU 3); and a set of monitoring registers provided inside or outside the second central processing unit, for receiving information representing an internal state of the first central processing unit, whereby the semiconductor device is configured to transfer said information from the first central processing unit (CPU 0) during execution of a program, and whereby said set of monitoring registers is configured to hold the transferred information, the set of monitoring registers being mapped in a memory space of the second central processing unit (CPU 3); wherein: the first central processing unit (CPU 0) includes a first core circuit (10_0) for executing the program; the second central processing unit (CPU 3) includes a second core circuit (10_3) for executing the program; and the second central processing unit (CPU 3) is capable of reading the information held in the set of monitoring registers by executing a command; the first central processing unit (CPU 0) includes a first core circuit (10_0) for executing the program; the second central processing unit (CPU 3) includes a second core circuit (10_3) for executing the program; and the second central processing unit (CPU 3) is capable of reading the information held in the set of monitoring registers by executing a command; characterized in that: the set of monitoring registers includes a first monitoring register; and in that the semiconductor device is further configured to update a value of the first monitoring register, only when a value transferred from the first central processing unit (CPU 0) has changed, with information before said change. the set of monitoring registers includes a first monitoring register; and in that the semiconductor device is further configured to update a value of the first monitoring register, only when a value transferred from the first central processing unit (CPU 0) has changed, with information before said change.