A processing node, connected to another processing node (205, 305), comprising a processing unit and a first transactional cache, wherein the first transactional cache is connected to the processing unit by using a first interface; the processing unit is configured to: obtain an operation instruction in a transaction, wherein the operation instruction carries a destination address, and the destination address is an address in an internal memory to be accessed by the operation instruction; determine that the operation instruction is an instruction of a transaction for accessing shared data, wherein the shared data is data that can be accessed by both the processing node and the another processing node; and access the first transactional cache based on the foregoing determining, wherein the first transactional cache is configured to cache only shared data of a transaction that is being processed by the processing node (105, 205, 305); and the first transactional cache is further configured to: determine that the destination address fails to hit a cache line in the first transactional cache; send the destination address to a second transactional cache in the another processing node (205, 305); receive status information that is of a cache line hit by the destination address and that is returned by the second transactional cache in the another processing node, wherein the shared data is cached in the cache line hit by the destination address, and the status information is used to indicate an access status of the shared data in the second transactional cache in the another processing node (205, 305); and determine, based on the status information, whether the operation instruction conflicts with an operation instruction that is being executed by the another processing node (205, 305). the processing unit is configured to: obtain an operation instruction in a transaction, wherein the operation instruction carries a destination address, and the destination address is an address in an internal memory to be accessed by the operation instruction; determine that the operation instruction is an instruction of a transaction for accessing shared data, wherein the shared data is data that can be accessed by both the processing node and the another processing node; and access the first transactional cache based on the foregoing determining, wherein the first transactional cache is configured to cache only shared data of a transaction that is being processed by the processing node (105, 205, 305); and obtain an operation instruction in a transaction, wherein the operation instruction carries a destination address, and the destination address is an address in an internal memory to be accessed by the operation instruction; determine that the operation instruction is an instruction of a transaction for accessing shared data, wherein the shared data is data that can be accessed by both the processing node and the another processing node; and access the first transactional cache based on the foregoing determining, wherein the first transactional cache is configured to cache only shared data of a transaction that is being processed by the processing node (105, 205, 305); and the first transactional cache is further configured to: determine that the destination address fails to hit a cache line in the first transactional cache; send the destination address to a second transactional cache in the another processing node (205, 305); receive status information that is of a cache line hit by the destination address and that is returned by the second transactional cache in the another processing node, wherein the shared data is cached in the cache line hit by the destination address, and the status information is used to indicate an access status of the shared data in the second transactional cache in the another processing node (205, 305); and determine, based on the status information, whether the operation instruction conflicts with an operation instruction that is being executed by the another processing node (205, 305). determine that the destination address fails to hit a cache line in the first transactional cache; send the destination address to a second transactional cache in the another processing node (205, 305); receive status information that is of a cache line hit by the destination address and that is returned by the second transactional cache in the another processing node, wherein the shared data is cached in the cache line hit by the destination address, and the status information is used to indicate an access status of the shared data in the second transactional cache in the another processing node (205, 305); and determine, based on the status information, whether the operation instruction conflicts with an operation instruction that is being executed by the another processing node (205, 305).