Sampler circuitry (300, 400) configured to operate based on a differential input voltage signal provided between first and second input nodes (314 A, 314 B), the sampler circuitry (300, 400) comprising: load circuitry comprising sampler switching transistors (340 A0, 340 A1, 340 AN-1, 340 B0, 340 B1, 340 BN-1) configured to sample first and second load currents which define a differential current signal, the load circuitry having first and second load nodes (316 A, 316 B) and a biasing node, wherein the source terminal of each sampler switching transistor (340 A0, 340 A1, 340A N-1, 340 B0, 340 B1, 340 BN-1) is connected to either the first or second load node(316A, 316B); a power supply node (V H) for connection to a voltage source; a first current path (300 A) extending from the power supply node (V H) to the first load node (316 A) to provide the first load current at the first load node (316 A) for use by the load circuitry, wherein a first supply-connection impedance (320 A) as the first current path (300 A) connects the power supply node (V H) to the first load node (316 A); a second current path (300 B) extending, in parallel with the first current path (300 A), from the power supply node (V H) to the second load node (316 B) to provide the second load current at the second load node (316 B) for use by the load circuitry, wherein a second supply-connection impedance (320 B) as the second current path (300 B) connects the power supply node (V H) to the second load node (316 B); first and second input-connection impedances (330 A, 330 B); and control circuitry, wherein: the control circuitry is configured, based on measurement of a common mode voltage indicative of a common mode between voltages at the first and second load nodes (316 A, 316 B), to control a biasing signal provided to the biasing node of the load circuitry, wherein the biasing signal controls the DC voltage level of gate-control-switching signals provided to the gate terminals of the switching transistors to regulate the common mode voltage the first and second input nodes (314 A, 314 B) are connected to the first and second load nodes (316 A, 316 B) via the first and second input-connection impedances (330 A, 330 B), respectively, so that the differential current signal is dependent on the differential input voltage signal; and the first and second input-connection impedances (330 A, 330 B) and the first and second supply-connection impedances (320 A, 320 B) are passive impedances. load circuitry comprising sampler switching transistors (340 A0, 340 A1, 340 AN-1, 340 B0, 340 B1, 340 BN-1) configured to sample first and second load currents which define a differential current signal, the load circuitry having first and second load nodes (316 A, 316 B) and a biasing node, wherein the source terminal of each sampler switching transistor (340 A0, 340 A1, 340A N-1, 340 B0, 340 B1, 340 BN-1) is connected to either the first or second load node(316A, 316B); a power supply node (V H) for connection to a voltage source; a first current path (300 A) extending from the power supply node (V H) to the first load node (316 A) to provide the first load current at the first load node (316 A) for use by the load circuitry, wherein a first supply-connection impedance (320 A) as the first current path (300 A) connects the power supply node (V H) to the first load node (316 A); a second current path (300 B) extending, in parallel with the first current path (300 A), from the power supply node (V H) to the second load node (316 B) to provide the second load current at the second load node (316 B) for use by the load circuitry, wherein a second supply-connection impedance (320 B) as the second current path (300 B) connects the power supply node (V H) to the second load node (316 B); first and second input-connection impedances (330 A, 330 B); and control circuitry, wherein: the control circuitry is configured, based on measurement of a common mode voltage indicative of a common mode between voltages at the first and second load nodes (316 A, 316 B), to control a biasing signal provided to the biasing node of the load circuitry, wherein the biasing signal controls the DC voltage level of gate-control-switching signals provided to the gate terminals of the switching transistors to regulate the common mode voltage the first and second input nodes (314 A, 314 B) are connected to the first and second load nodes (316 A, 316 B) via the first and second input-connection impedances (330 A, 330 B), respectively, so that the differential current signal is dependent on the differential input voltage signal; and the first and second input-connection impedances (330 A, 330 B) and the first and second supply-connection impedances (320 A, 320 B) are passive impedances. the control circuitry is configured, based on measurement of a common mode voltage indicative of a common mode between voltages at the first and second load nodes (316 A, 316 B), to control a biasing signal provided to the biasing node of the load circuitry, wherein the biasing signal controls the DC voltage level of gate-control-switching signals provided to the gate terminals of the switching transistors to regulate the common mode voltage the first and second input nodes (314 A, 314 B) are connected to the first and second load nodes (316 A, 316 B) via the first and second input-connection impedances (330 A, 330 B), respectively, so that the differential current signal is dependent on the differential input voltage signal; and the first and second input-connection impedances (330 A, 330 B) and the first and second supply-connection impedances (320 A, 320 B) are passive impedances.