A display apparatus having a display area and a peripheral area, characterized by comprising: a plurality of gate lines; a plurality of data lines; an insulating layer between the plurality of gate lines and the plurality of data lines; a gate-driver-on-array circuit in the peripheral area comprising N numbers of shift register units for respectively outputting a plurality of gate scanning signals to the plurality of gate lines; a plurality of multiplexers; and a plurality of clock terminals, wherein an n-th shift register unit of the N numbers of shift register units comprises an input port for receiving an input signal from an output port of a m-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p-th shift register unit through a reset signal line, 1 ≤ m < n < p ≤ N; at least one of the input signal line and the reset signal line comprises a first segment in a same layer as the plurality of gate lines, and a second segment in a same layer as the plurality of data lines; and the first segment and the second segment are electrically connected to each other through a via extending through the insulating layer, wherein the N numbers of shift register units are in a first region of the peripheral area; the input signal line for the n-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer; and the reset signal line for the n-th shift register unit comprises a first reset signal line segment in a same layer as the plurality of gate lines, and a second reset signal line segment in a same layer as the plurality of data lines, the first reset signal line segment and the second reset signal line segment electrically connected to each other through a via extending through the insulating layer, wherein each of the plurality of clock terminals is electrically connected to one of the plurality of data lines; each of the plurality of clock terminals is electrically connected to one of the plurality of multiplexers through a connection line; the connection line is in a same layer as the plurality of gate lines, the first input signal line segment, and the first reset signal line segment; and the connection line crosses over the second input signal line segment and the second reset signal line segment. a plurality of gate lines; a plurality of data lines; an insulating layer between the plurality of gate lines and the plurality of data lines; a gate-driver-on-array circuit in the peripheral area comprising N numbers of shift register units for respectively outputting a plurality of gate scanning signals to the plurality of gate lines; a plurality of multiplexers; and a plurality of clock terminals, wherein an n-th shift register unit of the N numbers of shift register units comprises an input port for receiving an input signal from an output port of a m-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p-th shift register unit through a reset signal line, 1 ≤ m < n < p ≤ N; at least one of the input signal line and the reset signal line comprises a first segment in a same layer as the plurality of gate lines, and a second segment in a same layer as the plurality of data lines; and the first segment and the second segment are electrically connected to each other through a via extending through the insulating layer, wherein the N numbers of shift register units are in a first region of the peripheral area; the input signal line for the n-th shift register unit comprises a first input signal line segment in a same layer as the plurality of gate lines, and a second input signal line segment in a same layer as the plurality of data lines, the first input signal line segment and the second input signal line segment electrically connected to each other through a via extending through the insulating layer; and the reset signal line for the n-th shift register unit comprises a first reset signal line segment in a same layer as the plurality of gate lines, and a second reset signal line segment in a same layer as the plurality of data lines, the first reset signal line segment and the second reset signal line segment electrically connected to each other through a via extending through the insulating layer, wherein each of the plurality of clock terminals is electrically connected to one of the plurality of data lines; each of the plurality of clock terminals is electrically connected to one of the plurality of multiplexers through a connection line; the connection line is in a same layer as the plurality of gate lines, the first input signal line segment, and the first reset signal line segment; and the connection line crosses over the second input signal line segment and the second reset signal line segment.