A system comprising: a processing unit having a core configured to execute instructions; and a host processing unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein each instruction of the set of instructions includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions determined to be executed in parallel; and provide the set of instructions to the processing unit for the core to execute, wherein the core is configured to: determine whether an instruction is the last instruction of the set of instructions based on an indication bit associated with the instruction; the system characterized in that the core is further configured: in response to the determination that the instruction is not the last instruction of the set of instructions, fetch a subsequent instruction of the set of instructions; or in response to the determination that the instruction is the last instruction of the set of instructions, wait until the instructions of the set of instructions have finished executing without fetching another instruction. a processing unit having a core configured to execute instructions; and a host processing unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein each instruction of the set of instructions includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions determined to be executed in parallel; and provide the set of instructions to the processing unit for the core to execute, compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein each instruction of the set of instructions includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions determined to be executed in parallel; and provide the set of instructions to the processing unit for the core to execute, wherein the core is configured to: determine whether an instruction is the last instruction of the set of instructions based on an indication bit associated with the instruction; the system characterized in that the core is further configured: in response to the determination that the instruction is not the last instruction of the set of instructions, fetch a subsequent instruction of the set of instructions; or in response to the determination that the instruction is the last instruction of the set of instructions, wait until the instructions of the set of instructions have finished executing without fetching another instruction. in response to the determination that the instruction is not the last instruction of the set of instructions, fetch a subsequent instruction of the set of instructions; or in response to the determination that the instruction is the last instruction of the set of instructions, wait until the instructions of the set of instructions have finished executing without fetching another instruction.