A dynamic set associative cache apparatus for a processor, comprising: a plurality of cache ways, wherein each cache way comprises the same number of cache blocks, and each cache block comprises a tag block and a data block, and has an index, wherein cache blocks having the same index form a cache set; and characterised by: a table unit recording a valid/invalid bit of each cache block, wherein the valid/invalid bit of each cache block is used to indicate whether each cache block is valid or invalid; and wherein when the processor performs a read access to a cache set on the cache apparatus, the valid/invalid bit of each cache block in the cache set to be accessed is obtained by checking the table unit, and the cache apparatus is configured to set an enable/disable bit of a cache way in which a cache block with an invalid bit in the cache set to be accessed is located, to be disabled and to set the enable/disable bit of a cache way in which a cache block with an valid bit in the cache set to be accessed is located, to be enabled, to read the cache blocks with the valid bit in the cache set to be accessed, and to read data from the data block in the cache block with the valid bit whose tag block matches a tag section in the memory address of the read access comprising an index section for indexing the cache set to be accessed. a plurality of cache ways, wherein each cache way comprises the same number of cache blocks, and each cache block comprises a tag block and a data block, and has an index, wherein cache blocks having the same index form a cache set; and characterised by: a table unit recording a valid/invalid bit of each cache block, wherein the valid/invalid bit of each cache block is used to indicate whether each cache block is valid or invalid; and wherein when the processor performs a read access to a cache set on the cache apparatus, the valid/invalid bit of each cache block in the cache set to be accessed is obtained by checking the table unit, and the cache apparatus is configured to set an enable/disable bit of a cache way in which a cache block with an invalid bit in the cache set to be accessed is located, to be disabled and to set the enable/disable bit of a cache way in which a cache block with an valid bit in the cache set to be accessed is located, to be enabled, to read the cache blocks with the valid bit in the cache set to be accessed, and to read data from the data block in the cache block with the valid bit whose tag block matches a tag section in the memory address of the read access comprising an index section for indexing the cache set to be accessed. a table unit recording a valid/invalid bit of each cache block, wherein the valid/invalid bit of each cache block is used to indicate whether each cache block is valid or invalid; and wherein when the processor performs a read access to a cache set on the cache apparatus, the valid/invalid bit of each cache block in the cache set to be accessed is obtained by checking the table unit, and the cache apparatus is configured to set an enable/disable bit of a cache way in which a cache block with an invalid bit in the cache set to be accessed is located, to be disabled and to set the enable/disable bit of a cache way in which a cache block with an valid bit in the cache set to be accessed is located, to be enabled, to read the cache blocks with the valid bit in the cache set to be accessed, and to read data from the data block in the cache block with the valid bit whose tag block matches a tag section in the memory address of the read access comprising an index section for indexing the cache set to be accessed.