A clock distribution system comprising: a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal (54, 104), the standing-wave resonator comprising at least one anti-node portion that extends along a length of the standing-wave resonator and wherein each of the at least one anti-node portion comprises a predetermined length of the standing-wave resonator defined by a current amplitude of the sinusoidal clock signal (54, 104) that is between a predetermined current amplitude threshold associated with the sinusoidal clock signal (54, 104) and the peak current amplitude associated with an absolute anti-node (58, 108); and at least one clock line (60,110) interconnecting each of the at least one anti-node portion and an associated circuit, the at least one clock line (60,110) being configured to propagate the sinusoidal clock signal (54, 104) for timing functions associated with the associated circuit; and wherein the at least one clock line (60,110) comprises a plurality of clock lines (60,110) inductively coupled to each of the at least one anti-node portion along the predetermined length of the at least one anti-node portion; characterized by the plurality clock lines (162, 164, 166, 168, 170) being configured to be inductively coupled to a respective anti-node portion at a variable inductance with respect to each other based on a relative position of the respective clock lines (162, 164, 166, 168, 170) along the length of the anti-node portion, such that the amplitude of the sinusoidal clock signal propagated by each of the clock lines (162, 164, 166, 168, 170) is substantially equal. a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal (54, 104), the standing-wave resonator comprising at least one anti-node portion that extends along a length of the standing-wave resonator and wherein each of the at least one anti-node portion comprises a predetermined length of the standing-wave resonator defined by a current amplitude of the sinusoidal clock signal (54, 104) that is between a predetermined current amplitude threshold associated with the sinusoidal clock signal (54, 104) and the peak current amplitude associated with an absolute anti-node (58, 108); and at least one clock line (60,110) interconnecting each of the at least one anti-node portion and an associated circuit, the at least one clock line (60,110) being configured to propagate the sinusoidal clock signal (54, 104) for timing functions associated with the associated circuit; and wherein the at least one clock line (60,110) comprises a plurality of clock lines (60,110) inductively coupled to each of the at least one anti-node portion along the predetermined length of the at least one anti-node portion; characterized by the plurality clock lines (162, 164, 166, 168, 170) being configured to be inductively coupled to a respective anti-node portion at a variable inductance with respect to each other based on a relative position of the respective clock lines (162, 164, 166, 168, 170) along the length of the anti-node portion, such that the amplitude of the sinusoidal clock signal propagated by each of the clock lines (162, 164, 166, 168, 170) is substantially equal.