A memory management system configured to manage an address space, wherein the memory management system comprises: a translation lookaside buffer configured to store a first memory translation table comprising a first plurality of table entries each corresponding with one of a first plurality of virtual memory addresses, wherein: a first table entry of the first plurality of table entries associates a first virtual memory address to a first physical memory address in a first memory device (20, 22, 24), to first access data relating to how frequently the first physical memory address is accessed, and to first type data that identifies a first memory type of the first memory device (20, 22, 24); and the translation lookaside buffer is configured to perform a first table walk in the first memory translation table to search for a virtual memory address received from a processor; and a translation device configured to store a second memory translation table comprising a second plurality of table entries each corresponding with one of a second plurality of virtual memory addresses that is non-overlapping with the first plurality of virtual memory addresses, wherein: a second table entry of the second plurality of table entries associates a second virtual memory address to a second physical memory address in a second memory device (20, 22, 24), to second access data that indicates how frequently the second physical memory address is accessed, and to second type data that identifies a second memory type of the second memory device (20, 22, 24); and the translation device comprises a control unit configured to perform a second table walk in the second memory translation table to search for the virtual memory address received from the processor, wherein the first table walk and the second table walk are performed concurrently. a translation lookaside buffer configured to store a first memory translation table comprising a first plurality of table entries each corresponding with one of a first plurality of virtual memory addresses, wherein: a first table entry of the first plurality of table entries associates a first virtual memory address to a first physical memory address in a first memory device (20, 22, 24), to first access data relating to how frequently the first physical memory address is accessed, and to first type data that identifies a first memory type of the first memory device (20, 22, 24); and the translation lookaside buffer is configured to perform a first table walk in the first memory translation table to search for a virtual memory address received from a processor; and a first table entry of the first plurality of table entries associates a first virtual memory address to a first physical memory address in a first memory device (20, 22, 24), to first access data relating to how frequently the first physical memory address is accessed, and to first type data that identifies a first memory type of the first memory device (20, 22, 24); and the translation lookaside buffer is configured to perform a first table walk in the first memory translation table to search for a virtual memory address received from a processor; and a translation device configured to store a second memory translation table comprising a second plurality of table entries each corresponding with one of a second plurality of virtual memory addresses that is non-overlapping with the first plurality of virtual memory addresses, wherein: a second table entry of the second plurality of table entries associates a second virtual memory address to a second physical memory address in a second memory device (20, 22, 24), to second access data that indicates how frequently the second physical memory address is accessed, and to second type data that identifies a second memory type of the second memory device (20, 22, 24); and the translation device comprises a control unit configured to perform a second table walk in the second memory translation table to search for the virtual memory address received from the processor, wherein the first table walk and the second table walk are performed concurrently. a second table entry of the second plurality of table entries associates a second virtual memory address to a second physical memory address in a second memory device (20, 22, 24), to second access data that indicates how frequently the second physical memory address is accessed, and to second type data that identifies a second memory type of the second memory device (20, 22, 24); and the translation device comprises a control unit configured to perform a second table walk in the second memory translation table to search for the virtual memory address received from the processor, wherein the first table walk and the second table walk are performed concurrently.