An operation adjustment method for a semiconductor device comprising: a semiconductor substrate; a deep N-well formed in the semiconductor substrate; an N-well formed in the deep N-well; a P-well formed in the deep N-well; a semiconductor layer formed in a surface portion of the semiconductor substrate; and a buried dielectric layer formed between the semiconductor layer and the deep N-well to electrically isolate the semiconductor layer and the deep N-well, a pn junction being formed between the N-well and the P-well, a PMOS transistor being formed in the semiconductor layer at a position opposing to the N-well, an NMOS transistor being formed in the semiconductor layer at a position opposing to the P-well, and the method comprising the steps of: (a) obtaining a drain current-substrate bias voltage characteristic of the NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of the PMOS transistor as a voltage obtained by subtracting a built-in potential of the pn junction from the lowest substrate bias voltage; (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit; and (e) adjusting the substrate bias voltage of the PMOS transistor as determined in the (d) step. a semiconductor substrate; a deep N-well formed in the semiconductor substrate; an N-well formed in the deep N-well; a P-well formed in the deep N-well; a semiconductor layer formed in a surface portion of the semiconductor substrate; and a buried dielectric layer formed between the semiconductor layer and the deep N-well to electrically isolate the semiconductor layer and the deep N-well, a pn junction being formed between the N-well and the P-well, a PMOS transistor being formed in the semiconductor layer at a position opposing to the N-well, an NMOS transistor being formed in the semiconductor layer at a position opposing to the P-well, and the method comprising the steps of: (a) obtaining a drain current-substrate bias voltage characteristic of the NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of the PMOS transistor as a voltage obtained by subtracting a built-in potential of the pn junction from the lowest substrate bias voltage; (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit; and (e) adjusting the substrate bias voltage of the PMOS transistor as determined in the (d) step. (a) obtaining a drain current-substrate bias voltage characteristic of the NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of the PMOS transistor as a voltage obtained by subtracting a built-in potential of the pn junction from the lowest substrate bias voltage; (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit; and (e) adjusting the substrate bias voltage of the PMOS transistor as determined in the (d) step.