A stacked chip device comprising: a first stack unit comprising - a plurality of electrode patterns (111, 112) arranged on a face of a non-conductive sheet, - two common electrode patterns (121, 122) configured to be connected to ground, each one of the two common electrode patterns being arranged on a separate non-conductive sheet (102, 103), the two non-conductive sheets (102, 103) being arranged above and respectively below the non-conductive sheet comprising the plurality of electrode patterns (111, 112) such that each of the two common electrode patterns (121, 122) overlaps the plurality of electrode patterns (111, 112); a second stack unit disposed on the first stack unit and comprising a plurality of second conductor patterns (211- 216), a third stack unit disposed under the first stack unit and comprising a plurality of third conductor patterns (311 - 316), the plurality of second and third conductor patterns (211- 216; 311 - 316) being formed on a second and respectively third plurality of non-conductive sheets (201 - 206; 301 - 306) and being respectively connected vertically through vias (511, 512; 521, 522) penetrating through at least some of the second and respectively third plurality of nonconductive sheets, wherein each one of the two common electrode patterns (121, 122), is arranged such as to surround on its corresponding non-conductive sheet, non-conductor regions (711, 712, 713) facing the vias (511, 512; 521, 522), wherein the non-conductor regions expose the non-conductive sheets on which the common electrode patterns are arranged, and have a size greater than that of the vias (511, 512; 521, 522), the stacked chip device being characterised in that the non-conductive sheets (101 - 103) on which the plurality of electrode patterns (111, 112) and the two common electrode patterns (121, 122) are respectively formed have no vias. a first stack unit comprising - a plurality of electrode patterns (111, 112) arranged on a face of a non-conductive sheet, - two common electrode patterns (121, 122) configured to be connected to ground, each one of the two common electrode patterns being arranged on a separate non-conductive sheet (102, 103), the two non-conductive sheets (102, 103) being arranged above and respectively below the non-conductive sheet comprising the plurality of electrode patterns (111, 112) such that each of the two common electrode patterns (121, 122) overlaps the plurality of electrode patterns (111, 112); - a plurality of electrode patterns (111, 112) arranged on a face of a non-conductive sheet, - two common electrode patterns (121, 122) configured to be connected to ground, each one of the two common electrode patterns being arranged on a separate non-conductive sheet (102, 103), the two non-conductive sheets (102, 103) being arranged above and respectively below the non-conductive sheet comprising the plurality of electrode patterns (111, 112) such that each of the two common electrode patterns (121, 122) overlaps the plurality of electrode patterns (111, 112); a second stack unit disposed on the first stack unit and comprising a plurality of second conductor patterns (211- 216), a third stack unit disposed under the first stack unit and comprising a plurality of third conductor patterns (311 - 316), the plurality of second and third conductor patterns (211- 216; 311 - 316) being formed on a second and respectively third plurality of non-conductive sheets (201 - 206; 301 - 306) and being respectively connected vertically through vias (511, 512; 521, 522) penetrating through at least some of the second and respectively third plurality of nonconductive sheets, wherein each one of the two common electrode patterns (121, 122), is arranged such as to surround on its corresponding non-conductive sheet, non-conductor regions (711, 712, 713) facing the vias (511, 512; 521, 522), wherein the non-conductor regions expose the non-conductive sheets on which the common electrode patterns are arranged, and have a size greater than that of the vias (511, 512; 521, 522), the stacked chip device being characterised in that the non-conductive sheets (101 - 103) on which the plurality of electrode patterns (111, 112) and the two common electrode patterns (121, 122) are respectively formed have no vias.