A display device comprising: a display panel having data lines (DL1, DL2,..., DLm), gate lines (GL1, GL2,..., GLn) and a plurality of subpixels, wherein each of the plurality of subpixels exist at intersections of the data lines (DL1, DL2,..., DLm) and the gate lines (GL1, GL2,..., GLn), and each of the plurality of subpixels includes a circuit having a transistor; a timing controller adapted to supply data (DATA) to the subpixels; a plurality of data driver integrated circuits, hereinafter referred to as DICs including a driving section adapted to supply analog data voltages (Vdata) to a plurality of the subpixels and including a sensing section for the plurality of subpixels which the corresponding DIC controls; a digital to analog converter, hereinafter referred to as DAC, disposed within the driving sections of each of the plurality of DICs and adapted to convert the data (DATA) input from the timing controller 140 into the analog data voltages (Vdata); an analog to digital converter, hereinafter referred to as ADC, disposed within the sensing section of each of the plurality of DICS, wherein the ADC disposed in the sensing section of each of the plurality of DICs includes a plurality of sensing channels (CH1, CH2, CH3) and wherein the ADC is adapted to sense voltages (Vsen) in sensing nodes of circuits within the plurality of subpixels, which it controls, through two or more of the sensing channels (CH1, CH2, CH3), and is adapted to convert the sensed voltages (Vsen) into digital sensed data (Dsen); a memory being coupled to the timing controller and at least one of the DICs adapted for storing a lookup table, hereinafter referred to as LUT that includes ADC characteristic information; wherein the timing controller further includes: an ADC compensation circuit adapted to compensate a characteristic of the ADC within each of the plurality of DICs by updating the LUT; and a pixel compensation circuit adapted to compensate a characteristic of the transistor within each of the plurality of subpixels based on the sensed data (Dsen) and according to the lookup table updated by the ADC compensation circuit, wherein in such way the timing controller is adapted to change the data (DATA) to be supplied to the subpixels into changed data (DATA') using the sensed data (Dsen) and according to the LUT and then is adapted to output the changed data (DATA') to the DIC, wherein said digital sensed data (Dsen) converted by the ADC are sent as input to the memory and the LUT is updated on the basis of these digital sensed data (Dsen). a display panel having data lines (DL1, DL2,..., DLm), gate lines (GL1, GL2,..., GLn) and a plurality of subpixels, wherein each of the plurality of subpixels exist at intersections of the data lines (DL1, DL2,..., DLm) and the gate lines (GL1, GL2,..., GLn), and each of the plurality of subpixels includes a circuit having a transistor; a timing controller adapted to supply data (DATA) to the subpixels; a plurality of data driver integrated circuits, hereinafter referred to as DICs including a driving section adapted to supply analog data voltages (Vdata) to a plurality of the subpixels and including a sensing section for the plurality of subpixels which the corresponding DIC controls; a digital to analog converter, hereinafter referred to as DAC, disposed within the driving sections of each of the plurality of DICs and adapted to convert the data (DATA) input from the timing controller 140 into the analog data voltages (Vdata); an analog to digital converter, hereinafter referred to as ADC, disposed within the sensing section of each of the plurality of DICS, wherein the ADC disposed in the sensing section of each of the plurality of DICs includes a plurality of sensing channels (CH1, CH2, CH3) and wherein the ADC is adapted to sense voltages (Vsen) in sensing nodes of circuits within the plurality of subpixels, which it controls, through two or more of the sensing channels (CH1, CH2, CH3), and is adapted to convert the sensed voltages (Vsen) into digital sensed data (Dsen); a memory being coupled to the timing controller and at least one of the DICs adapted for storing a lookup table, hereinafter referred to as LUT that includes ADC characteristic information; wherein the timing controller further includes: an ADC compensation circuit adapted to compensate a characteristic of the ADC within each of the plurality of DICs by updating the LUT; and a pixel compensation circuit adapted to compensate a characteristic of the transistor within each of the plurality of subpixels based on the sensed data (Dsen) and according to the lookup table updated by the ADC compensation circuit, wherein in such way the timing controller is adapted to change the data (DATA) to be supplied to the subpixels into changed data (DATA') using the sensed data (Dsen) and according to the LUT and then is adapted to output the changed data (DATA') to the DIC, wherein said digital sensed data (Dsen) converted by the ADC are sent as input to the memory and the LUT is updated on the basis of these digital sensed data (Dsen).