A processor element, the processor element comprising: a silicon layer; a dielectric layer disposed upon and forming an interface with the silicon layer; a conductive via in contact with the dielectric layer, the conductive via comprising a metallic portion having an interface end in contact with the dielectric layer and a distal end; a second conductive via in contact with the dielectric layer, the second conductive via comprising a second metallic portion having an interface end in contact with the dielectric layer and a distal end; a source electrode; a drain electrode; and two polysilicon gate electrodes (106A, 106B); wherein a cross-sectional area of the interface end of the metallic portion of the conductive via is less than or equal to 100nm by 100nm and a cross-sectional area of the interface end of the second metallic portion of the second conductive via is less than or equal to 100nm by 100nm; wherein the conductive via is electrically connected such that the application of a bias potential to the distal end of the conductive via induces a quantum dot at the interface between the dielectric layer and the silicon layer, the quantum dot for confining one or more electrons or holes in the silicon layer; wherein the second conductive via is electrically connected such that the application of a bias potential to the distal end of the second conductive via induces a second quantum dot at the second interface between the dielectric layer and the silicon layer, the second quantum dot for confining an electron or a hole in the silicon layer; wherein the quantum dot provides a single electron transistor, SET, island formed in the silicon layer between tunnelling junctions connected to the source and the drain electrodes (112A, 112B), wherein the tunnelling between the SET island and the source and drain electrodes is controlled by the potentials applied to the two polysilicon gate electrodes (106A, 106B); wherein the quantum dot and the second quantum dot are proximally located and separated by a quantum tunnelling barrier; and wherein the second quantum dot is for confining an electron or a hole for use as a qubit. a silicon layer; a dielectric layer disposed upon and forming an interface with the silicon layer; a conductive via in contact with the dielectric layer, the conductive via comprising a metallic portion having an interface end in contact with the dielectric layer and a distal end; a second conductive via in contact with the dielectric layer, the second conductive via comprising a second metallic portion having an interface end in contact with the dielectric layer and a distal end; a source electrode; a drain electrode; and two polysilicon gate electrodes (106A, 106B); wherein a cross-sectional area of the interface end of the metallic portion of the conductive via is less than or equal to 100nm by 100nm and a cross-sectional area of the interface end of the second metallic portion of the second conductive via is less than or equal to 100nm by 100nm; wherein the conductive via is electrically connected such that the application of a bias potential to the distal end of the conductive via induces a quantum dot at the interface between the dielectric layer and the silicon layer, the quantum dot for confining one or more electrons or holes in the silicon layer; wherein the second conductive via is electrically connected such that the application of a bias potential to the distal end of the second conductive via induces a second quantum dot at the second interface between the dielectric layer and the silicon layer, the second quantum dot for confining an electron or a hole in the silicon layer; wherein the quantum dot provides a single electron transistor, SET, island formed in the silicon layer between tunnelling junctions connected to the source and the drain electrodes (112A, 112B), wherein the tunnelling between the SET island and the source and drain electrodes is controlled by the potentials applied to the two polysilicon gate electrodes (106A, 106B); wherein the quantum dot and the second quantum dot are proximally located and separated by a quantum tunnelling barrier; and wherein the second quantum dot is for confining an electron or a hole for use as a qubit.