A retimer (130; 231-233; 300; 400; 600) for link equalization, wherein the retimer (130; 231-233; 300; 400; 600) comprises a data channel circuit, a link adjustment circuit (420; 630), and at least two phase locked loops (431, 432), wherein a) the data channel circuit comprises a clock and data recovery circuit, an output buffer, and an equalization circuit (301, 302; 611, 614, 633, 624, 621); b) the data channel circuit is configured to implement, under a function of a currently used phase locked loop (431, 432), equalization processing-based transparent transmission of a signal between a first communications device (110; 210) and a second communications device (120; 220), wherein an equalization processing-based transparent transmission is a transparent transmission in which other processing than equalization processing that changes a format or content of the signal is not performed; c) the link adjustment circuit (420; 630) is configured to obtain the signal transmitted in the data channel circuit; d) the link adjustment circuit (420; 630) is configured to obtain link status information based on the obtained signal; e) the link adjustment circuit (420; 630) is configured to perform equalization adjustment on the equalization circuit (301, 302; 611, 614, 633, 624, 621) when determining, based on the link status information, that the link is in an equalized state; f) the link adjustment circuit (420; 630) is further configured to: when determining, based on the link status information, that a rate of a link needs to be changed, configure in advance of the rate change an operating parameter of a target phase locked loop (431, 432) as an operating parameter corresponding to a changed rate, wherein the target phase locked loop (431, 432) is an unused phase locked loop (431, 432) in the at least two phase locked loops (431, 432); g) the link adjustment circuit (420; 630) is further configured to switch the currently used phase locked loop (431, 432) to the target phase locked loop (431, 432) when detecting that the link enters a rate-changing state; and h) the data channel circuit is further configured to implement, under a function of the target phase locked loop (431, 432), the equalization processing-based transparent transmission of the signal between the first communications device (110; 210) and the second communications device (120; 220). a) the data channel circuit comprises a clock and data recovery circuit, an output buffer, and an equalization circuit (301, 302; 611, 614, 633, 624, 621); b) the data channel circuit is configured to implement, under a function of a currently used phase locked loop (431, 432), equalization processing-based transparent transmission of a signal between a first communications device (110; 210) and a second communications device (120; 220), wherein an equalization processing-based transparent transmission is a transparent transmission in which other processing than equalization processing that changes a format or content of the signal is not performed; c) the link adjustment circuit (420; 630) is configured to obtain the signal transmitted in the data channel circuit; d) the link adjustment circuit (420; 630) is configured to obtain link status information based on the obtained signal; e) the link adjustment circuit (420; 630) is configured to perform equalization adjustment on the equalization circuit (301, 302; 611, 614, 633, 624, 621) when determining, based on the link status information, that the link is in an equalized state; f) the link adjustment circuit (420; 630) is further configured to: when determining, based on the link status information, that a rate of a link needs to be changed, configure in advance of the rate change an operating parameter of a target phase locked loop (431, 432) as an operating parameter corresponding to a changed rate, wherein the target phase locked loop (431, 432) is an unused phase locked loop (431, 432) in the at least two phase locked loops (431, 432); g) the link adjustment circuit (420; 630) is further configured to switch the currently used phase locked loop (431, 432) to the target phase locked loop (431, 432) when detecting that the link enters a rate-changing state; and h) the data channel circuit is further configured to implement, under a function of the target phase locked loop (431, 432), the equalization processing-based transparent transmission of the signal between the first communications device (110; 210) and the second communications device (120; 220).