A system (600; 700) comprising: a non-volatile resistive memory (400; 500; 601) comprising a plurality of portions (401 j; S i,j) of a plurality of pages (P i,j,k) each, the memory comprising first and second ports enabling to simultaneously access two pages of the memory, provided that these pages belong to different portions of the non-volatile resistive memory, each of said portions (401 j; S i,j) comprising a single port (A, d in, d out) of access to the pages in the portion, where the port can be connected to one or the other of the first and second ports of the non-volatile resistive memory via multiplexing circuits (405 j, 407 j, MUX1, MUX2; S1 j, S2 j); and a control circuit (603; 703) capable of implementing, via the second port, a method of managing the wear of the non-volatile resistive memory (400; 500; 601) comprising read and/or write accesses to data stored in the non-volatile resistive memory, by simultaneously allowing user accesses to the non-volatile resistive memory content via the first port, the control circuit (603; 703) being capable of performing an access to a portion (401 j; S i,j) of the non-volatile resistive memory for the wear management method only when no user access is being performed on this portion of the non-volatile resistive memory, characterized in that the control circuit (603; 703) is capable of being clocked by a clock having a frequency higher than that of the non-volatile resistive memory and in that user accesses can be performed at any clock cycle of the control circuit, and of only performing an access to a portion (401 j; S i,j) of the non-volatile resistive memory for the wear management method when a user access is being performed simultaneously on another portion of the non-volatile resistive memory. a non-volatile resistive memory (400; 500; 601) comprising a plurality of portions (401 j; S i,j) of a plurality of pages (P i,j,k) each, the memory comprising first and second ports enabling to simultaneously access two pages of the memory, provided that these pages belong to different portions of the non-volatile resistive memory, each of said portions (401 j; S i,j) comprising a single port (A, d in, d out) of access to the pages in the portion, where the port can be connected to one or the other of the first and second ports of the non-volatile resistive memory via multiplexing circuits (405 j, 407 j, MUX1, MUX2; S1 j, S2 j); and a control circuit (603; 703) capable of implementing, via the second port, a method of managing the wear of the non-volatile resistive memory (400; 500; 601) comprising read and/or write accesses to data stored in the non-volatile resistive memory, by simultaneously allowing user accesses to the non-volatile resistive memory content via the first port, the control circuit (603; 703) being capable of performing an access to a portion (401 j; S i,j) of the non-volatile resistive memory for the wear management method only when no user access is being performed on this portion of the non-volatile resistive memory, characterized in that the control circuit (603; 703) is capable of being clocked by a clock having a frequency higher than that of the non-volatile resistive memory and in that user accesses can be performed at any clock cycle of the control circuit, and of only performing an access to a portion (401 j; S i,j) of the non-volatile resistive memory for the wear management method when a user access is being performed simultaneously on another portion of the non-volatile resistive memory.