A system comprising: a processor including: a coprocessor issue circuit configured to issue coprocessor instructions to an interface circuit for transmission to a coprocessor; and the interface circuit, wherein the interface circuit is coupled to the coprocessor issue circuit and includes a buffer having a plurality of buffer entries, wherein the interface circuit is configured to accumulate, in a buffer entry of the plurality of buffer entries, data describing multiple ones of the coprocessor instructions, wherein the data identifies, for a given one of the multiple coprocessor instructions, an opcode and a payload, and wherein the data includes respective source data specified by one or more of the multiple coprocessor instructions; wherein the interface circuit is further configured to write a command to the buffer entry, close the buffer entry, and transmit the buffer entry's contents to the coprocessor, and wherein the command comprises opcodes corresponding to respective ones of the multiple coprocessor instructions; and the coprocessor, wherein the coprocessor is configured to execute the coprocessor instructions, wherein the coprocessor is configured to execute the coprocessor instructions at up to a first rate, and wherein the interface circuit is configured to provide the coprocessor instructions at an average rate that matches the first rate. a processor including: a coprocessor issue circuit configured to issue coprocessor instructions to an interface circuit for transmission to a coprocessor; and the interface circuit, wherein the interface circuit is coupled to the coprocessor issue circuit and includes a buffer having a plurality of buffer entries, wherein the interface circuit is configured to accumulate, in a buffer entry of the plurality of buffer entries, data describing multiple ones of the coprocessor instructions, wherein the data identifies, for a given one of the multiple coprocessor instructions, an opcode and a payload, and wherein the data includes respective source data specified by one or more of the multiple coprocessor instructions; wherein the interface circuit is further configured to write a command to the buffer entry, close the buffer entry, and transmit the buffer entry's contents to the coprocessor, and wherein the command comprises opcodes corresponding to respective ones of the multiple coprocessor instructions; and a coprocessor issue circuit configured to issue coprocessor instructions to an interface circuit for transmission to a coprocessor; and the interface circuit, wherein the interface circuit is coupled to the coprocessor issue circuit and includes a buffer having a plurality of buffer entries, wherein the interface circuit is configured to accumulate, in a buffer entry of the plurality of buffer entries, data describing multiple ones of the coprocessor instructions, wherein the data identifies, for a given one of the multiple coprocessor instructions, an opcode and a payload, and wherein the data includes respective source data specified by one or more of the multiple coprocessor instructions; wherein the interface circuit is further configured to write a command to the buffer entry, close the buffer entry, and transmit the buffer entry's contents to the coprocessor, and wherein the command comprises opcodes corresponding to respective ones of the multiple coprocessor instructions; and the coprocessor, wherein the coprocessor is configured to execute the coprocessor instructions, wherein the coprocessor is configured to execute the coprocessor instructions at up to a first rate, and wherein the interface circuit is configured to provide the coprocessor instructions at an average rate that matches the first rate.