An apparatus comprising a block-based processor, the block-based processor comprising: one or more processing cores configured to fetch and execute a plurality of instruction blocks wherein the plurality of instruction blocks comprises a first instruction block wherein the first instruction block comprises a plurality of memory store instructions; and a control unit configured, to cause at least one of the processing cores to: retrieve data indicating execution ordering of the plurality of memory store instructions; detect a predicated instruction during instruction execution wherein the predicated instruction is associated with a condition; determine a first memory store instruction of the plurality of memory store instructions wherein the first memory store instruction will not execute when the condition of the predicated instruction is satisfied; generate a nullification instruction, where a target field of the nullification instruction identifies a load/store identifier, LSID, of the first memory store instruction; nullify the first memory store instruction wherein the control unit is further configured to cause at least one of the processing cores to, during the nullifying, mark the LSID of the first memory store instruction as completed as if the first memory store instruction has executed; and issue the predicated instruction. one or more processing cores configured to fetch and execute a plurality of instruction blocks wherein the plurality of instruction blocks comprises a first instruction block wherein the first instruction block comprises a plurality of memory store instructions; and a control unit configured, to cause at least one of the processing cores to: retrieve data indicating execution ordering of the plurality of memory store instructions; detect a predicated instruction during instruction execution wherein the predicated instruction is associated with a condition; determine a first memory store instruction of the plurality of memory store instructions wherein the first memory store instruction will not execute when the condition of the predicated instruction is satisfied; generate a nullification instruction, where a target field of the nullification instruction identifies a load/store identifier, LSID, of the first memory store instruction; nullify the first memory store instruction wherein the control unit is further configured to cause at least one of the processing cores to, during the nullifying, mark the LSID of the first memory store instruction as completed as if the first memory store instruction has executed; and issue the predicated instruction. retrieve data indicating execution ordering of the plurality of memory store instructions; detect a predicated instruction during instruction execution wherein the predicated instruction is associated with a condition; determine a first memory store instruction of the plurality of memory store instructions wherein the first memory store instruction will not execute when the condition of the predicated instruction is satisfied; generate a nullification instruction, where a target field of the nullification instruction identifies a load/store identifier, LSID, of the first memory store instruction; nullify the first memory store instruction wherein the control unit is further configured to cause at least one of the processing cores to, during the nullifying, mark the LSID of the first memory store instruction as completed as if the first memory store instruction has executed; and issue the predicated instruction.