A stress sensor incorporated in a layered structure, the layered structure comprising multiple levels (M n,M n+1) comprising electric conductors (1,3,4) and via connections (7,8) for interconnecting the conductors of different levels, the conductors and via connections of the levels being embedded in layers of a dielectric material, the stress sensor comprising: - A first conductor in a first level (M n) of the layered structure, the first conductor performing the function of the gate electrode of a transistor, - A dielectric layer in contact with the first conductor, said layer performing the function of the gate dielectric of the transistor, - A portion of semiconductor material on the dielectric layer, said portion performing the function of the channel of the transistor, - A first and second via (7,8) in electrical contact with the channel, the first and second via respectively performing the function of source and drain electrodes of the transistor, the vias (7,8) being electrically connected to respective conductors (3,4) in a second level (M n+1) adjacent to the first level (M n), wherein at least one of the vias, hereafter termed 'pseudo-via', is formed of a material whose electrical resistance is sensitive to mechanical stress acting on the layered structure in the direction of the vias, characterised in that: - the resistance of the at least one pseudo-via is sufficiently large to dominate the channel resistance when the transistor is in the ON state, - the sensitivity of the resistance of the at least one pseudo-via to the mechanical stress is such that the sensor enables the measurement of said stress in the direction of the vias by reading out the drain current of the transistor, when the transistor is in the ON state. - A first conductor in a first level (M n) of the layered structure, the first conductor performing the function of the gate electrode of a transistor, - A dielectric layer in contact with the first conductor, said layer performing the function of the gate dielectric of the transistor, - A portion of semiconductor material on the dielectric layer, said portion performing the function of the channel of the transistor, - A first and second via (7,8) in electrical contact with the channel, the first and second via respectively performing the function of source and drain electrodes of the transistor, the vias (7,8) being electrically connected to respective conductors (3,4) in a second level (M n+1) adjacent to the first level (M n), wherein at least one of the vias, hereafter termed 'pseudo-via', is formed of a material whose electrical resistance is sensitive to mechanical stress acting on the layered structure in the direction of the vias, characterised in that: - the resistance of the at least one pseudo-via is sufficiently large to dominate the channel resistance when the transistor is in the ON state, - the sensitivity of the resistance of the at least one pseudo-via to the mechanical stress is such that the sensor enables the measurement of said stress in the direction of the vias by reading out the drain current of the transistor, when the transistor is in the ON state. - the resistance of the at least one pseudo-via is sufficiently large to dominate the channel resistance when the transistor is in the ON state, - the sensitivity of the resistance of the at least one pseudo-via to the mechanical stress is such that the sensor enables the measurement of said stress in the direction of the vias by reading out the drain current of the transistor, when the transistor is in the ON state.