An abnormality detection apparatus for resolver comprising: a resolver that is provided with a first system excitation winding, first system two output windings (111A, 112A), a second system excitation winding, and second system two output windings (111B, 112B), in which magnetic interference occurs between a first system and a second system; a first system excitation unit configured to apply AC voltage of a first period to the first system excitation winding; a second system excitation unit configured to apply the AC voltage of a second period different from the first period, to the second system excitation winding; a first system output signal detection unit configured to detect periodically output signals (V1A_S, V2A_S) of the first system two output windings (111A, 112A) at preliminarily set detection timing; a first system reduction processing unit configured to perform a second period component reduction processing which reduces component of the second period, to detection values of the output signals of the first system two output windings (V1A_S, V2A_S); a first system square sum calculation unit configured to calculate a first system square sum (V1_amp) which is a sum of square values of the detection values of output signals of first system two output windings (V1A_F, V2A_F) after the second period component reduction processing; and a first system abnormality detection unit configured to determine abnormality of first system, based on whether or not the first system square sum (V1_amp) is within a preliminarily set normal range of first system, wherein the second period is set longer than the first period, wherein the first system reduction processing unit, as the second period component reduction processing, is configured to addt the detection values of output signals of first system two output windings (V1A_S, V2A_S) detected at this time detection timing, and the detection values of output signals of first system two output windings (V1A_Sold, V2A_Sold) detected at the detection timing earlier by a first system reduction processing interval (ΔT1) than this time detection timing, wherein when setting the second period to TB, the first system reduction processing interval (ΔT1) is set to TB/2+TB×M (M is an integer greater than or equal to 0), and wherein the first system square sum calculation unit is configured to calculate the first system square sum (V1_amp) which is a sum of square values of the detection values of output signals of first system two output windings (V1A_F, V2A_F) after addition. a resolver that is provided with a first system excitation winding, first system two output windings (111A, 112A), a second system excitation winding, and second system two output windings (111B, 112B), in which magnetic interference occurs between a first system and a second system; a first system excitation unit configured to apply AC voltage of a first period to the first system excitation winding; a second system excitation unit configured to apply the AC voltage of a second period different from the first period, to the second system excitation winding; a first system output signal detection unit configured to detect periodically output signals (V1A_S, V2A_S) of the first system two output windings (111A, 112A) at preliminarily set detection timing; a first system reduction processing unit configured to perform a second period component reduction processing which reduces component of the second period, to detection values of the output signals of the first system two output windings (V1A_S, V2A_S); a first system square sum calculation unit configured to calculate a first system square sum (V1_amp) which is a sum of square values of the detection values of output signals of first system two output windings (V1A_F, V2A_F) after the second period component reduction processing; and a first system abnormality detection unit configured to determine abnormality of first system, based on whether or not the first system square sum (V1_amp) is within a preliminarily set normal range of first system, wherein the second period is set longer than the first period, wherein the first system reduction processing unit, as the second period component reduction processing, is configured to addt the detection values of output signals of first system two output windings (V1A_S, V2A_S) detected at this time detection timing, and the detection values of output signals of first system two output windings (V1A_Sold, V2A_Sold) detected at the detection timing earlier by a first system reduction processing interval (ΔT1) than this time detection timing, wherein when setting the second period to TB, the first system reduction processing interval (ΔT1) is set to TB/2+TB×M (M is an integer greater than or equal to 0), and wherein the first system square sum calculation unit is configured to calculate the first system square sum (V1_amp) which is a sum of square values of the detection values of output signals of first system two output windings (V1A_F, V2A_F) after addition.