An amplifier, comprising: a pair of transistors (CG FET, CS FET) arranged in a cascode amplifier arrangement, the pair of transistors serially connected between a first voltage source (Vdd) and a ground potential, and wherein an input RF signal is fed to a control electrode of a first one of the pair of transistors (CS FET) to produce an amplified RF signal at an output electrode of a second one of the pair of transistors (CG FET); and a DC bias regulator, comprising: a DC bias circuit comprising a reference transistor (Q Ref) connected as a current source, the reference transistor serially connected between a second voltage source (Vss) and the ground potential through a grounded resistor (R1, R1a), the current source configured to produce a reference current (I REF) that passes through the grounded resistor (R1, R1a) to produce a reference voltage (Vg_cs) at the control electrode of the first one of the pair of transistors (CS FET); and a voltage combiner having a pair of inputs (20, 22), a first one of the pair of inputs being coupled to the reference voltage (Vg_cs) and a second one of the pair of inputs being coupled to the first voltage source (Vdd) to produce a DC bias voltage (Vg_cg) at a control electrode of the second one of the pair of transistors (CG FET) related to a combination of the reference voltage (Vg_cs) and the first voltage source (Vdd); wherein the voltage combiner includes a pair of resistors (Rx, Ry), and wherein a first one of the pair of resistors (Rx) is connected between the first one of the pair of inputs and an output of the combiner and a second one of the pair of resistors (Ry) is connected between a second one of the pair of inputs and the output of the combiner, and wherein the reference transistor (Q REF), the first one of the pair of transistors (CS FET), and the second one of the pair of transistors (CG FET) are all formed in near proximity on the same integrated circuit, so that both the semiconductor material properties and environmental conditions are the same for the three transistors. a pair of transistors (CG FET, CS FET) arranged in a cascode amplifier arrangement, the pair of transistors serially connected between a first voltage source (Vdd) and a ground potential, and wherein an input RF signal is fed to a control electrode of a first one of the pair of transistors (CS FET) to produce an amplified RF signal at an output electrode of a second one of the pair of transistors (CG FET); and a DC bias regulator, comprising: a DC bias circuit comprising a reference transistor (Q Ref) connected as a current source, the reference transistor serially connected between a second voltage source (Vss) and the ground potential through a grounded resistor (R1, R1a), the current source configured to produce a reference current (I REF) that passes through the grounded resistor (R1, R1a) to produce a reference voltage (Vg_cs) at the control electrode of the first one of the pair of transistors (CS FET); and a voltage combiner having a pair of inputs (20, 22), a first one of the pair of inputs being coupled to the reference voltage (Vg_cs) and a second one of the pair of inputs being coupled to the first voltage source (Vdd) to produce a DC bias voltage (Vg_cg) at a control electrode of the second one of the pair of transistors (CG FET) related to a combination of the reference voltage (Vg_cs) and the first voltage source (Vdd); a DC bias circuit comprising a reference transistor (Q Ref) connected as a current source, the reference transistor serially connected between a second voltage source (Vss) and the ground potential through a grounded resistor (R1, R1a), the current source configured to produce a reference current (I REF) that passes through the grounded resistor (R1, R1a) to produce a reference voltage (Vg_cs) at the control electrode of the first one of the pair of transistors (CS FET); and a voltage combiner having a pair of inputs (20, 22), a first one of the pair of inputs being coupled to the reference voltage (Vg_cs) and a second one of the pair of inputs being coupled to the first voltage source (Vdd) to produce a DC bias voltage (Vg_cg) at a control electrode of the second one of the pair of transistors (CG FET) related to a combination of the reference voltage (Vg_cs) and the first voltage source (Vdd); wherein the voltage combiner includes a pair of resistors (Rx, Ry), and wherein a first one of the pair of resistors (Rx) is connected between the first one of the pair of inputs and an output of the combiner and a second one of the pair of resistors (Ry) is connected between a second one of the pair of inputs and the output of the combiner, and wherein the reference transistor (Q REF), the first one of the pair of transistors (CS FET), and the second one of the pair of transistors (CG FET) are all formed in near proximity on the same integrated circuit, so that both the semiconductor material properties and environmental conditions are the same for the three transistors.