A multi-core processor system comprising: a plurality of cores; a shared memory configured to be accessed by the cores; and an arbiter circuit configured to arbitrate, using calculated ratios of access rights of the cores to access the shared memory, contention of right to access the shared memory by the cores, wherein the multi-core processor system further comprises: an acquiring unit configured to acquire, for each of the cores, a measured speed of access to the shared memory, the speed at which each core accesses the shared memory is measured when software does not come to an end within an estimated time period; a first calculating unit configured to calculate, for each of the cores, a response performance based on the measured speeds of access acquired by the acquiring unit and a theoretical speed of access for each of the cores; a second calculating unit configured to calculate, for the cores and based on the response performance calculated by the first calculating unit for each of the cores, ratios of access rights to access the shared memory, the second calculating unit calculating the ratios such that a ratio of access rights of a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and a notifying unit configured to notify the arbiter circuit of the calculated ratios of access rights of the cores to access the shared memory. a plurality of cores; a shared memory configured to be accessed by the cores; and an arbiter circuit configured to arbitrate, using calculated ratios of access rights of the cores to access the shared memory, contention of right to access the shared memory by the cores, wherein the multi-core processor system further comprises: an acquiring unit configured to acquire, for each of the cores, a measured speed of access to the shared memory, the speed at which each core accesses the shared memory is measured when software does not come to an end within an estimated time period; a first calculating unit configured to calculate, for each of the cores, a response performance based on the measured speeds of access acquired by the acquiring unit and a theoretical speed of access for each of the cores; a second calculating unit configured to calculate, for the cores and based on the response performance calculated by the first calculating unit for each of the cores, ratios of access rights to access the shared memory, the second calculating unit calculating the ratios such that a ratio of access rights of a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and a notifying unit configured to notify the arbiter circuit of the calculated ratios of access rights of the cores to access the shared memory. an acquiring unit configured to acquire, for each of the cores, a measured speed of access to the shared memory, the speed at which each core accesses the shared memory is measured when software does not come to an end within an estimated time period; a first calculating unit configured to calculate, for each of the cores, a response performance based on the measured speeds of access acquired by the acquiring unit and a theoretical speed of access for each of the cores; a second calculating unit configured to calculate, for the cores and based on the response performance calculated by the first calculating unit for each of the cores, ratios of access rights to access the shared memory, the second calculating unit calculating the ratios such that a ratio of access rights of a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and a notifying unit configured to notify the arbiter circuit of the calculated ratios of access rights of the cores to access the shared memory.