A method for performing a convolution operation on an image using a reconfigurable convolution engine comprising a processor and an adder engine, the method comprising: receiving, by the processor, image data for performing a convolution operation on an image by using a convolution engine, the image data comprising a convolution layer to be performed on the image; determining, by the processor, a kernel size based on the image data, clock speed associated to the convolution engine and number of available on-chip resources; generating, by the processor, a plurality of instances based on the kernel size, wherein each instance comprises a respective multiplier of a reconfigurable multiplier engine comprised in the reconfigurable convolution engine, wherein the reconfigurable multiplier engine is segmented into the plurality of the instances having size MxM that is equal to the kernel size, wherein the plurality of instances is configured to operate in parallel mode, and wherein each instance of the plurality of instances is configured to perform convolution operation with the clock speed of the convolution engine, and wherein each instance of the plurality of instances is represented as a unique identification number; configuring, by the processor, the adder engine based on the plurality of instances, wherein the adder engine comprises a plurality of adders configured to operate in a pipelined structure and in parallel with the plurality of instances; executing, by the processor, the convolution operation on each of the plurality of instances and the adder engine; and filtering, by the processor, an output of the convolution operation by using a filter function configured to operate on a predefined threshold function thereby performing the convolution operation on the image using the reconfigurable convolution engine. receiving, by the processor, image data for performing a convolution operation on an image by using a convolution engine, the image data comprising a convolution layer to be performed on the image; determining, by the processor, a kernel size based on the image data, clock speed associated to the convolution engine and number of available on-chip resources; generating, by the processor, a plurality of instances based on the kernel size, wherein each instance comprises a respective multiplier of a reconfigurable multiplier engine comprised in the reconfigurable convolution engine, wherein the reconfigurable multiplier engine is segmented into the plurality of the instances having size MxM that is equal to the kernel size, wherein the plurality of instances is configured to operate in parallel mode, and wherein each instance of the plurality of instances is configured to perform convolution operation with the clock speed of the convolution engine, and wherein each instance of the plurality of instances is represented as a unique identification number; configuring, by the processor, the adder engine based on the plurality of instances, wherein the adder engine comprises a plurality of adders configured to operate in a pipelined structure and in parallel with the plurality of instances; executing, by the processor, the convolution operation on each of the plurality of instances and the adder engine; and filtering, by the processor, an output of the convolution operation by using a filter function configured to operate on a predefined threshold function thereby performing the convolution operation on the image using the reconfigurable convolution engine.