A bias circuit for a power amplifier, PA, comprising a first transistor having its drain terminal and its gate terminal connected to a first circuit node (x) and its source terminal connected to a first supply terminal; a first current source connected to the first circuit node (x); a first resistor connected between the first circuit node (x) and a second circuit node (y); a second transistor configured to receive a first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal; and a third transistor configured to receive a second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal; wherein the gate terminals of the second transistor and the third transistor are configured to be biased by a first voltage; and the bias circuit is configured to generate a bias voltage (Vbias) for the PA at the second circuit node (y); and wherein the bias circuit comprises: a fourth transistor having its gate terminal connected to a third circuit node (z), its drain terminal connected to the first circuit node (x), and its source terminal connected to the first supply terminal a fifth transistor having its drain terminal and its gate terminal connected to the third circuit node (z) and its source terminal connected to the first supply terminal; a sixth transistor configured to receive the first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the third circuit node (z) and its source terminal connected to the second supply terminal; and a seventh transistor configured to receive the second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the third circuit node (z) and its source terminal connected to the second supply terminal. a first transistor having its drain terminal and its gate terminal connected to a first circuit node (x) and its source terminal connected to a first supply terminal; a first current source connected to the first circuit node (x); a first resistor connected between the first circuit node (x) and a second circuit node (y); a second transistor configured to receive a first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal; and a third transistor configured to receive a second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal; wherein the gate terminals of the second transistor and the third transistor are configured to be biased by a first voltage; and the bias circuit is configured to generate a bias voltage (Vbias) for the PA at the second circuit node (y); and wherein the bias circuit comprises: a fourth transistor having its gate terminal connected to a third circuit node (z), its drain terminal connected to the first circuit node (x), and its source terminal connected to the first supply terminal a fifth transistor having its drain terminal and its gate terminal connected to the third circuit node (z) and its source terminal connected to the first supply terminal; a sixth transistor configured to receive the first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the third circuit node (z) and its source terminal connected to the second supply terminal; and a seventh transistor configured to receive the second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the third circuit node (z) and its source terminal connected to the second supply terminal. a fourth transistor having its gate terminal connected to a third circuit node (z), its drain terminal connected to the first circuit node (x), and its source terminal connected to the first supply terminal a fifth transistor having its drain terminal and its gate terminal connected to the third circuit node (z) and its source terminal connected to the first supply terminal; a sixth transistor configured to receive the first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the third circuit node (z) and its source terminal connected to the second supply terminal; and a seventh transistor configured to receive the second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the third circuit node (z) and its source terminal connected to the second supply terminal.