A semiconductor device (1, 2) comprising: a memory array comprising a plurality of complementary cells, each of which comprises a first memory cell and a second memory cell, the memory array being capable of holding data in the complementary cells using a difference between a threshold voltage of the first memory cell and a threshold voltage of the second memory cell; a memory control circuit configured to control data writing to and data reading from the plurality of complementary cells; and an ID generation circuit configured to generate an ID for the memory array using an initial threshold voltage of the first memory cell and an initial threshold voltage of the second memory cell, wherein: the memory array comprises a complementary cell for data holding and a complementary cell for ID generation as the plurality of complementary cells; the ID generation circuit is configured to generate the ID for the memory array using the complementary cell for ID generation; the ID generation circuit is configured to: read out data in the complementary cell for ID generation as first data in a first state in which the initial threshold voltage of the first memory cell has been virtually offset; read out data in the complementary cell for ID generation as second data in a second state in which the initial threshold voltage of the second memory cell has been virtually offset; and when the first data in the complementary cell for ID generation read out in the first state and the second data in the complementary cell for ID generation read out in the second state coincide with each other, use the coincident data as the ID for the memory array; and wherein when the first and second data in the complementary cell for ID generation have been determined not to coincide with each other, the memory control circuit is configured to switch the complementary cell for ID generation to a complementary cell for data holding. a memory array comprising a plurality of complementary cells, each of which comprises a first memory cell and a second memory cell, the memory array being capable of holding data in the complementary cells using a difference between a threshold voltage of the first memory cell and a threshold voltage of the second memory cell; a memory control circuit configured to control data writing to and data reading from the plurality of complementary cells; and an ID generation circuit configured to generate an ID for the memory array using an initial threshold voltage of the first memory cell and an initial threshold voltage of the second memory cell, wherein: the memory array comprises a complementary cell for data holding and a complementary cell for ID generation as the plurality of complementary cells; the ID generation circuit is configured to generate the ID for the memory array using the complementary cell for ID generation; the ID generation circuit is configured to: read out data in the complementary cell for ID generation as first data in a first state in which the initial threshold voltage of the first memory cell has been virtually offset; read out data in the complementary cell for ID generation as second data in a second state in which the initial threshold voltage of the second memory cell has been virtually offset; and when the first data in the complementary cell for ID generation read out in the first state and the second data in the complementary cell for ID generation read out in the second state coincide with each other, use the coincident data as the ID for the memory array; and the memory array comprises a complementary cell for data holding and a complementary cell for ID generation as the plurality of complementary cells; the ID generation circuit is configured to generate the ID for the memory array using the complementary cell for ID generation; the ID generation circuit is configured to: read out data in the complementary cell for ID generation as first data in a first state in which the initial threshold voltage of the first memory cell has been virtually offset; read out data in the complementary cell for ID generation as second data in a second state in which the initial threshold voltage of the second memory cell has been virtually offset; and when the first data in the complementary cell for ID generation read out in the first state and the second data in the complementary cell for ID generation read out in the second state coincide with each other, use the coincident data as the ID for the memory array; and read out data in the complementary cell for ID generation as first data in a first state in which the initial threshold voltage of the first memory cell has been virtually offset; read out data in the complementary cell for ID generation as second data in a second state in which the initial threshold voltage of the second memory cell has been virtually offset; and when the first data in the complementary cell for ID generation read out in the first state and the second data in the complementary cell for ID generation read out in the second state coincide with each other, use the coincident data as the ID for the memory array; and wherein when the first and second data in the complementary cell for ID generation have been determined not to coincide with each other, the memory control circuit is configured to switch the complementary cell for ID generation to a complementary cell for data holding.