A memory array, comprising: a plurality of identical N-wells (301, 302) within a P-type substrate; and at least two independently programmable memory segments; wherein each of the at least two independently programmable memory segments resides within a unique and separate one of the plurality of N-wells (301, 302) such that each N-well (301, 302) can be biased independently from the other N-wells (301, 302), wherein the at least two independently programmable memory segments have a common number of rows, and wherein each of the at least two independently programmable memory segments comprises: a plurality of memory cells, wherein each memory cell comprises a single P-channel memory transistor (401, 402...416) and the P-channel memory transistors (401; 402..408; 409..416) are arranged in a plurality of said rows and a plurality of columns thereby forming a plurality of memory units, wherein a memory unit defines the smallest portion of the memory array that may be addressed by a write and erase operation; for each column, a single associated P-type source select transistor (501...516), each P-type source select transistor (501...516) being connected to a source of each P-type memory transistor (401; 402..408; 409..416) of the associated column; for each row, a word line (WL, WL2..n) wherein each word line (WL, WL2..n) connects to all memory transistors gates of a single associated row, wherein each word line is common for the at least two independently programmable memory segments; for each column, a bit line (BL1..16) connected to a drain of each memory transistor within a single associated column; first and second select lines (SL1, SL2) connected to the gate and source, respectively of each P-type source select transistor (501..516); wherein said memory array further comprises independent connections to each N-well (301, 302) for individual biasing of said N-wells (301, 302); and wherein said memory array further comprises row select circuitry coupled with said word lines outside of said N-wells (301, 302). a plurality of identical N-wells (301, 302) within a P-type substrate; and at least two independently programmable memory segments; wherein each of the at least two independently programmable memory segments resides within a unique and separate one of the plurality of N-wells (301, 302) such that each N-well (301, 302) can be biased independently from the other N-wells (301, 302), wherein the at least two independently programmable memory segments have a common number of rows, and wherein each of the at least two independently programmable memory segments comprises: a plurality of memory cells, wherein each memory cell comprises a single P-channel memory transistor (401, 402...416) and the P-channel memory transistors (401; 402..408; 409..416) are arranged in a plurality of said rows and a plurality of columns thereby forming a plurality of memory units, wherein a memory unit defines the smallest portion of the memory array that may be addressed by a write and erase operation; for each column, a single associated P-type source select transistor (501...516), each P-type source select transistor (501...516) being connected to a source of each P-type memory transistor (401; 402..408; 409..416) of the associated column; for each row, a word line (WL, WL2..n) wherein each word line (WL, WL2..n) connects to all memory transistors gates of a single associated row, wherein each word line is common for the at least two independently programmable memory segments; for each column, a bit line (BL1..16) connected to a drain of each memory transistor within a single associated column; first and second select lines (SL1, SL2) connected to the gate and source, respectively of each P-type source select transistor (501..516); wherein said memory array further comprises independent connections to each N-well (301, 302) for individual biasing of said N-wells (301, 302); and wherein said memory array further comprises row select circuitry coupled with said word lines outside of said N-wells (301, 302). a plurality of memory cells, wherein each memory cell comprises a single P-channel memory transistor (401, 402...416) and the P-channel memory transistors (401; 402..408; 409..416) are arranged in a plurality of said rows and a plurality of columns thereby forming a plurality of memory units, wherein a memory unit defines the smallest portion of the memory array that may be addressed by a write and erase operation; for each column, a single associated P-type source select transistor (501...516), each P-type source select transistor (501...516) being connected to a source of each P-type memory transistor (401; 402..408; 409..416) of the associated column; for each row, a word line (WL, WL2..n) wherein each word line (WL, WL2..n) connects to all memory transistors gates of a single associated row, wherein each word line is common for the at least two independently programmable memory segments; for each column, a bit line (BL1..16) connected to a drain of each memory transistor within a single associated column; first and second select lines (SL1, SL2) connected to the gate and source, respectively of each P-type source select transistor (501..516); wherein said memory array further comprises independent connections to each N-well (301, 302) for individual biasing of said N-wells (301, 302);