A fault tolerant, dynamically erectable computer system comprising: a. a data and instruction domain comprising: i. a set of processors operating only in said data and instruction domain ii. a set of memories operable in the data and instruction domain; and b. a meta mentor domain independent and distinct from the data and instruction domain, said meta mentor domain comprising: i. meta information including data, algorithms, and rule sets; ii. a mentor domain memory containing the meta information; iii. a set of mentor domain processors including access to the mentor domain memory meta information; iv. a set of mentor switches providing communication between the sets of processors and memories in the data and instruction domain, the set of mentor switches cooperating with the set of mentor domain processors for mentoring all said communications according to the meta information, said mentoring including one or more of the set of mentor domain processors using the meta information to dynamically monitor, control, configure and reconfigure the data and instruction domain by means of said mentor switches; characterized in: v. the mentor switches providing an abstraction layer between the sets of processors and resources to schedule applications and processes; and vi. the mentor switches communicating information among other mentor switches or among system components to create multi-domained systems. a. a data and instruction domain comprising: i. a set of processors operating only in said data and instruction domain ii. a set of memories operable in the data and instruction domain; and i. a set of processors operating only in said data and instruction domain ii. a set of memories operable in the data and instruction domain; and b. a meta mentor domain independent and distinct from the data and instruction domain, said meta mentor domain comprising: i. meta information including data, algorithms, and rule sets; ii. a mentor domain memory containing the meta information; iii. a set of mentor domain processors including access to the mentor domain memory meta information; iv. a set of mentor switches providing communication between the sets of processors and memories in the data and instruction domain, the set of mentor switches cooperating with the set of mentor domain processors for mentoring all said communications according to the meta information, said mentoring including one or more of the set of mentor domain processors using the meta information to dynamically monitor, control, configure and reconfigure the data and instruction domain by means of said mentor switches; characterized in: v. the mentor switches providing an abstraction layer between the sets of processors and resources to schedule applications and processes; and vi. the mentor switches communicating information among other mentor switches or among system components to create multi-domained systems. i. meta information including data, algorithms, and rule sets; ii. a mentor domain memory containing the meta information; iii. a set of mentor domain processors including access to the mentor domain memory meta information; iv. a set of mentor switches providing communication between the sets of processors and memories in the data and instruction domain, the set of mentor switches cooperating with the set of mentor domain processors for mentoring all said communications according to the meta information, said mentoring including one or more of the set of mentor domain processors using the meta information to dynamically monitor, control, configure and reconfigure the data and instruction domain by means of said mentor switches; characterized in: v. the mentor switches providing an abstraction layer between the sets of processors and resources to schedule applications and processes; and vi. the mentor switches communicating information among other mentor switches or among system components to create multi-domained systems. v. the mentor switches providing an abstraction layer between the sets of processors and resources to schedule applications and processes; and vi. the mentor switches communicating information among other mentor switches or among system components to create multi-domained systems.