A wireless device comprising: a digital baseband processor having a general purpose input/output port (30, GPIO) not designed to receive synchronous parallel data; a camera module having a data interface directly connected to the general purpose input/output port of the digital baseband processor and configured to output a synchronous parallel data stream to the data interface; a logic circuit connected to the general purpose input/output port of the digital baseband processor and the camera module and configured for: receiving a horizontal synchronisation signal (HREF) and a pixel clock signal (PCLK) from the camera module and a direct memory access grant signal (DMA_EBUS_GNT) from the digital baseband processor, generating an interrupt signal ("Byte Ready Interrupt") in response to the signals from the camera module and the digital baseband processor and providing the interrupt signal to the digital baseband processor to synchronize the transfer of the synchronous parallel data through the general purpose input/output port, wherein the general purpose input/output port comprises a plurality of independently-controllable input/output lines, the wireless device further comprising: a memory to store the synchronous parallel data, the digital baseband processor including a processing unit having a direct memory access controller configured for DMA transfer of the synchronous parallel data from the general purpose input/output port to the memory in response to the interrupt signal. a digital baseband processor having a general purpose input/output port (30, GPIO) not designed to receive synchronous parallel data; a camera module having a data interface directly connected to the general purpose input/output port of the digital baseband processor and configured to output a synchronous parallel data stream to the data interface; a logic circuit connected to the general purpose input/output port of the digital baseband processor and the camera module and configured for: receiving a horizontal synchronisation signal (HREF) and a pixel clock signal (PCLK) from the camera module and a direct memory access grant signal (DMA_EBUS_GNT) from the digital baseband processor, generating an interrupt signal ("Byte Ready Interrupt") in response to the signals from the camera module and the digital baseband processor and providing the interrupt signal to the digital baseband processor to synchronize the transfer of the synchronous parallel data through the general purpose input/output port, wherein the general purpose input/output port comprises a plurality of independently-controllable input/output lines, the wireless device further comprising: a memory to store the synchronous parallel data, the digital baseband processor including a processing unit having a direct memory access controller configured for DMA transfer of the synchronous parallel data from the general purpose input/output port to the memory in response to the interrupt signal. a memory to store the synchronous parallel data, the digital baseband processor including a processing unit having a direct memory access controller configured for DMA transfer of the synchronous parallel data from the general purpose input/output port to the memory in response to the interrupt signal.