A semiconductor device comprising: a semiconductor layer; a source region and a drain region of a first conductivity type formed separately from each other in the semiconductor layer, the semiconductor layer being of a second conductivity type opposite to the first conductivity type; a channel formation region located between the source region and the drain region; a first insulating region (STId) formed in the semiconductor layer between the channel formation region and the drain region; a gate electrode formed via a gate insulating film on the channel formation region and extending to a position above the first insulating region (STId); a first semiconductor region (HNDF) of the first conductivity type surrounding the drain region; a second semiconductor region of the second conductivity type surrounding the source region; a third semiconductor region (PISO) of the second conductivity type arranged below the first semiconductor region (HNDF); and a fourth semiconductor region (H1PW) of the second conductivity type arranged between the third semiconductor region (PISO) and the second semiconductor region, the fourth semiconductor region (H1PW) being located at a position deeper than the second semiconductor region and at a position shallower than the third semiconductor region (PISO), wherein the fourth semiconductor region (H1PW) is arranged so as to overlap an end part of the third semiconductor region (PISO) on a side closer to the second semiconductor region, and the fourth semiconductor region (H1PW) is arranged so as to overlap an end part of the second semiconductor region on a side closer to the first semiconductor region (HNDF), an impurity concentration of the second conductivity type of the third semiconductor region (PISO) is higher than an impurity concentration of the second conductivity type of the semiconductor layer, and an impurity concentration of the second conductivity type of the fourth semiconductor region (H1PW) is higher than the impurity concentration of the second conductivity type of the semiconductor layer. a semiconductor layer; a source region and a drain region of a first conductivity type formed separately from each other in the semiconductor layer, the semiconductor layer being of a second conductivity type opposite to the first conductivity type; a channel formation region located between the source region and the drain region; a first insulating region (STId) formed in the semiconductor layer between the channel formation region and the drain region; a gate electrode formed via a gate insulating film on the channel formation region and extending to a position above the first insulating region (STId); a first semiconductor region (HNDF) of the first conductivity type surrounding the drain region; a second semiconductor region of the second conductivity type surrounding the source region; a third semiconductor region (PISO) of the second conductivity type arranged below the first semiconductor region (HNDF); and a fourth semiconductor region (H1PW) of the second conductivity type arranged between the third semiconductor region (PISO) and the second semiconductor region, the fourth semiconductor region (H1PW) being located at a position deeper than the second semiconductor region and at a position shallower than the third semiconductor region (PISO), wherein the fourth semiconductor region (H1PW) is arranged so as to overlap an end part of the third semiconductor region (PISO) on a side closer to the second semiconductor region, and the fourth semiconductor region (H1PW) is arranged so as to overlap an end part of the second semiconductor region on a side closer to the first semiconductor region (HNDF), an impurity concentration of the second conductivity type of the third semiconductor region (PISO) is higher than an impurity concentration of the second conductivity type of the semiconductor layer, and an impurity concentration of the second conductivity type of the fourth semiconductor region (H1PW) is higher than the impurity concentration of the second conductivity type of the semiconductor layer.