A reconfigurable hardware modeling device comprising: a plurality of reconfigurable hardware modeling circuits interconnected either directly or indirectly, wherein each of the plurality of reconfigurable hardware modeling circuits comprises: serializer circuitry (430; 530) and deserializer circuitry (420; 520) for one or more communication ports (340, 350, 360, 370) of the each of the plurality of reconfigurable hardware modeling circuits, the serializer circuitry (430; 530) having first sub-channels for receiving data to be sent out from the each of the plurality of reconfigurable hardware modeling circuits, the deserializer circuitry (420; 520) having second sub-channels for outputting data received by the each of the plurality of reconfigurable hardware modeling circuits, static switching circuitry (510; 640) configurable, while implementing a hardware model of a circuit design in the reconfigurable hardware modeling device, to couple each of first one or more sub-channels in the first sub-channels with one of signal sources during a verification process for the circuit design, the signal sources comprising the second sub-channels, wherein the static switching circuitry (510; 640) is configured to maintain a fixed connection configuration without changing the connection configuration at different clock cycles for the whole verification process, and dynamic switching circuitry (330; 410; 630) configurable, while implementing the hardware model of the circuit design in the reconfigurable hardware modeling device, to couple, in a time-division multiplexing mode, each of second one or more sub-channels in the first sub-channels with more than one of the signal sources during the verification process for the circuit design. a plurality of reconfigurable hardware modeling circuits interconnected either directly or indirectly, wherein each of the plurality of reconfigurable hardware modeling circuits comprises: serializer circuitry (430; 530) and deserializer circuitry (420; 520) for one or more communication ports (340, 350, 360, 370) of the each of the plurality of reconfigurable hardware modeling circuits, the serializer circuitry (430; 530) having first sub-channels for receiving data to be sent out from the each of the plurality of reconfigurable hardware modeling circuits, the deserializer circuitry (420; 520) having second sub-channels for outputting data received by the each of the plurality of reconfigurable hardware modeling circuits, static switching circuitry (510; 640) configurable, while implementing a hardware model of a circuit design in the reconfigurable hardware modeling device, to couple each of first one or more sub-channels in the first sub-channels with one of signal sources during a verification process for the circuit design, the signal sources comprising the second sub-channels, wherein the static switching circuitry (510; 640) is configured to maintain a fixed connection configuration without changing the connection configuration at different clock cycles for the whole verification process, and dynamic switching circuitry (330; 410; 630) configurable, while implementing the hardware model of the circuit design in the reconfigurable hardware modeling device, to couple, in a time-division multiplexing mode, each of second one or more sub-channels in the first sub-channels with more than one of the signal sources during the verification process for the circuit design. serializer circuitry (430; 530) and deserializer circuitry (420; 520) for one or more communication ports (340, 350, 360, 370) of the each of the plurality of reconfigurable hardware modeling circuits, the serializer circuitry (430; 530) having first sub-channels for receiving data to be sent out from the each of the plurality of reconfigurable hardware modeling circuits, the deserializer circuitry (420; 520) having second sub-channels for outputting data received by the each of the plurality of reconfigurable hardware modeling circuits, static switching circuitry (510; 640) configurable, while implementing a hardware model of a circuit design in the reconfigurable hardware modeling device, to couple each of first one or more sub-channels in the first sub-channels with one of signal sources during a verification process for the circuit design, the signal sources comprising the second sub-channels, wherein the static switching circuitry (510; 640) is configured to maintain a fixed connection configuration without changing the connection configuration at different clock cycles for the whole verification process, and dynamic switching circuitry (330; 410; 630) configurable, while implementing the hardware model of the circuit design in the reconfigurable hardware modeling device, to couple, in a time-division multiplexing mode, each of second one or more sub-channels in the first sub-channels with more than one of the signal sources during the verification process for the circuit design.