A three dimensional on-chip radio frequency amplifier, the chip comprising a substrate having a top side and a bottom side, the radio frequency amplifier comprising: a first on-chip transformer comprising a first on-chip inductor and a second on-chip inductor; a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor; a first on-chip transistor comprising a gate, a drain and a source; wherein each of the first, second, third and fourth on-chip inductors comprises a plurality of first segments in a first metal layer, the first metal layer being above the top side of the substrate; a plurality of second segments in a redistribution design layer, RDL, the RDL being below the bottom side of the substrate; a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metal layer and the RDL; and a plurality of through silicon vias extending from the top side of the substrate to the bottom side of the substrate and coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input; the first on-chip inductor being inductively coupled to the second on-chip inductor, the third on-chip inductor being inductively coupled to the fourth on-chip inductor, and the first, second, third and fourth on-chip inductors not being physically coupled to one another except through ground; the first inductor input of the first on-chip inductor being coupled to an input of the on-chip radio frequency amplifier; the first inductor input of the second on-chip inductor being coupled to the gate of the first on-chip transistor; the first inductor input of the third on-chip inductor being coupled to the drain of the first on-chip transistor, the first inductor input of the fourth on-chip inductor being coupled to an output of the on-chip radio frequency amplifier; the second inductor input of the first, second, third and fourth on-chip inductors being coupled to ground; and the source of the first on-chip transistor being coupled to ground; wherein the inductors do not form part of a crack stop structure. a first on-chip transformer comprising a first on-chip inductor and a second on-chip inductor; a second on-chip transformer comprising a third on-chip inductor and a fourth on-chip inductor; a first on-chip transistor comprising a gate, a drain and a source; wherein each of the first, second, third and fourth on-chip inductors comprises a plurality of first segments in a first metal layer, the first metal layer being above the top side of the substrate; a plurality of second segments in a redistribution design layer, RDL, the RDL being below the bottom side of the substrate; a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metal layer and the RDL; and a plurality of through silicon vias extending from the top side of the substrate to the bottom side of the substrate and coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input; the first on-chip inductor being inductively coupled to the second on-chip inductor, the third on-chip inductor being inductively coupled to the fourth on-chip inductor, and the first, second, third and fourth on-chip inductors not being physically coupled to one another except through ground; the first inductor input of the first on-chip inductor being coupled to an input of the on-chip radio frequency amplifier; the first inductor input of the second on-chip inductor being coupled to the gate of the first on-chip transistor; the first inductor input of the third on-chip inductor being coupled to the drain of the first on-chip transistor, the first inductor input of the fourth on-chip inductor being coupled to an output of the on-chip radio frequency amplifier; the second inductor input of the first, second, third and fourth on-chip inductors being coupled to ground; and the source of the first on-chip transistor being coupled to ground; wherein the inductors do not form part of a crack stop structure.