A clock generator circuit for generating a wanted RF clock signal, the clock generator circuit comprising: an up-converter to up-convert modulation signals and quadrature local radio frequency clock signals to obtain an up-converted signal having a frequency equal to a desired frequency of the wanted RF clock signal; a band pass filter to filter the up-converted signal to output a filtered version of the up-converted signal; a first clock driver/divider to amplify and clip the filtered version of the up-converted signal into a first-clipped clock signal; a spurious tone cancellation circuit to receive the first-clipped clock signal, the spurious tone cancellation circuit including: a tone detection circuit to detect a residual error signal of one or more unwanted frequency tones in a compensated version of the first-clipped clock signal, a controller to receive the residual error signal from the tone detection circuit and generate control signals, a tone generation circuit to receive the control signals and write data patterns to a pattern register and to generate cancellation tones that have amplitude and phase values to cancel the one or more unwanted frequency tones, and a coupler to couple the cancellation tones to the first-clipped clock signal to obtain the compensated version of the first-clipped clock signal; and a second clock driver/divider to further clip the compensated version of the first-clipped clock signal to obtain the wanted RF clock signal. an up-converter to up-convert modulation signals and quadrature local radio frequency clock signals to obtain an up-converted signal having a frequency equal to a desired frequency of the wanted RF clock signal; a band pass filter to filter the up-converted signal to output a filtered version of the up-converted signal; a first clock driver/divider to amplify and clip the filtered version of the up-converted signal into a first-clipped clock signal; a spurious tone cancellation circuit to receive the first-clipped clock signal, the spurious tone cancellation circuit including: a tone detection circuit to detect a residual error signal of one or more unwanted frequency tones in a compensated version of the first-clipped clock signal, a controller to receive the residual error signal from the tone detection circuit and generate control signals, a tone generation circuit to receive the control signals and write data patterns to a pattern register and to generate cancellation tones that have amplitude and phase values to cancel the one or more unwanted frequency tones, and a coupler to couple the cancellation tones to the first-clipped clock signal to obtain the compensated version of the first-clipped clock signal; and a tone detection circuit to detect a residual error signal of one or more unwanted frequency tones in a compensated version of the first-clipped clock signal, a controller to receive the residual error signal from the tone detection circuit and generate control signals, a tone generation circuit to receive the control signals and write data patterns to a pattern register and to generate cancellation tones that have amplitude and phase values to cancel the one or more unwanted frequency tones, and a coupler to couple the cancellation tones to the first-clipped clock signal to obtain the compensated version of the first-clipped clock signal; and a second clock driver/divider to further clip the compensated version of the first-clipped clock signal to obtain the wanted RF clock signal.