A compute-in-memory bitcell array, comprising: a read bit line; a shared capacitor having a first plate connected to the read bit line; a first compute-in-memory bitcell that includes a first pair of cross-coupled inverters (120, 125) having a first output node for a first stored bit and includes a first transmission gate connected between the first output node and a second plate of the shared capacitor, the first transmission gate being configured to close in response to a first input bit being true and to open in response to the first input bit being false; a second compute-in-memory bitcell that includes a second pair of cross-coupled inverters (120, 125) having a second output node for a second stored bit and includes a second transmission gate connected between the second output node and the second plate of the shared capacitor, the second transmission gate being configured to close in response to a second input bit being true and to open in response to the second input bit being false; wherein the first pair of cross-coupled inverters includes a third output node for a complement of the first stored bit and the first compute-in-memory bitcell further includes a third transmission gate connected between the third output node and the second plate of the shared capacitor, the third transmission gate being configured to open in response to the first input bit being true and to close in response to the first input bit being false; and wherein the second pair of cross-coupled inverters includes a fourth output node for a complement of the second stored bit and the second compute-in-memory bitcell further includes a fourth transmission gate connected between the fourth output node and the second plate of the shared capacitor, the fourth transmission gate being configured to open in response to the second input bit being true and to close in response to the second input bit being false. a read bit line; a shared capacitor having a first plate connected to the read bit line; a first compute-in-memory bitcell that includes a first pair of cross-coupled inverters (120, 125) having a first output node for a first stored bit and includes a first transmission gate connected between the first output node and a second plate of the shared capacitor, the first transmission gate being configured to close in response to a first input bit being true and to open in response to the first input bit being false; a second compute-in-memory bitcell that includes a second pair of cross-coupled inverters (120, 125) having a second output node for a second stored bit and includes a second transmission gate connected between the second output node and the second plate of the shared capacitor, the second transmission gate being configured to close in response to a second input bit being true and to open in response to the second input bit being false; wherein the first pair of cross-coupled inverters includes a third output node for a complement of the first stored bit and the first compute-in-memory bitcell further includes a third transmission gate connected between the third output node and the second plate of the shared capacitor, the third transmission gate being configured to open in response to the first input bit being true and to close in response to the first input bit being false; and wherein the second pair of cross-coupled inverters includes a fourth output node for a complement of the second stored bit and the second compute-in-memory bitcell further includes a fourth transmission gate connected between the fourth output node and the second plate of the shared capacitor, the fourth transmission gate being configured to open in response to the second input bit being true and to close in response to the second input bit being false.