A method for evaluating a neural network model in a system comprising a plurality of nodes interconnected via a network, the neural network model comprising a plurality of layers encoded as matrices of weights expressed in the form of coefficients, each node being configured to operate on fixed-size vectors and on fixed-size matrices of coefficients, the fixed-size matrices having a native size of each of the nodes, said native size being of N rows and M columns, wherein N is an integer equal to or greater than 8 and M is an integer equal to or greater than 8, wherein each node comprises: N tiles (940, 950, 960), each tile (940, 950, 960) comprising a respective on-chip memory (942, 952, 962) and a respective compute unit; an ingress tree (710, 712, 714) coupled to each of the N tiles (940, 950, 960); and an egress pipeline coupled to each of the N tiles (940, 950, 960); wherein the method comprises: partitioning the matrices of the neural network model into a plurality of N by M matrices of coefficients; pinning the plurality of N by M matrices of coefficients to the plurality of nodes by, for each node of said plurality of nodes: storing all the rows of a respective N by M matrix of coefficients in the on-chip memories (942, 952, 962) of the node such that the ith row of the N by M matrix of coefficients is stored in an on-chip memory incorporated within the ith one of the N tiles (940, 950, 960); at each node: receiving an input vector via the ingress tree (710, 712, 714); processing all the rows of the respective N by M matrix of coefficients and the input vector by performing a point-wise dot product operation on the input vector and the ith row of the N by M matrix of coefficients stored in the on-chip memory incorporated within the ith one of the N tiles (940, 950, 960) using a compute unit incorporated within the ith one of the N tiles (940, 950, 960); and outputting values generated by each point-wise dot product operation via the egress pipeline. wherein each node comprises: N tiles (940, 950, 960), each tile (940, 950, 960) comprising a respective on-chip memory (942, 952, 962) and a respective compute unit; an ingress tree (710, 712, 714) coupled to each of the N tiles (940, 950, 960); and an egress pipeline coupled to each of the N tiles (940, 950, 960); N tiles (940, 950, 960), each tile (940, 950, 960) comprising a respective on-chip memory (942, 952, 962) and a respective compute unit; an ingress tree (710, 712, 714) coupled to each of the N tiles (940, 950, 960); and an egress pipeline coupled to each of the N tiles (940, 950, 960); wherein the method comprises: partitioning the matrices of the neural network model into a plurality of N by M matrices of coefficients; pinning the plurality of N by M matrices of coefficients to the plurality of nodes by, for each node of said plurality of nodes: storing all the rows of a respective N by M matrix of coefficients in the on-chip memories (942, 952, 962) of the node such that the ith row of the N by M matrix of coefficients is stored in an on-chip memory incorporated within the ith one of the N tiles (940, 950, 960); at each node: receiving an input vector via the ingress tree (710, 712, 714); processing all the rows of the respective N by M matrix of coefficients and the input vector by performing a point-wise dot product operation on the input vector and the ith row of the N by M matrix of coefficients stored in the on-chip memory incorporated within the ith one of the N tiles (940, 950, 960) using a compute unit incorporated within the ith one of the N tiles (940, 950, 960); and outputting values generated by each point-wise dot product operation via the egress pipeline. partitioning the matrices of the neural network model into a plurality of N by M matrices of coefficients; pinning the plurality of N by M matrices of coefficients to the plurality of nodes by, for each node of said plurality of nodes: storing all the rows of a respective N by M matrix of coefficients in the on-chip memories (942, 952, 962) of the node such that the ith row of the N by M matrix of coefficients is stored in an on-chip memory incorporated within the ith one of the N tiles (940, 950, 960); at each node: receiving an input vector via the ingress tree (710, 712, 714); processing all the rows of the respective N by M matrix of coefficients and the input vector by performing a point-wise dot product operation on the input vector and the ith row of the N by M matrix of coefficients stored in the on-chip memory incorporated within the ith one of the N tiles (940, 950, 960) using a compute unit incorporated within the ith one of the N tiles (940, 950, 960); and outputting values generated by each point-wise dot product operation via the egress pipeline.