Segmented circuitry comprising: a plurality of mutually-similar and mutually-similarly-scaled segments, including at least three first segments and at least three second segments, each said segment having signal changing means operable to change a magnitude of a controllable current signal of the segment in dependence upon a control signal, each said first segment being connected operatively to a first node of the circuitry such that its controllable current signal passes through the first node and each said second segment being connected operatively to a second node of the circuitry such that its controllable current signal passes through the second node; and impedance ladder means, including a first load impedance element (Z L; Z LG; 32) connected between said first node and a load line and a second load impedance element (Z L; Z LG; 32) connected between said second node and said load line and a divider impedance element (Z DIV) connected between said first and second nodes, for producing a weighted combination of the controllable current signals of the plurality of segments, a contribution of the controllable current signal of each said second segment to said weighted combination being 1/k of a contribution of the controllable current signal of each said first segment based on the values of said impedance elements, where k is a scaling factor, and where the load line is a ground or another supply reference, wherein the control signals for the first segments are derived from first bits of a digital input signal of the circuitry, and the control signals for the second segments are derived from second bits of said digital input signal, each said second bit being less significant than each first bit. a plurality of mutually-similar and mutually-similarly-scaled segments, including at least three first segments and at least three second segments, each said segment having signal changing means operable to change a magnitude of a controllable current signal of the segment in dependence upon a control signal, each said first segment being connected operatively to a first node of the circuitry such that its controllable current signal passes through the first node and each said second segment being connected operatively to a second node of the circuitry such that its controllable current signal passes through the second node; and impedance ladder means, including a first load impedance element (Z L; Z LG; 32) connected between said first node and a load line and a second load impedance element (Z L; Z LG; 32) connected between said second node and said load line and a divider impedance element (Z DIV) connected between said first and second nodes, for producing a weighted combination of the controllable current signals of the plurality of segments, a contribution of the controllable current signal of each said second segment to said weighted combination being 1/k of a contribution of the controllable current signal of each said first segment based on the values of said impedance elements, where k is a scaling factor, and where the load line is a ground or another supply reference, wherein the control signals for the first segments are derived from first bits of a digital input signal of the circuitry, and the control signals for the second segments are derived from second bits of said digital input signal, each said second bit being less significant than each first bit.