Memory system control circuitry (108, 208), comprising: memory management circuitry; and non-volatile memory control circuitry (222, 322), which non-volatile memory control circuitry (222, 322) is configured to: write original data associated with a plurality of logical addresses in a first stripe across a plurality of channels (442-1, 442-2, 442-N); and write updated data associated with a subset of the plurality of addresses in a second stripe across the plurality of channels (442-1, 442-2, 442-N) without reading or copying the original data in the first stripe; the memory system control circuitry (108, 208) being characterised in that: the non-volatile memory control circuitry (222, 322) is further configured to write unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe; and detect an error associated with a portion of the second stripe; the memory management circuitry is configured to effectively remove the portion of the second stripe from the second stripe in response to the non-volatile memory control circuitry (222, 322) detecting the error; and the non-volatile memory control circuitry (222, 322) is further configured to operate the second stripe without the removed portion of the second stripe. memory management circuitry; and non-volatile memory control circuitry (222, 322), which non-volatile memory control circuitry (222, 322) is configured to: write original data associated with a plurality of logical addresses in a first stripe across a plurality of channels (442-1, 442-2, 442-N); and write updated data associated with a subset of the plurality of addresses in a second stripe across the plurality of channels (442-1, 442-2, 442-N) without reading or copying the original data in the first stripe; write original data associated with a plurality of logical addresses in a first stripe across a plurality of channels (442-1, 442-2, 442-N); and write updated data associated with a subset of the plurality of addresses in a second stripe across the plurality of channels (442-1, 442-2, 442-N) without reading or copying the original data in the first stripe; the memory system control circuitry (108, 208) being characterised in that: the non-volatile memory control circuitry (222, 322) is further configured to write unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe; and detect an error associated with a portion of the second stripe; the memory management circuitry is configured to effectively remove the portion of the second stripe from the second stripe in response to the non-volatile memory control circuitry (222, 322) detecting the error; and the non-volatile memory control circuitry (222, 322) is further configured to operate the second stripe without the removed portion of the second stripe. the non-volatile memory control circuitry (222, 322) is further configured to write unrelated data in the second stripe concurrent with writing the updated data in the second stripe, wherein the unrelated data is unrelated to the original data in the first stripe and the updated data in the second stripe; and detect an error associated with a portion of the second stripe; the memory management circuitry is configured to effectively remove the portion of the second stripe from the second stripe in response to the non-volatile memory control circuitry (222, 322) detecting the error; and the non-volatile memory control circuitry (222, 322) is further configured to operate the second stripe without the removed portion of the second stripe.