A bootstrapped, passive, differential mixer having differential mixer inputs (RFN, RFP), comprising: at least eight mixing transistors (PNI, NNI, NPI, PPI, PNQ, NNQ, NPQ, PPQ), arranged in differential pairs; at least four shared bootstrap circuits (16, 18, 20, 22), each including a capacitor and being connected to a different pair of mixing transistors (PNI, NNI, NPI, PPI, PNQ, NNQ, NPQ, PPQ); wherein a first plurality of the shared bootstrap circuits (16, 18) are each operative to charge their capacitor during each second half-period of a clock signal (Clk_N) and operative, during each first half-period of the clock signal (Clk), to bootstrap an enabled one of the mixing transistors (PNI, NNI, NPI, PPI) of the connected pair by connecting the charged capacitor between a mixer input (RFN, RFP) and the gate terminal of the enabled mixing transistor (PNI, NNI, NPI, PPI); wherein a second plurality of the shared bootstrap circuits (20, 22) are each operative to charge their capacitor during each first half-period of the clock signal (Clk) and operative, during each second half-period of the clock signal (Clk_N), to bootstrap an enabled one of the mixing transistors (PNQ, NNQ, NPQ, PPQ) of the connected pair by connecting the charged capacitor between a mixer input (RFN, RFP) and the gate terminal of the enabled mixing transistor (PNQ, NNQ, NPQ, PPQ); and wherein first one, and then the other, mixing transistor (PNI, NNI, NPI, PPI, PNQ, NNQ, NPQ, PPQ) of each pair are alternately enabled during the half-period of the clock signal (Clk, Clk_N) in which the connected shared bootstrap circuit (16, 18, 20, 22) is not charging its capacitor. at least eight mixing transistors (PNI, NNI, NPI, PPI, PNQ, NNQ, NPQ, PPQ), arranged in differential pairs; at least four shared bootstrap circuits (16, 18, 20, 22), each including a capacitor and being connected to a different pair of mixing transistors (PNI, NNI, NPI, PPI, PNQ, NNQ, NPQ, PPQ); wherein a first plurality of the shared bootstrap circuits (16, 18) are each operative to charge their capacitor during each second half-period of a clock signal (Clk_N) and operative, during each first half-period of the clock signal (Clk), to bootstrap an enabled one of the mixing transistors (PNI, NNI, NPI, PPI) of the connected pair by connecting the charged capacitor between a mixer input (RFN, RFP) and the gate terminal of the enabled mixing transistor (PNI, NNI, NPI, PPI); wherein a second plurality of the shared bootstrap circuits (20, 22) are each operative to charge their capacitor during each first half-period of the clock signal (Clk) and operative, during each second half-period of the clock signal (Clk_N), to bootstrap an enabled one of the mixing transistors (PNQ, NNQ, NPQ, PPQ) of the connected pair by connecting the charged capacitor between a mixer input (RFN, RFP) and the gate terminal of the enabled mixing transistor (PNQ, NNQ, NPQ, PPQ); and wherein first one, and then the other, mixing transistor (PNI, NNI, NPI, PPI, PNQ, NNQ, NPQ, PPQ) of each pair are alternately enabled during the half-period of the clock signal (Clk, Clk_N) in which the connected shared bootstrap circuit (16, 18, 20, 22) is not charging its capacitor.