Method for production of an integrated circuit arrangement, comprising the following steps, which are carried out in the stated sequence: application of a dielectric layer (160, 300) to a metallization layer which contains a large number of interconnects and at least one first electrode, with the dielectric layer (160, 300) having a thickness of less than 150 nm, application of at least one hard mask layer to the dielectric layer (160, 300), application of a resist layer to the hard mask layer, structuring of the hard mask layer with the aid of the resist layer, with the dielectric layer (160, 300) not being completely structured in that a contact hole or a via (162, 164) is not completely opened, removal of the residues of the resist layer, after the removal of the residues of the resist layer, complete structuring of the dielectric layer (160, 300) with the aid of the hard mask layer, with the contact hole or the via (162, 164) being completely opened and an area, which is located underneath it, of at least one second electrode in the metallization layer being exposed, with a further metallization layer which contains a large number of interconnects being produced after the structuring of the dielectric layer (160, 300) with the dielectric layer (160, 300) not being etched through during the non-complete structuring, with the electrodes (138, 140) still being protected by the dielectric layer during the removal of the residues of the resist layer, and with the residues of the resist layer being removed using a method which is not the same as the method used for structuring of the dielectric layer (160, 300), characterized in that both metallization layers (102, 104) are spaced apart from one another by less than 100 nm by the dielectric layer (160, 300) outside the contact hole or via (162, 164), and in that a layer of the hard mask layer which is adjacent to the dielectric layer (160, 300) is an electrically insulating layer which is removed once again. application of a dielectric layer (160, 300) to a metallization layer which contains a large number of interconnects and at least one first electrode, with the dielectric layer (160, 300) having a thickness of less than 150 nm, application of at least one hard mask layer to the dielectric layer (160, 300), application of a resist layer to the hard mask layer, structuring of the hard mask layer with the aid of the resist layer, with the dielectric layer (160, 300) not being completely structured in that a contact hole or a via (162, 164) is not completely opened, removal of the residues of the resist layer, after the removal of the residues of the resist layer, complete structuring of the dielectric layer (160, 300) with the aid of the hard mask layer, with the contact hole or the via (162, 164) being completely opened and an area, which is located underneath it, of at least one second electrode in the metallization layer being exposed, with a further metallization layer which contains a large number of interconnects being produced after the structuring of the dielectric layer (160, 300) with the dielectric layer (160, 300) not being etched through during the non-complete structuring, with the electrodes (138, 140) still being protected by the dielectric layer during the removal of the residues of the resist layer, and with the residues of the resist layer being removed using a method which is not the same as the method used for structuring of the dielectric layer (160, 300), characterized in that both metallization layers (102, 104) are spaced apart from one another by less than 100 nm by the dielectric layer (160, 300) outside the contact hole or via (162, 164), and in that a layer of the hard mask layer which is adjacent to the dielectric layer (160, 300) is an electrically insulating layer which is removed once again.