An analog-to-digital converter, ADC, comprising a plurality of sub ADCs (A1-A M) configured to operate in a time-interleaved manner; a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs (Al-AM); a test signal generation circuit configured to generate a test signal for calibration of the ADC; wherein the sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal; the sampling circuit comprises an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit, wherein the first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase, wherein the amplifier circuit is a differential single ended amplifier with a negative input and a positive gain to ensure negative feedback with the positive input of the differential amplifier being the one connected to signal ground; the sampling circuit comprises an input circuit comprising one or more capacitors (C1, C2), each having a first node and a second node; the sampling circuit comprises sampling switches connecting the first and second inputs (61, 62) with nodes of capacitors (C1, C2) in the input circuit to sample the analog input signal and the test signal represented as electrical charges on capacitors in the input circuit; each of the capacitors in the input circuit is configured to be connected with its second node to said input of the amplifier circuit during the second clock phase; and the sampling circuit comprises a second feedback switch connected between the output of the amplifier circuit and the first node of at least one of the capacitors in the input circuit, wherein the second feedback switch is configured to be closed during the second clock phase and open during the first clock phase. a plurality of sub ADCs (A1-A M) configured to operate in a time-interleaved manner; a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs (Al-AM); a test signal generation circuit configured to generate a test signal for calibration of the ADC; wherein the sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal; the sampling circuit comprises an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit, wherein the first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase, wherein the amplifier circuit is a differential single ended amplifier with a negative input and a positive gain to ensure negative feedback with the positive input of the differential amplifier being the one connected to signal ground; the sampling circuit comprises an input circuit comprising one or more capacitors (C1, C2), each having a first node and a second node; the sampling circuit comprises sampling switches connecting the first and second inputs (61, 62) with nodes of capacitors (C1, C2) in the input circuit to sample the analog input signal and the test signal represented as electrical charges on capacitors in the input circuit; each of the capacitors in the input circuit is configured to be connected with its second node to said input of the amplifier circuit during the second clock phase; and the sampling circuit comprises a second feedback switch connected between the output of the amplifier circuit and the first node of at least one of the capacitors in the input circuit, wherein the second feedback switch is configured to be closed during the second clock phase and open during the first clock phase.