A semiconductor arrangement comprising: a circuit board comprising a metallization layer with a first conductor track and a second conductor track; a multiplicity of individual semiconductor chips each comprising a controllable semiconductor element, a first load electrode, a second load electrode and a control electrode, the first load electrodes of the individual semiconductor chips electrically connected to one another, the second load electrodes of the individual semiconductor chips electrically connected to one another, and the control electrodes of the individual semiconductor chips electrically connected to one another, wherein the first conductor track comprises a base section and a first, second and third section (31, 32, 33), the base section extending in a first horizontal direction of the circuit board, the first, second and third sections (31, 32, 33) extending in a second horizontal direction that is perpendicular to the first horizontal direction, the third section arranged between the first and second sections (31, 32), and the base section electrically connecting the first, second and third sections (31, 32, 33); the second conductor track comprises a base section and a first and a second section (41, 42), the base section extending in the first horizontal direction, the first and second sections (41, 42) extending in the second horizontal direction, and the base section electrically connecting the first and second sections (41, 42); the first section of the second conductor track is arranged between the first and the third section (31, 33) of the first conductor track; the second section of the second conductor track is arranged between the second and the third section (32, 33) of the first conductor track; the third section of the first conductor track is arranged between the first and the second section (41, 42) of the second conductor track; a first subset and a second subset of the multiplicity of semiconductor chips are arranged on the first section of the second conductor track; a third subset and a fourth subset of the multiplicity of semiconductor chips are arranged on the second section of the second conductor track; the first load electrode of each of the semiconductor chips of the first and the second subset is, via at least one first electrical connection (51, 52), electrically connected to the first section of the first conductor track and, via at least one second electrical connection (51, 52), to the third section of the first conductor track; and the first load electrode of each of the semiconductor chips of the third and the fourth subset is, via at least one third electrical connection (51, 52), electrically connected to the third section of the first metallization and, via at least one fourth electrical connection (51, 52), to the second section of the first conductor track. a circuit board comprising a metallization layer with a first conductor track and a second conductor track; a multiplicity of individual semiconductor chips each comprising a controllable semiconductor element, a first load electrode, a second load electrode and a control electrode, the first load electrodes of the individual semiconductor chips electrically connected to one another, the second load electrodes of the individual semiconductor chips electrically connected to one another, and the control electrodes of the individual semiconductor chips electrically connected to one another, wherein the first conductor track comprises a base section and a first, second and third section (31, 32, 33), the base section extending in a first horizontal direction of the circuit board, the first, second and third sections (31, 32, 33) extending in a second horizontal direction that is perpendicular to the first horizontal direction, the third section arranged between the first and second sections (31, 32), and the base section electrically connecting the first, second and third sections (31, 32, 33); the second conductor track comprises a base section and a first and a second section (41, 42), the base section extending in the first horizontal direction, the first and second sections (41, 42) extending in the second horizontal direction, and the base section electrically connecting the first and second sections (41, 42); the first section of the second conductor track is arranged between the first and the third section (31, 33) of the first conductor track; the second section of the second conductor track is arranged between the second and the third section (32, 33) of the first conductor track; the third section of the first conductor track is arranged between the first and the second section (41, 42) of the second conductor track; a first subset and a second subset of the multiplicity of semiconductor chips are arranged on the first section of the second conductor track; a third subset and a fourth subset of the multiplicity of semiconductor chips are arranged on the second section of the second conductor track; the first load electrode of each of the semiconductor chips of the first and the second subset is, via at least one first electrical connection (51, 52), electrically connected to the first section of the first conductor track and, via at least one second electrical connection (51, 52), to the third section of the first conductor track; and the first load electrode of each of the semiconductor chips of the third and the fourth subset is, via at least one third electrical connection (51, 52), electrically connected to the third section of the first metallization and, via at least one fourth electrical connection (51, 52), to the second section of the first conductor track.