A display device comprising: a flexible substrate; gate lines (GL1,..., GLm), data lines (DL1,..., DLn), and power lines on the flexible substrate, the data lines (DL1,..., DLn) and the power lines intersecting the gate lines (GL1,..., GLm); a plurality of subpixels defined by an intersection of the gate lines (GL1,..., GLm), data lines (DL1,..., DLn), and power lines on the flexible substrate, wherein each subpixel includes: an emission portion configured to emit light and a circuit portion in which a thin film transistor (D_TFT) is disposed on the flexible substrate; a first electrode connected to the thin film transistor (D_TFT); a bank layer including a pixel definition portion exposing the first electrode and a groove portion spaced apart from the pixel definition portion, wherein the groove portion of the bank layer is disposed in a remaining area excluding the emission portion and the circuit portion of the subpixel; an organic layer disposed on the first electrode and the bank layer; and a second electrode disposed on the organic layer, the display device further comprising: a protective layer disposed on the second electrode; an adhesive layer disposed on the protective layer; and an upper protective member disposed on the adhesive layer, wherein a first collection space is provided between the protective layer and the adhesive layer in the pixel definition portion of the bank layer, and wherein a second collection space is provided between the protective layer and the adhesive layer in the groove portion of the bank layer, and wherein the adhesive layer selectively contacts the protective layer at the circuit portion. a flexible substrate; gate lines (GL1,..., GLm), data lines (DL1,..., DLn), and power lines on the flexible substrate, the data lines (DL1,..., DLn) and the power lines intersecting the gate lines (GL1,..., GLm); a plurality of subpixels defined by an intersection of the gate lines (GL1,..., GLm), data lines (DL1,..., DLn), and power lines on the flexible substrate, wherein each subpixel includes: an emission portion configured to emit light and a circuit portion in which a thin film transistor (D_TFT) is disposed on the flexible substrate; a first electrode connected to the thin film transistor (D_TFT); a bank layer including a pixel definition portion exposing the first electrode and a groove portion spaced apart from the pixel definition portion, wherein the groove portion of the bank layer is disposed in a remaining area excluding the emission portion and the circuit portion of the subpixel; an organic layer disposed on the first electrode and the bank layer; and a second electrode disposed on the organic layer, the display device further comprising: a protective layer disposed on the second electrode; an adhesive layer disposed on the protective layer; and an upper protective member disposed on the adhesive layer, wherein a first collection space is provided between the protective layer and the adhesive layer in the pixel definition portion of the bank layer, and wherein a second collection space is provided between the protective layer and the adhesive layer in the groove portion of the bank layer, and wherein the adhesive layer selectively contacts the protective layer at the circuit portion. an emission portion configured to emit light and a circuit portion in which a thin film transistor (D_TFT) is disposed on the flexible substrate; a first electrode connected to the thin film transistor (D_TFT); a bank layer including a pixel definition portion exposing the first electrode and a groove portion spaced apart from the pixel definition portion, wherein the groove portion of the bank layer is disposed in a remaining area excluding the emission portion and the circuit portion of the subpixel; an organic layer disposed on the first electrode and the bank layer; and a second electrode disposed on the organic layer, the display device further comprising: a protective layer disposed on the second electrode; an adhesive layer disposed on the protective layer; and an upper protective member disposed on the adhesive layer, wherein a first collection space is provided between the protective layer and the adhesive layer in the pixel definition portion of the bank layer, and wherein a second collection space is provided between the protective layer and the adhesive layer in the groove portion of the bank layer, and wherein the adhesive layer selectively contacts the protective layer at the circuit portion. a protective layer disposed on the second electrode; an adhesive layer disposed on the protective layer; and an upper protective member disposed on the adhesive layer, wherein a first collection space is provided between the protective layer and the adhesive layer in the pixel definition portion of the bank layer, and wherein a second collection space is provided between the protective layer and the adhesive layer in the groove portion of the bank layer, and wherein the adhesive layer selectively contacts the protective layer at the circuit portion.