A microprocessor capable of supporting multiple instruction set architectures, ISAs, and comprising a plurality of hardware registers that are shared by the ISAs, the microprocessor being characterized in that: it is configured to run both x86 ISA machine language programs and Advanced RISC Machines, ARM, ISA machine language programs; it has architectural state that is specific to the x86 ISA; it has architectural state that is specific to the ARM ISA; it has architectural state that is shared by the x86 ISA and ARM ISA; it comprises: a mode indicator configured to indicate whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program, wherein when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state, and when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state; and a hardware instruction translator configured, in accordance with the mode indicator, to translate x86 and ARM instructions into microinstructions of the microprocessor, wherein the microinstructions are from a microinstruction set that is distinct from the x86 ISA and the ARM ISA; and it is configured to execute a reset instruction to reset the microprocessor from a first one of the x86 ISA and the ARM ISA to a second one of the x86 ISA and the ARM ISA, and to respond to the reset instruction by: re-initializing the ISA-specific architectural state of the second ISA to default values; re-initializing the architectural state that is shared by the x86 ISA and ARM ISA to default values; and fetching a first instruction of the second ISA from a programmable address (624, 654) defined in one or more of the plurality of hardware registers. it is configured to run both x86 ISA machine language programs and Advanced RISC Machines, ARM, ISA machine language programs; it has architectural state that is specific to the x86 ISA; it has architectural state that is specific to the ARM ISA; it has architectural state that is shared by the x86 ISA and ARM ISA; it comprises: a mode indicator configured to indicate whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program, wherein when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state, and when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state; and a hardware instruction translator configured, in accordance with the mode indicator, to translate x86 and ARM instructions into microinstructions of the microprocessor, wherein the microinstructions are from a microinstruction set that is distinct from the x86 ISA and the ARM ISA; and a mode indicator configured to indicate whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program, wherein when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state, and when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state; and a hardware instruction translator configured, in accordance with the mode indicator, to translate x86 and ARM instructions into microinstructions of the microprocessor, wherein the microinstructions are from a microinstruction set that is distinct from the x86 ISA and the ARM ISA; and it is configured to execute a reset instruction to reset the microprocessor from a first one of the x86 ISA and the ARM ISA to a second one of the x86 ISA and the ARM ISA, and to respond to the reset instruction by: re-initializing the ISA-specific architectural state of the second ISA to default values; re-initializing the architectural state that is shared by the x86 ISA and ARM ISA to default values; and fetching a first instruction of the second ISA from a programmable address (624, 654) defined in one or more of the plurality of hardware registers. re-initializing the ISA-specific architectural state of the second ISA to default values; re-initializing the architectural state that is shared by the x86 ISA and ARM ISA to default values; and fetching a first instruction of the second ISA from a programmable address (624, 654) defined in one or more of the plurality of hardware registers.