A display, comprising: a pixel structure including a plurality of units arranged along a line respectively in both a longitudinal direction and a horizontal direction, wherein each unit includes a first pixel unit and a second pixel unit arranged in the horizontal direction, each of the first and second pixel units (100a, 100b) includes a red sub-pixel, a green sub-pixel and a blue sub-pixel, the blue sub-pixel (B, 110) of the first pixel unit is adjacent to the blue sub-pixel of the second pixel unit, the red sub-pixel (R, 120) of the first pixel unit is axial symmetrical to the red sub-pixel of the second pixel unit, and the green sub-pixel (G, 130) of the first pixel unit is axial symmetrical to the green sub-pixel of the second pixel unit; wherein the first pixel unit is divided into a first region and a second region in the longitudinal direction, the blue sub-pixel (B, 110) of the first pixel unit is positioned in the first region, the red sub-pixel (R, 120) and the green sub-pixel (G, 130) of the first pixel unit are positioned in the second region, and the red sub-pixel (R, 120) and the green sub-pixel (G, 130) are juxtaposed in the horizontal direction; characterized by comprising: an integrated circuit having a plurality of ports including a plurality of port units arranged in sequence, each port unit including a red sub-pixel port, a green sub-pixel port and a blue sub-pixel port arranged in sequence; and diagonal wires, configured to connect the plurality of ports to a data line of each column of the pixel structure respectively, the diagonal wires including a first cross diagonal wire and a second cross diagonal wire arranged crosswise, the first cross diagonal wire configured to connect a data line of a column where the red sub-pixel of the second pixel unit is positioned, to the red sub-pixel port, and the second cross diagonal wire configured to connect a data line of a column where the green sub-pixel of the second pixel unit is positioned, to the green sub-pixel port; wherein the diagonal wires further include a third diagonal wire, the third diagonal wire connecting a data line of a column where the blue sub-pixel of the second pixel unit is positioned, to the blue sub-pixel port, and the third diagonal wire is arranged away from the first cross diagonal wire and the second cross diagonal wire. a pixel structure including a plurality of units arranged along a line respectively in both a longitudinal direction and a horizontal direction, wherein each unit includes a first pixel unit and a second pixel unit arranged in the horizontal direction, each of the first and second pixel units (100a, 100b) includes a red sub-pixel, a green sub-pixel and a blue sub-pixel, the blue sub-pixel (B, 110) of the first pixel unit is adjacent to the blue sub-pixel of the second pixel unit, the red sub-pixel (R, 120) of the first pixel unit is axial symmetrical to the red sub-pixel of the second pixel unit, and the green sub-pixel (G, 130) of the first pixel unit is axial symmetrical to the green sub-pixel of the second pixel unit; wherein the first pixel unit is divided into a first region and a second region in the longitudinal direction, the blue sub-pixel (B, 110) of the first pixel unit is positioned in the first region, the red sub-pixel (R, 120) and the green sub-pixel (G, 130) of the first pixel unit are positioned in the second region, and the red sub-pixel (R, 120) and the green sub-pixel (G, 130) are juxtaposed in the horizontal direction; characterized by comprising: an integrated circuit having a plurality of ports including a plurality of port units arranged in sequence, each port unit including a red sub-pixel port, a green sub-pixel port and a blue sub-pixel port arranged in sequence; and diagonal wires, configured to connect the plurality of ports to a data line of each column of the pixel structure respectively, the diagonal wires including a first cross diagonal wire and a second cross diagonal wire arranged crosswise, the first cross diagonal wire configured to connect a data line of a column where the red sub-pixel of the second pixel unit is positioned, to the red sub-pixel port, and the second cross diagonal wire configured to connect a data line of a column where the green sub-pixel of the second pixel unit is positioned, to the green sub-pixel port; an integrated circuit having a plurality of ports including a plurality of port units arranged in sequence, each port unit including a red sub-pixel port, a green sub-pixel port and a blue sub-pixel port arranged in sequence; and diagonal wires, configured to connect the plurality of ports to a data line of each column of the pixel structure respectively, the diagonal wires including a first cross diagonal wire and a second cross diagonal wire arranged crosswise, the first cross diagonal wire configured to connect a data line of a column where the red sub-pixel of the second pixel unit is positioned, to the red sub-pixel port, and the second cross diagonal wire configured to connect a data line of a column where the green sub-pixel of the second pixel unit is positioned, to the green sub-pixel port; wherein the diagonal wires further include a third diagonal wire, the third diagonal wire connecting a data line of a column where the blue sub-pixel of the second pixel unit is positioned, to the blue sub-pixel port, and the third diagonal wire is arranged away from the first cross diagonal wire and the second cross diagonal wire.