A computer-implemented method for partitioning a hierarchical cache having a shared n-way associative last-level cache, LLC,, comprising: storing, by at least one processor, a first bitmask, wherein the first bitmask comprises n bits, wherein n is a predetermined number equal to the number of ways in the LLC; associating, by the at least one processor, the first bitmask with a first core of the at least one processor, wherein the at least one processor comprises at least one multi-core processor; setting, by the at least one processor, a subset of the bits of the first bitmask, wherein the subset of the bits of the first bitmask represents at least one first portion of the LLC (160, 170, 180, 190), and wherein any part of the first bitmask excluding the subset of the bits of the first bitmask represents at least one second portion of the LLC (160, 170, 180, 190); disallowing, by the at least one processor, eviction of any cache line in the at least one second portion of the LLC (160, 170, 180, 190) by the first core of the at least one processor wherein setting a bit at an i-th position of the first bitmask means that the first core evicts cache lines from the i-th portion of the LLC; wherein unsetting the bit at the i-th position means that the first core does not evict cache lines from the i-th portion of LLC; and dynamically updating, by the at least one processor, the first bitmask by setting, unsetting and/or toggling at least one bit of the first bitmask in response to a context switch or thread migration with respect to the first core such that any new process or thread running on the first core at a different time benefits from having an updated bitmask. storing, by at least one processor, a first bitmask, wherein the first bitmask comprises n bits, wherein n is a predetermined number equal to the number of ways in the LLC; associating, by the at least one processor, the first bitmask with a first core of the at least one processor, wherein the at least one processor comprises at least one multi-core processor; setting, by the at least one processor, a subset of the bits of the first bitmask, wherein the subset of the bits of the first bitmask represents at least one first portion of the LLC (160, 170, 180, 190), and wherein any part of the first bitmask excluding the subset of the bits of the first bitmask represents at least one second portion of the LLC (160, 170, 180, 190); disallowing, by the at least one processor, eviction of any cache line in the at least one second portion of the LLC (160, 170, 180, 190) by the first core of the at least one processor wherein setting a bit at an i-th position of the first bitmask means that the first core evicts cache lines from the i-th portion of the LLC; wherein unsetting the bit at the i-th position means that the first core does not evict cache lines from the i-th portion of LLC; and dynamically updating, by the at least one processor, the first bitmask by setting, unsetting and/or toggling at least one bit of the first bitmask in response to a context switch or thread migration with respect to the first core such that any new process or thread running on the first core at a different time benefits from having an updated bitmask. wherein setting a bit at an i-th position of the first bitmask means that the first core evicts cache lines from the i-th portion of the LLC; wherein unsetting the bit at the i-th position means that the first core does not evict cache lines from the i-th portion of LLC; and dynamically updating, by the at least one processor, the first bitmask by setting, unsetting and/or toggling at least one bit of the first bitmask in response to a context switch or thread migration with respect to the first core such that any new process or thread running on the first core at a different time benefits from having an updated bitmask.