A method for managing a single event latched, SEL, condition, the method comprising operations to: monitor, at a watchdog pulse generator of a microprocessor, test result signals received from a plurality of devices coupled to the microprocessor and from the microprocessor to determine by the watchdog pulse generator whether a pass condition is satisfied; output to a watchdog timer watchdog pulses by the watchdog pulse generator only when the pass condition is satisfied, thereby indicating the absence of a malfunction condition associated with the SEL condition; configure and send by the watchdog timer hardware reset signals to each of the plurality of devices and the microprocessor in response to the watchdog pulses not arriving when expected; count by the watchdog timer the number of times the hardware reset signals are sent; in response to the count exceeding a predetermined threshold, set by the watchdog timer the hardware reset signals to a failsafe state and send the hardware reset signals in the failsafe state to each of the plurality of devices and the microprocessor; monitor by a power control module, that the hardware reset signals have been persistently set to the failsafe state for at least a predetermined time interval; and control by the power control module provision of power to the microprocessor and the plurality of devices in response to detecting that the hardware reset signals have been persistently set to the failsafe state for at least the predetermined time interval; wherein controlling the provision of power includes triggering a power restart that removes power supplied to the microprocessor and the plurality of devices, the power being subsequently automatically restored to the microprocessor and the plurality of devices; the method further comprising operations to: count by an On/Off control module a number of times that a power restart is triggered; and disallow the restoration of power in response to the number of times counted exceeding a second threshold value. monitor, at a watchdog pulse generator of a microprocessor, test result signals received from a plurality of devices coupled to the microprocessor and from the microprocessor to determine by the watchdog pulse generator whether a pass condition is satisfied; output to a watchdog timer watchdog pulses by the watchdog pulse generator only when the pass condition is satisfied, thereby indicating the absence of a malfunction condition associated with the SEL condition; configure and send by the watchdog timer hardware reset signals to each of the plurality of devices and the microprocessor in response to the watchdog pulses not arriving when expected; count by the watchdog timer the number of times the hardware reset signals are sent; in response to the count exceeding a predetermined threshold, set by the watchdog timer the hardware reset signals to a failsafe state and send the hardware reset signals in the failsafe state to each of the plurality of devices and the microprocessor; monitor by a power control module, that the hardware reset signals have been persistently set to the failsafe state for at least a predetermined time interval; and control by the power control module provision of power to the microprocessor and the plurality of devices in response to detecting that the hardware reset signals have been persistently set to the failsafe state for at least the predetermined time interval; wherein controlling the provision of power includes triggering a power restart that removes power supplied to the microprocessor and the plurality of devices, the power being subsequently automatically restored to the microprocessor and the plurality of devices; the method further comprising operations to: count by an On/Off control module a number of times that a power restart is triggered; and disallow the restoration of power in response to the number of times counted exceeding a second threshold value. count by an On/Off control module a number of times that a power restart is triggered; and disallow the restoration of power in response to the number of times counted exceeding a second threshold value.