System, comprising: a memory array that includes a plurality of memory cells configured in a column-row arrangement with a plurality of rows of cells intersecting a plurality of columns of cells, with each cell being addressable via a particular column and a particular row, the memory cells being configured to store data values; computation circuits in electrical communication with columns of the memory array, the computation circuits including circuitry configured to, in operation, calculate or determine a sum of the cell values from each cell in those corresponding columns, a sensing circuit (210a-210b) coupled to said computation circuits and being configured to read the sum calculated or determined by the computation circuits; and calibration circuitry configured to, in operation: apply a pattern of test data to a selected one or more memory cells in electrical communication with the computation circuits; generate calibration information, the calibration information being generated by analyzing an output provided by the sensing circuit in response to the application of the pattern of test data to the selected memory cells of the memory array in view of results expected from application of the test data pattern, the generated calibration information including estimated offset data for the selected memory cells to which the test data pattern was applied; and store the generated calibration information in a distributed manner within at least some memory cells of the plurality of memory cells so that the calibration information are stored in one or more regions of a memory array corresponding to those memory cells coupled to the sensing circuit on which such calibration information is based; wherein, in operation and after the storing of the generated calibration information in the distributed manner, the computation circuits are configured to calculate or determine a sum of the data values and offset data from each cell of the same column. a memory array that includes a plurality of memory cells configured in a column-row arrangement with a plurality of rows of cells intersecting a plurality of columns of cells, with each cell being addressable via a particular column and a particular row, the memory cells being configured to store data values; computation circuits in electrical communication with columns of the memory array, the computation circuits including circuitry configured to, in operation, calculate or determine a sum of the cell values from each cell in those corresponding columns, a sensing circuit (210a-210b) coupled to said computation circuits and being configured to read the sum calculated or determined by the computation circuits; and calibration circuitry configured to, in operation: apply a pattern of test data to a selected one or more memory cells in electrical communication with the computation circuits; generate calibration information, the calibration information being generated by analyzing an output provided by the sensing circuit in response to the application of the pattern of test data to the selected memory cells of the memory array in view of results expected from application of the test data pattern, the generated calibration information including estimated offset data for the selected memory cells to which the test data pattern was applied; and store the generated calibration information in a distributed manner within at least some memory cells of the plurality of memory cells so that the calibration information are stored in one or more regions of a memory array corresponding to those memory cells coupled to the sensing circuit on which such calibration information is based; apply a pattern of test data to a selected one or more memory cells in electrical communication with the computation circuits; generate calibration information, the calibration information being generated by analyzing an output provided by the sensing circuit in response to the application of the pattern of test data to the selected memory cells of the memory array in view of results expected from application of the test data pattern, the generated calibration information including estimated offset data for the selected memory cells to which the test data pattern was applied; and store the generated calibration information in a distributed manner within at least some memory cells of the plurality of memory cells so that the calibration information are stored in one or more regions of a memory array corresponding to those memory cells coupled to the sensing circuit on which such calibration information is based; wherein, in operation and after the storing of the generated calibration information in the distributed manner, the computation circuits are configured to calculate or determine a sum of the data values and offset data from each cell of the same column.