A semiconductor integrated circuit comprising: an arithmetic processing circuit including a first processor core configured to perform arithmetic processing and a common unit containing a cache memory storing data and programs, at least one of the first processor core and the common unit being divided into a first circuit and a second circuit; a first clock gating circuit configured to supply or to stop a clock signal to the first circuit; a first power switch configured to supply to cut off a power supply voltage to the first circuit; a second clock gating circuit configured to supply or to stop the clock signal to the second circuit; a second power switch configured to supply or to cut off the power supply voltage to the second circuit; and a controller configured to control the first and second clock gating circuits and the first and second power switches, characterized in that the controller 2. includes a buffer configured to store wakeup signals to activate at least one of the first circuit, the second circuit, the first processor core and the common unit to an operating state and input times of the wakeup signals, and the controller further includes a selector configured to select one of the wakeup signals which is input n signals (n is an integer equal to 1 or greater) before a wakeup signal input most recently from the buffer based on a selection signal, wherein the controller includes a plurality of power saving modes that control at least one of the first circuit, the second circuit, the first processor core and the common unit to power saving states, the controller is configured to calculate a time difference between an input time of the wakeup signal input most recently and an input time of the one of the wakeup signals input n signals before, and the controller is configured to compare the time difference and a switching threshold to select the power saving mode for at least one of the first circuit, the second circuit, the first processor core and the common unit in accordance with a comparison result. an arithmetic processing circuit including a first processor core configured to perform arithmetic processing and a common unit containing a cache memory storing data and programs, at least one of the first processor core and the common unit being divided into a first circuit and a second circuit; a first clock gating circuit configured to supply or to stop a clock signal to the first circuit; a first power switch configured to supply to cut off a power supply voltage to the first circuit; a second clock gating circuit configured to supply or to stop the clock signal to the second circuit; a second power switch configured to supply or to cut off the power supply voltage to the second circuit; and a controller configured to control the first and second clock gating circuits and the first and second power switches, characterized in that the controller 2. includes a buffer configured to store wakeup signals to activate at least one of the first circuit, the second circuit, the first processor core and the common unit to an operating state and input times of the wakeup signals, and the controller further includes a selector configured to select one of the wakeup signals which is input n signals (n is an integer equal to 1 or greater) before a wakeup signal input most recently from the buffer based on a selection signal, wherein the controller includes a plurality of power saving modes that control at least one of the first circuit, the second circuit, the first processor core and the common unit to power saving states, the controller is configured to calculate a time difference between an input time of the wakeup signal input most recently and an input time of the one of the wakeup signals input n signals before, and the controller is configured to compare the time difference and a switching threshold to select the power saving mode for at least one of the first circuit, the second circuit, the first processor core and the common unit in accordance with a comparison result.