A processor for performing a configurable sliding window operation on an array of data elements stored in a plurality of input vector registers comprising a logic circuit, the processor being configured to receive an instruction to execute a configurable sliding window operation, the logic circuit comprising: the plurality of input vector registers, for storing the array; a coefficient register for storing a coefficient vector containing N coefficients, where N is strictly larger than one; an output register for storing a result vector; and an arithmetic unit in response to the execution of the instruction configured to: receive a pattern for selecting N data elements from the plurality of input vector registers; select a plurality of groups of N data elements from the plurality of input vector registers in parallel, wherein each group is selected in accordance with the pattern and a starting point in the input vector registers, the pattern being a bit mask, wherein a first group is selected with the pattern and wherein for each following group the starting point is shifted by a constant value with respect to a previous selected group, and the following group is selected with the shifted starting point; perform an arithmetic operation between each of the selected groups and the coefficients in parallel; and store results of the arithmetic operation in the output register, wherein the logic circuit is configured to receive the pattern, the input vectors of the input vector registers and the coefficients from the instruction. the plurality of input vector registers, for storing the array; a coefficient register for storing a coefficient vector containing N coefficients, where N is strictly larger than one; an output register for storing a result vector; and an arithmetic unit in response to the execution of the instruction configured to: receive a pattern for selecting N data elements from the plurality of input vector registers; select a plurality of groups of N data elements from the plurality of input vector registers in parallel, wherein each group is selected in accordance with the pattern and a starting point in the input vector registers, the pattern being a bit mask, wherein a first group is selected with the pattern and wherein for each following group the starting point is shifted by a constant value with respect to a previous selected group, and the following group is selected with the shifted starting point; perform an arithmetic operation between each of the selected groups and the coefficients in parallel; and store results of the arithmetic operation in the output register, wherein the logic circuit is configured to receive the pattern, the input vectors of the input vector registers and the coefficients from the instruction. receive a pattern for selecting N data elements from the plurality of input vector registers; select a plurality of groups of N data elements from the plurality of input vector registers in parallel, wherein each group is selected in accordance with the pattern and a starting point in the input vector registers, the pattern being a bit mask, wherein a first group is selected with the pattern and wherein for each following group the starting point is shifted by a constant value with respect to a previous selected group, and the following group is selected with the shifted starting point; perform an arithmetic operation between each of the selected groups and the coefficients in parallel; and store results of the arithmetic operation in the output register, wherein the logic circuit is configured to receive the pattern, the input vectors of the input vector registers and the coefficients from the instruction.