An apparatus comprising: processing circuitry to perform speculative execution of instructions; a main cache storage region; a speculative cache storage region; and cache control circuitry to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative, in which: when the speculative memory access which triggered allocation of the entry to the speculative cache storage region is a speculative load memory access for loading data from a memory system, the entry allocated to the speculative cache storage region in response to the speculative load memory access specifies the data loaded from the memory system; the cache control circuitry is configured to transfer an entry allocated in response to a speculative memory access from the speculative cache storage region to the main cache storage region after the speculative memory access has been resolved as correct; and following the processing circuitry switching from a more privileged state to a less privileged state, the cache control circuitry is configured to: permit the processing circuitry in the less privileged state to access entries stored in the main cache storage region; and prevent the processing circuitry in the less privileged state from accessing entries stored in the speculative cache storage region which were allocated to the speculative cache storage region while operating in the more privileged state. processing circuitry to perform speculative execution of instructions; a main cache storage region; a speculative cache storage region; and cache control circuitry to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative, in which: when the speculative memory access which triggered allocation of the entry to the speculative cache storage region is a speculative load memory access for loading data from a memory system, the entry allocated to the speculative cache storage region in response to the speculative load memory access specifies the data loaded from the memory system; the cache control circuitry is configured to transfer an entry allocated in response to a speculative memory access from the speculative cache storage region to the main cache storage region after the speculative memory access has been resolved as correct; and following the processing circuitry switching from a more privileged state to a less privileged state, the cache control circuitry is configured to: permit the processing circuitry in the less privileged state to access entries stored in the main cache storage region; and prevent the processing circuitry in the less privileged state from accessing entries stored in the speculative cache storage region which were allocated to the speculative cache storage region while operating in the more privileged state. when the speculative memory access which triggered allocation of the entry to the speculative cache storage region is a speculative load memory access for loading data from a memory system, the entry allocated to the speculative cache storage region in response to the speculative load memory access specifies the data loaded from the memory system; the cache control circuitry is configured to transfer an entry allocated in response to a speculative memory access from the speculative cache storage region to the main cache storage region after the speculative memory access has been resolved as correct; and following the processing circuitry switching from a more privileged state to a less privileged state, the cache control circuitry is configured to: permit the processing circuitry in the less privileged state to access entries stored in the main cache storage region; and prevent the processing circuitry in the less privileged state from accessing entries stored in the speculative cache storage region which were allocated to the speculative cache storage region while operating in the more privileged state. permit the processing circuitry in the less privileged state to access entries stored in the main cache storage region; and prevent the processing circuitry in the less privileged state from accessing entries stored in the speculative cache storage region which were allocated to the speculative cache storage region while operating in the more privileged state.