mhurhangee/ep-ind-claims huggingface dataset:
Method for controlling separate running of linked program blocks that are designed for implementing functions of safety-relevant systems, preferably in motor vehicles, having the steps of: execution of a first of the program blocks on a processor, wherein the first program block is present in a first section (10, 110) of a memory and the processor accesses the memory, wherein during the execution of the first program block a second of the program blocks is called, and the second program block is present in a second section (12, 112), which is different than the first section (10, 110) of the memory; monitoring of the access to the memory by a memory protection device, wherein the memory protection device triggers an exception if the monitoring of the access by the memory protection device prompts ascertainment that during the execution of the first of the program blocks the second of the program blocks is called, wherein the second program block is called by a task manager during the execution of the first program block or the second program block is called by a command in the first program block, wherein occurrence of the exception prompts an exception handler to disable the first section (10, 110) for access for the execution of the first program block and to enable the second section (12, 112) for execution. execution of a first of the program blocks on a processor, wherein the first program block is present in a first section (10, 110) of a memory and the processor accesses the memory, wherein during the execution of the first program block a second of the program blocks is called, and the second program block is present in a second section (12, 112), which is different than the first section (10, 110) of the memory; monitoring of the access to the memory by a memory protection device, wherein the memory protection device triggers an exception if the monitoring of the access by the memory protection device prompts ascertainment that during the execution of the first of the program blocks the second of the program blocks is called, wherein the second program block is called by a task manager during the execution of the first program block or the second program block is called by a command in the first program block, wherein occurrence of the exception prompts an exception handler to disable the first section (10, 110) for access for the execution of the first program block and to enable the second section (12, 112) for execution.
An apparatus configured to process a first signal in a first frequency band having a first bandwidth by a digital processor having a digital processor bandwidth in a second frequency band, comprising: a single receive unit configured to receive the first signal, the single receive unit comprising: a single converter, communicatively coupled to the single receive unit, the converter configured to convert the first signal of the first bandwidth into a first intermediate frequency band; a splitter, communicatively coupled to the converter, the splitter configured to split the converted first signal into N intermediate signals, each in a respective one of a first set of N sub-bands and each having a bandwidth less than or equal to the digital processor bandwidth, wherein N is an integer greater than one; N downconverters (316A-316N), each of the N downconverters communicatively coupled to the splitter and each of the N downconverters configured to downconvert an associated one of the N intermediate signals to the second frequency band; and a digital processing unit, configured to process the downconverted plurality of signals with the digital processor to generate N processed signals, wherein each sub-band of the first set of N sub-bands is selected to substantially exclude lower order spurs generated by at least one of the N downconverters. a single converter, communicatively coupled to the single receive unit, the converter configured to convert the first signal of the first bandwidth into a first intermediate frequency band; a splitter, communicatively coupled to the converter, the splitter configured to split the converted first signal into N intermediate signals, each in a respective one of a first set of N sub-bands and each having a bandwidth less than or equal to the digital processor bandwidth, wherein N is an integer greater than one; N downconverters (316A-316N), each of the N downconverters communicatively coupled to the splitter and each of the N downconverters configured to downconvert an associated one of the N intermediate signals to the second frequency band; and a digital processing unit, configured to process the downconverted plurality of signals with the digital processor to generate N processed signals, wherein each sub-band of the first set of N sub-bands is selected to substantially exclude lower order spurs generated by at least one of the N downconverters.
Electrical harness for a turbomachine, comprising a first termination connected while in use to an apparatus capable of emitting an electrical signal, and a second termination connected while in use to a signal processing apparatus, characterised in that it comprises an electronic circuit for filtering the signal, said circuit comprising at least one electronic component associated with an operating temperature threshold, and at least one thermally triggered electrical interruption means connected in series or in parallel with said at least one electronic component, said at least one electrical interruption means being capable of changing from an open state in which a current cannot flow through it, to a closed state in which a current can flow through it, or reciprocally from a closed state to an open state, from a tripping temperature lower than or equal to the operating temperature threshold of said at least one electronic component, so as to continue to ensure electrical transmission between the first termination and the second termination if the temperature becomes higher than said tripping temperature.
A method for in-situ cleaning one or more components of a gas turbine engine characterised in that, the method comprises injecting a gel detergent into at least a portion of the gas turbine engine at a predetermined pressure, the gel detergent comprising a plurality of abrasive particles suspended in a gel composition, the plurality of abrasive particles comprising organic material, the gel composition comprising a mixture of detergent particles dissolved in a gel reactant; and allowing the gel detergent to flow across or within one or more of the components of the gas turbine engine so as to clean one or more of the components.
A processor-implemented pose estimation method, the method comprising: tracking a position of a feature point extracted from image information comprising a plurality of image frames, the image information being received from an image sensor; predicting a current state variable of an estimation model for determining a pose of an electronic device, based on motion information received from a motion sensor; determining noise due to an uncertainty of the estimation model based on a residual between a first position of the feature point extracted from the image frames and a second position of the feature point predicted based on the current state variable; updating the current state variable based on the current state variable, the tracked position of the feature point, and the noise; and determining the pose of the electronic device based on the updated current state variable. tracking a position of a feature point extracted from image information comprising a plurality of image frames, the image information being received from an image sensor; predicting a current state variable of an estimation model for determining a pose of an electronic device, based on motion information received from a motion sensor; determining noise due to an uncertainty of the estimation model based on a residual between a first position of the feature point extracted from the image frames and a second position of the feature point predicted based on the current state variable; updating the current state variable based on the current state variable, the tracked position of the feature point, and the noise; and determining the pose of the electronic device based on the updated current state variable.
A wear-resistant aluminum alloy extruded material that exhibits excellent fatigue strength and machinability, the aluminum alloy extruded material being formed using an aluminum alloy that comprises 3.0 to 8.0 mass% of Si, 0.1 to 0.5 mass% of Mg, 0.01 to 0.5 mass% of Cu, 0.1 to 0.5 mass% of Zr, 0.4 to 0.9 mass% of Fe, 0.01 to 0.5 mass% of Mn, 0.01 to 0.5 mass% of Cr, and 0.01 to 0.1 mass% of Ti, with the balance being Al and unavoidable impurities.
Method for assigning an operating address to a bus-capable operating device for lamps, comprising the following steps: - determining an absolute position or a relative position of the operating device by means of a position detection device, - converting the position into an operating address, which includes the position, and - storing the operating address for the operating device in a storage medium of the operating device, wherein the operating device is addressed by a control unit via the operating address. - determining an absolute position or a relative position of the operating device by means of a position detection device, - converting the position into an operating address, which includes the position, and - storing the operating address for the operating device in a storage medium of the operating device, wherein the operating device is addressed by a control unit via the operating address.
A method for evaluating the scent performance of perfumes or perfume mixtures by measuring the response of the olfactory receptor, characterized in that: (a) the olfactory receptors were amplified from human genomic DNA and specific primers for human olfactory receptors, (b) the olfactory receptors were cloned into a pCI expression vector including Rho-tag as a leader peptide sequence, (c) the generated recombinant plasmids were verified by sequencing and the olfactory receptors expressed on a cell surface (d) at least one odorant is brought into contact with an olfactory receptor wherein the olfactory receptor is OR1B1. (a) the olfactory receptors were amplified from human genomic DNA and specific primers for human olfactory receptors, (b) the olfactory receptors were cloned into a pCI expression vector including Rho-tag as a leader peptide sequence, (c) the generated recombinant plasmids were verified by sequencing and the olfactory receptors expressed on a cell surface (d) at least one odorant is brought into contact with an olfactory receptor wherein the olfactory receptor is OR1B1.
A chair for facilitating entry and exit for a user, the chair comprising: a seat; a backrest; and a supporting structure for the seat and the backrest, wherein the supporting structure comprises at each side of the seat a supporting limb, each of which is defined by a single continuously curved elongate spring member, wherein each spring member has, in an unloaded condition of the chair, the shape of an open loop, defined by a continuous convex curvature between a first upper free end and a second opposite lower free end of the spring member, wherein each spring member has a rearwardly-directed upper run terminating at the first upper free end, a floor-engaging region and a lower run terminating at the second lower free end, with the upper run supporting the seat and the backrest, wherein each spring member has an inherent resilience with a bias into a configuration in which, in the unloaded condition of the chair, the first upper and second lower free ends are spaced apart vertically from one another while overlapping horizontally with each other, with the first upper free end located above the second lower free end, and in the unloaded condition the seat is downwardly inclined towards its front edge to facilitate user entry into the chair; and the resilience of the spring member is selected so that when a user sits into the chair, the spring member is resiliently yieldable under user weight into a configuration in which the first upper free end approaches or comes into engagement with the second lower free end and the seat is moved out of the downward inclination towards its front edge. a seat; a backrest; and a supporting structure for the seat and the backrest, wherein the supporting structure comprises at each side of the seat a supporting limb, each of which is defined by a single continuously curved elongate spring member, wherein each spring member has, in an unloaded condition of the chair, the shape of an open loop, defined by a continuous convex curvature between a first upper free end and a second opposite lower free end of the spring member, wherein each spring member has a rearwardly-directed upper run terminating at the first upper free end, a floor-engaging region and a lower run terminating at the second lower free end, with the upper run supporting the seat and the backrest, wherein each spring member has an inherent resilience with a bias into a configuration in which, in the unloaded condition of the chair, the first upper and second lower free ends are spaced apart vertically from one another while overlapping horizontally with each other, with the first upper free end located above the second lower free end, and in the unloaded condition the seat is downwardly inclined towards its front edge to facilitate user entry into the chair; and the resilience of the spring member is selected so that when a user sits into the chair, the spring member is resiliently yieldable under user weight into a configuration in which the first upper free end approaches or comes into engagement with the second lower free end and the seat is moved out of the downward inclination towards its front edge.
A method for implementing fast reroute 1, FRR, characterized by comprising the following steps of: a. a system starting up an upper layer protocol software to manage and configure a FRR route; b. the upper layer protocol software sending down an IP address of an active next hop of a FRR group and allocating an index to the FRR group different from an index of an equal-cost multi-path routing, ECMP, group; a driver writing the IP address of the active next hop of the FRR group into an ECMP table of an ASIC chip and creating a software table to store correspondence between the FRR group and the corresponding ECMP group on the chip; c. the upper layer protocol software informing the driver of a prefix address of a subnet route and the index of the FRR group, and the driver finding the corresponding index of the ECMP group in the software table according to the index of the FRR group, and writing information of the subnet route and the index of the ECMP group into hardware; d. the upper layer protocol software informing the driver of the index of the FRR group and an IP address of a new standby next hop when the IP address of the active next hop of the FRR group fails; the driver looking up the software table for the corresponding index of the ECMP group according to the index of the FRR group, and updating the next hop of the ECMP group to the IP address of the new standby next hop to complete the FRR. a. a system starting up an upper layer protocol software to manage and configure a FRR route; b. the upper layer protocol software sending down an IP address of an active next hop of a FRR group and allocating an index to the FRR group different from an index of an equal-cost multi-path routing, ECMP, group; a driver writing the IP address of the active next hop of the FRR group into an ECMP table of an ASIC chip and creating a software table to store correspondence between the FRR group and the corresponding ECMP group on the chip; c. the upper layer protocol software informing the driver of a prefix address of a subnet route and the index of the FRR group, and the driver finding the corresponding index of the ECMP group in the software table according to the index of the FRR group, and writing information of the subnet route and the index of the ECMP group into hardware; d. the upper layer protocol software informing the driver of the index of the FRR group and an IP address of a new standby next hop when the IP address of the active next hop of the FRR group fails; the driver looking up the software table for the corresponding index of the ECMP group according to the index of the FRR group, and updating the next hop of the ECMP group to the IP address of the new standby next hop to complete the FRR.
A concealing structure for 3G+4G multi-sector antennas, antennas that are integrated into a mast associated with a bench, pillar, facing or similar, including a radome or envelope for said assembly of antennas, wherein the radome or envelope has a prismatic configuration with a quadrangular plan, which is finished off with a square upper cover, and which is configured to be linked to said mast by means of anchors, wherein said prismatic radome or envelope is obtained from four panels, two of which have a C-shaped plan cross section while the other two panels are flat panels (11-11'-11"), one of these flat panels (11'-11") being swingable and with stabilisation means in the closing situation, wherein the panels are fixed to each other, in correspondence with the ends of the free branches of the C-shaped panels, by means of non-metallic screws, such that said screws are separated from the vertical edges of the prismatic radome or envelope.
A method of forming a barrel assembly for an airgun, the method comprising: (a) locating a barrel having a bore extending from a breech end to a muzzle end in a mold (1 50); (b) introducing a polymeric material into the mold to engage a part of the barrel and to form a baffle assembly having: (i) a baffle stack of at least one baffle spaced from the muzzle end, the baffle at least partly defining a radially extending expansion gap, the expansion gap having an open end; (ii) a muzzle end barrel receiving section sized to receive the length of the barrel to locate the muzzle end within the baffle assembly; and (iii) a breech end receiving section sized to receive at least a portion of the breech end and providing features proximate the breech end for operably engaging the barrel assembly with a receiver or stock of the airgun; and (c) removing the barrel, the engaged baffle assembly and the engagement feature from the mold. (a) locating a barrel having a bore extending from a breech end to a muzzle end in a mold (1 50); (b) introducing a polymeric material into the mold to engage a part of the barrel and to form a baffle assembly having: (i) a baffle stack of at least one baffle spaced from the muzzle end, the baffle at least partly defining a radially extending expansion gap, the expansion gap having an open end; (ii) a muzzle end barrel receiving section sized to receive the length of the barrel to locate the muzzle end within the baffle assembly; and (iii) a breech end receiving section sized to receive at least a portion of the breech end and providing features proximate the breech end for operably engaging the barrel assembly with a receiver or stock of the airgun; and (i) a baffle stack of at least one baffle spaced from the muzzle end, the baffle at least partly defining a radially extending expansion gap, the expansion gap having an open end; (ii) a muzzle end barrel receiving section sized to receive the length of the barrel to locate the muzzle end within the baffle assembly; and (iii) a breech end receiving section sized to receive at least a portion of the breech end and providing features proximate the breech end for operably engaging the barrel assembly with a receiver or stock of the airgun; and (c) removing the barrel, the engaged baffle assembly and the engagement feature from the mold.
A microprocessor comprising at least one elementary stochastic computation module able to receive, as input, two random and independent binary input signals (A, B) each representing a binary coding of two respective given input probability values, and able to generate, as output, at least one random binary output signal from two input signals (A, B), said elementary module comprising: - at least one programmable logic unit, able to combine two input signals (A, B) to generate an output signal according to at least one determined logic function, such that the output signal represents a binary coding of an output probability value as a function of the given input probability values; - at least one addressable memory, able to store an output probability value coded by an output signal generated by the logic unit; - at least one first stochastic clock, able to produce a first random impulse clock signal to control the writing speed, in the memory, of an output probability value coded by the output signal generated by the logic unit; - at least one second stochastic clock, able to produce a second random impulse clock signal to control the reading speed of the memory, so as to provide the current evaluation, over a given time window, of an output probability value stored in the memory. - at least one programmable logic unit, able to combine two input signals (A, B) to generate an output signal according to at least one determined logic function, such that the output signal represents a binary coding of an output probability value as a function of the given input probability values; - at least one addressable memory, able to store an output probability value coded by an output signal generated by the logic unit; - at least one first stochastic clock, able to produce a first random impulse clock signal to control the writing speed, in the memory, of an output probability value coded by the output signal generated by the logic unit; - at least one second stochastic clock, able to produce a second random impulse clock signal to control the reading speed of the memory, so as to provide the current evaluation, over a given time window, of an output probability value stored in the memory.