A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, said device comprising a surface having a via feature therein, said via feature comprising a sidewall extending from said surface, and a bottom, said sidewall, said bottom and said surface having a metalizing substrate thereon for deposition of copper, said metalizing substrate comprising a seed layer, the process comprising: immersing said metalizing substrate in an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 25 micrometers, a depth dimension between 50 micrometers and 300 micrometers, and an aspect ratio greater than 2:1, said metalizing substrate providing a cathode for electrolytic deposition of copper thereon, the deposition composition comprising: a source of copper ions; an acid component selected from among an inorganic acid, an organic sulfonic acid, and mixtures thereof; an accelerator; a suppressor; a leveler; and chloride ions; establishing an electrodeposition circuit comprising an anode, said electrolytic composition, said cathode, and a power source; applying a potential between said anode and said cathode that establishes a positive polarity at said anode and a negative polarity at said cathode during a via filling cycle to generate a cathodic electrodeposition current causing reduction of copper ions at said cathode, thereby plating copper onto said substrate at the bottom and sidewall of said via, the via preferentially plating on the bottom and lower sidewall to cause filling of the via from the bottom with copper; during said filling cycle, reversing the polarity of circuit for a plurality of intervals to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via; resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature, wherein a ratio of cumulative duration of cathodic current during copper deposition within said filling cycle to cumulative duration of all anodic potential intervals at said metalizing substrate is at least 80:1; wherein the via filling cycle comprises a plurality of faradaically material anodic potential intervals in each of which an average anodic charge transfer is at least 3 x 10 4 coulombs/cm 2 integrated over a total electrodic surface area of said metalizing substrate, and wherein between successive faradaically material anodic potential intervals, an integrated average cathodic current charge transfer over the total electrodic surface area of said metalizing substrate is at least 1.5 x 10 2 coulombs/cm 2. immersing said metalizing substrate in an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 25 micrometers, a depth dimension between 50 micrometers and 300 micrometers, and an aspect ratio greater than 2:1, said metalizing substrate providing a cathode for electrolytic deposition of copper thereon, the deposition composition comprising: a source of copper ions; an acid component selected from among an inorganic acid, an organic sulfonic acid, and mixtures thereof; an accelerator; a suppressor; a leveler; and chloride ions; a source of copper ions; an acid component selected from among an inorganic acid, an organic sulfonic acid, and mixtures thereof; an accelerator; a suppressor; a leveler; and chloride ions; establishing an electrodeposition circuit comprising an anode, said electrolytic composition, said cathode, and a power source; applying a potential between said anode and said cathode that establishes a positive polarity at said anode and a negative polarity at said cathode during a via filling cycle to generate a cathodic electrodeposition current causing reduction of copper ions at said cathode, thereby plating copper onto said substrate at the bottom and sidewall of said via, the via preferentially plating on the bottom and lower sidewall to cause filling of the via from the bottom with copper; during said filling cycle, reversing the polarity of circuit for a plurality of intervals to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via; resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature, wherein a ratio of cumulative duration of cathodic current during copper deposition within said filling cycle to cumulative duration of all anodic potential intervals at said metalizing substrate is at least 80:1; wherein the via filling cycle comprises a plurality of faradaically material anodic potential intervals in each of which an average anodic charge transfer is at least 3 x 10 4 coulombs/cm 2 integrated over a total electrodic surface area of said metalizing substrate, and wherein between successive faradaically material anodic potential intervals, an integrated average cathodic current charge transfer over the total electrodic surface area of said metalizing substrate is at least 1.5 x 10 2 coulombs/cm 2.