An apparatus (104, 204, 1104, 1106) comprising: an interface circuit of a slave device (104, 204, 1104, 1106) and for coupling to a two wire communication link (110, 205), the interface circuit to: receive, from a master device (102, 202, 1102) via a first single wire bus of the two wire communication link (110, 205), a first synchronization command with delay setting information (232, 1012, 1108, 1112), and receive, from the master device (102, 202, 1102) via the first bus of the two wire communication link (110, 205), a second synchronization command (210, 1116) for generating a trigger signal after the reception of the first synchronization command; a control circuit of the slave device (104, 204, 1104, 1106) to: track a number of selected transitions of a clock signal (108, 208, 1008) following the reception of the second synchronization command (210, 1116), wherein the clock signal (108, 208, 1008) is carried by a second single wire bus of the two wire communication link (110, 205), generate the trigger signal (1036, 1118, 1122) to perform a time-delayed measurement, wherein the trigger signal (1036, 1118, 1122) is responsive to the number of selected transitions reaching a delay setting (1016, 1120, 1124) indicated by the delay setting information (232, 1012, 1108, 1112), and receive data in response to the time-delayed measurement; wherein the interface circuit is configured to transmit the data to the master device (102, 202, 1102) over the first single wire bus of the two wire communication link (110, 205) in response to a poll from the master device (102, 202, 1102). an interface circuit of a slave device (104, 204, 1104, 1106) and for coupling to a two wire communication link (110, 205), the interface circuit to: receive, from a master device (102, 202, 1102) via a first single wire bus of the two wire communication link (110, 205), a first synchronization command with delay setting information (232, 1012, 1108, 1112), and receive, from the master device (102, 202, 1102) via the first bus of the two wire communication link (110, 205), a second synchronization command (210, 1116) for generating a trigger signal after the reception of the first synchronization command; receive, from a master device (102, 202, 1102) via a first single wire bus of the two wire communication link (110, 205), a first synchronization command with delay setting information (232, 1012, 1108, 1112), and receive, from the master device (102, 202, 1102) via the first bus of the two wire communication link (110, 205), a second synchronization command (210, 1116) for generating a trigger signal after the reception of the first synchronization command; a control circuit of the slave device (104, 204, 1104, 1106) to: track a number of selected transitions of a clock signal (108, 208, 1008) following the reception of the second synchronization command (210, 1116), wherein the clock signal (108, 208, 1008) is carried by a second single wire bus of the two wire communication link (110, 205), generate the trigger signal (1036, 1118, 1122) to perform a time-delayed measurement, wherein the trigger signal (1036, 1118, 1122) is responsive to the number of selected transitions reaching a delay setting (1016, 1120, 1124) indicated by the delay setting information (232, 1012, 1108, 1112), and receive data in response to the time-delayed measurement; wherein the interface circuit is configured to transmit the data to the master device (102, 202, 1102) over the first single wire bus of the two wire communication link (110, 205) in response to a poll from the master device (102, 202, 1102). track a number of selected transitions of a clock signal (108, 208, 1008) following the reception of the second synchronization command (210, 1116), wherein the clock signal (108, 208, 1008) is carried by a second single wire bus of the two wire communication link (110, 205), generate the trigger signal (1036, 1118, 1122) to perform a time-delayed measurement, wherein the trigger signal (1036, 1118, 1122) is responsive to the number of selected transitions reaching a delay setting (1016, 1120, 1124) indicated by the delay setting information (232, 1012, 1108, 1112), and receive data in response to the time-delayed measurement; wherein the interface circuit is configured to transmit the data to the master device (102, 202, 1102) over the first single wire bus of the two wire communication link (110, 205) in response to a poll from the master device (102, 202, 1102).