A nonvolatile memory structure, comprising: a substrate comprising a first active region (102, 700), a second active region (104, 702), and an n-type erase region, wherein the n-type erase region is insulated from the first active region (102, 700) and the second active region (104, 702); a p-type well surrounding the n-type erase region; a first PMOS transistor and a first floating-gate transistor on the first active region (102, 700) respectively, wherein the first PMOS transistor includes a first select gate (108a, SG1), the first floating-gate transistor includes a first floating gate (110a, FG1) between the first select gate and the n-type erase region, and the first floating gate comprises an extended portion extending in a first direction to a first portion of the n-type erase region; a second PMOS transistor and a second floating-gate transistor on the second active region (104, 702) respectively, wherein the second PMOS transistor includes a second select gate (112a, SG2), the second floating-gate transistor includes a second floating gate (114a, FG2) between the second select gate and the n-type erase region, and the second floating gate comprises an extended portion extending in the first direction to a second portion of the n-type erase region; a source line connected with sources of the first PMOS transistor and the second PMOS transistor; a bit line connected with a drain of the first floating-gate transistor; a word line connected with the first select gate and the second select gate; and an erase line connected with the n-type erase region, wherein an overlap area between the first floating gate and the first active region is A1, an overlap area between the first floating gate and the n-type erase region is A2, and a ratio of A1 to a sum of A1 and A2 is more than 75%, wherein an overlap area between the second floating gate and the second active region is A3, an overlap area between the second floating gate and the n-type erase region is A4, and a ratio of A3 to a sum of A3 and A4 is more than 75%, wherein the first direction is perpendicular to an extending direction of the n-type erase region, the first active region (102, 700) extends in a second direction from under the first PMOS transistor to under the first floating-gate transistor, and the second active region (104, 702) extends in a third direction from under the second PMOS transistor to under the second floating-gate transistor, characterized in that the bit line is connected with a drain of the second floating-gate transistor; the first direction is parallel to the second direction and to the third direction and the n-type erase region is a n+ region. a substrate comprising a first active region (102, 700), a second active region (104, 702), and an n-type erase region, wherein the n-type erase region is insulated from the first active region (102, 700) and the second active region (104, 702); a p-type well surrounding the n-type erase region; a first PMOS transistor and a first floating-gate transistor on the first active region (102, 700) respectively, wherein the first PMOS transistor includes a first select gate (108a, SG1), the first floating-gate transistor includes a first floating gate (110a, FG1) between the first select gate and the n-type erase region, and the first floating gate comprises an extended portion extending in a first direction to a first portion of the n-type erase region; a second PMOS transistor and a second floating-gate transistor on the second active region (104, 702) respectively, wherein the second PMOS transistor includes a second select gate (112a, SG2), the second floating-gate transistor includes a second floating gate (114a, FG2) between the second select gate and the n-type erase region, and the second floating gate comprises an extended portion extending in the first direction to a second portion of the n-type erase region; a source line connected with sources of the first PMOS transistor and the second PMOS transistor; a bit line connected with a drain of the first floating-gate transistor; a word line connected with the first select gate and the second select gate; and an erase line connected with the n-type erase region, wherein an overlap area between the first floating gate and the first active region is A1, an overlap area between the first floating gate and the n-type erase region is A2, and a ratio of A1 to a sum of A1 and A2 is more than 75%, wherein an overlap area between the second floating gate and the second active region is A3, an overlap area between the second floating gate and the n-type erase region is A4, and a ratio of A3 to a sum of A3 and A4 is more than 75%, wherein the first direction is perpendicular to an extending direction of the n-type erase region, the first active region (102, 700) extends in a second direction from under the first PMOS transistor to under the first floating-gate transistor, and the second active region (104, 702) extends in a third direction from under the second PMOS transistor to under the second floating-gate transistor, characterized in that the bit line is connected with a drain of the second floating-gate transistor; the first direction is parallel to the second direction and to the third direction and the n-type erase region is a n+ region.