A non-volatile semiconductor memory device comprising: a plurality of memory cell units, each including a plurality of non-volatile memory cells capable of having data electrically rewritten therein; and a storage unit (54; 82; 88; 100b) configured to store defect information identifying one or more defective memory cell units among the plurality of memory cell units; characterised by: an access inhibiting circuit (30, 14; 68, 14; 86, 14) configured to inhibit access to the defective memory cell unit and to set the memory device to a ready status when a command (BCOM, RCOM, ECOM, ADD) fed from an exterior of the memory device is detected as an access to the defective memory cell unit (BBLKFLG) according to the defect information stored in the memory cell unit, a bad block outputting circuit configured to output a flag signal to a flag terminal (FLG#) in response to a detection of the access to the defective memory cell units (BBLKFLG), wherein the flag signal indicates that the access to the defective memory cell is inhibited, and a controlling circuit configured to set a ready/busy terminal (RY/BT#) to the ready status in response to the detection of the access to the defective memory cell units (BBLKFLG). a plurality of memory cell units, each including a plurality of non-volatile memory cells capable of having data electrically rewritten therein; and a storage unit (54; 82; 88; 100b) configured to store defect information identifying one or more defective memory cell units among the plurality of memory cell units; characterised by: an access inhibiting circuit (30, 14; 68, 14; 86, 14) configured to inhibit access to the defective memory cell unit and to set the memory device to a ready status when a command (BCOM, RCOM, ECOM, ADD) fed from an exterior of the memory device is detected as an access to the defective memory cell unit (BBLKFLG) according to the defect information stored in the memory cell unit, a bad block outputting circuit configured to output a flag signal to a flag terminal (FLG#) in response to a detection of the access to the defective memory cell units (BBLKFLG), wherein the flag signal indicates that the access to the defective memory cell is inhibited, and a controlling circuit configured to set a ready/busy terminal (RY/BT#) to the ready status in response to the detection of the access to the defective memory cell units (BBLKFLG). an access inhibiting circuit (30, 14; 68, 14; 86, 14) configured to inhibit access to the defective memory cell unit and to set the memory device to a ready status when a command (BCOM, RCOM, ECOM, ADD) fed from an exterior of the memory device is detected as an access to the defective memory cell unit (BBLKFLG) according to the defect information stored in the memory cell unit, a bad block outputting circuit configured to output a flag signal to a flag terminal (FLG#) in response to a detection of the access to the defective memory cell units (BBLKFLG), wherein the flag signal indicates that the access to the defective memory cell is inhibited, and a controlling circuit configured to set a ready/busy terminal (RY/BT#) to the ready status in response to the detection of the access to the defective memory cell units (BBLKFLG).