An antifuse one time programmable memory cell comprising: an antifuse unit, disposed on a substrate, wherein the substrate has a first conductive type, and the antifuse unit comprises: an antifuse gate, disposed on the substrate; an antifuse layer, disposed between the antifuse gate and the substrate; and a first doped region and a second doped region, having a second conductive type, and respectively disposed in the substrate at two opposite sides of the antifuse gate; a select transistor, disposed on the substrate and comprising: a select gate, disposed on the substrate; a gate dielectric layer, disposed between the select gate and the substrate; and the second doped region and a third doped region, having the second conductive type, and respectively disposed in the substrate at two opposite sides of the select gate, characterized in that the antifuse unit comprises a modified extension doped region, having the second conductive type, and disposed in the substrate below the antifuse layer, wherein the antifuse layer, the antifuse gate and the modified extension doped region form a varactor; wherein the select transistor is a gate dielectric layer metal oxide semiconductor transistor, and a thickness of the gate dielectric layer close to the second doped region is greater than a thickness of the gate dielectric layer close to the third doped region, wherein the select transistor further comprises: a lightly doped region, having the second conductive type, and disposed between the select gate and the second doped region; and a source/drain extension, having the second conductive type, and disposed between the select gate and the third doped region, wherein a junction depth of the source/drain extension is smaller than a junction depth of the lightly doped region, and a doping concentration of the source/drain extension is greater than the doping concentration of the lightly doped region. an antifuse unit, disposed on a substrate, wherein the substrate has a first conductive type, and the antifuse unit comprises: an antifuse gate, disposed on the substrate; an antifuse layer, disposed between the antifuse gate and the substrate; and a first doped region and a second doped region, having a second conductive type, and respectively disposed in the substrate at two opposite sides of the antifuse gate; an antifuse gate, disposed on the substrate; an antifuse layer, disposed between the antifuse gate and the substrate; and a first doped region and a second doped region, having a second conductive type, and respectively disposed in the substrate at two opposite sides of the antifuse gate; a select transistor, disposed on the substrate and comprising: a select gate, disposed on the substrate; a gate dielectric layer, disposed between the select gate and the substrate; and the second doped region and a third doped region, having the second conductive type, and respectively disposed in the substrate at two opposite sides of the select gate, a select gate, disposed on the substrate; a gate dielectric layer, disposed between the select gate and the substrate; and the second doped region and a third doped region, having the second conductive type, and respectively disposed in the substrate at two opposite sides of the select gate, characterized in that the antifuse unit comprises a modified extension doped region, having the second conductive type, and disposed in the substrate below the antifuse layer, wherein the antifuse layer, the antifuse gate and the modified extension doped region form a varactor; wherein the select transistor is a gate dielectric layer metal oxide semiconductor transistor, and a thickness of the gate dielectric layer close to the second doped region is greater than a thickness of the gate dielectric layer close to the third doped region, wherein the select transistor further comprises: a lightly doped region, having the second conductive type, and disposed between the select gate and the second doped region; and a source/drain extension, having the second conductive type, and disposed between the select gate and the third doped region, wherein a junction depth of the source/drain extension is smaller than a junction depth of the lightly doped region, and a doping concentration of the source/drain extension is greater than the doping concentration of the lightly doped region. a lightly doped region, having the second conductive type, and disposed between the select gate and the second doped region; and a source/drain extension, having the second conductive type, and disposed between the select gate and the third doped region, wherein a junction depth of the source/drain extension is smaller than a junction depth of the lightly doped region, and a doping concentration of the source/drain extension is greater than the doping concentration of the lightly doped region.