A computer implemented method for generating a set of pulse-width modulation, PWM, control signals for a multi-level power converter, the method comprising: generating a base reference signal (502, 504, 506) for each of three or more reference phases, characterized in that the method further comprises: determining a maximum reference, max, and minimum reference, min, based on the base reference signals (502, 504, 506); calculating a reference sum of the maximum reference and the minimum reference; generating a first offset, calculated as 1-max when the reference sum is positive and -1-min when the reference sum is negative; generating a second offset, calculated as -1-min when the reference sum is positive and 1-max when the reference sum is negative; for each of the three reference phases: generating an upper reference, calculated by adding the first offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the second offset when the signal (502, 504, 506) is negative; generating a lower reference, calculated by adding the second offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the first offset when the signal (502, 504, 506) is negative; comparing the upper reference to a triangular upper carrier signal to generate an upper PWM output; comparing the lower reference to a triangular lower carrier signal to generate a lower PWM output; and combining the upper PWM output and lower PWM output to generate a multi-level PWM control signal for the reference phase; and outputting a set of multi-level PWM control signals generated for the three or more reference phases to a multi-level power converter. generating a base reference signal (502, 504, 506) for each of three or more reference phases, characterized in that the method further comprises: determining a maximum reference, max, and minimum reference, min, based on the base reference signals (502, 504, 506); calculating a reference sum of the maximum reference and the minimum reference; generating a first offset, calculated as 1-max when the reference sum is positive and -1-min when the reference sum is negative; generating a second offset, calculated as -1-min when the reference sum is positive and 1-max when the reference sum is negative; for each of the three reference phases: generating an upper reference, calculated by adding the first offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the second offset when the signal (502, 504, 506) is negative; generating a lower reference, calculated by adding the second offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the first offset when the signal (502, 504, 506) is negative; comparing the upper reference to a triangular upper carrier signal to generate an upper PWM output; comparing the lower reference to a triangular lower carrier signal to generate a lower PWM output; and combining the upper PWM output and lower PWM output to generate a multi-level PWM control signal for the reference phase; and outputting a set of multi-level PWM control signals generated for the three or more reference phases to a multi-level power converter. determining a maximum reference, max, and minimum reference, min, based on the base reference signals (502, 504, 506); calculating a reference sum of the maximum reference and the minimum reference; generating a first offset, calculated as 1-max when the reference sum is positive and -1-min when the reference sum is negative; generating a second offset, calculated as -1-min when the reference sum is positive and 1-max when the reference sum is negative; for each of the three reference phases: generating an upper reference, calculated by adding the first offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the second offset when the signal (502, 504, 506) is negative; generating a lower reference, calculated by adding the second offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the first offset when the signal (502, 504, 506) is negative; comparing the upper reference to a triangular upper carrier signal to generate an upper PWM output; comparing the lower reference to a triangular lower carrier signal to generate a lower PWM output; and combining the upper PWM output and lower PWM output to generate a multi-level PWM control signal for the reference phase; and generating an upper reference, calculated by adding the first offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the second offset when the signal (502, 504, 506) is negative; generating a lower reference, calculated by adding the second offset to the base reference signal (502, 504, 506) when the signal (502, 504, 506) is positive and adding the first offset when the signal (502, 504, 506) is negative; comparing the upper reference to a triangular upper carrier signal to generate an upper PWM output; comparing the lower reference to a triangular lower carrier signal to generate a lower PWM output; and combining the upper PWM output and lower PWM output to generate a multi-level PWM control signal for the reference phase; and outputting a set of multi-level PWM control signals generated for the three or more reference phases to a multi-level power converter.