A method for manufacturing a photodetection device, which includes the following steps: a) depositing, onto a semiconductor substrate (110; 210; 310) of CdxHg 1-x Te, a source coating which includes at least one cadmium-rich layer having a higher average cadmium concentration than the semiconductor substrate, with the cadmium-rich layer being in direct physical contact with an upper face (111; 311) of the semiconductor substrate; b) making a first etch mask (140; 240), superimposed on the source coating on the side opposite to the semiconductor substrate; c) first etching step, to etch the source coating across the first etch mask (140; 240) and thus forming at least one first through opening in the source coating, the source coating provided with the at least one first through opening being called a structured coating (122; 222; 422); d) second etching step, to widen at least one second through opening (141; 291) in a structure (140; 290) on top of the structured coating (122; 222) at the end of the first etching step, and thus to form a second etch mask (150; 250; 450); e) injecting acceptor dopant elements into the semiconductor substrate (110; 210; 310), across through openings in the second etch mask (150; 250; 450), with the acceptor dopant elements passing locally through the structured coating (122; 222); f) activating and diffusing the acceptor dopant elements to form at least one P-doped region in the semiconductor substrate; g) selectively interdiffusion annealing the cadmium, implemented after step f) or at least partly simultaneously with step f), during which cadmium atoms diffuse from the structured coating (122; 222) towards the at least one P-doped region, so as to form, in each P-doped region, a concentrated case with at least one intermediate-gap zone and at least one high-gap zone, where the intermediate-gap zone has an average cadmium concentration strictly lower than the average cadmium concentration in the high-gap zone; and h) depositing a metal layer contacting the semiconductor substrate (110; 210; 310) at the at least one first through opening in the structured coating (122; 222), to form at least one electrical contact pad. a) depositing, onto a semiconductor substrate (110; 210; 310) of CdxHg 1-x Te, a source coating which includes at least one cadmium-rich layer having a higher average cadmium concentration than the semiconductor substrate, with the cadmium-rich layer being in direct physical contact with an upper face (111; 311) of the semiconductor substrate; b) making a first etch mask (140; 240), superimposed on the source coating on the side opposite to the semiconductor substrate; c) first etching step, to etch the source coating across the first etch mask (140; 240) and thus forming at least one first through opening in the source coating, the source coating provided with the at least one first through opening being called a structured coating (122; 222; 422); d) second etching step, to widen at least one second through opening (141; 291) in a structure (140; 290) on top of the structured coating (122; 222) at the end of the first etching step, and thus to form a second etch mask (150; 250; 450); e) injecting acceptor dopant elements into the semiconductor substrate (110; 210; 310), across through openings in the second etch mask (150; 250; 450), with the acceptor dopant elements passing locally through the structured coating (122; 222); f) activating and diffusing the acceptor dopant elements to form at least one P-doped region in the semiconductor substrate; g) selectively interdiffusion annealing the cadmium, implemented after step f) or at least partly simultaneously with step f), during which cadmium atoms diffuse from the structured coating (122; 222) towards the at least one P-doped region, so as to form, in each P-doped region, a concentrated case with at least one intermediate-gap zone and at least one high-gap zone, where the intermediate-gap zone has an average cadmium concentration strictly lower than the average cadmium concentration in the high-gap zone; and h) depositing a metal layer contacting the semiconductor substrate (110; 210; 310) at the at least one first through opening in the structured coating (122; 222), to form at least one electrical contact pad.