A multi-channel class-D amplifier comprising: a signal source; and plurality of class-D amplifier channel modules (304-0 to 304-N-1), wherein: the signal source provides a plurality of input signals (INPUT-0 to INPUT-N-1) and generates a synchronization signal (SYNC2), the synchronization signal comprising information for switching frequencies and processing offsets for each of the plurality of class-D amplifier channel modules (304-0 to 304-N-1); each class-D amplifier channel module is configured to process a corresponding input signal from the plurality of input signals to produce a corresponding output signal (OUTPUT-0 to OUTPUT-N-1) whereby: the same switching frequency is employed for the plurality of class-D amplifier channel modules; and the processing of the plurality of input signals is offset in time across the plurality of class-D amplifier channel modules according to the processing offsets; the multi-channel class-D amplifier is characterised by: the signal source providing the synchronization signal such that the synchronization signal further comprises a plurality of coded portions wherein each coded portion corresponds to one of the class-D amplifier channels; and each class-D amplifier channel module comprising a synchronization module (306-0 to 306-N-1) configured to recognize an occurrence of its assigned coded portion in the synchronization signal and upon recognition generate a sync signal to process its corresponding input signal. a signal source; and plurality of class-D amplifier channel modules (304-0 to 304-N-1), wherein: the signal source provides a plurality of input signals (INPUT-0 to INPUT-N-1) and generates a synchronization signal (SYNC2), the synchronization signal comprising information for switching frequencies and processing offsets for each of the plurality of class-D amplifier channel modules (304-0 to 304-N-1); each class-D amplifier channel module is configured to process a corresponding input signal from the plurality of input signals to produce a corresponding output signal (OUTPUT-0 to OUTPUT-N-1) whereby: the same switching frequency is employed for the plurality of class-D amplifier channel modules; and the processing of the plurality of input signals is offset in time across the plurality of class-D amplifier channel modules according to the processing offsets; the multi-channel class-D amplifier is characterised by: the signal source providing the synchronization signal such that the synchronization signal further comprises a plurality of coded portions wherein each coded portion corresponds to one of the class-D amplifier channels; and each class-D amplifier channel module comprising a synchronization module (306-0 to 306-N-1) configured to recognize an occurrence of its assigned coded portion in the synchronization signal and upon recognition generate a sync signal to process its corresponding input signal. the signal source provides a plurality of input signals (INPUT-0 to INPUT-N-1) and generates a synchronization signal (SYNC2), the synchronization signal comprising information for switching frequencies and processing offsets for each of the plurality of class-D amplifier channel modules (304-0 to 304-N-1); each class-D amplifier channel module is configured to process a corresponding input signal from the plurality of input signals to produce a corresponding output signal (OUTPUT-0 to OUTPUT-N-1) whereby: the same switching frequency is employed for the plurality of class-D amplifier channel modules; and the processing of the plurality of input signals is offset in time across the plurality of class-D amplifier channel modules according to the processing offsets; the multi-channel class-D amplifier is characterised by: the signal source providing the synchronization signal such that the synchronization signal further comprises a plurality of coded portions wherein each coded portion corresponds to one of the class-D amplifier channels; and each class-D amplifier channel module comprising a synchronization module (306-0 to 306-N-1) configured to recognize an occurrence of its assigned coded portion in the synchronization signal and upon recognition generate a sync signal to process its corresponding input signal.