A sense-amplifier circuit, for a non-volatile memory device having a memory array with memory cells arranged in wordlines and bitlines, comprising: a biasing stage, configured to bias at least one bitline of said memory array for pre-charging said bitline in a pre-charging step of a reading operation of a datum stored in a corresponding memory cell; and a current-to-voltage converter stage, having a differential configuration with a first circuit branch and a second circuit branch, which are designed to receive on a respective comparison input (IN a, IN b), during a reading step of the datum subsequent to the pre-charging step, a cell current (I cell) from the bitline and a reference current (I ref) from a current-reference structure and to supply an output voltage (V out) between a respective first differential output terminal (out a) and second differential output terminal (out b), wherein each of said first and second circuit branches comprises a respective amplification module (22a, 22b), configured to generate during said reading step a respective amplified voltage (V a, V b) as a function, respectively, of the cell current and of the reference current, said output voltage (V out) being a function of the difference between said amplified voltages (V a, V b) and indicative of the value of said datum, wherein said current-to-voltage converter stage comprises a capacitive compensation module configured to detect and store an offset between said first circuit branch and said second circuit branch during said pre-charging step, and to compensate said offset in the output voltage (V out) during said reading step of the stored datum, characterized in that each of said first and second circuit branches (12a, 12b) further comprises a respective transconductance module (24a, 24b) having: a respective input (N3 a, N3 b), selectively connected to an output (N2 a, N2 b) of the respective amplification module (22a, 22b), during said pre-charging step, for receiving a respective feedback voltage (Vg a, Vg b); and a respective output connected to an input (N1 a, N1 b) of the respective amplification module (22a, 22b) and designed to supply a respective regeneration current (Id a, Id b), which is a function of the respective feedback voltage (Vg a, Vg b). a biasing stage, configured to bias at least one bitline of said memory array for pre-charging said bitline in a pre-charging step of a reading operation of a datum stored in a corresponding memory cell; and a current-to-voltage converter stage, having a differential configuration with a first circuit branch and a second circuit branch, which are designed to receive on a respective comparison input (IN a, IN b), during a reading step of the datum subsequent to the pre-charging step, a cell current (I cell) from the bitline and a reference current (I ref) from a current-reference structure and to supply an output voltage (V out) between a respective first differential output terminal (out a) and second differential output terminal (out b), wherein each of said first and second circuit branches comprises a respective amplification module (22a, 22b), configured to generate during said reading step a respective amplified voltage (V a, V b) as a function, respectively, of the cell current and of the reference current, said output voltage (V out) being a function of the difference between said amplified voltages (V a, V b) and indicative of the value of said datum, wherein said current-to-voltage converter stage comprises a capacitive compensation module configured to detect and store an offset between said first circuit branch and said second circuit branch during said pre-charging step, and to compensate said offset in the output voltage (V out) during said reading step of the stored datum, characterized in that each of said first and second circuit branches (12a, 12b) further comprises a respective transconductance module (24a, 24b) having: a respective input (N3 a, N3 b), selectively connected to an output (N2 a, N2 b) of the respective amplification module (22a, 22b), during said pre-charging step, for receiving a respective feedback voltage (Vg a, Vg b); and a respective output connected to an input (N1 a, N1 b) of the respective amplification module (22a, 22b) and designed to supply a respective regeneration current (Id a, Id b), which is a function of the respective feedback voltage (Vg a, Vg b).