An apparatus comprising: a memory controller comprising a word line control module and a bit line control module, wherein the word line control module includes a word line selection logic, the bit line control module includes a bit line selection logic, the word line selection logic or the bit line selection logic includes a switching device which is a metal oxide semiconductor field effect transistor, MOSFET, and the memory controller is configured to initiate selection of a memory cell in a phase change memory; a selection current source; a pulse current source; and a mitigation module (120, 124) configured to reduce a transient energy dissipation related to snap back occurring when selecting the memory cell, by: enabling the selection current source to provide a selection current greater than or equal to a hold current associated with the memory cell to select the memory cell; during provision of the selection current, controlling the switching device to provide a first drain-source resistance for the switching device in a current path, the current path being through the word line selection logic, the memory cell, the bit line selection logic; after the snap back of the memory cell, controlling the switching device to provide a second drain-source resistance for the switching device in the current path to increase an allowable current to the memory cell, the second drain-source resistance arranged to be less than the first drain-source resistance; enabling the pulse current source to provide a pulse current to the memory cell to at least one of read from and/or program the memory cell; and disabling the selection current source when the pulse current source is enabled. a memory controller comprising a word line control module and a bit line control module, wherein the word line control module includes a word line selection logic, the bit line control module includes a bit line selection logic, the word line selection logic or the bit line selection logic includes a switching device which is a metal oxide semiconductor field effect transistor, MOSFET, and the memory controller is configured to initiate selection of a memory cell in a phase change memory; a selection current source; a pulse current source; and a mitigation module (120, 124) configured to reduce a transient energy dissipation related to snap back occurring when selecting the memory cell, by: enabling the selection current source to provide a selection current greater than or equal to a hold current associated with the memory cell to select the memory cell; during provision of the selection current, controlling the switching device to provide a first drain-source resistance for the switching device in a current path, the current path being through the word line selection logic, the memory cell, the bit line selection logic; after the snap back of the memory cell, controlling the switching device to provide a second drain-source resistance for the switching device in the current path to increase an allowable current to the memory cell, the second drain-source resistance arranged to be less than the first drain-source resistance; enabling the pulse current source to provide a pulse current to the memory cell to at least one of read from and/or program the memory cell; and disabling the selection current source when the pulse current source is enabled. enabling the selection current source to provide a selection current greater than or equal to a hold current associated with the memory cell to select the memory cell; during provision of the selection current, controlling the switching device to provide a first drain-source resistance for the switching device in a current path, the current path being through the word line selection logic, the memory cell, the bit line selection logic; after the snap back of the memory cell, controlling the switching device to provide a second drain-source resistance for the switching device in the current path to increase an allowable current to the memory cell, the second drain-source resistance arranged to be less than the first drain-source resistance; enabling the pulse current source to provide a pulse current to the memory cell to at least one of read from and/or program the memory cell; and disabling the selection current source when the pulse current source is enabled.