A nonvolatile memory comprising a first one-bit memory cell, wherein the first one-bit memory cell is formed on a substrate, and the first one-bit memory cell comprises: a first bit line; and N storage units (SU1, SU2, SU3, SU4), wherein each of the N storage units (SU1, SU2, SU3, SU4) comprises a first doped region (11, 21, 31, 41), a second doped region (12, 22, 32, 42) and a third doped region (13, 23, 33, 43), which are formed in a surface of the substrate, wherein a first gate structure (14, 15; 24, 25, 34, 35; 44, 45) is disposed over a first channel region between the first doped region (11, 21, 31, 41) and the second doped region (12, 22, 32, 42), and a second gate structure (16, 17; 26, 27; 36, 37; 46, 47) is disposed over a second channel region between the second doped region (12, 22, 32, 42) and the third doped region (13, 23, 33, 43), wherein the first doped region of the first storage unit is connected to the first bit line, the first gate structure (14, 15) of the first storage unit is connected to a first control signal line, and the second gate structure (16, 17) of the first storage unit is connected to a first anti-fuse signal line, wherein the first doped region (21, 31, 41) of the m-th storage unit (SU2, SU3, SU4) is connected to the third doped region (13, 23, 33), of the (m-1)-th storage unit (SU1, SU2, SU3), the first gate structure (24, 25, 34, 35; 44, 45) of the m-th storage unit (SU2, SU3, SU4) is connected to an m-th control signal line (C2, C3, C4), and the second gate structure (26, 27; 36, 37; 46, 47) of the m-th storage unit (SU2, SU3, SU4) is connected to an m-th anti-fuse signal line (AF2, AF3, AF4), wherein m is an integer larger than or equal to 2 and smaller than or equal to N. a first bit line; and N storage units (SU1, SU2, SU3, SU4), wherein each of the N storage units (SU1, SU2, SU3, SU4) comprises a first doped region (11, 21, 31, 41), a second doped region (12, 22, 32, 42) and a third doped region (13, 23, 33, 43), which are formed in a surface of the substrate, wherein a first gate structure (14, 15; 24, 25, 34, 35; 44, 45) is disposed over a first channel region between the first doped region (11, 21, 31, 41) and the second doped region (12, 22, 32, 42), and a second gate structure (16, 17; 26, 27; 36, 37; 46, 47) is disposed over a second channel region between the second doped region (12, 22, 32, 42) and the third doped region (13, 23, 33, 43), wherein the first doped region of the first storage unit is connected to the first bit line, the first gate structure (14, 15) of the first storage unit is connected to a first control signal line, and the second gate structure (16, 17) of the first storage unit is connected to a first anti-fuse signal line, wherein the first doped region (21, 31, 41) of the m-th storage unit (SU2, SU3, SU4) is connected to the third doped region (13, 23, 33), of the (m-1)-th storage unit (SU1, SU2, SU3), the first gate structure (24, 25, 34, 35; 44, 45) of the m-th storage unit (SU2, SU3, SU4) is connected to an m-th control signal line (C2, C3, C4), and the second gate structure (26, 27; 36, 37; 46, 47) of the m-th storage unit (SU2, SU3, SU4) is connected to an m-th anti-fuse signal line (AF2, AF3, AF4), wherein m is an integer larger than or equal to 2 and smaller than or equal to N.