A circuit for receiving serial data, the circuit having an input for receiving an analog input signal (Vin) and comprising: a baud-rate clock and data recovery circuit, comprising: a first sampler for sampling the analog input signal (Vin) relative to a first reference voltage (α); a second sampler for sampling the analog input signal (Vin) relative to a second reference voltage (-α), the second reference voltage (-α) having a sign opposite to that of the first reference voltage (α); and a reference voltage control circuit configured to adjust the first reference voltage (α) and the second reference voltage (-α), based on a first sample of the analog input signal (Vin), the first sample taken at a sampling time corresponding to a middle one bit of three consecutive one bits, wherein the magnitude of the second reference voltage (-α) equals the magnitude of the first reference voltage (α), wherein: the reference voltage control circuit is configured to adjust a third reference voltage (3α) based on the first sample, and the first reference voltage (α) is equal to a function of the third reference voltage (3α), and wherein the reference voltage control circuit comprises: a third sampler for sampling the analog input signal (Vin) relative to the third reference voltage (3α); a first pattern filter to select a bit pattern comprising the three consecutive one bits; and a first accumulator for accumulating, in a register of the first accumulator, output values of the third sampler for samples corresponding to the second bit of each pattern matched by the first pattern filter, and configured to provide an output for said adjustment of the third reference voltage. a baud-rate clock and data recovery circuit, comprising: a first sampler for sampling the analog input signal (Vin) relative to a first reference voltage (α); a second sampler for sampling the analog input signal (Vin) relative to a second reference voltage (-α), the second reference voltage (-α) having a sign opposite to that of the first reference voltage (α); and a first sampler for sampling the analog input signal (Vin) relative to a first reference voltage (α); a second sampler for sampling the analog input signal (Vin) relative to a second reference voltage (-α), the second reference voltage (-α) having a sign opposite to that of the first reference voltage (α); and a reference voltage control circuit configured to adjust the first reference voltage (α) and the second reference voltage (-α), based on a first sample of the analog input signal (Vin), the first sample taken at a sampling time corresponding to a middle one bit of three consecutive one bits, wherein the magnitude of the second reference voltage (-α) equals the magnitude of the first reference voltage (α), wherein: the reference voltage control circuit is configured to adjust a third reference voltage (3α) based on the first sample, and the first reference voltage (α) is equal to a function of the third reference voltage (3α), and wherein the reference voltage control circuit comprises: a third sampler for sampling the analog input signal (Vin) relative to the third reference voltage (3α); a first pattern filter to select a bit pattern comprising the three consecutive one bits; and a first accumulator for accumulating, in a register of the first accumulator, output values of the third sampler for samples corresponding to the second bit of each pattern matched by the first pattern filter, and configured to provide an output for said adjustment of the third reference voltage. the reference voltage control circuit is configured to adjust a third reference voltage (3α) based on the first sample, and the first reference voltage (α) is equal to a function of the third reference voltage (3α), and wherein the reference voltage control circuit comprises: a third sampler for sampling the analog input signal (Vin) relative to the third reference voltage (3α); a first pattern filter to select a bit pattern comprising the three consecutive one bits; and a first accumulator for accumulating, in a register of the first accumulator, output values of the third sampler for samples corresponding to the second bit of each pattern matched by the first pattern filter, and configured to provide an output for said adjustment of the third reference voltage. a third sampler for sampling the analog input signal (Vin) relative to the third reference voltage (3α); a first pattern filter to select a bit pattern comprising the three consecutive one bits; and a first accumulator for accumulating, in a register of the first accumulator, output values of the third sampler for samples corresponding to the second bit of each pattern matched by the first pattern filter, and configured to provide an output for said adjustment of the third reference voltage.