Process for collectively curving a set of electronic chips, comprising the steps: a) providing the set of electronic chips, said chips having been diced beforehand and each comprising a stack comprising: - a matrix-array of pixels, - an interconnect layer, electrically connected to the matrix-array of pixels, - a first layer, comprising through-vias that are electrically connected to the interconnect layer; the stack possessing a first thickness and a first coefficient of thermal expansion; b) joining the set of diced electronic chips to a carrier substrate, via the side opposite the first layers, so as to leave a spacing region between adjacent electronic chips; c) forming a redistribution layer comprising metal tracks that are electrically connected to the through-vias, the metal tracks having lateral ends extending into each spacing region; d) forming metal pillars on the lateral ends of the metal tracks; e) moulding a material on the redistribution layer, the material comprising: - first segments, facing the first layers of the electronic chips, - second segments, which are separate from the first segments, and which extend in the spacing regions around the metal pillars; the first and second segments (50, 51) of the material being coplanar; the material possessing a formation temperature; f) applying a heat treatment at the formation temperature of the material, the first and second segments (50, 51) of the material being mechanically attached to the first layers and to the carrier substrate, respectively, the formed material possessing a second thickness, and a second coefficient of thermal expansion strictly higher than the first coefficient of thermal expansion; the ratio between the first and second coefficients of thermal expansion, the ratio between the first and second thicknesses and the formation temperature being adapted so that, at the end of step f), the stack of each electronic chip is curved with a preset convex shape, which is oriented toward the matrix-array of pixels, at a given corresponding operating temperature of the electronic chip; the second segments of the material formed around the metal pillars remaining coplanar at the end of step f). a) providing the set of electronic chips, said chips having been diced beforehand and each comprising a stack comprising: - a matrix-array of pixels, - an interconnect layer, electrically connected to the matrix-array of pixels, - a first layer, comprising through-vias that are electrically connected to the interconnect layer; the stack possessing a first thickness and a first coefficient of thermal expansion; - a matrix-array of pixels, - an interconnect layer, electrically connected to the matrix-array of pixels, - a first layer, comprising through-vias that are electrically connected to the interconnect layer; the stack possessing a first thickness and a first coefficient of thermal expansion; b) joining the set of diced electronic chips to a carrier substrate, via the side opposite the first layers, so as to leave a spacing region between adjacent electronic chips; c) forming a redistribution layer comprising metal tracks that are electrically connected to the through-vias, the metal tracks having lateral ends extending into each spacing region; d) forming metal pillars on the lateral ends of the metal tracks; e) moulding a material on the redistribution layer, the material comprising: - first segments, facing the first layers of the electronic chips, - second segments, which are separate from the first segments, and which extend in the spacing regions around the metal pillars; the first and second segments (50, 51) of the material being coplanar; the material possessing a formation temperature; - first segments, facing the first layers of the electronic chips, - second segments, which are separate from the first segments, and which extend in the spacing regions around the metal pillars; the first and second segments (50, 51) of the material being coplanar; the material possessing a formation temperature; f) applying a heat treatment at the formation temperature of the material, the first and second segments (50, 51) of the material being mechanically attached to the first layers and to the carrier substrate, respectively, the formed material possessing a second thickness, and a second coefficient of thermal expansion strictly higher than the first coefficient of thermal expansion; the ratio between the first and second coefficients of thermal expansion, the ratio between the first and second thicknesses and the formation temperature being adapted so that, at the end of step f), the stack of each electronic chip is curved with a preset convex shape, which is oriented toward the matrix-array of pixels, at a given corresponding operating temperature of the electronic chip; the second segments of the material formed around the metal pillars remaining coplanar at the end of step f).