A processor comprising: a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; a destination register to store a third plurality and a fourth plurality of packed data elements, each of the third and fourth plurality of packed data elements to be encoded with fewer bits than each of the first and second plurality of packed data elements; characterized in that the processor further comprises: a decoder to decode a instruction to generate a decoded instruction, wherein the instruction is a two-source down-convert and interleave instruction; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: down-conversion circuitry to down-convert each of the first plurality of packed data elements to generate one of the third plurality of packed data elements and to down-convert each of the second plurality of packed data elements to generate one of the fourth plurality of packed data elements, wherein each data element in the first and second plurality of packed data elements comprises N bits and wherein each data element in the third and fourth plurality of packed data elements comprises N/2 bits; interleave circuitry to interleave the third plurality of packed data elements with the fourth plurality of packed data elements within the destination register. a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; a destination register to store a third plurality and a fourth plurality of packed data elements, each of the third and fourth plurality of packed data elements to be encoded with fewer bits than each of the first and second plurality of packed data elements; characterized in that the processor further comprises: a decoder to decode a instruction to generate a decoded instruction, wherein the instruction is a two-source down-convert and interleave instruction; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: down-conversion circuitry to down-convert each of the first plurality of packed data elements to generate one of the third plurality of packed data elements and to down-convert each of the second plurality of packed data elements to generate one of the fourth plurality of packed data elements, wherein each data element in the first and second plurality of packed data elements comprises N bits and wherein each data element in the third and fourth plurality of packed data elements comprises N/2 bits; interleave circuitry to interleave the third plurality of packed data elements with the fourth plurality of packed data elements within the destination register. a decoder to decode a instruction to generate a decoded instruction, wherein the instruction is a two-source down-convert and interleave instruction; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: down-conversion circuitry to down-convert each of the first plurality of packed data elements to generate one of the third plurality of packed data elements and to down-convert each of the second plurality of packed data elements to generate one of the fourth plurality of packed data elements, wherein each data element in the first and second plurality of packed data elements comprises N bits and wherein each data element in the third and fourth plurality of packed data elements comprises N/2 bits; interleave circuitry to interleave the third plurality of packed data elements with the fourth plurality of packed data elements within the destination register.