An imaging device, comprising: a first chip including: a first semiconductor substrate including a plurality of pixel regions arranged in a matrix and that convert incident light into electric charge; and a first insulating layer including a first multilayer wiring electrically connected to the plurality of pixel regions, wherein the first multilayer wiring includes a plurality of vertical signal lines to output respective pixel signals based on the electric charge, and at least one first wiring; and a second chip including: a second semiconductor substrate including a logic circuit to process the pixel signals; and a second insulating layer including a second multilayer wiring electrically connected to the logic circuit, wherein the second multilayer wiring includes at least one second wiring, wherein the first chip and the second chip are bonded to one another via at least the at least one first wiring and the at least one second wiring, wherein, in a plan view, the at least one first wiring and the at least one second wiring overlap with the plurality of vertical signal lines, characterised in that the plurality of vertical signal lines extend in a first direction and are arranged in the first multilayer wiring at a first regular interval in a second direction perpendicular to the first direction, and wherein the at least one first wiring is a plurality of first wirings that include first portions extending in the first direction and arranged in the first multilayer wiring at a second regular interval in the second direction, and wherein the first regular interval corresponds to a pitch between two of the plurality of pixel regions, and the second regular interval corresponds to half of the pitch. a first semiconductor substrate including a plurality of pixel regions arranged in a matrix and that convert incident light into electric charge; and a first insulating layer including a first multilayer wiring electrically connected to the plurality of pixel regions, wherein the first multilayer wiring includes a plurality of vertical signal lines to output respective pixel signals based on the electric charge, and at least one first wiring; and a second chip including: a second semiconductor substrate including a logic circuit to process the pixel signals; and a second insulating layer including a second multilayer wiring electrically connected to the logic circuit, wherein the second multilayer wiring includes at least one second wiring, wherein the first chip and the second chip are bonded to one another via at least the at least one first wiring and the at least one second wiring, wherein, in a plan view, the at least one first wiring and the at least one second wiring overlap with the plurality of vertical signal lines, characterised in that the plurality of vertical signal lines extend in a first direction and are arranged in the first multilayer wiring at a first regular interval in a second direction perpendicular to the first direction, and wherein the at least one first wiring is a plurality of first wirings that include first portions extending in the first direction and arranged in the first multilayer wiring at a second regular interval in the second direction, and a second semiconductor substrate including a logic circuit to process the pixel signals; and a second insulating layer including a second multilayer wiring electrically connected to the logic circuit, wherein the second multilayer wiring includes at least one second wiring, wherein the first chip and the second chip are bonded to one another via at least the at least one first wiring and the at least one second wiring, wherein, in a plan view, the at least one first wiring and the at least one second wiring overlap with the plurality of vertical signal lines, characterised in that the plurality of vertical signal lines extend in a first direction and are arranged in the first multilayer wiring at a first regular interval in a second direction perpendicular to the first direction, and wherein the at least one first wiring is a plurality of first wirings that include first portions extending in the first direction and arranged in the first multilayer wiring at a second regular interval in the second direction, and