A reference circuit for generating a reference voltage for reading data from one memory cell among a plurality of memory cells. the reference circuit comprising: a first reference circuit including a plurality of reference voltage setting circuits, each of which includes: a plurality of current load circuits (30, 31,... 3n) each connected to a reference element (9-r) via one sub reference line (50... 5n) corresponding thereto among a plurality of sub reference lines, and a current-voltage conversion circuit (110-r) for converting a current flowing through one sub reference line among the plurality of sub reference lines into a reference voltage representing a potential of the one sub reference line, characterized in that each of the plurality of current load circuits includes a PMOS transistor (70r0-7nrn) and the reference voltage which is output from one reference voltage setting circuit among the plurality of reference voltage setting circuits controls the current supply capability of at least one of the plurality of current load circuits included in another reference voltage setting circuit among the plurality of reference voltage setting circuits by current minor connecting a PMOS transistor of one current load circuit among the plurality of current load circuits included in the one reference voltage setting circuit with the PMOS transistor of the at least one of the plurality of current load circuits among the plurality of current load circuits included in the another reference voltage setting circuit. a first reference circuit including a plurality of reference voltage setting circuits, each of which includes: a plurality of current load circuits (30, 31,... 3n) each connected to a reference element (9-r) via one sub reference line (50... 5n) corresponding thereto among a plurality of sub reference lines, and a current-voltage conversion circuit (110-r) for converting a current flowing through one sub reference line among the plurality of sub reference lines into a reference voltage representing a potential of the one sub reference line, characterized in that each of the plurality of current load circuits includes a PMOS transistor (70r0-7nrn) and the reference voltage which is output from one reference voltage setting circuit among the plurality of reference voltage setting circuits controls the current supply capability of at least one of the plurality of current load circuits included in another reference voltage setting circuit among the plurality of reference voltage setting circuits by current minor connecting a PMOS transistor of one current load circuit among the plurality of current load circuits included in the one reference voltage setting circuit with the PMOS transistor of the at least one of the plurality of current load circuits among the plurality of current load circuits included in the another reference voltage setting circuit. a plurality of current load circuits (30, 31,... 3n) each connected to a reference element (9-r) via one sub reference line (50... 5n) corresponding thereto among a plurality of sub reference lines, and a current-voltage conversion circuit (110-r) for converting a current flowing through one sub reference line among the plurality of sub reference lines into a reference voltage representing a potential of the one sub reference line, characterized in that each of the plurality of current load circuits includes a PMOS transistor (70r0-7nrn) and the reference voltage which is output from one reference voltage setting circuit among the plurality of reference voltage setting circuits controls the current supply capability of at least one of the plurality of current load circuits included in another reference voltage setting circuit among the plurality of reference voltage setting circuits by current minor connecting a PMOS transistor of one current load circuit among the plurality of current load circuits included in the one reference voltage setting circuit with the PMOS transistor of the at least one of the plurality of current load circuits among the plurality of current load circuits included in the another reference voltage setting circuit.