A circuit to generate an output current that is substantially insensitive to variations in a voltage supply, the circuit comprising: a current mirror including a first set of transistors (122, 132) and a second set of transistors (124, 134), each transistor comprising either a gate, a drain configured to function as an input and a source configured to function as an output, or a base, an emitter configured to function as an input and a collector configured to function as an output, wherein at least one of the transistors in the first set of transistors (122, 132) and at least one of the transistors in the second set of transistors (124, 134) is in a cascode arrangement; a first operational amplifier having an output coupled to each of the gates or bases of the first set of transistors (122, 132) and including a first input configured to receive a first bias voltage determined by a reference voltage circuit that sets a second bias voltage to one of a plurality of selectable voltage levels within a range of voltages; a current source coupled to the output of the first transistor of the second set of transistors (124, 134); and a second operational amplifier having an output coupled to each of the gates or bases of the second set of transistors (124, 134) and including a first input configured to receive the second bias voltage determined by the reference voltage circuit; wherein a first transistor of the first set of transistors (122, 132) has its input coupled to the voltage supply and its output coupled to the input of a first transistor of the second set of transistors (124, 134), wherein a second transistor of the first set of transistors (122, 132) has its input coupled to the voltage supply and its output coupled to the input of a second transistor of the second set of transistors (124, 134), and wherein the second transistor of the second set of transistors is configured to generate an output that drives the output current, the output current being suitable for being provided to a voltage domain that has a voltage supply limited by the second bias voltage, wherein the output of the first transistor in the second set of transistors (124, 134) is coupled to a second input to the first operational amplifier to define a first feedback loop, and wherein the output of the first transistor in the first set of transistors (122, 132) is coupled to a second input to the second operational amplifier to define a second feedback loop. a current mirror including a first set of transistors (122, 132) and a second set of transistors (124, 134), each transistor comprising either a gate, a drain configured to function as an input and a source configured to function as an output, or a base, an emitter configured to function as an input and a collector configured to function as an output, wherein at least one of the transistors in the first set of transistors (122, 132) and at least one of the transistors in the second set of transistors (124, 134) is in a cascode arrangement; a first operational amplifier having an output coupled to each of the gates or bases of the first set of transistors (122, 132) and including a first input configured to receive a first bias voltage determined by a reference voltage circuit that sets a second bias voltage to one of a plurality of selectable voltage levels within a range of voltages; a current source coupled to the output of the first transistor of the second set of transistors (124, 134); and a second operational amplifier having an output coupled to each of the gates or bases of the second set of transistors (124, 134) and including a first input configured to receive the second bias voltage determined by the reference voltage circuit; wherein a first transistor of the first set of transistors (122, 132) has its input coupled to the voltage supply and its output coupled to the input of a first transistor of the second set of transistors (124, 134), wherein a second transistor of the first set of transistors (122, 132) has its input coupled to the voltage supply and its output coupled to the input of a second transistor of the second set of transistors (124, 134), and wherein the second transistor of the second set of transistors is configured to generate an output that drives the output current, the output current being suitable for being provided to a voltage domain that has a voltage supply limited by the second bias voltage, wherein the output of the first transistor in the second set of transistors (124, 134) is coupled to a second input to the first operational amplifier to define a first feedback loop, and wherein the output of the first transistor in the first set of transistors (122, 132) is coupled to a second input to the second operational amplifier to define a second feedback loop.