A power multiplexor (100, 400) comprising: a first branch including a first transistor coupled in series with a second transistor between a first power supply (VDD_AUX) and a power output, wherein a source of the first transistor is connected to the first power supply, and wherein a drain of the second transistor is connected to the power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply (VDD_DOM) and the power output, wherein a source of the third transistor is connected to the second power supply (VDD_DOM), and wherein a drain of the fourth transistor is connected to the power output, and wherein the first power supply (VDD_AUX) is operable to output a first voltage level, and wherein the second power supply (VDD_DOM) is operable to output a second voltage level that is higher than the first voltage level; a controller (130, 430) configured to selectively assert and de-assert first and second control signals (En_1, En_2) to the first branch and the second branch, respectively, wherein the first and second control signals (En_1, En_2), when asserted, are configured to have a voltage level corresponding to that of the first power supply (VDD_AUX); characterized in that: the first control signal (En_l) is directly connected to the gate of the first transistor and connected to the gate of the second transistor via a first voltage level shifter; the second control signal (En_2) is directly connected to the gate of the fourth transistor and connected to the gate of the third transistor via a second voltage level shifter; the first voltage level shifter is configured to increase the voltage of the first control signal (En_l) to a voltage level corresponding to that of the second power supply (VDD_DOM), when the first control signal (En_l) is asserted; and the second voltage level shifter is configured to increase the voltage of the second control signal (En_2) to a voltage level corresponding to that of the second power supply (VDD_DOM), when the second control signal (En_2) is asserted. a first branch including a first transistor coupled in series with a second transistor between a first power supply (VDD_AUX) and a power output, wherein a source of the first transistor is connected to the first power supply, and wherein a drain of the second transistor is connected to the power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply (VDD_DOM) and the power output, wherein a source of the third transistor is connected to the second power supply (VDD_DOM), and wherein a drain of the fourth transistor is connected to the power output, and wherein the first power supply (VDD_AUX) is operable to output a first voltage level, and wherein the second power supply (VDD_DOM) is operable to output a second voltage level that is higher than the first voltage level; a controller (130, 430) configured to selectively assert and de-assert first and second control signals (En_1, En_2) to the first branch and the second branch, respectively, wherein the first and second control signals (En_1, En_2), when asserted, are configured to have a voltage level corresponding to that of the first power supply (VDD_AUX); characterized in that: the first control signal (En_l) is directly connected to the gate of the first transistor and connected to the gate of the second transistor via a first voltage level shifter; the second control signal (En_2) is directly connected to the gate of the fourth transistor and connected to the gate of the third transistor via a second voltage level shifter; the first voltage level shifter is configured to increase the voltage of the first control signal (En_l) to a voltage level corresponding to that of the second power supply (VDD_DOM), when the first control signal (En_l) is asserted; and the second voltage level shifter is configured to increase the voltage of the second control signal (En_2) to a voltage level corresponding to that of the second power supply (VDD_DOM), when the second control signal (En_2) is asserted. the first control signal (En_l) is directly connected to the gate of the first transistor and connected to the gate of the second transistor via a first voltage level shifter; the second control signal (En_2) is directly connected to the gate of the fourth transistor and connected to the gate of the third transistor via a second voltage level shifter; the first voltage level shifter is configured to increase the voltage of the first control signal (En_l) to a voltage level corresponding to that of the second power supply (VDD_DOM), when the first control signal (En_l) is asserted; and the second voltage level shifter is configured to increase the voltage of the second control signal (En_2) to a voltage level corresponding to that of the second power supply (VDD_DOM), when the second control signal (En_2) is asserted.