An apparatus comprising: a fused compute engine comprising a high precision SIMD component which operates at a high speed, and a low precision SIMD component which operates at a low speed; and logic, at least partially including hardware logic, characterized to: receive instructions in the fused compute engine with highprecision and low precision instruction sets; by an application programming interface select, based on compute requirements for a particular workload or thread, at least one of the high precision instruction set for the high precision SIMD component or the low precision instruction set for the low precision SIMD component to execute the instructions; and power-gate or clock-gate the at least one of the high precision SIMD component for the low precision instruction set or the low precision SIMD component for the high precision instruction set to execute the instructions, wherein if the compute requirements indicate that the particular workload or thread requires the high precision SIMD component, the high precision SIMD component is selected and the low precision SIMD component is clock gated or power gated, and if the compute requirements indicate that the particular workload or thread requires the low precision SIMD component, then the low precision hardware SIMD component is selected and the high precision SIMD component is clock gated or power gated. a fused compute engine comprising a high precision SIMD component which operates at a high speed, and a low precision SIMD component which operates at a low speed; and logic, at least partially including hardware logic, characterized to: receive instructions in the fused compute engine with highprecision and low precision instruction sets; by an application programming interface select, based on compute requirements for a particular workload or thread, at least one of the high precision instruction set for the high precision SIMD component or the low precision instruction set for the low precision SIMD component to execute the instructions; and power-gate or clock-gate the at least one of the high precision SIMD component for the low precision instruction set or the low precision SIMD component for the high precision instruction set to execute the instructions, receive instructions in the fused compute engine with highprecision and low precision instruction sets; by an application programming interface select, based on compute requirements for a particular workload or thread, at least one of the high precision instruction set for the high precision SIMD component or the low precision instruction set for the low precision SIMD component to execute the instructions; and power-gate or clock-gate the at least one of the high precision SIMD component for the low precision instruction set or the low precision SIMD component for the high precision instruction set to execute the instructions, wherein if the compute requirements indicate that the particular workload or thread requires the high precision SIMD component, the high precision SIMD component is selected and the low precision SIMD component is clock gated or power gated, and if the compute requirements indicate that the particular workload or thread requires the low precision SIMD component, then the low precision hardware SIMD component is selected and the high precision SIMD component is clock gated or power gated.