A display device comprising: a display portion comprising a plurality of pixels arranged in matrix; a line buffer circuit for holding a video signal required to display one row; a source driver circuit for sampling the video signal, and for outputting the video signal to a row of pixels of the plurality of the pixels; a timing controller; and a test circuit for testing the video signal held in the line buffer circuit, wherein the timing controller is configured to generate signals required for driving the display device based on a reference clock signal and a synchronization signal input to the timing controller, the signals including a source driver start pulse and a write erase selection signal (W/E); wherein when the video signal is detected to be a specific video signal, the test circuit outputs: a control signal for stopping the input of the source driver start pulse to the display portion so that the source driver circuit stops sampling the video signal; and a control signal for stopping the input of the write erase selection signal (W/E) to the display portion, and wherein when the specific video signal is a video signal by which all the pixels of the one row display black, the level of the write erase selection signal is fixed at a level such that the video signal is not outputted to a source signal line and an erasing signal is continuously inputted thereto; or wherein when the specific video signal is a video signal by which all the pixels of the one row display white, the level of the write erase selection signal is fixed at a level such that the erasing signal is not inputted to the source signal line. a display portion comprising a plurality of pixels arranged in matrix; a line buffer circuit for holding a video signal required to display one row; a source driver circuit for sampling the video signal, and for outputting the video signal to a row of pixels of the plurality of the pixels; a timing controller; and a test circuit for testing the video signal held in the line buffer circuit, wherein the timing controller is configured to generate signals required for driving the display device based on a reference clock signal and a synchronization signal input to the timing controller, the signals including a source driver start pulse and a write erase selection signal (W/E); wherein when the video signal is detected to be a specific video signal, the test circuit outputs: a control signal for stopping the input of the source driver start pulse to the display portion so that the source driver circuit stops sampling the video signal; and a control signal for stopping the input of the write erase selection signal (W/E) to the display portion, and a control signal for stopping the input of the source driver start pulse to the display portion so that the source driver circuit stops sampling the video signal; and a control signal for stopping the input of the write erase selection signal (W/E) to the display portion, and wherein when the specific video signal is a video signal by which all the pixels of the one row display black, the level of the write erase selection signal is fixed at a level such that the video signal is not outputted to a source signal line and an erasing signal is continuously inputted thereto; or wherein when the specific video signal is a video signal by which all the pixels of the one row display white, the level of the write erase selection signal is fixed at a level such that the erasing signal is not inputted to the source signal line.