A multi-channel switchmode audio amplifier, comprising: a number of amplifier channels, each including a modulator (72b-78b), a feedback loop (72a-78a, 72e-78e), a switching power amplifier stage (72c-78c) including a number of switching transistors (110a, 110b, 112a, 112b) that are configured to open and close to direct current through a speaker, and an error amplifier that has one input that is configured to receive an input signal to be amplified and another input that is configured to receive a sample of an output signal of a respective amplifier channel via the feedback loop to control the signal that is applied to the input of the modulator of the respective amplifier channel; and a programmed processor that is configured to connect two or more channels in parallel to drive the speaker by connecting an output of a modulator (72b-78b) from a master channel out of the number of amplifier channels to an input of the power amplifier stage (72c-78c) for one or more slave channels out of the number of amplifier channels and by disconnecting the modulator (72b-78b) for the one or more slave channels from the switching power amplifier stages (72c-78c) of the one or more slave channels, thereby disconnecting the feedback loop (72a-78a, 72e-78e) of each slave channel such that current sharing between the master channel and the one or more slave channels is controlled by limiting timing differences in switching of the switching transistors (110a, 110b, 112a, 112b) in the power amplifier stages (72c-78c) of the parallely connected master and slave channels to within 100 nano seconds; and wherein traces on a circuit board are laid out to minimize differences in signal delay between the output of the modulator (72b-78b) for the master channel and the power amplifier stages (72c-78c) of the one or more slave channels. a number of amplifier channels, each including a modulator (72b-78b), a feedback loop (72a-78a, 72e-78e), a switching power amplifier stage (72c-78c) including a number of switching transistors (110a, 110b, 112a, 112b) that are configured to open and close to direct current through a speaker, and an error amplifier that has one input that is configured to receive an input signal to be amplified and another input that is configured to receive a sample of an output signal of a respective amplifier channel via the feedback loop to control the signal that is applied to the input of the modulator of the respective amplifier channel; and a programmed processor that is configured to connect two or more channels in parallel to drive the speaker by connecting an output of a modulator (72b-78b) from a master channel out of the number of amplifier channels to an input of the power amplifier stage (72c-78c) for one or more slave channels out of the number of amplifier channels and by disconnecting the modulator (72b-78b) for the one or more slave channels from the switching power amplifier stages (72c-78c) of the one or more slave channels, thereby disconnecting the feedback loop (72a-78a, 72e-78e) of each slave channel such that current sharing between the master channel and the one or more slave channels is controlled by limiting timing differences in switching of the switching transistors (110a, 110b, 112a, 112b) in the power amplifier stages (72c-78c) of the parallely connected master and slave channels to within 100 nano seconds; and wherein traces on a circuit board are laid out to minimize differences in signal delay between the output of the modulator (72b-78b) for the master channel and the power amplifier stages (72c-78c) of the one or more slave channels.