A method of forming a silicon carbide power device, wherein the silicon carbide power device comprises a Metal Oxide Semiconductor Field Effect Transistor, the method comprising: forming an n - silicon carbide layer on an n + or n - silicon carbide substrate; forming a p-type silicon carbide well region on the n - silicon carbide layer; forming a buried region of p + silicon carbide in the p-type silicon carbide well region; forming an n + region of silicon carbide on the buried region of p + silicon carbide, the n + region providing a source region of the device, an initial channel region of the power device being adjacent the buried region of p + and n + region of silicon carbide; forming, by implanting, an n-type region of silicon carbide in the p-type silicon carbide well region using a patterned mask, the initial channel region comprising the n-type region of silicon carbide and a portion of the p-type silicon carbide region between the p + region of silicon carbide and the n-type region; forming an n - region on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region; removing a portion of the n - region from on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region so that a portion of the n - region remains on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region to provide a reduction in a surface roughness of a final channel region; and removing a portion of the remaining n - region such that the remaining n - region is removed from the n + region; wherein the final channel region includes the n-type region of silicon carbide, the portion of the p-type silicon carbide well region between the p + region of silicon carbide and the n-type region and the portion of the n - region that remains on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region. forming an n - silicon carbide layer on an n + or n - silicon carbide substrate; forming a p-type silicon carbide well region on the n - silicon carbide layer; forming a buried region of p + silicon carbide in the p-type silicon carbide well region; forming an n + region of silicon carbide on the buried region of p + silicon carbide, the n + region providing a source region of the device, an initial channel region of the power device being adjacent the buried region of p + and n + region of silicon carbide; forming, by implanting, an n-type region of silicon carbide in the p-type silicon carbide well region using a patterned mask, the initial channel region comprising the n-type region of silicon carbide and a portion of the p-type silicon carbide region between the p + region of silicon carbide and the n-type region; forming an n - region on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region; removing a portion of the n - region from on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region so that a portion of the n - region remains on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region to provide a reduction in a surface roughness of a final channel region; and removing a portion of the remaining n - region such that the remaining n - region is removed from the n + region; wherein the final channel region includes the n-type region of silicon carbide, the portion of the p-type silicon carbide well region between the p + region of silicon carbide and the n-type region and the portion of the n - region that remains on the n-type region of silicon carbide and the p-type silicon carbide region of the initial channel region.