A gain control circuit (100; 200; 300) for a variable gain amplifier, VGA, (10; 20), which comprises a first transistor stack (Q1, Q2) to which at least one input signal (V in, V inb) that is to be amplified by the VGA (10; 20) is to be applied and a second transistor stack (Q3-Q6) to which differential gain control voltages (V c, V cb) for controlling the gain of the VGA (10; 20) are to be applied, the gain control circuit comprising: - a gain-control differential pair circuit, which comprises two branches, a first one of the two branches comprising a first one of two transistors and the other one of the two branches comprising the other one of the two transistors, the two transistors (M1, M2) forming a differential pair, for generating the differential gain control voltages (V c, V cb) in dependence of a gain control signal applied to the first one of the two transistors, wherein a fixed reference signal is applied to the other one of the two transistors, wherein the gain-control differential pair circuit further comprises two load resistances (R D) for converting the gain control signal and the fixed reference signal into the differential gain control voltages (V c, V cb), wherein further a source degeneration resistor (Rs) for increasing the range in which the gain control signal can change the gain of the gain-control differential pair circuit is provided between the two branches of the gain-control differential pair circuit, and characterised by the gain control circuit further comprising: - a common-mode adjustment circuit (110; 210; 310) for adjusting the common mode of the differential gain control voltages (V c, V cb) in dependence of a desired amplification of the VGA (10; 20), wherein the common-mode adjustment circuit (110; 210; 310) comprises a double current mirror circuit comprising two further transistors (M3, M4), each of which is connected to a different branch of the two branches of the gain-control differential pair circuit, for providing a bias current (I bias) equally to each of the two branches of the gain-control differential pair circuit, and wherein the common-mode adjustment circuit (110; 210; 310) comprises a current source for providing a current (I 2) and a control circuit (120; 220; 320) for providing the current (I 2) to generate a part of the bias current (I bias) in dependence of a desired amplification of the VGA (10; 20). - a gain-control differential pair circuit, which comprises two branches, a first one of the two branches comprising a first one of two transistors and the other one of the two branches comprising the other one of the two transistors, the two transistors (M1, M2) forming a differential pair, for generating the differential gain control voltages (V c, V cb) in dependence of a gain control signal applied to the first one of the two transistors, wherein a fixed reference signal is applied to the other one of the two transistors, wherein the gain-control differential pair circuit further comprises two load resistances (R D) for converting the gain control signal and the fixed reference signal into the differential gain control voltages (V c, V cb), wherein further a source degeneration resistor (Rs) for increasing the range in which the gain control signal can change the gain of the gain-control differential pair circuit is provided between the two branches of the gain-control differential pair circuit, and characterised by the gain control circuit further comprising: - a common-mode adjustment circuit (110; 210; 310) for adjusting the common mode of the differential gain control voltages (V c, V cb) in dependence of a desired amplification of the VGA (10; 20), wherein the common-mode adjustment circuit (110; 210; 310) comprises a double current mirror circuit comprising two further transistors (M3, M4), each of which is connected to a different branch of the two branches of the gain-control differential pair circuit, for providing a bias current (I bias) equally to each of the two branches of the gain-control differential pair circuit, and wherein the common-mode adjustment circuit (110; 210; 310) comprises a current source for providing a current (I 2) and a control circuit (120; 220; 320) for providing the current (I 2) to generate a part of the bias current (I bias) in dependence of a desired amplification of the VGA (10; 20). - a common-mode adjustment circuit (110; 210; 310) for adjusting the common mode of the differential gain control voltages (V c, V cb) in dependence of a desired amplification of the VGA (10; 20),