An apparatus, the apparatus comprising: a memory cell array (110, 690) of memory cells configured to output respective current sums of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells; sampling circuits, comprising respective capacitors connected to each of the column lines, each configured to be charged by a sampling voltage of a corresponding current sum of the column lines; and a processing circuit (130-140, 600) comprising: a control signal generator (630, 910) configured to generate a trigger pulse at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of a capacitor of the respective capacitors, and a counting pulse in synchronism with the generation of the trigger pulse; a comparator (130, 640, 920, 1021-1023), connected to each of the column lines, configured to compare a reference voltage and a currently charged voltage in the capacitor in response to the trigger pulse, the comparator being configured to receive the trigger pulse as a start signal of the comparison operation, and output a stop signal when the currently charged voltage reaches the reference voltage; and a time-digital converter, TDC, (140, 650, 930, 1030) configured to determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage, the TDC being configured to output a counting value of the counting pulse as a digital value when the stop signal is received, the counting pulse being applied in synchronism with the trigger pulse at a time point when the stop signal is received. a memory cell array (110, 690) of memory cells configured to output respective current sums of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells; sampling circuits, comprising respective capacitors connected to each of the column lines, each configured to be charged by a sampling voltage of a corresponding current sum of the column lines; and a processing circuit (130-140, 600) comprising: a control signal generator (630, 910) configured to generate a trigger pulse at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of a capacitor of the respective capacitors, and a counting pulse in synchronism with the generation of the trigger pulse; a comparator (130, 640, 920, 1021-1023), connected to each of the column lines, configured to compare a reference voltage and a currently charged voltage in the capacitor in response to the trigger pulse, the comparator being configured to receive the trigger pulse as a start signal of the comparison operation, and output a stop signal when the currently charged voltage reaches the reference voltage; and a control signal generator (630, 910) configured to generate a trigger pulse at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of a capacitor of the respective capacitors, and a counting pulse in synchronism with the generation of the trigger pulse; a comparator (130, 640, 920, 1021-1023), connected to each of the column lines, configured to compare a reference voltage and a currently charged voltage in the capacitor in response to the trigger pulse, the comparator being configured to receive the trigger pulse as a start signal of the comparison operation, and output a stop signal when the currently charged voltage reaches the reference voltage; and a time-digital converter, TDC, (140, 650, 930, 1030) configured to determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage, the TDC being configured to output a counting value of the counting pulse as a digital value when the stop signal is received, the counting pulse being applied in synchronism with the trigger pulse at a time point when the stop signal is received.