A semiconductor device, comprising: a plurality of semiconductor fins (102, 202) disposed above a semiconductor substrate, each semiconductor fin having a doped sub-fin portion (102A, 152A, 202A, 214A, 305) below a protruding portion (102B, 152B, 202B, 214B, 304), the sub-fin portion (102A, 152A, 202A, 214A, 305) narrower than the protruding portion (102B, 152B, 202B, 214B, 304); a solid state dopant source layer (216, 220, 390) and a capping layer (122, 218, 222, 392) disposed above the semiconductor substrate, conformal with the sub-fin portion (202A, 214A, 305) but not the protruding portion (102B, 152B, 202B, 214B, 304) of each of the plurality of semiconductor fin, wherein the solid state dopant source layer (216, 220, 390) and the capping layer (122, 218, 222, 392) are patterned to be confined to the sub-fin portions (102A, 152A, 202A, 214A, 305) with a spacing between the capping layers (122, 218, 222, 392) of each sub-fin portion (202A, 214A, 305); an isolation layer disposed above the solid state dopant source layer (216, 220, 390) and on the capping layer (122, 218, 222, 392) and between the sub-fin portions (202A, 214A, 305) of the plurality of semiconductor fins (102, 202); a gate stack disposed above the isolation layer and conformal with the protruding portions (102B, 152B, 202B, 214B, 304) of each of the plurality of semiconductor fins (102, 202), the gate stack comprising a gate dielectric layer and gate electrode; and source and drain regions disposed in the protruding portions (102B, 152B, 202B, 214B, 304) of each of the plurality of semiconductor fins (102, 202), on either side of the gate stack. a plurality of semiconductor fins (102, 202) disposed above a semiconductor substrate, each semiconductor fin having a doped sub-fin portion (102A, 152A, 202A, 214A, 305) below a protruding portion (102B, 152B, 202B, 214B, 304), the sub-fin portion (102A, 152A, 202A, 214A, 305) narrower than the protruding portion (102B, 152B, 202B, 214B, 304); a solid state dopant source layer (216, 220, 390) and a capping layer (122, 218, 222, 392) disposed above the semiconductor substrate, conformal with the sub-fin portion (202A, 214A, 305) but not the protruding portion (102B, 152B, 202B, 214B, 304) of each of the plurality of semiconductor fin, wherein the solid state dopant source layer (216, 220, 390) and the capping layer (122, 218, 222, 392) are patterned to be confined to the sub-fin portions (102A, 152A, 202A, 214A, 305) with a spacing between the capping layers (122, 218, 222, 392) of each sub-fin portion (202A, 214A, 305); an isolation layer disposed above the solid state dopant source layer (216, 220, 390) and on the capping layer (122, 218, 222, 392) and between the sub-fin portions (202A, 214A, 305) of the plurality of semiconductor fins (102, 202); a gate stack disposed above the isolation layer and conformal with the protruding portions (102B, 152B, 202B, 214B, 304) of each of the plurality of semiconductor fins (102, 202), the gate stack comprising a gate dielectric layer and gate electrode; and source and drain regions disposed in the protruding portions (102B, 152B, 202B, 214B, 304) of each of the plurality of semiconductor fins (102, 202), on either side of the gate stack.