A method for manufacturing a hybrid MOSFET device comprising a first MOSFET having a first channel material and a second MOSFET having a second channel material, comprising the following steps: providing a first substrate comprising a group IV bulk semiconductor material suitable to function as the first channel material; providing a second substrate comprising a III-V layer covered by and in contact with an exposed insulator layer, wherein the III-V layer comprises a III-V compound suitable to function as the second channel material; direct substrate bonding of the first substrate with the second substrate, such that a III-V-on-insulator stack is provided on the first substrate, the III-V-on-insulator stack comprising the insulating layer overlying and in contact with the first substrate over a first region (I, I') and a second region and the III-V layer overlying and in contact with the insulator layer over the first region (I, I') and the second region; removing the III-V layer and the insulator layer in the first region (I, I'), selectively with respect to the second region, thereby exposing the bulk semiconductor material (107, 108) in the first region (I, I'); characterized in that the III-V-on-insulator stack has a thickness lower than 15 nm and in that the method comprises the following steps: forming a shallow trench isolation pattern (105, 105') in the first substrate before the III-V-on-insulator stack is provided thereon, to insulate the first region (I, I') from the second region; and forming a first gate stack (109, 109') of the first MOSFET directly on the exposed bulk semiconductor material in the first region (I, I') and forming a second gate stack (109") of the second MOSFET on the III-V layer in the second region, wherein the first and second gate stacks are formed simultaneously. providing a first substrate comprising a group IV bulk semiconductor material suitable to function as the first channel material; providing a second substrate comprising a III-V layer covered by and in contact with an exposed insulator layer, wherein the III-V layer comprises a III-V compound suitable to function as the second channel material; direct substrate bonding of the first substrate with the second substrate, such that a III-V-on-insulator stack is provided on the first substrate, the III-V-on-insulator stack comprising the insulating layer overlying and in contact with the first substrate over a first region (I, I') and a second region and the III-V layer overlying and in contact with the insulator layer over the first region (I, I') and the second region; removing the III-V layer and the insulator layer in the first region (I, I'), selectively with respect to the second region, thereby exposing the bulk semiconductor material (107, 108) in the first region (I, I'); characterized in that the III-V-on-insulator stack has a thickness lower than 15 nm and in that the method comprises the following steps: forming a shallow trench isolation pattern (105, 105') in the first substrate before the III-V-on-insulator stack is provided thereon, to insulate the first region (I, I') from the second region; and forming a first gate stack (109, 109') of the first MOSFET directly on the exposed bulk semiconductor material in the first region (I, I') and forming a second gate stack (109") of the second MOSFET on the III-V layer in the second region, wherein the first and second gate stacks are formed simultaneously. forming a shallow trench isolation pattern (105, 105') in the first substrate before the III-V-on-insulator stack is provided thereon, to insulate the first region (I, I') from the second region; and forming a first gate stack (109, 109') of the first MOSFET directly on the exposed bulk semiconductor material in the first region (I, I') and forming a second gate stack (109") of the second MOSFET on the III-V layer in the second region, wherein the first and second gate stacks are formed simultaneously.