A method of fabricating a semiconductor device, comprising the steps of: forming a first insulating film (21, 41) in a first region and a second region of a semiconductor substrate by performing thermal oxidation treatment; removing said first insulating film (21, 41) on said first region while leaving said first insulating film (21, 41) on said second region; forming a second insulating film (22b, 42b) in said first region and turning said first insulating film (21, 41) of said second region to a third insulating film (22a, 42a) having a film thickness larger than that of said second insulating film (22b, 42b) by performing thermal oxidation treatment; forming a silicon nitride film (23, 44) on said second insulating film (22b, 42b) and said third insulating film (22a, 42a); forming first trenches (24b, 45b) in said first region of said semiconductor substrate by etching said silicon nitride film (23, 44), said second insulating film (22b, 42b) and said first region of said semiconductor substrate and forming second trenches (24a, 45a) in said second region of said semiconductor substrate by etching said silicon nitride film (23, 44), said third insulating film (22a, 42a) and said second region of said semiconductor substrate; increasing a curvature of a top edge portion of said second trench (24a, 45a) to become larger than a curvature of a top edge portion of said first trench (24b, 45b) by oxidizing inner surfaces of said first (24b, 45b) and second (24a, 45a) trenches; filling said first (24b, 45b) and second (24a, 45a) trenches with an insulating material (26, 47); and forming a first element in said first region and a second element in said second region, wherein during operation of said semiconductor device a voltage applied to said second element is higher than a voltage applied to said first element, wherein said first element is a MOS transistor and said second element is a memory cell of a nonvolatile semiconductor memory. forming a first insulating film (21, 41) in a first region and a second region of a semiconductor substrate by performing thermal oxidation treatment; removing said first insulating film (21, 41) on said first region while leaving said first insulating film (21, 41) on said second region; forming a second insulating film (22b, 42b) in said first region and turning said first insulating film (21, 41) of said second region to a third insulating film (22a, 42a) having a film thickness larger than that of said second insulating film (22b, 42b) by performing thermal oxidation treatment; forming a silicon nitride film (23, 44) on said second insulating film (22b, 42b) and said third insulating film (22a, 42a); forming a second insulating film (22b, 42b) in said first region and turning said first insulating film (21, 41) of said second region to a third insulating film (22a, 42a) having a film thickness larger than that of said second insulating film (22b, 42b) by performing thermal oxidation treatment; forming a silicon nitride film (23, 44) on said second insulating film (22b, 42b) and said third insulating film (22a, 42a); forming first trenches (24b, 45b) in said first region of said semiconductor substrate by etching said silicon nitride film (23, 44), said second insulating film (22b, 42b) and said first region of said semiconductor substrate and forming second trenches (24a, 45a) in said second region of said semiconductor substrate by etching said silicon nitride film (23, 44), said third insulating film (22a, 42a) and said second region of said semiconductor substrate; increasing a curvature of a top edge portion of said second trench (24a, 45a) to become larger than a curvature of a top edge portion of said first trench (24b, 45b) by oxidizing inner surfaces of said first (24b, 45b) and second (24a, 45a) trenches; filling said first (24b, 45b) and second (24a, 45a) trenches with an insulating material (26, 47); and forming a first element in said first region and a second element in said second region, wherein during operation of said semiconductor device a voltage applied to said second element is higher than a voltage applied to said first element, wherein said first element is a MOS transistor and said second element is a memory cell of a nonvolatile semiconductor memory.