A radar system comprising: first direct digital synthesizer, DDS, circuitry; first phase-locked loop, PLL, circuitry configured to generate a first sinusoidal signal based on a first DDS signal generated by the first DDS circuitry, wherein the first PLL circuitry includes a first integer-N PLL, and wherein the first DDS circuitry directly drives a clock input to the first integer-N PLL; first band-pass filter, BPF, circuitry configured to generate a first band-filtered signal based on the first sinusoidal signal; transmitter circuitry (422, 424, 430) configured to generate a radar signal based on the first band-filtered signal; one or more antennas configured to transmit the radar signal and receive a return signal based on the radar signal; second DDS circuitry; second PLL circuitry configured to generate a second sinusoidal signal based on a second DDS signal generated by the second DDS circuitry, wherein the first PLL circuitry or the second PLL circuitry includes fixed-frequency PLL circuitry, wherein the second PLL circuitry includes a second integer-N PLL, and wherein the second DDS circuitry directly drives a clock input to the second integer-N PLL; second BPF circuitry configured to generate a second band-filtered signal based on the second sinusoidal signal; coupler circuitry configured to couple the first band-filtered signal to a switch; receiver circuitry configured to deliver the return signal to a first input of a mixer and configured to process the return signal; and said switch configured, in a first configuration, to deliver the first band-filtered signal to a second input of the mixer, and, in a second configuration, to deliver the second band-filtered signal to the second input of the mixer. first direct digital synthesizer, DDS, circuitry; first phase-locked loop, PLL, circuitry configured to generate a first sinusoidal signal based on a first DDS signal generated by the first DDS circuitry, wherein the first PLL circuitry includes a first integer-N PLL, and wherein the first DDS circuitry directly drives a clock input to the first integer-N PLL; first band-pass filter, BPF, circuitry configured to generate a first band-filtered signal based on the first sinusoidal signal; transmitter circuitry (422, 424, 430) configured to generate a radar signal based on the first band-filtered signal; one or more antennas configured to transmit the radar signal and receive a return signal based on the radar signal; second DDS circuitry; second PLL circuitry configured to generate a second sinusoidal signal based on a second DDS signal generated by the second DDS circuitry, wherein the first PLL circuitry or the second PLL circuitry includes fixed-frequency PLL circuitry, wherein the second PLL circuitry includes a second integer-N PLL, and wherein the second DDS circuitry directly drives a clock input to the second integer-N PLL; second BPF circuitry configured to generate a second band-filtered signal based on the second sinusoidal signal; coupler circuitry configured to couple the first band-filtered signal to a switch; receiver circuitry configured to deliver the return signal to a first input of a mixer and configured to process the return signal; and said switch configured, in a first configuration, to deliver the first band-filtered signal to a second input of the mixer, and, in a second configuration, to deliver the second band-filtered signal to the second input of the mixer.