A receiver comprising: a first Bit-Interleaved Coded Modulation, BICM, decoder configured to decode a first input signal which is generated at a transmitter by superimposing an upper layer signal of an upper layer and a lower layer signal of a lower layer, to generate a first output signal corresponding to the upper layer; a parity generator configured to generate one or more parity bits based on a result of the decoding of the first input signal; and a second BICM decoder configured to decode a second input signal which is generated based on the first input signal and the one or more parity bits to generate a second output signal corresponding to the lower layer; wherein the first BICM decoder comprises: a Bose-Chaudhuri-Hocquenghem, BCH, decoder, and a Low Density Parity Check, LDPC, decoder configured to decode the first input signal to generate information bits and parity bits based on a LDPC code, wherein the parity generator is configured to generate parity bits corresponding to the information bits using values of information part parity check, IPPC, expressions obtained based on a parity check matrix of the LDPC code, and wherein the parity generator is configured to, if an error is not in the information bits, generate the parity bits using the values of the IPPC expressions, and if the error is in the information bits, determine a location of a bit in which the error occurs among the information bits based on a result of BCH decoding of the information bits, flip a value of a IPPC expression corresponding to the bit in which the error occurs among the values of the IPPC expressions and generate the parity bits using the values of the IPPC expressions comprising the flipped value. a first Bit-Interleaved Coded Modulation, BICM, decoder configured to decode a first input signal which is generated at a transmitter by superimposing an upper layer signal of an upper layer and a lower layer signal of a lower layer, to generate a first output signal corresponding to the upper layer; a parity generator configured to generate one or more parity bits based on a result of the decoding of the first input signal; and a second BICM decoder configured to decode a second input signal which is generated based on the first input signal and the one or more parity bits to generate a second output signal corresponding to the lower layer; wherein the first BICM decoder comprises: a Bose-Chaudhuri-Hocquenghem, BCH, decoder, and a Low Density Parity Check, LDPC, decoder configured to decode the first input signal to generate information bits and parity bits based on a LDPC code, wherein the parity generator is configured to generate parity bits corresponding to the information bits using values of information part parity check, IPPC, expressions obtained based on a parity check matrix of the LDPC code, and wherein the parity generator is configured to, if an error is not in the information bits, generate the parity bits using the values of the IPPC expressions, and if the error is in the information bits, determine a location of a bit in which the error occurs among the information bits based on a result of BCH decoding of the information bits, flip a value of a IPPC expression corresponding to the bit in which the error occurs among the values of the IPPC expressions and generate the parity bits using the values of the IPPC expressions comprising the flipped value. a Bose-Chaudhuri-Hocquenghem, BCH, decoder, and a Low Density Parity Check, LDPC, decoder configured to decode the first input signal to generate information bits and parity bits based on a LDPC code, wherein the parity generator is configured to generate parity bits corresponding to the information bits using values of information part parity check, IPPC, expressions obtained based on a parity check matrix of the LDPC code, and wherein the parity generator is configured to, if an error is not in the information bits, generate the parity bits using the values of the IPPC expressions, and if the error is in the information bits, determine a location of a bit in which the error occurs among the information bits based on a result of BCH decoding of the information bits, flip a value of a IPPC expression corresponding to the bit in which the error occurs among the values of the IPPC expressions and generate the parity bits using the values of the IPPC expressions comprising the flipped value.