A processor comprising: copy engine hardware circuitry to facilitate copying surface data in memory and comprising: a plurality of copy front-end hardware circuitry (2910A, 2910B, 2910c) to generate a plurality of surface data sub-blocks from the surface data, wherein a number of the plurality of copy front-end hardware circuitry corresponds to a number of partitions configured for the processor, with each partition associated with a single copy front-end hardware circuitry of the plurality of copy front-end hardware circuitry; a plurality of copy back-end hardware circuitry (2930A, 2930B, 2930C) to operate in parallel to process the plurality of surface data sub-blocks to perform memory accesses, wherein subsets of the plurality of copy back-end hardware circuitry are each associated with the single copy front-end hardware circuitry associated with each partition; and a connectivity matrix hardware circuitry to communicably connect the plurality of copy front-end hardware circuitry to the plurality of copy back-end hardware circuitry, wherein each set of the single copy front-end hardware circuitry and one of the subsets of the copy back-end hardware circuitry that is assigned to the single copy front-end hardware circuitry is to form a copy engine building block of the copy engine hardware circuitry, and wherein responsive to one of the partitions being reconfigured, the copy engine building block corresponding to the one of the partitions being reconfigured is reset to an unassigned state by resetting the copy front-end hardware circuitry associated with the one of the partitions and draining to an idle state the subset of copy back-end hardware circuitry corresponding to the copy front-end hardware circuitry being reset. a plurality of copy front-end hardware circuitry (2910A, 2910B, 2910c) to generate a plurality of surface data sub-blocks from the surface data, wherein a number of the plurality of copy front-end hardware circuitry corresponds to a number of partitions configured for the processor, with each partition associated with a single copy front-end hardware circuitry of the plurality of copy front-end hardware circuitry; a plurality of copy back-end hardware circuitry (2930A, 2930B, 2930C) to operate in parallel to process the plurality of surface data sub-blocks to perform memory accesses, wherein subsets of the plurality of copy back-end hardware circuitry are each associated with the single copy front-end hardware circuitry associated with each partition; and a connectivity matrix hardware circuitry to communicably connect the plurality of copy front-end hardware circuitry to the plurality of copy back-end hardware circuitry, wherein each set of the single copy front-end hardware circuitry and one of the subsets of the copy back-end hardware circuitry that is assigned to the single copy front-end hardware circuitry is to form a copy engine building block of the copy engine hardware circuitry, and wherein responsive to one of the partitions being reconfigured, the copy engine building block corresponding to the one of the partitions being reconfigured is reset to an unassigned state by resetting the copy front-end hardware circuitry associated with the one of the partitions and draining to an idle state the subset of copy back-end hardware circuitry corresponding to the copy front-end hardware circuitry being reset.