A memory device comprising a sensing circuit (200, 600, 700, 800), a selected memory cell, and a reference memory cell, the sensing circuit comprising: a memory data read block (210, 610, 710, 810) for sensing the selected memory cell; a memory reference read block (220, 620, 720, 820) for sensing the reference memory cell; a differential amplifier block (230, 630, 730, 830) comprising a cross-coupled inverter pair, first capacitor (260, 660, 760, 860) comprising a first terminal and a second terminal, a second capacitor (270, 670, 770, 870) comprising a first terminal and a second terminal, a first NMOS transistor comprising a gate connected to the second terminal of the first capacitor and a drain connected to the cross-coupled inverter pair, a second NMOS transistor comprising a gate connected to the second terminal of the second capacitor and a drain connected to the cross-coupled inverter pair, a third NMOS transistor coupled to a source of the first NMOS transistor and a source of the second NMOS transistor and providing a bias voltage to the first NMOS transistor and the second NMOS transistor, a precharge circuit for charging the first terminal and second terminal of the first capacitor and the second terminal of the second capacitor prior to a sensing operation, and an output; wherein the first terminal of the first capacitor is connected to the memory data read block and the first terminal of the second capacitor is connected to the memory reference read block and the second terminal of the second capacitor is connected to the differential amplifier block; wherein during the sensing operation the output of the differential amplifier block indicates a value stored in the selected memory cell. a memory data read block (210, 610, 710, 810) for sensing the selected memory cell; a memory reference read block (220, 620, 720, 820) for sensing the reference memory cell; a differential amplifier block (230, 630, 730, 830) comprising a cross-coupled inverter pair, first capacitor (260, 660, 760, 860) comprising a first terminal and a second terminal, a second capacitor (270, 670, 770, 870) comprising a first terminal and a second terminal, a first NMOS transistor comprising a gate connected to the second terminal of the first capacitor and a drain connected to the cross-coupled inverter pair, a second NMOS transistor comprising a gate connected to the second terminal of the second capacitor and a drain connected to the cross-coupled inverter pair, a third NMOS transistor coupled to a source of the first NMOS transistor and a source of the second NMOS transistor and providing a bias voltage to the first NMOS transistor and the second NMOS transistor, a precharge circuit for charging the first terminal and second terminal of the first capacitor and the second terminal of the second capacitor prior to a sensing operation, and an output; wherein the first terminal of the first capacitor is connected to the memory data read block and the first terminal of the second capacitor is connected to the memory reference read block and the second terminal of the second capacitor is connected to the differential amplifier block; wherein during the sensing operation the output of the differential amplifier block indicates a value stored in the selected memory cell.