A gated synchronization voltage-controlled multi-phase clock oscillator (106, 200), comprising: a first delay cell comprising a first input terminal a second input terminal an output terminal and a complementary output terminal; a second delay cell comprising a first input terminal, an output terminal coupled to its first input terminal, a complementary output terminal, and a second input terminal coupled to the output terminal of the first delay cell; a third delay cell comprising a first input terminal coupled to the output terminal of the first delay cell, and a second input terminal coupled to the output terminal of the second delay cell, an output terminal, and a complementary output terminal coupled to the first input terminal of the first delay cell; a fourth delay cell comprising an output terminal a first input terminal coupled to its output terminal, a second input terminal coupled to the output terminal of the third delay cell, and a complementary output terminal coupled to the second input terminal of the first delay cell; and a data edge detection circuit to receive an input data signal and to generate a select pulse in response to transitions in said input data signal, wherein the first, second, third and fourth delay cells are configured to receive the select pulse corresponding to an input data transition, and in absence of the select pulse, to select their respective second input terminals and apply respective delays to oscillate with an oscillation generating a first phase shifted recovered clock at the output of the second delay cell, a second phase shifted recovered clock at the output of the fourth delay cell, a third phase shifted recovered clock at the complementary output of the second delay cell, and a fourth phase shifted recovered clock at the complementary output of the fourth delay cell, and wherein the first, second, third and fourth delay cells are configured, based on said selecting their respective first input terminals in response to the select pulse, to synchronize the first, second, third and fourth phase shifted recovered clocks to align with a first, second, third and fourth data, respectively, following the data transition that causes the data edge detection circuit to generate said select pulse. a first delay cell comprising a first input terminal a second input terminal an output terminal and a complementary output terminal; a second delay cell comprising a first input terminal, an output terminal coupled to its first input terminal, a complementary output terminal, and a second input terminal coupled to the output terminal of the first delay cell; a third delay cell comprising a first input terminal coupled to the output terminal of the first delay cell, and a second input terminal coupled to the output terminal of the second delay cell, an output terminal, and a complementary output terminal coupled to the first input terminal of the first delay cell; a fourth delay cell comprising an output terminal a first input terminal coupled to its output terminal, a second input terminal coupled to the output terminal of the third delay cell, and a complementary output terminal coupled to the second input terminal of the first delay cell; and a data edge detection circuit to receive an input data signal and to generate a select pulse in response to transitions in said input data signal, wherein the first, second, third and fourth delay cells are configured to receive the select pulse corresponding to an input data transition, and in absence of the select pulse, to select their respective second input terminals and apply respective delays to oscillate with an oscillation generating a first phase shifted recovered clock at the output of the second delay cell, a second phase shifted recovered clock at the output of the fourth delay cell, a third phase shifted recovered clock at the complementary output of the second delay cell, and a fourth phase shifted recovered clock at the complementary output of the fourth delay cell, and wherein the first, second, third and fourth delay cells are configured, based on said selecting their respective first input terminals in response to the select pulse, to synchronize the first, second, third and fourth phase shifted recovered clocks to align with a first, second, third and fourth data, respectively, following the data transition that causes the data edge detection circuit to generate said select pulse.