A spin-torque magnetoresistive memory, comprising: an array of spin-torque magnetoresistive memory cells; a plurality of latches; a circuit coupled to the array of memory cells and the plurality of latches, the circuit configured to: sample bits within the array, wherein sampling provides a sampled voltage for each of the bits, wherein the circuit is configured to sample each of the bits by applying a first voltage across a memory cell storing the bit and converting a current resulting from applying the first voltage to the corresponding sampled voltage; after sampling the bits, apply a first write current pulse to each of the memory cells storing the bits to set the bits to a first logic state; after applying the first write current pulse to each of the memory cells storing the bits, resample each of the bits wherein the circuit is configured to resample each of the bits by reapplying the first voltage across the memory cell storing the bit, adding an offset current to a current resulting from reapplying the first voltage across the memory cell storing the bit, for each of the bits, compare the corresponding resulting current through the memory cell storing the bit added with the offset current with the corresponding current due to the corresponding sampled voltage to generate a corresponding evaluation voltage, for each of the bits based on the corresponding evaluation voltage, determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and store the bit state for each of the bits in a corresponding latch of the plurality of latches; and for each of the bits having the second logic state as stored in the plurality of latches, initiate a write-back to reset the bit to the second state in the array, wherein the write-back for the bit includes applying a second write current pulse to the corresponding memory cell to set the bit to the second state. an array of spin-torque magnetoresistive memory cells; a plurality of latches; a circuit coupled to the array of memory cells and the plurality of latches, the circuit configured to: sample bits within the array, wherein sampling provides a sampled voltage for each of the bits, wherein the circuit is configured to sample each of the bits by applying a first voltage across a memory cell storing the bit and converting a current resulting from applying the first voltage to the corresponding sampled voltage; after sampling the bits, apply a first write current pulse to each of the memory cells storing the bits to set the bits to a first logic state; after applying the first write current pulse to each of the memory cells storing the bits, resample each of the bits wherein the circuit is configured to resample each of the bits by reapplying the first voltage across the memory cell storing the bit, adding an offset current to a current resulting from reapplying the first voltage across the memory cell storing the bit, for each of the bits, compare the corresponding resulting current through the memory cell storing the bit added with the offset current with the corresponding current due to the corresponding sampled voltage to generate a corresponding evaluation voltage, for each of the bits based on the corresponding evaluation voltage, determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and store the bit state for each of the bits in a corresponding latch of the plurality of latches; and for each of the bits having the second logic state as stored in the plurality of latches, initiate a write-back to reset the bit to the second state in the array, wherein the write-back for the bit includes applying a second write current pulse to the corresponding memory cell to set the bit to the second state. sample bits within the array, wherein sampling provides a sampled voltage for each of the bits, wherein the circuit is configured to sample each of the bits by applying a first voltage across a memory cell storing the bit and converting a current resulting from applying the first voltage to the corresponding sampled voltage; after sampling the bits, apply a first write current pulse to each of the memory cells storing the bits to set the bits to a first logic state; after applying the first write current pulse to each of the memory cells storing the bits, resample each of the bits wherein the circuit is configured to resample each of the bits by reapplying the first voltage across the memory cell storing the bit, adding an offset current to a current resulting from reapplying the first voltage across the memory cell storing the bit, for each of the bits, compare the corresponding resulting current through the memory cell storing the bit added with the offset current with the corresponding current due to the corresponding sampled voltage to generate a corresponding evaluation voltage, for each of the bits based on the corresponding evaluation voltage, determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and store the bit state for each of the bits in a corresponding latch of the plurality of latches; and for each of the bits having the second logic state as stored in the plurality of latches, initiate a write-back to reset the bit to the second state in the array, wherein the write-back for the bit includes applying a second write current pulse to the corresponding memory cell to set the bit to the second state.