A power semiconductor device comprising: a heat conducting and insulating ceramic substrate; an element circuit pattern formed on a top surface of said substrate and made of Cu covered with an Ni-P plating layer formed by chemical electroless NiP plating; a power semiconductor element (40, 42) bonded to said element circuit pattern by a first solder (30, 32) formed in a first reflow process by melting a first alloy consisting of Sn, Sb, and Cu, said first alloy having a weight percent of Sb in the range of 6.5 to 8%, inclusive, and a weight percent of Cu in the range of 0.5 to 1%, inclusive, the remaining weight percents of said first alloy being Sn, and said first alloy having a solidus temperature in the range of 235 to 238°C, inclusive, wherein a compound layer of Cu-Sn-Ni is formed at the interface between the Ni-P plating layer and the first solder (30, 32) when this solder is melted in said first reflow process, the Cu-Sn-Ni compound layer acting as a barrier layer to prevent the diffusion of Ni from the Ni-P plating layer into the first solder (30, 32); a terminal circuit pattern formed on said top surface of said substrate and made of Cu covered with an Ni-P plating layer formed by chemical electroless NiP plating; and a terminal bonded to said terminal circuit pattern by a second solder formed in a second reflow process by melting an Sn-Ag-based or Sn-Ag-Cu-based unleaded solder having a liquidus temperature in the range of 215 to 220°C, inclusive, said second reflow process being performed after said first reflow process and being performed at a temperature lower than 235°C, said first solder (30, 32) not having remelted in said second reflow process. a heat conducting and insulating ceramic substrate; an element circuit pattern formed on a top surface of said substrate and made of Cu covered with an Ni-P plating layer formed by chemical electroless NiP plating; a power semiconductor element (40, 42) bonded to said element circuit pattern by a first solder (30, 32) formed in a first reflow process by melting a first alloy consisting of Sn, Sb, and Cu, said first alloy having a weight percent of Sb in the range of 6.5 to 8%, inclusive, and a weight percent of Cu in the range of 0.5 to 1%, inclusive, the remaining weight percents of said first alloy being Sn, and said first alloy having a solidus temperature in the range of 235 to 238°C, inclusive, wherein a compound layer of Cu-Sn-Ni is formed at the interface between the Ni-P plating layer and the first solder (30, 32) when this solder is melted in said first reflow process, the Cu-Sn-Ni compound layer acting as a barrier layer to prevent the diffusion of Ni from the Ni-P plating layer into the first solder (30, 32); a terminal circuit pattern formed on said top surface of said substrate and made of Cu covered with an Ni-P plating layer formed by chemical electroless NiP plating; and a terminal bonded to said terminal circuit pattern by a second solder formed in a second reflow process by melting an Sn-Ag-based or Sn-Ag-Cu-based unleaded solder having a liquidus temperature in the range of 215 to 220°C, inclusive, said second reflow process being performed after said first reflow process and being performed at a temperature lower than 235°C, said first solder (30, 32) not having remelted in said second reflow process.