A reception circuit comprising: a determination circuit including: a first number of first comparator circuits (12-H0, 12-Z0, 12-L0) configured to perform determination of a level of a received signal on the basis of a first clock signal among four clock signals having different phases and output first determination signals; and the first number of second comparator circuits (12-H1, 12-Z1, 12-L1) configured to perform determination of a level of the received signal on the basis of a second clock signal among the four clock signals, wherein the phase difference between the first and second clock signals is 180 degrees, and output second determination signals, the determination circuit being configured to perform determination by using the first number of the first comparator circuits (12-H0, 12-Z0, 12-L0) and the first number of the second comparator circuits (12-H1, 12-Z1, 12-L1) when the received signal is a first signal which is a multi-valued signal, and configured to perform determination by using a second number of the first comparator circuits (12-H0, 12-Z0, 12-L0) and the second number of the second comparator circuits (12-H1, 12-Z1, 12-L1), the second number being two or more and smaller than the first number, when the received signal is a second signal, a number of possible values of the second signal being smaller than a number of possible values of the first signal; a timing aligner circuit configured to synchronize the first determination signals and the second determination signals with one of the four clock signals and output first synchronized determination signals corresponding to the first determination signals and second synchronized determination signals corresponding to the second determination signals; and a logic circuit configured to generate digital signals based on the first and second synchronized determination signals, the logic circuit being configured to operate as a decoder which decodes the first and second synchronized determination signals and generates the digital signals when the received signal is the first signal, and configured to operate as a selector which selects one of the first synchronized determination signals and one of the second synchronized determination signals and generates the digital signals when the received signal is the second signal. a first number of first comparator circuits (12-H0, 12-Z0, 12-L0) configured to perform determination of a level of a received signal on the basis of a first clock signal among four clock signals having different phases and output first determination signals; and the first number of second comparator circuits (12-H1, 12-Z1, 12-L1) configured to perform determination of a level of the received signal on the basis of a second clock signal among the four clock signals, wherein the phase difference between the first and second clock signals is 180 degrees, and output second determination signals, the determination circuit being configured to perform determination by using the first number of the first comparator circuits (12-H0, 12-Z0, 12-L0) and the first number of the second comparator circuits (12-H1, 12-Z1, 12-L1) when the received signal is a first signal which is a multi-valued signal, and configured to perform determination by using a second number of the first comparator circuits (12-H0, 12-Z0, 12-L0) and the second number of the second comparator circuits (12-H1, 12-Z1, 12-L1), the second number being two or more and smaller than the first number, when the received signal is a second signal, a number of possible values of the second signal being smaller than a number of possible values of the first signal; a timing aligner circuit configured to synchronize the first determination signals and the second determination signals with one of the four clock signals and output first synchronized determination signals corresponding to the first determination signals and second synchronized determination signals corresponding to the second determination signals; and a logic circuit configured to generate digital signals based on the first and second synchronized determination signals, the logic circuit being configured to operate as a decoder which decodes the first and second synchronized determination signals and generates the digital signals when the received signal is the first signal, and configured to operate as a selector which selects one of the first synchronized determination signals and one of the second synchronized determination signals and generates the digital signals when the received signal is the second signal.