Back bias generator circuit at least comprising: - a digital to analog converter generating an output voltage at an output terminal based on a digital input to the circuit, - an upper and a lower switched capacitor circuit, and - a control unit for the digital to analog converter and switched capacitor circuits, - wherein said digital to analog converter -- has an upper supply terminal (vdd) and a lower supply terminal (vss) for applying an upper supply voltage and a lower supply voltage, respectively, an upper input terminal (vddh), a lower input terminal (vssl), a lower terminal (vddl) and an upper terminal (vssh), and -- is formed of a resistor string and a switching network of several switching transistors which are arranged to allow a tapping of a voltage at selectable locations of the resistor string and at the upper and lower input terminals (vddh, vssl) and to pass the tapped voltage to the output terminal, the resistor string being connected between the upper supply terminal (vdd) and the lower supply terminal (vss), wherein -- an uppermost resistor or combination of resistors in series of the resistor string with an upper end is directly connected to the upper supply terminal (vdd) and with a lower end via the lower terminal (vddl) to the upper switched capacitor circuit, and a lowermost resistor or combination of resistors in series of the resistor string with a lower end is directly connected to the lower supply terminal (vss) and with an upper end via the upper terminal (vssh) to the lower switched capacitor circuit, and - wherein said upper switched capacitor circuit and said lower switched capacitor circuit being formed to generate and supply an extended upper voltage (VDDH) to the upper input terminal (vddh) of the digital to analog converter and an extended lower voltage (VSSL) to the lower input terminal of the digital to analog converter, said extended upper voltage (VDDH) exceeding the upper supply voltage by a voltage difference between the upper supply voltage and a voltage (VDDL) at the lower terminal (vddl), said extended lower voltage (VSSL) undercutting the lower supply voltage by a voltage difference between a voltage (VSSH) at the upper terminal (vssh) and the lower supply voltage. - a digital to analog converter generating an output voltage at an output terminal based on a digital input to the circuit, - an upper and a lower switched capacitor circuit, and - a control unit for the digital to analog converter and switched capacitor circuits, - wherein said digital to analog converter -- has an upper supply terminal (vdd) and a lower supply terminal (vss) for applying an upper supply voltage and a lower supply voltage, respectively, an upper input terminal (vddh), a lower input terminal (vssl), a lower terminal (vddl) and an upper terminal (vssh), and -- is formed of a resistor string and a switching network of several switching transistors which are arranged to allow a tapping of a voltage at selectable locations of the resistor string and at the upper and lower input terminals (vddh, vssl) and to pass the tapped voltage to the output terminal, the resistor string being connected between the upper supply terminal (vdd) and the lower supply terminal (vss), wherein -- an uppermost resistor or combination of resistors in series of the resistor string with an upper end is directly connected to the upper supply terminal (vdd) and with a lower end via the lower terminal (vddl) to the upper switched capacitor circuit, and a lowermost resistor or combination of resistors in series of the resistor string with a lower end is directly connected to the lower supply terminal (vss) and with an upper end via the upper terminal (vssh) to the lower switched capacitor circuit, and -- has an upper supply terminal (vdd) and a lower supply terminal (vss) for applying an upper supply voltage and a lower supply voltage, respectively, an upper input terminal (vddh), a lower input terminal (vssl), a lower terminal (vddl) and an upper terminal (vssh), and -- is formed of a resistor string and a switching network of several switching transistors which are arranged to allow a tapping of a voltage at selectable locations of the resistor string and at the upper and lower input terminals (vddh, vssl) and to pass the tapped voltage to the output terminal, the resistor string being connected between the upper supply terminal (vdd) and the lower supply terminal (vss), wherein -- an uppermost resistor or combination of resistors in series of the resistor string with an upper end is directly connected to the upper supply terminal (vdd) and with a lower end via the lower terminal (vddl) to the upper switched capacitor circuit, and a lowermost resistor or combination of resistors in series of the resistor string with a lower end is directly connected to the lower supply terminal (vss) and with an upper end via the upper terminal (vssh) to the lower switched capacitor circuit, and - wherein said upper switched capacitor circuit and said lower switched capacitor circuit being formed to generate and supply an extended upper voltage (VDDH) to the upper input terminal (vddh) of the digital to analog converter and an extended lower voltage (VSSL) to the lower input terminal of the digital to analog converter, said extended upper voltage (VDDH) exceeding the upper supply voltage by a voltage difference between the upper supply voltage and a voltage (VDDL) at the lower terminal (vddl), said extended lower voltage (VSSL) undercutting the lower supply voltage by a voltage difference between a voltage (VSSH) at the upper terminal (vssh) and the lower supply voltage.