A shift register unit comprising: a pull-up control module configured to receive an input signal and output a pull-up control signal to a pull-up node; a pull-up module configured to provide a signal input from a first clock signal input terminal to a first output terminal (OutPut1) according to the pull-up control signal at the pull-up node; a reset module configured to provide a first power supply voltage to the pull-up node and the first output terminal (OutPut1) according to a reset signal at a reset signal input terminal (Rst) and a reset control signal; a noise removal module configured to hold a signal output from the first output terminal (OutPut1) in response to the signal output from the first output terminal (OutPut1) having a level higher than a first preset threshold and to output the held signal at a second output terminal (OutPut2) in response to a signal output from a noise removal control signal output terminal having a level higher than a second preset threshold, so that the signal output at the second output terminal (OutPut2) is free of noise; wherein the noise removal control signal output terminal is connected to a second clock signal input terminal (CLKB) or a reset control node, and wherein a signal input from the second clock signal input terminal (CLKB) has an opposite phase to the signal input from the first clock signal input terminal, and a reset control module configured to output the reset control signal to the reset control node according to the pull-up control signal and according to one of a second power supply voltage and the signal input from the second clock signal input terminal (CLKB). a pull-up control module configured to receive an input signal and output a pull-up control signal to a pull-up node; a pull-up module configured to provide a signal input from a first clock signal input terminal to a first output terminal (OutPut1) according to the pull-up control signal at the pull-up node; a reset module configured to provide a first power supply voltage to the pull-up node and the first output terminal (OutPut1) according to a reset signal at a reset signal input terminal (Rst) and a reset control signal; a noise removal module configured to hold a signal output from the first output terminal (OutPut1) in response to the signal output from the first output terminal (OutPut1) having a level higher than a first preset threshold and to output the held signal at a second output terminal (OutPut2) in response to a signal output from a noise removal control signal output terminal having a level higher than a second preset threshold, so that the signal output at the second output terminal (OutPut2) is free of noise; wherein the noise removal control signal output terminal is connected to a second clock signal input terminal (CLKB) or a reset control node, and wherein a signal input from the second clock signal input terminal (CLKB) has an opposite phase to the signal input from the first clock signal input terminal, and a reset control module configured to output the reset control signal to the reset control node according to the pull-up control signal and according to one of a second power supply voltage and the signal input from the second clock signal input terminal (CLKB).