An analog neural memory system comprising: an array of non-volatile split gate or stacked gate flash memory cells, wherein the cells are arranged in rows (row0 - row3) and columns, the memory cells of each row are coupled to a respective common source line (SLO, SL1); the columns are arranged in groups of two physically adjacent pairs of physically adjacent columns ((BL0, BL1); (BL2, BL3)), wherein within each pair of physically adjacent columns, one column comprises cells storing positive weight values and the other column comprises cells storing negative weight values, wherein adjacent cells in a row within each pair of physically adjacent columns are configured to store differential weight bits, the array further comprising two redundant columns (BL01, BL23), one on each side of each group of two physically adjacent pairs of physically adjacent columns, wherein the system is configured to remap the weight bits of each physically adjacent column (BL1, BL2) of the two physically adjacent pairs of physically adjacent columns ((BL0, BL1); (BL2, BL3)) to the corresponding redundant column resulting in no adjacent "1" weight bits between any physically adjacent column of the group; the array further comprising two dummy cell columns configured to operate as source line pull down bit lines (BLPWDN), one on each side of each redundant column of the group, wherein each column of the two physically adjacent pairs of physically adjacent columns is coupled to bit line switches on a first side of the array and the two dummy cell columns are coupled to dummy bit line switches on a second side of the array opposite the first side, wherein each dummy cell column is configured to connect memory cell source lines to ground through the dummy bit line switch; and the system further comprising a summer configured for generating a first sum of an output (W+) from a first bit line and generating a second sum of an output (W-) from a second bit line and outputting a difference between the first sum and the second sum (W = (W+) - (W-)). an array of non-volatile split gate or stacked gate flash memory cells, wherein the cells are arranged in rows (row0 - row3) and columns, the memory cells of each row are coupled to a respective common source line (SLO, SL1); the columns are arranged in groups of two physically adjacent pairs of physically adjacent columns ((BL0, BL1); (BL2, BL3)), wherein within each pair of physically adjacent columns, one column comprises cells storing positive weight values and the other column comprises cells storing negative weight values, wherein adjacent cells in a row within each pair of physically adjacent columns are configured to store differential weight bits, the array further comprising two redundant columns (BL01, BL23), one on each side of each group of two physically adjacent pairs of physically adjacent columns, wherein the system is configured to remap the weight bits of each physically adjacent column (BL1, BL2) of the two physically adjacent pairs of physically adjacent columns ((BL0, BL1); (BL2, BL3)) to the corresponding redundant column resulting in no adjacent "1" weight bits between any physically adjacent column of the group; the array further comprising two dummy cell columns configured to operate as source line pull down bit lines (BLPWDN), one on each side of each redundant column of the group, wherein each column of the two physically adjacent pairs of physically adjacent columns is coupled to bit line switches on a first side of the array and the two dummy cell columns are coupled to dummy bit line switches on a second side of the array opposite the first side, wherein each dummy cell column is configured to connect memory cell source lines to ground through the dummy bit line switch; and the system further comprising a summer configured for generating a first sum of an output (W+) from a first bit line and generating a second sum of an output (W-) from a second bit line and outputting a difference between the first sum and the second sum (W = (W+) - (W-)).