A placement system comprising: one or more computer processors; one or more computer-readable media having instructions that, responsive to execution by the one or more computer processors, implements a placement manager, the placement manager configured to: receive, for a first type of clock cell (102, 104, 106, 304), a first keep-out region (108, 110, 112, 510); receive, for a second type of clock cell (102, 104, 106, 304), a second keep-out region (108, 110, 112, 510) having a different size than the first keep-out region (108, 110, 112, 510), wherein the first keep-out region (108, 110, 112, 510) and the second keep-out region (108, 110, 112, 510) are determined based on the power-usage density of the first type of clock cell (102, 104, 106, 304) and the power-usage density of the second type of clock cell (102, 104, 106, 304), respectively; and place in an integrated circuit the first type of clock cell (102, 104, 106, 304) and the second type of clock cell (102, 104, 106, 304) without overlap of the first keep-out region (108, 110, 112, 510) and the second keep-out region (108, 110, 112, 510); and place non-clock cells such as data cells within the keep-out regions (108, 110, 112, 510). one or more computer processors; one or more computer-readable media having instructions that, responsive to execution by the one or more computer processors, implements a placement manager, the placement manager configured to: receive, for a first type of clock cell (102, 104, 106, 304), a first keep-out region (108, 110, 112, 510); receive, for a second type of clock cell (102, 104, 106, 304), a second keep-out region (108, 110, 112, 510) having a different size than the first keep-out region (108, 110, 112, 510), wherein the first keep-out region (108, 110, 112, 510) and the second keep-out region (108, 110, 112, 510) are determined based on the power-usage density of the first type of clock cell (102, 104, 106, 304) and the power-usage density of the second type of clock cell (102, 104, 106, 304), respectively; and place in an integrated circuit the first type of clock cell (102, 104, 106, 304) and the second type of clock cell (102, 104, 106, 304) without overlap of the first keep-out region (108, 110, 112, 510) and the second keep-out region (108, 110, 112, 510); and place non-clock cells such as data cells within the keep-out regions (108, 110, 112, 510). receive, for a first type of clock cell (102, 104, 106, 304), a first keep-out region (108, 110, 112, 510); receive, for a second type of clock cell (102, 104, 106, 304), a second keep-out region (108, 110, 112, 510) having a different size than the first keep-out region (108, 110, 112, 510), wherein the first keep-out region (108, 110, 112, 510) and the second keep-out region (108, 110, 112, 510) are determined based on the power-usage density of the first type of clock cell (102, 104, 106, 304) and the power-usage density of the second type of clock cell (102, 104, 106, 304), respectively; and place in an integrated circuit the first type of clock cell (102, 104, 106, 304) and the second type of clock cell (102, 104, 106, 304) without overlap of the first keep-out region (108, 110, 112, 510) and the second keep-out region (108, 110, 112, 510); and place non-clock cells such as data cells within the keep-out regions (108, 110, 112, 510).