A computing node, comprising: one or more processors; a system address decoder; and a host fabric interface, HFI, comprising logic configured to: receive, from the one or more processors, a command to copy data, the command indicating a source address, a target address and an offset value; determine, via the system address decoder, a source non-uniform memory access, NUMA, domain ID for the source address and a target NUMA domain ID for the target address; identify a source computing node, coupled to the computing node, with memory that corresponds to the source NUMA domain ID and a target computing node, coupled to the computing node, with memory that corresponds to the target NUMA domain ID using a translation table; and generate a command for copying data in a source memory range of the source computing node to a target memory range of the target computing node, wherein the source memory range is defined by the source address and the offset value and the target memory range is defined by the target address and the offset value, wherein the HFI further comprises logic to: transmit the command to the source computing node, wherein the source computing node is configured to read the data in the source memory range and write the data to the target memory range of the target computing node, and wherein the one or more processors are not used to copy the data from the source memory range of the source computing node to the target memory range of the target computing node. one or more processors; a system address decoder; and a host fabric interface, HFI, comprising logic configured to: receive, from the one or more processors, a command to copy data, the command indicating a source address, a target address and an offset value; determine, via the system address decoder, a source non-uniform memory access, NUMA, domain ID for the source address and a target NUMA domain ID for the target address; identify a source computing node, coupled to the computing node, with memory that corresponds to the source NUMA domain ID and a target computing node, coupled to the computing node, with memory that corresponds to the target NUMA domain ID using a translation table; and generate a command for copying data in a source memory range of the source computing node to a target memory range of the target computing node, wherein the source memory range is defined by the source address and the offset value and the target memory range is defined by the target address and the offset value, wherein the HFI further comprises logic to: transmit the command to the source computing node, wherein the source computing node is configured to read the data in the source memory range and write the data to the target memory range of the target computing node, and wherein the one or more processors are not used to copy the data from the source memory range of the source computing node to the target memory range of the target computing node. receive, from the one or more processors, a command to copy data, the command indicating a source address, a target address and an offset value; determine, via the system address decoder, a source non-uniform memory access, NUMA, domain ID for the source address and a target NUMA domain ID for the target address; identify a source computing node, coupled to the computing node, with memory that corresponds to the source NUMA domain ID and a target computing node, coupled to the computing node, with memory that corresponds to the target NUMA domain ID using a translation table; and generate a command for copying data in a source memory range of the source computing node to a target memory range of the target computing node, wherein the source memory range is defined by the source address and the offset value and the target memory range is defined by the target address and the offset value, wherein the HFI further comprises logic to: transmit the command to the source computing node, wherein the source computing node is configured to read the data in the source memory range and write the data to the target memory range of the target computing node, and wherein the one or more processors are not used to copy the data from the source memory range of the source computing node to the target memory range of the target computing node.