A distributed voltage network circuit (300, 400), comprising: a voltage distribution source component (308, 408) comprising a plurality of source nodes (306, 406); a distributed load circuit (316, 416) comprising a plurality of voltage load nodes (314, 414); a distributed source distribution network (302, 402), comprising: a plurality of resistive interconnects (312, 412) interconnecting each source node among the plurality of source nodes to a corresponding voltage load node among the plurality of voltage load nodes; a plurality of transistors (304, 404), each transistor among the plurality of transistors corresponding to a source node among the plurality of source nodes and a voltage load node among the plurality of voltage load nodes; and a plurality of voltage tap nodes (322, 422), wherein a single voltage tap node corresponds to each voltage load node among the plurality of voltage load nodes; and a voltage averaging circuit (328, 428), comprising: a plurality of resistive elements (326, 426), each resistive element among the plurality of resistive elements comprising: an input node (324, 424) coupled to a corresponding voltage tap node among the plurality of voltage tap nodes; and an output node (330, 430); and a voltage output node (332, 432) coupled to the output node of each resistive element among the plurality of resistive elements, the voltage output node configured to provide an average voltage of the distributed load circuit; characterized in that each resistive element has a resistance based on a gate width of the transistor corresponding to the voltage load node of the corresponding voltage tap node. a voltage distribution source component (308, 408) comprising a plurality of source nodes (306, 406); a distributed load circuit (316, 416) comprising a plurality of voltage load nodes (314, 414); a distributed source distribution network (302, 402), comprising: a plurality of resistive interconnects (312, 412) interconnecting each source node among the plurality of source nodes to a corresponding voltage load node among the plurality of voltage load nodes; a plurality of transistors (304, 404), each transistor among the plurality of transistors corresponding to a source node among the plurality of source nodes and a voltage load node among the plurality of voltage load nodes; and a plurality of voltage tap nodes (322, 422), wherein a single voltage tap node corresponds to each voltage load node among the plurality of voltage load nodes; and a plurality of resistive interconnects (312, 412) interconnecting each source node among the plurality of source nodes to a corresponding voltage load node among the plurality of voltage load nodes; a plurality of transistors (304, 404), each transistor among the plurality of transistors corresponding to a source node among the plurality of source nodes and a voltage load node among the plurality of voltage load nodes; and a plurality of voltage tap nodes (322, 422), wherein a single voltage tap node corresponds to each voltage load node among the plurality of voltage load nodes; and a voltage averaging circuit (328, 428), comprising: a plurality of resistive elements (326, 426), each resistive element among the plurality of resistive elements comprising: an input node (324, 424) coupled to a corresponding voltage tap node among the plurality of voltage tap nodes; and an output node (330, 430); and a voltage output node (332, 432) coupled to the output node of each resistive element among the plurality of resistive elements, the voltage output node configured to provide an average voltage of the distributed load circuit; a plurality of resistive elements (326, 426), each resistive element among the plurality of resistive elements comprising: an input node (324, 424) coupled to a corresponding voltage tap node among the plurality of voltage tap nodes; and an output node (330, 430); and an input node (324, 424) coupled to a corresponding voltage tap node among the plurality of voltage tap nodes; and an output node (330, 430); and a voltage output node (332, 432) coupled to the output node of each resistive element among the plurality of resistive elements, the voltage output node configured to provide an average voltage of the distributed load circuit; characterized in that each resistive element has a resistance based on a gate width of the transistor corresponding to the voltage load node of the corresponding voltage tap node.