A storage device comprising: a plurality of nonvolatile memories (NVM11 to NVMmn), each including a plurality of multi-level cell memory blocks including a plurality of pages including multi-level memory cells storing plural bits of data, each of the plurality of pages comprising a plurality of sub-pages, wherein each of the plurality of sub-pages corresponds to a memory cell level, and each of the plurality of nonvolatile memories (NVM11 to NVMmn) performing high-speed programming, HSP, operation to program the sub-pages included one of the plurality of pages in one-time operation; and a controller configured to control the plurality of nonvolatile memories (NVM11 to NVMmn), wherein the controller is configured to buffer data chunks received along with write commands from a host, is configured to determine a size of continuous data based on a start logical address and a chunk size of the data chunks, is configured to determine a striping number indicating a number of nonvolatile memory which is for distributing and storing the data chunks in sub-page units based on the size of continuous data, and is configured to distribute and provide the data chunks in the sub-page unit to one or more nonvolatile memories selected from among the plurality of nonvolatile memories (NVM11 to NVMmn) based on the determined striping number, the one or more selected nonvolatile memories are configured to perform the HSP operation on the provided data chunks in parallel, wherein the controller is configured to determine any one of candidate striping numbers as the striping number according to a result of comparing a value obtained by dividing the size of continuous data by a sub-page size with a given candidate striping number, and wherein the controller is configured to determine the striping number so that the striping number increases as the size of continuous data increases. a plurality of nonvolatile memories (NVM11 to NVMmn), each including a plurality of multi-level cell memory blocks including a plurality of pages including multi-level memory cells storing plural bits of data, each of the plurality of pages comprising a plurality of sub-pages, wherein each of the plurality of sub-pages corresponds to a memory cell level, and each of the plurality of nonvolatile memories (NVM11 to NVMmn) performing high-speed programming, HSP, operation to program the sub-pages included one of the plurality of pages in one-time operation; and a controller configured to control the plurality of nonvolatile memories (NVM11 to NVMmn), wherein the controller is configured to buffer data chunks received along with write commands from a host, is configured to determine a size of continuous data based on a start logical address and a chunk size of the data chunks, is configured to determine a striping number indicating a number of nonvolatile memory which is for distributing and storing the data chunks in sub-page units based on the size of continuous data, and is configured to distribute and provide the data chunks in the sub-page unit to one or more nonvolatile memories selected from among the plurality of nonvolatile memories (NVM11 to NVMmn) based on the determined striping number, the one or more selected nonvolatile memories are configured to perform the HSP operation on the provided data chunks in parallel, wherein the controller is configured to determine any one of candidate striping numbers as the striping number according to a result of comparing a value obtained by dividing the size of continuous data by a sub-page size with a given candidate striping number, and wherein the controller is configured to determine the striping number so that the striping number increases as the size of continuous data increases.