A bit line structure for connecting columns of spin moment transfer MRAM cells hereinafter SMT MRAM cells within an array of SMT MRAM cells arranged in rows and columns comprising: - pairs of true data bit lines (250a, 250b,..., 250n-1, 250n), wherein, for each pair of true data bit lines, one true data bit line (250a, 250b,..., 250n-1, 250n) of the pair of true data bit lines (250a, 250b,..., 250n-1, 250n) is connected to an MTJ device of each SMT MRAM cell of a column of a corresponding pair of columns of the SMT MRAM cells and the other true data bit line (250a, 250b,..., 250n-1, 250n) of the pair of true data bit lines (250a, 250b,..., 250n-1, 250n) is connected to the MTJ device of each SMT MRAM cell of the other column of the corresponding pair of columns of the SMT MRAM cells; - complement data bit lines (255a,..., 255n), each complement data bit line connected to a source of a gating transistor of each SMT MRAM cell of a corresponding pair of associated columns of the SMT MRAM cells; - pairs of shunting switch transistors (205a,..., 205n and 206a,..., 206n) wherein, for each pair of shunting switch transistors, a first shunting transistor (205a,..., 205n) of the pair of shunting switch transistors (205an..., 205n and 206a,..., 206n) is connected between one true data bit line (250a, 250b,..., 250n-1, 250n) and the complement data bit line (255a,..., 255n) of one corresponding column pair of columns of the SMT MRAM cells, and a second shunting transistor (206a,..., 206n) of the pair of shunting switch transistors (205a,..., 205n and 206a,..., 206n) is connected between the other true bit line (250a, 250b,..., 250n-1, 250n) and the complement bit line (255a,..., 255n) of the corresponding column pair of the SMT MRAM cells, - a shunting switch transistor activation signal line and a complement shunting switch transistor activation signal line; characterized in that the first shunting transistors of the pairs of shunting switch transistors (205a,..., 205n and 206a,..., 206n) each has an activation terminal connected to the shunting switch transistor activation signal line and the second shunting transistors of the pairs of shunting switch transistors (206a,..., 206n) each has an activation terminal connected to the complement shunting switch transistor activation signal line, such that each true data bit lines (250a, 250b,..., 250n-1, 250n) of unselected columns corresponding to said pairs of shunting switch transistors is connected in parallel with the corresponding shared complement data bit line (255a,..., 255n) to effectively reduce program disturb effects in the unselected column of SMT MRAM cells - pairs of true data bit lines (250a, 250b,..., 250n-1, 250n), wherein, for each pair of true data bit lines, one true data bit line (250a, 250b,..., 250n-1, 250n) of the pair of true data bit lines (250a, 250b,..., 250n-1, 250n) is connected to an MTJ device of each SMT MRAM cell of a column of a corresponding pair of columns of the SMT MRAM cells and the other true data bit line (250a, 250b,..., 250n-1, 250n) of the pair of true data bit lines (250a, 250b,..., 250n-1, 250n) is connected to the MTJ device of each SMT MRAM cell of the other column of the corresponding pair of columns of the SMT MRAM cells; - complement data bit lines (255a,..., 255n), each complement data bit line connected to a source of a gating transistor of each SMT MRAM cell of a corresponding pair of associated columns of the SMT MRAM cells; - pairs of shunting switch transistors (205a,..., 205n and 206a,..., 206n) wherein, for each pair of shunting switch transistors, a first shunting transistor (205a,..., 205n) of the pair of shunting switch transistors (205an..., 205n and 206a,..., 206n) is connected between one true data bit line (250a, 250b,..., 250n-1, 250n) and the complement data bit line (255a,..., 255n) of one corresponding column pair of columns of the SMT MRAM cells, and a second shunting transistor (206a,..., 206n) of the pair of shunting switch transistors (205a,..., 205n and 206a,..., 206n) is connected between the other true bit line (250a, 250b,..., 250n-1, 250n) and the complement bit line (255a,..., 255n) of the corresponding column pair of the SMT MRAM cells, - a shunting switch transistor activation signal line and a complement shunting switch transistor activation signal line;