A storage device comprising: a reference clock pin configured to receive a reference clock signal (REF_CLK) from a host (200; 200A; 200B; 1100); a reference clock frequency determination circuitry (140; 140b; 140c) configured to determine a reference clock frequency from the reference clock signal (REF_CLK) received through the reference clock pin; and a device controller circuitry (120; 120a; 1210; 3100) configured to perform a high speed mode link startup between the host (200; 200A; 200B; 1100) and the storage device (100; 100A; 100B; 1200) according to the reference clock frequency, and characterized in that the reference clock frequency determination circuitry includes: a first resistor-capacitor filter configured to generate, at a first time point, a first output voltage (Vout1) corresponding to the reference clock signal (REF_CLK); and a second resistor-capacitor filter configured to generate, at a second time point, a second output voltage (Vout2) corresponding to the reference clock signal (REF_CLK), the second time point being different from the first time point, wherein the reference clock frequency determination circuitry is configured to determine the reference clock frequency based on the first and second output voltages (Vout1, Vout2), and wherein the reference clock frequency determination circuitry further includes a frequency divider circuitry connected between the reference clock pin and the first and second resistor-capacitor filters (144a, 144b) and configured to generate a frequency-divided reference clock signal (REF_CLK_DIV) by frequency-dividing the reference clock signal (REF_CLK), the first resistor-capacitor filter being configured to generate the first output voltage (Vout1) from the frequency-divided reference clock signal (REF_CLK_DIV) at the first time point corresponding to a first time constant, and the second resistor-capacitor filter being configured to generate the second output voltage (Vout2) from the frequency-divided reference clock signal (REF_CLK_DIV) at the second time point corresponding to a second time constant. a reference clock pin configured to receive a reference clock signal (REF_CLK) from a host (200; 200A; 200B; 1100); a reference clock frequency determination circuitry (140; 140b; 140c) configured to determine a reference clock frequency from the reference clock signal (REF_CLK) received through the reference clock pin; and a device controller circuitry (120; 120a; 1210; 3100) configured to perform a high speed mode link startup between the host (200; 200A; 200B; 1100) and the storage device (100; 100A; 100B; 1200) according to the reference clock frequency, and characterized in that the reference clock frequency determination circuitry includes: a first resistor-capacitor filter configured to generate, at a first time point, a first output voltage (Vout1) corresponding to the reference clock signal (REF_CLK); and a second resistor-capacitor filter configured to generate, at a second time point, a second output voltage (Vout2) corresponding to the reference clock signal (REF_CLK), the second time point being different from the first time point, wherein the reference clock frequency determination circuitry is configured to determine the reference clock frequency based on the first and second output voltages (Vout1, Vout2), and wherein the reference clock frequency determination circuitry further includes a frequency divider circuitry connected between the reference clock pin and the first and second resistor-capacitor filters (144a, 144b) and configured to generate a frequency-divided reference clock signal (REF_CLK_DIV) by frequency-dividing the reference clock signal (REF_CLK), the first resistor-capacitor filter being configured to generate the first output voltage (Vout1) from the frequency-divided reference clock signal (REF_CLK_DIV) at the first time point corresponding to a first time constant, and the second resistor-capacitor filter being configured to generate the second output voltage (Vout2) from the frequency-divided reference clock signal (REF_CLK_DIV) at the second time point corresponding to a second time constant. a first resistor-capacitor filter configured to generate, at a first time point, a first output voltage (Vout1) corresponding to the reference clock signal (REF_CLK); and a second resistor-capacitor filter configured to generate, at a second time point, a second output voltage (Vout2) corresponding to the reference clock signal (REF_CLK), the second time point being different from the first time point, wherein the reference clock frequency determination circuitry is configured to determine the reference clock frequency based on the first and second output voltages (Vout1, Vout2), and wherein the reference clock frequency determination circuitry further includes a frequency divider circuitry connected between the reference clock pin and the first and second resistor-capacitor filters (144a, 144b) and configured to generate a frequency-divided reference clock signal (REF_CLK_DIV) by frequency-dividing the reference clock signal (REF_CLK), the first resistor-capacitor filter being configured to generate the first output voltage (Vout1) from the frequency-divided reference clock signal (REF_CLK_DIV) at the first time point corresponding to a first time constant, and the second resistor-capacitor filter being configured to generate the second output voltage (Vout2) from the frequency-divided reference clock signal (REF_CLK_DIV) at the second time point corresponding to a second time constant.