A programmable-resistance non-volatile memory comprising a plurality of elementary cells (300; 500; 600; 700; 800) arranged in rows and in columns, each cell comprising: a first access transistor coupling first (n) and second nodes of the cell; a second access transistor coupling the first node (n) to a third node (DL; SL) of the cell; and a single programmable-resistance storage element connected to the first node (n), this storage element coupling the first node (n) to a fourth node (SL; DL) of the cell, wherein, in each row, the cells have their fourth nodes (SL; DL) connected by a first row-connection conductive track (SL i), and the gates of their first transistors connected by a second row-connection conductive track (WL ij), and wherein, in each column, the cells have their second nodes connected by a first column-connection conductive track (BL j) and their third nodes (DL; SL) connected by a second column-connection conductive track (DL j), the memory further comprising a control circuit connected to the cells via the first (SL i) and second (WL ij) row-connection conductive tracks and the first (BL j) and second (DL j) column-connection conductive tracks, this circuit being configured for: during a phase of programming a cell to a first state, maintaining the second transistor of the cell off and applying a voltage of a first biasing across the storage element of the cell via the fourth (SL; DL) and second nodes and the first transistor of the cell; and during a phase of programming the cell to a second state, maintaining the first transistor of the cell off and applying a voltage having an opposite biasing across the storage element of the cell via the fourth (SL; DL) and third (DL; SL) nodes and the second transistor of the cell, wherein the first and second transistors are MOS transistors of opposite conductivity types and/or of different dimensions. a first access transistor coupling first (n) and second nodes of the cell; a second access transistor coupling the first node (n) to a third node (DL; SL) of the cell; and a single programmable-resistance storage element connected to the first node (n), this storage element coupling the first node (n) to a fourth node (SL; DL) of the cell, wherein, in each row, the cells have their fourth nodes (SL; DL) connected by a first row-connection conductive track (SL i), and the gates of their first transistors connected by a second row-connection conductive track (WL ij), and wherein, in each column, the cells have their second nodes connected by a first column-connection conductive track (BL j) and their third nodes (DL; SL) connected by a second column-connection conductive track (DL j), the memory further comprising a control circuit connected to the cells via the first (SL i) and second (WL ij) row-connection conductive tracks and the first (BL j) and second (DL j) column-connection conductive tracks, this circuit being configured for: during a phase of programming a cell to a first state, maintaining the second transistor of the cell off and applying a voltage of a first biasing across the storage element of the cell via the fourth (SL; DL) and second nodes and the first transistor of the cell; and during a phase of programming the cell to a second state, maintaining the first transistor of the cell off and applying a voltage having an opposite biasing across the storage element of the cell via the fourth (SL; DL) and third (DL; SL) nodes and the second transistor of the cell, wherein the first and second transistors are MOS transistors of opposite conductivity types and/or of different dimensions. during a phase of programming a cell to a first state, maintaining the second transistor of the cell off and applying a voltage of a first biasing across the storage element of the cell via the fourth (SL; DL) and second nodes and the first transistor of the cell; and during a phase of programming the cell to a second state, maintaining the first transistor of the cell off and applying a voltage having an opposite biasing across the storage element of the cell via the fourth (SL; DL) and third (DL; SL) nodes and the second transistor of the cell, wherein the first and second transistors are MOS transistors of opposite conductivity types and/or of different dimensions.