A semiconductor light emitting device, comprising: a) a semiconductor layer including a first major surface, a second major surface opposite to the first major surface, and a light emitting layer, the semiconductor layer not including a substrate on the first major surface side; b1) a first electrode provided on a region including the light emitting layer on the second major surface; b2) a second electrode provided on the second major surface and at least partially interposed in the first electrode in a plan view; c) a first insulating layer provided on the second major surface side of the semiconductor layer, and covering a side surface continuing from the first major surface of the semiconductor layer; d1) a first interconnect layer provided on the first insulating layer on a side opposite to the semiconductor layer, the first interconnect layer provided in a first opening formed in the first insulating layer reaching the first electrode, and the first interconnect layer connected to the first electrode; d2) a second interconnect layer provided on the first insulating layer on the side opposite to the semiconductor layer, the second interconnect layer provided in a second opening formed in the first insulating layer reaching the second electrode, and the second interconnect layer connected to the second electrode; e1) a first metal pillar provided on a face of the first interconnect layer on a side opposite to the first electrode; e2) a second metal pillar provided on a face of the second interconnect layer on a side opposite to the second electrode; f) a second insulating layer provided between a side face of the first metal pillar and a side face of the second metal pillar; and g) a fluorescent layer provided on the first major surface side without a substrate between the first major surface and the fluorescent layer; wherein d21) a portion of the second interconnect layer extends to a portion facing the light emitting layer on the first insulating layer so as to overlay with a portion of the light emitting layer in the plan view; wherein h) a connecting area between the first interconnect layer and the first electrode is greater than a connecting area between the second interconnect layer and the second electrode; wherein h1) there are provided a number of first and second openings and the number of first openings is larger than a number of the second openings. a) a semiconductor layer including a first major surface, a second major surface opposite to the first major surface, and a light emitting layer, the semiconductor layer not including a substrate on the first major surface side; b1) a first electrode provided on a region including the light emitting layer on the second major surface; b2) a second electrode provided on the second major surface and at least partially interposed in the first electrode in a plan view; c) a first insulating layer provided on the second major surface side of the semiconductor layer, and covering a side surface continuing from the first major surface of the semiconductor layer; d1) a first interconnect layer provided on the first insulating layer on a side opposite to the semiconductor layer, the first interconnect layer provided in a first opening formed in the first insulating layer reaching the first electrode, and the first interconnect layer connected to the first electrode; d2) a second interconnect layer provided on the first insulating layer on the side opposite to the semiconductor layer, the second interconnect layer provided in a second opening formed in the first insulating layer reaching the second electrode, and the second interconnect layer connected to the second electrode; e1) a first metal pillar provided on a face of the first interconnect layer on a side opposite to the first electrode; e2) a second metal pillar provided on a face of the second interconnect layer on a side opposite to the second electrode; f) a second insulating layer provided between a side face of the first metal pillar and a side face of the second metal pillar; and g) a fluorescent layer provided on the first major surface side without a substrate between the first major surface and the fluorescent layer; wherein d21) a portion of the second interconnect layer extends to a portion facing the light emitting layer on the first insulating layer so as to overlay with a portion of the light emitting layer in the plan view; wherein h) a connecting area between the first interconnect layer and the first electrode is greater than a connecting area between the second interconnect layer and the second electrode; wherein h1) there are provided a number of first and second openings and the number of first openings is larger than a number of the second openings.