A sensing circuit for use in a memory device, comprising: a first circuit block coupled to a selected memory cell, wherein the first circuit block comprises a current source, a cascoding sensing N-LDE2 transistor, a bitline clamp N-LDE2 transistor, and a diode connected sensing load P-LDE1 transistor; a second circuit block coupled to a reference memory cell, wherein the second circuit block comprises a current source, a reference bitline clamp N-LDE2 transistor, a cascoding sensing N-LDE2 transistor, and a diode connected sensing load P-LDE1 transistor; and a third circuit block coupled to the first circuit block and second circuit block to generate an output indicating the data stored in the selected memory cell, wherein the third circuit block comprises input differential pair N-LDE2 transistors (131, 135), current mirror load P-LDE2 transistors (132, 133), output P-LDE2 transistor, current bias N-LDE2 transistor, and output current bias N-LDE2 transistor; wherein each P-LDE1 transistor is a PMOS transistor comprising a gate whose edge is 0.6-1.0 μm away from the edge of the nearest shallow trench isolation area and an STI area of width 1.9-2.0 μm, and wherein each P-LDE1 transistor was manufactured with a well spacing of 1.0-2.0 μm to its drain and a well spacing of 1.0-2.0 μm to its source; wherein each N-LDE2 transistor is an NMOS transistor comprising a gate whose edge is 2-4 μm away from the edge of the nearest shallow trench isolation area and an STI area of width 0.2-0.3 μm, and wherein each N-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source; and wherein each P-LDE2 transistor is a PMOS transistor comprising a gate whose edge is 0.6-1.0 μm away from the edge of the nearest shallow trench isolation area and an STI area of width 1.9-2.0 μm, and wherein each P-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source. a first circuit block coupled to a selected memory cell, wherein the first circuit block comprises a current source, a cascoding sensing N-LDE2 transistor, a bitline clamp N-LDE2 transistor, and a diode connected sensing load P-LDE1 transistor; a second circuit block coupled to a reference memory cell, wherein the second circuit block comprises a current source, a reference bitline clamp N-LDE2 transistor, a cascoding sensing N-LDE2 transistor, and a diode connected sensing load P-LDE1 transistor; and a third circuit block coupled to the first circuit block and second circuit block to generate an output indicating the data stored in the selected memory cell, wherein the third circuit block comprises input differential pair N-LDE2 transistors (131, 135), current mirror load P-LDE2 transistors (132, 133), output P-LDE2 transistor, current bias N-LDE2 transistor, and output current bias N-LDE2 transistor; wherein each P-LDE1 transistor is a PMOS transistor comprising a gate whose edge is 0.6-1.0 μm away from the edge of the nearest shallow trench isolation area and an STI area of width 1.9-2.0 μm, and wherein each P-LDE1 transistor was manufactured with a well spacing of 1.0-2.0 μm to its drain and a well spacing of 1.0-2.0 μm to its source; wherein each N-LDE2 transistor is an NMOS transistor comprising a gate whose edge is 2-4 μm away from the edge of the nearest shallow trench isolation area and an STI area of width 0.2-0.3 μm, and wherein each N-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source; and wherein each P-LDE2 transistor is a PMOS transistor comprising a gate whose edge is 0.6-1.0 μm away from the edge of the nearest shallow trench isolation area and an STI area of width 1.9-2.0 μm, and wherein each P-LDE2 transistor was manufactured with a well spacing of 0.5-0.6 μm to its drain and a well spacing of 1.0-2.0 μm to its source.