A memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases, wherein each memory location of the memory is capable of being assigned to any one of a plurality of alias address zones each accessible using a corresponding address alias among the plurality of address aliases; means for extracting a first address alias of said plurality of address aliases from an address associated with a first read operation of a first memory location in the memory, wherein the first memory location stores a first data value (DATA 1) and a first marker (MARKER 1); and a verification circuit configured: - to receive (401, 501), in relation with the first read operation, the first address alias; - to verify (402, 502), based on rules stored by the verification circuit defining access rights of the processing device using a current access type of the processing device corresponding to a current operating mode of the processing device, that the processing device is permitted to read the memory using the first address alias; and if is determined that access is permitted by the current access type of the processing device, the verification circuit is configured: - to receive, during the first read operation, the first marker stored at the first memory location, wherein the first marker indicates an address alias stored during a first write operation of the first data value; and - to verify, based on the first marker and on the first address alias, that the processing device is permitted to use the first data value. a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases, wherein each memory location of the memory is capable of being assigned to any one of a plurality of alias address zones each accessible using a corresponding address alias among the plurality of address aliases; means for extracting a first address alias of said plurality of address aliases from an address associated with a first read operation of a first memory location in the memory, wherein the first memory location stores a first data value (DATA 1) and a first marker (MARKER 1); and a verification circuit configured: - to receive (401, 501), in relation with the first read operation, the first address alias; - to verify (402, 502), based on rules stored by the verification circuit defining access rights of the processing device using a current access type of the processing device corresponding to a current operating mode of the processing device, that the processing device is permitted to read the memory using the first address alias; and if is determined that access is permitted by the current access type of the processing device, the verification circuit is configured: - to receive, during the first read operation, the first marker stored at the first memory location, wherein the first marker indicates an address alias stored during a first write operation of the first data value; and - to verify, based on the first marker and on the first address alias, that the processing device is permitted to use the first data value. - to receive (401, 501), in relation with the first read operation, the first address alias; - to verify (402, 502), based on rules stored by the verification circuit defining access rights of the processing device using a current access type of the processing device corresponding to a current operating mode of the processing device, that the processing device is permitted to read the memory using the first address alias; and if is determined that access is permitted by the current access type of the processing device, the verification circuit is configured: - to receive, during the first read operation, the first marker stored at the first memory location, wherein the first marker indicates an address alias stored during a first write operation of the first data value; and - to verify, based on the first marker and on the first address alias, that the processing device is permitted to use the first data value.