A display device comprising: a thin film transistor including a gate connected to a gate line, a drain connected to a data line, and a source connected to a pixel electrode; and a passivation layer pattern (PAC; PASO) formed in an opening of a pixel, except the thin film transistor and a peripheral area of the thin film transistor, wherein the pixel electrode directly contacts the source of the thin film transistor on the gate of the thin film transistor or the gate line; further comprising: a contact electrode, configured to be supplied with a common voltage; a first oxide semiconductor pattern disposed in a channel region of the thin film transistor, the first oxide semiconductor pattern configured to contact the data line and the source and the drain of the thin film transistor; a second oxide semiconductor pattern configured to contact the contact electrode; and an insulator including an insulating pattern covering a portion of the first oxide semiconductor pattern and an insulating pattern covering a portion of the second oxide semiconductor pattern; wherein the pixel electrode overlaps the second oxide semiconductor pattern on the insulator; wherein a portion of the first oxide semiconductor pattern not covered by the insulator is metallized and so has a sheet resistance lower than the portion of the first oxide semiconductor pattern covered by the insulator, wherein the metallized portion of the first oxide semiconductor pattern serves as a source contact area and a drain contact area of the thin film transistor, and wherein a portion of the second oxide semiconductor pattern not covered by the insulator is metallized and so has a sheet resistance lower than the portion of the second oxide semiconductor pattern covered by the insulator, wherein the metallized portion of the second oxide semiconductor pattern serves as a common electrode of the display device. a thin film transistor including a gate connected to a gate line, a drain connected to a data line, and a source connected to a pixel electrode; and a passivation layer pattern (PAC; PASO) formed in an opening of a pixel, except the thin film transistor and a peripheral area of the thin film transistor, wherein the pixel electrode directly contacts the source of the thin film transistor on the gate of the thin film transistor or the gate line; further comprising: a contact electrode, configured to be supplied with a common voltage; a first oxide semiconductor pattern disposed in a channel region of the thin film transistor, the first oxide semiconductor pattern configured to contact the data line and the source and the drain of the thin film transistor; a second oxide semiconductor pattern configured to contact the contact electrode; and an insulator including an insulating pattern covering a portion of the first oxide semiconductor pattern and an insulating pattern covering a portion of the second oxide semiconductor pattern; a contact electrode, configured to be supplied with a common voltage; a first oxide semiconductor pattern disposed in a channel region of the thin film transistor, the first oxide semiconductor pattern configured to contact the data line and the source and the drain of the thin film transistor; a second oxide semiconductor pattern configured to contact the contact electrode; and an insulator including an insulating pattern covering a portion of the first oxide semiconductor pattern and an insulating pattern covering a portion of the second oxide semiconductor pattern; wherein the pixel electrode overlaps the second oxide semiconductor pattern on the insulator; wherein a portion of the first oxide semiconductor pattern not covered by the insulator is metallized and so has a sheet resistance lower than the portion of the first oxide semiconductor pattern covered by the insulator, wherein the metallized portion of the first oxide semiconductor pattern serves as a source contact area and a drain contact area of the thin film transistor, and wherein a portion of the second oxide semiconductor pattern not covered by the insulator is metallized and so has a sheet resistance lower than the portion of the second oxide semiconductor pattern covered by the insulator, wherein the metallized portion of the second oxide semiconductor pattern serves as a common electrode of the display device.