A postal security device for processing requests for evidence of postage payment comprising a primary single integrated circuit including: a postal security device processor for processing the requests for evidence of postage payment; a plurality of non-volatile memory registers operatively connected to the postal security device processor for storing postal funds record data; a primary bus and control circuit operatively connecting the postal security device processor to the non-volatile memory registers for read and write access; a secondary memory access device operatively connected to the non-volatile memory registers to provide read only access to the plurality of non-volatile memory registers, wherein: the secondary memory access device comprises a state machine and bus multiplexor and a write disable circuit; a first clock circuit for providing clock signals to the postal security device processor, the plurality of non-volatile memory registers, and the primary bus and control circuit; a second clock circuit for providing clock signals to the secondary memory access device and alternatively providing clock signals to the plurality of non-volatile memory registers; and the state machine being arranged to erase cryptographic keys from secure memory locations before providing read only access to the plurality of non-volatile memory registers. a postal security device processor for processing the requests for evidence of postage payment; a plurality of non-volatile memory registers operatively connected to the postal security device processor for storing postal funds record data; a primary bus and control circuit operatively connecting the postal security device processor to the non-volatile memory registers for read and write access; a secondary memory access device operatively connected to the non-volatile memory registers to provide read only access to the plurality of non-volatile memory registers, wherein: the secondary memory access device comprises a state machine and bus multiplexor and a write disable circuit; a first clock circuit for providing clock signals to the postal security device processor, the plurality of non-volatile memory registers, and the primary bus and control circuit; a second clock circuit for providing clock signals to the secondary memory access device and alternatively providing clock signals to the plurality of non-volatile memory registers; and the state machine being arranged to erase cryptographic keys from secure memory locations before providing read only access to the plurality of non-volatile memory registers. the secondary memory access device comprises a state machine and bus multiplexor and a write disable circuit; a first clock circuit for providing clock signals to the postal security device processor, the plurality of non-volatile memory registers, and the primary bus and control circuit; a second clock circuit for providing clock signals to the secondary memory access device and alternatively providing clock signals to the plurality of non-volatile memory registers; and the state machine being arranged to erase cryptographic keys from secure memory locations before providing read only access to the plurality of non-volatile memory registers.