A programmable logic device comprising: a plurality of Complex Logic Blocks, CLBs, arranged in rows and columns of an array; a plurality of inter-CLB lines interconnecting the plurality of CLBs; wherein each of the plurality of CLBs comprises a first slice and a second slice, wherein the first slices in a first one of the columns are interconnected with each other via a first carry chain and the second slices in a second one of the columns are interconnected with each other via a second carry chain and wherein the first slice and the second slice each contain one or more logic cells, wherein one of the logic cells includes: - a Look Up Table for implementing logic functions on a first set of at least two inputs provided to the one of the logic cells; and - a second Look Up Table for implementing logic functions on a second set of at least two inputs provided to the one of the logic cells, wherein the first set and the second set have at least one uncommon signal (D2A, D2B); and - a Look Up Table output multiplexer configured to receive outputs of the first and the second Look Up Tables and a control input for controlling an output of the Look Up Table output multiplexer; - an arithmetic logic unit configured to implement arithmetic logic functions; - a first output multiplexer; - a second output multiplexer and - an output register connected to the second output multiplexer for generating a registered output from an input selected by the second output multiplexer; and - a swap multiplexer; characterized in that the output register is adapted to provide its registered output as a feedback signal from the output register to the swap multiplexer and wherein the swap multiplexer is configured to selectively provide either the register feedback signal or an input of the second set to the second Look Up Table. a plurality of Complex Logic Blocks, CLBs, arranged in rows and columns of an array; a plurality of inter-CLB lines interconnecting the plurality of CLBs; wherein each of the plurality of CLBs comprises a first slice and a second slice, wherein the first slices in a first one of the columns are interconnected with each other via a first carry chain and the second slices in a second one of the columns are interconnected with each other via a second carry chain and wherein the first slice and the second slice each contain one or more logic cells, wherein one of the logic cells includes: - a Look Up Table for implementing logic functions on a first set of at least two inputs provided to the one of the logic cells; and - a second Look Up Table for implementing logic functions on a second set of at least two inputs provided to the one of the logic cells, wherein the first set and the second set have at least one uncommon signal (D2A, D2B); and - a Look Up Table output multiplexer configured to receive outputs of the first and the second Look Up Tables and a control input for controlling an output of the Look Up Table output multiplexer; - an arithmetic logic unit configured to implement arithmetic logic functions; - a first output multiplexer; - a second output multiplexer and - an output register connected to the second output multiplexer for generating a registered output from an input selected by the second output multiplexer; and - a swap multiplexer; - a Look Up Table for implementing logic functions on a first set of at least two inputs provided to the one of the logic cells; and - a second Look Up Table for implementing logic functions on a second set of at least two inputs provided to the one of the logic cells, wherein the first set and the second set have at least one uncommon signal (D2A, D2B); and - a Look Up Table output multiplexer configured to receive outputs of the first and the second Look Up Tables and a control input for controlling an output of the Look Up Table output multiplexer; - an arithmetic logic unit configured to implement arithmetic logic functions; - a first output multiplexer; - a second output multiplexer and - an output register connected to the second output multiplexer for generating a registered output from an input selected by the second output multiplexer; and - a swap multiplexer;