A chip comprising a substrate having a first surface and a second surface opposite the first surface; an integrated circuit mounted on a landing zone on the first surface of the substrate, the landing zone defining a landing zone region of the substrate being surrounded by a peripheral region of the substrate; a plurality of electrical contacts provided about the first surface in the peripheral region; a plurality of wire-bonds providing electrical connections between the integrated circuit and the plurality of electrical contacts; a plurality of solder ball connections provided in the peripheral region on the second surface; a plurality of connections provided in the substrate for connecting the electrical contacts on the first surface with the solder ball connections on the second surface; wherein the substrate comprises at least one conductive track routed through the landing zone region of the substrate, wherein the at least one conductive track provides an electrical connection to the integrated circuit which is required for the normal operation of the integrated circuit. characterized in that the chip is configured such that an alteration in the at least one conductive track prevents operation of the integrated circuit, wherein the at least one conductive track is a security track forming part of a security mechanism, wherein the security mechanism is configured to detect an interference with the integrity of the security track and in response to enable at least one counter measure, the security mechanism comprising: a signal transmitter on the integrated circuit for providing a signal to a first end of the security track; and a detection circuit connected to a second end of the security track for detecting an alteration to the signal, wherein the security mechanism further comprises a response circuit responsive to the detection circuit for causing the performance of the at least one counter measure and wherein the at least one countermeasure comprises resetting or disabling all or part of functionalities of the chip. a substrate having a first surface and a second surface opposite the first surface; an integrated circuit mounted on a landing zone on the first surface of the substrate, the landing zone defining a landing zone region of the substrate being surrounded by a peripheral region of the substrate; a plurality of electrical contacts provided about the first surface in the peripheral region; a plurality of wire-bonds providing electrical connections between the integrated circuit and the plurality of electrical contacts; a plurality of solder ball connections provided in the peripheral region on the second surface; a plurality of connections provided in the substrate for connecting the electrical contacts on the first surface with the solder ball connections on the second surface; wherein the substrate comprises at least one conductive track routed through the landing zone region of the substrate, wherein the at least one conductive track provides an electrical connection to the integrated circuit which is required for the normal operation of the integrated circuit. characterized in that the chip is configured such that an alteration in the at least one conductive track prevents operation of the integrated circuit, wherein the at least one conductive track is a security track forming part of a security mechanism, wherein the security mechanism is configured to detect an interference with the integrity of the security track and in response to enable at least one counter measure, the security mechanism comprising: a signal transmitter on the integrated circuit for providing a signal to a first end of the security track; and a detection circuit connected to a second end of the security track for detecting an alteration to the signal, a signal transmitter on the integrated circuit for providing a signal to a first end of the security track; and a detection circuit connected to a second end of the security track for detecting an alteration to the signal, wherein the security mechanism further comprises a response circuit responsive to the detection circuit for causing the performance of the at least one counter measure and wherein the at least one countermeasure comprises resetting or disabling all or part of functionalities of the chip.