An apparatus comprising: memory access circuitry to control access to data stored in a memory; and memory security circuitry to verify integrity of data stored in a protected memory region of the memory; wherein: the memory security circuitry is configured to maintain a main counter integrity tree comprising a plurality of nodes, each node specifying a plurality of counters associated with respective data blocks of the protected memory region, the plurality of nodes comprising at least one parent node for which at least one of the counters is associated with a data block storing a child node providing further counters of the main counter integrity tree, and at least one leaf node for which at least one of the counters is associated with a data block storing data other than the main counter integrity tree; in response to access to a target data block of the protected memory region, the memory security circuitry is configured to verify integrity of the target data block by comparing a stored authentication code associated with the target data block with a calculated authentication code generated based on the target data block and a target counter of the counter integrity tree which is associated with the target data block; and at least one of the nodes of the main counter integrity tree comprises a split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters; and in response to a size increase trigger event associated with a given split-counter node of the main counter integrity tree, the memory security circuitry is configured to increase a size of the minor counters of the given split-counter node and to allocate a subset of the minor counters of the given split-counter node in a corresponding split-counter node of at least one mirror counter integrity tree. memory access circuitry to control access to data stored in a memory; and memory security circuitry to verify integrity of data stored in a protected memory region of the memory; wherein: the memory security circuitry is configured to maintain a main counter integrity tree comprising a plurality of nodes, each node specifying a plurality of counters associated with respective data blocks of the protected memory region, the plurality of nodes comprising at least one parent node for which at least one of the counters is associated with a data block storing a child node providing further counters of the main counter integrity tree, and at least one leaf node for which at least one of the counters is associated with a data block storing data other than the main counter integrity tree; in response to access to a target data block of the protected memory region, the memory security circuitry is configured to verify integrity of the target data block by comparing a stored authentication code associated with the target data block with a calculated authentication code generated based on the target data block and a target counter of the counter integrity tree which is associated with the target data block; and at least one of the nodes of the main counter integrity tree comprises a split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters; and in response to a size increase trigger event associated with a given split-counter node of the main counter integrity tree, the memory security circuitry is configured to increase a size of the minor counters of the given split-counter node and to allocate a subset of the minor counters of the given split-counter node in a corresponding split-counter node of at least one mirror counter integrity tree. the memory security circuitry is configured to maintain a main counter integrity tree comprising a plurality of nodes, each node specifying a plurality of counters associated with respective data blocks of the protected memory region, the plurality of nodes comprising at least one parent node for which at least one of the counters is associated with a data block storing a child node providing further counters of the main counter integrity tree, and at least one leaf node for which at least one of the counters is associated with a data block storing data other than the main counter integrity tree; in response to access to a target data block of the protected memory region, the memory security circuitry is configured to verify integrity of the target data block by comparing a stored authentication code associated with the target data block with a calculated authentication code generated based on the target data block and a target counter of the counter integrity tree which is associated with the target data block; and at least one of the nodes of the main counter integrity tree comprises a split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters; and in response to a size increase trigger event associated with a given split-counter node of the main counter integrity tree, the memory security circuitry is configured to increase a size of the minor counters of the given split-counter node and to allocate a subset of the minor counters of the given split-counter node in a corresponding split-counter node of at least one mirror counter integrity tree.