A method for configuring an accelerator, wherein the method is performed by a server, wherein the server comprises a first service board, a second service board, and a switching board; the first service board comprising a master CPU, a network adapter, a first FPGA chip, wherein the first FPGA chip is connected to the network adapter using a serializer-deserializer, serdes, bus and the network adapter is connected to the master CPU using a PCIe bus, and wherein the first FPGA chip is connected to the switching board using a serdes bus; the second service board comprising a slave CPU, multiple accelerator hardware units 1-N, and at least one second FPGA chip, wherein the at least one second FPGA is connected to the slave CPU using a PCIe bus and the at least one second FPGA is connected to the multiple accelerator hardware units using a serdes bus, and wherein the at least one second FPGA chip is connected to the switching board using a serdes bus; wherein the master CPU is configured to control the slave CPU, the slave CPU is configured to load a basic logic function onto one or more accelerator hardware units to generate one or more bare accelerators, and the at least one second FPGA chip is configured to implement a network adapter function and a PCIe controller function, which are respectively responsible for data-plane and control plane communication of the one or more accelerator hardware units; the method comprising: determining, by the master CPU, a target service type and a target bare accelerator; determining, by the master CPU, a service logic function corresponding to the target service type; loading, by the slave CPU, the service logic function corresponding to the target service type for the target bare accelerator, to generate a target service accelerator, wherein the target service accelerator is capable of providing an acceleration service for a service of the target service type; and allocating, by the slave CPU, an identifier to the target service accelerator, and reporting the identifier of the target service accelerator to the master CPU; wherein the method further comprising: accelerating, by the server, the service of the target service type by using the path between the master CPU and the target bare accelerator via the network adapter, the first FPGA chip, the switching board, and the at least one second FPGA chip, whereby the slave CPU is bypassed. the first service board comprising a master CPU, a network adapter, a first FPGA chip, wherein the first FPGA chip is connected to the network adapter using a serializer-deserializer, serdes, bus and the network adapter is connected to the master CPU using a PCIe bus, and wherein the first FPGA chip is connected to the switching board using a serdes bus; the second service board comprising a slave CPU, multiple accelerator hardware units 1-N, and at least one second FPGA chip, wherein the at least one second FPGA is connected to the slave CPU using a PCIe bus and the at least one second FPGA is connected to the multiple accelerator hardware units using a serdes bus, and wherein the at least one second FPGA chip is connected to the switching board using a serdes bus; wherein the master CPU is configured to control the slave CPU, the slave CPU is configured to load a basic logic function onto one or more accelerator hardware units to generate one or more bare accelerators, and the at least one second FPGA chip is configured to implement a network adapter function and a PCIe controller function, which are respectively responsible for data-plane and control plane communication of the one or more accelerator hardware units; the method comprising: determining, by the master CPU, a target service type and a target bare accelerator; determining, by the master CPU, a service logic function corresponding to the target service type; loading, by the slave CPU, the service logic function corresponding to the target service type for the target bare accelerator, to generate a target service accelerator, wherein the target service accelerator is capable of providing an acceleration service for a service of the target service type; and allocating, by the slave CPU, an identifier to the target service accelerator, and reporting the identifier of the target service accelerator to the master CPU; determining, by the master CPU, a target service type and a target bare accelerator; determining, by the master CPU, a service logic function corresponding to the target service type; loading, by the slave CPU, the service logic function corresponding to the target service type for the target bare accelerator, to generate a target service accelerator, wherein the target service accelerator is capable of providing an acceleration service for a service of the target service type; and allocating, by the slave CPU, an identifier to the target service accelerator, and reporting the identifier of the target service accelerator to the master CPU; wherein the method further comprising: accelerating, by the server, the service of the target service type by using the path between the master CPU and the target bare accelerator via the network adapter, the first FPGA chip, the switching board, and the at least one second FPGA chip, whereby the slave CPU is bypassed.