A system that stores memory reordering hints into a processor trace, the system comprising: one or more processing units; a processor cache comprising a plurality of cache lines; and logic that is configured to perform at least the following while executing, at the one or more processing units, a plurality of machine code instructions: initiate execution of a particular machine code instruction that performs a load from a memory address into a register, wherein a particular cache line corresponds to the memory address; as a result of the load, logging the particular cache line, wherein logging comprises, based on initiation of the particular machine code instruction, initiate logging, into the processor trace, the particular cache line in the processor cache, including initiating logging of a value that corresponds to the memory address in connection with logging the particular cache line; after initiating logging of the particular cache line into the processor trace, and prior to committing the particular machine code instruction, detect an event affecting the particular cache line; the system characterized by: based on the detection, storing a reordering hint, wherein storing comprises, based at least on detecting the event affecting the particular cache line, initiate storing of the memory reordering hint into the processor trace, wherein the memory reordering hint comprises at least one of: how long ago the particular machine code instruction read from the particular cache line; whether or not the particular machine code instruction read a current value from the particular cache line; or an indication of which value the particular machine code instruction read from the particular cache. one or more processing units; a processor cache comprising a plurality of cache lines; and logic that is configured to perform at least the following while executing, at the one or more processing units, a plurality of machine code instructions: initiate execution of a particular machine code instruction that performs a load from a memory address into a register, wherein a particular cache line corresponds to the memory address; as a result of the load, logging the particular cache line, wherein logging comprises, based on initiation of the particular machine code instruction, initiate logging, into the processor trace, the particular cache line in the processor cache, including initiating logging of a value that corresponds to the memory address in connection with logging the particular cache line; after initiating logging of the particular cache line into the processor trace, and prior to committing the particular machine code instruction, detect an event affecting the particular cache line; the system characterized by: based on the detection, storing a reordering hint, wherein storing comprises, based at least on detecting the event affecting the particular cache line, initiate storing of the memory reordering hint into the processor trace, wherein the memory reordering hint comprises at least one of: how long ago the particular machine code instruction read from the particular cache line; whether or not the particular machine code instruction read a current value from the particular cache line; or an indication of which value the particular machine code instruction read from the particular cache. initiate execution of a particular machine code instruction that performs a load from a memory address into a register, wherein a particular cache line corresponds to the memory address; as a result of the load, logging the particular cache line, wherein logging comprises, based on initiation of the particular machine code instruction, initiate logging, into the processor trace, the particular cache line in the processor cache, including initiating logging of a value that corresponds to the memory address in connection with logging the particular cache line; after initiating logging of the particular cache line into the processor trace, and prior to committing the particular machine code instruction, detect an event affecting the particular cache line; the system characterized by: based on the detection, storing a reordering hint, wherein storing comprises, based at least on detecting the event affecting the particular cache line, initiate storing of the memory reordering hint into the processor trace, wherein the memory reordering hint comprises at least one of: how long ago the particular machine code instruction read from the particular cache line; whether or not the particular machine code instruction read a current value from the particular cache line; or an indication of which value the particular machine code instruction read from the particular cache. based on the detection, storing a reordering hint, wherein storing comprises, based at least on detecting the event affecting the particular cache line, initiate storing of the memory reordering hint into the processor trace, wherein the memory reordering hint comprises at least one of: how long ago the particular machine code instruction read from the particular cache line; whether or not the particular machine code instruction read a current value from the particular cache line; or an indication of which value the particular machine code instruction read from the particular cache. how long ago the particular machine code instruction read from the particular cache line; whether or not the particular machine code instruction read a current value from the particular cache line; or an indication of which value the particular machine code instruction read from the particular cache.