A disk drive system for a host device with a high power mode and a low power mode, the disk drive system comprising: a low power disk drive, LPDD; a high power disk drive, HPDD; a nonvolatile semiconductor memory interface; and a control module configured to communicate with the nonvolatile semiconductor memory interface, with the LPDD and the HPDD, wherein during a storing request for write data in the low power mode, the control module is configured to determine whether there is sufficient space available on the LPDD for the write data and to transfer the write data to the LPDD if sufficient space on the LPDD is available and to store the write data on the HPDD if insufficient space on the LPDD is available, wherein the LPDD and the HPDD are configured to communicate with the host device via the nonvolatile semiconductor memory interface, and wherein the nonvolatile semiconductor memory interface comprises a processor, a line cache connected with a flash memory, a buffer configured to store the write data from the control module, a buffer manager configured to control the buffer, the nonvolatile semiconductor memory interface further comprising an interface controller configured to communicate with the buffer manager, the nonvolatile semiconductor memory interface further comprising a circuit for track format generation and defect management, said circuit being connected with the buffer manager, wherein the interface controller comprises: a flash register in communication with a processor bus, the processor bus being connected i) between the line cache and the interface controller and ii) between the processor and the circuit for track format generation and defect management, wherein the flash register is configured to store commands programmed by the host device and the processor, the interface controller further comprising a flash first-in first-out wrapper, and a flash controller configured to communicate with a host semiconductor memory interface of the host device, the flash register, and the flash first-in-first-out wrapper, wherein the flash first-in-first-out wrapper is configured to generate control signals for transferring the buffer data to and receiving the buffer data from the buffer manager. a low power disk drive, LPDD; a high power disk drive, HPDD; a nonvolatile semiconductor memory interface; and a control module configured to communicate with the nonvolatile semiconductor memory interface, with the LPDD and the HPDD, wherein during a storing request for write data in the low power mode, the control module is configured to determine whether there is sufficient space available on the LPDD for the write data and to transfer the write data to the LPDD if sufficient space on the LPDD is available and to store the write data on the HPDD if insufficient space on the LPDD is available, wherein the LPDD and the HPDD are configured to communicate with the host device via the nonvolatile semiconductor memory interface, and wherein the nonvolatile semiconductor memory interface comprises a processor, a line cache connected with a flash memory, a buffer configured to store the write data from the control module, a buffer manager configured to control the buffer, the nonvolatile semiconductor memory interface further comprising an interface controller configured to communicate with the buffer manager, the nonvolatile semiconductor memory interface further comprising a circuit for track format generation and defect management, said circuit being connected with the buffer manager, wherein the interface controller comprises: a flash register in communication with a processor bus, the processor bus being connected i) between the line cache and the interface controller and ii) between the processor and the circuit for track format generation and defect management, wherein the flash register is configured to store commands programmed by the host device and the processor, the interface controller further comprising a flash first-in first-out wrapper, and a flash controller configured to communicate with a host semiconductor memory interface of the host device, the flash register, and the flash first-in-first-out wrapper, wherein the flash first-in-first-out wrapper is configured to generate control signals for transferring the buffer data to and receiving the buffer data from the buffer manager. a flash register in communication with a processor bus, the processor bus being connected i) between the line cache and the interface controller and ii) between the processor and the circuit for track format generation and defect management, wherein the flash register is configured to store commands programmed by the host device and the processor, the interface controller further comprising a flash first-in first-out wrapper, and a flash controller configured to communicate with a host semiconductor memory interface of the host device, the flash register, and the flash first-in-first-out wrapper, wherein the flash first-in-first-out wrapper is configured to generate control signals for transferring the buffer data to and receiving the buffer data from the buffer manager.