A radio frequency, RF, amplifier comprising: a transistor (120, 220) with a control terminal and first and second current carrying terminals; an output pre-match impedance conditioning shunt circuit coupled between the first current carrying terminal and a ground reference node, wherein the output pre-match impedance conditioning shunt circuit includes at least a first shunt inductive element (134, 134', 234, 434), a second shunt inductive element (135, 135', 235 435, 935, 935'), and a shunt capacitor (142, 142', 342, 442) coupled in series; wherein the first shunt inductive element (134, 134', 234, 434) comprises a plurality of bondwires coupled between the first current carrying terminal and the second shunt inductive element (135, 135', 235 435, 935, 935'), and the second shunt inductive element (135, 135', 235 435, 935, 935') comprises an integrated inductor coupled between the first shunt inductive element (134, 134', 234, 434) and a first terminal of the shunt capacitor (142, 142', 342, 442); and the shunt capacitor (142, 342, 442) is configured to provide capacitive harmonic control of an output of the transistor (120, 220); wherein the output pre-match impedance conditioning shunt circuit is configured to create an RF cold point node (168, 168', 468, 968) that functions as a virtual ground reference voltage for RF electrical signals between the second shunt inductive element (135, 135', 235 435, 935, 935') and the shunt capacitor (142, 142', 342, 442); wherein the output pre-match impedance conditioning shunt circuit is coupled to an envelope frequency termination circuit (149, 249) coupled between the RF cold point node (168, 168', 468, 968) and a ground reference node, and wherein the output pre-match impedance conditioning shunt circuit is configured to generate a 90° phase shift in the output of the transistor (120, 220) for use with an inverted Doherty architecture. a transistor (120, 220) with a control terminal and first and second current carrying terminals; an output pre-match impedance conditioning shunt circuit coupled between the first current carrying terminal and a ground reference node, wherein the output pre-match impedance conditioning shunt circuit includes at least a first shunt inductive element (134, 134', 234, 434), a second shunt inductive element (135, 135', 235 435, 935, 935'), and a shunt capacitor (142, 142', 342, 442) coupled in series; wherein the first shunt inductive element (134, 134', 234, 434) comprises a plurality of bondwires coupled between the first current carrying terminal and the second shunt inductive element (135, 135', 235 435, 935, 935'), and the second shunt inductive element (135, 135', 235 435, 935, 935') comprises an integrated inductor coupled between the first shunt inductive element (134, 134', 234, 434) and a first terminal of the shunt capacitor (142, 142', 342, 442); and the shunt capacitor (142, 342, 442) is configured to provide capacitive harmonic control of an output of the transistor (120, 220); wherein the output pre-match impedance conditioning shunt circuit is configured to create an RF cold point node (168, 168', 468, 968) that functions as a virtual ground reference voltage for RF electrical signals between the second shunt inductive element (135, 135', 235 435, 935, 935') and the shunt capacitor (142, 142', 342, 442); wherein the output pre-match impedance conditioning shunt circuit is coupled to an envelope frequency termination circuit (149, 249) coupled between the RF cold point node (168, 168', 468, 968) and a ground reference node, and wherein the output pre-match impedance conditioning shunt circuit is configured to generate a 90° phase shift in the output of the transistor (120, 220) for use with an inverted Doherty architecture.