A multiple-way cache memory configured to employ a set associative method, and to pass data to a processor according to a request from the processor, the multiple-way cache memory comprising: a plurality of blocks in each way, each of the blocks including a plurality of lines, each of the lines including: data, a tag having an entry address and a status bit including information indicating whether the tag is valid, and a line address indicating a position of the data and the tag; a storage unit configured to hold the ways divided into the blocks; an access-address acquiring unit configured to acquire an access address that includes: a line address of a position of the data requested by the processor and a tag comparison address; a cache hit detector configured to: determine which one block of any of the ways is enabled, based on: a mode signal indicating either a first mode of use of a cache capacity or a second mode of use of the cache capacity, and the status bit of the tag, of said one block of any of the ways, that corresponds to the line address of the acquired access address, and determine whether the data requested by the processor has been hit, based on: the determination of which one block of any of the ways is enabled, and a comparison between the tag comparison address and the entry address of the tag, of said one block of any of the ways, that corresponds to the line address of the acquired access address, wherein the first mode of use is to use the entire cache capacity in which a head bit of the entry address of the tag of said one block of any of the ways corresponds to an uppermost bit of the entry address, and a head bit of the tag comparison address of the access address corresponds to the uppermost bit of the tag comparison address, and wherein the second mode of use is to condense the cache capacity in a line direction in which a last bit of the entry address of the tag of said one block of any of the ways corresponds to the uppermost bit of the entry address, and a last bit of the tag comparison address of the access address corresponds to the uppermost bit of the tag comparison address. a plurality of blocks in each way, each of the blocks including a plurality of lines, each of the lines including: data, a tag having an entry address and a status bit including information indicating whether the tag is valid, and a line address indicating a position of the data and the tag; a storage unit configured to hold the ways divided into the blocks; an access-address acquiring unit configured to acquire an access address that includes: a line address of a position of the data requested by the processor and a tag comparison address; a cache hit detector configured to: determine which one block of any of the ways is enabled, based on: a mode signal indicating either a first mode of use of a cache capacity or a second mode of use of the cache capacity, and the status bit of the tag, of said one block of any of the ways, that corresponds to the line address of the acquired access address, and determine whether the data requested by the processor has been hit, based on: the determination of which one block of any of the ways is enabled, and determine which one block of any of the ways is enabled, based on: a mode signal indicating either a first mode of use of a cache capacity or a second mode of use of the cache capacity, and the status bit of the tag, of said one block of any of the ways, that corresponds to the line address of the acquired access address, and a mode signal indicating either a first mode of use of a cache capacity or a second mode of use of the cache capacity, and the status bit of the tag, of said one block of any of the ways, that corresponds to the line address of the acquired access address, and determine whether the data requested by the processor has been hit, based on: the determination of which one block of any of the ways is enabled, and the determination of which one block of any of the ways is enabled, and a comparison between the tag comparison address and the entry address of the tag, of said one block of any of the ways, that corresponds to the line address of the acquired access address, wherein the first mode of use is to use the entire cache capacity in which a head bit of the entry address of the tag of said one block of any of the ways corresponds to an uppermost bit of the entry address, and a head bit of the tag comparison address of the access address corresponds to the uppermost bit of the tag comparison address, and wherein the second mode of use is to condense the cache capacity in a line direction in which a last bit of the entry address of the tag of said one block of any of the ways corresponds to the uppermost bit of the entry address, and a last bit of the tag comparison address of the access address corresponds to the uppermost bit of the tag comparison address.