A memory array (230, 330), comprising: a first address space (131, 231, 331) comprising memory cells (270, 370) coupled to a first number of select lines (204-2,..., 204-N, 304-2,..., 304-N) and to a number of sense lines (205, 305); and a second address space (132, 232, 332) comprising memory cells (270, 370) coupled to a second number of select lines (204-0, 204-1, 304-0, 304-1) and to the number of sense lines (205, 305), wherein the memory cells (270, 370) of the first address space (131, 231, 331) and the second address space (132, 232, 332) have a same memory cell structure; wherein: the first address space (131, 231, 331) is independently addressable relative to the second address space (132, 232, 332); a compute component is coupled to the number of sense lines (205, 305) and the second address space (132, 232, 332) is used as temporary storage for the compute component; the first number of select lines (204-2,..., 204-N, 304-2,..., 304-N) are coupled to a decoder (146, 246, 346) and the second number of select lines (204-0, 204-1, 304-0, 304-1) are coupled directly to an address circuitry (142, 242, 342); the address circuitry (142, 242, 342) is configured to receive an address associated with the second address space (132, 232, 332) and activate at least a select line of the second number of select lines (204-0, 204-1, 304-0, 304-1) without decoding the address associated with the second address space (132, 232, 332); and the second number of select lines (204-0, 204-1, 304-0, 304-1) are activatable simultaneously along with one of the first number of select lines (204-2,..., 204-N, 304-2,..., 304-N). a first address space (131, 231, 331) comprising memory cells (270, 370) coupled to a first number of select lines (204-2,..., 204-N, 304-2,..., 304-N) and to a number of sense lines (205, 305); and a second address space (132, 232, 332) comprising memory cells (270, 370) coupled to a second number of select lines (204-0, 204-1, 304-0, 304-1) and to the number of sense lines (205, 305), wherein the memory cells (270, 370) of the first address space (131, 231, 331) and the second address space (132, 232, 332) have a same memory cell structure; wherein: the first address space (131, 231, 331) is independently addressable relative to the second address space (132, 232, 332); a compute component is coupled to the number of sense lines (205, 305) and the second address space (132, 232, 332) is used as temporary storage for the compute component; the first number of select lines (204-2,..., 204-N, 304-2,..., 304-N) are coupled to a decoder (146, 246, 346) and the second number of select lines (204-0, 204-1, 304-0, 304-1) are coupled directly to an address circuitry (142, 242, 342); the address circuitry (142, 242, 342) is configured to receive an address associated with the second address space (132, 232, 332) and activate at least a select line of the second number of select lines (204-0, 204-1, 304-0, 304-1) without decoding the address associated with the second address space (132, 232, 332); and the second number of select lines (204-0, 204-1, 304-0, 304-1) are activatable simultaneously along with one of the first number of select lines (204-2,..., 204-N, 304-2,..., 304-N). the first address space (131, 231, 331) is independently addressable relative to the second address space (132, 232, 332); a compute component is coupled to the number of sense lines (205, 305) and the second address space (132, 232, 332) is used as temporary storage for the compute component; the first number of select lines (204-2,..., 204-N, 304-2,..., 304-N) are coupled to a decoder (146, 246, 346) and the second number of select lines (204-0, 204-1, 304-0, 304-1) are coupled directly to an address circuitry (142, 242, 342); the address circuitry (142, 242, 342) is configured to receive an address associated with the second address space (132, 232, 332) and activate at least a select line of the second number of select lines (204-0, 204-1, 304-0, 304-1) without decoding the address associated with the second address space (132, 232, 332); and the second number of select lines (204-0, 204-1, 304-0, 304-1) are activatable simultaneously along with one of the first number of select lines (204-2,..., 204-N, 304-2,..., 304-N).