An apparatus comprising: a plurality of multi-level output line drivers (140, 240, 340, 440), each multi-level output line driver (140, 240, 340, 440) of the plurality of multi-level output line drivers configured to generate a signal corresponding to a symbol of a codeword on a respective wire of a multi-wire bus, each multi-level output line driver (140, 240, 340, 440) comprising: a plurality of driver slices (500, 600) arranged in parallel, each driver slice (500, 600) having a digital driver input and a slice output wherein each driver slice (500, 600) comprises: a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and, for each resistive element, a voltage switching circuit (501, 502, 503) connected to the second end of the resistive element, the voltage switching circuit (501, 502, 503) configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit (501, 502, 503) being controlled by the digital driver input; an adjustable delay circuit configured to receive a transmit clock and to responsively generate a skew pre-compensated transmit clock having an offset with respect to at least one other skew pre-compensated transmit clock in a different multi-level output line driver (140, 240, 340, 440) of the plurality of multi-level output line drivers (140, 240, 340, 440); and a common output node connected to the plurality of driver slice outputs and the respective wire of the multi-wire bus. a plurality of driver slices (500, 600) arranged in parallel, each driver slice (500, 600) having a digital driver input and a slice output wherein each driver slice (500, 600) comprises: a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and, for each resistive element, a voltage switching circuit (501, 502, 503) connected to the second end of the resistive element, the voltage switching circuit (501, 502, 503) configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit (501, 502, 503) being controlled by the digital driver input; a plurality of resistive elements having a first and a second end, the first end of each of the resistive elements being connected to the driver slice output; and, for each resistive element, a voltage switching circuit (501, 502, 503) connected to the second end of the resistive element, the voltage switching circuit (501, 502, 503) configured to selectively couple the second end of the resistive element to a respective constant-voltage node in a group of at least two constant-voltage nodes, the voltage switching circuit (501, 502, 503) being controlled by the digital driver input; an adjustable delay circuit configured to receive a transmit clock and to responsively generate a skew pre-compensated transmit clock having an offset with respect to at least one other skew pre-compensated transmit clock in a different multi-level output line driver (140, 240, 340, 440) of the plurality of multi-level output line drivers (140, 240, 340, 440); and a common output node connected to the plurality of driver slice outputs and the respective wire of the multi-wire bus.