A method for forming a semiconductor device comprising a first field-effect transistor, FET, device and a second FET device, the method comprising: forming, on a semiconductor substrate, a first transistor structure and a second transistor structure separated by a trench, wherein each of the first and the second transistor structures comprises a plurality of stacked nanosheets (102a, 102b) forming a channel structure, and a source portion and a drain portion horizontally separated by said channel structure, and wherein a first spacer is formed in the trench at a sidewall of a first source/drain portion of the first transistor structure, and a second spacer is formed in the trench at a sidewall of a first source/drain portion of the second transistor structure, said first and second spacer both protruding above a top surface of the transistor structures; applying a first mask layer including an opening exposing the first spacer at the first source/drain portion of the first transistor structure and covering the second spacer; partially etching back the exposed first spacer through said opening, exposing a portion of the sidewall of the first source/drain portion of the first transistor structure; removing said mask layer; depositing a contact material over the transistor structures and the etched-back first spacer and the second spacer, thereby filling the trench and contacting the first source/drain portion of the first transistor structure; and etching back the contact material layer below a top surface of the second spacer. forming, on a semiconductor substrate, a first transistor structure and a second transistor structure separated by a trench, wherein each of the first and the second transistor structures comprises a plurality of stacked nanosheets (102a, 102b) forming a channel structure, and a source portion and a drain portion horizontally separated by said channel structure, and wherein a first spacer is formed in the trench at a sidewall of a first source/drain portion of the first transistor structure, and a second spacer is formed in the trench at a sidewall of a first source/drain portion of the second transistor structure, said first and second spacer both protruding above a top surface of the transistor structures; wherein each of the first and the second transistor structures comprises a plurality of stacked nanosheets (102a, 102b) forming a channel structure, and a source portion and a drain portion horizontally separated by said channel structure, and wherein a first spacer is formed in the trench at a sidewall of a first source/drain portion of the first transistor structure, and a second spacer is formed in the trench at a sidewall of a first source/drain portion of the second transistor structure, said first and second spacer both protruding above a top surface of the transistor structures; applying a first mask layer including an opening exposing the first spacer at the first source/drain portion of the first transistor structure and covering the second spacer; partially etching back the exposed first spacer through said opening, exposing a portion of the sidewall of the first source/drain portion of the first transistor structure; removing said mask layer; depositing a contact material over the transistor structures and the etched-back first spacer and the second spacer, thereby filling the trench and contacting the first source/drain portion of the first transistor structure; and etching back the contact material layer below a top surface of the second spacer.