A processing system comprising a positive supply terminal and a negative supply terminal configured to be connected to a supply voltage and a sub-circuit (50 1) comprising: - a transmission terminal; - a three-state driver circuit (502; 5060) comprising a first electronic switch connected between said transmission terminal and said positive supply terminal and a second electronic switch connected between said transmission terminal and said negative supply terminal, wherein said three-state driver circuit (502; 5060) comprises a combinational logic circuit (INV1, INV2, OR1; AND1) configured to monitor the logic levels of a first signal and a second signal (CTRL1), and selectively activate one of the following switching states as a function of the logic levels of said first signal and said second signal (CTRL1): - in a first switching state, connect said transmission terminal to said positive supply terminal by closing said first electronic switch, - in a second switching state, connect said transmission terminal to said negative supply terminal by closing said second electronic switch, and - in a third switching state, put said transmission terminal in a high-impedance state by opening said first electronic switch and said second electronic switch; - a CAN FD Light controller configured to sequentially transmit the bits of a CAN FD Light frame, wherein said CAN FD Light frame comprises: - a start-of-frame bit, - a sequence of bits (CD-EOF) comprising in sequence a Cyclic Redundancy Check, CRC, delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and - a plurality of intermediate bits (SID-CRC) between said start-of-frame bit and said CRC delimiter bit, and wherein, in a first operating mode (508; 5066), said CAN FD Light controller is configured to sequentially transmit the bits of said CAN FD Light frame by generating said first signal and said second signal (CTRL1) in response to a transmission clock signal (CLK 2) in order to: - transmit said start-of-frame bit by activating said second switching state for one clock cycle, - sequentially transmit said intermediate bits (SID-CRC) by sequentially selecting a bit of said intermediate bits (SID-CRC) and activating said first or said second switching state as a function of the logic level of the selected bit, and - once having transmitted said intermediate bits (SID-CRC), activate said third switching state. - a transmission terminal; - a three-state driver circuit (502; 5060) comprising a first electronic switch connected between said transmission terminal and said positive supply terminal and a second electronic switch connected between said transmission terminal and said negative supply terminal, wherein said three-state driver circuit (502; 5060) comprises a combinational logic circuit (INV1, INV2, OR1; AND1) configured to monitor the logic levels of a first signal and a second signal (CTRL1), and selectively activate one of the following switching states as a function of the logic levels of said first signal and said second signal (CTRL1): - in a first switching state, connect said transmission terminal to said positive supply terminal by closing said first electronic switch, - in a second switching state, connect said transmission terminal to said negative supply terminal by closing said second electronic switch, and - in a third switching state, put said transmission terminal in a high-impedance state by opening said first electronic switch and said second electronic switch; - a CAN FD Light controller configured to sequentially transmit the bits of a CAN FD Light frame, wherein said CAN FD Light frame comprises: - a start-of-frame bit, - a sequence of bits (CD-EOF) comprising in sequence a Cyclic Redundancy Check, CRC, delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and - a plurality of intermediate bits (SID-CRC) between said start-of-frame bit and said CRC delimiter bit, and - in a first switching state, connect said transmission terminal to said positive supply terminal by closing said first electronic switch, - in a second switching state, connect said transmission terminal to said negative supply terminal by closing said second electronic switch, and - in a third switching state, put said transmission terminal in a high-impedance state by opening said first electronic switch and said second electronic switch; - a CAN FD Light controller configured to sequentially transmit the bits of a CAN FD Light frame, wherein said CAN FD Light frame comprises: - a start-of-frame bit, - a sequence of bits (CD-EOF) comprising in sequence a Cyclic Redundancy Check, CRC, delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and - a plurality of intermediate bits (SID-CRC) between said start-of-frame bit and said CRC delimiter bit, and - a start-of-frame bit, - a sequence of bits (CD-EOF) comprising in sequence a Cyclic Redundancy Check, CRC, delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and - a plurality of intermediate bits (SID-CRC) between said start-of-frame bit and said CRC delimiter bit, and - transmit said start-of-frame bit by activating said second switching state for one clock cycle, - sequentially transmit said intermediate bits (SID-CRC) by sequentially selecting a bit of said intermediate bits (SID-CRC) and activating said first or said second switching state as a function of the logic level of the selected bit, and - once having transmitted said intermediate bits (SID-CRC), activate said third switching state.