A high-voltage semiconductor device, comprising: a semiconductor substrate having a first conductivity type; a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type; a second well region formed in a portion of the first well region, having the first conductivity type; a first gate structure (Gi) formed over a portion of the second well region and a portion of the first well region; a first doped region formed in a portion of the second well region, having the second conductivity type and functioning as a source; and a second doped region formed in a portion of the first well region, having the second conductivity type and functioning as a drain; and a second gate structure formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region; wherein the first gate structure comprises a first dielectric layer and a first conductive layer formed over the first dielectric layer, and the second gate structure comprises a second dielectric layer and a second conductive layer formed over the second dielectric layer, wherein second conductive layer preferably comprises polysilicon or metal; wherein the first gate structure and the second gate structure are combined to function as a combined gate; wherein the second gate structure covers 20 % -80 % of a top surface of the first gate structure (Gi); wherein the high-voltage semiconductor device further comprises a first conductive contact, a second conductive contact, and a first conductive line, wherein the first conductive contact is connected to the first conductive layer and to the first conductive line, and wherein the second conductive contact is connected to the second conductive layer and to the first conductive line, so that the second gate structure and the first gate structure thus form said combined gate and are provided with the same electrical potential in use. a semiconductor substrate having a first conductivity type; a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type; a second well region formed in a portion of the first well region, having the first conductivity type; a first gate structure (Gi) formed over a portion of the second well region and a portion of the first well region; a first doped region formed in a portion of the second well region, having the second conductivity type and functioning as a source; and a second doped region formed in a portion of the first well region, having the second conductivity type and functioning as a drain; and a second gate structure formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region; wherein the first gate structure comprises a first dielectric layer and a first conductive layer formed over the first dielectric layer, and the second gate structure comprises a second dielectric layer and a second conductive layer formed over the second dielectric layer, wherein second conductive layer preferably comprises polysilicon or metal; wherein the first gate structure and the second gate structure are combined to function as a combined gate; wherein the second gate structure covers 20 % -80 % of a top surface of the first gate structure (Gi); wherein the high-voltage semiconductor device further comprises a first conductive contact, a second conductive contact, and a first conductive line, wherein the first conductive contact is connected to the first conductive layer and to the first conductive line, and wherein the second conductive contact is connected to the second conductive layer and to the first conductive line, so that the second gate structure and the first gate structure thus form said combined gate and are provided with the same electrical potential in use.