3D stack of electronic chips comprising: - a first chip having on a first face a plurality of first interconnection pads of rectangular section, arranged in lines and in columns, the columns of first interconnection pads having a first pitch (P X1) in a first direction and the lines of first interconnection pads having a second pitch (P Y1) in a second direction perpendicular to the first direction; - a second chip having, on a second face bonded to the first face of the first chip, a plurality of second interconnection pads arranged in lines and in columns, the columns of second interconnection pads having a third pitch (P X2) in the first direction and the lines of second interconnection pads having a fourth pitch (P Y2) in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips; and wherein: - the first interconnection pads have a first dimension (A X1) in the first direction equal to m times the third pitch (P X2), where m is a non-zero natural integer, and a second dimension (A Y1) in the second direction equal to n times the fourth pitch (P Y2), where n is a non-zero natural integer; - the first interconnection pads belonging to a same line and to two consecutive columns are separated in the first direction by a first distance (D X1) equal to q times the third pitch (P X2), where q is a non-zero natural integer; - the first interconnection pads belonging to a same column and to two consecutive lines are separated in the second direction by a second distance (D Y1) equal to r times the fourth pitch (P Y2), where r is a non-zero natural integer; - the second interconnection pads are interconnected in a plurality of groups, each group comprising a number N of interconnected second interconnection pads such that: N = m + q n + r, each group being electrically connected to a first interconnection pad by at least one of the second interconnection pads of the group. - a first chip having on a first face a plurality of first interconnection pads of rectangular section, arranged in lines and in columns, the columns of first interconnection pads having a first pitch (P X1) in a first direction and the lines of first interconnection pads having a second pitch (P Y1) in a second direction perpendicular to the first direction; - a second chip having, on a second face bonded to the first face of the first chip, a plurality of second interconnection pads arranged in lines and in columns, the columns of second interconnection pads having a third pitch (P X2) in the first direction and the lines of second interconnection pads having a fourth pitch (P Y2) in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips; - the first interconnection pads have a first dimension (A X1) in the first direction equal to m times the third pitch (P X2), where m is a non-zero natural integer, and a second dimension (A Y1) in the second direction equal to n times the fourth pitch (P Y2), where n is a non-zero natural integer; - the first interconnection pads belonging to a same line and to two consecutive columns are separated in the first direction by a first distance (D X1) equal to q times the third pitch (P X2), where q is a non-zero natural integer; - the first interconnection pads belonging to a same column and to two consecutive lines are separated in the second direction by a second distance (D Y1) equal to r times the fourth pitch (P Y2), where r is a non-zero natural integer; - the second interconnection pads are interconnected in a plurality of groups, each group comprising a number N of interconnected second interconnection pads such that: N = m + q n + r, each group being electrically connected to a first interconnection pad by at least one of the second interconnection pads of the group.