An apparatus for performing a microcode patch from system memory, the apparatus comprising: a microcode ROM address bus, configured to provide a microcode ROM address (ADDR) of a location in a microcode ROM, said microcode ROM address indexing a micro instruction sequence that corresponds to a macro instruction; a patch array, configured to receive said microcode ROM address and to determine that said microcode ROM address matches one of a plurality of entries within said patch array, and configured to output a corresponding branch instruction and to assert a hit signal when said microcode ROM address matches; a mux, configured to receive said branch instruction from said patch array and a micro instruction corresponding to said microcode ROM address from said microcode ROM, and configured to provide said micro instruction or said corresponding branch instruction to an instruction register based upon the state of said hit signal, wherein said branch instruction prescribes a microcode branch target address; a RAM, configured to store an enable bypass sequence of micro instructions, wherein said enable bypass sequence is to be executed in place of said micro instruction, and wherein a first micro instruction in said enable bypass sequence is stored at a location in said RAM corresponding to said microcode branch target address, and wherein a last micro instruction in said enable bypass sequence prescribes a branch to a bypass location in the system memory, and wherein execution of said enable bypass sequence causes a microprocessor to enter bypass mode; and bypass logic, enabled when said microprocessor enters said bypass mode, and configured to detect wrapper instructions fetched from the system memory, to strip native instructions from within said wrapper instructions, and to provide said native instructions directly to a native instruction bus for execution. a microcode ROM address bus, configured to provide a microcode ROM address (ADDR) of a location in a microcode ROM, said microcode ROM address indexing a micro instruction sequence that corresponds to a macro instruction; a patch array, configured to receive said microcode ROM address and to determine that said microcode ROM address matches one of a plurality of entries within said patch array, and configured to output a corresponding branch instruction and to assert a hit signal when said microcode ROM address matches; a mux, configured to receive said branch instruction from said patch array and a micro instruction corresponding to said microcode ROM address from said microcode ROM, and configured to provide said micro instruction or said corresponding branch instruction to an instruction register based upon the state of said hit signal, wherein said branch instruction prescribes a microcode branch target address; a RAM, configured to store an enable bypass sequence of micro instructions, wherein said enable bypass sequence is to be executed in place of said micro instruction, and wherein a first micro instruction in said enable bypass sequence is stored at a location in said RAM corresponding to said microcode branch target address, and wherein a last micro instruction in said enable bypass sequence prescribes a branch to a bypass location in the system memory, and wherein execution of said enable bypass sequence causes a microprocessor to enter bypass mode; and bypass logic, enabled when said microprocessor enters said bypass mode, and configured to detect wrapper instructions fetched from the system memory, to strip native instructions from within said wrapper instructions, and to provide said native instructions directly to a native instruction bus for execution.