A matrix liquid crystal display having at least N rows and P columns, and comprising an image memory (MEMR) containing the luminance data for the pixels received for an image to be displayed, including data for each of M rows containing a non-zero image information item, M less than or equal to N, and a graphics processor (PRGR) that is capable of extracting from the memory the addresses of the M rows, and, for each of these, P luminance levels to be applied by P column conductors to the P pixels of the row, with a periodic duration T L for writing a row, and a high-voltage stage having N inputs and having N outputs that are each respectively connected to a respective row conductor that is common to the pixels of one and the same row of the matrix in order to allow the selection of a row of pixels for the purpose of writing luminance data to this row, the display being further characterized in that it comprises: N sampling and conversion circuits (E-C) having at least one common signal input to be sampled, this input receiving from the graphics processor a pattern of N successive binary words in the course of a duration T L, in which the binary words follow one another at a frequency F H that is equal to at least N/T L, for writing one row among the M rows, and in which the binary word of rank i in the succession has a first value if the row of rank i needs to be written and another value if not, the sampling and conversion circuits having sampling control inputs that are distinct from one another, the output of a sampling and conversion circuit of any rank i being connected to a corresponding input of rank i of the high-voltage stage and supplying this input with a voltage (VGon, VGoff) that is dependent on the binary word received, - a sampling control circuit that is actuated at the frequency F H in sync with the succession of binary words of rank i = 1 to N that are received at the common signal input of the sampling and conversion circuits, the sampling control circuit successively applying a sampling order to each of the N sampling control inputs of the sampling and conversion circuits, so as to sample and convert in the sampling and conversion circuit of rank i the binary word of rank i from the succession of N binary words, a control input of the high-voltage stage in order to apply to the N row conductors voltages corresponding to the voltages that are present on the outputs of the sampling and conversion circuits at the end of reception of the succession of N binary words, and in order to maintain these voltages over a duration that is necessary for writing a row. N sampling and conversion circuits (E-C) having at least one common signal input to be sampled, this input receiving from the graphics processor a pattern of N successive binary words in the course of a duration T L, in which the binary words follow one another at a frequency F H that is equal to at least N/T L, for writing one row among the M rows, and in which the binary word of rank i in the succession has a first value if the row of rank i needs to be written and another value if not, the sampling and conversion circuits having sampling control inputs that are distinct from one another, the output of a sampling and conversion circuit of any rank i being connected to a corresponding input of rank i of the high-voltage stage and supplying this input with a voltage (VGon, VGoff) that is dependent on the binary word received, - a sampling control circuit that is actuated at the frequency F H in sync with the succession of binary words of rank i = 1 to N that are received at the common signal input of the sampling and conversion circuits, the sampling control circuit successively applying a sampling order to each of the N sampling control inputs of the sampling and conversion circuits, so as to sample and convert in the sampling and conversion circuit of rank i the binary word of rank i from the succession of N binary words, a control input of the high-voltage stage in order to apply to the N row conductors voltages corresponding to the voltages that are present on the outputs of the sampling and conversion circuits at the end of reception of the succession of N binary words, and in order to maintain these voltages over a duration that is necessary for writing a row.