A test circuit, comprising: a plurality of test subcircuits respectively corresponding to a plurality of tested circuits, wherein the plurality of test subcircuits are configured to respectively connect the corresponding tested circuits to a test bus; a j th test subcircuit in the plurality of test subcircuits comprises Nj data distribution circuits and M first selectors, wherein Nj and M are both positive integers, M is equal to a bit width of the test bus, and M is greater than or equal to Nj; the j th test subcircuit is any one of the plurality of test subcircuits; in the j th test subcircuit, first input ends of the Nj data distribution circuits are respectively connected to Nj inputs of the test bus, first output ends of the Nj data distribution circuits are connected to a scan input channel of the tested circuit corresponding to the j th test subcircuit, and second input ends of the Nj data distribution circuits are connected to a scan output channel of the tested circuit corresponding to the j th test subcircuit; in the j th test subcircuit, output ends of the M first selectors are respectively connected to M outputs of the test bus; first input ends of Nj first selectors of the M first selectors are respectively connected to second output ends of the Nj data distribution circuits, and first input ends of remaining M - Nj first selectors are respectively connected to inputs of M - Nj test buses on which no data distribution circuit is disposed; second input ends of Nj first selectors of the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and second input ends of the remaining M - Nj first selectors are respectively connected to the inputs of the M - Nj test buses on which no data distribution circuit is disposed; and the test buses connected to the first input end and the second input end of each first selector are different. a plurality of test subcircuits respectively corresponding to a plurality of tested circuits, wherein the plurality of test subcircuits are configured to respectively connect the corresponding tested circuits to a test bus; a j th test subcircuit in the plurality of test subcircuits comprises Nj data distribution circuits and M first selectors, wherein Nj and M are both positive integers, M is equal to a bit width of the test bus, and M is greater than or equal to Nj; the j th test subcircuit is any one of the plurality of test subcircuits; in the j th test subcircuit, first input ends of the Nj data distribution circuits are respectively connected to Nj inputs of the test bus, first output ends of the Nj data distribution circuits are connected to a scan input channel of the tested circuit corresponding to the j th test subcircuit, and second input ends of the Nj data distribution circuits are connected to a scan output channel of the tested circuit corresponding to the j th test subcircuit; in the j th test subcircuit, output ends of the M first selectors are respectively connected to M outputs of the test bus; first input ends of Nj first selectors of the M first selectors are respectively connected to second output ends of the Nj data distribution circuits, and first input ends of remaining M - Nj first selectors are respectively connected to inputs of M - Nj test buses on which no data distribution circuit is disposed; second input ends of Nj first selectors of the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and second input ends of the remaining M - Nj first selectors are respectively connected to the inputs of the M - Nj test buses on which no data distribution circuit is disposed; and the test buses connected to the first input end and the second input end of each first selector are different.