A time-to-digital converter, TDC, comprising: a ring oscillator module configured to receive a sampling signal, an addressing signal, and a preset signal, the ring oscillator module includes: (i) a ring oscillator arranged with a plurality of inverters; (ii) a phase sampler configured to sample phase signals generated by the inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal; (iii) a counter clock generator configured to generate first and second clock signals, based on receipt of the sampling signal and respective phase signals generated by the first and last inverters of the ring oscillator; (iv) first and second counters (3030, 3032) configured to respectively generate first and second counter (3030, 3032) output signals, based on receipt of the first and second clock signals respectively; and (v) a data sampler configured to sample the first and second counter (3030, 3032) output signals to respectively generate second and third output signals; and a digital error correction module arranged to process the first, second and third output signals for generating a digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal by the TDC, wherein the ring oscillator is arranged to be operated between first and second modes on receipt of the preset signal, in which in the first mode, the ring oscillator is electrically switched on for a period corresponding to the time difference, and in the second mode, the ring oscillator is electrically switched off by presetting an inverter based on the addressing signal, which includes an identification of the inverter selected to be preset at each conversion cycle of the ring oscillator. a ring oscillator module configured to receive a sampling signal, an addressing signal, and a preset signal, the ring oscillator module includes: (i) a ring oscillator arranged with a plurality of inverters; (ii) a phase sampler configured to sample phase signals generated by the inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal; (iii) a counter clock generator configured to generate first and second clock signals, based on receipt of the sampling signal and respective phase signals generated by the first and last inverters of the ring oscillator; (iv) first and second counters (3030, 3032) configured to respectively generate first and second counter (3030, 3032) output signals, based on receipt of the first and second clock signals respectively; and (v) a data sampler configured to sample the first and second counter (3030, 3032) output signals to respectively generate second and third output signals; and (i) a ring oscillator arranged with a plurality of inverters; (ii) a phase sampler configured to sample phase signals generated by the inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal; (iii) a counter clock generator configured to generate first and second clock signals, based on receipt of the sampling signal and respective phase signals generated by the first and last inverters of the ring oscillator; (iv) first and second counters (3030, 3032) configured to respectively generate first and second counter (3030, 3032) output signals, based on receipt of the first and second clock signals respectively; and (v) a data sampler configured to sample the first and second counter (3030, 3032) output signals to respectively generate second and third output signals; and a digital error correction module arranged to process the first, second and third output signals for generating a digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal by the TDC, wherein the ring oscillator is arranged to be operated between first and second modes on receipt of the preset signal, in which in the first mode, the ring oscillator is electrically switched on for a period corresponding to the time difference, and in the second mode, the ring oscillator is electrically switched off by presetting an inverter based on the addressing signal, which includes an identification of the inverter selected to be preset at each conversion cycle of the ring oscillator.