An integrated circuit, comprising: a programmable circuitry operable according to a first clock frequency and configured by loading configuration data to extract search keys (815, 1010, 1110, 1210, 1310) from packets; a first memory block (205, 500, 700) comprising: a first memory element (210, 505, 705) having a data port; and a first memory processor (215, 510, 710) coupled to the data port of the first memory element and to the programmable circuitry; wherein the first memory processor and the data port of the first memory element are operable according to a second clock frequency that is higher than the first clock frequency; and wherein the first memory processor performs operations only in the first memory element; and a second memory block (205, 500, 700) comprising: a second memory element (210, 505, 705) having a data port; and a second memory processor (215, 510, 710) coupled to the data port of the second memory element and serially connected to the first memory processor through a hardwired connection (225, 230, 405) functional within the integrated circuit without loading the configuration data; wherein the second memory processor and the data port of the second memory element operate at the second clock frequency; and wherein the memory processor performs operations only in the second memory element; and wherein each of the first and the second memory blocks operates upon a portion of a search key obtained from the programmable circuitry. a programmable circuitry operable according to a first clock frequency and configured by loading configuration data to extract search keys (815, 1010, 1110, 1210, 1310) from packets; a first memory block (205, 500, 700) comprising: a first memory element (210, 505, 705) having a data port; and a first memory processor (215, 510, 710) coupled to the data port of the first memory element and to the programmable circuitry; wherein the first memory processor and the data port of the first memory element are operable according to a second clock frequency that is higher than the first clock frequency; and wherein the first memory processor performs operations only in the first memory element; and a first memory element (210, 505, 705) having a data port; and a first memory processor (215, 510, 710) coupled to the data port of the first memory element and to the programmable circuitry; a second memory block (205, 500, 700) comprising: a second memory element (210, 505, 705) having a data port; and a second memory processor (215, 510, 710) coupled to the data port of the second memory element and serially connected to the first memory processor through a hardwired connection (225, 230, 405) functional within the integrated circuit without loading the configuration data; wherein the second memory processor and the data port of the second memory element operate at the second clock frequency; and wherein the memory processor performs operations only in the second memory element; and a second memory element (210, 505, 705) having a data port; and a second memory processor (215, 510, 710) coupled to the data port of the second memory element and serially connected to the first memory processor through a hardwired connection (225, 230, 405) functional within the integrated circuit without loading the configuration data;