A self-biased amplifier circuit (100; 200), comprising: an input, wherein the input comprises a first (102; 202) and a second input node (104; 204) for receiving a first input signal and a second input signal forming a differential input signal, wherein the input comprises a first p-channel metal-oxide-semiconductor, PMOS, input transistor (110; 210) and a first n-channel metal-oxide-semiconductor, NMOS, input transistor (112; 212) forming two complementary input transistors at the first input node (102; 202) and each configured to receive the first input signal at a gate, and wherein the input comprises a second PMOS input transistor (114; 214) and a second NMOS input transistor (116; 216) forming two complementary input transistors at the second input node (104; 204) and each configured to receive the second input signal at a gate, wherein a drain of the first PMOS input transistor (110; 210) and a drain of the first NMOS input transistor (112; 212) are connected to each other to form an inverter defining a first output node (106; 206) therebetween and wherein a drain of the second PMOS input transistor (114; 214) and a drain of the second NMOS input transistor (116; 216) are connected to each other to form an inverter defining a second output node (108; 208) therebetween; at least one PMOS bias transistor (118, 120; 218) and at least one NMOS bias transistor (122, 124; 222), wherein a source of each of the first and the second PMOS input transistor (110, 114; 210, 214) is connected to a drain of the at least one PMOS bias transistor (118, 120; 218) and wherein a source of each of the first and the second NMOS input transistor (112, 116; 212, 216) is connected to a drain of the at least one NMOS bias transistor (122, 124; 222) for providing a bias current to the inverters; an output connected to at least one of the first output node (106; 206) and the second output node (108; 208) for providing an output signal; and characterized in that the self-biased amplifier circuit further comprises a first and a second transistor switch (126, 128; 226, 228), wherein the first transistor switch (126; 226) is connected between one of the first (106; 206) or the second output node (108; 208) and a gate of a first PMOS bias transistor of the at least one PMOS bias transistor (118, 120; 218), and wherein the second transistor switch (128; 228) is connected between said one of the first (106; 206) or the second output node (108; 208) and a gate of a first NMOS bias transistor of the at least one NMOS bias transistor (122, 124; 222), wherein the first and the second transistor switches (126, 128; 226, 228) are connected in series between the gate of the first PMOS bias transistor and the gate of the first NMOS bias transistor and configured to control the self-biased amplifier circuit (100; 200) to assume an active mode or a standby mode. an input, wherein the input comprises a first (102; 202) and a second input node (104; 204) for receiving a first input signal and a second input signal forming a differential input signal, wherein the input comprises a first p-channel metal-oxide-semiconductor, PMOS, input transistor (110; 210) and a first n-channel metal-oxide-semiconductor, NMOS, input transistor (112; 212) forming two complementary input transistors at the first input node (102; 202) and each configured to receive the first input signal at a gate, and wherein the input comprises a second PMOS input transistor (114; 214) and a second NMOS input transistor (116; 216) forming two complementary input transistors at the second input node (104; 204) and each configured to receive the second input signal at a gate, wherein a drain of the first PMOS input transistor (110; 210) and a drain of the first NMOS input transistor (112; 212) are connected to each other to form an inverter defining a first output node (106; 206) therebetween and wherein a drain of the second PMOS input transistor (114; 214) and a drain of the second NMOS input transistor (116; 216) are connected to each other to form an inverter defining a second output node (108; 208) therebetween; at least one PMOS bias transistor (118, 120; 218) and at least one NMOS bias transistor (122, 124; 222), wherein a source of each of the first and the second PMOS input transistor (110, 114; 210, 214) is connected to a drain of the at least one PMOS bias transistor (118, 120; 218) and wherein a source of each of the first and the second NMOS input transistor (112, 116; 212, 216) is connected to a drain of the at least one NMOS bias transistor (122, 124; 222) for providing a bias current to the inverters; an output connected to at least one of the first output node (106; 206) and the second output node (108; 208) for providing an output signal; and characterized in that the self-biased amplifier circuit further comprises a first and a second transistor switch (126, 128; 226, 228), wherein the first transistor switch (126; 226) is connected between one of the first (106; 206) or the second output node (108; 208) and a gate of a first PMOS bias transistor of the at least one PMOS bias transistor (118, 120; 218), and wherein the second transistor switch (128; 228) is connected between said one of the first (106; 206) or the second output node (108; 208) and a gate of a first NMOS bias transistor of the at least one NMOS bias transistor (122, 124; 222), wherein the first and the second transistor switches (126, 128; 226, 228) are connected in series between the gate of the first PMOS bias transistor and the gate of the first NMOS bias transistor and configured to control the self-biased amplifier circuit (100; 200) to assume an active mode or a standby mode.