A configurable circuit of a plurality of configurable circuits (200, 205), each configurable circuit comprising: a configurable computation circuit; a first memory circuit coupled to the configurable computation circuit; a plurality of synchronous network inputs comprising a plurality of input registers; a plurality of synchronous network outputs comprising a plurality of output registers; characterised by: the plurality of synchronous network outputs directly coupled through a synchronous network to the plurality of synchronous network inputs of adjacent configurable circuits of the plurality of configurable circuits; a second memory circuit coupled to the configurable computation circuit, to the synchronous network inputs, and to the synchronous network outputs; and a control circuit coupled to the configurable computation circuit, the control circuit comprising: a memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a plurality of thread identifiers, having a first, data completion count for each thread identifier of the plurality of thread identifiers, and for each thread identifier for a current thread of the plurality of thread identifiers, another thread identifier identifying a next thread for execution following execution of the current thread to provide ordered thread execution; and a thread control circuit adapted to self-schedule and queue a thread for execution when, for its thread identifier, its data completion count has decremented to zero to indicate completion of any data dependencies and its thread identifier is identified as the next thread. a configurable computation circuit; a first memory circuit coupled to the configurable computation circuit; a plurality of synchronous network inputs comprising a plurality of input registers; a plurality of synchronous network outputs comprising a plurality of output registers; the plurality of synchronous network outputs directly coupled through a synchronous network to the plurality of synchronous network inputs of adjacent configurable circuits of the plurality of configurable circuits; a second memory circuit coupled to the configurable computation circuit, to the synchronous network inputs, and to the synchronous network outputs; and a control circuit coupled to the configurable computation circuit, the control circuit comprising: a memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a plurality of thread identifiers, having a first, data completion count for each thread identifier of the plurality of thread identifiers, and for each thread identifier for a current thread of the plurality of thread identifiers, another thread identifier identifying a next thread for execution following execution of the current thread to provide ordered thread execution; and a thread control circuit adapted to self-schedule and queue a thread for execution when, for its thread identifier, its data completion count has decremented to zero to indicate completion of any data dependencies and its thread identifier is identified as the next thread. a memory control circuit; a plurality of control registers, wherein the plurality of control registers store a completion table having a plurality of thread identifiers, having a first, data completion count for each thread identifier of the plurality of thread identifiers, and for each thread identifier for a current thread of the plurality of thread identifiers, another thread identifier identifying a next thread for execution following execution of the current thread to provide ordered thread execution; and a thread control circuit adapted to self-schedule and queue a thread for execution when, for its thread identifier, its data completion count has decremented to zero to indicate completion of any data dependencies and its thread identifier is identified as the next thread.