A processor, comprising: a vector unit comprising: a vector register file comprising at least one vector register to hold a varying number of elements; and a length register file comprising: a first vector length register; and a second vector length register and an execution unit to: execute a first vector instruction comprising a first identifier representing the vector register and a second identifier representing the first vector length register storing a first value to specify a first number of operations applied to the varying number of elements, wherein the first number of operations is independent from a number of elements that the vector register is capable of packing therein; and responsive to executing the first vector instruction, execute a second vector instruction comprising the first identifier representing the vector register and a third identifier representing the second vector length register storing a second value to specify a second number of operations applied to the varying number of elements, wherein the second number of operations is independent from the number of elements that the vector register is capable of packing therein. a vector register file comprising at least one vector register to hold a varying number of elements; and a length register file comprising: a first vector length register; and a second vector length register and a first vector length register; and a second vector length register and an execution unit to: execute a first vector instruction comprising a first identifier representing the vector register and a second identifier representing the first vector length register storing a first value to specify a first number of operations applied to the varying number of elements, wherein the first number of operations is independent from a number of elements that the vector register is capable of packing therein; and responsive to executing the first vector instruction, execute a second vector instruction comprising the first identifier representing the vector register and a third identifier representing the second vector length register storing a second value to specify a second number of operations applied to the varying number of elements, wherein the second number of operations is independent from the number of elements that the vector register is capable of packing therein. execute a first vector instruction comprising a first identifier representing the vector register and a second identifier representing the first vector length register storing a first value to specify a first number of operations applied to the varying number of elements, wherein the first number of operations is independent from a number of elements that the vector register is capable of packing therein; and responsive to executing the first vector instruction, execute a second vector instruction comprising the first identifier representing the vector register and a third identifier representing the second vector length register storing a second value to specify a second number of operations applied to the varying number of elements, wherein the second number of operations is independent from the number of elements that the vector register is capable of packing therein.