A system comprising: a plurality of simultaneous multithreading, SMT, cores (100_1, 100_Q) to process instructions of multiple threads, each SMT core comprising: execution circuitry to execute instructions of a first thread and a second thread using first and second context data, respectively; and a plurality of registers to store the first and second context data; an integrated memory controller to couple the plurality of SMT cores to a system memory; an accelerator interface to couple the one or more cores to an accelerator circuit, wherein at least one of the first and second threads are to store information associated with work to be performed by the accelerator circuit in a region of the system memory accessible to the accelerator circuit; memory management circuitry to translate virtual addresses within a virtual address space shared by the plurality of SMT cores and the accelerator circuit, the virtual addresses to be translated to physical addresses of a system memory accessible by the SMT cores and the accelerator circuit, the memory management circuitry including a translation lookaside buffer, TLB, to be shared by the first and second threads to cache virtual-to-physical address translations to be used to access the system memory; logic circuitry to swap out first accelerator context data associated with the first thread for second accelerator context data associated with the second thread in response to a context switch from the first thread to the second thread; and wherein the information associated with work to be performed comprises one or more commands to be executed by the accelerator circuit, the commands to be identified using one or more virtual addresses within the virtual address space shared by the plurality of SMT cores and the accelerator circuit. execution circuitry to execute instructions of a first thread and a second thread using first and second context data, respectively; and a plurality of registers to store the first and second context data; an integrated memory controller to couple the plurality of SMT cores to a system memory; an accelerator interface to couple the one or more cores to an accelerator circuit, wherein at least one of the first and second threads are to store information associated with work to be performed by the accelerator circuit in a region of the system memory accessible to the accelerator circuit; memory management circuitry to translate virtual addresses within a virtual address space shared by the plurality of SMT cores and the accelerator circuit, the virtual addresses to be translated to physical addresses of a system memory accessible by the SMT cores and the accelerator circuit, the memory management circuitry including a translation lookaside buffer, TLB, to be shared by the first and second threads to cache virtual-to-physical address translations to be used to access the system memory; logic circuitry to swap out first accelerator context data associated with the first thread for second accelerator context data associated with the second thread in response to a context switch from the first thread to the second thread; and wherein the information associated with work to be performed comprises one or more commands to be executed by the accelerator circuit, the commands to be identified using one or more virtual addresses within the virtual address space shared by the plurality of SMT cores and the accelerator circuit.