A semiconductor memory cell (100, 102, 104, 200, 100R1, 100R2, 300, 400, 500 comprising: a bi-stable floating body transistor (40, 340, 440, 40D) comprising a first body (24, 324, 424); and an access device (42, 342, 442, 42A, 42B) comprising a second transistor having a second body (12, 12', 312, 424'); wherein said bi-stable floating body transistor and said access device are electrically connected in series, a substrate region (10, 310) underlying both of said first and second bodies; a buried well region (30, 330, 430) interposed between said substrate region and at least one of said first and second bodies; a first source region (16, 18, 316, 318, 18A, 18B) contacting said first body; a first drain region (16, 18, 316, 318, 18A, 18B) separated from said first source region and contacting said first body; a first gate (60, 360, 60A) insulated from said first body; an insulating member (26, 326) insulating said first body from said second body; a second source region (20, 20A, 20B, 20', 320) contacting said second body; a second drain region (22, 22A, 22B, 22', 322) separated from said second source region and contacting said second body; and a second gate (64, 364. 64A) insulated from said second body, a buried well terminal (78, 78a through 78n, 378, 478) which is electrically connected to the buried well region; and a substrate terminal (80, 80a through 80n, 380, 480) which is connected to the substrate region, wherein a holding operation on the memory cell is performed by applying a back bias to the buried well region through the buried well terminal or by applying a back bias to the substrate region through the substrate terminal. a bi-stable floating body transistor (40, 340, 440, 40D) comprising a first body (24, 324, 424); and an access device (42, 342, 442, 42A, 42B) comprising a second transistor having a second body (12, 12', 312, 424'); wherein said bi-stable floating body transistor and said access device are electrically connected in series, a substrate region (10, 310) underlying both of said first and second bodies; a buried well region (30, 330, 430) interposed between said substrate region and at least one of said first and second bodies; a first source region (16, 18, 316, 318, 18A, 18B) contacting said first body; a first drain region (16, 18, 316, 318, 18A, 18B) separated from said first source region and contacting said first body; a first gate (60, 360, 60A) insulated from said first body; an insulating member (26, 326) insulating said first body from said second body; a second source region (20, 20A, 20B, 20', 320) contacting said second body; a second drain region (22, 22A, 22B, 22', 322) separated from said second source region and contacting said second body; and a second gate (64, 364. 64A) insulated from said second body, a buried well terminal (78, 78a through 78n, 378, 478) which is electrically connected to the buried well region; and a substrate terminal (80, 80a through 80n, 380, 480) which is connected to the substrate region, wherein a holding operation on the memory cell is performed by applying a back bias to the buried well region through the buried well terminal or by applying a back bias to the substrate region through the substrate terminal.