A solid-state image sensor comprising: a differential amplifier circuit that amplifies a pair of differential input voltages and includes a signal-side amplifier transistor, a reference-side amplifier transistor and a constant current source, wherein the signal-side amplifier transistor is disposed in an effective pixel circuit and is configured to generate an output voltage (V 0) corresponding to a signal current (I s, I s ') corresponding to one of a pair of differential input voltages (V in_s), which is a voltage of a floating diffusion layer included in the effective pixel circuit, by supplying the signal current (I s, I s ') from an output node to a common-phase node, and wherein the signal-side amplifier transistor outputs a P-phase level as the output voltage (V 0) and then outputs a D-phase level that is different from the P-phase level as the output voltage (V 0); wherein the reference-side amplifier transistor is disposed in a dummy pixel circuit and is configured to supply a reference current (I r, I r ') corresponding to the other one of the pair of differential input voltages (V in_r), which is a voltage of a floating diffusion layer included in the dummy pixel circuit, to the common-phase node; wherein the constant current source is configured to constantly control a sum of the signal current (I s, I s ') and the reference current (I r, I r ') to be merged at the common-phase node; a bypass control unit configured to connect the output node and the common-phase node and supply the signal current (I s, I s ') having a value corresponding to a predetermined limit voltage (V clip_p, V clip_d) to the common-phase node in a case in which the output voltage (V 0) reaches the limit voltage (V clip_p, V clip_d), wherein the predetermined limit voltage (V clip_p, V clip_d) includes a P-phase limit voltage (V clip_p) that limits the P-phase level and a D-phase limit voltage (V clip_d) that limits the D-phase level, wherein the bypass control unit includes a bypass transistor having a source connected to the output node; and a signal processing unit configured to perform predetermined signal processing by reading a signal obtained by amplifying the pair of differential input voltages (V in_s, V in_r). a differential amplifier circuit that amplifies a pair of differential input voltages and includes a signal-side amplifier transistor, a reference-side amplifier transistor and a constant current source, wherein the signal-side amplifier transistor is disposed in an effective pixel circuit and is configured to generate an output voltage (V 0) corresponding to a signal current (I s, I s ') corresponding to one of a pair of differential input voltages (V in_s), which is a voltage of a floating diffusion layer included in the effective pixel circuit, by supplying the signal current (I s, I s ') from an output node to a common-phase node, and wherein the signal-side amplifier transistor outputs a P-phase level as the output voltage (V 0) and then outputs a D-phase level that is different from the P-phase level as the output voltage (V 0); wherein the reference-side amplifier transistor is disposed in a dummy pixel circuit and is configured to supply a reference current (I r, I r ') corresponding to the other one of the pair of differential input voltages (V in_r), which is a voltage of a floating diffusion layer included in the dummy pixel circuit, to the common-phase node; wherein the constant current source is configured to constantly control a sum of the signal current (I s, I s ') and the reference current (I r, I r ') to be merged at the common-phase node; a bypass control unit configured to connect the output node and the common-phase node and supply the signal current (I s, I s ') having a value corresponding to a predetermined limit voltage (V clip_p, V clip_d) to the common-phase node in a case in which the output voltage (V 0) reaches the limit voltage (V clip_p, V clip_d), wherein the predetermined limit voltage (V clip_p, V clip_d) includes a P-phase limit voltage (V clip_p) that limits the P-phase level and a D-phase limit voltage (V clip_d) that limits the D-phase level, wherein the bypass control unit includes a bypass transistor having a source connected to the output node; and a signal processing unit configured to perform predetermined signal processing by reading a signal obtained by amplifying the pair of differential input voltages (V in_s, V in_r).