An electronic device comprising: a semiconductor die; a pulse generation arrangement on the semiconductor die configured to generate first and second command signals (PWM1, PWM2); a driver arrangement on the semiconductor die configured to generate switch control signals (HG1, LG1) based on the command signals, the switch control signals comprising an output from the semiconductor die at an output interface (117, 119) and configured to control operation of switching circuitry that regulates current from/to at least a first node to/from an electrical load, the switching circuitry configured to couple to the output interface (117, 119); and wherein the driver arrangement comprises first driver circuitry to generate the first switch control signal based on the first command signal and second driver circuitry to generate the second switch control signal based on the second command signal; and a timer arrangement on the semiconductor die and coupled to the driver arrangement configured to measure a first time difference (tpdon1, tpdoff 1) between a first change in the first command signal and a corresponding response in the first switch control signal to the first change in the first command signal; and wherein the timer arrangement is coupled to the driver arrangement and further configured to measure a second time difference (tpdoff2, tpdon2) between a second change in the second command signal and a corresponding response to the second change, in the second switch control signal; a first register coupled to the timer arrangement and configured to store the first time difference (tpdon1, tpdoff1) and the second time difference (tpdoff2, tpdon2); and a second register configured to store a target dead time value (dt); and control circuitry coupled to the first and second registers configured to determine an offset for the first command signal and an offset for the second command signal for a subsequent change of a command relative to a change of the other command based on the first and second time difference (tpdon1, tpdoff 1, tpdoff2, tpdon2), on fall time (toff2 or toff1) characteristic values associated with a corresponding switching element of the switch circuitry and on target dead time value (dt), to ensure avoiding potentially damaging shoot-through currents in the switching circuit. a semiconductor die; a pulse generation arrangement on the semiconductor die configured to generate first and second command signals (PWM1, PWM2); a driver arrangement on the semiconductor die configured to generate switch control signals (HG1, LG1) based on the command signals, the switch control signals comprising an output from the semiconductor die at an output interface (117, 119) and configured to control operation of switching circuitry that regulates current from/to at least a first node to/from an electrical load, the switching circuitry configured to couple to the output interface (117, 119); and wherein the driver arrangement comprises first driver circuitry to generate the first switch control signal based on the first command signal and second driver circuitry to generate the second switch control signal based on the second command signal; and a timer arrangement on the semiconductor die and coupled to the driver arrangement configured to measure a first time difference (tpdon1, tpdoff 1) between a first change in the first command signal and a corresponding response in the first switch control signal to the first change in the first command signal; and wherein the timer arrangement is coupled to the driver arrangement and further configured to measure a second time difference (tpdoff2, tpdon2) between a second change in the second command signal and a corresponding response to the second change, in the second switch control signal; a first register coupled to the timer arrangement and configured to store the first time difference (tpdon1, tpdoff1) and the second time difference (tpdoff2, tpdon2); and a second register configured to store a target dead time value (dt); and control circuitry coupled to the first and second registers configured to determine an offset for the first command signal and an offset for the second command signal for a subsequent change of a command relative to a change of the other command based on the first and second time difference (tpdon1, tpdoff 1, tpdoff2, tpdon2), on fall time (toff2 or toff1) characteristic values associated with a corresponding switching element of the switch circuitry and on target dead time value (dt), to ensure avoiding potentially damaging shoot-through currents in the switching circuit.