A Tunnel Field Effect Transistor device (TFET) made of at least following layers: - a highly doped drain layer made of a drain semiconductor material, e.g. with a doping level of 10 16 cm -3 or higher such as for example between 10 16 cm -3 and 5.10 20 cm -3, preferably between 10 17 cm -3 and 10 20 cm -3, - a highly doped source layer, oppositely doped with respect to the drain layer, made of a source semiconductor material e.g. with a doping level of 10 16 cm -3 or higher such as for example between 10 16 cm -3 and 5.10 20 cm -3, preferably between 5.10 18 cm -3 and 10 20 cm -3, and - a channel layer made of a lowly doped, e.g. doped at a doping level below 10 18 cm -3, for example between 0 cm -3 and 10 18 cm -3, preferably between 10 15 cm -3 and 10 17 cm -3, or undoped channel semiconductor material situated in between the source and the drain layer, and - a gate structure (8, 9) comprising a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer and the gate electrode layer extending along the gate dielectric layer along a face of the gate dielectric layer opposing the face of the gate dielectric layer facing the source layer and not extending beyond the gate dielectric layer, - a highly doped, pocket layer, counterdoped with respect to the source layer, extending to between and along the source layer and the channel layer, made of a semiconductor material with a doping level of for example 10 16 cm -3 or higher such as for example between 10 16 cm -3 and 5.10 20 cm -3, preferably between 10 17 cm -3 and 10 20 cm -3, - the source, pocket, channel and drain layers being substantially planar and positioned on top and along each other characterized in that the pocket layer extends in between and along the gate dielectric layer and the source layer and that an active region is defined in the assembly of the pocket layer and the source layer where the gate dielectric layer and the gate electrode layer are positioned along the source layer and the pocket layer. - a highly doped drain layer made of a drain semiconductor material, e.g. with a doping level of 10 16 cm -3 or higher such as for example between 10 16 cm -3 and 5.10 20 cm -3, preferably between 10 17 cm -3 and 10 20 cm -3, - a highly doped source layer, oppositely doped with respect to the drain layer, made of a source semiconductor material e.g. with a doping level of 10 16 cm -3 or higher such as for example between 10 16 cm -3 and 5.10 20 cm -3, preferably between 5.10 18 cm -3 and 10 20 cm -3, and - a channel layer made of a lowly doped, e.g. doped at a doping level below 10 18 cm -3, for example between 0 cm -3 and 10 18 cm -3, preferably between 10 15 cm -3 and 10 17 cm -3, or undoped channel semiconductor material situated in between the source and the drain layer, and - a gate structure (8, 9) comprising a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer and the gate electrode layer extending along the gate dielectric layer along a face of the gate dielectric layer opposing the face of the gate dielectric layer facing the source layer and not extending beyond the gate dielectric layer, - a highly doped, pocket layer, counterdoped with respect to the source layer, extending to between and along the source layer and the channel layer, made of a semiconductor material with a doping level of for example 10 16 cm -3 or higher such as for example between 10 16 cm -3 and 5.10 20 cm -3, preferably between 10 17 cm -3 and 10 20 cm -3, - the source, pocket, channel and drain layers being substantially planar and positioned on top and along each other characterized in that the pocket layer extends in between and along the gate dielectric layer and the source layer and that an active region is defined in the assembly of the pocket layer and the source layer where the gate dielectric layer and the gate electrode layer are positioned along the source layer and the pocket layer.