An apparatus, comprising: a read cache memory device (102, 360), comprising: a dynamic random-access memory, DRAM, array (104, 234, 364-1, 364-2), comprising a qualified zone for promotion of data; and a first NAND array (106-1, 232-1, 366-1) and a second NAND array (106-2, 232-2, 366-2); and a controller (108, 370) configured to: dynamically mark bad pages within the first NAND array, wherein bad pages cannot be read-verified after written; manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array, wherein data moved from the DRAM array to the first NAND array is in a particular percentage range of most frequently visited data in the DRAM array; wherein data moved from the first NAND array to the second NAND array does not include the marked bad pages and comprises data promoted in response to the data meeting a threshold requirement and in response to the first NAND array reaching a first threshold capacity; and in response to the second NAND array reaching a second threshold capacity, demote remaining cached data within the second NAND array to the DRAM array, erase the remaining data of the first NAND array, and exchange positions of the first and the second NAND arrays; and evict data from the DRAM array that does not meet the threshold requirement to be moved to the first NAND array or the second NAND array, wherein the threshold requirement includes an access threshold. a dynamic random-access memory, DRAM, array (104, 234, 364-1, 364-2), comprising a qualified zone for promotion of data; and a first NAND array (106-1, 232-1, 366-1) and a second NAND array (106-2, 232-2, 366-2); and a controller (108, 370) configured to: dynamically mark bad pages within the first NAND array, wherein bad pages cannot be read-verified after written; manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array, wherein data moved from the DRAM array to the first NAND array is in a particular percentage range of most frequently visited data in the DRAM array; wherein data moved from the first NAND array to the second NAND array does not include the marked bad pages and comprises data promoted in response to the data meeting a threshold requirement and in response to the first NAND array reaching a first threshold capacity; and in response to the second NAND array reaching a second threshold capacity, demote remaining cached data within the second NAND array to the DRAM array, erase the remaining data of the first NAND array, and exchange positions of the first and the second NAND arrays; and evict data from the DRAM array that does not meet the threshold requirement to be moved to the first NAND array or the second NAND array, wherein the threshold requirement includes an access threshold. dynamically mark bad pages within the first NAND array, wherein bad pages cannot be read-verified after written; manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array, wherein data moved from the DRAM array to the first NAND array is in a particular percentage range of most frequently visited data in the DRAM array; wherein data moved from the first NAND array to the second NAND array does not include the marked bad pages and comprises data promoted in response to the data meeting a threshold requirement and in response to the first NAND array reaching a first threshold capacity; and in response to the second NAND array reaching a second threshold capacity, demote remaining cached data within the second NAND array to the DRAM array, erase the remaining data of the first NAND array, and exchange positions of the first and the second NAND arrays; and evict data from the DRAM array that does not meet the threshold requirement to be moved to the first NAND array or the second NAND array, wherein the threshold requirement includes an access threshold.