A method for data caching, comprising: acquiring an output matrix from a processor, wherein the output matrix is an N-order matrix, and N is a positive integer; respectively writing N rows of data of a previous output matrix into N first-level cache queues of a first queue set of a first cache unit; respectively writing N rows of data of the current output matrix into N first-level cache queues of a second queue set of the first cache unit; wherein the first cache unit is preconfigured with two queue sets, the second queue set is the queue set that is not used to store the previous output matrix in the two queue sets; and the writing speed of the first cache unit matches with the computing speed of the processor; after the previous output matrix stored in the first cache unit is written into a second cache unit, writing the data of the current output matrix stored in the second queue set into the second cache unit line by line, so as to write the current output matrix into the second cache unit; wherein the writing speed of the second cache unit matches with the computing speed of the processor; and after valid data of the previous output matrix stored in the second cache unit is written into a third cache unit, determining valid data in the current output matrix in the second cache unit according to preset parameters, and writing the valid data of the current output matrix into the third cache unit; wherein the valid data of a plurality of output matrixes in the third cache unit is configured to be sequentially written into a memory, in a sequence in which the output matrixes are acquired, and wherein the writing speed of the third cache unit matches with the computing speed of the processor. acquiring an output matrix from a processor, wherein the output matrix is an N-order matrix, and N is a positive integer; respectively writing N rows of data of a previous output matrix into N first-level cache queues of a first queue set of a first cache unit; respectively writing N rows of data of the current output matrix into N first-level cache queues of a second queue set of the first cache unit; wherein the first cache unit is preconfigured with two queue sets, the second queue set is the queue set that is not used to store the previous output matrix in the two queue sets; and the writing speed of the first cache unit matches with the computing speed of the processor; after the previous output matrix stored in the first cache unit is written into a second cache unit, writing the data of the current output matrix stored in the second queue set into the second cache unit line by line, so as to write the current output matrix into the second cache unit; wherein the writing speed of the second cache unit matches with the computing speed of the processor; and after valid data of the previous output matrix stored in the second cache unit is written into a third cache unit, determining valid data in the current output matrix in the second cache unit according to preset parameters, and writing the valid data of the current output matrix into the third cache unit; wherein the valid data of a plurality of output matrixes in the third cache unit is configured to be sequentially written into a memory, in a sequence in which the output matrixes are acquired, and wherein the writing speed of the third cache unit matches with the computing speed of the processor.