A dual in-line memory module, DIMM, comprising: a plurality of burst data storage units; each burst data storage unit among the plurality of burst data storage units comprising: a burst data word storage unit striped over a plurality of data line storage units totaling a burst length, each data line storage unit among the plurality of data line storage units comprising sixty-four data bit cells; and a burst error correcting code ECC storage unit striped over a plurality of ECC line storage units (154 -156), each ECC line storage unit among the plurality of ECC line storage units (154 -156) corresponding to a data line storage unit, each ECC line storage unit comprising eight data bit cells; and the DIMM configured to: receive a write data address for a burst memory write request; receive burst write data of a burst write data block length for the burst memory write request, the burst write data comprising a burst write data word, a burst ECC word for the burst write data word, and at least one data indicator for the burst write data word; stripe the received burst write data word across the burst data word storage unit at the received write data address; stripe the received burst ECC word for the burst write data word across the burst ECC storage unit in fewer bits than a number of data bit cells in the burst ECC storage unit at the received write data address; and store the at least one data indicator for the burst write data word in the burst ECC storage unit of the burst data storage unit at the received write data address. a plurality of burst data storage units; each burst data storage unit among the plurality of burst data storage units comprising: a burst data word storage unit striped over a plurality of data line storage units totaling a burst length, each data line storage unit among the plurality of data line storage units comprising sixty-four data bit cells; and a burst error correcting code ECC storage unit striped over a plurality of ECC line storage units (154 -156), each ECC line storage unit among the plurality of ECC line storage units (154 -156) corresponding to a data line storage unit, each ECC line storage unit comprising eight data bit cells; and a burst data word storage unit striped over a plurality of data line storage units totaling a burst length, each data line storage unit among the plurality of data line storage units comprising sixty-four data bit cells; and a burst error correcting code ECC storage unit striped over a plurality of ECC line storage units (154 -156), each ECC line storage unit among the plurality of ECC line storage units (154 -156) corresponding to a data line storage unit, each ECC line storage unit comprising eight data bit cells; and the DIMM configured to: receive a write data address for a burst memory write request; receive burst write data of a burst write data block length for the burst memory write request, the burst write data comprising a burst write data word, a burst ECC word for the burst write data word, and at least one data indicator for the burst write data word; stripe the received burst write data word across the burst data word storage unit at the received write data address; stripe the received burst ECC word for the burst write data word across the burst ECC storage unit in fewer bits than a number of data bit cells in the burst ECC storage unit at the received write data address; and store the at least one data indicator for the burst write data word in the burst ECC storage unit of the burst data storage unit at the received write data address. receive a write data address for a burst memory write request; receive burst write data of a burst write data block length for the burst memory write request, the burst write data comprising a burst write data word, a burst ECC word for the burst write data word, and at least one data indicator for the burst write data word; stripe the received burst write data word across the burst data word storage unit at the received write data address; stripe the received burst ECC word for the burst write data word across the burst ECC storage unit in fewer bits than a number of data bit cells in the burst ECC storage unit at the received write data address; and store the at least one data indicator for the burst write data word in the burst ECC storage unit of the burst data storage unit at the received write data address.