An apparatus in a pipeline microprocessor, for ensuring coherency of instructions within stages of the pipeline microprocessor, the apparatus comprising: instruction cache management logic, configured to receive an address corresponding to a next instruction, and configured to detect that a part of a memory page corresponding to said next instruction cannot be freely accessed without checking for coherency of the instructions within said part of said memory page and, upon detection, configured to provide said address; and synchronization logic, configured to receive said address from said instruction cache management logic, and configured to direct data cache management logic to check for coherency of the instructions within said part of said memory page, and, if the instructions are not coherent within said part of said memory page, said synchronization logic is configured to direct the pipeline microprocessor to stall a fetch of said next instruction until the stages of the pipeline microprocessor have executed all preceding instructions, characterized in that: said instruction cache management logic evaluates an instruction translation lookaside buffer (ITLB) entry corresponding to said address to detect that said part cannot be freely accessed, wherein said ITLB entry corresponds to said memory page, wherein said ITLB entry comprises a first plurality of part-page ownership bits and wherein one of said first plurality of part-page ownership bits corresponds to said part of said memory page; said data cache management logic evaluates a data translation lookaside buffer (DTLB) entry corresponding to said address to detect that the instructions are not coherent within said part of said memory page, wherein said DTLB entry corresponds to said memory page, wherein said DTLB entry comprises a second plurality of part-page ownership bits, and wherein one of said second plurality of part-page ownership bits corresponds to said part of said memory page; and said synchronization logic directs said data cache management logic to release ownership of said part of said memory page by changing the value of said one of said second plurality of part page ownership bits, wherein said synchronization logic directs said instruction cache management logic to establish ownership of said part of said memory page by changing the value of said one of said first plurality of part page ownerships bits. instruction cache management logic, configured to receive an address corresponding to a next instruction, and configured to detect that a part of a memory page corresponding to said next instruction cannot be freely accessed without checking for coherency of the instructions within said part of said memory page and, upon detection, configured to provide said address; and synchronization logic, configured to receive said address from said instruction cache management logic, and configured to direct data cache management logic to check for coherency of the instructions within said part of said memory page, and, if the instructions are not coherent within said part of said memory page, said synchronization logic is configured to direct the pipeline microprocessor to stall a fetch of said next instruction until the stages of the pipeline microprocessor have executed all preceding instructions, characterized in that: said instruction cache management logic evaluates an instruction translation lookaside buffer (ITLB) entry corresponding to said address to detect that said part cannot be freely accessed, wherein said ITLB entry corresponds to said memory page, wherein said ITLB entry comprises a first plurality of part-page ownership bits and wherein one of said first plurality of part-page ownership bits corresponds to said part of said memory page; said data cache management logic evaluates a data translation lookaside buffer (DTLB) entry corresponding to said address to detect that the instructions are not coherent within said part of said memory page, wherein said DTLB entry corresponds to said memory page, wherein said DTLB entry comprises a second plurality of part-page ownership bits, and wherein one of said second plurality of part-page ownership bits corresponds to said part of said memory page; and said synchronization logic directs said data cache management logic to release ownership of said part of said memory page by changing the value of said one of said second plurality of part page ownership bits, wherein said synchronization logic directs said instruction cache management logic to establish ownership of said part of said memory page by changing the value of said one of said first plurality of part page ownerships bits.