An apparatus comprising: a cascode circuit susceptible to overvoltage conditions including avalanche breakdown, the cascode circuit including a first transistor having a gate, a source, a channel and a drain, and a second transistor having a gate, a source, a channel and a drain electrically connected to the source of the first transistor, wherein the source of the second transistor is electrically connected to the gate of the first transistor, the second transistor being configured and arranged to control the first transistor in an off state by applying a voltage to the gate of the first transistor; a plurality of conductive trenches; and a set of one or more doped regions, each doped region being between a respective adjacent pair of the conductive trenches and configured to provide a p-n junction, wherein the plurality of conductive trenches and one or more doped regions are configured and arranged with the cascode circuit to provide capacitance across the source and the drain of the second transistor and to mitigate avalanche breakdown of the second transistor by restricting a voltage level at the source or the drain of the second transistor, wherein each conductive trench is lined with an insulating material and further filled with a conductive material, wherein the conductive trenches extend from between portions of a body implant layer into a doped substrate, wherein the p-n junction is formed between the body implant layer in the one or more doped regions and the doped substrate, wherein contacts couple a conductive layer to the conductive trenches and to a body implant layer of the second transistor, wherein the doped substrate is coupled to, or is part of, the drain of the second transistor, which is implemented as a vertical MOS transistor, and wherein the conductive layer is coupled to, or is part of, the source of the second transistor. a cascode circuit susceptible to overvoltage conditions including avalanche breakdown, the cascode circuit including a first transistor having a gate, a source, a channel and a drain, and a second transistor having a gate, a source, a channel and a drain electrically connected to the source of the first transistor, wherein the source of the second transistor is electrically connected to the gate of the first transistor, the second transistor being configured and arranged to control the first transistor in an off state by applying a voltage to the gate of the first transistor; a first transistor having a gate, a source, a channel and a drain, and a second transistor having a gate, a source, a channel and a drain electrically connected to the source of the first transistor, wherein the source of the second transistor is electrically connected to the gate of the first transistor, the second transistor being configured and arranged to control the first transistor in an off state by applying a voltage to the gate of the first transistor; a plurality of conductive trenches; and a set of one or more doped regions, each doped region being between a respective adjacent pair of the conductive trenches and configured to provide a p-n junction, wherein the plurality of conductive trenches and one or more doped regions are configured and arranged with the cascode circuit to provide capacitance across the source and the drain of the second transistor and to mitigate avalanche breakdown of the second transistor by restricting a voltage level at the source or the drain of the second transistor, wherein each conductive trench is lined with an insulating material and further filled with a conductive material, wherein the conductive trenches extend from between portions of a body implant layer into a doped substrate, wherein the p-n junction is formed between the body implant layer in the one or more doped regions and the doped substrate, wherein contacts couple a conductive layer to the conductive trenches and to a body implant layer of the second transistor, wherein the doped substrate is coupled to, or is part of, the drain of the second transistor, which is implemented as a vertical MOS transistor, and wherein the conductive layer is coupled to, or is part of, the source of the second transistor.