A method for operating a memory device, comprising: selecting, using a controller (675, 676) external to the memory device, a particular access line dependent biasing scheme (316-1, 316-2, 316-3) and corresponding bias conditions for use in performing an access operation on an array (100, 600) of NAND flash memory cells of the memory device; and providing, to an inhibit register of an internal controller of the memory device, bias condition information corresponding to the selected particular access line dependent biasing scheme (316-1, 316-2, 316-3) prior to providing a data load command associated with the particular access operation to the internal controller, wherein the selected particular access line dependent biasing scheme (316-1, 316-2, 316-3) comprises one of a number of program inhibit schemes; and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions; wherein the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller (675, 676) external to the memory device based, at least partially, on a relative position of a target access line within a block of memory cells of the array (100, 600); and wherein the particular access line dependent biasing scheme is one of a plurality of different access line dependent biasing schemes (316-1, 316-2, 316-3) selectable by the controller (675, 676) external to the memory device, the plurality of different access line dependent biasing schemes including: the number of program inhibit schemes; a number of different selectable program voltage ramp rate schemes; and a number of different selectable read biasing schemes. selecting, using a controller (675, 676) external to the memory device, a particular access line dependent biasing scheme (316-1, 316-2, 316-3) and corresponding bias conditions for use in performing an access operation on an array (100, 600) of NAND flash memory cells of the memory device; and providing, to an inhibit register of an internal controller of the memory device, bias condition information corresponding to the selected particular access line dependent biasing scheme (316-1, 316-2, 316-3) prior to providing a data load command associated with the particular access operation to the internal controller, wherein the selected particular access line dependent biasing scheme (316-1, 316-2, 316-3) comprises one of a number of program inhibit schemes; and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions; wherein the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller (675, 676) external to the memory device based, at least partially, on a relative position of a target access line within a block of memory cells of the array (100, 600); and wherein the particular access line dependent biasing scheme is one of a plurality of different access line dependent biasing schemes (316-1, 316-2, 316-3) selectable by the controller (675, 676) external to the memory device, the plurality of different access line dependent biasing schemes including: the number of program inhibit schemes; a number of different selectable program voltage ramp rate schemes; and a number of different selectable read biasing schemes. the number of program inhibit schemes; a number of different selectable program voltage ramp rate schemes; and a number of different selectable read biasing schemes.