A computer implemented method for system-level validation of a digital hardware system comprising the steps of: generating a high-level description of the digital hardware system; embedding into the high level description a number of quick error detection transformations; generating from the high-level description an executable software program representative of operation of the digital system; generating the digital hardware system from the high-level description including the QED transformations; executing, on a processor, the executable software program wherein upon execution one or more software signatures are generated; operating the generated digital hardware system wherein upon operation one or more hardware signatures are generated; comparing the software signatures to the hardware signatures; and in response to the comparison, providing an output indicative of that comparison; the method characterized in that: the transformations are time redundant QED (TR-QH) transformations that modify a state machine of a circuit to re-execute each single-entry-point and single-exit-point of a region of code (basic block) and variables representing inputs to a region that are modified in that region are saved and restored for re-execution and variables representing outputs of a region are saved in a first pass for comparison with a second pass; wherein the execution of the software program and the operation of the digital hardware system are done at different times; and wherein the digital hardware system is not programmable. generating a high-level description of the digital hardware system; embedding into the high level description a number of quick error detection transformations; generating from the high-level description an executable software program representative of operation of the digital system; generating the digital hardware system from the high-level description including the QED transformations; executing, on a processor, the executable software program wherein upon execution one or more software signatures are generated; operating the generated digital hardware system wherein upon operation one or more hardware signatures are generated; comparing the software signatures to the hardware signatures; and in response to the comparison, providing an output indicative of that comparison; the method characterized in that: the transformations are time redundant QED (TR-QH) transformations that modify a state machine of a circuit to re-execute each single-entry-point and single-exit-point of a region of code (basic block) and variables representing inputs to a region that are modified in that region are saved and restored for re-execution and variables representing outputs of a region are saved in a first pass for comparison with a second pass; wherein the execution of the software program and the operation of the digital hardware system are done at different times; and wherein the digital hardware system is not programmable. the transformations are time redundant QED (TR-QH) transformations that modify a state machine of a circuit to re-execute each single-entry-point and single-exit-point of a region of code (basic block) and variables representing inputs to a region that are modified in that region are saved and restored for re-execution and variables representing outputs of a region are saved in a first pass for comparison with a second pass; wherein the execution of the software program and the operation of the digital hardware system are done at different times; and wherein the digital hardware system is not programmable.