A method for fabricating a one-transistor one-capacitor, 1T1C, dynamic random access memory, DRAM, comprising: providing a substrate, a plurality of active areas arranged at intervals being provided in the substrate, and the substrate being covered with an insulating layer and a barrier layer stacked sequentially; forming a plurality of first trenches arranged at intervals in the barrier layer, each of the plurality of first trenches extending along a first direction and penetrating through the barrier layer; forming a filling layer in each of the plurality of first trenches, and forming a first mask layer on the barrier layer and the filling layer; forming a plurality of second trenches arranged at intervals in the first mask layer each of the plurality of second trenches extending along a second direction, and each of the plurality of second trenches exposing the filling layer; and removing the filling layer exposed in each of the plurality of second trenches and the insulating layer corresponding to the filling layer to form a contact hole, the contact hole exposing each of the plurality of active areas; the method characterized in that the forming the plurality of first trenches arranged at intervals in the barrier layer comprises: forming a third mask layer, a second mask layer and a first photoresist laye sequentially stacked on the barrier layer; etching the second mask layer using the first photoresist layer as a mask to form a third trench in the second mask layer, the third trench extending along the first direction; forming a first intermediate layer on a side wall and a bottom of the third trench respectively, the first intermediate layer positioned in the third trench defining a first filling groove; forming a first dielectric layer in the first filling groove; removing part of the first intermediate layer to form a plurality of first etching grooves arranged at intervals; etching the third mask layer along each of the plurality of first etching grooves to form a second etching groove in the third mask layer; and etching the barrier layer along the second etching groove to form the plurality of first trenches in the barrier layer. providing a substrate, a plurality of active areas arranged at intervals being provided in the substrate, and the substrate being covered with an insulating layer and a barrier layer stacked sequentially; forming a plurality of first trenches arranged at intervals in the barrier layer, each of the plurality of first trenches extending along a first direction and penetrating through the barrier layer; forming a filling layer in each of the plurality of first trenches, and forming a first mask layer on the barrier layer and the filling layer; forming a plurality of second trenches arranged at intervals in the first mask layer each of the plurality of second trenches extending along a second direction, and each of the plurality of second trenches exposing the filling layer; and removing the filling layer exposed in each of the plurality of second trenches and the insulating layer corresponding to the filling layer to form a contact hole, the contact hole exposing each of the plurality of active areas; the method characterized in that the forming the plurality of first trenches arranged at intervals in the barrier layer comprises: forming a third mask layer, a second mask layer and a first photoresist laye sequentially stacked on the barrier layer; etching the second mask layer using the first photoresist layer as a mask to form a third trench in the second mask layer, the third trench extending along the first direction; forming a first intermediate layer on a side wall and a bottom of the third trench respectively, the first intermediate layer positioned in the third trench defining a first filling groove; forming a first dielectric layer in the first filling groove; removing part of the first intermediate layer to form a plurality of first etching grooves arranged at intervals; etching the third mask layer along each of the plurality of first etching grooves to form a second etching groove in the third mask layer; and etching the barrier layer along the second etching groove to form the plurality of first trenches in the barrier layer.