An analog-to-digital converter, ADC, comprising: a plurality of single slope ADCs (32, 34, 36, 38), each single slope ADC comprising: an analog input operable to receive an analog input signal; a ramp input operable to receive an analog ramp signal; a comparator operable to compare the analog input signal to the analog ramp signal; and an output operable to produce a digital representation of the analog input signal based upon the comparison, wherein the plurality of single slope ADCs (32, 34, 36, 38) are operable to receive the analog ramp signals that are out of phase with each other and the analog input signals that are spaced apart in time from each other and are coupled to a common analog input of the analog-to-digital converter; and a ramp generator that is operable to generate the analog ramp signals for each of the plurality of single slope ADCs (32, 34, 36, 38); and digital output circuitry operable to receive the outputs from each of the plurality of single slope ADCs (32, 34, 36, 38) and to produce a digital representation of the analog input signal based thereupon; wherein the plurality of single slope ADCs (32, 34, 36, 38) comprise four single slope ADCs and the four single slope ADCs are operable such that at any time of operation: a first single slope ADC is in a reset mode; a second single slope ADC is receiving the analog input signal; a third single slope ADC is converting the analog input signal to a corresponding digital representation; and a fourth single slope ADC is conveying a digital representation of an analog input signal of a previous clock cycle; wherein the ramp generator comprises circuitry to simultaneously generate the analog ramp signal for each of the plurality of single slope ADCs (32, 34, 36, 38); wherein the ramp generator is operable to produce a plurality of ramp signals that are all out of phase with each other, and such that successive ramp signals are out of phase by a single clock period. a plurality of single slope ADCs (32, 34, 36, 38), each single slope ADC comprising: an analog input operable to receive an analog input signal; a ramp input operable to receive an analog ramp signal; a comparator operable to compare the analog input signal to the analog ramp signal; and an output operable to produce a digital representation of the analog input signal based upon the comparison, wherein the plurality of single slope ADCs (32, 34, 36, 38) are operable to receive the analog ramp signals that are out of phase with each other and the analog input signals that are spaced apart in time from each other and are coupled to a common analog input of the analog-to-digital converter; and an analog input operable to receive an analog input signal; a ramp input operable to receive an analog ramp signal; a comparator operable to compare the analog input signal to the analog ramp signal; and an output operable to produce a digital representation of the analog input signal based upon the comparison, wherein the plurality of single slope ADCs (32, 34, 36, 38) are operable to receive the analog ramp signals that are out of phase with each other and the analog input signals that are spaced apart in time from each other and are coupled to a common analog input of the analog-to-digital converter; and a ramp generator that is operable to generate the analog ramp signals for each of the plurality of single slope ADCs (32, 34, 36, 38); and digital output circuitry operable to receive the outputs from each of the plurality of single slope ADCs (32, 34, 36, 38) and to produce a digital representation of the analog input signal based thereupon; wherein the plurality of single slope ADCs (32, 34, 36, 38) comprise four single slope ADCs and the four single slope ADCs are operable such that at any time of operation: a first single slope ADC is in a reset mode; a second single slope ADC is receiving the analog input signal; a third single slope ADC is converting the analog input signal to a corresponding digital representation; and a fourth single slope ADC is conveying a digital representation of an analog input signal of a previous clock cycle; wherein the ramp generator comprises circuitry to simultaneously generate the analog ramp signal for each of the plurality of single slope ADCs (32, 34, 36, 38); wherein the ramp generator is operable to produce a plurality of ramp signals that are all out of phase with each other, and such that successive ramp signals are out of phase by a single clock period. a first single slope ADC is in a reset mode; a second single slope ADC is receiving the analog input signal; a third single slope ADC is converting the analog input signal to a corresponding digital representation; and a fourth single slope ADC is conveying a digital representation of an analog input signal of a previous clock cycle; wherein the ramp generator comprises circuitry to simultaneously generate the analog ramp signal for each of the plurality of single slope ADCs (32, 34, 36, 38); wherein the ramp generator is operable to produce a plurality of ramp signals that are all out of phase with each other, and such that successive ramp signals are out of phase by a single clock period.