A cache system comprising a set associative cache with a number of cache ways, at least one way being a RAM set cache, the cache system comprising: a data memory having a plurality of addressable entries corresponding to the RAM set cache; a tag register defining an address range for a contiguous block of information from main memory addresses mapped to said data memory;a global valid bit associated with the tag register; valid entry bits associated with the plurality of addressable entries of the address range; cache control circuitry configured to selectively fill said data memory either by set fill mode where all locations of said data memory are filled after setting said tag register or line-by-line fill mode, where entries of said data memory are filled in response to an access by a processing core to a corresponding address in said data memory; and hit-miss logic configured to determine whether information accessed by said processing core is stored in said data memory, wherein the control circuitry is adapted to perform the steps: for the line-by-line fill mode, the global valid bit is set to "1" and the valid entry bits are set to "0" when the tag register is set to the high order bits of a starting address of a contiguous block of main memory; upon receiving an address from the core, a valid entry bit is selected based on the low order bits of the address; a line of the data memory is loaded from main memory each time that a miss situation occurs, the miss situation occurring when a comparator determines a match between the tag register with high order bits from the address from the processing core, the global valid bit equals "1" and the valid entry bit associated with the line address equals "0", and wherein when the line is loaded into the data memory from main memory, the valid entry bit corresponding to the line is set to "1"; for the set fill mode, the global valid bit and the valid entry bits are set to "0"; when a starting address of a contiguous block of main memory is written to the tag register, the data memory is filled through a direct memory access process; as each line is loaded from main memory, the valid entry bit corresponding to the line is set to "1"; after the data memory has been completely loaded from main memory, the global valid bit is set to "1"; the hit-miss logic is adapted to perform the steps: when an address is received from the processing core in connection with a read operation, if both the high order bits of the address from the core match the high order bits of the starting address and the global valid bit equals "1", then if the valid entry bit at the line corresponding to the low order bits of the address is set to "1", the line is presented to the core processor; otherwise, if the valid entry bit at the line corresponding to the low order bits of the address is set to "0", the line is loaded into the data memory from main memory; if the high order bits of the address from the core do not match the high order bits of the starting address or the global valid bit equals "0", then a cache hit determination in the remaining ways of the set associative cache is performed. a data memory having a plurality of addressable entries corresponding to the RAM set cache; a tag register defining an address range for a contiguous block of information from main memory addresses mapped to said data memory;a global valid bit associated with the tag register; for the line-by-line fill mode, the global valid bit is set to "1" and the valid entry bits are set to "0" when the tag register is set to the high order bits of a starting address of a contiguous block of main memory; upon receiving an address from the core, a valid entry bit is selected based on the low order bits of the address; a line of the data memory is loaded from main memory each time that a miss situation occurs, the miss situation occurring when a comparator determines a match between the tag register with high order bits from the address from the processing core, the global valid bit equals "1" and the valid entry bit associated with the line address equals "0", and wherein when the line is loaded into the data memory from main memory, the valid entry bit corresponding to the line is set to "1"; for the set fill mode, the global valid bit and the valid entry bits are set to "0"; when a starting address of a contiguous block of main memory is written to the tag register, the data memory is filled through a direct memory access process; as each line is loaded from main memory, the valid entry bit corresponding to the line is set to "1"; after the data memory has been completely loaded from main memory, the global valid bit is set to "1"; when an address is received from the processing core in connection with a read operation, if both the high order bits of the address from the core match the high order bits of the starting address and the global valid bit equals "1", then if the valid entry bit at the line corresponding to the low order bits of the address is set to "1", the line is presented to the core processor; otherwise, if the valid entry bit at the line corresponding to the low order bits of the address is set to "0", the line is loaded into the data memory from main memory;