A method for communication of a binary data word using a vector signaling code between a memory controller device and at least one memory device, the method comprising: receiving the binary data word comprising a first bit, a second bit, and a third bit, and prior output states of a ternary driver circuit configured to drive a first wire, a second wire and a third wire, wherein the prior output states represent a previously transmitted vector signaling code word; encoding the binary data word into a vector signaling code word as transitions from the prior output states of the previously transmitted vector signaling code word, wherein the encoding comprises: selecting, based upon a determination of a first two bits of the three input bits both not being logic ones, an output wire based on the first two bits, determining a new output state of the selected wire according to a first transition-limiting function operating on: (i) the prior state of the selected wire; and (ii) the third input bit; determining, based upon both of the first two bits being logic one and the third bit being logic zero, new output states of the first wire and the second wire, and wherein the new states are determined according to a second transition-limiting function operating on the prior states of the first two wires; and transmitting the vector signaling code word in one transmission interval on a set of wires connecting the memory controller device and the at least one memory device. receiving the binary data word comprising a first bit, a second bit, and a third bit, and prior output states of a ternary driver circuit configured to drive a first wire, a second wire and a third wire, wherein the prior output states represent a previously transmitted vector signaling code word; encoding the binary data word into a vector signaling code word as transitions from the prior output states of the previously transmitted vector signaling code word, wherein the encoding comprises: selecting, based upon a determination of a first two bits of the three input bits both not being logic ones, an output wire based on the first two bits, determining a new output state of the selected wire according to a first transition-limiting function operating on: (i) the prior state of the selected wire; and (ii) the third input bit; determining, based upon both of the first two bits being logic one and the third bit being logic zero, new output states of the first wire and the second wire, and wherein the new states are determined according to a second transition-limiting function operating on the prior states of the first two wires; and transmitting the vector signaling code word in one transmission interval on a set of wires connecting the memory controller device and the at least one memory device. selecting, based upon a determination of a first two bits of the three input bits both not being logic ones, an output wire based on the first two bits, determining a new output state of the selected wire according to a first transition-limiting function operating on: (i) the prior state of the selected wire; and (ii) the third input bit; (i) the prior state of the selected wire; and (ii) the third input bit; determining, based upon both of the first two bits being logic one and the third bit being logic zero, new output states of the first wire and the second wire, and wherein the new states are determined according to a second transition-limiting function operating on the prior states of the first two wires; and transmitting the vector signaling code word in one transmission interval on a set of wires connecting the memory controller device and the at least one memory device.