An electronic system (100, 400), comprising: a processing sub-system (110, 412) configured to execute a program (112, 414) using a set of virtual memory addresses to reference memory locations for storage of variables of the program (112, 414); a programmable logic sub-system (120, 420) configured to implement a set of circuits specified in a configuration data stream, the set of circuits including a plurality of input/output circuits (124, 126, 426, 428), each input/output circuit (124, 126, 426, 428) having a respective identifier and configured to access a respective one of the variables; a memory (190, 490); a memory management circuit (170, 470) configured to: map the set of virtual memory addresses to physical memory addresses of the memory (190, 490); and for each of the plurality of input/output circuits (124, 126, 426, 428) that accesses the respective one of the variables of the program (112, 414), map the respective ID of the input/output circuit (124, 126, 426, 428) to the physical memory address that corresponds to the respective one of the variables; at least one translation look-aside buffer, TLB (144, 146, 442, 444, 446), coupled to at least one input/output circuit of the plurality of input/output circuits (124, 126, 426, 428), the at least one translation look-aside buffer (144, 146, 442, 444, 446) configured to determine, in response to receiving a memory access request indicating an ID, a physical memory address that is mapped to the ID indicated in the memory access request and to provide to the memory (190, 490) a memory access request indicating the physical memory address that is mapped to the ID; and wherein the set of circuits implemented by the programmable logic sub-system (120, 420) includes the at least one TLB (144, 146, 442, 444, 446). a processing sub-system (110, 412) configured to execute a program (112, 414) using a set of virtual memory addresses to reference memory locations for storage of variables of the program (112, 414); a programmable logic sub-system (120, 420) configured to implement a set of circuits specified in a configuration data stream, the set of circuits including a plurality of input/output circuits (124, 126, 426, 428), each input/output circuit (124, 126, 426, 428) having a respective identifier and configured to access a respective one of the variables; a memory (190, 490); a memory management circuit (170, 470) configured to: map the set of virtual memory addresses to physical memory addresses of the memory (190, 490); and for each of the plurality of input/output circuits (124, 126, 426, 428) that accesses the respective one of the variables of the program (112, 414), map the respective ID of the input/output circuit (124, 126, 426, 428) to the physical memory address that corresponds to the respective one of the variables; map the set of virtual memory addresses to physical memory addresses of the memory (190, 490); and for each of the plurality of input/output circuits (124, 126, 426, 428) that accesses the respective one of the variables of the program (112, 414), map the respective ID of the input/output circuit (124, 126, 426, 428) to the physical memory address that corresponds to the respective one of the variables; at least one translation look-aside buffer, TLB (144, 146, 442, 444, 446), coupled to at least one input/output circuit of the plurality of input/output circuits (124, 126, 426, 428), the at least one translation look-aside buffer (144, 146, 442, 444, 446) configured to determine, in response to receiving a memory access request indicating an ID, a physical memory address that is mapped to the ID indicated in the memory access request and to provide to the memory (190, 490) a memory access request indicating the physical memory address that is mapped to the ID; and wherein the set of circuits implemented by the programmable logic sub-system (120, 420) includes the at least one TLB (144, 146, 442, 444, 446).