A shift register, comprising a plurality of stages, {S n}, connected in serial, n = 1, 2,..., N, N being a positive integer, wherein each stage S n comprises: a first output for outputting a gate signal (G(n)); a second output for outputting a stage carry signal (ST(n)); a pull-up circuit electrically coupled between a node (Q(n)) and the second output; wherein the pull-up circuit comprises a transistor having a gate electrically coupled to the node (Q(n)), a source configured to receive one of a plurality of control signals, {HCj}, j = 1, 2,..., M, M being a positive integer, and a drain electrically coupled to the second output, and wherein the pull-up circuit further comprises a capacitor (c) electrically coupled between the gate and drain of the transistor; a pull-up control circuit electrically coupled to the node (Q(n)); a pull-down circuit electrically coupled to the node (Q(n)) and the first output; and a control circuit electrically coupled between the node (Q(n)) and the first output, wherein the pull-up control circuit of the stage S n is further electrically coupled to the node (Q(n-1)) and the second output of the stage S n-1, wherein the pull-up control circuit further comprises: (a) a first transistor having a gate, a source electrically coupled to the second output of the stage S n-1 for receiving the stage carry signal (ST(n-1)) therefrom and a drain electrically coupled to the input node (Q(n)); and (b) a second transistor having a gate electrically coupled to the node (Q(n-1)) of the stage S n-1, a source configured to receive one of a plurality of control signals {HCj}, and a drain electrically coupled to the gate of the first transistor; and wherein the control circuit is configured to receive a DC voltage signal such that the first output is configured to output the gate signal (G(n)) at a high voltage level when the voltage of the node (Q(n)) is pulled up to a high level, and the first output is configured to output the gate signal (G(n)) with a further higher voltage level when the voltage of the node (Q(n)) is pulled up to a further higher level, wherein the control circuit comprises a transistor having a gate electrically coupled to the node (Q(n)), a source configured to receive the DC voltage signal and a drain electrically coupled to the first output. a first output for outputting a gate signal (G(n)); a second output for outputting a stage carry signal (ST(n)); a pull-up circuit electrically coupled between a node (Q(n)) and the second output; wherein the pull-up circuit comprises a transistor having a gate electrically coupled to the node (Q(n)), a source configured to receive one of a plurality of control signals, {HCj}, j = 1, 2,..., M, M being a positive integer, and a drain electrically coupled to the second output, and wherein the pull-up circuit further comprises a capacitor (c) electrically coupled between the gate and drain of the transistor; a pull-up control circuit electrically coupled to the node (Q(n)); a pull-down circuit electrically coupled to the node (Q(n)) and the first output; and a control circuit electrically coupled between the node (Q(n)) and the first output, wherein the pull-up control circuit of the stage S n is further electrically coupled to the node (Q(n-1)) and the second output of the stage S n-1, wherein the pull-up control circuit further comprises: (a) a first transistor having a gate, a source electrically coupled to the second output of the stage S n-1 for receiving the stage carry signal (ST(n-1)) therefrom and a drain electrically coupled to the input node (Q(n)); and (b) a second transistor having a gate electrically coupled to the node (Q(n-1)) of the stage S n-1, a source configured to receive one of a plurality of control signals {HCj}, and a drain electrically coupled to the gate of the first transistor; and wherein (a) a first transistor having a gate, a source electrically coupled to the second output of the stage S n-1 for receiving the stage carry signal (ST(n-1)) therefrom and a drain electrically coupled to the input node (Q(n)); and (b) a second transistor having a gate electrically coupled to the node (Q(n-1)) of the stage S n-1, a source configured to receive one of a plurality of control signals {HCj}, and a drain electrically coupled to the gate of the first transistor; and wherein the control circuit is configured to receive a DC voltage signal such that the first output is configured to output the gate signal (G(n)) at a high voltage level when the voltage of the node (Q(n)) is pulled up to a high level, and the first output is configured to output the gate signal (G(n)) with a further higher voltage level when the voltage of the node (Q(n)) is pulled up to a further higher level, wherein the control circuit comprises a transistor having a gate electrically coupled to the node (Q(n)), a source configured to receive the DC voltage signal and a drain electrically coupled to the first output.