An electronically variable oscillator circuit comprising: a piezoelectric resonator, a capacitance connected in parallel with the piezoelectric resonator, the capacitance comprising two capacitors (114, 115) connected in series, the electronically variable oscillator circuit being characterised in that it further comprises an electronically variable simulated inductor connected in parallel with the piezoelectric resonator and the capacitance, the electronically variable simulated inductor comprising: an input comprising first and second terminals (11, 11'), the said capacitors (114, 115) being connected in series between the first and second input terminals, an integrator having an input connected to receive a scaled version (V 2) of the voltage (V 1) present at the input of the simulated inductor from the node between the said capacitors (114, 115) and being configured to provide a voltage signal (V 3) that is an integrated version of the voltage signal (V 2) at its input, and a transconductor having two controlled current terminals respectively connected to the input terminals (11, 11') of the simulated inductor and a control terminal connected to receive the signal output by the integrator and being configured to control the current passed by the controlled current terminals, wherein the gain round the loop that includes the integrator and the transconductor is variable in response to an electronic control signal. a piezoelectric resonator, a capacitance connected in parallel with the piezoelectric resonator, the capacitance comprising two capacitors (114, 115) connected in series, the electronically variable oscillator circuit being characterised in that it further comprises an electronically variable simulated inductor connected in parallel with the piezoelectric resonator and the capacitance, the electronically variable simulated inductor comprising: an input comprising first and second terminals (11, 11'), the said capacitors (114, 115) being connected in series between the first and second input terminals, an integrator having an input connected to receive a scaled version (V 2) of the voltage (V 1) present at the input of the simulated inductor from the node between the said capacitors (114, 115) and being configured to provide a voltage signal (V 3) that is an integrated version of the voltage signal (V 2) at its input, and a transconductor having two controlled current terminals respectively connected to the input terminals (11, 11') of the simulated inductor and a control terminal connected to receive the signal output by the integrator and being configured to control the current passed by the controlled current terminals, an input comprising first and second terminals (11, 11'), the said capacitors (114, 115) being connected in series between the first and second input terminals, an integrator having an input connected to receive a scaled version (V 2) of the voltage (V 1) present at the input of the simulated inductor from the node between the said capacitors (114, 115) and being configured to provide a voltage signal (V 3) that is an integrated version of the voltage signal (V 2) at its input, and a transconductor having two controlled current terminals respectively connected to the input terminals (11, 11') of the simulated inductor and a control terminal connected to receive the signal output by the integrator and being configured to control the current passed by the controlled current terminals,