A solid-state image sensing apparatus, comprising: a pixel portion which includes a plurality of pixels arranged in an array form; a conversion portion which includes a first group for at least one column of pixels of said pixel portion, including an analog/digital conversion unit for converting an analog signal output from pixels in a respective column of said pixel portion into a digital signal, and a second group for at least one column of pixels of said pixel portion other than the at least one column of pixels of the first group, including an analog/digital conversion unit for converting an analog signal output from pixels in a respective column of said pixel portion into a digital signal; and a clock supply unit for propagating a clock signal, wherein each of the analog/digital conversion units of the first group and the second group includes a comparison unit and a counter unit, said comparison unit is adapted to compare the analog signal with a comparison reference potential which changes with time and outputs a result, and said counter unit is adapted to count a clock signal supplied from said clock supply unit, characterized in that said clock supply unit includes a first clock buffer for buffering the propagating clock signal and a second clock buffer for buffering the propagating clock signal, which are connected in series to each other, the first clock buffer is adapted to correct a duty ratio of the clock signal by using a differential circuit (3, 4), and to output the clock signal to each of the counter units of the first group and to the second clock bluffer via even-numbered CMOS inverter stages, and the second clock buffer is adapted to correct a duty ratio of a clock signal supplied from the first clock buffer by using a differential circuit (3, 4), and to output the clock signal to each of the counter units of the second group via even-numbered CMOS inverter stages. a pixel portion which includes a plurality of pixels arranged in an array form; a conversion portion which includes a first group for at least one column of pixels of said pixel portion, including an analog/digital conversion unit for converting an analog signal output from pixels in a respective column of said pixel portion into a digital signal, and a second group for at least one column of pixels of said pixel portion other than the at least one column of pixels of the first group, including an analog/digital conversion unit for converting an analog signal output from pixels in a respective column of said pixel portion into a digital signal; and a clock supply unit for propagating a clock signal, wherein each of the analog/digital conversion units of the first group and the second group includes a comparison unit and a counter unit, said comparison unit is adapted to compare the analog signal with a comparison reference potential which changes with time and outputs a result, and said counter unit is adapted to count a clock signal supplied from said clock supply unit, said clock supply unit includes a first clock buffer for buffering the propagating clock signal and a second clock buffer for buffering the propagating clock signal, which are connected in series to each other, the first clock buffer is adapted to correct a duty ratio of the clock signal by using a differential circuit (3, 4), and to output the clock signal to each of the counter units of the first group and to the second clock bluffer via even-numbered CMOS inverter stages, and the second clock buffer is adapted to correct a duty ratio of a clock signal supplied from the first clock buffer by using a differential circuit (3, 4), and to output the clock signal to each of the counter units of the second group via even-numbered CMOS inverter stages.