A system for transferring a data signal from a first clock domain to a second clock domain, wherein the first clock domain comprises a first clock (ck_fast) and the second clock domain comprises a second clock (ck_slow), wherein the first clock (ck_fast) has a frequency greater than a frequency of the second clock (ck_slow), wherein the first and second clock domains (4, 8) are not synchronised to each other, the system comprising: a signal input for receiving an input signal (sig_fast) from the first clock domain; means for checking (16, 18) whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, said checking means (16, 18) being clocked by the first clock (ck_fast); and means for transferring (14,20,22) the input signal (sig_fast) as an output signal (sig_slow) to the second clock domain if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition; the system being characterised by: means for detecting if there is a new input signal from the first clock domain, wherein the means for detecting comprises a comparator between the input signal (sig_fast) from the first clock domain and the output signal (sig_slow) to the second clock domain; and in that the means for transferring (14, 20, 22) is adapted to transfer the input signal (sig_fast) to the second clock domain only if the means for detecting determines that the input signal (sig_fast) from the first clock domain and the output signal (sig_slow) to the second clock domain are different. a signal input for receiving an input signal (sig_fast) from the first clock domain; means for checking (16, 18) whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, said checking means (16, 18) being clocked by the first clock (ck_fast); and means for transferring (14,20,22) the input signal (sig_fast) as an output signal (sig_slow) to the second clock domain if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition; the system being characterised by: means for detecting if there is a new input signal from the first clock domain, wherein the means for detecting comprises a comparator between the input signal (sig_fast) from the first clock domain and the output signal (sig_slow) to the second clock domain; and in that the means for transferring (14, 20, 22) is adapted to transfer the input signal (sig_fast) to the second clock domain only if the means for detecting determines that the input signal (sig_fast) from the first clock domain and the output signal (sig_slow) to the second clock domain are different. means for detecting if there is a new input signal from the first clock domain, wherein the means for detecting comprises a comparator between the input signal (sig_fast) from the first clock domain and the output signal (sig_slow) to the second clock domain; and in that the means for transferring (14, 20, 22) is adapted to transfer the input signal (sig_fast) to the second clock domain only if the means for detecting determines that the input signal (sig_fast) from the first clock domain and the output signal (sig_slow) to the second clock domain are different.