An electronic device (200, 300) comprising: a first write driver (203,333); a second write driver (205, 335); at least one magnetic tunnel junction - MTJ - (220, 221, 222, 223, 350, 351, 352, 353, 354, 355) coupled to a bit line (208, 302, 303) and coupled to a source line (210, 304, 305); a current sink circuit (206, 340, 341) for providing a single discharge path from the bit line to a local ground (231 320 321), wherein the single discharge path comprises a first transistor comprising a gate coupled to the source line and wherein the bit line is selectively coupled to the local ground in response to a voltage at the source line; a first path from the first write driver to the second write driver via the MTJ, wherein the first path has a first length; and a second path from the first write driver to the current sink circuit via the MTJ, wherein the second path has a second length, wherein: when a first write operation is performed and the first length is shorter than the second length, a write current flows from the first write driver to the MTJ and to the second write driver, when the first write operation is performed and the second length is shorter than the first length, the write current flows from the first write driver to the MTJ and to the current sink circuit; and when a second write operation is performed, the write current flows from the second write driver to the MTJ and to the first write driver; characterised in that the single discharge path further comprises a second transistor serially coupled to the first transistor and wherein the second transistor is responsive to a test mode signal to selectively block a discharge of the bit line through the signal discharge path during a test mode. a first write driver (203,333); a second write driver (205, 335); at least one magnetic tunnel junction - MTJ - (220, 221, 222, 223, 350, 351, 352, 353, 354, 355) coupled to a bit line (208, 302, 303) and coupled to a source line (210, 304, 305); a current sink circuit (206, 340, 341) for providing a single discharge path from the bit line to a local ground (231 320 321), wherein the single discharge path comprises a first transistor comprising a gate coupled to the source line and wherein the bit line is selectively coupled to the local ground in response to a voltage at the source line; a first path from the first write driver to the second write driver via the MTJ, wherein the first path has a first length; and a second path from the first write driver to the current sink circuit via the MTJ, wherein the second path has a second length, wherein: when a first write operation is performed and the first length is shorter than the second length, a write current flows from the first write driver to the MTJ and to the second write driver, when the first write operation is performed and the second length is shorter than the first length, the write current flows from the first write driver to the MTJ and to the current sink circuit; and when a second write operation is performed, the write current flows from the second write driver to the MTJ and to the first write driver; characterised in that the single discharge path further comprises a second transistor serially coupled to the first transistor and wherein the second transistor is responsive to a test mode signal to selectively block a discharge of the bit line through the signal discharge path during a test mode. when a first write operation is performed and the first length is shorter than the second length, a write current flows from the first write driver to the MTJ and to the second write driver, when the first write operation is performed and the second length is shorter than the first length, the write current flows from the first write driver to the MTJ and to the current sink circuit; and when a second write operation is performed, the write current flows from the second write driver to the MTJ and to the first write driver; characterised in that the single discharge path further comprises a second transistor serially coupled to the first transistor and wherein the second transistor is responsive to a test mode signal to selectively block a discharge of the bit line through the signal discharge path during a test mode.