An input protection circuit for generating an output voltage in response to an input voltage, comprising: a first cascode switch to limit the output voltage when input voltage excursions are below a specified voltage operation range comprising a high-voltage PMOS field effect transistor (PMOSFET) having a control electrode, a first current carrying electrode connected across a first zener diode to the control electrode, and a second current carrying electrode connected to receive an input voltage; a blocking field effect transistor having a control electrode connected to a power supply voltage, a first current carrying electrode connected across a second zener diode to the power supply voltage, and a second current carrying electrode connected to the control electrode of the high-voltage PMOSFET; a second cascode switch to limit the output voltage when input voltage excursions are above the specified voltage operation range comprising a high-voltage NMOS field effect transistor (NMOSFET) having a control electrode connected to the power supply voltage, a first current carrying electrode providing the output voltage and connected across a third zener diode to the control electrode, and a second current carrying electrode connected to a source follower node (NODE 2); and a level shifter circuit connected between the first current carrying electrode of the high-voltage PMOSFET and the source follower node, wherein the level shifter circuit comprises a transistor having a control electrode connected to the first current carrying electrode of the high-voltage PMOSFET, a first current carrying electrode comprising the source follower node that is connected across a fourth zener diode to the control electrode of the transistor, and a second current carrying electrode coupled over a diode to the power supply voltage, and wherein each of the high-voltage PMOSFET, blocking FET, high-voltage NMOSFET, and transistor is separately connected to the same second power supply voltage by a current source circuit. a first cascode switch to limit the output voltage when input voltage excursions are below a specified voltage operation range comprising a high-voltage PMOS field effect transistor (PMOSFET) having a control electrode, a first current carrying electrode connected across a first zener diode to the control electrode, and a second current carrying electrode connected to receive an input voltage; a blocking field effect transistor having a control electrode connected to a power supply voltage, a first current carrying electrode connected across a second zener diode to the power supply voltage, and a second current carrying electrode connected to the control electrode of the high-voltage PMOSFET; a second cascode switch to limit the output voltage when input voltage excursions are above the specified voltage operation range comprising a high-voltage NMOS field effect transistor (NMOSFET) having a control electrode connected to the power supply voltage, a first current carrying electrode providing the output voltage and connected across a third zener diode to the control electrode, and a second current carrying electrode connected to a source follower node (NODE 2); and a level shifter circuit connected between the first current carrying electrode of the high-voltage PMOSFET and the source follower node, wherein the level shifter circuit comprises a transistor having a control electrode connected to the first current carrying electrode of the high-voltage PMOSFET, a first current carrying electrode comprising the source follower node that is connected across a fourth zener diode to the control electrode of the transistor, and a second current carrying electrode coupled over a diode to the power supply voltage, and wherein each of the high-voltage PMOSFET, blocking FET, high-voltage NMOSFET, and transistor is separately connected to the same second power supply voltage by a current source circuit.