A microcontroller circuit comprising a first memory bank, a second memory bank, a processing unit, and a timer circuit, wherein the processing unit is configured to: i) generate an output sequence of binary values encoding an outgoing CAN frame according to a CAN protocol, ii) process said output sequence of binary values to detect a sequence of ordered PWM periods (1P, SP, LP), each PWM period comprising a first portion having a dominant state and a second portion having a recessive state, each PWM period having a respective total duration and a respective duty-cycle value, iii) store into said first memory bank a set of ordered first values indicative of a first parameter of said PWM periods in said sequence of ordered PWM periods, and iv) store into said second memory bank a set of ordered second values indicative of a second parameter of said PWM periods in said sequence of ordered PWM periods, wherein said first parameter and said second parameter define a shape of said PWM periods, and wherein the timer circuit comprises: a first register configured to read (25a, 26a) from said first memory bank and store a value indicative of the first parameter of a current PWM period in said sequence of ordered PWM periods, a counter circuit configured to increase an internal count number and to reset the internal count number as a function of said value stored in said first register, and configured to trigger reading (25a, 26a) from said first memory bank and storing into said first register a subsequent value indicative of the first parameter of a subsequent PWM period in said sequence of ordered PWM periods as a function of said value stored in said first register, and a second register configured to read (25b, 26b) from said second memory bank and store a value indicative of the second parameter of the current PWM period, compare said internal count number of the counter circuit to said value stored into said second register, and: drive an output pin of the microcontroller circuit to a dominant value or to a recessive value as a function of said comparing the internal count number of the counter circuit to the value stored into said second register, whereby said output pin provides an output PWM signal comprising said sequence of ordered PWM periods, the second register being further configured to read (25b, 26b) from said second memory bank and store a subsequent value indicative of the second parameter of a subsequent PWM period in said sequence of ordered PWM periods in response to the internal count number of the counter circuit reaching said value stored into said second register, or in response to the internal count number of the counter circuit reaching said value stored into said first register. i) generate an output sequence of binary values encoding an outgoing CAN frame according to a CAN protocol, ii) process said output sequence of binary values to detect a sequence of ordered PWM periods (1P, SP, LP), each PWM period comprising a first portion having a dominant state and a second portion having a recessive state, each PWM period having a respective total duration and a respective duty-cycle value, iii) store into said first memory bank a set of ordered first values indicative of a first parameter of said PWM periods in said sequence of ordered PWM periods, and iv) store into said second memory bank a set of ordered second values indicative of a second parameter of said PWM periods in said sequence of ordered PWM periods, a first register configured to read (25a, 26a) from said first memory bank and store a value indicative of the first parameter of a current PWM period in said sequence of ordered PWM periods, a counter circuit configured to increase an internal count number and to reset the internal count number as a function of said value stored in said first register, and configured to trigger reading (25a, 26a) from said first memory bank and storing into said first register a subsequent value indicative of the first parameter of a subsequent PWM period in said sequence of ordered PWM periods as a function of said value stored in said first register, and a second register configured to read (25b, 26b) from said second memory bank and store a value indicative of the second parameter of the current PWM period, compare said internal count number of the counter circuit to said value stored into said second register, and: drive an output pin of the microcontroller circuit to a dominant value or to a recessive value as a function of said comparing the internal count number of the counter circuit to the value stored into said second register, whereby said output pin provides an output PWM signal comprising said sequence of ordered PWM periods, drive an output pin of the microcontroller circuit to a dominant value or to a recessive value as a function of said comparing the internal count number of the counter circuit to the value stored into said second register, whereby said output pin provides an output PWM signal comprising said sequence of ordered PWM periods, the second register being further configured to read (25b, 26b) from said second memory bank and store a subsequent value indicative of the second parameter of a subsequent PWM period in said sequence of ordered PWM periods in response to the internal count number of the counter circuit reaching said value stored into said second register, or in response to the internal count number of the counter circuit reaching said value stored into said first register.