A neural network convolution operation device for implementing a convolution of a weight matrix and a neuron matrix in a neural network by a matrix multiplication operation, the neural network convolution operation device comprising an arithmetic unit and a controller, wherein the arithmetic unit comprises a shift arithmetic unit and a matrix multiplier, wherein the shift arithmetic unit is configured to perform a winograd transformation on the neuron matrix and the weight matrix respectively, so as to obtain a transformed neuron matrix and a transformed weight matrix; the matrix multiplier is configured to perform the matrix multiplication operation which multiplies the transformed neuron matrix and the transformed weight matrix together, so as to obtain a multiplication matrix; the shift arithmetic unit is further configured to perform a winograd inverse transformation on the multiplication matrix to obtain a convolution result; wherein the shift arithmetic unit and the matrix multiplier are connected in a way to enable a bi-directional data communication between the shift arithmetic unit and the matrix multiplier; wherein the controller is configured to control the shift arithmetic unit to perform the winograd transformation or the winograd inverse transformation, and control the matrix multiplier to perform the matrix multiplication operation; wherein the arithmetic unit further comprises a sparse processing unit configured to sparsely process the transformed weight matrix to generate a binary sparse sequence, wherein "0" corresponds to the element of which the value is "0" in the transformed weight matrix, and " 1" corresponds to the element of which the value is not "0" in the transformed weight matrix; wherein the sparse processing unit is connected to the matrix multiplier for receiving data from the matrix multiplier; wherein the arithmetic unit further comprises a mapping unit configured to generate a mapping table between the binary sparse sequence and a position of the element in the transformed neuron matrix; wherein a K th bit of the binary sparse sequence corresponds to the element locating in the i th row and the j th column of the neuron matrix with M rows and N columns, and (i-1) × N+j=K or (j-1) × M+i=K; wherein the mapping unit is connected to the matrix multiplier for transmitting data to the matrix multiplier, and the mapping unit and the sparse processing unit are connected in a way to enable a bi-directional data communication between the mapping unit and the sparse processing unit; wherein the controller is also configured to control the matrix multiplier to perform the matrix multiplication operation according to the mapping table, wherein the element in the neuron matrix corresponding to a bit "0" in the binary sparse sequence does not perform the matrix multiplication operation. wherein the arithmetic unit comprises a shift arithmetic unit and a matrix multiplier, wherein the shift arithmetic unit is configured to perform a winograd transformation on the neuron matrix and the weight matrix respectively, so as to obtain a transformed neuron matrix and a transformed weight matrix; the matrix multiplier is configured to perform the matrix multiplication operation which multiplies the transformed neuron matrix and the transformed weight matrix together, so as to obtain a multiplication matrix; the shift arithmetic unit is further configured to perform a winograd inverse transformation on the multiplication matrix to obtain a convolution result; wherein the shift arithmetic unit and the matrix multiplier are connected in a way to enable a bi-directional data communication between the shift arithmetic unit and the matrix multiplier; wherein the controller is configured to control the shift arithmetic unit to perform the winograd transformation or the winograd inverse transformation, and control the matrix multiplier to perform the matrix multiplication operation; wherein the arithmetic unit further comprises a sparse processing unit configured to sparsely process the transformed weight matrix to generate a binary sparse sequence, wherein "0" corresponds to the element of which the value is "0" in the transformed weight matrix, and " 1" corresponds to the element of which the value is not "0" in the transformed weight matrix; wherein the sparse processing unit is connected to the matrix multiplier for receiving data from the matrix multiplier; wherein the arithmetic unit further comprises a mapping unit configured to generate a mapping table between the binary sparse sequence and a position of the element in the transformed neuron matrix; wherein a K th bit of the binary sparse sequence corresponds to the element locating in the i th row and the j th column of the neuron matrix with M rows and N columns, and (i-1) × N+j=K or (j-1) × M+i=K; wherein the mapping unit is connected to the matrix multiplier for transmitting data to the matrix multiplier, and the mapping unit and the sparse processing unit are connected in a way to enable a bi-directional data communication between the mapping unit and the sparse processing unit; wherein the controller is also configured to control the matrix multiplier to perform the matrix multiplication operation according to the mapping table, wherein the element in the neuron matrix corresponding to a bit "0" in the binary sparse sequence does not perform the matrix multiplication operation.