A high-frequency amplifier comprising: a common-source transistor that has a plurality of gate fingers (14-1 to 14-8), a plurality of drain fingers (15-1 to 15-4), and a plurality of source fingers (16-1 to 16-5), and that is configured to amplify a signal applied to each of the gate fingers (14-1 to 14-8) as a signal to be amplified, and configured to output an amplified signal from each of the drain fingers (15-1 to 15-4); a common-gate transistor that has a plurality of source fingers (33-1 to 33-8) connected to the drain fingers (15-1 to 15-4) of the common-source transistor, a plurality of drain fingers (34-1 to 34-4), and a plurality of gate fingers (35-1 to 35-8), and that is configured to amplify the amplified signal output from each of the drain fingers of the common-source transistor; a gate bus bar connected to the gate fingers (35-1 to 35-8) of the common-gate transistor; and a plurality of capacitors (39-1 to 39-8) each having a first end connected to the gate bus bar and a second end grounded, wherein the capacitors (39-1 to 39-8) are arranged at respective positions where distances from the respective gate fingers (35-1 to 35-8) of the common-gate transistor to the respective capacitors (39-1 to 39-8) related to the respective gate fingers (35-1 to 35-8) of the common-gate transistor are equal to each other, wherein impedances obtained by looking toward the respective capacitors (39-1 to 39-8) from the respective gate fingers (35-1 to 35-8) of the common-gate transistor are equal to each other, and wherein each of the capacitors (39-1 to 39-8) is disposed between each of the gate fingers (35-1 to 35-8) of the common-gate transistor and each of the source fingers (16-1 to 16-5) of the common-source transistor, wherein each of the source fingers (16-1 to 16-5) of the common-source transistor is a source electrode with an individual source via, ISV, structure having a via hole, and wherein each of the capacitors (39-1 to 39-8) are provided on the corresponding source electrode. a common-source transistor that has a plurality of gate fingers (14-1 to 14-8), a plurality of drain fingers (15-1 to 15-4), and a plurality of source fingers (16-1 to 16-5), and that is configured to amplify a signal applied to each of the gate fingers (14-1 to 14-8) as a signal to be amplified, and configured to output an amplified signal from each of the drain fingers (15-1 to 15-4); a common-gate transistor that has a plurality of source fingers (33-1 to 33-8) connected to the drain fingers (15-1 to 15-4) of the common-source transistor, a plurality of drain fingers (34-1 to 34-4), and a plurality of gate fingers (35-1 to 35-8), and that is configured to amplify the amplified signal output from each of the drain fingers of the common-source transistor; a gate bus bar connected to the gate fingers (35-1 to 35-8) of the common-gate transistor; and a plurality of capacitors (39-1 to 39-8) each having a first end connected to the gate bus bar and a second end grounded, wherein the capacitors (39-1 to 39-8) are arranged at respective positions where distances from the respective gate fingers (35-1 to 35-8) of the common-gate transistor to the respective capacitors (39-1 to 39-8) related to the respective gate fingers (35-1 to 35-8) of the common-gate transistor are equal to each other, wherein impedances obtained by looking toward the respective capacitors (39-1 to 39-8) from the respective gate fingers (35-1 to 35-8) of the common-gate transistor are equal to each other, and wherein each of the capacitors (39-1 to 39-8) is disposed between each of the gate fingers (35-1 to 35-8) of the common-gate transistor and each of the source fingers (16-1 to 16-5) of the common-source transistor, wherein each of the source fingers (16-1 to 16-5) of the common-source transistor is a source electrode with an individual source via, ISV, structure having a via hole, and wherein each of the capacitors (39-1 to 39-8) are provided on the corresponding source electrode.