A semiconductor package (10; 50; 60), comprising: at least one die pad; a plurality of outer contacts; a first semiconductor device; a second semiconductor device (15; 15'; 15'') arranged laterally adjacent the first semiconductor device, wherein the second semiconductor device (15; 15', 15'') comprises a first transistor device having a source electrode, a gate electrode and a drain electrode, the second semiconductor device (15; 15'; 15'') comprising a front surface and a rear surface, a front metallization on the front surface and a rear metallization on the rear surface, wherein the front metallization comprises a first power contact pad coupled to the source electrode, the first power contact pad being mounted on the die pad, and the rear metallization comprises a second power contact pad on the rear surface that is electrically coupled to the drain electrode and an auxiliary lateral redistribution structure that is arranged on the rear surface laterally adjacent to the second power contact pad and that is electrically insulated from the second power contact pad and the drain electrode, wherein the first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure and to an outer contact by way of the auxiliary lateral redistribution structure on the second semiconductor device, wherein the auxiliary lateral redistribution structure comprises a conductive trace (28; 64) extending into a contact pad (29, 30) at one or two ends of the conductive trace (28; 64), characterised in that the first semiconductor device comprises gate driver circuitry and is electrically coupled to the gate electrode of the first transistor device by way of the auxiliary lateral redistribution structure, and in that the second semiconductor device (15'; 15'') further comprises at least one through substrate via (55, 67, 68) extending from the rear surface to the front surface, the through substrate via (55, 67, 68) being electrically coupled to the auxiliary lateral redistribution structure on the rear surface. at least one die pad; a plurality of outer contacts; a first semiconductor device; a second semiconductor device (15; 15'; 15'') arranged laterally adjacent the first semiconductor device, wherein the second semiconductor device (15; 15', 15'') comprises a first transistor device having a source electrode, a gate electrode and a drain electrode, the second semiconductor device (15; 15'; 15'') comprising a front surface and a rear surface, a front metallization on the front surface and a rear metallization on the rear surface, wherein the front metallization comprises a first power contact pad coupled to the source electrode, the first power contact pad being mounted on the die pad, and the rear metallization comprises a second power contact pad on the rear surface that is electrically coupled to the drain electrode and an auxiliary lateral redistribution structure that is arranged on the rear surface laterally adjacent to the second power contact pad and that is electrically insulated from the second power contact pad and the drain electrode, wherein the first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure and to an outer contact by way of the auxiliary lateral redistribution structure on the second semiconductor device, wherein the auxiliary lateral redistribution structure comprises a conductive trace (28; 64) extending into a contact pad (29, 30) at one or two ends of the conductive trace (28; 64), characterised in that the first semiconductor device comprises gate driver circuitry and is electrically coupled to the gate electrode of the first transistor device by way of the auxiliary lateral redistribution structure, and in that the second semiconductor device (15'; 15'') further comprises at least one through substrate via (55, 67, 68) extending from the rear surface to the front surface, the through substrate via (55, 67, 68) being electrically coupled to the auxiliary lateral redistribution structure on the rear surface.