A computing device for processing multiple bit-sized computing tasks, the computing device comprising: a plurality of x-bit shift registers coupled in series, a number of the x-bit shift registers being gated such that an output value of an x-bit shift register is directed to a next-register output or a controller output in response to a gating signal, the next-register output being coupled to a next x-bit shift register in the series; a first n-bit operand register having a plurality of x-bit operand segments; a second n-bit operand register having a plurality of x-bit operand segments; a plurality of modular multipliers coupled to the plurality of x-bit operand segments in the first and second n-bit operand registers such that each modular multiplier is coupled to a x-bit operand segment of the first operand register and a corresponding x-bit operand segment of the second operand register; a controller coupled to the plurality of x-bit shift registers, the first n-bit operand register, the second n-bit operand register, and the plurality of modular multipliers, the controller configured to: receive a first task having y bits and a second task having z bits; divide the y-bit first task into a first plurality of x-bit segments, and the z-bit second task into a second plurality of x-bit segments; and load the first plurality of x-bit segments into a first group of shift registers of the plurality of x-bit shift registers such that each x-bit segment of the first plurality of x-bit segments is loaded into a corresponding x-bit shift register in the first group of shift registers, and the second plurality of x-bit segments into a second group of shift registers of the plurality of x-bit shift registers such that each x-bit segment of the second plurality of x-bit segments is loaded into a corresponding x-bit shift register in the second group of shift registers. a plurality of x-bit shift registers coupled in series, a number of the x-bit shift registers being gated such that an output value of an x-bit shift register is directed to a next-register output or a controller output in response to a gating signal, the next-register output being coupled to a next x-bit shift register in the series; a first n-bit operand register having a plurality of x-bit operand segments; a second n-bit operand register having a plurality of x-bit operand segments; a plurality of modular multipliers coupled to the plurality of x-bit operand segments in the first and second n-bit operand registers such that each modular multiplier is coupled to a x-bit operand segment of the first operand register and a corresponding x-bit operand segment of the second operand register; a controller coupled to the plurality of x-bit shift registers, the first n-bit operand register, the second n-bit operand register, and the plurality of modular multipliers, the controller configured to: receive a first task having y bits and a second task having z bits; divide the y-bit first task into a first plurality of x-bit segments, and the z-bit second task into a second plurality of x-bit segments; and load the first plurality of x-bit segments into a first group of shift registers of the plurality of x-bit shift registers such that each x-bit segment of the first plurality of x-bit segments is loaded into a corresponding x-bit shift register in the first group of shift registers, and the second plurality of x-bit segments into a second group of shift registers of the plurality of x-bit shift registers such that each x-bit segment of the second plurality of x-bit segments is loaded into a corresponding x-bit shift register in the second group of shift registers. receive a first task having y bits and a second task having z bits; divide the y-bit first task into a first plurality of x-bit segments, and the z-bit second task into a second plurality of x-bit segments; and load the first plurality of x-bit segments into a first group of shift registers of the plurality of x-bit shift registers such that each x-bit segment of the first plurality of x-bit segments is loaded into a corresponding x-bit shift register in the first group of shift registers, and the second plurality of x-bit segments into a second group of shift registers of the plurality of x-bit shift registers such that each x-bit segment of the second plurality of x-bit segments is loaded into a corresponding x-bit shift register in the second group of shift registers.