A display device comprising: a plurality of input ports, wherein an external input interface corresponds to each of the plurality of input ports; and a processor configured to: detect that a source device is connected through an unselected input port of the plurality of input ports; activate an external input interface corresponding to the unselected input port; perform a connection process between the source device and the external input interface; deactivate an error detection operation between the source device and the external input interface; generate fake connection information for maintaining connection between the source device and the external input interface based on information input to the external input interface from the source device; and switch the external input interface to a standby mode wherein the processor is further configured to: acquire sync information of a signal input from the source device; and acquire characteristic information of an encrypted signal input from the source device; wherein the fake connection information is generated based on the sync information and the characteristic information of the encrypted signal, wherein the external input interface includes a PHY module that is a physical layer and a LINK module that is a data link layer; and wherein the processor is further configured to, when the external input interface is switched to the standby mode: turn off a continuous time linear equalizer, CTLE, and a decision feedback equalizer, DFE, included in the PHY module; and maintain an ON state of an on-die termination, ODT, in the PHY module. a plurality of input ports, wherein an external input interface corresponds to each of the plurality of input ports; and a processor configured to: detect that a source device is connected through an unselected input port of the plurality of input ports; activate an external input interface corresponding to the unselected input port; perform a connection process between the source device and the external input interface; deactivate an error detection operation between the source device and the external input interface; generate fake connection information for maintaining connection between the source device and the external input interface based on information input to the external input interface from the source device; and switch the external input interface to a standby mode wherein the processor is further configured to: acquire sync information of a signal input from the source device; and acquire characteristic information of an encrypted signal input from the source device; wherein the fake connection information is generated based on the sync information and the characteristic information of the encrypted signal, wherein the external input interface includes a PHY module that is a physical layer and a LINK module that is a data link layer; and wherein the processor is further configured to, when the external input interface is switched to the standby mode: turn off a continuous time linear equalizer, CTLE, and a decision feedback equalizer, DFE, included in the PHY module; and maintain an ON state of an on-die termination, ODT, in the PHY module. detect that a source device is connected through an unselected input port of the plurality of input ports; activate an external input interface corresponding to the unselected input port; perform a connection process between the source device and the external input interface; deactivate an error detection operation between the source device and the external input interface; generate fake connection information for maintaining connection between the source device and the external input interface based on information input to the external input interface from the source device; and switch the external input interface to a standby mode wherein the processor is further configured to: acquire sync information of a signal input from the source device; and acquire characteristic information of an encrypted signal input from the source device; wherein the fake connection information is generated based on the sync information and the characteristic information of the encrypted signal, wherein the external input interface includes a PHY module that is a physical layer and a LINK module that is a data link layer; and wherein the processor is further configured to, when the external input interface is switched to the standby mode: turn off a continuous time linear equalizer, CTLE, and a decision feedback equalizer, DFE, included in the PHY module; and maintain an ON state of an on-die termination, ODT, in the PHY module. acquire sync information of a signal input from the source device; and acquire characteristic information of an encrypted signal input from the source device; wherein the fake connection information is generated based on the sync information and the characteristic information of the encrypted signal, wherein the external input interface includes a PHY module that is a physical layer and a LINK module that is a data link layer; and wherein the processor is further configured to, when the external input interface is switched to the standby mode: turn off a continuous time linear equalizer, CTLE, and a decision feedback equalizer, DFE, included in the PHY module; and maintain an ON state of an on-die termination, ODT, in the PHY module. turn off a continuous time linear equalizer, CTLE, and a decision feedback equalizer, DFE, included in the PHY module; and maintain an ON state of an on-die termination, ODT, in the PHY module.