A digital-to-analog converter, comprising: a first plurality of digital-to-analog converter cells (110-1,..., 110-N) configured to generate a first analog signal; a second plurality of digital-to-analog converter cells (120-1,..., 120-N) configured to generate a second analog signal, wherein the first analog signal and the second analog signal form a differential signal pair, and wherein the first plurality of digital-to-analog converter cells (110-1,..., 110-N) and the second plurality of digital-to-analog converter cells (120-1,..., 120-N) form a digital-to-analog converter core of the digital-to-analog converter; and a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells (110-1,..., 110-N), a second input node coupled to the second plurality of digital-to-analog converter cells (120-1,..., 120-N), a first output node coupled to an output node of the digital-to-analog converter, and a second output node coupled to another output node of the digital-to-analog converter, wherein the transmission line transformer is a matching network configured to present a first impedance at the first and second input nodes (131, 132) and to present a second impedance at the first output node for impedance transformation from the digital-to-analog converter core to an external load coupled to the output node and the other output node of the digital-to-analog converter, wherein the first plurality of digital-to-analog converter cells (110-1,..., 110-N), the second plurality of digital-to-analog converter cells (120-1,..., 120-N) and the transmission line transformer are integrated in a same semiconductor die. a first plurality of digital-to-analog converter cells (110-1,..., 110-N) configured to generate a first analog signal; a second plurality of digital-to-analog converter cells (120-1,..., 120-N) configured to generate a second analog signal, wherein the first analog signal and the second analog signal form a differential signal pair, and wherein the first plurality of digital-to-analog converter cells (110-1,..., 110-N) and the second plurality of digital-to-analog converter cells (120-1,..., 120-N) form a digital-to-analog converter core of the digital-to-analog converter; and a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells (110-1,..., 110-N), a second input node coupled to the second plurality of digital-to-analog converter cells (120-1,..., 120-N), a first output node coupled to an output node of the digital-to-analog converter, and a second output node coupled to another output node of the digital-to-analog converter, wherein the transmission line transformer is a matching network configured to present a first impedance at the first and second input nodes (131, 132) and to present a second impedance at the first output node for impedance transformation from the digital-to-analog converter core to an external load coupled to the output node and the other output node of the digital-to-analog converter, wherein the first plurality of digital-to-analog converter cells (110-1,..., 110-N), the second plurality of digital-to-analog converter cells (120-1,..., 120-N) and the transmission line transformer are integrated in a same semiconductor die.