Method for controlling at least two power semiconductor switches (LHS1..LHSn) connected in parallel for switching a total current (I_tot), wherein the at least two power semiconductor switches (LHS1..LHSn) connected in parallel each have a gate terminal for controlling the respective power semiconductor switch (LHS1..LHSn), comprising the following steps: providing an input terminal for feeding the total current (I_tot), an output terminal for conducting away the total current (I_tot) and a common control terminal for receiving a common control signal having the states open or close, wherein the at least two power semiconductor switches (LHS1..LHSn) connected in parallel are connected to the input terminal on the input side and to the output terminal on the output side; providing at least one ascertaining unit configured to receive the common control signal on the input side and to ascertain at least two individual control signals (SI1..SIn) depending on the common control signal for controlling the at least two power semiconductor switches (LHS1..LHSn) and, on the output side, to output the at least two individual control signals ascertained to the respective gate terminals of the at least two power semiconductor switches, wherein the at least two individual control signals (SI1..SIn) each have the states open or close and the at least two individual control signals (SI1..SIn) differ at least at times, characterized in that the loading of the power semiconductor switches (LHS1..LHSn) is determined and ascertaining an individual control signal (SI1..SIn) is carried out depending on the respective loading of the power semiconductor switch (LHS1..LHSn) to be controlled, wherein in order to determine a loading of a power semiconductor switch (LHS1..LHSn), the temperature thereof, the power loss thereof, the transmitted quantity of energy thereof or the switching frequency thereof is taken into account, and wherein ascertaining an individual control signal (SI1..SIn) is carried out depending on a cumulated loading over the entire operating time of one or of a subset of the power semiconductor switches connected in parallel (LHS1..LHSn). providing an input terminal for feeding the total current (I_tot), an output terminal for conducting away the total current (I_tot) and a common control terminal for receiving a common control signal having the states open or close, wherein the at least two power semiconductor switches (LHS1..LHSn) connected in parallel are connected to the input terminal on the input side and to the output terminal on the output side; providing at least one ascertaining unit configured to receive the common control signal on the input side and to ascertain at least two individual control signals (SI1..SIn) depending on the common control signal for controlling the at least two power semiconductor switches (LHS1..LHSn) and, on the output side, to output the at least two individual control signals ascertained to the respective gate terminals of the at least two power semiconductor switches, wherein the at least two individual control signals (SI1..SIn) each have the states open or close and the at least two individual control signals (SI1..SIn) differ at least at times, characterized in that the loading of the power semiconductor switches (LHS1..LHSn) is determined and ascertaining an individual control signal (SI1..SIn) is carried out depending on the respective loading of the power semiconductor switch (LHS1..LHSn) to be controlled, wherein in order to determine a loading of a power semiconductor switch (LHS1..LHSn), the temperature thereof, the power loss thereof, the transmitted quantity of energy thereof or the switching frequency thereof is taken into account, and wherein ascertaining an individual control signal (SI1..SIn) is carried out depending on a cumulated loading over the entire operating time of one or of a subset of the power semiconductor switches connected in parallel (LHS1..LHSn).