A three-dimensional integrated circuit structure, comprising: a first insulating layer formed over a substrate; first gate electrodes (GN, GP) formed in openings in the first dielectric layer; a first gate dielectric layer formed over the first insulating layer and the first gate electrodes (GN, GP); a first layer of graphene formed over the first gate dielectric layer; a first level of one or more field effect transistors having gate structures respectively comprising the first gate electrodes (GN, GP) and the first gate dielectric layer in contact with the first layer of graphene; a second insulating layer formed over the first level of one or more field effect transistors; second gate electrodes (GN, GP) formed in openings in the second dielectric layer; a second gate dielectric layer formed over the second insulating layer and the second gate electrodes (GN, GP); a second layer of graphene formed over the second gate dielectric layer; and a second level of one or more field effect transistors having gate structures respectively comprising the second gate electrodes (GN, GP) and the second gate dielectric layer in contact with the second layer of graphene, the second level of one or more field effect transistors electrically interconnected with the first level of one or more field effect transistors, wherein the one or more field effect transistors of the first and second levels have a bottom gate orientation relationship with respect to the associated graphene layer (214, 224); a plurality of source and drain contacts disposed on each of the first and second layers of graphene (214, 224), above the first and second gate electrodes (GN, GP) under the graphene layers (214, 224); one or more first level conductive pad structures formed adjacent the first layer of graphene such that a bottom surface of the one or more first level conductive pad structures is substantially co-planar with a bottom surface of the first gate dielectric layer; and one or more second level conductive pad structures formed adjacent the second layer of graphene such that a bottom surface of the one or more second level conductive pad structures is substantially co-planar with a bottom surface of the second gate dielectric layer; wherein the graphene is a two-dimensional planar sheet of carbon atoms arranged in a hexagonal benzene ring structure. a first insulating layer formed over a substrate; first gate electrodes (GN, GP) formed in openings in the first dielectric layer; a first gate dielectric layer formed over the first insulating layer and the first gate electrodes (GN, GP); a first layer of graphene formed over the first gate dielectric layer; a first level of one or more field effect transistors having gate structures respectively comprising the first gate electrodes (GN, GP) and the first gate dielectric layer in contact with the first layer of graphene; a second insulating layer formed over the first level of one or more field effect transistors; second gate electrodes (GN, GP) formed in openings in the second dielectric layer; a second gate dielectric layer formed over the second insulating layer and the second gate electrodes (GN, GP); a second layer of graphene formed over the second gate dielectric layer; and a second level of one or more field effect transistors having gate structures respectively comprising the second gate electrodes (GN, GP) and the second gate dielectric layer in contact with the second layer of graphene, the second level of one or more field effect transistors electrically interconnected with the first level of one or more field effect transistors, wherein the one or more field effect transistors of the first and second levels have a bottom gate orientation relationship with respect to the associated graphene layer (214, 224); a plurality of source and drain contacts disposed on each of the first and second layers of graphene (214, 224), above the first and second gate electrodes (GN, GP) under the graphene layers (214, 224); one or more first level conductive pad structures formed adjacent the first layer of graphene such that a bottom surface of the one or more first level conductive pad structures is substantially co-planar with a bottom surface of the first gate dielectric layer; and one or more second level conductive pad structures formed adjacent the second layer of graphene such that a bottom surface of the one or more second level conductive pad structures is substantially co-planar with a bottom surface of the second gate dielectric layer; wherein the graphene is a two-dimensional planar sheet of carbon atoms arranged in a hexagonal benzene ring structure.