A non-volatile memory device comprising: a first array of flash memory cells; a second array of dummy flash memory cells; and a sensing amplifier (350-0, 1100) coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising: a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell, the comparator coupled to the selected bit line through a first capacitor and to the dummy bit line through a second capacitor and comprising cross-coupled inverter pairs comprising a first pair of a PMOS transistor and an NMOS transistor and a second pair of a PMOS transistor and an NMOS transistor, wherein the first pair and second pair have different dimensions to introduce a sensing offset; a first circuit coupled to the dummy bit line and comprising a third capacitor for storing a first bias voltage and a third NMOS transistor arranged to discharge the third capacitor during the read operation, the third capacitor and the third NMOS transistor being connected in parallel between the dummy bit line and ground; and a second circuit coupled to the selected bit line and comprising a fourth capacitor for storing a second bias voltage and a fourth NMOS transistor arranged to discharge the fourth capacitor during the read operation, the fourth capacitor and the fourth NMOS transistor being connected in parallel between the selected bit line and ground; wherein the third and fourth NMOS transistors (1136, 1126) are sized together with the size of the third and fourth capacitors (1135, 1125), respectively, to make a voltage slope ramping offset between the dummy bit line and the selected bit line such that the voltage slope ramping of the dummy bit line linearly decreases between the voltage slope ramping corresponding to a programmed cell (BL'O) and the voltage slope ramping corresponding to an erased cell (BL'1). a first array of flash memory cells; a second array of dummy flash memory cells; and a sensing amplifier (350-0, 1100) coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising: a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell, the comparator coupled to the selected bit line through a first capacitor and to the dummy bit line through a second capacitor and comprising cross-coupled inverter pairs comprising a first pair of a PMOS transistor and an NMOS transistor and a second pair of a PMOS transistor and an NMOS transistor, wherein the first pair and second pair have different dimensions to introduce a sensing offset; a first circuit coupled to the dummy bit line and comprising a third capacitor for storing a first bias voltage and a third NMOS transistor arranged to discharge the third capacitor during the read operation, the third capacitor and the third NMOS transistor being connected in parallel between the dummy bit line and ground; and a second circuit coupled to the selected bit line and comprising a fourth capacitor for storing a second bias voltage and a fourth NMOS transistor arranged to discharge the fourth capacitor during the read operation, the fourth capacitor and the fourth NMOS transistor being connected in parallel between the selected bit line and ground; wherein the third and fourth NMOS transistors (1136, 1126) are sized together with the size of the third and fourth capacitors (1135, 1125), respectively, to make a voltage slope ramping offset between the dummy bit line and the selected bit line such that the voltage slope ramping of the dummy bit line linearly decreases between the voltage slope ramping corresponding to a programmed cell (BL'O) and the voltage slope ramping corresponding to an erased cell (BL'1). a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell, the comparator coupled to the selected bit line through a first capacitor and to the dummy bit line through a second capacitor and comprising cross-coupled inverter pairs comprising a first pair of a PMOS transistor and an NMOS transistor and a second pair of a PMOS transistor and an NMOS transistor, wherein the first pair and second pair have different dimensions to introduce a sensing offset; a first circuit coupled to the dummy bit line and comprising a third capacitor for storing a first bias voltage and a third NMOS transistor arranged to discharge the third capacitor during the read operation, the third capacitor and the third NMOS transistor being connected in parallel between the dummy bit line and ground; and a second circuit coupled to the selected bit line and comprising a fourth capacitor for storing a second bias voltage and a fourth NMOS transistor arranged to discharge the fourth capacitor during the read operation, the fourth capacitor and the fourth NMOS transistor being connected in parallel between the selected bit line and ground; wherein the third and fourth NMOS transistors (1136, 1126) are sized together with the size of the third and fourth capacitors (1135, 1125), respectively, to make a voltage slope ramping offset between the dummy bit line and the selected bit line such that the voltage slope ramping of the dummy bit line linearly decreases between the voltage slope ramping corresponding to a programmed cell (BL'O) and the voltage slope ramping corresponding to an erased cell (BL'1).