A memory system comprising: a. a memory bus having a plurality of system data lines (DQ3, DQ2, DQ1, DQ0); and b. at least one memory module (300, 400, 450, 500, 620, 625) having: i. a plurality of module pins (510, 640) connected to respective ones of the system data lines (DQ3, DQ2, DQ1, DQ0); ii. a plurality of memory banks (PB0,..., PB7); iii. configuration and control logic connected to the memory banks (PB0,..., PB7) and adapted to configure the memory banks (PB0,..., PB7) to form one of several memory-width configurations; and iv. a switch matrix (315, 460) connected between the memory banks (PB0,..., PB7) and the plurality of module pins (510, 640), the switch matrix (315, 460) adapted to programmably connect the memory banks (PB0,..., PB7) to all or a subset of the system data pins; c. a memory controller (605, 905) adapted to sense the number of memory modules (300, 400, 450, 500, 620, 625) in the system, wherein the memory controller (605, 905) automatically alters the memory-width configuration of each memory module (300, 400, 450, 500, 620, 625) in response to changes in the number of memory modules (300, 400, 450, 500, 620, 625), wherein doubling the number of memory modules (300, 400, 450, 500, 620, 625) in the system automatically halves the memory-width configuration for each module (300, 400, 450, 500, 620, 625). a. a memory bus having a plurality of system data lines (DQ3, DQ2, DQ1, DQ0); and b. at least one memory module (300, 400, 450, 500, 620, 625) having: i. a plurality of module pins (510, 640) connected to respective ones of the system data lines (DQ3, DQ2, DQ1, DQ0); ii. a plurality of memory banks (PB0,..., PB7); iii. configuration and control logic connected to the memory banks (PB0,..., PB7) and adapted to configure the memory banks (PB0,..., PB7) to form one of several memory-width configurations; and iv. a switch matrix (315, 460) connected between the memory banks (PB0,..., PB7) and the plurality of module pins (510, 640), the switch matrix (315, 460) adapted to programmably connect the memory banks (PB0,..., PB7) to all or a subset of the system data pins; i. a plurality of module pins (510, 640) connected to respective ones of the system data lines (DQ3, DQ2, DQ1, DQ0); ii. a plurality of memory banks (PB0,..., PB7); iii. configuration and control logic connected to the memory banks (PB0,..., PB7) and adapted to configure the memory banks (PB0,..., PB7) to form one of several memory-width configurations; and iv. a switch matrix (315, 460) connected between the memory banks (PB0,..., PB7) and the plurality of module pins (510, 640), the switch matrix (315, 460) adapted to programmably connect the memory banks (PB0,..., PB7) to all or a subset of the system data pins; c. a memory controller (605, 905) adapted to sense the number of memory modules (300, 400, 450, 500, 620, 625) in the system, wherein the memory controller (605, 905) automatically alters the memory-width configuration of each memory module (300, 400, 450, 500, 620, 625) in response to changes in the number of memory modules (300, 400, 450, 500, 620, 625), wherein doubling the number of memory modules (300, 400, 450, 500, 620, 625) in the system automatically halves the memory-width configuration for each module (300, 400, 450, 500, 620, 625).