A circuit comprising: a control block configured to generate a common control signal, wherein the control block is further configured to receive a program signal, and the control block is configured to generate the common control signal based on the program signal; an oscillator configured to generate a reference clock signal, the oscillator including a plurality of delay elements in a relaxation oscillator configuration, each delay element of the oscillator being configured to receive the common control signal and to introduce a delay in the reference clock signal based on the common control signal, the delay elements of the oscillator being collectively arranged so as to generate the reference clock signal when the oscillator is oscillating; and a delay block configured to receive a data clock signal and to generate a delayed clock signal, the delay block including one or more delay elements, each delay element of the delay block being configured to receive the common control signal and to introduce a delay in the data clock signal based on the common control signal, the delay elements of the delay block being arranged so as to delay the data clock signal to generate the delayed clock signal, and wherein the delay elements of the oscillator are in a delay-based ring oscillator configuration, characterised in that: the circuit further comprises an inverting logic gate configured to receive as input an enable signal and the reference clock signal, the output of the inverting logic gate being coupled to a first one of the delay elements of the oscillator, the enable signal being configured to trigger oscillation of the oscillator. a control block configured to generate a common control signal, wherein the control block is further configured to receive a program signal, and the control block is configured to generate the common control signal based on the program signal; an oscillator configured to generate a reference clock signal, the oscillator including a plurality of delay elements in a relaxation oscillator configuration, each delay element of the oscillator being configured to receive the common control signal and to introduce a delay in the reference clock signal based on the common control signal, the delay elements of the oscillator being collectively arranged so as to generate the reference clock signal when the oscillator is oscillating; and a delay block configured to receive a data clock signal and to generate a delayed clock signal, the delay block including one or more delay elements, each delay element of the delay block being configured to receive the common control signal and to introduce a delay in the data clock signal based on the common control signal, the delay elements of the delay block being arranged so as to delay the data clock signal to generate the delayed clock signal, and wherein the delay elements of the oscillator are in a delay-based ring oscillator configuration, characterised in that: the circuit further comprises an inverting logic gate configured to receive as input an enable signal and the reference clock signal, the output of the inverting logic gate being coupled to a first one of the delay elements of the oscillator, the enable signal being configured to trigger oscillation of the oscillator. the circuit further comprises an inverting logic gate configured to receive as input an enable signal and the reference clock signal, the output of the inverting logic gate being coupled to a first one of the delay elements of the oscillator, the enable signal being configured to trigger oscillation of the oscillator.