A printed circuit board (100, 200, 300) comprising: a first semiconductor package (1, 28, 42) including a first plurality of ball electrodes (12, 32, 50) and a second plurality of ball electrodes (13, 33, 53); a second semiconductor package (2, 29, 43) including a third plurality of ball electrodes (14, 34, 54) and a fourth plurality of ball electrodes (15, 35, 57) and transmitting a bus signal to the first semiconductor package (1, 28, 42); a printed wiring board (101, 201, 301) in which the first semiconductor package (1, 28, 42) is mounted on a first surface layer (102, 205, 302) via the first and second pluralities of ball electrodes (12, 32, 50, 13, 33, 53) and the second semiconductor package (2, 29, 43) is mounted on a second surface layer (103, 204, 303) via the third and fourth pluralities of ball electrodes (14, 34, 54, 15, 35, 57); a plurality of first bus wirings (17, 40, 64) formed on a second signal layer (103, 203, 303) of the printed wiring board (101, 201, 301), the plurality of first bus wirings (17, 40, 64) being connected to a plurality of first via holes (16, 36, 58), which is prepared in mounting area of the first semiconductor package (1, 28, 42); and a plurality of second bus wirings (18, 41, 67) formed on a first signal layer (102, 202, 302) of the printed wiring board (101, 201, 301), the plurality of second bus wirings (18, 41, 67) being connected to a plurality of second via holes (19, 39, 63), which is prepared in mounting area of the second semiconductor package (2, 29, 43), wherein the first plurality of ball electrodes (12, 32, 50) of the first semiconductor package (1, 28, 42) is connected to the third plurality of ball electrodes (14, 34, 54) of the second semiconductor package (2, 29, 43) via the plurality of first via holes (16, 36, 58) and the plurality of first bus wirings (17, 40, 64), wherein the second plurality of ball electrodes (13, 33, 53) of the first semiconductor package (1, 28, 42) is connected to the fourth plurality of ball electrodes (15, 35, 57) of the second semiconductor package (2, 29, 43) via the plurality of second bus wirings (18, 41, 67) and the plurality of second via holes (19, 39, 63), characterized in that the second plurality of ball electrodes (13, 33, 53) is arranged on an outer circumference side of the first semiconductor package (1, 28, 42) with respect to the first plurality of ball electrodes (12, 32, 50), which is closer to the second semiconductor package (2, 29, 43), and the fourth plurality of ball electrodes (15, 35, 57) is arranged on an inner circumference side of the second semiconductor package (2, 29, 43) with respect to the third plurality of ball electrodes (14, 34, 54), which is farther away from the first semiconductor package (1, 28, 42). a first semiconductor package (1, 28, 42) including a first plurality of ball electrodes (12, 32, 50) and a second plurality of ball electrodes (13, 33, 53); a second semiconductor package (2, 29, 43) including a third plurality of ball electrodes (14, 34, 54) and a fourth plurality of ball electrodes (15, 35, 57) and transmitting a bus signal to the first semiconductor package (1, 28, 42); a printed wiring board (101, 201, 301) in which the first semiconductor package (1, 28, 42) is mounted on a first surface layer (102, 205, 302) via the first and second pluralities of ball electrodes (12, 32, 50, 13, 33, 53) and the second semiconductor package (2, 29, 43) is mounted on a second surface layer (103, 204, 303) via the third and fourth pluralities of ball electrodes (14, 34, 54, 15, 35, 57); a plurality of first bus wirings (17, 40, 64) formed on a second signal layer (103, 203, 303) of the printed wiring board (101, 201, 301), the plurality of first bus wirings (17, 40, 64) being connected to a plurality of first via holes (16, 36, 58), which is prepared in mounting area of the first semiconductor package (1, 28, 42); and a plurality of second bus wirings (18, 41, 67) formed on a first signal layer (102, 202, 302) of the printed wiring board (101, 201, 301), the plurality of second bus wirings (18, 41, 67) being connected to a plurality of second via holes (19, 39, 63), which is prepared in mounting area of the second semiconductor package (2, 29, 43), wherein the first plurality of ball electrodes (12, 32, 50) of the first semiconductor package (1, 28, 42) is connected to the third plurality of ball electrodes (14, 34, 54) of the second semiconductor package (2, 29, 43) via the plurality of first via holes (16, 36, 58) and the plurality of first bus wirings (17, 40, 64), wherein the second plurality of ball electrodes (13, 33, 53) of the first semiconductor package (1, 28, 42) is connected to the fourth plurality of ball electrodes (15, 35, 57) of the second semiconductor package (2, 29, 43) via the plurality of second bus wirings (18, 41, 67) and the plurality of second via holes (19, 39, 63), characterized in that the second plurality of ball electrodes (13, 33, 53) is arranged on an outer circumference side of the first semiconductor package (1, 28, 42) with respect to the first plurality of ball electrodes (12, 32, 50), which is closer to the second semiconductor package (2, 29, 43), and the fourth plurality of ball electrodes (15, 35, 57) is arranged on an inner circumference side of the second semiconductor package (2, 29, 43) with respect to the third plurality of ball electrodes (14, 34, 54), which is farther away from the first semiconductor package (1, 28, 42).