Apparatus for data processing, said apparatus comprising: a shifting circuit; an arithmetic circuit; a promotion circuit; and an instruction decoder responsive to a single instruction multiple data (SIMD) instruction to control said shifting circuit, said arithmetic circuit and said promotion circuit to perform an operation upon a first input operand data word Rm and a second different input operand data word Rn, wherein said operation yields a value given by: selecting a plurality of non-adjacent multibit portions of said first input operand data word Rm to form a plurality of multibit portions each of bit length A; in dependence on whether the SIMD instruction specifies a parameter indicating that an optional shift is to be applied, optionally shifting said plurality of non-adjacent multibit portions by a common shift amount to shifted bit positions; promoting in length each of said plurality of non-adjacent multibit portions from said bit length of A to a bit length of B using one of a zero extension and a sign extension to form a plurality of promoted multibit portions, wherein said promoted multibit portions may be abutted to form a promoted data word P; and performing a plurality of independent SIMD arithmetic operations using as input operands respective bit position portions of bit length B from both said promoted data word P and said second different input operand data word Rn to form a result data word Rd. a shifting circuit; an arithmetic circuit; a promotion circuit; and an instruction decoder responsive to a single instruction multiple data (SIMD) instruction to control said shifting circuit, said arithmetic circuit and said promotion circuit to perform an operation upon a first input operand data word Rm and a second different input operand data word Rn, wherein said operation yields a value given by: selecting a plurality of non-adjacent multibit portions of said first input operand data word Rm to form a plurality of multibit portions each of bit length A; in dependence on whether the SIMD instruction specifies a parameter indicating that an optional shift is to be applied, optionally shifting said plurality of non-adjacent multibit portions by a common shift amount to shifted bit positions; promoting in length each of said plurality of non-adjacent multibit portions from said bit length of A to a bit length of B using one of a zero extension and a sign extension to form a plurality of promoted multibit portions, wherein said promoted multibit portions may be abutted to form a promoted data word P; and performing a plurality of independent SIMD arithmetic operations using as input operands respective bit position portions of bit length B from both said promoted data word P and said second different input operand data word Rn to form a result data word Rd. selecting a plurality of non-adjacent multibit portions of said first input operand data word Rm to form a plurality of multibit portions each of bit length A; in dependence on whether the SIMD instruction specifies a parameter indicating that an optional shift is to be applied, optionally shifting said plurality of non-adjacent multibit portions by a common shift amount to shifted bit positions; promoting in length each of said plurality of non-adjacent multibit portions from said bit length of A to a bit length of B using one of a zero extension and a sign extension to form a plurality of promoted multibit portions, wherein said promoted multibit portions may be abutted to form a promoted data word P; and performing a plurality of independent SIMD arithmetic operations using as input operands respective bit position portions of bit length B from both said promoted data word P and said second different input operand data word Rn to form a result data word Rd.