An integrated circuit (101; 101') comprising: · a safety processor; · a memory; and · a secure computing module, comprising: - a secure processor; - first and second cryptographic units (133, 134) for encrypting and decrypting data in the memory; and - first and second data transfer units (128, 129) for transferring data between the memory and the first and second cryptographic units respectively; wherein the first cryptographic unit and the first data transfer unit provide a first cryptographic data handling system, and the second cryptographic unit and the second data transfer unit provide a second cryptographic data handling system; the integrated circuit further comprising: · a switch; and the secure computing module further comprises: - selector circuitry for selectively coupling and uncoupling the first and second cryptographic data handling systems in response to control signals from the switch, such that: in a first mode, the first and second cryptographic data handling systems are uncoupled and operable independently of each other; and in a second mode, the first and second cryptographic data handling system are coupled and operable together to provide hardware redundancy. · a safety processor; · a memory; and · a secure computing module, comprising: - a secure processor; - first and second cryptographic units (133, 134) for encrypting and decrypting data in the memory; and - first and second data transfer units (128, 129) for transferring data between the memory and the first and second cryptographic units respectively; wherein the first cryptographic unit and the first data transfer unit provide a first cryptographic data handling system, and the second cryptographic unit and the second data transfer unit provide a second cryptographic data handling system; the integrated circuit further comprising: · a switch; and the secure computing module further comprises: - selector circuitry for selectively coupling and uncoupling the first and second cryptographic data handling systems in response to control signals from the switch, such that: in a first mode, the first and second cryptographic data handling systems are uncoupled and operable independently of each other; and in a second mode, the first and second cryptographic data handling system are coupled and operable together to provide hardware redundancy. - a secure processor; - first and second cryptographic units (133, 134) for encrypting and decrypting data in the memory; and - first and second data transfer units (128, 129) for transferring data between the memory and the first and second cryptographic units respectively; the integrated circuit further comprising: · a switch; · a switch; and the secure computing module further comprises: - selector circuitry for selectively coupling and uncoupling the first and second cryptographic data handling systems in response to control signals from the switch, such that: in a first mode, the first and second cryptographic data handling systems are uncoupled and operable independently of each other; and in a second mode, the first and second cryptographic data handling system are coupled and operable together to provide hardware redundancy. - selector circuitry for selectively coupling and uncoupling the first and second cryptographic data handling systems in response to control signals from the switch, such that: in a first mode, the first and second cryptographic data handling systems are uncoupled and operable independently of each other; and in a second mode, the first and second cryptographic data handling system are coupled and operable together to provide hardware redundancy. in a first mode, the first and second cryptographic data handling systems are uncoupled and operable independently of each other; and in a second mode, the first and second cryptographic data handling system are coupled and operable together to provide hardware redundancy.