A power amplifier comprising: - a first transistor (M H) having a first main channel coupled between a positive power supply terminal (V dd) and an output terminal (V out), said first transistor having a control terminal configured to be driven by a first gate signal (V gatehigh) provided by a high driver circuit, which is configured to be biased from a bootstrap voltage at a first voltage terminal (V boot), - a bootstrap capacitor (C boot) coupled between the first voltage terminal (V boot) and the output terminal (V out), - a second transistor (M L) having a second main channel coupled between the output terminal (V out) and a negative power supply terminal (V ss), said second transistor having a second control terminal configured to be driven by a second gate signal (V gatelow) provided by a low driver circuit, which is configured to be biased from a regulated source at a second voltage terminal (V reg), - a switch circuit coupled between the first voltage terminal (V boot) and the second voltage terminal (V reg), said switch circuit configured to be controlled by the second gate signal (V gatelow); comprising a third transistor (M boot) having a third main channel directly coupled between the first voltage terminal (V boot) and the second voltage terminal (V reg) said third transistor (M boot) having a third gate terminal (V b); and - a latch circuit configured to be controlled by the second gate signal (V gatelow) and having an output configured to drive the third gate terminal (V b), said latch circuit comprising: - a first inverter having a first inverter input coupled to the third gate terminal (V b) and a first inverter output coupled to an intermediate node (V a), and - a second inverter having a second inverter input terminal coupled to the intermediate node (V a) and a second inverter output coupled to the third gate terminal (V b). - a first transistor (M H) having a first main channel coupled between a positive power supply terminal (V dd) and an output terminal (V out), said first transistor having a control terminal configured to be driven by a first gate signal (V gatehigh) provided by a high driver circuit, which is configured to be biased from a bootstrap voltage at a first voltage terminal (V boot), - a bootstrap capacitor (C boot) coupled between the first voltage terminal (V boot) and the output terminal (V out), - a second transistor (M L) having a second main channel coupled between the output terminal (V out) and a negative power supply terminal (V ss), said second transistor having a second control terminal configured to be driven by a second gate signal (V gatelow) provided by a low driver circuit, which is configured to be biased from a regulated source at a second voltage terminal (V reg), - a switch circuit coupled between the first voltage terminal (V boot) and the second voltage terminal (V reg), said switch circuit configured to be controlled by the second gate signal (V gatelow); comprising a third transistor (M boot) having a third main channel directly coupled between the first voltage terminal (V boot) and the second voltage terminal (V reg) said third transistor (M boot) having a third gate terminal (V b); and - a latch circuit configured to be controlled by the second gate signal (V gatelow) and having an output configured to drive the third gate terminal (V b), said latch circuit comprising: - a first inverter having a first inverter input coupled to the third gate terminal (V b) and a first inverter output coupled to an intermediate node (V a), and - a second inverter having a second inverter input terminal coupled to the intermediate node (V a) and a second inverter output coupled to the third gate terminal (V b). - a first inverter having a first inverter input coupled to the third gate terminal (V b) and a first inverter output coupled to an intermediate node (V a), and - a second inverter having a second inverter input terminal coupled to the intermediate node (V a) and a second inverter output coupled to the third gate terminal (V b).