An image sensor comprising: a pixel array including a plurality of pixels arranged in rows and columns, wherein the pixels in each column are electrically connected to a column output line; a plurality of sample and hold circuits (516, 63-66) each sample and hold circuit (516, 63-66) being electrically connected to a respective column output line, wherein each sample and hold circuit (516, 63-66) includes a first capacitor for receiving a signal voltage and a second capacitor for receiving a reset voltage; a plurality of pairs of buffer amplifiers (624, 626, 704, 706, 708, 710) with each pair of buffer amplifiers (624, 626) being electrically connected to a distinct group of four or more sample and hold circuits so that a first buffer amplifier (626, 704, 708) in the pair of buffer amplifiers is electrically connected to a first portion of the sample and hold circuits (516a, 63, 65) in the group, and so that a second buffer amplifier (624, 706, 710) in each pair of buffer amplifiers is electrically connected to a second portion of the sample and hold circuits (516b, 64, 66) in the group, wherein the sample-and-hold circuits (516, 63-66) are divided into M groups with M being an integer greater than one; a first global bus (528a, 714) for receiving signal and reset voltages from at least a portion of the first buffer amplifiers (626, 704) in the plurality of pairs of buffer amplifiers (624, 626, 704, 706, 708, 710); and a second global bus (528b, 718) for receiving signal and reset voltages from at least a portion of the second buffer amplifiers (624, 708) in the plurality of pairs of buffer amplifiers (624, 626, 704, 706, 708, 710); a first differential amplifier (604, 800) electrically connected to the first global bus (528a, 714) for receiving a signal voltage and a reset voltage from the first global bus (528a, 714) and for determining a difference between the signal voltage and the reset voltage from the first global bus (528a, 714); a second differential amplifier (606, 802) electrically connected to the second global bus (528b, 718) for receiving a signal voltage and a reset voltage from the second global bus (528b, 718) and for determining a difference between the signal voltage and the reset voltage from the second global bus (528b, 718). a pixel array including a plurality of pixels arranged in rows and columns, wherein the pixels in each column are electrically connected to a column output line; a plurality of sample and hold circuits (516, 63-66) each sample and hold circuit (516, 63-66) being electrically connected to a respective column output line, wherein each sample and hold circuit (516, 63-66) includes a first capacitor for receiving a signal voltage and a second capacitor for receiving a reset voltage; a plurality of pairs of buffer amplifiers (624, 626, 704, 706, 708, 710) with each pair of buffer amplifiers (624, 626) being electrically connected to a distinct group of four or more sample and hold circuits so that a first buffer amplifier (626, 704, 708) in the pair of buffer amplifiers is electrically connected to a first portion of the sample and hold circuits (516a, 63, 65) in the group, and so that a second buffer amplifier (624, 706, 710) in each pair of buffer amplifiers is electrically connected to a second portion of the sample and hold circuits (516b, 64, 66) in the group, wherein the sample-and-hold circuits (516, 63-66) are divided into M groups with M being an integer greater than one; a first global bus (528a, 714) for receiving signal and reset voltages from at least a portion of the first buffer amplifiers (626, 704) in the plurality of pairs of buffer amplifiers (624, 626, 704, 706, 708, 710); and a second global bus (528b, 718) for receiving signal and reset voltages from at least a portion of the second buffer amplifiers (624, 708) in the plurality of pairs of buffer amplifiers (624, 626, 704, 706, 708, 710); a first differential amplifier (604, 800) electrically connected to the first global bus (528a, 714) for receiving a signal voltage and a reset voltage from the first global bus (528a, 714) and for determining a difference between the signal voltage and the reset voltage from the first global bus (528a, 714); a second differential amplifier (606, 802) electrically connected to the second global bus (528b, 718) for receiving a signal voltage and a reset voltage from the second global bus (528b, 718) and for determining a difference between the signal voltage and the reset voltage from the second global bus (528b, 718).