An apparatus, comprising: a processor; a memory coupled to the processor; and a memory manager configured to be operated by the processor to: ascertain that a first interval of the memory is free; modify a state of the first interval of the memory to indicate that the first interval of the memory is in a coalescing state; determine whether a second interval of the memory, immediately preceding or immediately following the first interval of the memory, is free; after a determination that the second interval of the memory is free, modify a state of the second interval of the memory to indicate that the second interval of the memory is in a coalescing state; and coalesce the first interval of the memory and the second interval of the memory, wherein the memory manager is further configured to determine, from a header associated with the first interval of the memory, whether the second interval of the memory is free, in use, or in a coalescing state; after a determination that the second interval of the memory is in a coalescing state, insert an identification of the first interval of the memory into a coalesce queue to temporarily delay coalesce of the first and second intervals of the memory; and after a determination that the second interval of the memory is no longer in a coalescing state, remove the first interval of the memory from the coalesce queue and, if the second interval of the memory has transitioned from the in coalescing state to being free, enable a coalesce operation to coalesce the first and second intervals of the memory to proceed. a processor; a memory coupled to the processor; and a memory manager configured to be operated by the processor to: ascertain that a first interval of the memory is free; modify a state of the first interval of the memory to indicate that the first interval of the memory is in a coalescing state; determine whether a second interval of the memory, immediately preceding or immediately following the first interval of the memory, is free; after a determination that the second interval of the memory is free, modify a state of the second interval of the memory to indicate that the second interval of the memory is in a coalescing state; and coalesce the first interval of the memory and the second interval of the memory, wherein the memory manager is further configured to determine, from a header associated with the first interval of the memory, whether the second interval of the memory is free, in use, or in a coalescing state; after a determination that the second interval of the memory is in a coalescing state, insert an identification of the first interval of the memory into a coalesce queue to temporarily delay coalesce of the first and second intervals of the memory; and after a determination that the second interval of the memory is no longer in a coalescing state, remove the first interval of the memory from the coalesce queue and, if the second interval of the memory has transitioned from the in coalescing state to being free, enable a coalesce operation to coalesce the first and second intervals of the memory to proceed. ascertain that a first interval of the memory is free; modify a state of the first interval of the memory to indicate that the first interval of the memory is in a coalescing state; determine whether a second interval of the memory, immediately preceding or immediately following the first interval of the memory, is free; after a determination that the second interval of the memory is free, modify a state of the second interval of the memory to indicate that the second interval of the memory is in a coalescing state; and coalesce the first interval of the memory and the second interval of the memory, wherein the memory manager is further configured to determine, from a header associated with the first interval of the memory, whether the second interval of the memory is free, in use, or in a coalescing state; after a determination that the second interval of the memory is in a coalescing state, insert an identification of the first interval of the memory into a coalesce queue to temporarily delay coalesce of the first and second intervals of the memory; and after a determination that the second interval of the memory is no longer in a coalescing state, remove the first interval of the memory from the coalesce queue and, if the second interval of the memory has transitioned from the in coalescing state to being free, enable a coalesce operation to coalesce the first and second intervals of the memory to proceed.