A method for generating a calibrated clock signal, in an integrated circuit wherein the method comprises the steps of: - providing at least one oscillator signal (φ to φ(2 i -1)) having a plurality of phase signals in an oscillator signal time period such that two successive phase signals of said oscillator signal are separated by a basic Step of Time, said oscillator signal having oscillator periods corresponding to a free running frequency; - computing a calibrated value equal to an average number of Steps of Time in a bit period inside a received flow of bits by measuring on a USB data bus the number of the oscillator periods between two consecutive USB Start of Frame in the received flow of bits and by computing said average number by performing a division of the measured number of oscillator periods by the number of separating bits and by multiplying the result by the number of phase signals of the oscillator signal time period; - generating a counting value current value by adding to said calibrated value a previous value of said counting value; - computing an integer part and a fractional part of said counting value current value; - generating a clock signal active edge in phase with at least said one oscillator signal (φ to φ(2 i -1)), timely separated from a previous clock signal active edge by a time duration equal to the Step of Time multiplied by said integer part of said counting value current value; - computing a time delay equal to the Step of Time multiplied by said fractional part of said counting value current value; and - from said clock signal, obtaining the calibrated clock signal by delaying the generated active edge of the clock signal by said computed delay, wherein the delaying of the clock signal is made by providing a plurality of delayed signals (D 0 to D M+L) each delayed signals being delayed from one to each other of an elementary delay, and by selecting one of said plurality of delayed signals for obtaining the calibrated clock signal, wherein the elementary delay is calibrated in a calibration mode including the following steps: - measuring the maximum number (k) of elementary delays that can be added for having a total delay inferior to a Step of Time; and - storing the measured maximum number (k), and wherein the computing of the delay is made by the multiplication of the fractional number of Step of Time by the maximum number. - providing at least one oscillator signal (φ to φ(2 i -1)) having a plurality of phase signals in an oscillator signal time period such that two successive phase signals of said oscillator signal are separated by a basic Step of Time, said oscillator signal having oscillator periods corresponding to a free running frequency; - computing a calibrated value equal to an average number of Steps of Time in a bit period inside a received flow of bits by measuring on a USB data bus the number of the oscillator periods between two consecutive USB Start of Frame in the received flow of bits and by computing said average number by performing a division of the measured number of oscillator periods by the number of separating bits and by multiplying the result by the number of phase signals of the oscillator signal time period; - generating a counting value current value by adding to said calibrated value a previous value of said counting value; - computing an integer part and a fractional part of said counting value current value; - generating a clock signal active edge in phase with at least said one oscillator signal (φ to φ(2 i -1)), timely separated from a previous clock signal active edge by a time duration equal to the Step of Time multiplied by said integer part of said counting value current value; - computing a time delay equal to the Step of Time multiplied by said fractional part of said counting value current value; and - from said clock signal, obtaining the calibrated clock signal by delaying the generated active edge of the clock signal by said computed delay, wherein the delaying of the clock signal is made by providing a plurality of delayed signals (D 0 to D M+L) each delayed signals being delayed from one to each other of an elementary delay, and by selecting one of said plurality of delayed signals for obtaining the calibrated clock signal, wherein the elementary delay is calibrated in a calibration mode including the following steps: - measuring the maximum number (k) of elementary delays that can be added for having a total delay inferior to a Step of Time; and - storing the measured maximum number (k),