An electronic device (301; 401) in which acceleration of data processing operations is provided, which device comprises: - storage areas (304; 404) to which access is restricted, - a processor (303;403) configured to operate either in a normal execution mode or a secure execution mode, and - an accelerator (311; 411) for accelerating data processing operations, which accelerator (311; 411) is arranged with: - a first logical interface (312; 412) over which data to be processed is provided to the accelerator by applications executed in a processing means in the device, and - a secure second logical interface (312; 414) over which cryptographic keys stored in the storage areas and employed in the operation of processing said data are provided to the accelerator by protected applications executed by the processor (303; 403) when in secure execution mode, wherein the accelerator (311; 411) is arranged such that the first logical interface and the secure second logical interface share the same physical interface or are provided via respective physical interfaces (412, 414); wherein the accelerator (311; 411) is located outside the storage areas (304; 404) to prevent entries/exits to the storage areas (304; 404) every time data is encrypted/decrypted by the accelerator; wherein the first logical interface (312; 412) of the accelerator (311; 411) is arranged such that it is accessible by any application, while the secure second logical interface (312; 414) of the accelerator (311; 411) is arranged such that it is accessible by the protected applications only, and wherein in the secure execution mode, only the protected applications are allowed to be executed by the processor. - storage areas (304; 404) to which access is restricted, - a processor (303;403) configured to operate either in a normal execution mode or a secure execution mode, and - an accelerator (311; 411) for accelerating data processing operations, which accelerator (311; 411) is arranged with: - a first logical interface (312; 412) over which data to be processed is provided to the accelerator by applications executed in a processing means in the device, and - a secure second logical interface (312; 414) over which cryptographic keys stored in the storage areas and employed in the operation of processing said data are provided to the accelerator by protected applications executed by the processor (303; 403) when in secure execution mode, wherein the accelerator (311; 411) is arranged such that the first logical interface and the secure second logical interface share the same physical interface or are provided via respective physical interfaces (412, 414); wherein the accelerator (311; 411) is located outside the storage areas (304; 404) to prevent entries/exits to the storage areas (304; 404) every time data is encrypted/decrypted by the accelerator; wherein the first logical interface (312; 412) of the accelerator (311; 411) is arranged such that it is accessible by any application, while the secure second logical interface (312; 414) of the accelerator (311; 411) is arranged such that it is accessible by the protected applications only, and wherein in the secure execution mode, only the protected applications are allowed to be executed by the processor. - a first logical interface (312; 412) over which data to be processed is provided to the accelerator by applications executed in a processing means in the device, and - a secure second logical interface (312; 414) over which cryptographic keys stored in the storage areas and employed in the operation of processing said data are provided to the accelerator by protected applications executed by the processor (303; 403) when in secure execution mode,