A semiconductor device comprising: a memory cell array arranged in a matrix; a plurality of word lines provided corresponding to each row of the matrix of the memory cell array; a word driver configured to drive one of the word lines; a plurality of row selecting lines coupled to the word driver; a row decoder configured to output a row selection signal to the plurality of row selection lines based on input row address information, the word driver being configured to select one of the word lines according to the row selection signal; a first row encoder coupled to the word lines and configured to generate first row address information based on signal levels of the word lines; a second row encoder coupled to the word lines and configured to generate second row address information which is complementary to the first row address information; a first row determination circuit configured to output a first row determination signal (RFLG) based on comparison between the first row address information and the second row address information; a plurality of bit lines provided corresponding to each column of the matrix of the memory cell array; a column selecting circuit configured to select one of the bit lines; a plurality of column selecting lines coupled to the column selecting circuit; a column decoder configured to output column selecting signals to the column selecting lines based on input column address information; characterised by further comprising a first column encoder coupled to the column selecting lines and configured to output first column address information based on signal levels of the column selecting lines; a second column encoder coupled to the column selecting lines and configured to output second column address information which is complementary to the first column address information based on signal levels of the column selecting lines; and a first column determination circuit configured to output a first column determination signal (CFLG) based on comparison between the first column address information and the second column address information. a memory cell array arranged in a matrix; a plurality of word lines provided corresponding to each row of the matrix of the memory cell array; a word driver configured to drive one of the word lines; a plurality of row selecting lines coupled to the word driver; a row decoder configured to output a row selection signal to the plurality of row selection lines based on input row address information, the word driver being configured to select one of the word lines according to the row selection signal; a first row encoder coupled to the word lines and configured to generate first row address information based on signal levels of the word lines; a second row encoder coupled to the word lines and configured to generate second row address information which is complementary to the first row address information; a first row determination circuit configured to output a first row determination signal (RFLG) based on comparison between the first row address information and the second row address information; a plurality of bit lines provided corresponding to each column of the matrix of the memory cell array; a column selecting circuit configured to select one of the bit lines; a plurality of column selecting lines coupled to the column selecting circuit; a column decoder configured to output column selecting signals to the column selecting lines based on input column address information; characterised by further comprising a first column encoder coupled to the column selecting lines and configured to output first column address information based on signal levels of the column selecting lines; a second column encoder coupled to the column selecting lines and configured to output second column address information which is complementary to the first column address information based on signal levels of the column selecting lines; and a first column determination circuit configured to output a first column determination signal (CFLG) based on comparison between the first column address information and the second column address information.