Apparatus for data processing comprising: processing circuitry (16, 18) to execute data processing instructions to perform data processing operations, wherein the data processing operations comprise accessing a memory system, and wherein the processing circuitry is capable of executing the data processing instructions in a plurality of virtual machine contexts; and memory system interaction circuitry (56, 58, 60, 62) to provide an interface between the processing circuitry and the memory system, wherein the memory system interaction circuitry is capable of, in response to the processing circuitry executing a barrier instruction in a current context of the plurality of contexts, enforcing an access ordering constraint, wherein the memory system interaction circuitry comprises a store buffer to buffer pending accesses and the store buffer is configured to store each pending access with a tag identifier indicative of the context from which that pending access was issued, wherein the memory system interaction circuitry is capable of limiting enforcement of the access ordering constraint to accesses initiated by the processing circuitry when operating in an identified context, wherein the store buffer comprises a context tracking storage with multiple storage locations, and wherein the store buffer is capable of storing an entry in one of the multiple storage locations for the current context when the current context has initiated accesses since the access ordering constraint was last enforced for the current context, and wherein when all of the multiple storage locations in the context tracking storage are occupied and the store buffer does not have an occupied entry for the current context, the store buffer is capable of enforcing an implicit access ordering constraint for pending accesses initiated by a victim context other than the current context which has a corresponding victim entry, and clearing the victim entry for the selected context, wherein the implicit access ordering constraint does not require the processing circuitry to execute a corresponding barrier instruction. processing circuitry (16, 18) to execute data processing instructions to perform data processing operations, wherein the data processing operations comprise accessing a memory system, and wherein the processing circuitry is capable of executing the data processing instructions in a plurality of virtual machine contexts; and memory system interaction circuitry (56, 58, 60, 62) to provide an interface between the processing circuitry and the memory system, wherein the memory system interaction circuitry is capable of, in response to the processing circuitry executing a barrier instruction in a current context of the plurality of contexts, enforcing an access ordering constraint, wherein the memory system interaction circuitry comprises a store buffer to buffer pending accesses and the store buffer is configured to store each pending access with a tag identifier indicative of the context from which that pending access was issued, wherein the memory system interaction circuitry is capable of limiting enforcement of the access ordering constraint to accesses initiated by the processing circuitry when operating in an identified context, wherein the store buffer comprises a context tracking storage with multiple storage locations, and wherein the store buffer is capable of storing an entry in one of the multiple storage locations for the current context when the current context has initiated accesses since the access ordering constraint was last enforced for the current context, and wherein when all of the multiple storage locations in the context tracking storage are occupied and the store buffer does not have an occupied entry for the current context, the store buffer is capable of enforcing an implicit access ordering constraint for pending accesses initiated by a victim context other than the current context which has a corresponding victim entry, and clearing the victim entry for the selected context, wherein the implicit access ordering constraint does not require the processing circuitry to execute a corresponding barrier instruction.