An acceleration control system based on a binarization algorithm, the acceleration control system being used for reading and writing an external image memory by means of an AHB bus, wherein the acceleration control system further comprises a main control module, a binarization module and a binarization FIFO module, wherein the binarization module includes a binarization logic circuit and a register, under the control of the main control module, wherein the binarization module reads the pixel data in the image memory by means of the AHB bus in a burst mode and transmits, in a burst mode, the pixel data to the binarization logic circuit, wherein the transmitted pixel data is binarized in the binarization logic circuit based on the binarization algorithm, and the obtained binarized data is transmitted to the binarization FIFO module, and wherein the binarization module notifies the acceleration control system to send an interrupt instruction to a CPU when all the pixel data of an image stored in the memory has been is processed; wherein the main control module comprises a main state machine, a burst read state machine, a burst write state machine and an interface control state machine, and the main control module is configured to control, by means of the interface control state machine, the AHB bus to read pixel data to be processed in the image memory and control current pixel data in the AHB bus to be transmitted to the binarization module in a burst mode for processing when the main state machine is in a burst read mode state, and meanwhile control, by means of the burst read state machine, the binarization FIFO module to read the binarized data obtained by processing previous pixel data, transmitted in the burst mode, in the binarization module, such that the acceleration control system increases a processing speed of binarization by means of a pipeline running mode under control by the main control machine; and wherein the main control module is further configured to write, by means of the burst write state machine, the binarized data stored in the binarization FIFO module into the AHB bus when the main state machine is in a burst write mode state, and meanwhile write, by means of the interface control state machine, the binarized data in the AHB bus back into the image memory. wherein the binarization module includes a binarization logic circuit and a register, under the control of the main control module, wherein the binarization module reads the pixel data in the image memory by means of the AHB bus in a burst mode and transmits, in a burst mode, the pixel data to the binarization logic circuit, wherein the transmitted pixel data is binarized in the binarization logic circuit based on the binarization algorithm, and the obtained binarized data is transmitted to the binarization FIFO module, and wherein the binarization module notifies the acceleration control system to send an interrupt instruction to a CPU when all the pixel data of an image stored in the memory has been is processed; wherein the main control module comprises a main state machine, a burst read state machine, a burst write state machine and an interface control state machine, and the main control module is configured to control, by means of the interface control state machine, the AHB bus to read pixel data to be processed in the image memory and control current pixel data in the AHB bus to be transmitted to the binarization module in a burst mode for processing when the main state machine is in a burst read mode state, and meanwhile control, by means of the burst read state machine, the binarization FIFO module to read the binarized data obtained by processing previous pixel data, transmitted in the burst mode, in the binarization module, such that the acceleration control system increases a processing speed of binarization by means of a pipeline running mode under control by the main control machine; and wherein the main control module is further configured to write, by means of the burst write state machine, the binarized data stored in the binarization FIFO module into the AHB bus when the main state machine is in a burst write mode state, and meanwhile write, by means of the interface control state machine, the binarized data in the AHB bus back into the image memory.