A system for computational offloading, comprising: a storage device in communication with a first processing element and including a solid state drive, SSD, and a second processing element, wherein the second processing element comprises a first DRAM memory, the first memory being connected to storage component, included in the SSD, via a first connection; the first processing element configured to issue a first request to the storage device; the SSD, responsive to the first request, configured to obtain first data on the storage component and configured to provide the first data to the first memory for storage; the second processing element configured to read the first data from the first memory and configured to perform at least one of an operation or a computation on the first data to generate second data; the second processing element configured to provide the second data to the first processing element; and wherein the first processing element comprises a central processing unit, CPU, of the host device, wherein the second processing element comprises a field-programmable gate array, FPGA, wherein the CPU and the FPGA communicate via an FPGA cache, wherein the kernel on the FPGA utilizes its DRAM and on-chip memory as a cache while data resides primarily on the SSD, wherein the cache is managed by software on the CPU, and one or more cache policies can be customized on the host device so that the cache remains operational when the cache policies are being changed such as there is no need to change the kernel on the FPGA, thereby avoiding FPGA recompilation, wherein the second processing element communicates with the storage component via a switch, wherein the first memory comprises a first portion accessible by the first processing element and accessible by the second processing element and wherein the first portion is used for providing the second data to the first processing element a storage device in communication with a first processing element and including a solid state drive, SSD, and a second processing element, wherein the second processing element comprises a first DRAM memory, the first memory being connected to storage component, included in the SSD, via a first connection; the first processing element configured to issue a first request to the storage device; the SSD, responsive to the first request, configured to obtain first data on the storage component and configured to provide the first data to the first memory for storage; the second processing element configured to read the first data from the first memory and configured to perform at least one of an operation or a computation on the first data to generate second data; the second processing element configured to provide the second data to the first processing element; and wherein the first processing element comprises a central processing unit, CPU, of the host device, wherein the second processing element comprises a field-programmable gate array, FPGA, wherein the CPU and the FPGA communicate via an FPGA cache, wherein the kernel on the FPGA utilizes its DRAM and on-chip memory as a cache while data resides primarily on the SSD, wherein the cache is managed by software on the CPU, and one or more cache policies can be customized on the host device so that the cache remains operational when the cache policies are being changed such as there is no need to change the kernel on the FPGA, thereby avoiding FPGA recompilation, wherein the second processing element communicates with the storage component via a switch, wherein the first memory comprises a first portion accessible by the first processing element and accessible by the second processing element and wherein the first portion is used for providing the second data to the first processing element