A transmitter, comprising: an input circuit configured to couple a logic signal to a first node and a second node; a first level-shifter having an input coupled to the first node; a first pre-driver having an input coupled to an output of the first level-shifter; a second-level shifter having an input coupled to the second node, wherein the second level-shifter is configured to perform a first level shift of the logic signal to generate a first logic signal and a second level shift of the logic signal to generate a second logic signal, and wherein the output of the second level-shifter includes the first logic signal and the second logic signal; a second pre-driver having an input coupled to an output of the second level-shifter, the second pre-driver configured to generate an output signal having a first voltage swing in a first mode and a second voltage swing in a second mode, the second pre-driver comprising a stack of a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor coupled between a supply node (vcco) and a reference node, a gate of the first p-channel transistor receiving the first logic signal, a gate of the second n-channel transistor receiving the second logic signal, and gates of the second p-channel transistor and the first n-channel transistor receiving the first and second bias voltages, respectively; and a driver including a stack of a top p-channel transistor (MP_top), a bottom p-channel transistor (MP_bot), a top n-channel transistor(MN_top), and a bottom n-channel transistor (MN_bot) coupled between the supply node (vcco) and a ground node (gnd), a gate of the top p-channel transistor (MP_top) coupled to receive the output signal of the second pre-driver, a gate of the bottom n-channel transistor (MN_bot) coupled to an output of the first pre-driver, and gates of the bottom p-channel transistor (MP_bot) and the top n-channel transistor (MN_top) coupled to receive first and second bias voltages, respectively. an input circuit configured to couple a logic signal to a first node and a second node; a first level-shifter having an input coupled to the first node; a first pre-driver having an input coupled to an output of the first level-shifter; a second-level shifter having an input coupled to the second node, wherein the second level-shifter is configured to perform a first level shift of the logic signal to generate a first logic signal and a second level shift of the logic signal to generate a second logic signal, and wherein the output of the second level-shifter includes the first logic signal and the second logic signal; a second pre-driver having an input coupled to an output of the second level-shifter, the second pre-driver configured to generate an output signal having a first voltage swing in a first mode and a second voltage swing in a second mode, the second pre-driver comprising a stack of a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor coupled between a supply node (vcco) and a reference node, a gate of the first p-channel transistor receiving the first logic signal, a gate of the second n-channel transistor receiving the second logic signal, and gates of the second p-channel transistor and the first n-channel transistor receiving the first and second bias voltages, respectively; and a driver including a stack of a top p-channel transistor (MP_top), a bottom p-channel transistor (MP_bot), a top n-channel transistor(MN_top), and a bottom n-channel transistor (MN_bot) coupled between the supply node (vcco) and a ground node (gnd), a gate of the top p-channel transistor (MP_top) coupled to receive the output signal of the second pre-driver, a gate of the bottom n-channel transistor (MN_bot) coupled to an output of the first pre-driver, and gates of the bottom p-channel transistor (MP_bot) and the top n-channel transistor (MN_top) coupled to receive first and second bias voltages, respectively.