A method comprising: applying a bias condition to read contents of phase change memory, "PCM", cells of a memory device; determining coded data representing said read contents of said memory device by using an error correction code "ECC" engine; determining whether to modify said bias condition based, at least in part, on a comparison of a number of logic "0" bits of said coded data to a number of logic "1" bits of said coded data, wherein the logic "0" and logic "1" bits correspond to states of the PCM cells based, at least in part, on resistances of the PCM cells corresponding to crystalline and amorphous states of the PCM cells, wherein logic "0" bits correspond to amorphous, high resistance states and logic "1" bits correspond to crystalline, low resistance states; modifying said bias condition in response to a count of read errors in said read contents of said memory device exceeding a threshold number, wherein said bias condition comprises a read bias voltage and further comprising: comparing a number of logic "0" bits of said coded data to a number of logic "1" bits of said coded data; increasing said bias condition in response to said number of logic "0" bits exceeding said number of logic "1" bits; and decreasing said bias condition in response to said number of logic "1" bits exceeding said number of logic "0" bits; after modifying said bias condition, reading said contents of said memory device using said modified bias condition (363, 373), wherein in response to the count of read errors being less than the threshold number, refreshing the coded data, wherein refreshing comprises generating new coded data using the ECC engine. applying a bias condition to read contents of phase change memory, "PCM", cells of a memory device; determining coded data representing said read contents of said memory device by using an error correction code "ECC" engine; determining whether to modify said bias condition based, at least in part, on a comparison of a number of logic "0" bits of said coded data to a number of logic "1" bits of said coded data, wherein the logic "0" and logic "1" bits correspond to states of the PCM cells based, at least in part, on resistances of the PCM cells corresponding to crystalline and amorphous states of the PCM cells, wherein logic "0" bits correspond to amorphous, high resistance states and logic "1" bits correspond to crystalline, low resistance states; modifying said bias condition in response to a count of read errors in said read contents of said memory device exceeding a threshold number, wherein said bias condition comprises a read bias voltage and further comprising: comparing a number of logic "0" bits of said coded data to a number of logic "1" bits of said coded data; increasing said bias condition in response to said number of logic "0" bits exceeding said number of logic "1" bits; and decreasing said bias condition in response to said number of logic "1" bits exceeding said number of logic "0" bits; after modifying said bias condition, reading said contents of said memory device using said modified bias condition (363, 373), wherein in response to the count of read errors being less than the threshold number, refreshing the coded data, wherein refreshing comprises generating new coded data using the ECC engine. comparing a number of logic "0" bits of said coded data to a number of logic "1" bits of said coded data; increasing said bias condition in response to said number of logic "0" bits exceeding said number of logic "1" bits; and decreasing said bias condition in response to said number of logic "1" bits exceeding said number of logic "0" bits; after modifying said bias condition, reading said contents of said memory device using said modified bias condition (363, 373), wherein in response to the count of read errors being less than the threshold number, refreshing the coded data, wherein refreshing comprises generating new coded data using the ECC engine.