A super junction, SJ, device, comprising: a device layer having a first conductivity type, wherein the device layer comprises a top region having a second conductivity type disposed in a top surface of the device layer; a first charge balance, CB, layer having the first conductivity type disposed adjacent to the device layer, wherein the first CB layer comprises a first plurality of charge balance, CB, regions having the second conductivity type; a first connection region having the second conductivity type disposed in the device layer and the first CB layer, wherein the first connection region extends from the top region of the device layer to at least a first CB region of the first plurality of CB regions of the first CB layer, and a second charge balance, CB, layer having the first conductivity type disposed adjacent to the first CB layer, wherein second CB layer comprises a second plurality of charge balance, CB, regions having the second conductivity type, wherein the first connection region extends from the top region of the device layer to at least one of the second plurality of CB regions of the second CB layer, wherein the top region comprises a well region, a body region of a field effect transistor, FET, or a junction barrier region of a junction barrier Schottky, JBS, diode or a merged PiN Schottky, MPS, diode, and wherein the first connection region extends through a thickness of the first CB region of the first plurality of CB regions, wherein the first plurality of CB regions are discrete from the second plurality of CB regions, characterised in that the spacing between the CB regions of the first plurality of CB regions in the first CB layer is different from the spacing between the CB regions of the second plurality of CB regions in the second CB layer. a device layer having a first conductivity type, wherein the device layer comprises a top region having a second conductivity type disposed in a top surface of the device layer; a first charge balance, CB, layer having the first conductivity type disposed adjacent to the device layer, wherein the first CB layer comprises a first plurality of charge balance, CB, regions having the second conductivity type; a first connection region having the second conductivity type disposed in the device layer and the first CB layer, wherein the first connection region extends from the top region of the device layer to at least a first CB region of the first plurality of CB regions of the first CB layer, and a second charge balance, CB, layer having the first conductivity type disposed adjacent to the first CB layer, wherein second CB layer comprises a second plurality of charge balance, CB, regions having the second conductivity type, wherein the first connection region extends from the top region of the device layer to at least one of the second plurality of CB regions of the second CB layer, wherein the top region comprises a well region, a body region of a field effect transistor, FET, or a junction barrier region of a junction barrier Schottky, JBS, diode or a merged PiN Schottky, MPS, diode, and wherein the first connection region extends through a thickness of the first CB region of the first plurality of CB regions, wherein the first plurality of CB regions are discrete from the second plurality of CB regions, characterised in that the spacing between the CB regions of the first plurality of CB regions in the first CB layer is different from the spacing between the CB regions of the second plurality of CB regions in the second CB layer.