An organic light emitting diode (OLED) display comprising: a display panel including a plurality of pixels, a plurality of data lines and a plurality of scan lines; a data driver configured to generate data voltages and output the data voltages to the data lines of the display panel; a gate driver configured to sequentially supply a scan pulse to the scan lines in response to a gate shift clock; and a timing controller configured to: divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, each subframe representing one bit of the data of the input image, the scan line of the display panel being addressed in a said subframe such that the addressing of pixels of each scan line includes: a data address time during which data voltage are written on the pixels of said scan line; and an emission time during which the pixels of the scan line emit light in response to said written data voltages; and to control an operation of the data and gate drivers wherein the timing controller is configured to synchronize the operation timings of the output of said data voltages to said data lines and the sequential supply of said scan pulse to said scan lines, characterized in that the timing controller is further configured to adjust a period of said gate shift clock for at least one subframe of the frame to thereby adjust the data addressing speed of said at least one subframe with respect to the data addressing speed of the previous subframe of said frame wherein the duration of the data addressing time of each scan line for said at least one subframe is different from that of the data addressing time for each scan line of said previous subframe, and whereby the resulting emission times of the upper scan lines of the display panel for said previous subframe differ from the resulting emission times of the lower scan lines of the display panel. a display panel including a plurality of pixels, a plurality of data lines and a plurality of scan lines; a data driver configured to generate data voltages and output the data voltages to the data lines of the display panel; a gate driver configured to sequentially supply a scan pulse to the scan lines in response to a gate shift clock; and a timing controller configured to: divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, each subframe representing one bit of the data of the input image, the scan line of the display panel being addressed in a said subframe such that the addressing of pixels of each scan line includes: a data address time during which data voltage are written on the pixels of said scan line; and an emission time during which the pixels of the scan line emit light in response to said written data voltages; and to control an operation of the data and gate drivers wherein the timing controller is configured to synchronize the operation timings of the output of said data voltages to said data lines and the sequential supply of said scan pulse to said scan lines, characterized in that the timing controller is further configured to adjust a period of said gate shift clock for at least one subframe of the frame to thereby adjust the data addressing speed of said at least one subframe with respect to the data addressing speed of the previous subframe of said frame wherein the duration of the data addressing time of each scan line for said at least one subframe is different from that of the data addressing time for each scan line of said previous subframe, and whereby the resulting emission times of the upper scan lines of the display panel for said previous subframe differ from the resulting emission times of the lower scan lines of the display panel. divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, each subframe representing one bit of the data of the input image, the scan line of the display panel being addressed in a said subframe such that the addressing of pixels of each scan line includes: a data address time during which data voltage are written on the pixels of said scan line; and an emission time during which the pixels of the scan line emit light in response to said written data voltages; a data address time during which data voltage are written on the pixels of said scan line; and an emission time during which the pixels of the scan line emit light in response to said written data voltages; and to control an operation of the data and gate drivers wherein the timing controller is configured to synchronize the operation timings of the output of said data voltages to said data lines and the sequential supply of said scan pulse to said scan lines, characterized in that the timing controller is further configured to adjust a period of said gate shift clock for at least one subframe of the frame to thereby adjust the data addressing speed of said at least one subframe with respect to the data addressing speed of the previous subframe of said frame wherein the duration of the data addressing time of each scan line for said at least one subframe is different from that of the data addressing time for each scan line of said previous subframe, and whereby the resulting emission times of the upper scan lines of the display panel for said previous subframe differ from the resulting emission times of the lower scan lines of the display panel.