A high electron mobility transistor (HEMT) comprising: a plurality of active Group-III nitride semiconductor layers (16,18) on a substrate, said active semiconductor layers comprising a buffer layer, and a barrier layer on said buffer layer and spanning an entire distance between said source and drain electrodes; wherein said HEMT is configured to induce a two-dimensional electron gas at a heterointerface between said buffer layer and said barrier layer during operation of said HEMT; source and drain electrodes (20,22) configured to be in electrical contact with said 2DEG during said operation of said HEMT; a gate between said source and drain electrodes and directly on said active semiconductor layers; a spacer layer covering at least part of a surface of said active semiconductor layers between said gate and said drain electrode, and covering at least part of said surface of said active semiconductor layers between said gate and said source, wherein said spacer layer at least partially covers said gate; a metal field plate on said spacer layer, wherein said metal field plate at least partially overlaps said gate and extends on said spacer layer a distance Lf from an edge of said gate toward said drain electrode, wherein said spacer layer extends on said gate to isolate said gate from said metal field plate; and at least two conductive paths (34,46) that run between said metal field plate and said source electrode, said at least two conductive paths running outside of a region covering an active region of said HEMT and providing said metal field plate electrical connection with said source electrode. a plurality of active Group-III nitride semiconductor layers (16,18) on a substrate, said active semiconductor layers comprising a buffer layer, and a barrier layer on said buffer layer and spanning an entire distance between said source and drain electrodes; wherein said HEMT is configured to induce a two-dimensional electron gas at a heterointerface between said buffer layer and said barrier layer during operation of said HEMT; source and drain electrodes (20,22) configured to be in electrical contact with said 2DEG during said operation of said HEMT; a gate between said source and drain electrodes and directly on said active semiconductor layers; a spacer layer covering at least part of a surface of said active semiconductor layers between said gate and said drain electrode, and covering at least part of said surface of said active semiconductor layers between said gate and said source, wherein said spacer layer at least partially covers said gate; a metal field plate on said spacer layer, wherein said metal field plate at least partially overlaps said gate and extends on said spacer layer a distance Lf from an edge of said gate toward said drain electrode, wherein said spacer layer extends on said gate to isolate said gate from said metal field plate; and at least two conductive paths (34,46) that run between said metal field plate and said source electrode, said at least two conductive paths running outside of a region covering an active region of said HEMT and providing said metal field plate electrical connection with said source electrode.