A sensing device comprising: a photodetector; a load element connected interposingly between the photodetector and a first reference potential (Vdd); a first transistor of a first conductivity type, a gate of the first transistor being directly connected to the load element and the photodetector via a first signal line interposed between the photodetector and the load element, wherein the first transistor is configured to be turned on according to a voltage of the first signal line; a second transistor of the first conductivity type, a source of the second transistor being connected to the first reference potential (Vdd), a drain of the second transistor being connected to a source of the first transistor, and a gate of the second transistor being connected to a second signal line, wherein the second transistor is configured to be turned on according to a current of the first transistor, and wherein the second transistor is configured to be turned off according to a voltage of the second signal line; a third transistor of a second conductivity type, a drain of the third transistor being connected to a drain of the first transistor, a source of the third transistor being connected to a second reference potential, and a gate of the third transistor being connected to a gate of the second transistor via the second signal line, wherein the third transistor is configured to be turned on according to the voltage of the second signal line; and a first inverter connected interposingly between a third signal line and a fourth signal line (Vout), the third signal line being interposed between the first transistor and the third transistor. a photodetector; a load element connected interposingly between the photodetector and a first reference potential (Vdd); a first transistor of a first conductivity type, a gate of the first transistor being directly connected to the load element and the photodetector via a first signal line interposed between the photodetector and the load element, wherein the first transistor is configured to be turned on according to a voltage of the first signal line; a second transistor of the first conductivity type, a source of the second transistor being connected to the first reference potential (Vdd), a drain of the second transistor being connected to a source of the first transistor, and a gate of the second transistor being connected to a second signal line, wherein the second transistor is configured to be turned on according to a current of the first transistor, and wherein the second transistor is configured to be turned off according to a voltage of the second signal line; a third transistor of a second conductivity type, a drain of the third transistor being connected to a drain of the first transistor, a source of the third transistor being connected to a second reference potential, and a gate of the third transistor being connected to a gate of the second transistor via the second signal line, wherein the third transistor is configured to be turned on according to the voltage of the second signal line; and a first inverter connected interposingly between a third signal line and a fourth signal line (Vout), the third signal line being interposed between the first transistor and the third transistor.