An apparatus comprising: a processor core executing event-based programming code to interface a plurality of isolated execution contexts with a set of external communication channel hardware devices using time division multiplexing; an event latch connected and configured to store n hardware events as single-bit signals received from the set of external communication channel hardware devices, where each hardware event is remembered until an acknowledgment is received from the processor core signals that the hardware event has been processed; a timer circuit that generates a sequence of timer interrupt signals; and a masking circuit configured to sequentially mask the plurality of n hardware events stored in the event latch with a sequence of n-bit event masks which are sequentially applied in response to a plurality of timer interrupt signals generated by the timer circuit to generate, for each isolated execution context, a masked subset of hardware events specified by an n-bit event mask corresponding to said isolated execution context, wherein the processor core is configured to sequentially enable each isolated execution in response to the plurality of timer interrupt signals to communicate on the set of external communication channel hardware devices using only the masked subset of hardware events such that each isolated execution context is allowed to process only a masked subset of the hardware events specified by the n-bit event mask to ensure freedom from interference between the plurality of isolated execution contexts when communicating with the set of external communication channel hardware devices; characterized in that the masking circuit comprises: a hardware event mask register connected and configured to sequentially store the plurality of n-bit event masks, where each n-bit event mask is sequentially loaded into the hardware event mask register in response to a timer interrupt signal generated by the timer circuit; and an event selection circuit connected to logically combine the n hardware events stored in the event latch with an n-bit event mask stored in the hardware event mask register, thereby generating the masked subset of the hardware events in response to each timer interrupt signal. a processor core executing event-based programming code to interface a plurality of isolated execution contexts with a set of external communication channel hardware devices using time division multiplexing; an event latch connected and configured to store n hardware events as single-bit signals received from the set of external communication channel hardware devices, where each hardware event is remembered until an acknowledgment is received from the processor core signals that the hardware event has been processed; a timer circuit that generates a sequence of timer interrupt signals; and a masking circuit configured to sequentially mask the plurality of n hardware events stored in the event latch with a sequence of n-bit event masks which are sequentially applied in response to a plurality of timer interrupt signals generated by the timer circuit to generate, for each isolated execution context, a masked subset of hardware events specified by an n-bit event mask corresponding to said isolated execution context, wherein the processor core is configured to sequentially enable each isolated execution in response to the plurality of timer interrupt signals to communicate on the set of external communication channel hardware devices using only the masked subset of hardware events such that each isolated execution context is allowed to process only a masked subset of the hardware events specified by the n-bit event mask to ensure freedom from interference between the plurality of isolated execution contexts when communicating with the set of external communication channel hardware devices; a hardware event mask register connected and configured to sequentially store the plurality of n-bit event masks, where each n-bit event mask is sequentially loaded into the hardware event mask register in response to a timer interrupt signal generated by the timer circuit; and an event selection circuit connected to logically combine the n hardware events stored in the event latch with an n-bit event mask stored in the hardware event mask register, thereby generating the masked subset of the hardware events in response to each timer interrupt signal.