A battery management control circuit comprising: a processor comprising a transceiver; a plurality of battery management systems for an electric vehicle, wherein each battery management system is connected to a respective substring of a string of battery cells and wherein each battery management system comprises a first transceiver and a second transceiver; and a plurality of galvanic isolation circuits connecting adjacent ones of the battery management systems and the processor such that the processor can communicate with each of the battery management systems via the galvanic isolation circuits, wherein each galvanic isolation circuit comprises: a galvanic isolator having a first side and a second side; a first communication link connected to the first side of the galvanic isolator and connected to the first transceiver of one of the battery management systems; a second communication link connected to the second side of the galvanic isolator and connected to the second transceiver of a different one of the battery management systems or the transceiver of the processor; a first reference terminal connected to the first transceiver; a second reference terminal connected to the second transceiver, wherein the first reference terminal and the second reference terminal comprise a first ground terminal and a second ground terminal; and an AC short capacitor connected between the first reference terminal and the second reference terminal, wherein each galvanic isolator circuit further comprises: a first capacitive decoupling circuit connected between the first communication link and the first reference terminal; and a second capacitive decoupling circuit connected between the second communication link and the second reference terminal. a processor comprising a transceiver; a plurality of battery management systems for an electric vehicle, wherein each battery management system is connected to a respective substring of a string of battery cells and wherein each battery management system comprises a first transceiver and a second transceiver; and a plurality of galvanic isolation circuits connecting adjacent ones of the battery management systems and the processor such that the processor can communicate with each of the battery management systems via the galvanic isolation circuits, wherein each galvanic isolation circuit comprises: a galvanic isolator having a first side and a second side; a first communication link connected to the first side of the galvanic isolator and connected to the first transceiver of one of the battery management systems; a second communication link connected to the second side of the galvanic isolator and connected to the second transceiver of a different one of the battery management systems or the transceiver of the processor; a first reference terminal connected to the first transceiver; a second reference terminal connected to the second transceiver, wherein the first reference terminal and the second reference terminal comprise a first ground terminal and a second ground terminal; and an AC short capacitor connected between the first reference terminal and the second reference terminal, wherein each galvanic isolator circuit further comprises: a galvanic isolator having a first side and a second side; a first communication link connected to the first side of the galvanic isolator and connected to the first transceiver of one of the battery management systems; a second communication link connected to the second side of the galvanic isolator and connected to the second transceiver of a different one of the battery management systems or the transceiver of the processor; a first reference terminal connected to the first transceiver; a second reference terminal connected to the second transceiver, wherein the first reference terminal and the second reference terminal comprise a first ground terminal and a second ground terminal; and a first capacitive decoupling circuit connected between the first communication link and the first reference terminal; and a second capacitive decoupling circuit connected between the second communication link and the second reference terminal.