A distributed processor on a memory chip, comprising: a semiconductor substrate; a plurality of memory banks (2202,2204) disposed on the semiconductor substrate; a memory controller disposed on the semiconductor substrate and connected to each one of the plurality of memory banks (2202,2204); and a plurality of processing units (2212,2214,2216) disposed on the semiconductor substrate, each one of the plurality of processing units (2212, 2214,2216) being connected to the memory controller, the plurality of processing units (2212,2214,2216) including a configuration manager, wherein the plurality of processing units (2214,2216) comprise a plurality of accelerators (2216a-n) configured for pre-defined tasks; wherein the configuration manager is configured to: receive a first indication of a task to be performed, based on an instruction received at the memory chip from a host external to the memory chip, the task requiring at least one computation; signal at least one selected processing unit from among the plurality of processing units (2214,2216) disposed on the semiconductor substrate based upon a capability of the selected processing unit (2214,2216) for performing the at least one computation; and transmit a second indication to the at least one selected processing unit, and wherein the memory controller is configured to: route data from at least two memory banks (2202,2204) from among the plurality of memory banks disposed on the semiconductor substrate to the at least one selected processing unit disposed on the semiconductor substrate using at least one communication line, the at least one communication line being connected to the at least two memory banks and the at least one selected processing unit via the memory controller. a semiconductor substrate; a plurality of memory banks (2202,2204) disposed on the semiconductor substrate; a memory controller disposed on the semiconductor substrate and connected to each one of the plurality of memory banks (2202,2204); and a plurality of processing units (2212,2214,2216) disposed on the semiconductor substrate, each one of the plurality of processing units (2212, 2214,2216) being connected to the memory controller, the plurality of processing units (2212,2214,2216) including a configuration manager, wherein the plurality of processing units (2214,2216) comprise a plurality of accelerators (2216a-n) configured for pre-defined tasks; wherein the configuration manager is configured to: receive a first indication of a task to be performed, based on an instruction received at the memory chip from a host external to the memory chip, the task requiring at least one computation; signal at least one selected processing unit from among the plurality of processing units (2214,2216) disposed on the semiconductor substrate based upon a capability of the selected processing unit (2214,2216) for performing the at least one computation; and transmit a second indication to the at least one selected processing unit, and receive a first indication of a task to be performed, based on an instruction received at the memory chip from a host external to the memory chip, the task requiring at least one computation; signal at least one selected processing unit from among the plurality of processing units (2214,2216) disposed on the semiconductor substrate based upon a capability of the selected processing unit (2214,2216) for performing the at least one computation; and transmit a second indication to the at least one selected processing unit, and wherein the memory controller is configured to: route data from at least two memory banks (2202,2204) from among the plurality of memory banks disposed on the semiconductor substrate to the at least one selected processing unit disposed on the semiconductor substrate using at least one communication line, the at least one communication line being connected to the at least two memory banks and the at least one selected processing unit via the memory controller.