A System-on-Chip, SoC, comprising: a switchable memory configured to switch between a processor cache configuration and a random-access memory, RAM, configuration; and a controller configured to: dynamically switch, responsive to a power-down event or a power-on event, the switchable memory from the processor cache configuration to the RAM configuration; load boot code from a non-volatile memory into the switchable memory while the switchable memory is in the RAM configuration; execute the boot code from the switchable memory while the switchable memory is in the RAM configuration effective to boot an operating system of the SoC; and dynamically switch, responsive to booting the operating system of the SoC, the switchable memory from the RAM configuration to the processor cache configuration; characterized in that the processor cache configuration is a second-level, L2, configuration and the RAM configuration is a static RAM, SRAM, configuration and the controller is further configured to dynamically switch the memory from the L2 cache configuration to the SRAM configuration by: disabling the switchable memory as L2 cache by writing to an enable bit in a control register; cleaning the switchable memory; clearing a RAM select bit in a configuration register of the switchable memory; invalidating the switchable memory as L2 cache; waiting for the switchable memory to become idle; setting the SRAM select bit in the configuration register; and configuring a bank of the switchable memory for SRAM. a switchable memory configured to switch between a processor cache configuration and a random-access memory, RAM, configuration; and a controller configured to: dynamically switch, responsive to a power-down event or a power-on event, the switchable memory from the processor cache configuration to the RAM configuration; load boot code from a non-volatile memory into the switchable memory while the switchable memory is in the RAM configuration; execute the boot code from the switchable memory while the switchable memory is in the RAM configuration effective to boot an operating system of the SoC; and dynamically switch, responsive to booting the operating system of the SoC, the switchable memory from the RAM configuration to the processor cache configuration; characterized in that the processor cache configuration is a second-level, L2, configuration and the RAM configuration is a static RAM, SRAM, configuration and the controller is further configured to dynamically switch the memory from the L2 cache configuration to the SRAM configuration by: disabling the switchable memory as L2 cache by writing to an enable bit in a control register; cleaning the switchable memory; clearing a RAM select bit in a configuration register of the switchable memory; invalidating the switchable memory as L2 cache; waiting for the switchable memory to become idle; setting the SRAM select bit in the configuration register; and configuring a bank of the switchable memory for SRAM. dynamically switch, responsive to a power-down event or a power-on event, the switchable memory from the processor cache configuration to the RAM configuration; load boot code from a non-volatile memory into the switchable memory while the switchable memory is in the RAM configuration; execute the boot code from the switchable memory while the switchable memory is in the RAM configuration effective to boot an operating system of the SoC; and dynamically switch, responsive to booting the operating system of the SoC, the switchable memory from the RAM configuration to the processor cache configuration; characterized in that the processor cache configuration is a second-level, L2, configuration and the RAM configuration is a static RAM, SRAM, configuration and the controller is further configured to dynamically switch the memory from the L2 cache configuration to the SRAM configuration by: disabling the switchable memory as L2 cache by writing to an enable bit in a control register; cleaning the switchable memory; clearing a RAM select bit in a configuration register of the switchable memory; invalidating the switchable memory as L2 cache; waiting for the switchable memory to become idle; setting the SRAM select bit in the configuration register; and configuring a bank of the switchable memory for SRAM. disabling the switchable memory as L2 cache by writing to an enable bit in a control register; cleaning the switchable memory; clearing a RAM select bit in a configuration register of the switchable memory; invalidating the switchable memory as L2 cache; waiting for the switchable memory to become idle; setting the SRAM select bit in the configuration register; and configuring a bank of the switchable memory for SRAM.