: An adaptive self-biasing comparator, arranged for operation under low average power consumption for comparing a first analogue input signal (Vin+) with a second analogue input signal (Vin-) received respectively at a first and a second input node, said comparator comprising: - a first transistor, forming a bias current configured to provide a bias current to a first differential input stage, said first transistor having a gate connected to a gate and drain of a second transistor and a drain connected to a source of a third transistor and source of a fourth transistor; wherein - said third transistor and fourth transistor forming said first differential input stage for comparison of a transition between said first and second analogue input signals, and having gates connected to the first and the second input nodes of the comparator, respectively, and having drains connected to a gate and a source of a fifth transistor and a gate and a source of a sixth transistor, respectively, and to an output stage of the comparator; wherein - the gate and the source of said sixth transistor is further connected to a gate of a seventh transistor; wherein the comparator further comprises a second differential input stage comprising: - an eighth transistor and a ninth transistor having sources connected together to said drain of said seventh transistor wherein gates of the eighth transistor and the ninth transistor of said second differential input stage are connected to the second and the first input nodes, wherein - a drain of the eighth transistor forms an output of said second differential input stage and the drain of the gate of the second transistor are further connected to the output of said second differential input stage to form a feedback from the output of the second differential input stage to the bias current stage for controlling the bias current such that the bias current increases upon decrease of the transition between said first and second analogue input signals, wherein the comparator further comprises, - a tenth transistor having a gate and a drain connected together to a drain of said ninth transistor. - a first transistor, forming a bias current configured to provide a bias current to a first differential input stage, said first transistor having a gate connected to a gate and drain of a second transistor and a drain connected to a source of a third transistor and source of a fourth transistor; wherein - said third transistor and fourth transistor forming said first differential input stage for comparison of a transition between said first and second analogue input signals, and having gates connected to the first and the second input nodes of the comparator, respectively, and having drains connected to a gate and a source of a fifth transistor and a gate and a source of a sixth transistor, respectively, and to an output stage of the comparator; wherein - the gate and the source of said sixth transistor is further connected to a gate of a seventh transistor; wherein the comparator further comprises a second differential input stage comprising: - an eighth transistor and a ninth transistor having sources connected together to said drain of said seventh transistor wherein gates of the eighth transistor and the ninth transistor of said second differential input stage are connected to the second and the first input nodes, wherein wherein gates of the eighth transistor and the ninth transistor of said second differential input stage are connected to the second and the first input nodes, wherein - a drain of the eighth transistor forms an output of said second differential input stage and the drain of the gate of the second transistor are further connected to the output of said second differential input stage to form a feedback from the output of the second differential input stage to the bias current stage for controlling the bias current such that the bias current increases upon decrease of the transition between said first and second analogue input signals, wherein the comparator further comprises, - a tenth transistor having a gate and a drain connected together to a drain of said ninth transistor.