A method for processing configuration data that is stored in configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) on a programmable integrated circuit, the method comprising the steps of: identifying a don't care subset of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) that store don't care bits of the configuration data, wherein a polarity change in one of the don't care bits preserves the functionality of the circuit design implementation in the programmable integrated circuit; computing a first error check bit of a first subset of the configuration data stored in a first subset of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326); and storing the first error check bit in a first configuration memory cell (130; 210, 212, 214,... 226; 310, 312,... 326) in the don't care subset of configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326), characterized in that the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) comprise an array of configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) arranged in rows and columns, and wherein the first subset of the configuration data is stored in a row of configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) in the array; and the method further comprises: computing a second error check bit of a second subset of the configuration data stored in a second subset of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326), wherein the first and second subsets of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) overlap in a common predetermined configuration memory cell (130; 210, 212, 214,... 226; 310, 312,... 326). identifying a don't care subset of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) that store don't care bits of the configuration data, wherein a polarity change in one of the don't care bits preserves the functionality of the circuit design implementation in the programmable integrated circuit; computing a first error check bit of a first subset of the configuration data stored in a first subset of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326); and storing the first error check bit in a first configuration memory cell (130; 210, 212, 214,... 226; 310, 312,... 326) in the don't care subset of configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326), characterized in that the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) comprise an array of configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) arranged in rows and columns, and wherein the first subset of the configuration data is stored in a row of configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) in the array; and the method further comprises: computing a second error check bit of a second subset of the configuration data stored in a second subset of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326), wherein the first and second subsets of the configuration memory cells (130; 210, 212, 214,... 226; 310, 312,... 326) overlap in a common predetermined configuration memory cell (130; 210, 212, 214,... 226; 310, 312,... 326).