An apparatus comprising: an output driver (240, 300, 425) comprising a pull-up circuit (225, 340) including one or more pull-up legs (325, 605), and a pull-down circuit (230, 345) including one or more pull-down legs (330, 610); a control circuit (235, 420) coupled to the output driver (240, 300, 425), the control circuit (235, 420) comprising at least a first leg control circuit (215, 335A) coupled to the pull-up circuit (225, 340) and a second leg control circuit (220, 335B) coupled to the pull-down circuit (230, 345), wherein the control circuit (235, 420) is configured to: receive an input signal having a first logical value and a second logical value; determine whether a logical transition has occurred in the input signal, between the first logical value and the second logic value; cause, via the first leg control circuit (315, 335A) and the second leg control circuit (220, 335B), in response to determining the logical transition has occurred from the second logic value to the first logic value, the pull-up circuit (225, 340) and pull-down circuit (230, 345) respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion; wherein when the pull-up circuit (225, 340) and the pull-down circuit (230, 345) are in the first state, the output driver (240, 300, 425)drives an output signal to a first amplitude corresponding to the first logic value; wherein when the pull-up circuit (225, 340) and the pull-down circuit (230, 345) are in the second state, the output driver (240, 300, 425) drives the output signal to a second amplitude less than the first amplitude; characterized in that the control circuit (235, 420) is configured to adjust the second amplitude based at least in part on a control signal. an output driver (240, 300, 425) comprising a pull-up circuit (225, 340) including one or more pull-up legs (325, 605), and a pull-down circuit (230, 345) including one or more pull-down legs (330, 610); a control circuit (235, 420) coupled to the output driver (240, 300, 425), the control circuit (235, 420) comprising at least a first leg control circuit (215, 335A) coupled to the pull-up circuit (225, 340) and a second leg control circuit (220, 335B) coupled to the pull-down circuit (230, 345), wherein the control circuit (235, 420) is configured to: receive an input signal having a first logical value and a second logical value; determine whether a logical transition has occurred in the input signal, between the first logical value and the second logic value; cause, via the first leg control circuit (315, 335A) and the second leg control circuit (220, 335B), in response to determining the logical transition has occurred from the second logic value to the first logic value, the pull-up circuit (225, 340) and pull-down circuit (230, 345) respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion; receive an input signal having a first logical value and a second logical value; determine whether a logical transition has occurred in the input signal, between the first logical value and the second logic value; cause, via the first leg control circuit (315, 335A) and the second leg control circuit (220, 335B), in response to determining the logical transition has occurred from the second logic value to the first logic value, the pull-up circuit (225, 340) and pull-down circuit (230, 345) respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion; wherein when the pull-up circuit (225, 340) and the pull-down circuit (230, 345) are in the first state, the output driver (240, 300, 425)drives an output signal to a first amplitude corresponding to the first logic value; wherein when the pull-up circuit (225, 340) and the pull-down circuit (230, 345) are in the second state, the output driver (240, 300, 425) drives the output signal to a second amplitude less than the first amplitude; characterized in that the control circuit (235, 420) is configured to adjust the second amplitude based at least in part on a control signal.