An operation verification apparatus comprising: a division unit to read a first program including a plurality of control processings and a second program including a plurality of control processings where at least a portion of the plurality of control processings of the first program has been changed, to divide each of the plurality of control processings into a concurrency processing to implement a concurrent processing in the plurality of control processings and a functional sequential processing to implement a function to be achieved by the plurality of control processings, to output the first program with each of the plurality of control processings therein divided into the concurrency processing and the functional sequential processing as a first divided program, and to output the second program with each of the plurality of control processings therein divided into the concurrency processing and the functional sequential processing as a second divided program; wherein the plurality of control processings are processings including operation sets, branchings, mergings, and loopings; and a cause estimation unit to estimate the functional sequential processing that is different between the first divided program and the second divided program as a cause of a functional defect when the defect of the function is detected in the second divided program as the functional defect and to estimate the concurrency processing that is different between the first divided program and the second divided program as a cause of a concurrency defect when the defect that is caused by the concurrent processing is detected in the second divided program as the concurrency defect. a division unit to read a first program including a plurality of control processings and a second program including a plurality of control processings where at least a portion of the plurality of control processings of the first program has been changed, to divide each of the plurality of control processings into a concurrency processing to implement a concurrent processing in the plurality of control processings and a functional sequential processing to implement a function to be achieved by the plurality of control processings, to output the first program with each of the plurality of control processings therein divided into the concurrency processing and the functional sequential processing as a first divided program, and to output the second program with each of the plurality of control processings therein divided into the concurrency processing and the functional sequential processing as a second divided program; wherein the plurality of control processings are processings including operation sets, branchings, mergings, and loopings; and a cause estimation unit to estimate the functional sequential processing that is different between the first divided program and the second divided program as a cause of a functional defect when the defect of the function is detected in the second divided program as the functional defect and to estimate the concurrency processing that is different between the first divided program and the second divided program as a cause of a concurrency defect when the defect that is caused by the concurrent processing is detected in the second divided program as the concurrency defect.