An array substrate, comprising a plurality of data lines and a plurality of gate lines arranged to cross each other, and a column of pixel units being disposed between adjacent data lines, wherein each of the pixel units comprise at least two sub-pixel electrodes (31, 32, 33, 34), a voltage compensation unit configured to charge at least one sub-pixel electrode of the pixel unit, and a voltage division unit configured to reduce a voltage on at least one of the other sub-pixel electrodes of the pixel unit, the voltage compensation unit and the voltage division unit are configured such that voltages of respective sub-pixel electrodes are not all the same, the at least two sub-pixel electrodes comprise a first sub-pixel electrode and a second sub-pixel electrode, the pixel unit further comprises a common electrode line, the voltage compensation unit is electrically connected to the first sub-pixel electrode and the second sub-pixel electrode, and the voltage division unit is electrically connected to the first sub-pixel electrode and the common electrode line, the voltage division unit comprises a voltage division capacitor and a voltage division thin film transistor, and the voltage compensation unit comprises a voltage compensation capacitor and a voltage compensation thin film transistor, each of the pixel units further comprise a pair of first thin film transistors configured to charge the first sub-pixel electrode and the second sub-pixel electrode, respectively, and characterised in that the pair of first thin film transistors, the voltage compensation thin film transistor and the voltage division thin film transistor of the pixel unit are electrically connected with a same one of the plurality of gate lines. wherein each of the pixel units comprise at least two sub-pixel electrodes (31, 32, 33, 34), a voltage compensation unit configured to charge at least one sub-pixel electrode of the pixel unit, and a voltage division unit configured to reduce a voltage on at least one of the other sub-pixel electrodes of the pixel unit, the voltage compensation unit and the voltage division unit are configured such that voltages of respective sub-pixel electrodes are not all the same, the at least two sub-pixel electrodes comprise a first sub-pixel electrode and a second sub-pixel electrode, the pixel unit further comprises a common electrode line, the voltage compensation unit is electrically connected to the first sub-pixel electrode and the second sub-pixel electrode, and the voltage division unit is electrically connected to the first sub-pixel electrode and the common electrode line, the voltage division unit comprises a voltage division capacitor and a voltage division thin film transistor, and the voltage compensation unit comprises a voltage compensation capacitor and a voltage compensation thin film transistor, each of the pixel units further comprise a pair of first thin film transistors configured to charge the first sub-pixel electrode and the second sub-pixel electrode, respectively, and characterised in that the pair of first thin film transistors, the voltage compensation thin film transistor and the voltage division thin film transistor of the pixel unit are electrically connected with a same one of the plurality of gate lines.