A method for managing computer executable instructions, the method comprising: receiving, by a processor, at least one machine instruction for execution; analyzing, by an instruction decode unit of the processor, the at least one machine instruction; based on the instruction decode unit determining (808,908) that the machine instruction is a predefined instruction for storing a variable length first operand in a first memory location identified by the machine instruction, the first operand consisting of a first plurality of first blocks, determining (810,910), by an operand-overlap-determining module of the instruction decode unit during at least one instruction decoding cycle and based on fields of the machine instruction, a relative location of a variable length second operand of the machine instruction with respect to the first memory location of the first operand thereby to identify overlap between the first and second operands, the variable length second operand in a second memory location identified by the machine instruction and consisting of a second plurality of second blocks; and based on the relative location having a predefined relationship, performing by an instruction cracking unit of the processor during at least one instruction decoding cycle, a first cracking operation cracking the machine instruction into a first set of micro-ops Uops, wherein each Uop in the first set of Uops is executable in parallel with other machine instructions and Uops, sending the first set of Uops to an instruction sequencer unit; issuing a first Uop in the first set of Uops to a first execution unit; issuing at least a second Uop in the first set of Uops to at least a second execution unit; and executing, by the first and second executing units, the first Uop and the second Uop respectively, the executing causing a single block to be stored in each of the first plurality of first blocks of the first operand, each of the single blocks being identical. receiving, by a processor, at least one machine instruction for execution; analyzing, by an instruction decode unit of the processor, the at least one machine instruction; based on the instruction decode unit determining (808,908) that the machine instruction is a predefined instruction for storing a variable length first operand in a first memory location identified by the machine instruction, the first operand consisting of a first plurality of first blocks, determining (810,910), by an operand-overlap-determining module of the instruction decode unit during at least one instruction decoding cycle and based on fields of the machine instruction, a relative location of a variable length second operand of the machine instruction with respect to the first memory location of the first operand thereby to identify overlap between the first and second operands, the variable length second operand in a second memory location identified by the machine instruction and consisting of a second plurality of second blocks; and based on the relative location having a predefined relationship, performing by an instruction cracking unit of the processor during at least one instruction decoding cycle, a first cracking operation cracking the machine instruction into a first set of micro-ops Uops, wherein each Uop in the first set of Uops is executable in parallel with other machine instructions and Uops, sending the first set of Uops to an instruction sequencer unit; issuing a first Uop in the first set of Uops to a first execution unit; issuing at least a second Uop in the first set of Uops to at least a second execution unit; and executing, by the first and second executing units, the first Uop and the second Uop respectively, the executing causing a single block to be stored in each of the first plurality of first blocks of the first operand, each of the single blocks being identical.