A non-volatile memory device, comprising: a memory array having at least one memory cell; a reading circuit; a column decoder stage, coupled between the memory array and the reading circuit and comprising at least one selectable bitline (LBLi) and at least one selection switch, the at least one selectable bitline and the at least one selection switch being configured, when selected, to couple the memory cell to the reading circuit and define a selected read path; and a read supply voltage generator, comprising a voltage regulation circuit, a dummy column decoder, a voltage set resistor and a current set resistor, the dummy column decoder coupled between a first and a second intermediate nodes (56, 61), the dummy column decoder further coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path, the voltage regulation circuit comprising an operational amplifier and a feedback circuit, the operational amplifier having a first input, a second input, and an output, the first input of the operational amplifier receiving an electrical reference quantity (Vbg), the second input of the operational amplifier being coupled to the current set resistor and, the output of the operational amplifier being coupled to the dummy column decoder and to the output of the read supply voltage generator, and the feedback circuit comprises a current mirror circuit having a first current supplying node coupled to the second input of the operational amplifier and a second current supplying node coupled to the first intermediate node,the voltage set resistor coupled between the second intermediate node of the dummy column decoder and ground and configured to generate a first electrical quantity correlated to a desired voltage value (Vb) on the at least one selectable bitline (LBLi); the current set resistor coupled between the second input of the operational amplifier and ground, the current set resistor flowed by a fixed current supplied by the first current supplying node of the feedback circuit and configured to generate a second electrical quantity correlated to a desired current value (I R) for the at least one selectable bitline, the second electrical quantity supplied to the second input of the operational amplifier; the voltage regulation circuit being configured to receive the first electrical quantity and the second electrical quantity and to generate the regulated read supply voltage (V CDS) for the column decoder stage, the regulated read supply voltage controlling the column decoder stage to supply the at least one selectable bitline, when selected, with the desired voltage value at the desired current value. a memory array having at least one memory cell; a reading circuit; a column decoder stage, coupled between the memory array and the reading circuit and comprising at least one selectable bitline (LBLi) and at least one selection switch, the at least one selectable bitline and the at least one selection switch being configured, when selected, to couple the memory cell to the reading circuit and define a selected read path; and a read supply voltage generator, comprising a voltage regulation circuit, a dummy column decoder, a voltage set resistor and a current set resistor, the dummy column decoder coupled between a first and a second intermediate nodes (56, 61), the dummy column decoder further coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path, the voltage regulation circuit comprising an operational amplifier and a feedback circuit, the operational amplifier having a first input, a second input, and an output, the first input of the operational amplifier receiving an electrical reference quantity (Vbg), the second input of the operational amplifier being coupled to the current set resistor and, the output of the operational amplifier being coupled to the dummy column decoder and to the output of the read supply voltage generator, and the feedback circuit comprises a current mirror circuit having a first current supplying node coupled to the second input of the operational amplifier and a second current supplying node coupled to the first intermediate node,the voltage set resistor coupled between the second intermediate node of the dummy column decoder and ground and configured to generate a first electrical quantity correlated to a desired voltage value (Vb) on the at least one selectable bitline (LBLi); the current set resistor coupled between the second input of the operational amplifier and ground, the current set resistor flowed by a fixed current supplied by the first current supplying node of the feedback circuit and configured to generate a second electrical quantity correlated to a desired current value (I R) for the at least one selectable bitline, the second electrical quantity supplied to the second input of the operational amplifier; the voltage regulation circuit being configured to receive the first electrical quantity and the second electrical quantity and to generate the regulated read supply voltage (V CDS) for the column decoder stage, the regulated read supply voltage controlling the column decoder stage to supply the at least one selectable bitline, when selected, with the desired voltage value at the desired current value.