A data processing apparatus comprising: processing circuitry to perform data processing; and an instruction decoder to decode instructions to control the processing circuitry to perform the data processing; wherein the instruction decoder is configured to decode a complex multiply instruction to control the processing circuitry to perform a partial complex multiply operation on first and second operand vectors to set at least one target element of a destination vector to a value dependent on a result of adding or subtracting a first product and a second product, the first and second operand vectors and the destination vector each comprising a plurality of data elements including at least one real element for representing a real part of a complex number and at least one imaginary element for representing an imaginary part of a complex number; in response to a first form of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with the first product comprising a product of a real element of the first operand vector and a corresponding real element of the second operand vector, and the second product comprising a product of an imaginary element of the first operand vector and a corresponding imaginary element of the second operand vector; in response to a second form of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with the first product comprising a product of a real element of the first operand vector and an imaginary element of the second operand vector, and the second product comprising a product of an imaginary element of the first operand vector and a real element of the second operand vector; in response to one of the first and second forms of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with said at least one target element comprising at least one real element of the destination vector; in response to the other of the first and second forms of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with said at least one target element comprising at least one imaginary element of the destination vector; and in response to at least one of the first and second forms of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to suppress updating of at least one element of the destination vector other than said at least one target element. processing circuitry to perform data processing; and an instruction decoder to decode instructions to control the processing circuitry to perform the data processing; wherein the instruction decoder is configured to decode a complex multiply instruction to control the processing circuitry to perform a partial complex multiply operation on first and second operand vectors to set at least one target element of a destination vector to a value dependent on a result of adding or subtracting a first product and a second product, the first and second operand vectors and the destination vector each comprising a plurality of data elements including at least one real element for representing a real part of a complex number and at least one imaginary element for representing an imaginary part of a complex number; in response to a first form of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with the first product comprising a product of a real element of the first operand vector and a corresponding real element of the second operand vector, and the second product comprising a product of an imaginary element of the first operand vector and a corresponding imaginary element of the second operand vector; in response to a second form of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with the first product comprising a product of a real element of the first operand vector and an imaginary element of the second operand vector, and the second product comprising a product of an imaginary element of the first operand vector and a real element of the second operand vector; in response to one of the first and second forms of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with said at least one target element comprising at least one real element of the destination vector; in response to the other of the first and second forms of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to perform the partial complex multiply operation with said at least one target element comprising at least one imaginary element of the destination vector; and in response to at least one of the first and second forms of the complex multiply instruction, the instruction decoder is configured to control the processing circuitry to suppress updating of at least one element of the destination vector other than said at least one target element.