A joint detection accelerator to perform joint detection of received signals containing data from multiple users associated with a time slot, comprising: a memory unit to store input data values, intermediate results and output data values; an address generation unit to generate addresses for accessing the memory unit; one or more computation units, each comprising a data path (1306, 1307, 1308), to process the input data values and the intermediate results by executing operations of a joint detection algorithm on the input data values to obtain the intermediate results and by executing subsequent operations of the joint detection algorithm on the intermediate results to obtain the output data values, and to provide the output data values to the memory unit; a data selector to provide the input data values and the intermediate results to the one or more computation units; a controller to control the memory unit, the address generation unit, the one or more computation units and the data selector to perform joint detection processing by executing the joint detection algorithm; and an external interface to receive the input data values from a host processor and to provide the output data values to the host processor; wherein the input data values are obtained by the host processor by processing the received signals, and the output data values represent a specific user's data contained by the data from the multiple users; wherein the one or more computation units include a primary data path comprising a complex multiply accumulate unit; characterized in that the one or more computation units further comprise a secondary data path including a simplified complex multiply accumulate unit permitting multiplication of two complex values, wherein one of the two complex values is +1, -1, +j or -j. a memory unit to store input data values, intermediate results and output data values; an address generation unit to generate addresses for accessing the memory unit; one or more computation units, each comprising a data path (1306, 1307, 1308), to process the input data values and the intermediate results by executing operations of a joint detection algorithm on the input data values to obtain the intermediate results and by executing subsequent operations of the joint detection algorithm on the intermediate results to obtain the output data values, and to provide the output data values to the memory unit; a data selector to provide the input data values and the intermediate results to the one or more computation units; a controller to control the memory unit, the address generation unit, the one or more computation units and the data selector to perform joint detection processing by executing the joint detection algorithm; and an external interface to receive the input data values from a host processor and to provide the output data values to the host processor; wherein the input data values are obtained by the host processor by processing the received signals, and the output data values represent a specific user's data contained by the data from the multiple users; wherein the one or more computation units include a primary data path comprising a complex multiply accumulate unit; characterized in that the one or more computation units further comprise a secondary data path including a simplified complex multiply accumulate unit permitting multiplication of two complex values, wherein one of the two complex values is +1, -1, +j or -j.