A control circuit, comprising: a driving circuit (203, 205), comprising a voltage adjusting circuit (PUC, PDC) for generating a control voltage occurring on a voltage output terminal of the voltage adjusting circuit (PUC, PDC), comprising a first transistor (TP1, TN1) and a second transistor (TP2, TN2); wherein the first and second transistors (TP1, TP2, TN1, TN2) are PMOSFETs (TP1, TP2) or NMOSFETs (TN1, TN2); wherein the first transistor (TP1, TN1) comprises: a first terminal being a drain terminal; a second terminal being a source terminal; and a control terminal being a gate terminal, for receiving a bias voltage (Vb) generated from at least one operating voltage of the control circuit; wherein the second transistor (TP2, TN2) comprises: a first terminal being a drain terminal, coupled to the second terminal of the first transistor (TP1, TN1); a second terminal being a source terminal, for receiving a first predetermined voltage (VDD, GND); and a control terminal being a gate terminal, coupled to the voltage output terminal of the voltage adjusting circuit (PUC, PDC) for receiving the control voltage (CV, PD); characterized by: a core unit receiving a core voltage (Vcore); a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a multiplexer, for outputting one of the candidate voltages output from the candidate voltage selecting circuit and ground voltage as the bias voltage (Vb); wherein the candidate voltages are related with the at least one operating voltage of the control circuit and wherein the at least one operating voltage of the control circuit comprises the core voltage and/or the first predetermined voltage minus the core voltage (Vcore). a driving circuit (203, 205), comprising a voltage adjusting circuit (PUC, PDC) for generating a control voltage occurring on a voltage output terminal of the voltage adjusting circuit (PUC, PDC), comprising a first transistor (TP1, TN1) and a second transistor (TP2, TN2); wherein the first and second transistors (TP1, TP2, TN1, TN2) are PMOSFETs (TP1, TP2) or NMOSFETs (TN1, TN2); wherein the first transistor (TP1, TN1) comprises: a first terminal being a drain terminal; a second terminal being a source terminal; and a control terminal being a gate terminal, for receiving a bias voltage (Vb) generated from at least one operating voltage of the control circuit; a first terminal being a drain terminal; a second terminal being a source terminal; and a control terminal being a gate terminal, for receiving a bias voltage (Vb) generated from at least one operating voltage of the control circuit; wherein the second transistor (TP2, TN2) comprises: a first terminal being a drain terminal, coupled to the second terminal of the first transistor (TP1, TN1); a second terminal being a source terminal, for receiving a first predetermined voltage (VDD, GND); and a control terminal being a gate terminal, coupled to the voltage output terminal of the voltage adjusting circuit (PUC, PDC) for receiving the control voltage (CV, PD); characterized by: a core unit receiving a core voltage (Vcore); a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a multiplexer, for outputting one of the candidate voltages output from the candidate voltage selecting circuit and ground voltage as the bias voltage (Vb); wherein the candidate voltages are related with the at least one operating voltage of the control circuit and wherein the at least one operating voltage of the control circuit comprises the core voltage and/or the first predetermined voltage minus the core voltage (Vcore). a first terminal being a drain terminal, coupled to the second terminal of the first transistor (TP1, TN1); a second terminal being a source terminal, for receiving a first predetermined voltage (VDD, GND); and a control terminal being a gate terminal, coupled to the voltage output terminal of the voltage adjusting circuit (PUC, PDC) for receiving the control voltage (CV, PD); characterized by: a core unit receiving a core voltage (Vcore); a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a multiplexer, for outputting one of the candidate voltages output from the candidate voltage selecting circuit and ground voltage as the bias voltage (Vb); wherein the candidate voltages are related with the at least one operating voltage of the control circuit and wherein the at least one operating voltage of the control circuit comprises the core voltage and/or the first predetermined voltage minus the core voltage (Vcore). a core unit receiving a core voltage (Vcore); a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a multiplexer, for outputting one of the candidate voltages output from the candidate voltage selecting circuit and ground voltage as the bias voltage (Vb); wherein the candidate voltages are related with the at least one operating voltage of the control circuit and wherein the at least one operating voltage of the control circuit comprises the core voltage and/or the first predetermined voltage minus the core voltage (Vcore).