A memory cell for a static random access memory, the memory cell comprising: - a first transistor, a second transistor, a third transistor and a fourth transistor forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node and an inverted first storage node (D'), wherein the first inverter is connected to a first reference voltage and a first supply voltage, and wherein the second inverter is connected to a second reference voltage and a second supply voltage; - a fifth transistor connected between the first storage node and a first bit line; - a sixth transistor connected between the inverted first storage node (D') and a second bit line; - a first word line connected to the fifth transistor, said first word line controlling the access of the first bit line to the first storage node; and - a second word line, independent of the first word line, connected to the sixth transistor, said second word line controlling the access of the second bit line to the inverted first storage node (D') independently of the first bit line; wherein relative voltage levels of the first word line and first reference voltage, or of the first supply voltage and the first reference voltage, or of the second word line and second reference voltage, or of the second supply voltage and the second reference voltage, or of the first reference voltage and the second reference voltage, or of the first bit line and first reference voltage or first supply voltage, or of the second bit line and second reference voltage or second supply voltage are configured such that data of the first storage node and the inverted first storage node (D') can be read and written independently, characterised in that a first word line voltage of the first word line is boosted, such as boosted to a level of at least two times the first supply voltage, and wherein a first bit line voltage of the first bit line is boosted, such as boosted to a level of at least two times the first supply voltage during a write access of the first storage node, and wherein a second word line voltage of the second word line is boosted, such as boosted to a level of at least two times the second supply voltage, and wherein a second bit line voltage of the second bit line is boosted, such as boosted to a level of at least two times the second supply voltage during a write access of the inverted first storage node (D'), wherein the write access is the process of writing a logical "1" to the first storage node or the inverted first storage node (D'). - a first transistor, a second transistor, a third transistor and a fourth transistor forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node and an inverted first storage node (D'), wherein the first inverter is connected to a first reference voltage and a first supply voltage, and wherein the second inverter is connected to a second reference voltage and a second supply voltage; - a fifth transistor connected between the first storage node and a first bit line; - a sixth transistor connected between the inverted first storage node (D') and a second bit line; - a first word line connected to the fifth transistor, said first word line controlling the access of the first bit line to the first storage node; and - a second word line, independent of the first word line, connected to the sixth transistor, said second word line controlling the access of the second bit line to the inverted first storage node (D') independently of the first bit line; a first word line voltage of the first word line is boosted, such as boosted to a level of at least two times the first supply voltage, and wherein a first bit line voltage of the first bit line is boosted, such as boosted to a level of at least two times the first supply voltage during a write access of the first storage node, and wherein a second word line voltage of the second word line is boosted, such as boosted to a level of at least two times the second supply voltage, and wherein a second bit line voltage of the second bit line is boosted, such as boosted to a level of at least two times the second supply voltage during a write access of the inverted first storage node (D'), wherein the write access is the process of writing a logical "1" to the first storage node or the inverted first storage node (D').