A display substrate having a display area and a peripheral area, comprising: a base substrate; a first power pad on the base substrate, the first power pad comprising a first portion in the peripheral area and along a power line interface side of the display substrate, wherein the power line interface side is an integrated circuit bonding side of the display substrate at which one or more integrated circuits are connected to the display substrate; a planarization layer on a side of the first power pad away from the base substrate; a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; an encapsulating layer on a side of the pixel definition layer away from the base substrate; and a second power pad on the base substrate and in the peripheral area, the second power pad spaced apart from the first power pad, wherein the display substrate comprises a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area; and the encapsulating layer extends into the first groove and is in direct contact with the surface of the first portion, thereby encapsulating the display substrate; wherein the first portion comprises a first side away from the base substrate, a second side opposite to the first side and closer to the base substrate, a third side connecting the first side and the second side and closer to the display area, and a fourth side connecting the first side and the second side, the fourth side being opposite to the third side and away from the display area; the fourth side of the first portion is covered by one or a combination of the pixel definition layer and the planarization layer; the first groove exposes a portion of the first side; and the fourth side has a concave surface; and wherein the second power pad comprises at least one third portion on the power line interface side of the display substrate, the at least one third portion at least partially covered by one or a combination of the pixel definition layer and the planarization layer; the at least one third portion is on a side of the first portion extending away from the display area, the fourth side of the first portion and a respective one of the at least one third portion being spaced apart by a first gap; and the first groove is on a side of the first gap close to the display area. a base substrate; a first power pad on the base substrate, the first power pad comprising a first portion in the peripheral area and along a power line interface side of the display substrate, wherein the power line interface side is an integrated circuit bonding side of the display substrate at which one or more integrated circuits are connected to the display substrate; a planarization layer on a side of the first power pad away from the base substrate; a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; an encapsulating layer on a side of the pixel definition layer away from the base substrate; and a second power pad on the base substrate and in the peripheral area, the second power pad spaced apart from the first power pad, wherein the display substrate comprises a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area; and the encapsulating layer extends into the first groove and is in direct contact with the surface of the first portion, thereby encapsulating the display substrate; wherein the first portion comprises a first side away from the base substrate, a second side opposite to the first side and closer to the base substrate, a third side connecting the first side and the second side and closer to the display area, and a fourth side connecting the first side and the second side, the fourth side being opposite to the third side and away from the display area; the fourth side of the first portion is covered by one or a combination of the pixel definition layer and the planarization layer; the first groove exposes a portion of the first side; and the fourth side has a concave surface; and wherein the second power pad comprises at least one third portion on the power line interface side of the display substrate, the at least one third portion at least partially covered by one or a combination of the pixel definition layer and the planarization layer; the at least one third portion is on a side of the first portion extending away from the display area, the fourth side of the first portion and a respective one of the at least one third portion being spaced apart by a first gap; and the first groove is on a side of the first gap close to the display area.