A method comprising: performing a write operation to program a one-time programmable, OTP, memory device (100, 150, 202, 404, 602) to a non-volatile state, wherein the non-volatile state is based on a threshold voltage shift of the OTP memory device (100, 150, 202, 404, 602) and associated with a logical value at the OTP memory device (100, 150, 202, 404, 602), wherein the OTP memory device (100, 150, 202, 602) includes a p-type metal oxide semiconductor, PMOS, transistor with a breakdown condition, wherein the PMOS transistor includes a p-type metal gate, a substrate material, and an oxide layer between the p-type metal gate and the substrate material, the oxide layer comprising a hafnium oxide layer contacting the p-type metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer, wherein performing the write operation comprises applying a write voltage across the p-type metal gate while applying current compliance to generate a soft breakdown condition, wherein the soft breakdown condition is characterised in that the OTP memory device undergoes a non volatile threshold voltage shift but the gate voltage maintains control of the channel current between source and drain; and performing a read operation to read the non-volatile state at the OTP memory device (100, 150, 202, 404, 602). performing a write operation to program a one-time programmable, OTP, memory device (100, 150, 202, 404, 602) to a non-volatile state, wherein the non-volatile state is based on a threshold voltage shift of the OTP memory device (100, 150, 202, 404, 602) and associated with a logical value at the OTP memory device (100, 150, 202, 404, 602), wherein the OTP memory device (100, 150, 202, 602) includes a p-type metal oxide semiconductor, PMOS, transistor with a breakdown condition, wherein the PMOS transistor includes a p-type metal gate, a substrate material, and an oxide layer between the p-type metal gate and the substrate material, the oxide layer comprising a hafnium oxide layer contacting the p-type metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer, wherein performing the write operation comprises applying a write voltage across the p-type metal gate while applying current compliance to generate a soft breakdown condition, wherein the soft breakdown condition is characterised in that the OTP memory device undergoes a non volatile threshold voltage shift but the gate voltage maintains control of the channel current between source and drain; and wherein the non-volatile state is based on a threshold voltage shift of the OTP memory device (100, 150, 202, 404, 602) and associated with a logical value at the OTP memory device (100, 150, 202, 404, 602), wherein the OTP memory device (100, 150, 202, 602) includes a p-type metal oxide semiconductor, PMOS, transistor with a breakdown condition, wherein the PMOS transistor includes a p-type metal gate, a substrate material, and an oxide layer between the p-type metal gate and the substrate material, the oxide layer comprising a hafnium oxide layer contacting the p-type metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer, wherein performing the write operation comprises applying a write voltage across the p-type metal gate while applying current compliance to generate a soft breakdown condition, wherein the soft breakdown condition is characterised in that the OTP memory device undergoes a non volatile threshold voltage shift but the gate voltage maintains control of the channel current between source and drain; and performing a read operation to read the non-volatile state at the OTP memory device (100, 150, 202, 404, 602).