An impedance matching circuit comprising: a transistor (208, 308) comprising a gate electrode (210, 310); and a voltage source (250, 350) having a circuit node (256, 356) electrically coupled to the gate electrode of the transistor, via a multiplexer (212, 224, 312, 324), and configured to apply a gate voltage to the gate electrode of the transistor, wherein the voltage source comprises: a current source (252, 352) electrically coupled between a first power supply (254, 354) and the circuit node (256, 356); a plurality of impedance components (260-1, 260-2, 260-n, 360-1, 360-2, 360-n) electrically coupled in series between the circuit node (256, 356) and a second power supply (206, 306); and wherein the multiplexer (212, 224, 312, 324) comprises a high voltage terminal and a low voltage terminal which are electrically coupled, either, according to a first arrangement, to the circuit node (256, 356) and to the second power supply (206, 306), respectively, or, according to a second arrangement, to the second power supply and the circuit node respectively, wherein the circuit node (256, 356) is coupled to the gate electrode (210, 310) of the transistor (208, 308) via either the high voltage terminal in the first arrangement or via the low voltage terminal in the second arrangement, wherein the multiplexer is configured to selectively electrically couple the circuit node to the gate electrode (210, 310) of the transistor (208, 308) in response to a control signal voltage (V ENABLE), wherein the impedance components (260-1, 260-2, 260-n, 360-1, 360-2, 360-n) comprise a plurality of diode-connected transistors or a plurality of diodes. a transistor (208, 308) comprising a gate electrode (210, 310); and a voltage source (250, 350) having a circuit node (256, 356) electrically coupled to the gate electrode of the transistor, via a multiplexer (212, 224, 312, 324), and configured to apply a gate voltage to the gate electrode of the transistor, wherein the voltage source comprises: a current source (252, 352) electrically coupled between a first power supply (254, 354) and the circuit node (256, 356); a plurality of impedance components (260-1, 260-2, 260-n, 360-1, 360-2, 360-n) electrically coupled in series between the circuit node (256, 356) and a second power supply (206, 306); and wherein the multiplexer (212, 224, 312, 324) comprises a high voltage terminal and a low voltage terminal which are electrically coupled, either, according to a first arrangement, to the circuit node (256, 356) and to the second power supply (206, 306), respectively, or, according to a second arrangement, to the second power supply and the circuit node respectively, wherein the circuit node (256, 356) is coupled to the gate electrode (210, 310) of the transistor (208, 308) via either the high voltage terminal in the first arrangement or via the low voltage terminal in the second arrangement, wherein the multiplexer is configured to selectively electrically couple the circuit node to the gate electrode (210, 310) of the transistor (208, 308) in response to a control signal voltage (V ENABLE), wherein the impedance components (260-1, 260-2, 260-n, 360-1, 360-2, 360-n) comprise a plurality of diode-connected transistors or a plurality of diodes. a current source (252, 352) electrically coupled between a first power supply (254, 354) and the circuit node (256, 356); a plurality of impedance components (260-1, 260-2, 260-n, 360-1, 360-2, 360-n) electrically coupled in series between the circuit node (256, 356) and a second power supply (206, 306); and wherein the multiplexer (212, 224, 312, 324) comprises a high voltage terminal and a low voltage terminal which are electrically coupled, either, according to a first arrangement, to the circuit node (256, 356) and to the second power supply (206, 306), respectively, or, according to a second arrangement, to the second power supply and the circuit node respectively, wherein the circuit node (256, 356) is coupled to the gate electrode (210, 310) of the transistor (208, 308) via either the high voltage terminal in the first arrangement or via the low voltage terminal in the second arrangement, wherein the multiplexer is configured to selectively electrically couple the circuit node to the gate electrode (210, 310) of the transistor (208, 308) in response to a control signal voltage (V ENABLE), wherein the impedance components (260-1, 260-2, 260-n, 360-1, 360-2, 360-n) comprise a plurality of diode-connected transistors or a plurality of diodes.