A commutation cell configured for limiting switching overvoltage and for limiting recovery current, comprising: a power electronic switch ( Q 1) having a gate and a parasitic emitter inductance through which a voltage ( V Le) is generated upon turning on and off of the power electronic switch ( Q 1); a compensation circuit connected to the parasitic emitter inductance, and a gate driver connected to the compensation circuit and to the gate of the power electronic switch ( Q 1), the gate driver controlling a gate to emitter voltage ( V ge) applied to the power electronic switch ( Q 1), the gate driver including a reference; characterized in that: the compensation circuit comprises a resistive gain adaptor having a first resistor ( R e1) defining in part a first gain value, the resistive gain adaptor further comprising a turn-on diode ( D on) configured to place a second resistor ( R eON) in parallel with the first resistor ( R e1) when turning on the power electronic switch ( Q 1), the second resistor ( R eON) and the turn-on diode ( D on) being distinct components of the resistive gain adaptor, the first and second resistors ( R e1, R eON) in parallel defining in part a second gain value lower than the first gain value and greater than zero, the compensation circuit being configured to: 1) apply the first gain value to provide a sample of the voltage ( V Le) generated through the parasitic emitter inductance at turn-off of the power electronic switch ( Q 1), 2) apply the second gain value to provide a sample of the voltage ( V Le) generated through the parasitic emitter inductance at turn-on of the power electronic switch ( Q 1), and 3) add the samples of the voltage ( V Le) generated through the parasitic emitter inductance between the reference of the gate driver and the gate of the power electronic switch ( Q 1) to control the voltage ( V Le) generated through the parasitic emitter inductance. a power electronic switch ( Q 1) having a gate and a parasitic emitter inductance through which a voltage ( V Le) is generated upon turning on and off of the power electronic switch ( Q 1); a compensation circuit connected to the parasitic emitter inductance, and a gate driver connected to the compensation circuit and to the gate of the power electronic switch ( Q 1), the gate driver controlling a gate to emitter voltage ( V ge) applied to the power electronic switch ( Q 1), the gate driver including a reference; characterized in that: the compensation circuit comprises a resistive gain adaptor having a first resistor ( R e1) defining in part a first gain value, the resistive gain adaptor further comprising a turn-on diode ( D on) configured to place a second resistor ( R eON) in parallel with the first resistor ( R e1) when turning on the power electronic switch ( Q 1), the second resistor ( R eON) and the turn-on diode ( D on) being distinct components of the resistive gain adaptor, the first and second resistors ( R e1, R eON) in parallel defining in part a second gain value lower than the first gain value and greater than zero, the compensation circuit being configured to: 1) apply the first gain value to provide a sample of the voltage ( V Le) generated through the parasitic emitter inductance at turn-off of the power electronic switch ( Q 1), 2) apply the second gain value to provide a sample of the voltage ( V Le) generated through the parasitic emitter inductance at turn-on of the power electronic switch ( Q 1), and 3) add the samples of the voltage ( V Le) generated through the parasitic emitter inductance between the reference of the gate driver and the gate of the power electronic switch ( Q 1) to control the voltage ( V Le) generated through the parasitic emitter inductance. 1) apply the first gain value to provide a sample of the voltage ( V Le) generated through the parasitic emitter inductance at turn-off of the power electronic switch ( Q 1), 2) apply the second gain value to provide a sample of the voltage ( V Le) generated through the parasitic emitter inductance at turn-on of the power electronic switch ( Q 1), and 3) add the samples of the voltage ( V Le) generated through the parasitic emitter inductance between the reference of the gate driver and the gate of the power electronic switch ( Q 1) to control the voltage ( V Le) generated through the parasitic emitter inductance.