A phase-locked loop, PLL, comprising: an oscillator configured to generate a PLL output signal at an output of the PLL responsive to a reference signal input to the PLL; a detector configured to compare the reference signal to a feedback signal to control a frequency of the PLL output signal, the feedback signal being derived by a feedback path of the PLL from the PLL output signal; and a phase control circuit operatively connected to the feedback path of the PLL, said phase control circuit configured to generate a timing control signal responsive to a phase control signal, wherein application of the timing control signal to the feedback path shifts a timing of one or more pulses of the feedback signal to achieve a desired average time shift to generate a desired phase shift at the output of the PLL while maintaining a desired average divisor of the feedback signal; wherein the feedback path of the PLL comprises: a frequency divider configured to divide the frequency of the PLL output signal by a frequency divisor; a multiplexer controlled by the timing control signal, the multiplexer comprising a multiplexer output operatively connected to the detector and a plurality of multiplexer input connections; and a delay line comprising a plurality of serially connected delay elements operatively connected between the frequency divider and the multiplexer, said plurality of multiplexer input connections comprising an output of the frequency divider and outputs of at least some of the plurality of delay elements; wherein the multiplexer is configured to periodically select, responsive to the timing control signal, the signal at one of the plurality of multiplexer inputs as the feedback signal. an oscillator configured to generate a PLL output signal at an output of the PLL responsive to a reference signal input to the PLL; a detector configured to compare the reference signal to a feedback signal to control a frequency of the PLL output signal, the feedback signal being derived by a feedback path of the PLL from the PLL output signal; and a phase control circuit operatively connected to the feedback path of the PLL, said phase control circuit configured to generate a timing control signal responsive to a phase control signal, wherein application of the timing control signal to the feedback path shifts a timing of one or more pulses of the feedback signal to achieve a desired average time shift to generate a desired phase shift at the output of the PLL while maintaining a desired average divisor of the feedback signal; a frequency divider configured to divide the frequency of the PLL output signal by a frequency divisor; a multiplexer controlled by the timing control signal, the multiplexer comprising a multiplexer output operatively connected to the detector and a plurality of multiplexer input connections; and a delay line comprising a plurality of serially connected delay elements operatively connected between the frequency divider and the multiplexer, said plurality of multiplexer input connections comprising an output of the frequency divider and outputs of at least some of the plurality of delay elements; wherein the multiplexer is configured to periodically select, responsive to the timing control signal, the signal at one of the plurality of multiplexer inputs as the feedback signal.