An apparatus comprising: a processor; a packet generation logic adapted to generate a first packet including a first header portion, a first command portion and a first data payload portion, the first data payload portion comprising first data, wherein the first command portion comprises a first independent burst size and a first independent wrapping border, the first burst size being a size of the first data payload portion, the apparatus being characterized in that: the first burst size is in a measuring unit being a first fixed quantity, the first wrapping border is in a measuring unit being a second fixed quantity, in the expression fixed quantity means a quantity of data depending neither on the data width of the processor nor on the data width of any of the links of a network; the apparatus is in at least one of the following three implementations: in a wrapping burst implementation, the first wrapping border specifies a first value of an address jump between an end border and a start border of the address space used for the data by the processor, in a fixed address burst implementation, the first wrapping border specifies a first value of a beat size of the processor, i.e. at the processor, an amount of data that can be sent by the processor in a single clock cycle, in an incrementing burst implementation, the first wrapping border specifies a first value of the first wrapping border that is possible neither in a wrapping burst implementation nor in a fixed address burst implementation, the apparatus comprises an encoding logic adapted to encode the first packet with a first data width, by encoding the first command portion, the first independent burst size and the first independent wrapping border are independent in that they are information which is unassociated with a native bit width of the encoding logic and which is static as it traverses the network such that command re-coding operations are not required, and the apparatus further comprises a packet insertion logic adapted to insert the first packet into a first link of the network, the first link having the first width. a processor; a packet generation logic adapted to generate a first packet including a first header portion, a first command portion and a first data payload portion, the first data payload portion comprising first data, wherein the first command portion comprises a first independent burst size and a first independent wrapping border, the first burst size being a size of the first data payload portion, the apparatus being characterized in that: the first burst size is in a measuring unit being a first fixed quantity, the first wrapping border is in a measuring unit being a second fixed quantity, the first burst size is in a measuring unit being a first fixed quantity, the first wrapping border is in a measuring unit being a second fixed quantity, in the expression fixed quantity means a quantity of data depending neither on the data width of the processor nor on the data width of any of the links of a network; the apparatus is in at least one of the following three implementations: in a wrapping burst implementation, the first wrapping border specifies a first value of an address jump between an end border and a start border of the address space used for the data by the processor, in a fixed address burst implementation, the first wrapping border specifies a first value of a beat size of the processor, i.e. at the processor, an amount of data that can be sent by the processor in a single clock cycle, in an incrementing burst implementation, the first wrapping border specifies a first value of the first wrapping border that is possible neither in a wrapping burst implementation nor in a fixed address burst implementation, the apparatus comprises an encoding logic adapted to encode the first packet with a first data width, by encoding the first command portion, the first independent burst size and the first independent wrapping border are independent in that they are information which is unassociated with a native bit width of the encoding logic and which is static as it traverses the network such that command re-coding operations are not required, and the apparatus further comprises a packet insertion logic adapted to insert the first packet into a first link of the network, the first link having the first width. in a wrapping burst implementation, the first wrapping border specifies a first value of an address jump between an end border and a start border of the address space used for the data by the processor, in a fixed address burst implementation, the first wrapping border specifies a first value of a beat size of the processor, i.e. at the processor, an amount of data that can be sent by the processor in a single clock cycle, in an incrementing burst implementation, the first wrapping border specifies a first value of the first wrapping border that is possible neither in a wrapping burst implementation nor in a fixed address burst implementation, the apparatus comprises an encoding logic adapted to encode the first packet with a first data width, by encoding the first command portion, the first independent burst size and the first independent wrapping border are independent in that they are information which is unassociated with a native bit width of the encoding logic and which is static as it traverses the network such that command re-coding operations are not required, and the apparatus further comprises a packet insertion logic adapted to insert the first packet into a first link of the network, the first link having the first width.