A method of disabling and enabling clock signals so as to restore a relative phase relationship between them, comprising: receiving a reference clock signal; dividing the reference clock signal by at least a factor of two to generate a master clock signal; generating a first output clock signal from the reference clock signal and synchronously to the master clock signal in a first phase circuit; generating a second output clock signal from the reference clock signal and synchronously to the master clock signal in a second phase circuit, the second output clock signal having a predetermined phase relationship with the first output clock signal; disabling one of the first and second phase circuits (26A, 26B) to suppress generation of the respective output clock signal; and enabling the disabled phase circuit (26A,26B) synchronously to the master clock signal, such that after enabling the phase circuit, the predetermined phase relationship between the first and second output clock signals is restored; wherein enabling a disabled phase circuit (26A,26B) synchronously to the master clock signal comprises enabling the phase circuit only upon the conditions of an output clock enable signal (34A, 34B) associated with the phase circuit being asserted and the receipt, by a synchronization circuit (28A, 28B) associated with the disabled phase circuit (26A, 26B), of a predetermined number of master clock signal synchronizing edges, wherein the predetermined number of master clock signal synchronizing edges is at least two; wherein determining the receipt of a predetermined number of master clock signal synchronizing edges comprises clocking a chain comprising a corresponding number of serially connected storage elements (36A, 38A; 36B, 38B), comprised in the synchronization circuit (28A, 28B), with a synchronizing edge of the master clock signal, wherein a phase circuit enable signal (30A, 30B) is provided at the output of the chain, and the phase circuit is enabled, by logic comprised in the synchronization circuit, only if both the output clock enable signal (34A, 34B) and the phase circuit enable signal (30A, 30B) at the output of the storage element chain are asserted. receiving a reference clock signal; dividing the reference clock signal by at least a factor of two to generate a master clock signal; generating a first output clock signal from the reference clock signal and synchronously to the master clock signal in a first phase circuit; generating a second output clock signal from the reference clock signal and synchronously to the master clock signal in a second phase circuit, the second output clock signal having a predetermined phase relationship with the first output clock signal; disabling one of the first and second phase circuits (26A, 26B) to suppress generation of the respective output clock signal; and enabling the disabled phase circuit (26A,26B) synchronously to the master clock signal, such that after enabling the phase circuit, the predetermined phase relationship between the first and second output clock signals is restored; wherein enabling a disabled phase circuit (26A,26B) synchronously to the master clock signal comprises enabling the phase circuit only upon the conditions of an output clock enable signal (34A, 34B) associated with the phase circuit being asserted and the receipt, by a synchronization circuit (28A, 28B) associated with the disabled phase circuit (26A, 26B), of a predetermined number of master clock signal synchronizing edges, wherein the predetermined number of master clock signal synchronizing edges is at least two; wherein determining the receipt of a predetermined number of master clock signal synchronizing edges comprises clocking a chain comprising a corresponding number of serially connected storage elements (36A, 38A; 36B, 38B), comprised in the synchronization circuit (28A, 28B), with a synchronizing edge of the master clock signal, wherein a phase circuit enable signal (30A, 30B) is provided at the output of the chain, and the phase circuit is enabled, by logic comprised in the synchronization circuit, only if both the output clock enable signal (34A, 34B) and the phase circuit enable signal (30A, 30B) at the output of the storage element chain are asserted.