A shift register, comprising: an input sub-circuit, comprising a first transistor and a second transistor, wherein the first transistor has a control electrode and a first electrode both coupled to an input signal terminal (Input), and a second electrode coupled to a first electrode of the second transistor, and the second transistor has a control electrode coupled to a first clock signal terminal (CLKA) and a second electrode coupled to a pull-up node; an output sub-circuit, comprising a third transistor and a first capacitor, wherein the third transistor has a control electrode coupled to the pull-up node, a first electrode coupled to a second clock signal terminal (CLKB), and a second electrode coupled to an output terminal, and the first capacitor has a first end coupled to the control electrode of the third transistor and a second end coupled to the second electrode of the third transistor; a reset control sub-circuit, comprising a fifth transistor, a sixth transistor, and a second capacitor, wherein the fifth transistor has a control electrode and a first electrode both coupled to the first clock signal terminal, and a second electrode coupled to a pull-down node, the sixth transistor has a control electrode coupled to the input signal terminal (Input), a first electrode coupled to the second electrode of the fifth transistor, and a second electrode coupled to a level signal terminal for providing a constant low voltage level, and the second capacitor has a first end coupled to the first electrode of the sixth transistor and a second end coupled to the second electrode of the sixth transistor, and a ratio of a width-to-length ratio of the fifth transistor to a width-to-length ratio of the sixth transistor is 1:5; and a reset sub-circuit, comprising a fourth transistor and a seventh transistor, wherein the fourth transistor has a control electrode coupled to the pull-down node, a first electrode coupled to the output terminal, and a second electrode coupled to the level signal terminal, and the seventh transistor has a control electrode coupled to the pull-down node, a first electrode coupled to the pull-up node, and a second electrode coupled to the level signal terminal. an input sub-circuit, comprising a first transistor and a second transistor, wherein the first transistor has a control electrode and a first electrode both coupled to an input signal terminal (Input), and a second electrode coupled to a first electrode of the second transistor, and the second transistor has a control electrode coupled to a first clock signal terminal (CLKA) and a second electrode coupled to a pull-up node; an output sub-circuit, comprising a third transistor and a first capacitor, wherein the third transistor has a control electrode coupled to the pull-up node, a first electrode coupled to a second clock signal terminal (CLKB), and a second electrode coupled to an output terminal, and the first capacitor has a first end coupled to the control electrode of the third transistor and a second end coupled to the second electrode of the third transistor; a reset control sub-circuit, comprising a fifth transistor, a sixth transistor, and a second capacitor, wherein the fifth transistor has a control electrode and a first electrode both coupled to the first clock signal terminal, and a second electrode coupled to a pull-down node, the sixth transistor has a control electrode coupled to the input signal terminal (Input), a first electrode coupled to the second electrode of the fifth transistor, and a second electrode coupled to a level signal terminal for providing a constant low voltage level, and the second capacitor has a first end coupled to the first electrode of the sixth transistor and a second end coupled to the second electrode of the sixth transistor, and a ratio of a width-to-length ratio of the fifth transistor to a width-to-length ratio of the sixth transistor is 1:5; and a reset sub-circuit, comprising a fourth transistor and a seventh transistor, wherein the fourth transistor has a control electrode coupled to the pull-down node, a first electrode coupled to the output terminal, and a second electrode coupled to the level signal terminal, and the seventh transistor has a control electrode coupled to the pull-down node, a first electrode coupled to the pull-up node, and a second electrode coupled to the level signal terminal.