A nonvolatile memory device comprising a first nonvolatile memory (M1, M11, M12) and a second nonvolatile memory (M2, M12, M22, M222), which are sequentially stacked and have a complementary relationship to each other, wherein the first nonvolatile memory (M1, M11, M12) comprises: a first substrate including first isolation layers, a p-type first impurity region and a p-type second impurity region disposed between the first isolation layers, and a first channel region disposed between the p-type first and second impurity regions (10s, 10d); and a first gate stacked structure disposed on the first channel region, wherein the first gate stacked structure includes a first insulating layer, a first data storage layer, a second insulating layer, and a first control gate, which are sequentially stacked; further comprising: a first contact pad layer (P1, P11) and a second contact pad layer (P2, P22) disposed on and extending outside the p-type first and second impurity regions (10s,10d), respectively; a first interlayer dielectric covering the first (P1, P11) and second contact (P2, P22) pad layers and the first gate stacked structure; wherein the second nonvolatile memory comprises: a second substrate including second isolation layers, an n-type first impurity region and an n-type second impurity region disposed between the second isolation layers, and a second channel region disposed between the n-type first and second impurity regions (30s, 30d); and a second gate stacked structure disposed on the second channel region between the n-type first and second impurity regions (30s, 30d), wherein the second gate stacked structure includes a third insulating layer, a second data storage layer, a fourth insulating layer, and a second control gate, which are sequentially stacked; a third contact pad layer (P3, P33) and a fourth contact pad layer (P4, P44) disposed on and extending outside the n-type first and second impurity regions (30s, 30d), respectively; and a second interlayer dielectric covering the third (P3, P33) and fourth (P4, P44) contact pad layers and the second gate stacked structure and bonded to the first interlayer dielectric; wherein the second nonvolatile memory is inverted. a first substrate including first isolation layers, a p-type first impurity region and a p-type second impurity region disposed between the first isolation layers, and a first channel region disposed between the p-type first and second impurity regions (10s, 10d); and a first gate stacked structure disposed on the first channel region, wherein the first gate stacked structure includes a first insulating layer, a first data storage layer, a second insulating layer, and a first control gate, which are sequentially stacked; further comprising: a first contact pad layer (P1, P11) and a second contact pad layer (P2, P22) disposed on and extending outside the p-type first and second impurity regions (10s,10d), respectively; a first interlayer dielectric covering the first (P1, P11) and second contact (P2, P22) pad layers and the first gate stacked structure; a first contact pad layer (P1, P11) and a second contact pad layer (P2, P22) disposed on and extending outside the p-type first and second impurity regions (10s,10d), respectively; a first interlayer dielectric covering the first (P1, P11) and second contact (P2, P22) pad layers and the first gate stacked structure; wherein the second nonvolatile memory comprises: a second substrate including second isolation layers, an n-type first impurity region and an n-type second impurity region disposed between the second isolation layers, and a second channel region disposed between the n-type first and second impurity regions (30s, 30d); and a second gate stacked structure disposed on the second channel region between the n-type first and second impurity regions (30s, 30d), wherein the second gate stacked structure includes a third insulating layer, a second data storage layer, a fourth insulating layer, and a second control gate, which are sequentially stacked; a third contact pad layer (P3, P33) and a fourth contact pad layer (P4, P44) disposed on and extending outside the n-type first and second impurity regions (30s, 30d), respectively; and a second interlayer dielectric covering the third (P3, P33) and fourth (P4, P44) contact pad layers and the second gate stacked structure and bonded to the first interlayer dielectric; wherein the second nonvolatile memory is inverted. a second substrate including second isolation layers, an n-type first impurity region and an n-type second impurity region disposed between the second isolation layers, and a second channel region disposed between the n-type first and second impurity regions (30s, 30d); and a second gate stacked structure disposed on the second channel region between the n-type first and second impurity regions (30s, 30d), wherein the second gate stacked structure includes a third insulating layer, a second data storage layer, a fourth insulating layer, and a second control gate, which are sequentially stacked; a third contact pad layer (P3, P33) and a fourth contact pad layer (P4, P44) disposed on and extending outside the n-type first and second impurity regions (30s, 30d), respectively; and a second interlayer dielectric covering the third (P3, P33) and fourth (P4, P44) contact pad layers and the second gate stacked structure and bonded to the first interlayer dielectric; wherein the second nonvolatile memory is inverted.