A system, comprising: a field-programmable gate array, FPGA, comprising: an input pad configured to receive a signal; an input serializer comprising x serializer shift registers, wherein x is an integer greater than or equal to 2, wherein the input serializer is configured to receive the signal, wherein the signal passes through each serializer shift register in series, wherein the input serializer is configured to output an x-bit serial data word formed by the parallel data at the output of each serializer shift register indicative of the signal, wherein each serializer shift register shifts data at the time period of a serializer clock, wherein the input serializer takes x time periods to complete output of the x-bit serial data word; and an x-bit wide shift register communicatively coupled to the input serializer, wherein the x-bit wide shift register is an input deserializer, wherein the x-bit wide shift register is configured to receive the x-bit serial data word from the input serializer, wherein the x-bit wide shift register is sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the x-bit serial data word, wherein a speed of the shift register clock is less than a speed of the serializer clock, wherein the x-bit wide shift register has a shift register latency value indicative of an amount of time for the signal to travel from the input pad through the x-bit wide shift register; wherein the FPGA is configured to: determine a time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value; and determine a time when the signal arrived at the input pad based at least on the shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value. a field-programmable gate array, FPGA, comprising: an input pad configured to receive a signal; an input serializer comprising x serializer shift registers, wherein x is an integer greater than or equal to 2, wherein the input serializer is configured to receive the signal, wherein the signal passes through each serializer shift register in series, wherein the input serializer is configured to output an x-bit serial data word formed by the parallel data at the output of each serializer shift register indicative of the signal, wherein each serializer shift register shifts data at the time period of a serializer clock, wherein the input serializer takes x time periods to complete output of the x-bit serial data word; and an x-bit wide shift register communicatively coupled to the input serializer, wherein the x-bit wide shift register is an input deserializer, wherein the x-bit wide shift register is configured to receive the x-bit serial data word from the input serializer, wherein the x-bit wide shift register is sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the x-bit serial data word, wherein a speed of the shift register clock is less than a speed of the serializer clock, wherein the x-bit wide shift register has a shift register latency value indicative of an amount of time for the signal to travel from the input pad through the x-bit wide shift register; an input pad configured to receive a signal; an input serializer comprising x serializer shift registers, wherein x is an integer greater than or equal to 2, wherein the input serializer is configured to receive the signal, wherein the signal passes through each serializer shift register in series, wherein the input serializer is configured to output an x-bit serial data word formed by the parallel data at the output of each serializer shift register indicative of the signal, wherein each serializer shift register shifts data at the time period of a serializer clock, wherein the input serializer takes x time periods to complete output of the x-bit serial data word; and an x-bit wide shift register communicatively coupled to the input serializer, wherein the x-bit wide shift register is an input deserializer, wherein the x-bit wide shift register is configured to receive the x-bit serial data word from the input serializer, wherein the x-bit wide shift register is sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the x-bit serial data word, wherein a speed of the shift register clock is less than a speed of the serializer clock, wherein the x-bit wide shift register has a shift register latency value indicative of an amount of time for the signal to travel from the input pad through the x-bit wide shift register; wherein the FPGA is configured to: determine a time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value; and determine a time when the signal arrived at the input pad based at least on the shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.