A method for manufacturing a cell library, comprising: specifying a base structure comprising: a first block including a set of semiconductor fins (730, 731) in a first region of a substrate, the first block including outer fins on opposing outside edges of the first block, and inner fins between the outer fins, the first block being arranged for devices having channels with a first conductivity type; a second block including a set of semiconductor fins in a second region of the substrate, the second block including outer fins on opposing outside edges of the second block, and inner fins between the outer fins, the second block being arranged for devices having channels with a second conductivity type; specifying a cell on the base structure, the cell comprising elements of: a patterned gate conductor layer (720, 755; 721, 765) including a plurality of gate traces in the first and second blocks; at least one patterned conductor layer (722, 733, 743, 752, 762, 770) over the gate conductor layer, wherein a first trace in the at least one patterned conductor layer is arranged to connect a first plurality of semiconductor fins of the set of semiconductor fins in the first block to a second plurality of semiconductor fins of the set of semiconductor fins in the second block; one or more power traces arranged overlying each of the first and second blocks; and a plurality of inter-layer connectors (723, 724, 725, 732, 734, 742, 744, 753, 754, 763, 764, 771, 772, 775) that connect semiconductor fins, gate traces, traces in the at least one patterned conductor layer, and the one or more power traces; and storing machine readable specifications of the cell in a cell library. specifying a base structure comprising: a first block including a set of semiconductor fins (730, 731) in a first region of a substrate, the first block including outer fins on opposing outside edges of the first block, and inner fins between the outer fins, the first block being arranged for devices having channels with a first conductivity type; a second block including a set of semiconductor fins in a second region of the substrate, the second block including outer fins on opposing outside edges of the second block, and inner fins between the outer fins, the second block being arranged for devices having channels with a second conductivity type; a first block including a set of semiconductor fins (730, 731) in a first region of a substrate, the first block including outer fins on opposing outside edges of the first block, and inner fins between the outer fins, the first block being arranged for devices having channels with a first conductivity type; a second block including a set of semiconductor fins in a second region of the substrate, the second block including outer fins on opposing outside edges of the second block, and inner fins between the outer fins, the second block being arranged for devices having channels with a second conductivity type; specifying a cell on the base structure, the cell comprising elements of: a patterned gate conductor layer (720, 755; 721, 765) including a plurality of gate traces in the first and second blocks; at least one patterned conductor layer (722, 733, 743, 752, 762, 770) over the gate conductor layer, wherein a first trace in the at least one patterned conductor layer is arranged to connect a first plurality of semiconductor fins of the set of semiconductor fins in the first block to a second plurality of semiconductor fins of the set of semiconductor fins in the second block; one or more power traces arranged overlying each of the first and second blocks; and a plurality of inter-layer connectors (723, 724, 725, 732, 734, 742, 744, 753, 754, 763, 764, 771, 772, 775) that connect semiconductor fins, gate traces, traces in the at least one patterned conductor layer, and the one or more power traces; and storing machine readable specifications of the cell in a cell library. a patterned gate conductor layer (720, 755; 721, 765) including a plurality of gate traces in the first and second blocks; at least one patterned conductor layer (722, 733, 743, 752, 762, 770) over the gate conductor layer, wherein a first trace in the at least one patterned conductor layer is arranged to connect a first plurality of semiconductor fins of the set of semiconductor fins in the first block to a second plurality of semiconductor fins of the set of semiconductor fins in the second block; one or more power traces arranged overlying each of the first and second blocks; and a plurality of inter-layer connectors (723, 724, 725, 732, 734, 742, 744, 753, 754, 763, 764, 771, 772, 775) that connect semiconductor fins, gate traces, traces in the at least one patterned conductor layer, and the one or more power traces; and