A data processing device comprising: a set associative type cache memory which stores cache entries in a plurality of ways (12, 13), wherein when reading cache tags, the cache memory selects using a select circuit (71, 71A), from among the plurality of ways (12, 13), part of the ways (12, 13) according to a value of select data created based on tag address information which is part of address information, and reads cache tags from the selected ways (12, 13) by use of an index address in the address information, and when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways (12, 13) according to the value of the select data, characterized in that: the cache memory creates parity data in connection with tag address information which is part of the address information and an even-odd select signal which specifies even or odd parity to be used, and uses the parity data as the select data, the ways (12, 13) have tag ways for storing the cache tag corresponding to the index address and data ways for storing data corresponding to the index address, the cache entry includes the cache tag and data corresponding thereto, the tag ways are constituted by memory blocks whose activation or inactivation is selected for each tag way respectively, and when reading cache tags, the cache memory activates the some tag ways according to the value of the select data by memory block activation by use of the select data and deactivates the other tag ways. a set associative type cache memory which stores cache entries in a plurality of ways (12, 13), wherein when reading cache tags, the cache memory selects using a select circuit (71, 71A), from among the plurality of ways (12, 13), part of the ways (12, 13) according to a value of select data created based on tag address information which is part of address information, and reads cache tags from the selected ways (12, 13) by use of an index address in the address information, and when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways (12, 13) according to the value of the select data, characterized in that: the cache memory creates parity data in connection with tag address information which is part of the address information and an even-odd select signal which specifies even or odd parity to be used, and uses the parity data as the select data, the ways (12, 13) have tag ways for storing the cache tag corresponding to the index address and data ways for storing data corresponding to the index address, the cache entry includes the cache tag and data corresponding thereto, the tag ways are constituted by memory blocks whose activation or inactivation is selected for each tag way respectively, and when reading cache tags, the cache memory activates the some tag ways according to the value of the select data by memory block activation by use of the select data and deactivates the other tag ways. the cache memory creates parity data in connection with tag address information which is part of the address information and an even-odd select signal which specifies even or odd parity to be used, and uses the parity data as the select data, the ways (12, 13) have tag ways for storing the cache tag corresponding to the index address and data ways for storing data corresponding to the index address, the cache entry includes the cache tag and data corresponding thereto, the tag ways are constituted by memory blocks whose activation or inactivation is selected for each tag way respectively, and when reading cache tags, the cache memory activates the some tag ways according to the value of the select data by memory block activation by use of the select data and deactivates the other tag ways.