An analog-to-digital converter, ADC, (300, 400, 600 or 700 in FIG. 3a, 4a, 6a or 7a) coupled to an input signal at a first node (n3a, n4a, n6a or n7a in FIG. 3a, 4a, 6a or 7a), and converting a sample (V[i] in FIG. 3b, 5b or 7b, or V[2*i] in FIG. 6b) of the input signal to a sample (D[i] in FIG. 3b, 5b or 7b, or D[2*i] in FIG. 6b) of an output signal during a cycle (T[i] in FIG. 3b/3c, 4b, 5b/5c, 6b or 7b/7c), wherein the ADC comprises: a capacitor array (Cs in FIG. 3a, 4a, 6a or 7a) coupled to a second node (n3b, n4b, n6b or n7b in FIG. 3a, 4a, 6a or 7a); an auxiliary capacitor (Cr in FIG. 3a, 4a, 6a or 7a) coupled to a third node (n3c, n4c, n6c or n7c in FIG. 3a, 4a, 6a or 7a); wherein the auxiliary capacitor is variable to selectively provide a first capacitance (1*C) and a different second capacitance (n*C); a first switch (ss3, ss4, ss6e or ss7 in FIG. 3a, 4a, 6a or 7a) coupled between the first node and the second node; and a second switch (sr3, sr4, sr6e or sr7 in FIG. 3a, 4a, 6a or 7a) coupled between the second node and the third node; and a comparator (320, 420, 520, 620e, 720) coupled to the second switch; wherein the cycle comprises a sampling phase (Ta[i] in FIG. 3b/3c, 4b, 5b/5c, 6b or 7b/7c), a combining phase (Tb[i] in FIG. 3b/3c, 4b or 7b/7c; or Tf[i] in FIG. 5b/5c or 6b) a comparison phase (Tc[i] in FIG. 3b/3c, 4b, 5b/5c, 6b or 7b/7c) and a first scaling phase (Td[i] in FIG. 3b/3c, 4b, 5b/5c, 6b or 7b/7c) after the comparison phase; during the sampling phase, the first switch is on to conduct the first node to the second node, and the second switch is off to stop conduction between the second node and the third node; during the combining phase, the first switch is off to stop conduction between the first node and the second node, and the second switch is on to conduct the third node to the second node, so a combined signal is formed at the second node; during the comparison phase, the first switch is off, the second switch is on, the auxiliary capacitor provides the first capacitance, the comparator is enabled to quantize the combined signal and provide the sample of the output signal, and the capacitor array receives a feedback of the output signal to form an error signal at the second node; and during the first scaling phase, the first switch is off, the second switch is on, and the auxiliary capacitor provides the second capacitance. a capacitor array (Cs in FIG. 3a, 4a, 6a or 7a) coupled to a second node (n3b, n4b, n6b or n7b in FIG. 3a, 4a, 6a or 7a); an auxiliary capacitor (Cr in FIG. 3a, 4a, 6a or 7a) coupled to a third node (n3c, n4c, n6c or n7c in FIG. 3a, 4a, 6a or 7a); wherein the auxiliary capacitor is variable to selectively provide a first capacitance (1*C) and a different second capacitance (n*C); a first switch (ss3, ss4, ss6e or ss7 in FIG. 3a, 4a, 6a or 7a) coupled between the first node and the second node; and a second switch (sr3, sr4, sr6e or sr7 in FIG. 3a, 4a, 6a or 7a) coupled between the second node and the third node; and a comparator (320, 420, 520, 620e, 720) coupled to the second switch; wherein the cycle comprises a sampling phase (Ta[i] in FIG. 3b/3c, 4b, 5b/5c, 6b or 7b/7c), a combining phase (Tb[i] in FIG. 3b/3c, 4b or 7b/7c; or Tf[i] in FIG. 5b/5c or 6b) a comparison phase (Tc[i] in FIG. 3b/3c, 4b, 5b/5c, 6b or 7b/7c) and a first scaling phase (Td[i] in FIG. 3b/3c, 4b, 5b/5c, 6b or 7b/7c) after the comparison phase; during the sampling phase, the first switch is on to conduct the first node to the second node, and the second switch is off to stop conduction between the second node and the third node; during the combining phase, the first switch is off to stop conduction between the first node and the second node, and the second switch is on to conduct the third node to the second node, so a combined signal is formed at the second node; during the comparison phase, the first switch is off, the second switch is on, the auxiliary capacitor provides the first capacitance, the comparator is enabled to quantize the combined signal and provide the sample of the output signal, and the capacitor array receives a feedback of the output signal to form an error signal at the second node; and during the first scaling phase, the first switch is off, the second switch is on, and the auxiliary capacitor provides the second capacitance.