A memory cell (100, 211, 259) comprising: a semiconductor substrate (104, 207, 257, 300) having a surface with a source region and a drain region in the substrate and separated by a channel region; trench isolation structures (312, 313) extending into the semiconductor substrate, wherein the channel region has an active area with a length between the source region and the drain region, and a width orthogonal to the length, the width of the channel region defined by a spacing between the trench isolation structures (312, 313); a multilayer stack over the channel between the trench isolation structures (312, 313) including a tunneling barrier dielectric structure (105, 200, 250, 301) with an effective oxide thickness of greater than 3 nanometers disposed on the surface of the substrate above the channel region, a conductive field distribution layer (101, 204, 251, 302) disposed above the tunneling barrier dielectric structure and above the channel region, a charge trapping structure (106, 205, 303) disposed above the conductive field distribution layer, and a top dielectric structure (107, 206, 254, 304) disposed above the charge trapping structure and above the channel region, wherein the charge trapping structure (106, 205, 303) is a dielectric charge trapping structure, the charge trapping structure (106, 205, 303) is disposed above the conductive field distribution layer and above the channel region, and the width of the channel region is less than 45nm; a top conductive layer (108, 208, 258, 305) disposed above the top dielectric structure and above the channel region; and a word line disposed above the top conductive layer, characterized in that a top of the multilayer stack is lower than a top of the trench isolation structures (312, 313), and the areas of the top and bottom surfaces of the conductive field distribution layer are the product of a width of the word line and a spacing between the trench isolation structures (312, 313). a semiconductor substrate (104, 207, 257, 300) having a surface with a source region and a drain region in the substrate and separated by a channel region; trench isolation structures (312, 313) extending into the semiconductor substrate, wherein the channel region has an active area with a length between the source region and the drain region, and a width orthogonal to the length, the width of the channel region defined by a spacing between the trench isolation structures (312, 313); a multilayer stack over the channel between the trench isolation structures (312, 313) including a tunneling barrier dielectric structure (105, 200, 250, 301) with an effective oxide thickness of greater than 3 nanometers disposed on the surface of the substrate above the channel region, a conductive field distribution layer (101, 204, 251, 302) disposed above the tunneling barrier dielectric structure and above the channel region, a charge trapping structure (106, 205, 303) disposed above the conductive field distribution layer, and a top dielectric structure (107, 206, 254, 304) disposed above the charge trapping structure and above the channel region, wherein the charge trapping structure (106, 205, 303) is a dielectric charge trapping structure, the charge trapping structure (106, 205, 303) is disposed above the conductive field distribution layer and above the channel region, and the width of the channel region is less than 45nm; a top conductive layer (108, 208, 258, 305) disposed above the top dielectric structure and above the channel region; and a word line disposed above the top conductive layer,