A semiconductor device comprising: an array of resistive non-volatile memory cells; a reference voltage generation circuit including: a first set of reference resistive memory cells (58, 60, 62, 64, 66, 68) coupled to a first bit line (BLR 0), a second set of reference resistive memory cells (38, 40, 42, 44, 46, 48) coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line (BLRO), and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier, wherein the output of the amplifier is a reference voltage (Vr), and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage; and sense amplifier circuitry configured to use the reference voltage to read data stored in the array of memory cells; characterized in that the semiconductor device further comprises: a first switch having a first current electrode coupled to the first node and a second current electrode coupled to the first input to the amplifier; a second switch having a first current electrode coupled to the output of the amplifier and a second current electrode coupled to the first terminal of the third capacitor; and a third switch having a first current electrode coupled between the first terminal of the third capacitor and the second current electrode of the second switch, and a second current electrode coupled between the first input to the amplifier and the second current electrode of the first switch, wherein the reference voltage is tapped between the output of the amplifier and the first current electrode of the second switch. an array of resistive non-volatile memory cells; a reference voltage generation circuit including: a first set of reference resistive memory cells (58, 60, 62, 64, 66, 68) coupled to a first bit line (BLR 0), a second set of reference resistive memory cells (38, 40, 42, 44, 46, 48) coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line (BLRO), and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier, wherein the output of the amplifier is a reference voltage (Vr), and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage; and a first set of reference resistive memory cells (58, 60, 62, 64, 66, 68) coupled to a first bit line (BLR 0), a second set of reference resistive memory cells (38, 40, 42, 44, 46, 48) coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line (BLRO), and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier, wherein the output of the amplifier is a reference voltage (Vr), and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage; and sense amplifier circuitry configured to use the reference voltage to read data stored in the array of memory cells; characterized in that the semiconductor device further comprises: a first switch having a first current electrode coupled to the first node and a second current electrode coupled to the first input to the amplifier; a second switch having a first current electrode coupled to the output of the amplifier and a second current electrode coupled to the first terminal of the third capacitor; and a third switch having a first current electrode coupled between the first terminal of the third capacitor and the second current electrode of the second switch, and a second current electrode coupled between the first input to the amplifier and the second current electrode of the first switch, wherein the reference voltage is tapped between the output of the amplifier and the first current electrode of the second switch. a first switch having a first current electrode coupled to the first node and a second current electrode coupled to the first input to the amplifier; a second switch having a first current electrode coupled to the output of the amplifier and a second current electrode coupled to the first terminal of the third capacitor; and a third switch having a first current electrode coupled between the first terminal of the third capacitor and the second current electrode of the second switch, and a second current electrode coupled between the first input to the amplifier and the second current electrode of the first switch, wherein the reference voltage is tapped between the output of the amplifier and the first current electrode of the second switch.