A core (300, 400, 500) of neural processing units, NPUs, comprising: an NxN array of NPUs arranged in N rows and N columns in which N is an integer greater than equal to 2, each NPU comprising a memory, and a convolutional multiply-accumulate, MAC, circuit coupled to the memory, the memory configured to receive, store, and output input feature map, IFM, values, kernel values and output feature map, OFM, values, the NxN array of NPUs being configured to process IFM data by: storing IFM values of an array of IFM values so that each respective row of IFM values of the array of IFM values is sequentially stored in the respective memory of NPUs located along diagonals of the NxN array of NPUs; broadcasting an IFM value stored in the memory in each NPUs located in a current diagonal to memory of other NPUs located in a same row as the NPU; for each row of the NxN array of NPUs, multiplying an IFM value broadcast to the memory of an NPU in the row by a kernel value stored in the memory of each respective NPU in the row to form a product value PV for the NPU; for each column of the NxN array of NPUs, adding all product values PV in a column to form an OFM value for the column; storing each respective OFM value in the memory in a NPU located in the current diagonal; and repeating broadcasting, multiplying, adding and storing until all diagonals of the NxN array of NPUs have been processed, wherein the N rows comprise rows r i -r N, the N columns comprise columns c j -c N and the N diagonals comprise diagonals d k -d N, in which i is an integer value between 1 and N inclusive, j is an integer value between 1 and N inclusive and k is an integer value between 1 and N inclusive, and wherein each diagonal comprises N NPUs, and an k th diagonal d k extends in a direction from an j th NPU in row r i toward an NPU in a row r i+1 and in a column Cj+1 and wraps to a NPU in row r N-i. an NxN array of NPUs arranged in N rows and N columns in which N is an integer greater than equal to 2, each NPU comprising a memory, and a convolutional multiply-accumulate, MAC, circuit coupled to the memory, the memory configured to receive, store, and output input feature map, IFM, values, kernel values and output feature map, OFM, values, the NxN array of NPUs being configured to process IFM data by: storing IFM values of an array of IFM values so that each respective row of IFM values of the array of IFM values is sequentially stored in the respective memory of NPUs located along diagonals of the NxN array of NPUs; broadcasting an IFM value stored in the memory in each NPUs located in a current diagonal to memory of other NPUs located in a same row as the NPU; for each row of the NxN array of NPUs, multiplying an IFM value broadcast to the memory of an NPU in the row by a kernel value stored in the memory of each respective NPU in the row to form a product value PV for the NPU; for each column of the NxN array of NPUs, adding all product values PV in a column to form an OFM value for the column; storing each respective OFM value in the memory in a NPU located in the current diagonal; and repeating broadcasting, multiplying, adding and storing until all diagonals of the NxN array of NPUs have been processed, storing IFM values of an array of IFM values so that each respective row of IFM values of the array of IFM values is sequentially stored in the respective memory of NPUs located along diagonals of the NxN array of NPUs; broadcasting an IFM value stored in the memory in each NPUs located in a current diagonal to memory of other NPUs located in a same row as the NPU; for each row of the NxN array of NPUs, multiplying an IFM value broadcast to the memory of an NPU in the row by a kernel value stored in the memory of each respective NPU in the row to form a product value PV for the NPU; for each column of the NxN array of NPUs, adding all product values PV in a column to form an OFM value for the column; storing each respective OFM value in the memory in a NPU located in the current diagonal; and repeating broadcasting, multiplying, adding and storing until all diagonals of the NxN array of NPUs have been processed, wherein the N rows comprise rows r i -r N, the N columns comprise columns c j -c N and the N diagonals comprise diagonals d k -d N, in which i is an integer value between 1 and N inclusive, j is an integer value between 1 and N inclusive and k is an integer value between 1 and N inclusive, and wherein each diagonal comprises N NPUs, and an k th diagonal d k extends in a direction from an j th NPU in row r i toward an NPU in a row r i+1 and in a column Cj+1 and wraps to a NPU in row r N-i.