A circuit generating at least four control signals to control a demultiplexer (Demux) for a display having the demultiplexer, the circuit comprising: an integrated circuit unit configured to output three pulse signals (V1, V2, V3) including a first pulse signal, a second pulse signal, and a third pulse signal; and a logic unit electrically connected to the integrated circuit unit and configured to transform the three pulse signals (V1, V2, V3) having different digital waveforms into said at least four control signals (CKR, CKG, CKB, CKW), characterized in that the logic unit comprises NAND gate components and buffer components electrically connected to the NAND gate components; the integrated circuit unit provides the three pulse signals (V1, V2, V3) to the NAND gate components, wherein the NAND gate components comprise four 3-input NAND gates combined and connected to each other, the buffer components comprises four buffers designed to respectively supply said four control signals, and the four buffers and the four 3-input NAND gates are electrically connected to each other in a one-to-one correspondence; the four 3-input NAND gates respectively are a first 3-input NAND gate, a second 3-input NAND gate, a third 3-input NAND gate, and a fourth 3-input NAND gate; the four buffers respectively are a first buffer, a second buffer, a third buffer, and a fourth buffer, wherein a first input terminal of the first 3-input NAND gate is electrically connected to a second input terminal of the second 3-input NAND gate and the second input terminal of the third 3-inputs NAND gate; the second input terminal of the first 3-input NAND gate is electrically connected to a third input terminal of the second 3-input NAND gate and the second input terminal of the fourth 3-input NAND gate; the third input terminal of the first 3-input NAND gate is electrically connected to the third input terminal of the third 3-input NAND gate and the third input terminal of the fourth 3-input NAND gate; an output terminal of the first 3-input NAND gate is electrically connected to the first input terminal of the second 3-input NAND gate, the first input terminal of the third 3-input NAND gate, the first input terminal of the fourth 3-input NAND gate, and an input terminal of the first buffer; the output terminal of the second 3-input NAND gate is electrically connected to the input terminal of the second buffer; the output terminal of the third 3-input NAND gate is electrically connected to the input terminal of the third buffer; the output terminal of the fourth 3-input NAND gate is electrically connected to the input terminal of the fourth buffer; the first pulse signal, the second pulse signal, and the third pulse signal are respectively inputted to the first input terminal, the second input terminal, and the third input terminal of the first 3-input NAND gate, and wherein each buffer comprises a first inverter set and the first inverter set comprises three inverters connected in series. characterized in that the logic unit comprises NAND gate components and buffer components electrically connected to the NAND gate components; the integrated circuit unit provides the three pulse signals (V1, V2, V3) to the NAND gate components, wherein the NAND gate components comprise four 3-input NAND gates combined and connected to each other, the buffer components comprises four buffers designed to respectively supply said four control signals, and the four buffers and the four 3-input NAND gates are electrically connected to each other in a one-to-one correspondence; the four 3-input NAND gates respectively are a first 3-input NAND gate, a second 3-input NAND gate, a third 3-input NAND gate, and a fourth 3-input NAND gate; the four buffers respectively are a first buffer, a second buffer, a third buffer, and a fourth buffer, wherein a first input terminal of the first 3-input NAND gate is electrically connected to a second input terminal of the second 3-input NAND gate and the second input terminal of the third 3-inputs NAND gate; the second input terminal of the first 3-input NAND gate is electrically connected to a third input terminal of the second 3-input NAND gate and the second input terminal of the fourth 3-input NAND gate; the third input terminal of the first 3-input NAND gate is electrically connected to the third input terminal of the third 3-input NAND gate and the third input terminal of the fourth 3-input NAND gate; an output terminal of the first 3-input NAND gate is electrically connected to the first input terminal of the second 3-input NAND gate, the first input terminal of the third 3-input NAND gate, the first input terminal of the fourth 3-input NAND gate, and an input terminal of the first buffer; the output terminal of the second 3-input NAND gate is electrically connected to the input terminal of the second buffer; the output terminal of the third 3-input NAND gate is electrically connected to the input terminal of the third buffer; the output terminal of the fourth 3-input NAND gate is electrically connected to the input terminal of the fourth buffer; the first pulse signal, the second pulse signal, and the third pulse signal are respectively inputted to the first input terminal, the second input terminal, and the third input terminal of the first 3-input NAND gate, and wherein each buffer comprises a first inverter set and the first inverter set comprises three inverters connected in series.