An apparatus comprising: an instruction decoder to decode instructions; and processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder; in which: in response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder is configured to control the processing circuitry to perform a processing operation on at least one input data structure identified by the at least one input data structure identifier to generate an output data structure identified by the output data structure identifier; the at least one input data structure and the output data structure each comprise an arrangement of data corresponding to a plurality of memory addresses; and the apparatus comprises a plurality of sets of one or more data structure metadata registers, each set of one or more data structure metadata registers associated with a corresponding data structure identifier; characterised in that: each set of one or more data structure metadata registers is designated to hold address-indicating metadata for identifying the plurality of memory addresses for the data structure identified by the corresponding data structure identifier; and the processing circuitry is configured to operate according to an instruction set architecture which enables software to identify, for at least a subset of data structure identifiers, whether a data structure corresponding to one of the subset of data structure identifiers is clean or dirty. an instruction decoder to decode instructions; and processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder; in which: in response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder is configured to control the processing circuitry to perform a processing operation on at least one input data structure identified by the at least one input data structure identifier to generate an output data structure identified by the output data structure identifier; the at least one input data structure and the output data structure each comprise an arrangement of data corresponding to a plurality of memory addresses; and the apparatus comprises a plurality of sets of one or more data structure metadata registers, each set of one or more data structure metadata registers associated with a corresponding data structure identifier; in response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder is configured to control the processing circuitry to perform a processing operation on at least one input data structure identified by the at least one input data structure identifier to generate an output data structure identified by the output data structure identifier; the at least one input data structure and the output data structure each comprise an arrangement of data corresponding to a plurality of memory addresses; and the apparatus comprises a plurality of sets of one or more data structure metadata registers, each set of one or more data structure metadata registers associated with a corresponding data structure identifier; characterised in that: each set of one or more data structure metadata registers is designated to hold address-indicating metadata for identifying the plurality of memory addresses for the data structure identified by the corresponding data structure identifier; and the processing circuitry is configured to operate according to an instruction set architecture which enables software to identify, for at least a subset of data structure identifiers, whether a data structure corresponding to one of the subset of data structure identifiers is clean or dirty. each set of one or more data structure metadata registers is designated to hold address-indicating metadata for identifying the plurality of memory addresses for the data structure identified by the corresponding data structure identifier; and the processing circuitry is configured to operate according to an instruction set architecture which enables software to identify, for at least a subset of data structure identifiers, whether a data structure corresponding to one of the subset of data structure identifiers is clean or dirty.