A sense amplifier for sensing a state of a resistive memory bitcell, comprising: a differential sense input, the differential sense input configured to be coupled to a bit line of a resistive memory bitcell; a differential reference input, the differential reference input configured to be coupled to a reference line; a first inverter configured to invert a first inverter input into a first inverter output coupled to a second inverter input of a second inverter, the first inverter output configured to provide a sensed state of the resistive memory bitcell; the second inverter configured to invert the second inverter input into a second inverter output coupled to the first inverter input; and a control circuit configured to: couple the differential reference input to the first inverter and the differential sense input to the second inverter in a latch mode of the resistive memory bitcell; decouple the differential reference input to the first inverter and the differential sense input to the second inverter in a sensing mode of the resistive memory bitcell to provide the sensed state of the resistive memory bitcell on the first inverter output; and decouple the first inverter from a high voltage source and a low voltage source, and decouple the second inverter from the high voltage source and the low voltage source prior to coupling the differential reference input to the first inverter and the differential sense input to the second inverter in the latch mode of the resistive memory bitcell. a differential sense input, the differential sense input configured to be coupled to a bit line of a resistive memory bitcell; a differential reference input, the differential reference input configured to be coupled to a reference line; a first inverter configured to invert a first inverter input into a first inverter output coupled to a second inverter input of a second inverter, the first inverter output configured to provide a sensed state of the resistive memory bitcell; the second inverter configured to invert the second inverter input into a second inverter output coupled to the first inverter input; and a control circuit configured to: couple the differential reference input to the first inverter and the differential sense input to the second inverter in a latch mode of the resistive memory bitcell; decouple the differential reference input to the first inverter and the differential sense input to the second inverter in a sensing mode of the resistive memory bitcell to provide the sensed state of the resistive memory bitcell on the first inverter output; and decouple the first inverter from a high voltage source and a low voltage source, and decouple the second inverter from the high voltage source and the low voltage source prior to coupling the differential reference input to the first inverter and the differential sense input to the second inverter in the latch mode of the resistive memory bitcell. couple the differential reference input to the first inverter and the differential sense input to the second inverter in a latch mode of the resistive memory bitcell; decouple the differential reference input to the first inverter and the differential sense input to the second inverter in a sensing mode of the resistive memory bitcell to provide the sensed state of the resistive memory bitcell on the first inverter output; and decouple the first inverter from a high voltage source and a low voltage source, and decouple the second inverter from the high voltage source and the low voltage source prior to coupling the differential reference input to the first inverter and the differential sense input to the second inverter in the latch mode of the resistive memory bitcell.