A microcontroller comprising: a data memory divided into a plurality of memory banks (000...111), wherein said data memory comprises a first set of memory banks (000...011) and a second set of memory banks (100... 111) of said plurality of memory banks (000...111); an address multiplexer for providing an address to said data memory; an instruction register providing a first partial address to a first input of said address multiplexer; a bank select register for providing a second partial address to a said first input of said address multiplexer; and a plurality of special function registers mapped to said data memory, including an indirect memory address register coupled with a second input of said address multiplexer, wherein the bank select register is not mapped to said data memory, at least one special function register (INDF, TMR0, EECON, PCL, STATUS, FSR, OSCAL, EEDATA, PORTB, EEADR) is memory mapped to more than one memory bank of said first set of memory banks (000...011) under the same memory bank address and wherein the second set of memory banks (100..111) form a block of linear data memory to which no special function registers are mapped; wherein for direct addressing, a memory bank (000...111) is selected by said bank select register and said selected memory bank is addressed through said multiplexer by an address formed by the first partial address from said instruction register and the second partial address from said bank select register; and wherein for indirect addressing, said data memory is addressed indirectly by selecting an address provided by said indirect memory address register thereby allowing access to at least the entire linear memory block formed by said second set of memory banks (100...111). a data memory divided into a plurality of memory banks (000...111), wherein said data memory comprises a first set of memory banks (000...011) and a second set of memory banks (100... 111) of said plurality of memory banks (000...111); an address multiplexer for providing an address to said data memory; an instruction register providing a first partial address to a first input of said address multiplexer; a bank select register for providing a second partial address to a said first input of said address multiplexer; and a plurality of special function registers mapped to said data memory, including an indirect memory address register coupled with a second input of said address multiplexer, wherein the bank select register is not mapped to said data memory, at least one special function register (INDF, TMR0, EECON, PCL, STATUS, FSR, OSCAL, EEDATA, PORTB, EEADR) is memory mapped to more than one memory bank of said first set of memory banks (000...011) under the same memory bank address and wherein the second set of memory banks (100..111) form a block of linear data memory to which no special function registers are mapped; wherein for direct addressing, a memory bank (000...111) is selected by said bank select register and said selected memory bank is addressed through said multiplexer by an address formed by the first partial address from said instruction register and the second partial address from said bank select register; and wherein for indirect addressing, said data memory is addressed indirectly by selecting an address provided by said indirect memory address register thereby allowing access to at least the entire linear memory block formed by said second set of memory banks (100...111).