A multiple output comparator configured to compare a first input voltage signal with a second input voltage signal and at least one apparent threshold offset level comprising: a difference circuit configured to receive the first input voltage signal and the second input voltage signal and configured for determining when a magnitude of the first input voltage signal is greater than or lesser than the second input voltage signal and configured to provide a true output current signal and a complement output current signal that are indicative that magnitude of the first input voltage signal is greater than or lesser than the second input voltage signal; wherein: an output current mirror driver circuit in communication with the difference circuit for receiving the true output current signal and the complement output current signal comprising: - a first current mirror circuit configured for receiving the true output current signal from the difference circuit and configured for generating at least one mirrored true output current signal (MS IP1,..., MS IPn) indicating that the first input voltage signal is greater than or less than the second input voltage signal; - a second current mirror circuit configured for receiving the complementary output current signal from the difference circuit configured for generating at least one mirrored complement output current signal (MS OP1,..., MS OPn) based on the received complementary output current signal and a corresponding threshold offset current level (42a,..., 42n), for indicating that the first input voltage signal is greater than or less than the second input voltage signal as offset by a corresponding apparent threshold offset level, wherein the at least one mirrored complement output current signal (MS OP1,..., MS OPn) is combined with an associated at least one mirrored true current signal (MRS IP1,..., MRS IPn) to form a plurality of digital output voltage signals (OUT1,..., OUTn); and - at least one offset generator (40a,..., 40n) in communication with the second mirror circuit and configured for accurately generating a threshold offset current level (42a,..., 42n) for each corresponding apparent threshold offset level. a difference circuit configured to receive the first input voltage signal and the second input voltage signal and configured for determining when a magnitude of the first input voltage signal is greater than or lesser than the second input voltage signal and configured to provide a true output current signal and a complement output current signal that are indicative that magnitude of the first input voltage signal is greater than or lesser than the second input voltage signal; wherein: an output current mirror driver circuit in communication with the difference circuit for receiving the true output current signal and the complement output current signal comprising: - a first current mirror circuit configured for receiving the true output current signal from the difference circuit and configured for generating at least one mirrored true output current signal (MS IP1,..., MS IPn) indicating that the first input voltage signal is greater than or less than the second input voltage signal; - a second current mirror circuit configured for receiving the complementary output current signal from the difference circuit configured for generating at least one mirrored complement output current signal (MS OP1,..., MS OPn) based on the received complementary output current signal and a corresponding threshold offset current level (42a,..., 42n), for indicating that the first input voltage signal is greater than or less than the second input voltage signal as offset by a corresponding apparent threshold offset level, wherein the at least one mirrored complement output current signal (MS OP1,..., MS OPn) is combined with an associated at least one mirrored true current signal (MRS IP1,..., MRS IPn) to form a plurality of digital output voltage signals (OUT1,..., OUTn); and - at least one offset generator (40a,..., 40n) in communication with the second mirror circuit and configured for accurately generating a threshold offset current level (42a,..., 42n) for each corresponding apparent threshold offset level. - a first current mirror circuit configured for receiving the true output current signal from the difference circuit and configured for generating at least one mirrored true output current signal (MS IP1,..., MS IPn) indicating that the first input voltage signal is greater than or less than the second input voltage signal; - a second current mirror circuit configured for receiving the complementary output current signal from the difference circuit configured for generating at least one mirrored complement output current signal (MS OP1,..., MS OPn) based on the received complementary output current signal and a corresponding threshold offset current level (42a,..., 42n), for indicating that the first input voltage signal is greater than or less than the second input voltage signal as offset by a corresponding apparent threshold offset level, wherein the at least one mirrored complement output current signal (MS OP1,..., MS OPn) is combined with an associated at least one mirrored true current signal (MRS IP1,..., MRS IPn) to form a plurality of digital output voltage signals (OUT1,..., OUTn); and - at least one offset generator (40a,..., 40n) in communication with the second mirror circuit and configured for accurately generating a threshold offset current level (42a,..., 42n) for each corresponding apparent threshold offset level.