A digital unit, DU, of a base station, configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access, OFDMA, the DU comprising: a clock controller (212; 412): and a data processor (210; 410); wherein the clock controller (212; 412) is configured to: monitor whether an IQ data signal, IQ_data, is allocated to an input signal to the data processor, wherein IQ data signal is an inphase/quadrature, IQ, modulated signal comprising data related to control information and reference signals, wherein the IQ data signal may further comprise data related to user traffic; and control a frequency of a clock signal and provide this to the data processor depending on whether an IQ data signal is allocated to the input signal; wherein the clock signal is controlled: to have a first frequency when an IQ data signal is allocated to the input signal; to have a second frequency when an IQ data signal is not allocated to the input signal; wherein the first frequency is greater than the second frequency; wherein the data processor is further configured to process the input signal synchronizing with the clock signal and transfer the processed signal to a radio unit, RU, of the base station, the device further comprising a buffer configured to delay the IQ data signal by a delay time, Tw, corresponding to a time required for stabilization of the clock signal, and outputting the delayed IQ data signal to the data processor such that the data processor can process the IQ data signal after stabilization of the clock signal controlled by the clock controller and provided to the data processor. a clock controller (212; 412): and a data processor (210; 410); wherein the clock controller (212; 412) is configured to: monitor whether an IQ data signal, IQ_data, is allocated to an input signal to the data processor, wherein IQ data signal is an inphase/quadrature, IQ, modulated signal comprising data related to control information and reference signals, wherein the IQ data signal may further comprise data related to user traffic; and control a frequency of a clock signal and provide this to the data processor depending on whether an IQ data signal is allocated to the input signal; wherein the clock signal is controlled: to have a first frequency when an IQ data signal is allocated to the input signal; to have a second frequency when an IQ data signal is not allocated to the input signal; wherein the first frequency is greater than the second frequency; monitor whether an IQ data signal, IQ_data, is allocated to an input signal to the data processor, wherein IQ data signal is an inphase/quadrature, IQ, modulated signal comprising data related to control information and reference signals, wherein the IQ data signal may further comprise data related to user traffic; and control a frequency of a clock signal and provide this to the data processor depending on whether an IQ data signal is allocated to the input signal; wherein the clock signal is controlled: to have a first frequency when an IQ data signal is allocated to the input signal; to have a second frequency when an IQ data signal is not allocated to the input signal; wherein the first frequency is greater than the second frequency; to have a first frequency when an IQ data signal is allocated to the input signal; to have a second frequency when an IQ data signal is not allocated to the input signal; wherein the first frequency is greater than the second frequency; wherein the data processor is further configured to process the input signal synchronizing with the clock signal and transfer the processed signal to a radio unit, RU, of the base station, the device further comprising a buffer configured to delay the IQ data signal by a delay time, Tw, corresponding to a time required for stabilization of the clock signal, and outputting the delayed IQ data signal to the data processor such that the data processor can process the IQ data signal after stabilization of the clock signal controlled by the clock controller and provided to the data processor.