質問: windows 10 64ビット要件:cpuはcmpxchg16b、prefetchw、lahf / sahfをサポートしていますか? 私は現在、日付が少し古いノートブック(windows 7、64ビット)をwindows 10に更新するのが良いアイデアかどうかを調べています。問題は、microsoftが windows 10の仕様で述べていることです) 64ビット版のwindows 10を使用するには、cmpxchg16b、prefetchw、lahf/sahfをサポートするプロセッサが必要です。私のプロセッサが64ビット(intel core i5-2430m @ 2.40 ghz)であることはわかっていますが、cmpxchg16b、prefetchw、lahf/sahfをサポートしているかどうかを確認する方法がわかりません。これらの意味がわかりません。私はgoogleを使ってみましたが、私にとって意味のある結果は得られませんでした。私のi5と同様のamdプロセッサの比較だけです。 intelのark webサイトもチェックしました。誰かが私にもっと情報を得ることができる場所を教えてもらえたら、本当に感謝しています。
回答: linuxでcat /proc/cpuinfoのような機能を提供する、microsoft提供の coreinfo というユーティリティがあります。これを検索する必要がありますが、ここで情報を見つけることができます。lahf-sahf - supports lahf/sahf instructions in 64-bit mode nx - supports no-execute page protection cx16 * supports cmpxchg16b instruction x64 * supports 64-bit mode prefetchw - supports prefetchw instruction -はcpuにその機能がないことを意味し、*はcpuにその機能があることを意味します。私が見たところで、 coreinfoは実際にはそのドキュメントページで決定するためにmicrosoftから提案されています coreinfo は、cpuがこれらの機能のどれを持っているかを確認するために使用できるツールです。+ 私のプロセッサ、intel e7525の完全な結果は次のようになります。coreinfo v3.31 - dump information on system cpu and memory topology copyright (c) 2008-2014 mark russinovich sysinternals - www.sysinternals.com intel(r) xeon(tm) cpu 3.40ghz x86 family 15 model 4 stepping 3, genuineintel microcode signature: 00000005 htt * hyperthreading enabled hypervisor - hypervisor is present vmx - supports intel hardware-assisted virtualization svm - supports amd hardware-assisted virtualization x64 * supports 64-bit mode smx - supports intel trusted execution skinit - supports amd skinit nx - supports no-execute page protection smep - supports supervisor mode execution prevention smap - supports supervisor mode access prevention page1gb - supports 1 gb large pages pae * supports > 32-bit physical addresses pat * supports page attribute table pse * supports 4 mb pages pse36 * supports > 32-bit address 4 mb pages pge * supports global bit in page tables ss * supports bus snooping for cache operations vme * supports virtual-8086 mode rdwrfsgsbase - supports direct gs/fs base access fpu * implements i387 floating point instructions mmx * supports mmx instruction set mmxext - implements amd mmx extensions 3dnow - supports 3dnow! instructions 3dnowext - supports 3dnow! extension instructions sse * supports streaming simd extensions sse2 * supports streaming simd extensions 2 sse3 * supports streaming simd extensions 3 ssse3 - supports supplemental simd extensions 3 sse4a - supports streaming simdr extensions 4a sse4.1 - supports streaming simd extensions 4.1 sse4.2 - supports streaming simd extensions 4.2 aes - supports aes extensions avx - supports avx intruction extensions fma - supports fma extensions using ymm state msr * implements rdmsr/wrmsr instructions mtrr * supports memory type range registers xsave - supports xsave/xrstor instructions osxsave - supports xsetbv/xgetbv instructions rdrand - supports rdrand instruction rdseed - supports rdseed instruction cmov * supports cmovcc instruction clfsh * supports clflush instruction cx8 * supports compare and exchange 8-byte instructions cx16 * supports cmpxchg16b instruction bmi1 - supports bit manipulation extensions 1 bmi2 - supports bit manipulation extensions 2 adx - supports adcx/adox instructions dca - supports prefetch from memory-mapped device f16c - supports half-precision instruction fxsr * supports fxsave/fxstor instructions ffxsr - supports optimized fxsave/fsrstor instruction monitor * supports monitor and mwait instructions movbe - supports movbe instruction ermsb - supports enhanced rep movsb/stosb pclmuldq - supports pclmuldq instruction popcnt - supports popcnt instruction lzcnt - supports lzcnt instruction sep * supports fast system call instructions lahf-sahf - supports lahf/sahf instructions in 64-bit mode hle - supports hardware lock elision instructions rtm - supports restricted transactional memory instructions de * supports i/o breakpoints including cr4.de dtes64 * can write history of 64-bit branch addresses ds * implements memory-resident debug buffer ds-cpl * supports debug store feature with cpl pcid - supports pcids and settable cr4.pcide invpcid - supports invpcid instruction pdcm - supports performance capabilities msr rdtscp - supports rdtscp instruction tsc * supports rdtsc instruction tsc-deadline - local apic supports one-shot deadline timer tsc-invariant - tsc runs at constant rate xtpr * supports disabling task priority messages eist * supports enhanced intel speedstep acpi * implements msr for power management tm * implements thermal monitor circuitry tm2 - implements thermal monitor 2 control apic * implements software-accessible local apic x2apic - supports x2apic cnxt-id * l1 data cache mode adaptive or bios mce * supports machine check, int18 and cr4.mce mca * implements machine check architecture pbe * supports use of ferr#/pbe# pin psn - implements 96-bit processor serial number prefetchw - supports prefetchw instruction maximum implemented cpuid leaves: 00000005 (basic), 80000008 (extended). logical to physical processor map: *- physical processor 0 -* physical processor 1 logical processor to socket map: logical processor to numa node map: ** numa node 0 logical processor to cache map: