Math - Hundreds Place
The students have been doing an excellent job of adding 3 digit numbers. This week we will begin subtracting 3 digit numbers. They have the addition and subtraction skills to do the homework this week, but maybe not the planning and organizational skills to set up the problems. This may be a family homework activity!
Science Lab Fridays
I hope by now you have been hearing about the fun labs we are doing each Friday. The students are getting some hands on experience with physics and matter. In second grade this week we will be learning more about different types of matter. The big takeaways for the students should include; stuff is made of other stuff, matter can take different forms, matter is constantly rearranging to make new substances.
The students are also doing various physics experiments. In third grade students will learn more about how everything works. Our big second grade goal is to start to understand forces and inertia. Though they may not be able to articulate their understanding, they should internalize the principles.
Homework this week is just one math page and spelling. The math page might be tough. The students have all of the computation skills they will need, but not the setup and planning skills for some problems. This might be a family assignment.
We have two upcoming field trips. On April 22 (Earth Day) we are going to Chico to watch the new Disney Nature Movie - Monkey Kingdom.
I am also working to schedule a field trip to go on a Geology Hike in Upper Bidwell Park through Chico Creek Nature Center. I will let you know as soon as this is scheduled.
Thanks to everyone who came out to PLP's and the Auction last week. This is what makes our school so special. There are lots of people investing in your children and that is awesome.
I am going to Shady Creek with the Sixth Graders as the Principal Monday through Wednesday. Mrs. Wright will be doing her famous volcano unit for geology. We are starting to work with adding and subtracting 3 digit numbers now in math. The students should do great! If you have any questions please contact Jessica. I will be back Thursday.
Homework this week is a packet due Friday. It contains spelling and math homework. 20 minutes of Moby Max can be substituted for any math homework page. Just write Moby Max on the top and sign it and your child will get credit.
In addition to Geology we are doing a science lab series each Friday with 3rd grade. Ask your child about it. They are doing 3 different science labs each Friday. It has been great so far (2 weeks).
We had so much fun during Read Across America Week with our reading teams competition that the students wanted to do it again. This is week two of a two week competition. Any quizzes taken before recess Friday will count in this competition. The prize is one item from the current Book Order which is going home today.


Summary: Coin-flipping games immune against linear-sized coalitions
Tel Aviv University
IBM Almaden Research Center
February 22, 2002
Perfect information coin-flipping and leader-election games arise naturally in the study of
fault tolerant distributed computing and have been considered in many different scenarios.
Answering a question of Ben-Or and Linial we prove that for every c < 1 there are such games
on n players in which no coalition of cn players can influence the outcome with probability
greater than some universal constant times c. (Note that we actually prove this statement only
for all c < 1/3, but since our universal constant is bigger than 3 the above is trivial for c 1/3.)
We show that a random protocol of a certain length has this property and give an explicit
construction as well.
Address: Eskenazy School of Mathematics, Sackler Faculty of Exact Sciences, Tel Aviv University, Tel Aviv,
Israel. e-mail: firstname.lastname@example.org. Most of this work was done while the author was visiting IBM Almaden Research


ECF estimation of Markov models where the transition density is unknown
In this paper, we consider the estimation of Markov models where the transition density is unknown. The approach we propose is based on the empirical characteristic function estimation procedure with an approximate optimal weight function. The approximate optimal weight function is obtained through an Edgeworth/Gram--Charlier expansion of the logarithmic transition density of the Markov process. We derive the estimating equations and demonstrate that they are similar to the approximate maximum likelihood estimation (AMLE). However, in contrast to the conventional AMLE our approach ensures the consistency of the estimator even with the approximate likelihood function. We illustrate our approach with examples of various Markov processes. Monte Carlo simulations are performed to investigate the finite sample properties of the proposed estimator in comparison with other methods. Copyright The Author(s). Journal compilation Royal Economic Society 2010.
If you experience problems downloading a file, check if you have the proper application to view it first. In case of further problems read the IDEAS help page. Note that these files are not on the IDEAS site. Please be patient as the files may be large.
As the access to this document is restricted, you may want to look for a different version under "Related research" (further below) or search for a different version of it.
Volume (Year): 13 (2010)
Issue (Month): 2 (07)
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This 54-piece teaching décor set reinforces problem-solving strategies and keywords to help students grasp essential math concepts. Enhance learning with curriculum-based bulletin board sets. These content-rich bulletin boards for classrooms allow you to utilize valuable wall space for presenting essential concepts without sacrificing an inviting atmosphere. Look for coordinating products to accent your displays and create a cohesive classroom theme!
The Problem Solving bulletin board set contains these pieces:
•2 strategy reference charts
•5 math symbols (3-piece division symbol)
•45 blank pieces to create keywords
|Classroom management||Reminders & Tips|


After increasing the number of employees by 15% company has 253 employees. How many employees take?
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A simply connected topological space is called elliptic if both π*(X, ℚ) and H*(X, ℚ) are finite-dimensional ℚ-vector spaces. In this paper, we consider fibrations for which the fibre X is elliptic and H*(X, ℚ) is evenly graded. We show that in the generic cases, the genus of such a fibration is completely determined by generalized Chern classes of the fibration.
|Number of pages||10|
|Journal||Proceedings of the American Mathematical Society|
|Publication status||Published - Feb 2004|
All Science Journal Classification (ASJC) codes
- Applied Mathematics


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Points, Angles, Lines (Basic Geometry)
points on the same line
congruent line segment
Line segments that have the same length
a location in space that has no size
a set of points that form a stright path extending in oppsite directions without end
figure formed by two rays with the same initial point
the pure mathematics of points and lines and curves and surfaces
are points that do not lie on the same line
points all in one plane
the act of intersecting (as joining by causing your path to intersect your target's path), a place where two or more points meet
midpoint of a segment
The point that divides a segment into two congruent segments.
points on the ends of line segments
two dimensional flat surface, extends forever.
contains at least 4 points not in one line
an angle between 90 and 180 degrees
an angle of 180 degrees
formed by rays
two rays with the same initial point that go in opposite directions
the point of intersection of lines or the point opposite the base of a figure
bisector of a segment
a line, segment, ray, or plane that intersects the segment at its midpoint
an angle less than 90 degrees but more than 0 degrees
Angles that have the same measure
the 90 degree angle between two perpendicular lines
angles are formed opposite of each other when two lines intersect
bisector of an angle
the ray that divides the angle into two congruent adjacent angles
two lines that meet and form a right angle
points that are not in the same plane
a part of a line with two endpoints
Two angles with a common side, a common vertex, and no common points within the angles
Two angles that add to 180º are called
if the sum of two angles is 90%
unit based to measure angles ( symbol )
Part of a line that has one endpoint and extends indefinitely in one direction.
A line that is perpendicular to a segment at its midpoint.
two angles in corresponding positions relative to two lines cut by a transversal
alternate exterior angles
Two nonadjacent exterior angles on opposite of the transversal.
same side-interior angles
interior angles on the same side of a transversal
The angle on the outside of a transversal.
noncoplanar lines that do not intersect
planes that don't intersect
is a line that intersects each of two other coplanar lines in different points
the angle inside of a transversal
alternate interior angles
two nonadjacent interior angles on opposite of the transversal
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In choropleth mapping, most classification schemes that have been proposed are based on the properties of the data's statistical distribution without regard for the data's spatial distribution. However, one of the more important tasks associated with choropleth map reading is the task of regionalization and identifying spatial patterns. For this reason some authors have proposed class interval selection procedures that also consider spatial contiguity. This book evaluates different classification schemes based on given data sets statistical as well as its spatial distribution. This book also involved with the choosing of suitable choropleth technique for given data set considering their accuracy level.


Word of the Day
Apps by Dictionary
A lot vs. Alot: 9 Grammatical Pitfalls
the theorem that a function is analytic in a simply connected domain if its integral is zero around every simple closed curve of finite length in the domain.
after Italian mathematician and physicist Giacinto
(1856-1909), who formulated it
Based on the Random House Dictionary, © Random House, Inc. 2015.
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To insure the adoration of a theorem for any length of time, faith is not enough, a police force is...
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Jessie B. Rittenhouse
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3-manifolds not obtained by surgery on a knot
A well-known theorem of Lickorish and Wallace states that any closed orientable 3-manifold can be obtained by surgery on a link in the 3-sphere. For a given 3-manifold one can ask how "simple" a link can be used to obtain it, e.g., whether a manifold satisfying certain obvious necessary conditions on its fundamental group always arises by surgery on a knot. This question turns out to be rather subtle, and progress has been limited, but in general the answer is known to be "no." Here Ill summarize some recent results including joint work with Matt Hedden, Min Hoon Kim, and Kyungbae Park that give the first examples of 3-manifolds with the homology of S^1 x S^2 and having fundamental group of weight 1 that do not arise by surgery on a knot in the 3-sphere.


The first player rolls 2 dice. They add the numbers to get a total. They can then cover any of numbers, with a token, that add up to the total, or the total number itself. Example: If a 3 and a 2 are rolled the player can cover the 3 and the 2, the 4 and the 1, or a 5. If the player can not cover the total rolled or a combination that adds up to that number, the roll returns to the other player. A time limit can be set for the game or the game can end when one player covers all of their numbers. This is a great game for practicing addition and play strategies.


Current Flow Closeness Maximization
Code for paper https://arxiv.org/abs/1802.02556
Julia version 0.6.0
Julia package Laplacians.jl which can be installed by
julia -e 'Pkg.add("Laplacians.jl")'
How to run
OPENBLAS_NUM_THREADS=1 julia -O3 test.jl data-dir algos k, where
data-diris the directory where the edges list files are. The algorithms will run on these files in lexicographical order of the file names. The result will be printed to both console and file
algosdenotes which algorithms to run.
exactmeans running exact greedy,
approxmeans running approx greedy, and
bothmeans running both greedy algorithms (default
kis an integer, denotes the number of vertices to chose (default
OPENBLAS_NUM_THREADS=1is to enforce the program to run on a single thread.
OPENBLAS_NUM_THREADS=1 julia -O3 test.jl data exact 5
means running the exact greedy on networks in directory
choosing 5 vertices for each network. The result will be printed to
both console and


JFundi - Educational Software
Library Home || Full Table of Contents || Library Help
|JFundi offers educational software. Their first product is Times Tables intended to help children memorize the multiplication tables. The Java software runs on multiple platforms.|
|Resource Types:||Educational Vendors, Instructional Packages/Games, Web Interactive/Java|
© 1994- The Math Forum at NCTM. All rights reserved.


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|Mean Return||0.27||Value At Risk||0.72|
|Potential Upside||1.56||Standard Deviation||1.22|
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In this paper, we develop an agent-based multi-layered interbank network model based on a sample of large EU banks. The model allows for taking a more holistic approach to interbank contagion than is standard in the literature. A key finding of the paper is that there are non-negligible non-linearities in the propagation of shocks to individual banks when taking into account that banks are related to each other in various market segments. In a nutshell, the contagion effects when considering the shock propagation simultaneously across multiple layers of interbank networks can be substantially larger than the sum of the contagion-induced losses when considering the network layers individually. In addition, a bank “systemic importance” measure based on the multi-layered network model is developed and is shown to outperform standard network centrality indicators.


For the Meetup of February we will again offer a brain challenging evening. Andrew Tweddle will challenge us with various approaches to tackling the sum of squares problem. With Steven Taschuck we will discuss a paper about a collaboration network that is derived from the Marvel Universe. In the two abstracts below we provide more information on these talks.
The sum of all squares, by Andrew Tweddle (http://andrewtweddle.blogspot.ca/).
Abstract: How many squares are there on a chessboard? Include squares of all sizes: 1 x 1, 2 x 2 up to 8 x 8.More generally, how many squares are there on an n by n grid expressed as a function of n? Solve this problem in as many different ways as you can.Andrew Tweddle will be presenting a variety of solutions - algebraic, combinatorial and visual. Feel free to bring your own solutions for discussion. Let's see if we can find a particularly elegant solution to this problem.If time permits, Andrew will also demonstrate iPython and SymPy for automating some of the algebra.
Marvel Universe looks almost like a real social network (paper by R. Alberich, J. Miro-Julia, F.Rossello), (http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.332.2051&rep=rep1&type=pdf) presented by Steven Taschuck (http://www.amotlpaa.org/)
Abstract: We investigate the structure of the Marvel Universe collaboration network, where two Marvel characters are considered linked if they jointly appear in the same Marvel comic book. We show that this network is clearly not a random network, and that it has most, but not all, characteristics of “real-life” collaboration networks, such as movie actors or scientific collaboration networks. The study of this artificial universe that tries to look like a real one, helps to understand that there are underlying principles that make real-life networks have definite characteristics.


Dr. Ana-Maria Croicu was the 2015 recipient of the KSU Foundation Distinguished Teaching Award. A native of Romania, she received a PhD in pure mathematics in 2001 from the Babes-Bolyai University of Cluj-Napoca. In 2005 she was awarded a second PhD in applied mathematics from Florida State University. Since 2006 she has taught mathematics at Kennesaw State University. She is also program director of a STEM scholarship program funded by a grant from the National Science Foundation.
Interview with Ana-Maria Croicu, 2015-10-02, Kennesaw State University oral history series, Kennesaw State University Oral History Project, 1973- , KSU/45/05/001, Kennesaw State University Archives.
The digital reproductions on this site are provided for research consultation and scholarly purposes only. To request permission to publish, reproduce, publicly display, broadcast, or distribute this material in any format outside of fair use please contact the Kennesaw State University Archives.


By Stephane Pirouet at December 21 2018 17:59:39
Once you have a scope and sequence book, make a list of each area in math that he needs to work on for the school year. For example for grades three and four, by the end of the year in subtraction, your child should be able to:
I recommend getting one of these books when you first begin homeschooling and use it as a reference throughout your homeschool journey. Regardless of how long you homeschool, you'll always have doubts and questions about how your child is performing.A scope and sequence book can put your mind at ease.
These students have weak immediacy. This means that compared to other students, they are slow to come up with the right answers to basic math problems like 6 x 8, or 35 divided by 7. While other kids have the answer stored in their memory, these kids do not. This causes big problems when they try to work through the more complex problems they encounter in junior high math.
From a teacher's perspective our competition is tough. Passing out a handout of 30 problems that are all in a format of 534x25= is not as stimulating in the students' eyes as playing games such as Grand Theft Auto and Resident Evil.
Save Time : Free worksheets not only save you money, they can also save you time. If you decide that it is best for your child to do worksheets especially tailored for his needs, by doing a little research for printable math worksheets found online, you don't have to make the worksheets yourself. This can save a lot of time. Worksheets aren't that difficult to make, but it can be time consuming.
math worksheets fraction
math worksheets addition
math worksheets multiplication


Joules to Megajoules Converter
Enter the energy in joules below to get the value converted to megajoules.
Do you want to convert megajoules to joules?
How to Convert Joules to Megajoules
To convert a measurement in joules to a measurement in megajoules, divide the energy by the following conversion ratio: 1,000,000 joules/megajoule.
Since one megajoule is equal to 1,000,000 joules, you can use this simple formula to convert:
megajoules = joules ÷ 1,000,000
The energy in megajoules is equal to the energy in joules divided by 1,000,000.
Joules and megajoules are both units used to measure energy. Keep reading to learn more about each unit of measure.
What Is a Joule?
The joule is the energy equal to the force on an object of one newton at a distance of one meter. One joule is equal to the heat energy dissipated by the current of one ampere through one ohm of resistance for one second.
The joule is the SI derived unit for energy in the metric system. Joules can be abbreviated as J; for example, 1 joule can be written as 1 J.
Learn more about joules.
What Is a Megajoule?
The megajoule is a multiple of the joule, which is the SI derived unit for energy. In the metric system, "mega" is the prefix for millions, or 106. Megajoules can be abbreviated as MJ; for example, 1 megajoule can be written as 1 MJ.
Learn more about megajoules.
Joule to Megajoule Conversion Table
|1 J||0.000001 MJ|
|2 J||0.000002 MJ|
|3 J||0.000003 MJ|
|4 J||0.000004 MJ|
|5 J||0.000005 MJ|
|6 J||0.000006 MJ|
|7 J||0.000007 MJ|
|8 J||0.000008 MJ|
|9 J||0.000009 MJ|
|10 J||0.00001 MJ|
|100 J||0.0001 MJ|
|1,000 J||0.001 MJ|
|10,000 J||0.01 MJ|
|100,000 J||0.1 MJ|
|1,000,000 J||1 MJ|
- International Bureau of Weights and Measures, The International System of Units, 9th Edition, 2019, https://www.bipm.org/documents/20126/41483022/SI-Brochure-9-EN.pdf


How Many Robots(Games categories: Robots, 1 Player, Flash, Kids, Quizz, Numbers, Baby, Android game, Free Game)
Description of How Many Robots game:
Game description: How many robots there are is a game for children, a math game but also an observation game. We must count the robots in front of us in an extraterestrial scenery.
Game controls: This game is played by mouse only.
80 / 108 persons voted like for How Many Robots!
|Add game to your web or blog!|


Determine the equation of the parabola that opens downward from (1,-3) and is congruent to y=2(x-4)2.
Do you mean this: y=2(x-4)^2
or this: y=2(x-4)+2
or something else?
I'll GUESS that it's this: y=2(x-4)^2
This suggests a parabola oppening up and vertex at (4,0).
A "congruent" parabola, then, with the other requirements, might be y=-2(x-1)^2 - 3
Really, it goes straight to the heart of understanding the form of the equation. There isn't anything magic or calculation-intensive about it.


Lots of opportunities are available to those with a bachelor's degree in mathematics. In some fields, such as biostatistics, finaincial mathematics, or operations research, a professional master's degree is preferred (or at least qualifies one for a higher salary). In research mathematics, a Ph.D. is required. Keep in mind: graduate school in the mathematical sciences is often free. Most Ph.D. programs in pure mathematics have financial support available in the form of tuition waivers plus a research stipend or a part-time teaching/grading job. This is also true for Ph.D. programs in statistics, applied mathematics, computer science, and operations research. Financial support for master's degrees varies wildly from field to field and sometimes from school to school; it's rarely available for pure mathematics, but is much more available for applied mathematics, statistics, financial mathematics, and biostatistics.
How should you go about applying to doctoral programs? Try this:
The Registry of Undergraduate Researchers
might match you with a graduate school.
Want advanced work in actuarial science? Check the SOA list of programs and sort by level of courses offered, descending.
Make your own rankings for Ph.D. programs (that is, rankings based on criteria you choose). This site also has the most recent ranking of programs by the National Research Council as of 2010.
US News also ranks graduate and professional programs; check to see if your library has online access or the print edition. Also look for The Gourman Report, most recently published in 1997 but still reasonably relevant. Harvey Mudd maintains a list of graduate mathematics programs ordered by the National Research Council's 1995 rankings.
Here are hyperlinked lists of U.S. doctoral programs in mathematics and applied mathematics/operations research and statistics/biostatistics and mathematics education, so you can check out individual departments.


|Publication number||US7451326 B2|
|Application number||US 10/228,151|
|Publication date||Nov 11, 2008|
|Filing date||Aug 26, 2002|
|Priority date||Aug 26, 2002|
|Also published as||CN1689267A, CN100592676C, CN101916178A, CN101916178B, DE60313637D1, DE60313637T2, EP1547302A1, EP1547302B1, US7962758, US8386802, US20040039922, US20090055659, US20110208976, WO2004019548A1|
|Publication number||10228151, 228151, US 7451326 B2, US 7451326B2, US-B2-7451326, US7451326 B2, US7451326B2|
|Original Assignee||Mosaid Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (32), Non-Patent Citations (2), Referenced by (5), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to parallel processors, and in particular to a parallel processor capable of processing arbitrary key bit length encryption operations with similar efficiencies using a same processor.
It is becoming relatively common to exchange electronically stored documents between parties to a transaction, for instance via a widely distributed information network such as the Internet of the World Wide Web (WWW). A common problem with the Internet is a lack of secure communication channels. Thus, in order for hospitals, governments, banks, stockbrokers, and credit card companies to make use of the Internet, privacy and security must be ensured. One approach to solving the aforementioned problem uses data encryption prior to transmission. In a prior art system, a host computer system is provided with an encryption unit, for example an encryption processor that is in electrical communication with at least a memory circuit for storing at least a private encryption key. When information is to be transmitted from the host computer system to a recipient via the Internet and is of a confidential nature, the information is first passed to the encryption processor for encryption using the stored private key. Typically, a same private key is used every time a data encryption operation is performed. Alternatively, an encryption key is selected from a finite set of private encryption keys that is stored in the at least a memory circuit in electrical communication with the encryption processor.
Of course, a data encryption operation that is performed by an encryption processor is a mathematical algorithm in which an input data value, for instance a hashed version of an electronic document, is the only variable value. It is, therefore, possible to optimize the encryption processor to perform a desired encryption function using a least amount of processor resources. Additionally, in the prior art encryption units the optimized encryption processor is typically separate from the microprocessor of the host computer system, because it is best optimized in this way.
Several standards exist today for privacy and strong authentication on the Internet through encryption/decryption. Typically, encryption/decryption is performed based on algorithms which are intended to allow data transfer over an open channel between parties while maintaining the privacy of the message contents. This is accomplished by encrypting the data using an encryption key by the sender and decrypting it using a decryption key by the receiver. In symmetric key cryptography, the encryption and decryption keys are the same.
Encryption algorithms are typically classified into public-key and secret-key algorithms. In secret-key algorithms, keys are secret whereas in public-key algorithms, one of the keys is made widely known to the general public. Block ciphers are representative of the secret-key cryptosystems in use today. Usually, for block ciphers, symmetric keys are used. A block cipher takes a block of data, typically 32-128 bits, as input data and produces the same number of bits as output data. The encryption and decryption operations are performed using the key, having a length typically in the range of 56-128 bits. The encryption algorithm is designed such that it is very difficult to decrypt a message without knowing the key.
In addition to block ciphers, Internet security protocols also rely on public-key based algorithms. A public key cryptosystem such as the Rivest, Shamir, Adelman (RSA) cryptosystem described in U.S. Pat. No. 5,144,667 issued to Pogue and Rivest uses two keys, one of which is secret—private—and the other of which is publicly available. Once someone publishes a public key, anyone may send that person a secret message encrypted using that public key; however, decryption of the message can only be accomplished by use of the private key. The advantage of such public-key encryption is private keys are not distributed to all parties of a conversation beforehand. In contrast, when symmetric encryption is used, multiple secret keys are generated, one for each party intended to receive a message, and each secret key is privately communicated. Attempting to distribute secret keys in a secure fashion results in a similar problem as that faced in sending the message using only secret-key encryption; this is typically referred to as the key distribution problem.
Key exchange is another application of public-key techniques. In a key exchange protocol, two parties can agree on a secret key even if a third party intercepts their conversation. The Diffie-Hellman exponential key exchange method, described in U.S. Pat. No. 4,200,770, is an example of such a protocol.
Most public-key algorithms, such as RSA and Diffie-Hellman key exchange, are based on modular exponentiation, which is the computation of αx mod p. This expression means “multiply α by itself x times, divide the answer by p, and take the remainder.” This is very computationally expensive to perform, for the following reason. In order to perform this operation, many repeated multiplication operations and division operations are required. Techniques such as Montgomery's method, described in “Modular Multiplication Without Trial Division,” from Mathematics of Computation, Vol. 44, No. 170 of April 1985, can reduce the number of division operations required but do not overcome this overall computational expense. In addition, for present data encryption systems the numbers used are very large (typically 1024 bits or more), so the multiply and divide instructions found in common CPUs cannot be used directly. Instead, special algorithms that break down the large multiplication operations and division operations into operations small enough to be performed on a CPU are used. These algorithms usually have a run time proportional to the square of the number of machine words involved. These factors result in multiplication of large numbers being a very slow operation. For example, a Pentium® processor can perform a 32×32-bit multiply in 10 clock cycles. A 2048-bit number can be represented in 64 32-bit words. A 2048×2048-bit multiply requires 64×64 separate 32×32-bit multiplication operations, which takes 40960 clocks on the Pentium® processor. An exponentiation with a 2048-bit exponent requires up to 4096 multiplication operations if done in the straightforward fashion, which requires about 167 million clock cycles. If the Pentium processor is running at 166 MHZ, the entire operation requires roughly one second. Of course, the division operations add further time to the overall computation times. Clearly, a common CPU such as a Pentium cannot expect to do key generation and exchange at any great rate.
Pipeline processors comprising a plurality of separate processing elements arranged in a serial array, and in particular a large number of processing elements, are known in the prior art and are particularly well suited for executing data encryption algorithms. Two types of pipeline processor are known: processors of an in-one-end-and-out-the-other nature, wherein there is a single processing direction; and, bi-directional processors of an in-and-out-the-same-end nature, wherein there is a forward processing direction and a return processing direction. Considering a specific example of a bi-directional pipeline processor, a first data block is read from a memory buffer into a first processing element of the serial array, which element performs a first stage of processing and then passes the first data block on to a second processing element. The second processing element performs a second stage of processing while, in parallel, the first processing element reads a second data block from the memory buffer and performs a same first processing stage on the second data block. In turn, each data block propagates in a step-by-step fashion from one processing element to a next processing element along the forward processing direction of the serial array. At each step, there is a processing stage that performs a same mathematical operation on each data block that is provided thereto. Simultaneously, a result that is calculated at each processing element is provided to a previous processing element of the serial array, with respect to the return processing direction, which results comprise in aggregate the processed data returned by the encryption processor. This assembly-line approach to data processing, using a large number of processing elements, is a very efficient way of performing the computationally expensive data encryption algorithms described previously. Of course, the application of pipeline processors for performing computationally expensive processing operations is other than limited strictly to data encryption algorithms, which have been discussed in detail only by way of example.
It is a disadvantage of the prior art encryption processors that the processors are limited to fixed key sizes or alternatively to fixed performance. Thus, either a processor only works with keys of, for example, 128 bits or the processor requires equal time to process a 128 bit encryption operation as to process a 40 bit encryption operation. Typically, these two design requirements allow for best performance of the processor.
It would be advantageous to provide a parallel processor capable of processing arbitrary key bit length encryption operations with similar efficiencies using a same processor.
It is an object of the invention to provide a pipeline processor capable of processing encryption operations using keys with different bit lengths with similar efficiencies.
In accordance with the invention there is provided a method for processing data comprising the steps of:
In accordance with the invention there is provided an apparatus for processing data comprising:
In accordance with the invention there is provided an apparatus for processing data comprising:
The invention will be readily understood by the following description of preferred embodiments, in conjunction with the following drawings, in which:
The present invention is concerned with an implementation of a parallel processor for use in encryption operations, the implementation being such that the parallel processor supports variable length encryption keys without substantially compromising efficiency.
In order to perform an encryption operation, an encryption key of a predetermined length is provided to the processor 1 and the encryption operation is performed. Alternatively, if the encryption key is less than the predetermined length, it is padded to bring it to the predetermined length and then the operation is performed. In either case, the operation takes an approximately same predetermined amount of time. Unfortunately, as key lengths grow larger, the efficiency of the prior art processor 1 for processing older, shorter keys is reduced. For example, a processor designed to accommodate 256 bit keys will process a forty-bit key that has been padded to 256 bits at approximately ⅙th of the “efficient” time for processing only the forty-bit key. This is a poor allocation of resources. In order to better allocate resources, some processors include a plurality of processor arrays each for processing a different length encryption key as shown in
Referring now to
Referring now to
It is illustrative to consider a specific example, such as for instance a forty bit encryption operation requiring at least five individual eight bit processor elements to complete. In use, data is provided for encryption by the client station (not shown) via port 3, for example as a stream of individual blocks of data which comprise in aggregate a complete data file. At the beginning of a first processing cycle the first processor element 8 1 in array 6 a receives a first data block from a memory buffer (not shown) of port 3 and performs a predetermined first stage of processing thereon. In the present example the first stage of processing corresponds to an encryption operation using an eight-bit segment of the encryption key. Of course, first processor element 8 1 is time-synchronized with the memory buffer (not shown) of port 3 and with the logic circuit 7 such that the stream of data blocks is gated to first processor element 8 1 in synchronization. At the beginning of a second processing cycle, first processor element 8 1 receives a second data block via port 3. At approximately a same time the first processing element 8 1 provides an output in the form of the first data block along a forward processing-path to second processor element 8 2. Additionally, the first processor element 8 1 provides a first result calculated therein along a return processing-path to the memory buffer of port 3. This assembly line approach to processing data continues until the final result is provided to the memory buffer of port 3 along the return processing-path.
Advantageously, the stream of data blocks is gated to first processor element 8 1 in synchronization, as was described previously. At the beginning of each processing cycle the logic circuit 7 decrements the data indicative of the encryption key length by a predetermined amount. In the present example the encryption key length is forty bits, requiring five processor elements to complete the encryption operation, such that the data indicative of the encryption key length is representative of the value five. Then, at the beginning of the first processing cycle the logic circuit 7 decrements by one the value five to indicate that four processing cycles remain. The value is further decremented at the beginning of the second to fifth processing cycles, at which time the logic circuit 7 returns a zero value. If a zero value results, indicating that the end of the encryption data has been reached, then the logic circuit 7 transmits a last bit signal via the last bit signal conductor 9 to every processor element. A processor element having just received the last bit signal along the forward processing path, in this case the fifth processor element, “knows” immediately that it is the last processor element and turns the data around, such that data is other than propagated past said processor element along the forward processing path. Each of the processor elements preceding the last processor element receives data along both the forward processing path and the return processing path at the time that the last bit signal is transmitted, which is indicative of other than last element status.
Of course, if the value of the logic circuit 7 reaches other than zero during a particular processing cycle, then processing continues normally. For example, during the second processing cycle, first processor element 8 1 performs a same first processing operation on the second data block and second processor element 8 2 performs a second processing operation on the first data block. At the end of the second processing cycle, the first data block is propagated along the forward processing path between the second and the third processor elements 8 2 and 8 3, respectively. Simultaneously, the second data block is propagated along the forward processing path between the first and the second processor elements 8 1 and 8 2, respectively. Additionally, the second processor element 8 2 provides a result calculated therein along the return processing-path to the first processor element 8 1. Of course, simultaneously gating data blocks along the forward processing-path and along the return processing-path between adjacent processor elements typically involves synchronous timing.
Using the bi-directional pipeline design shown, the result is efficiently calculated regardless of key length and additional processing cycles are avoided. The use of processors for supporting keys of different lengths within the device supports more than one efficient encryption process at a time—each process having a maximum key size. That said, in a common encryption processing system, statistics are easily used to select processor sizes to provide statistically a best performance for a given resource usage.
Alternatively, the last-bit signal conductor 9 is in electrical connection with only a subset of the processor elements 8. For example, in serial array 6 a the last-bit signal conductor 9 is optionally connected to every fourth processor element. So with eight bit processor elements, the processor 5 processes encryption data as a series of 32 bit segments. For a processor which supports up to 256 bit encryption processed by 32 bit segments, eight possible processing lengths are supported. Advantageously the number of datapaths for conducting the last bit signal from the logic circuit 7 to the processor elements is reduced from 32 to only eight separate datapaths, greatly facilitating the ease of fabrication of the processor 5. Unfortunately, processing resources are allocated with lower efficiency for encryption key lengths that are other than divisible by 32 bits, for instance the forty-bit encryption key which padded to at least 64 bits prior to processing. Thus, the data is turned around at the eighth processor element, instead of the fifth processor element as was discussed above.
Referring now to
Referring now to
Because data indicative of a key length is provided to the processor along with the data for processing and the encryption key, the processor can allocate sufficient processing units to the task and thereby efficiently allocate resources. Processor 16 is shown with a logic circuit 7 as was previously disclosed with reference to
Referring now to
Here the array 6 b is bidirectional and, because of the implementation of the pipeline process as a bidirectional pipeline process, it is possible to begin using the last element of the array 6 b once it has completed processing for an operation occurring in its other direction. As such, a significant improvement in efficiency results.
Because data indicative of a key length is provided to the processor along with the data for processing and the encryption key, the processor can allocate sufficient processing units to the task and thereby efficiently allocate resources. Processor 18 is shown with a logic circuit 7 as was previously disclosed with reference to
The pipeline processors 16 and 18 of
Advantageously, since it is known when a processor will complete processing, it becomes possible to allocate that processor to processing downstream of another processor. For example, assuming the processor 6 a has processing elements for processing 256 bit encryption operations and begins processing a 256 bit encryption operation. Assume 6 b is a similar processor. If, sometime after processing element 6 a commences processing and before it is completed a processing request for a 512 bit operation arrives, it is possible to begin the operation on processing array 6 b knowing that by the time data has propagated to the last element of processing array 6 a, that element will have completed processing of the processing job in current processing. This improves overall system performance by reducing downtime of a processor while awaiting other processors to be available to support concatenated array processing.
Montgomery Based Pipeline Processing of Encryption Data
Applying Montgomery's algorithm, the cost of a modular exponentiation is reduced to a series of additions of very long integers. To avoid carry propagation in multiplication/addition architectures several solutions are known. These use Montgomery's algorithm, in combination with a redundant radix number system or a Residue Number System.
In S. E. Eldridge and C. D. Walter. Hardware implementation of Montgomery's modular multiplication algorithm. IEEE Transactions on Computers, 42(6):693-699, July 1993, Montgomery's modular multiplication algorithm is adapted for an efficient hardware implementation. A gain in speed results from a higher clock frequency, due to simpler combinatorial logic. Compared to previous techniques based on Brickell's Algorithm, a speed-up factor of two was reported.
The Research Laboratory of Digital Equipment Corp. reported in J. E. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. H. Touati, and P. Boucard. Programmable active memories: Reconfigurable systems come of age. IEEE Transactions on VLSI Systems, 4(1): 56-69, March 1996 and M. Shand and J. Vuillemin. Fast implementations of RSA cryptography. In Proceedings 11th IEEE Symposium on Computer Arithmetic, pages 252-259, 1993, an array of 16 XILINX 3090 FPGAs using several speed-up methods including the Chinese remainder theorem, asynchronous carry completion adder, and a windowing exponentiation method is used to implement modular exponentiation. The implementation computes a 970 bit RSA decryption at a rate of 185 kb/s (5.2 ms per 970 bit decryption) and a 512 bit RSA decryption in excess of 300 kb/s (1.7 ms per 512 bit decryption). A drawback of this solution is that the binary representation of the modulus is hardwired into the logic representation so that the architecture must be reconfigured with every new modulus.
The problem of using high radices in Montgomery's modular multiplication algorithm is a more complex determination of a quotient. This behavior renders a pipelined execution of the algorithm other than straightforward. In H. Orup. Simplifying quotient determination in high-radix modular multiplication. In Proceedings 12th Symposium on Computer Arithmetic, pages 193-9, 1995, the algorithm is rewritten to avoid any operation involved in the quotient determination. The necessary pre-computation is performed only once for a given modulus.
P. A. Wang in the article New VLSI architectures of RSA public key crypto systems. In Proceedings of 1997 IEEE International Symposium on Circuits and Systems, volume 3, pages 2040-3, 1997 proposes a novel VLSI architecture for Montgomery's modular multiplication algorithm. The critical path that determines the clock speed is pipelined. This is done by interleaving each iteration of the algorithm. Compared to previous propositions, an improvement of the time-area product of a factor two was reported.
J. Bajard, L. Didier, and P. Kornerup in the article An RNS Montgomery modular multiplication algorithm. IEEE Transactions on Computers, 47(7): 766 -76, July 1998, describe a new approach using a Residue Number System (RNS). The algorithm is implemented with n moduli in the RNS on n reasonably simple processors. The resulting processing time is O(n).
Of course, most of the references cited above relate to hardware implementations of processors that have little or no flexibility.
There have also been a number of proposals for systolic array architectures for modular arithmetic. These vary in terms of complexity and flexibility.
In E. F. Brickell. A survey of hardware implementations of RSA. In Advances in Cryptology—CRYPTO '89, pages 368-70.Springer-Verlag, 1990, E. F. Brickell summarizes the chips available in 1990 for performing RSA encryption.
In N. Takagi. A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplication operations. In Proceedings 10th IEEE Symposium on Computer Arithmetic, pages 35-42, 1991, the author proposes a radix-4 hardware algorithm. A redundant number representation is used and the propagation of carries in additions is therefore avoided. A processing speed-up of about six times compared to previous work is reported.
More recently an approach has been presented that utilizes pre-computed complements of the modulus and is based on the iterative Horner's rule in J. Yong-Yin and W. P. Burleson. VLSI array algorithms and architectures for RSA modular multiplication. IEEE Transactions on VLSI Systems, 5(2): 211-17, June 1997. Compared to Montgomery's algorithms these approaches use the most significant bits of an intermediate result to decide which multiples of the modulus to subtract. The drawback of these solutions is that they either need a large amount of storage space or many clock cycles to complete a modular multiplication.
The most popular algorithm for modular exponentiation is the square & multiply algorithm. Public-key encryption systems are, typically, based on modular exponentiation or repeated point addition. Both operations are in their most basic forms done by the square and multiply algorithm.
Method 1.1 takes 2(n−1) operations in the worst case and 1.5(n−1) on average. To compute a squaring and a multiplication in parallel, the following version of the square & multiply method can be used:
Method 1.2 takes 2n operations in the worst case and 1.5n on average. A speed-up is achieved by applying the 1-ary method, such as that disclosed in D. E. Knuth, The Art of Computer Programming. Volume 2: Seminumerical Algorithms. Addison-Wesley, Reading, Mass., 2nd edition, 1981, which is a generalization of Method 1.1. The 1-ary method processes 1 exponent bits at a time. The drawback here is that (21−2) multiples of X must be pre-computed and stored. A reduction to 21−1 pre-computations is possible. The resulting complexity is roughly n/l multiplication operations and n squaring operations.
As shown above, modular exponentiation is reduced to a series of modular multiplication operations and squaring steps using the Montgomery method. The method for modular multiplication described below was proposed by P. L. Montgomery in P. L. Montgomery. Modular multiplication without trial division. Mathematics of Computation, 44(170): 519-21, April 1985. It is a method for multiplying two integers modulo M, while avoiding division by M. The idea is to transform the integers in m-residues and compute the multiplication with these m-residues. In the end, the representations are transformed back to a normal representation thereof. This approach is only beneficial when a series of multiplication operations in the transform domain are computed (e.g., modular exponentiation).
To compute the Montgomery multiplication, a radix R>M, with gcd(M, R)=1 is selected. Division by R is preferably inexpensive, thus an optimal choice is R=2m if
The m-residue of x is xR mod M. M′=M−1 mod R is also computed. A function MRED(T) is provided that computes TR−1 mod M: This function computes the normal representation of T, given that T is an m-residue.
Method 1.3 MRED(T): Computes a Montgomery Reduction of T
The result of MRED(T) is t=TR−1 mod M.
Now to multiply two integers a and b in the transform domain, where their respective representations are (aR mod M) and (bR mod M), a product of the two representations is provided to MRED(T):
MRED((aR mod M)·(bR mod M))=abR 2 R −1 =abR mod M
For a modular exponentiation this step is repeated numerous times according to Method 1.1 or 1.2 to get the final result ZR mod M or PnR mod M. One of these values is provided to MRED(T) to get the result Z mod M or Pn mod M.
The initial transform step still requires costly modular reductions. To avoid the division involved, compute R2 mod M using division. This step needs to be done only once for a given cryptosystem. To get a and b in the transform domain MRED(a·R2 mod M) and MRED(b·R2 modM) are executed to get aR mod M and bR mod M. Obviously, any variable can be transformed in this manner.
For a hardware implementation of Method 1.3: an m×m-bit multiplication and a 2m-bit addition is used to compute step 2. The intermediate result can have as many as 2m bits. Instead of computing U at once, one digit of an r-radix representation is computed at a time. Choosing a radix r, such that gcd(M, r)=1 is preferred. Division by r is also preferably inexpensive, thus an optimal choice is r=2k. All variables are now represented in a basis-r representation. Another improvement is to include the multiplication A×B in the algorithm.
Method 1.4 Montgomery Modular Multiplication for Computing A·B mod M, Where
The result of applying the method 1.4 is Sm=ABR−1 mod M. At most two k×k-bit multiplication operations and a k-bit addition is required to compute step 3 for a radix 2k. For step 4 two k×m-bit multiplication operations and two m+k-bit additions are needed. The maximal bit length of S is reduced to m+k+2 bits, compared to the 2m bits of Method 1.3.
Method 1.5 is a simplification of Method 1.4 for radix r=2. For the radix r=2, the operations in step 3 of Method 1.4 are done modulo 2. The modulus M is odd due to the condition gcd(M, 2k)=1. It follows immediately that M=1 mod 2. Hence M′=−M−1 mod 2 also degenerates to M′=1. Thus the multiplication by M′ mod 2 in step 3 is optionally omitted.
Method 1.5 Montgomery Modular Multiplication (Radix r=2) for Computing
Montgomery Modular Multiplication for computing A·B mod M, where
The final comparison and subtraction in step 6 of Method 1.5 would be costly to implement, as an m bit comparison is very slow and expensive in terms of resource usage. It would also make a pipelined execution of the algorithm impossible. It can easily be verified that Si+1<2M always holds if A, B<M. Sm, however, can not be reused as input A or B for the next modular multiplication. If two more executions of the for loop are performed with am+1=0 and inputs A, B<2M, the inequality Sm+2<2M is satisfied. Now, Sm+2 can be used as input B for the next modular multiplication.
To further reduce the complexity of Method 1.5, B is shifted up by one position, i.e., multiplied by two. This results in ai·B mod 2=0 and the addition in step 3 is avoided. In the update of Si+1 (Si+qiM+aiB)/2 is replaced by (Si+qiM)/2+aiB. The cost of this simplification is one more execution of the loop with am+ 2=0. The Method below comprises these optimizations.
Method 1.6 Montgomery Modular Multiplication (Radix r=2) for Computing A·B mod M, where
The algorithm above calculates Sm+3=(2−(m+2)AB) mod M. To get the correct result an extra Montgomery modular multiplication by 22(m+2) mod M is performed. However, if further multiplication operations are required as in exponentiation algorithms, it is better to pre-multiply all inputs by the factor 22(m+2) mod M. Thus every intermediate result carries a factor 2m+2. Montgomery multiplying the result by “1” eliminates this factor.
The final Montgomery multiplication with “1” insures that a final result is smaller than M.
High-Radix Montgomery Algorithm
By avoiding costly comparison and subtraction operations of step 6 and changing the conditions to 4M<2km and A, B<2M some optimization results for implementing method 1.4 in hardware. The penalty is two more executions of the loop. The resulting method is as follows:
Method 1.7 Montgomery Modular Multiplication for Computing A·B mod M, where
The quotient qi determination complexity is further be reduced by replacing B by B·2k. Since aiB mod 2k=0, step 3 is reduced to q1=Si mod 2k. The addition in step 3 is avoided at the cost of an additional iteration of the loop, to compensate for the extra factor 2k in B. A Montgomery method optimized for hardware implementation is shown below:
Method 1.8 Montgomery Modular Multiplication for Computing A·B mod M, Where
The final result is then Montgomery multiplied by 1 to eliminate the factors therein as discussed herein above.
In a thesis submitted to the Faculty of the Worcester Polytechnic Institute entitled Modular Exponentiation on Reconfigurable Hardware and submitted by Thomas Blum on Apr. 8, 1999 incorporated herein by reference, Thomas Blum proposed two different pipeline architectures for performing encryption functions using modular multiplication and Montgomery spaces: an area efficient architecture based on Method 1.6 and a speed efficient architecture. As target devices Xilinx XC4000 family devices were used.
A general radix 2 systolic array uses m times m processing elements, where m is the number of bits of the modulus and each element processes a single bit. 2m modular multiplication operations can be processed simultaneously, featuring a throughput of one modular multiplication per clock cycle and a latency of 2m cycles. As this approach results in unrealistically large CLB counts for typical bit lengths required in modern public-key schemes, only one row of processing elements was implemented. With this approach two modular multiplication operations can be processed simultaneously and the performance reduces to a throughput of two modular multiplication operations per 2m cycles. The latency remains 2m cycles.
The second consideration was the choice of the radix r=2k. Increasing k reduces the amount of steps to be executed in Method 1.8. Such an approach, however, requires more resources; The main expense lies in the computation of the 2k multiples of M and B. These are either pre-computed and stored in RAM or calculated by a multiplexer network. Clearly, the CLB count becomes smallest for r=2, as no multiples of M or B have to be calculated or pre-computed.
Using a radix r=2, the equation according to Method 1.6 is computed. To further reduce the required number of CLBs the following measures are optionally taken: each unit processes more than a single bit. A single adder is used to precompute B+M and to perform the other addition operation during normal processing. Squares and multiplication operations are computed in parallel. This design is divided hierarchically into three levels.
Processing Element Computes u bits of a modular multiplication.
Modular Multiplication An array of processing elements computes a modular multiplication.
Modular Exponentiation Combine modular multiplication operations to a modular exponentiation according to Algorithm 1.2.
In the processing elements the following registers are present:
The registers need a total of (6u+5)/2 CLBs, the adder u/2+2 CLBs, the multiplexers 4·u/2 CLBs, and the decoder 2 CLBs. The possibility of re-using registers for combinatorial logic allows some savings of CLBs. MuxB and MuxRes are implemented in the CLBs of B-Reg and Result-Reg, Mux1 and Mux2 partially in M-Reg and B+M-Reg. The resulting costs are approximately 3u+4 CLBs per u-bit processing unit. That is 3 to 4 CLBs per bit, depending on the unit size u.
Before a unit can compute a modular multiplication, the system parameters have to be loaded. M is stored into M-Reg of the unit. At the beginning of a modular multiplication, the operand B is loaded from either B-in or S-Reg, according to the select line of multiplexer B-Mux. The next step is to compute M+B once and store the result in the B+M-Reg. This operation needs two clock cycles, as the result is clocked into S-Reg first. The select lines of Mux1 and Mux2 are controlled by ai or the control word respectively.
In the following 2(m+2) cycles a modular multiplication is computed according to Method 1.6. Multiplexer Mux1 selects one of its inputs 0, M, B, B+M to be fed in the adder according to the value of the binary variables ai and qi. Mux2 feeds the u−1 most significant bits of the previous result S-Reg2 plus the least significant result bit of the next unit (division by two/shift right) into the second input of the adder. The result is stored in S-Reg for one cycle. The least significant bit goes into the unit to the right (division by two/shift right) and the carry to the unit to the left. In this cycle a second modular multiplication is calculated in the adder, with updated values of S-Reg2, ai and qi. The second multiplication uses the same operand B but a different operand A.
At the end of a modular multiplication, Sm+3 is valid for one cycle at the output of the adder. This value is both stored into Result-Reg, as fed via S-Reg into B-Reg. The result of the second multiplication is fed into Result-Reg one cycle later.
The inputs and outputs of the units are connected to each other in the following way. The control word, qi and ai are pumped from right to left through the units. The result is pumped from left to right. The carry-out signals are fed to the carry-in inputs to the right. Output S—0_Out is always connected to input S—0_In of the unit to the right. This represents the division by 2 of the equation.
At first the modulus M is fed into the units. To allow enough time for the signals to propagate to all the units, M is valid for two clock cycles. We use two M-Buses, the M-even-Bus connected to all even numbered units and the M-odd-Bus connected to all odd numbered units this approach allows to feed u bits to the units per clock cycle. Thus it takes m/u cycles to load the full modulus M.
The operand B is loaded similarly. The signals are also valid for two clock cycles. After the operand B is loaded, the performance of the steps of Method 1.6 begins.
Starting at the rightmost unit, unit0, the control word, ai, and qi are fed into their registers. The adder computes S-Reg-2 plus B, M, or B+M in one clock cycle according to ai and qi. The least significant bit of the result is read back as qi+1 for the next computation. The resulting carry bit, the control word, ai and qi are pumped into the unit to the left, where the same computation takes place in the next clock cycle.
In such a systolic fashion the control word, ai, qi, and the carry bits are pumped from right to left through the whole unit array. The division by two in Method 1.6 leads also to a shift-right operation. The least significant bit of a unit's addition (S0) is always fed back into the unit to the right. After a modular multiplication is completed, the results are pumped from left to right through the units and consecutively stored in RAM for further processing.
A single processing element computes u bits of Si+1=(Si+qi·M)/2+ai·B. In clock cycle i, unit0 computes bits 0 . . . u−1 of Si. In cycle i+1, unit1 uses the resulting carry and computes bits u . . . 2u−1 of Si. Unit0 uses the right shifted (division by 2) bit u of Si (S0) to compute bits 0 . . . u−1 of Si+1 in clock cycle i+2. Clock cycle i+1 is unproductive in unit0 while waiting for the result of unit1. This inefficiency is avoided by computing squares and multiplication operations in parallel according to Method 1.2. Both pi+1 and zi+1 depend on zi. So, the intermediate result zi is stored in the B-Registers and fed with pi into the ai input of the units for squaring and multiplication.
Before a modular exponentiation is computed, the system parameters are loaded. The modulus M is read 2u bits at the time from I/O into M-Reg. Reading starts from low order bits to high order bits. M is fed from M-Reg u bits at the time alternatively to M-even-Bus and M-odd-Bus. The signals are valid two cycles at a time. The exponent E is read 16 bits at the time from I/O and stored into Exp-RAM. The first 16 bit wide word from I/O specifies the length of the exponent in bits. Up to 64 following words contain the actual exponent. The pre-computation factor 22(m+2) mod M is read from I/O 2u bits at the time. It is stored into Prec-RAM.
In state Pre-compute1 we read the X value from I/O, u bits per clock cycle, and store it into DP RAM Z. At the same time the pre-computation factor 22(m+2) mod M is read from Prec RAM and fed u bits per clock cycle alternatively via the B-even-Bus and B-odd-Bus to the B-registers of the units. In the next two clock cycles, B+M is calculated in the units.
The initial values for Method 1.2 are available. Both values have to be multiplied by 2, which can be done in parallel as both multiplication operations use a common operand 22(m+2) mod M that is already stored in B. The time-division-multiplexing (TDM) unit reads X from DP RAM Z and multiplexes X and 1. After 2(m+3) clock cycles the low order bits of the result appear at Result-Out and are stored in DP RAM Z. The low order bits of the next result appear at Result-Out one cycle later and are stored in DP RAM P. This process repeats for 2m cycles, until all digits of the two results are saved in DP RAM Z and DP RAM P. The result X·2m+2 mod M is also stored in the B-registers of the units.
In state pre-compute2 the actual steps of Method 1.2 begin. For both calculations of Z1 and P1 Z0 is used as an operand. This value is stored in the B-registers. The second operand Z0 or P0 respectively, is read from DP RAM Z and DP RAM P and “pumped” via TDM as ai into the units. After another 2(m+3) clock cycles the low order bits of the result of Z1 and P1 appear at Result-Out. Z1 is stored in DP RAM Z. P1 is needed only if the first bit of the exponent e0 is equal to “1”. Depending on e0, P1 is either stored in DP RAM P or discarded.
In state compute the loop of method 1.2 is executed n−1 times. Zi in DP RAM Z is updated after every cycle and “pumped” back as ai into the units. Pi in DP RAM P is updated only if the relevant bit of the exponent ei is equal to “1”. In this way always the last stored P is “pumped” back into the units.
After the processing of en−1, the FSM enters state post-compute. To eliminate the factor 2m+2 from the result Pn, a final Montgomery multiplication by 1 is computed. First the vector 0, 0, . . . 0, 1 is fed alternatively via the B-even-Bus and B-odd-Bus into the B-registers of the units. Pn is “pumped” from DP RAM P as ai into the units. After state post-compute is executed, u bits of the result Pn=XE mod M are valid at the I/O port. Every two clock cycles another u bits appear at I/O. State pre-compute1 can be re-entered immediately now for the calculation of another X value.
A full modular exponentiation is computed in 2(n+2)(m+4) clock cycles. That is the delay it takes from inserting the first u bits of X into the device until the first u result bits appear at the output. At that point, another X value can enter the device. With a additional latency of m/u clock cycles the last u bits appear on the output bus.
Hereinbelow the function blocks in
DP RAM P works almost the same way. It has an additional input ei, that activates the write-enable signal of the DP RAM in the case of ei=1.
In state pre-compute1 the pre-computation factor is read from RAM and fed to the B-registers of the units. The counter is incremented each clock cycle and 2u bits are loaded in the 2u-bit register. From there u bits are fed on B-even-bus each positive edge of the clock. On the negative clock edge, u bits are fed on the B-odd-bus.
A Speed Efficient Architecture
The above design was optimized in terms of resource usage. Using a radix r=2k, k>1, reduces the number of steps in Method 1.6 by a factor k. The computation of Method 1.8 is executed m+3 times (i=0 to m+2)
A speed efficient design is readily divided hierarchically into three levels.
Processing Element Computes 4 bits of a modular multiplication.
Modular Multiplication An array of processing elements computes a modular multiplication.
Modular Exponentiation Combines modular multiplication operations to a modular exponentiation according to Method 12.
The following elements are provided:
The operation of the units is evident from the thesis of T. Blum, referenced above, and from a review of the diagrams.
This measure allows us to choose a 100% utilized m×4-bit DP RAM instead of an only 50% utilized 2m×4-bit DP RAM. DP RAM P works almost the same way. It has an additional input ei, that activates the write-enable signal of the DP RAM in the case of ei=“1.”
Since the above pipeline processor architectures embody many pipelined processing elements, it is often difficult and costly to synchronise each element to the clock source within a same integrated circuit. Therefore, the present invention is highly advantageous in reducing overall resource requirements by reducing clock distribution problems. Also, since in one direction addition is required while in the other direction multiplication is required, it is evident that more time is necessary along one path than the other and, so, time-averaging of the paths is possible in accordance with an embodiment of the invention.
Numerous other embodiments may be envisaged without departing from the spirit or scope of the invention.
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|US5848159||Jan 16, 1997||Dec 8, 1998||Tandem Computers, Incorporated||Public key cryptographic apparatus and method|
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|WO2002052777A2||Dec 21, 2001||Jul 4, 2002||Mosaid Technologies Incorporated||Packet encrypton system and method|
|1||"Modular Exponentiation on Reconfigurable Hardware," by Thomas Blum (Thesis) Worcester Polytechnic Institute pp. 1-107 (1999).|
|2||Schubert, A., et al., "Reusable Cryptographic VLSI Core Based on the Safer K-128 Algorithm with 251.8 Mbit/s Throughput," Signal Processing Systems, 1998, SIPS '98, 1998 IEEE Workshop on Cambridge, MA, USA Oct. 8-10, 1998, New York, New York, USA, IEEE, US, pp. 437-446, Germany XP010303746 ISBN: 0-7803-4997-0.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7912886 *||Dec 14, 2006||Mar 22, 2011||Intel Corporation||Configurable exponent FIFO|
|US8301905 *||Sep 8, 2006||Oct 30, 2012||Inside Secure||System and method for encrypting data|
|US20080062803 *||Sep 8, 2006||Mar 13, 2008||Daniele Fronte||System and method for encrypting data|
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|CN103780381A *||Dec 17, 2012||May 7, 2014||深圳市证通电子股份有限公司||Realization device and method for Montgomery algorithmic based on high level systolic array|
|International Classification||G06F12/14, G06F11/30, G06F7/72, H04L9/32, H04L9/00, H04K1/00|
|Aug 26, 2002||AS||Assignment|
Owner name: CHRYSALIS-ITS, INC., CANADA
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Free format text: CHANGE OF ADDRESS OF ASSIGNEE;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:022542/0876
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By Shakuntala Devi
Read Online or Download Figuring Made Easy PDF
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Extra resources for Figuring Made Easy
For example, to check that 8216 X 4215 = 34630440: 8 + 2 + 1 + 6 = ^ = 1 1 , casting out the nines, leaves 8 as the check number. 4 + 2 + 1 + 5 = 12, casting out the nines, leaves 3 as the check number. 3 + 4 + 6 + 3 + 0 + 4 + 4 + 0 = 24, casting out the nines, leaves 6 as the check number. 3 x 8 = 24, 2 + 4 = 6 which was the check number of the original product. Therefore, the multiplication is correct. However, I must mention here that this system of casting out the nines is not infallible, but if the answer you have obtained checks out as correct when you have used it, the chances of your being wrong are very slim.
60 x 100 = 18760 1 ^ 0 = 4690 4 4690 X 3 = 14070 To multiply by 9, just remember that 9 is one less than 10, so all that is necessary is to add a zero and then subtract the original multiplicand. Take 9 X 84 10 X 84 = 840 840 - 84 = 756 This can be extended, if asked to multiply by 18. All that is necessary is to multiply by 9 and double the product. For example, 448 X 18 448 x 10 = 4480 4480 - 448 = 4032 4032 X 2 = 8064 Alternatively, you can start from the fact that 18 is 20 less 2, in which case the sequence is: 448 x 2 = 896 896 x 10 = 8960 8960 - 896 = 8064 This method can be used for all numbers which are multi pies of 9.
For example: 165 divided b,- 5 = 'V;. Jc by 15. vidend by 2 and divide by l - ' .


Or search by topic
A composite number is one that is neither prime nor 1.
Show that 10201 is composite in any base.
Likewise show that 10101 is composite in any base.
Further Reading: Learn About Number Bases by Toni Beardon
Start with any number of counters in any number of piles. 2 players take it in turns to remove any number of counters from a single pile. The loser is the player who takes the last counter.
Find b where 3723(base 10) = 123(base b).
A collection of games on the NIM theme


This greater than less than activity for Halloween is the perfect addition to any math center! Graphing, data analysis, and comparing numbers - so many math skills in one fun activity!
Geoboards are an excellent way to practice spatial awareness, fine motor skills and geometry with 2D shapes too! These task cards are great visuals for students to replicate fun themed objects.
INCLUDED IN THE GREATER THAN LESS THAN ACTIVITIES:
Use Astro-brights to match any theme!
These task cards are designed to be used with 5x5 peg geoboards and rubber bands. (not included)
Students will count the number of rubber bands used for the task card.
Then, record the number on the task card and fill out the graph to match. (There are several options for graphing depending on the level of learner.)
Once all of the task cards and graph are completed, the student will use the data from the graph to answer the questions and compare numbers by using greater than, less than, and equal signs on the graph or response sheet. (2 levels of difficulty - 1 transfer the numbers from the graph and 1 without)
Extra time or early finishers: Students can draw and describe the creation they made on one sheet or Create your own creation!
These are perfect to use as a group, in a center, independent activity, morning work, or for early finishers!
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Our theme this half term is Ancient Greece. In science we have been learning about changing materials. In maths we have been learning about decimals, fractions and units of measure.
In order to show off our learning, we thought why not bake some Pitta bread! As doing so will combine all of our learning into one learning project. Here are some images of the children planning their baking experiments.
Keep posted for more updates!


...My undergraduate degree is in mathematics, and I have worked as a computer professional, as well as a math tutor. My doctoral degree is in psychology. I think this is a wonderful combination: I can relate to students, understand their frustrations and fears, and at the same time I deeply unders...
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...I also have been a certified classroom teacher in math in the Berkeley, Oakland, and San Ramon School Districts. I have been a USMaster's Club swimmer for over 20 years. I have been coached and gone to numerous swimming workshops in all strokes during that time.
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Math 132 Section 6.1 Areas Between Curves
Finding the Area Between Curves:
Ex 1: Find the area between the two curves in the graph below:
Ex 2: Find the area between = 2 6 and = 12 2 .
Ex 3: Find the area between = cos() and = 1 cos
Math 132 Section 7.4 Integration by Partial Fractions
To integrate rational functions, we can break the function into a sum of simpler fractions that we
Rational Function: ( ) = ()
To use the method of partial fractions, the rational f
Math 132 Section 7.1 Integration by Parts
Integration by Parts
When integrating two functions multiplied together, and there is no relationship
between the two functions, we use the method of integration by parts.
Integration by Parts:
Math 132 Section 5.3 The Fundamental Theorem of Calculus
The Fundamental Theorem of Calculus has two parts. Suppose f is a continuous
function on the closed interval [a,b].
If () = () then () = ()
() = () (), where F(x) = f(x)
Part II: () =
Math 132 Section 6.2 Volumes
Volume = ( ) or ()
Ex 1: Find the volume of the solid obtained by rotating the region
= from = 0 to = 1 about the x-axis.
Ex 2: Find the volume of the solid obtained by rotating the region
= 1 2
Math 132 Section 7.2 Trigonometric Integration
When integrating trigonometric functions involving sine and cosine, look for the following:
Factor out one power
cos 2 () = 1 sin2()
Sections 5.3-5.5, 6.1-6.2, 7.1-7.3
October 10 & 11 reviews 7-9pm
Midterm #1 Wednesday, October 12th, 7-9pm in Goessman Room 64
Old MT #1 posted on the course chairs blog (no solutions)
sin (x)=cos( x)
Section 7.4 - Integration of Rational
Functions By Partial Fractions
Note: for any k, you should be able
to write down the partial fraction
decomposition. For small k you
should be able to solve for
Long Division of
1. (ln x)2 dx
x sin3 x dx
x3 1 x2 dx
R ln y
sin5 x cos4 x dx
2x + 3x + 1
cot2 x dx
sin x + sec x
tan5 x dx
R sin x cot x
Trigonometric Identities and Integrals
Erica M. Farelli
Math 132 - University of Massachusetts
sec x =
csc x =
tan x =
sin2 x + cos2 x = 1
cot x =
1 + cot2 x = csc2 x
cos 2x = cos2 x sin
Mutiple Choice Section: Choose the one option that best
answers the question. There is "no partial credit for questions
1. [5 points] Which of the following integrals calculates the
area of the shaded region?
re) y (x3
r at ' - 1-.-
The velocity function (in meters per second) for a particle moving along a line is given by
(a) Find the displacement (in meters) of the particle.
Displacement = meters
(b) Find the total distance traveled (in meters) by the particle.
MATH132 Spring 2017 Worksheet: Fundamental Theorem of Calculus
1) Graph the two curves
y = 3/2x 1/2
y = 3/4x2 11/4.
Set up the definite integral to find the area enclosed by these two curves
2) Find the derivative of the following functions
1 + 7t2 si
Math 132 Section 11.3 Integral Tests
Suppose is a continuous, positive, and decreasing function on [1, ) and let = ().
Examples: Do the following series converge or diverge?
Ex 1: 1 + 8 + 27 + 64 + 125 +
Trigonometric Identities and Integrals for Chapter 7
csc x =
sec x =
tan x =
cot x =
sin2 x + cos2 x = 1
cot x =
tan2 x + 1 = sec2 x
sin x cos x = 21 sin 2x
sin2 x = 12 (1 cos 2x)
Lecture 17: Power series.
A power series about a, or just a power series is
cn (x a)n ,
a is called the center, cn s are called the coefficients of the power series. By convention:
(x a)0 = 1,
even when x = a.
Two new concepts:
1. Radius of converge
Lecture 10: Improper Integrals
Improper Integral of Type I: When interval is infinite.
f (x)dx = limt
2. f (x)dx = limt t f (x)dx.
3. f (x)dx = f (x)dx + c f (x)dx, for any number c, c can be chosen to be 0
Lecture 13: Integral test and Comparison test
THE INTEGRAL TEST: Suppose
P f is a continuous, positive, decreasing on [1, ) and
let an = f (n). Then the series n=1 an is convergent if and only if the improper integral is
R In ot
Lecture 11: Sequences
Definition and notation for sequences.
A sequence is a list of numbers written in certain order: a1 , a2 , a3 , , an , , where a1 is
called the first term, an is called the n-th term or general term of the sequence.
There are two way
Lecture 12: Series
Definition and notation for series.
Given a sequence cfw_an , the associated series is created by taking the summation of all
elements in the sequence.
Formally, the sequence is denoted by
n=1 an .
To give a precise definition, first
Lecture 18: Representing functions as power series.
At this point, we only know the following power series representation:
= 1 + x + x2 + x3 +
xn , for |x| < 1.
We now look at three techniques allow us to obtain a series representation using
Lecture 9: Integration by partial fractions
In this section we are going to take a look at integrals of rational functions
both P (x) and Q(x) are polynomials.
The process of taking a rational expression and deco
Lecture 8: Trigonometric Substitution
Make a substitution x = a sin(), then dx = a cos()d and
a2 x2 = a cos().
1. Evaluate the integral
Let x = 5 sin(), then
25 sin2 ()
Math 132 Section 11.1 Sequences
Sequence: a list of numbers written in a definite order.
1 , 2 , 3 , , ,
Examples: Write out the first five terms of the following sequences.
Ex 1: cfw_+1
Ex 2: cfw_
Math 132 Section 11.2 Series
Any decimal can be written as a series.
Write = 3.14159265 as a series.
Some series converge and others diverge.
1 = + + 2 + 3 +
Ex 1: Does th
Sequences and Series Convergence Tests
A sequence is increasing if an < an+1 for all n 1.
A seqeunce is decreasing if an+1 < an for all n 1.
A sequence is called monotonic if it is either increasing of decreasing.
A sequence is boun
Math 132 Section 11.4 The Comparison Tests
Suppose and are series with positive terms.
1.) If is convergent and for all , then is also convergent.
2.) If is divergent and for all , then is also divergent.
Ex 1: Does the series converge or


My kids LOVE
these puzzles. They are challenged to figure out a number pattern, then use it to solve the puzzle to find a word that's math vocabulary. Solve the puzzle correctly and the word is spelled correctly.
Print in black and white or color. Print two puzzles on a page OR project puzzles saved one to each page.
: A blank sheet with a new alien can be used by an interested student to create a new puzzle to share with classmates. Give students a certificate congratulating them when they successfully create puzzles.
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What is the maximum number of edges in a graph on n vertices without triangles? Mantel’s answer in 1907—that at most half of the edges can be present—started a new field: extremal combinatorics. More generally, what is the maximum number of edges in an n-vertex graph that does not contain any subgraph isomorphic to H? What about if you consider hypergraphs instead of graphs? I will introduce the technique of sums of squares and discuss how it can be used to attack such problems.


62-Bit-Wide Arithmetic and Logic Unit Combining the CARRY LOOK AHEAD and CARRY SELECT ADDER Principles
Original Publication Date: 1988-Jun-01
Included in the Prior Art Database: 2005-Feb-15
The speed of an arithmetic and logic unit (ALU) depends on the number of bits it has to handle. In a classic embodiment, the least significant bits are always available before the most significant bits. To get around this disadvantage, an improved ALU has to be designed so that the most significant bits are accelerated. Half-sum generates and propagates are formed for each pair of bits (left and right operands). Then the ALU is divided in three groups of sixteen bits, themselves being divided in four groups of 4 bits and a group of fourteen bits itself divided in two groups of four bits and a group of six bits. From the four- and six-bit groups are formed the first level generate and propagate groups (GG1 and GP1).


Laura Harich from Hewlett-Packard shows kids how math can be fun on the HP Prime Graphing Calculator from HP
(Pompano Beach, FL – PR LOG/CISION –September 3, 2013) Popular Home improvement show Designing Spaces™ airing on Lifetime TV will feature HP on the “Kids Spaces of Hope: All About Kids” episode. Tune in on Wednesday, September 4th at 7:30 am (ET/PT), as Lara Harich, Marketing Manager for the Calculator Division at HP, joins the show to demonstrate the new Prime Graphing Calculator. This show will re-air Thursday, October 10th.
During the segment Harich will meet with a group of students to practice some exercises on HP’s new touch-screen graphing calculator, and talk about how math, the cornerstone of many STEM-based careers, doesn’t have to be intimidating with the right tools.
The HP Prime Graphing calculator has an intuitive, app-based interface and color touch-screen, which makes it more familiar and appealing to today’s tech savvy students. For early high school mathematics courses like Geometry and Algebra II, HP has built-in apps that make it easy for students to visualize and explore course concepts, such as the Dynamic Geometry, Triangle Solver and Advanced Graphing apps.
“We’re thrilled that HP, a worldwide name in technology, has come on Designing Spaces to show us that with the HP prime graphing calculator, math can easier and more fun,” said Lysa Liemer, Executive VP and Chief Operating Officer of Designing Spaces™ on Lifetime TV.
To learn more about the HP Prime Graphing Calculator, please visit: www.hp.com/calculators.
About Designing Spaces™ on Lifetime® Television
Entering its 10th year, Designing Spaces continues to be one of America’s favorite home improvement shows. The show inspires viewers on decorating ideas, do-it-yourself projects and step-by-step home improvements to help make every space count and provide solutions to help you enjoy the space you live, work and play in. Designing Spaces family of spaces includes Think Green Spaces, Kids Spaces and its widely popular Spaces of Hope which prides itself on assisting people and places in dire need of a makeover including children’s shelters, animal shelters, military families and more. Designing Spaces airs Thursdays and Fridays at 7:30 a.m. (ET/PT) on the Lifetime® channel.
To view special segments visit: www.designingspaces.tv
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